text
stringlengths 992
1.04M
|
|---|
module conmutacion
(
input [3:0] centenas,
input [3:0] decenas,
input [3:0] unidades,
input C,
input De,
input U,
input CLKOUTseg,
output reg [1:0] mostrar,
output reg [3:0] digito
);
reg logic0;
reg [1:0] titileo;
initial
begin
titileo = 0;
end
always@(posedge CLKOUTseg)
begin
if(C && De && U)
begin
/*if(titileo == 3)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(De && U)
begin
/*if(titileo == 1)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(U)
begin
titileo <= 1;
end
else
begin
titileo <= 0;
end
end
end
end
always@(posedge CLKOUTseg)
begin
case(titileo)
2'b00:
begin
mostrar = 2'b01;
digito = 0;
end
2'b01:
begin
mostrar = 2'b01;
digito = unidades;
end
2'b10:
begin
mostrar = 2'b10;
digito = decenas;
end
2'b11:
begin
mostrar = 2'b11;
digito = centenas;
end
endcase
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level module of qspi_4cs
//
// ====================================================================
module sirv_qspi_4cs_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
sirv_qspi_4cs u_sirv_qspi_4cs(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_port_cs_1 (io_port_cs_1 ),
.io_port_cs_2 (io_port_cs_2 ),
.io_port_cs_3 (io_port_cs_3 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/01/19 09:26:57
// Design Name: INST_MEM
// Module Name: INST_MEM
// Project Name: MIPS_CPU
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module INST_MEM(
input[31:0] a,
output[31:0] inst_out );
wire[31:0] rom[0:31];
assign rom[5'h0] = 32'h3c010000;
assign rom[5'h1] = 32'h34240050;
assign rom[5'h2] = 32'h20050004;
assign rom[5'h3] = 32'h0c000018;
assign rom[5'h4] = 32'hac820000;
assign rom[5'h5] = 32'h8c890000;
assign rom[5'h6] = 32'h01244022;
assign rom[5'h7] = 32'h20050003;
assign rom[5'h8] = 32'h20a5ffff;
assign rom[5'h9] = 32'h34a8ffff;
assign rom[5'ha] = 32'h39085555;
assign rom[5'hb] = 32'h2009ffff;
assign rom[5'hc] = 32'h3124ffff;
assign rom[5'hd] = 32'h01493025;
assign rom[5'he] = 32'h01494026;
assign rom[5'hf] = 32'h01463824;
assign rom[5'h10] = 32'h10a00001;
assign rom[5'h11] = 32'h08000008;
assign rom[5'h12] = 32'h2005ffff;
assign rom[5'h13] = 32'h000543c0;
assign rom[5'h14] = 32'h00084400;
assign rom[5'h15] = 32'h00084403;
assign rom[5'h16] = 32'h000843c2;
assign rom[5'h17] = 32'h08000017;
assign rom[5'h18] = 32'h00004020;
assign rom[5'h19] = 32'h8c890000;
assign rom[5'h1a] = 32'h20840004;
assign rom[5'h1b] = 32'h01094020;
assign rom[5'h1c] = 32'h20a5ffff;
assign rom[5'h1d] = 32'h14a0fffb;
assign rom[5'h1e] = 32'h00081000;
assign rom[5'h1f] = 32'h03e00008;
assign inst_out = rom[a[6:2]];
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] Operand1 = crc[31:0];
wire [15:0] Operand2 = crc[47:32];
wire Unsigned = crc[48];
reg rst;
parameter wl = 16;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [wl-1:0] Quotient; // From test of Test.v
wire [wl-1:0] Remainder; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.Quotient (Quotient[wl-1:0]),
.Remainder (Remainder[wl-1:0]),
// Inputs
.Operand1 (Operand1[wl*2-1:0]),
.Operand2 (Operand2[wl-1:0]),
.clk (clk),
.rst (rst),
.Unsigned (Unsigned));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, Quotient, Remainder};
// What checksum will we end up with
`define EXPECTED_SUM 64'h98d41f89a8be5693
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration);
`endif
cyc <= cyc + 1;
if (cyc < 20 || test.Iteration==4'd15) begin
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
end
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
rst <= 1'b1;
end
else if (cyc<20) begin
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'h8dd70a44972ad809) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
parameter wl = 16;
input [wl*2-1:0] Operand1;
input [wl-1:0] Operand2;
input clk, rst, Unsigned;
output [wl-1:0] Quotient, Remainder;
reg Cy, Overflow, Sign1, Sign2, Zero, Negative;
reg [wl-1:0] ah,al,Quotient, Remainder;
reg [3:0] Iteration;
reg [wl-1:0] sub_quot,op;
reg ah_ext;
reg [1:0] a,b,c,d,e;
always @(posedge clk) begin
if (!rst) begin
{a,b,c,d,e} = Operand1[9:0];
{a,b,c,d,e} = {e,d,c,b,a};
if (a != Operand1[1:0]) $stop;
if (b != Operand1[3:2]) $stop;
if (c != Operand1[5:4]) $stop;
if (d != Operand1[7:6]) $stop;
if (e != Operand1[9:8]) $stop;
end
end
always @(posedge clk) begin
if (rst) begin
Iteration <= 0;
Quotient <= 0;
Remainder <= 0;
end
else begin
if (Iteration == 0) begin
{ah,al} = Operand1;
op = Operand2;
Cy = 0;
Overflow = 0;
Sign1 = (~Unsigned)&ah[wl-1];
Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]);
if (Sign1) {ah,al} = -{ah,al};
end
`define BUG1
`ifdef BUG1
{ah_ext,ah,al} = {ah,al,Cy};
`else
ah_ext = ah[15];
ah[15:1] = ah[14:0];
ah[0] = al[15];
al[15:1] = al[14:0];
al[0] = Cy;
`endif
`ifdef TEST_VERBOSE
$display("%x %x %x %x %x %x %x %x %x",
Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy);
`endif
{Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op};
if (Cy)
begin
{ah_ext,ah} = {1'b0,sub_quot};
end
if (Iteration != 15 )
begin
if (ah_ext) Overflow = 1;
end
else
begin
if (al[14] && ~Unsigned) Overflow = 1;
Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy};
Remainder <= Sign1 ? -ah : ah;
if (Overflow)
begin
Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}};
Remainder <= Unsigned ? 16'hffff : 16'h8000;
Zero = 1;
Negative = 1;
end
end
Iteration <= Iteration + 1; // Count number of times this instruction is repeated
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module user_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_DATA_WIDTH = 128
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2 : 0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1 : 0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr,
input [2 : 0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata,
output [1 : 0] s0_axi_rresp,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
input pcie_ref_clk_p,
input pcie_ref_clk_n,
input pcie_perst_n,
output dev_irq_assert,
//PCIe Integrated Block Interface
input user_clk_out,
input user_reset_out,
input user_lnk_up,
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output rx_np_ok,
output rx_np_req,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_command,
input [15:0] cfg_dcommand,
input [15:0] cfg_lcommand,
input [5:0] pl_ltssm_state,
input pl_received_hot_rst,
output sys_clk,
output sys_rst_n
);
parameter C_PCIE_ADDR_WIDTH = 36;
wire pcie_user_rst_n;
wire w_pcie_user_logic_rst;
wire w_pcie_link_up_sync;
wire [5:0] w_pl_ltssm_state_sync;
wire [15:0] w_cfg_command_sync;
wire [2:0] w_cfg_interrupt_mmenable_sync;
wire w_cfg_interrupt_msienable_sync;
wire w_cfg_interrupt_msixenable_sync;
wire w_pcie_mreq_err_sync;
wire w_pcie_cpld_err_sync;
wire w_pcie_cpld_len_err_sync;
wire w_nvme_cc_en_sync;
wire [1:0] w_nvme_cc_shn_sync;
wire [1:0] w_nvme_csts_shst;
wire w_nvme_csts_rdy;
wire [8:0] w_sq_valid;
wire [7:0] w_io_sq1_size;
wire [7:0] w_io_sq2_size;
wire [7:0] w_io_sq3_size;
wire [7:0] w_io_sq4_size;
wire [7:0] w_io_sq5_size;
wire [7:0] w_io_sq6_size;
wire [7:0] w_io_sq7_size;
wire [7:0] w_io_sq8_size;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq1_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq2_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq3_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq4_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq5_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq6_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq7_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq8_bs_addr;
wire [3:0] w_io_sq1_cq_vec;
wire [3:0] w_io_sq2_cq_vec;
wire [3:0] w_io_sq3_cq_vec;
wire [3:0] w_io_sq4_cq_vec;
wire [3:0] w_io_sq5_cq_vec;
wire [3:0] w_io_sq6_cq_vec;
wire [3:0] w_io_sq7_cq_vec;
wire [3:0] w_io_sq8_cq_vec;
wire [8:0] w_cq_valid;
wire [7:0] w_io_cq1_size;
wire [7:0] w_io_cq2_size;
wire [7:0] w_io_cq3_size;
wire [7:0] w_io_cq4_size;
wire [7:0] w_io_cq5_size;
wire [7:0] w_io_cq6_size;
wire [7:0] w_io_cq7_size;
wire [7:0] w_io_cq8_size;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq1_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq2_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq3_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq4_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq5_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq6_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq7_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq8_bs_addr;
wire [8:0] w_io_cq_irq_en;
wire [2:0] w_io_cq1_iv;
wire [2:0] w_io_cq2_iv;
wire [2:0] w_io_cq3_iv;
wire [2:0] w_io_cq4_iv;
wire [2:0] w_io_cq5_iv;
wire [2:0] w_io_cq6_iv;
wire [2:0] w_io_cq7_iv;
wire [2:0] w_io_cq8_iv;
wire w_nvme_cc_en;
wire [1:0] w_nvme_cc_shn;
wire w_pcie_mreq_err;
wire w_pcie_cpld_err;
wire w_pcie_cpld_len_err;
wire [1:0] w_nvme_csts_shst_sync;
wire w_nvme_csts_rdy_sync;
wire [8:0] w_sq_rst_n_sync;
wire [8:0] w_sq_valid_sync;
wire [7:0] w_io_sq1_size_sync;
wire [7:0] w_io_sq2_size_sync;
wire [7:0] w_io_sq3_size_sync;
wire [7:0] w_io_sq4_size_sync;
wire [7:0] w_io_sq5_size_sync;
wire [7:0] w_io_sq6_size_sync;
wire [7:0] w_io_sq7_size_sync;
wire [7:0] w_io_sq8_size_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq1_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq2_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq3_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq4_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq5_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq6_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq7_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq8_bs_addr_sync;
wire [3:0] w_io_sq1_cq_vec_sync;
wire [3:0] w_io_sq2_cq_vec_sync;
wire [3:0] w_io_sq3_cq_vec_sync;
wire [3:0] w_io_sq4_cq_vec_sync;
wire [3:0] w_io_sq5_cq_vec_sync;
wire [3:0] w_io_sq6_cq_vec_sync;
wire [3:0] w_io_sq7_cq_vec_sync;
wire [3:0] w_io_sq8_cq_vec_sync;
wire [8:0] w_cq_rst_n_sync;
wire [8:0] w_cq_valid_sync;
wire [7:0] w_io_cq1_size_sync;
wire [7:0] w_io_cq2_size_sync;
wire [7:0] w_io_cq3_size_sync;
wire [7:0] w_io_cq4_size_sync;
wire [7:0] w_io_cq5_size_sync;
wire [7:0] w_io_cq6_size_sync;
wire [7:0] w_io_cq7_size_sync;
wire [7:0] w_io_cq8_size_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq1_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq2_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq3_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq4_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq5_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq6_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq7_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq8_bs_addr_sync;
wire [8:0] w_io_cq_irq_en_sync;
wire [2:0] w_io_cq1_iv_sync;
wire [2:0] w_io_cq2_iv_sync;
wire [2:0] w_io_cq3_iv_sync;
wire [2:0] w_io_cq4_iv_sync;
wire [2:0] w_io_cq5_iv_sync;
wire [2:0] w_io_cq6_iv_sync;
wire [2:0] w_io_cq7_iv_sync;
wire [2:0] w_io_cq8_iv_sync;
wire [10:0] w_hcmd_table_rd_addr;
wire [31:0] w_hcmd_table_rd_data;
wire w_hcmd_sq_rd_en;
wire [18:0] w_hcmd_sq_rd_data;
wire w_hcmd_sq_empty_n;
wire w_hcmd_cq_wr1_en;
wire [34:0] w_hcmd_cq_wr1_data0;
wire [34:0] w_hcmd_cq_wr1_data1;
wire w_hcmd_cq_wr1_rdy_n;
wire w_dma_cmd_wr_en;
wire [49:0] w_dma_cmd_wr_data0;
wire [49:0] w_dma_cmd_wr_data1;
wire w_dma_cmd_wr_rdy_n;
wire [7:0] w_dma_rx_direct_done_cnt;
wire [7:0] w_dma_tx_direct_done_cnt;
wire [7:0] w_dma_rx_done_cnt;
wire [7:0] w_dma_tx_done_cnt;
wire w_pcie_rx_fifo_rd_en;
wire [C_M0_AXI_DATA_WIDTH-1:0] w_pcie_rx_fifo_rd_data;
wire w_pcie_rx_fifo_free_en;
wire [9:4] w_pcie_rx_fifo_free_len;
wire w_pcie_rx_fifo_empty_n;
wire w_pcie_tx_fifo_alloc_en;
wire [9:4] w_pcie_tx_fifo_alloc_len;
wire w_pcie_tx_fifo_wr_en;
wire [C_M0_AXI_DATA_WIDTH-1:0] w_pcie_tx_fifo_wr_data;
wire w_pcie_tx_fifo_full_n;
wire w_dma_rx_done_wr_en;
wire [20:0] w_dma_rx_done_wr_data;
wire w_dma_rx_done_wr_rdy_n;
wire w_dev_rx_cmd_wr_en;
wire [29:0] w_dev_rx_cmd_wr_data;
wire w_dev_rx_cmd_full_n;
wire w_dev_tx_cmd_wr_en;
wire [29:0] w_dev_tx_cmd_wr_data;
wire w_dev_tx_cmd_full_n;
sys_rst
sys_rst_inst0(
.cpu_bus_clk (s0_axi_aclk),
.cpu_bus_rst_n (s0_axi_aresetn),
.pcie_perst_n (pcie_perst_n),
.user_reset_out (user_reset_out),
.pcie_pl_hot_rst (pl_received_hot_rst),
.pcie_user_logic_rst (w_pcie_user_logic_rst),
.pcie_sys_rst_n (sys_rst_n),
.pcie_user_rst_n (pcie_user_rst_n)
);
s_axi_top # (
.C_S0_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S0_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S0_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S0_AXI_HIGHADDR (C_S0_AXI_HIGHADDR),
.C_M0_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M0_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M0_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M0_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M0_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M0_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M0_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M0_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
s_axi_top_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s0_axi_aclk (s0_axi_aclk),
.s0_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s0_axi_awaddr (s0_axi_awaddr),
.s0_axi_awready (s0_axi_awready),
.s0_axi_awvalid (s0_axi_awvalid),
.s0_axi_awprot (s0_axi_awprot),
//Write data channel
.s0_axi_wvalid (s0_axi_wvalid),
.s0_axi_wready (s0_axi_wready),
.s0_axi_wdata (s0_axi_wdata),
.s0_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s0_axi_bvalid (s0_axi_bvalid),
.s0_axi_bready (s0_axi_bready),
.s0_axi_bresp (s0_axi_bresp),
//Read address channel
.s0_axi_arvalid (s0_axi_arvalid),
.s0_axi_arready (s0_axi_arready),
.s0_axi_araddr (s0_axi_araddr),
.s0_axi_arprot (s0_axi_arprot),
//Read data channel
.s0_axi_rvalid (s0_axi_rvalid),
.s0_axi_rready (s0_axi_rready),
.s0_axi_rdata (s0_axi_rdata),
.s0_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (w_pcie_mreq_err_sync),
.pcie_cpld_err (w_pcie_cpld_err_sync),
.pcie_cpld_len_err (w_pcie_cpld_len_err_sync),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (w_pcie_user_logic_rst),
.nvme_cc_en (w_nvme_cc_en_sync),
.nvme_cc_shn (w_nvme_cc_shn_sync),
.nvme_csts_shst (w_nvme_csts_shst),
.nvme_csts_rdy (w_nvme_csts_rdy),
.sq_valid (w_sq_valid),
.io_sq1_size (w_io_sq1_size),
.io_sq2_size (w_io_sq2_size),
.io_sq3_size (w_io_sq3_size),
.io_sq4_size (w_io_sq4_size),
.io_sq5_size (w_io_sq5_size),
.io_sq6_size (w_io_sq6_size),
.io_sq7_size (w_io_sq7_size),
.io_sq8_size (w_io_sq8_size),
.io_sq1_bs_addr (w_io_sq1_bs_addr),
.io_sq2_bs_addr (w_io_sq2_bs_addr),
.io_sq3_bs_addr (w_io_sq3_bs_addr),
.io_sq4_bs_addr (w_io_sq4_bs_addr),
.io_sq5_bs_addr (w_io_sq5_bs_addr),
.io_sq6_bs_addr (w_io_sq6_bs_addr),
.io_sq7_bs_addr (w_io_sq7_bs_addr),
.io_sq8_bs_addr (w_io_sq8_bs_addr),
.io_sq1_cq_vec (w_io_sq1_cq_vec),
.io_sq2_cq_vec (w_io_sq2_cq_vec),
.io_sq3_cq_vec (w_io_sq3_cq_vec),
.io_sq4_cq_vec (w_io_sq4_cq_vec),
.io_sq5_cq_vec (w_io_sq5_cq_vec),
.io_sq6_cq_vec (w_io_sq6_cq_vec),
.io_sq7_cq_vec (w_io_sq7_cq_vec),
.io_sq8_cq_vec (w_io_sq8_cq_vec),
.cq_valid (w_cq_valid),
.io_cq1_size (w_io_cq1_size),
.io_cq2_size (w_io_cq2_size),
.io_cq3_size (w_io_cq3_size),
.io_cq4_size (w_io_cq4_size),
.io_cq5_size (w_io_cq5_size),
.io_cq6_size (w_io_cq6_size),
.io_cq7_size (w_io_cq7_size),
.io_cq8_size (w_io_cq8_size),
.io_cq1_bs_addr (w_io_cq1_bs_addr),
.io_cq2_bs_addr (w_io_cq2_bs_addr),
.io_cq3_bs_addr (w_io_cq3_bs_addr),
.io_cq4_bs_addr (w_io_cq4_bs_addr),
.io_cq5_bs_addr (w_io_cq5_bs_addr),
.io_cq6_bs_addr (w_io_cq6_bs_addr),
.io_cq7_bs_addr (w_io_cq7_bs_addr),
.io_cq8_bs_addr (w_io_cq8_bs_addr),
.io_cq_irq_en (w_io_cq_irq_en),
.io_cq1_iv (w_io_cq1_iv),
.io_cq2_iv (w_io_cq2_iv),
.io_cq3_iv (w_io_cq3_iv),
.io_cq4_iv (w_io_cq4_iv),
.io_cq5_iv (w_io_cq5_iv),
.io_cq6_iv (w_io_cq6_iv),
.io_cq7_iv (w_io_cq7_iv),
.io_cq8_iv (w_io_cq8_iv),
.hcmd_sq_rd_en (w_hcmd_sq_rd_en),
.hcmd_sq_rd_data (w_hcmd_sq_rd_data),
.hcmd_sq_empty_n (w_hcmd_sq_empty_n),
.hcmd_table_rd_addr (w_hcmd_table_rd_addr),
.hcmd_table_rd_data (w_hcmd_table_rd_data),
.hcmd_cq_wr1_en (w_hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (w_hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (w_hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (w_hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (w_dma_cmd_wr_en),
.dma_cmd_wr_data0 (w_dma_cmd_wr_data0),
.dma_cmd_wr_data1 (w_dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (w_dma_cmd_wr_rdy_n),
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m0_axi_aclk (m0_axi_aclk),
.m0_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m0_axi_awid (m0_axi_awid),
.m0_axi_awaddr (m0_axi_awaddr),
.m0_axi_awlen (m0_axi_awlen),
.m0_axi_awsize (m0_axi_awsize),
.m0_axi_awburst (m0_axi_awburst),
.m0_axi_awlock (m0_axi_awlock),
.m0_axi_awcache (m0_axi_awcache),
.m0_axi_awprot (m0_axi_awprot),
.m0_axi_awregion (m0_axi_awregion),
.m0_axi_awqos (m0_axi_awqos),
.m0_axi_awuser (m0_axi_awuser),
.m0_axi_awvalid (m0_axi_awvalid),
.m0_axi_awready (m0_axi_awready),
// Write data channel
.m0_axi_wid (m0_axi_wid),
.m0_axi_wdata (m0_axi_wdata),
.m0_axi_wstrb (m0_axi_wstrb),
.m0_axi_wlast (m0_axi_wlast),
.m0_axi_wuser (m0_axi_wuser),
.m0_axi_wvalid (m0_axi_wvalid),
.m0_axi_wready (m0_axi_wready),
// Write response channel
.m0_axi_bid (m0_axi_bid),
.m0_axi_bresp (m0_axi_bresp),
.m0_axi_bvalid (m0_axi_bvalid),
.m0_axi_buser (m0_axi_buser),
.m0_axi_bready (m0_axi_bready),
// Read address channel
.m0_axi_arid (m0_axi_arid),
.m0_axi_araddr (m0_axi_araddr),
.m0_axi_arlen (m0_axi_arlen),
.m0_axi_arsize (m0_axi_arsize),
.m0_axi_arburst (m0_axi_arburst),
.m0_axi_arlock (m0_axi_arlock),
.m0_axi_arcache (m0_axi_arcache),
.m0_axi_arprot (m0_axi_arprot),
.m0_axi_arregion (m0_axi_arregion),
.m0_axi_arqos (m0_axi_arqos),
.m0_axi_aruser (m0_axi_aruser),
.m0_axi_arvalid (m0_axi_arvalid),
.m0_axi_arready (m0_axi_arready),
// Read data channel
.m0_axi_rid (m0_axi_rid),
.m0_axi_rdata (m0_axi_rdata),
.m0_axi_rresp (m0_axi_rresp),
.m0_axi_rlast (m0_axi_rlast),
.m0_axi_ruser (m0_axi_ruser),
.m0_axi_rvalid (m0_axi_rvalid),
.m0_axi_rready (m0_axi_rready),
.pcie_rx_fifo_rd_en (w_pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (w_pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (w_pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (w_pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (w_pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (w_pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (w_pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (w_pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (w_pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (w_pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (w_dma_rx_done_wr_en),
.dma_rx_done_wr_data (w_dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (w_dma_rx_done_wr_rdy_n),
.pcie_user_clk (user_clk_out),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (w_dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (w_dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (w_dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (w_dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (w_dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (w_dev_tx_cmd_full_n),
.dma_rx_direct_done_cnt (w_dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (w_dma_tx_direct_done_cnt),
.dma_rx_done_cnt (w_dma_rx_done_cnt),
.dma_tx_done_cnt (w_dma_tx_done_cnt),
.pcie_link_up (w_pcie_link_up_sync),
.pl_ltssm_state (w_pl_ltssm_state_sync),
.cfg_command (w_cfg_command_sync),
.cfg_interrupt_mmenable (w_cfg_interrupt_mmenable_sync),
.cfg_interrupt_msienable (w_cfg_interrupt_msienable_sync),
.cfg_interrupt_msixenable (w_cfg_interrupt_msixenable_sync)
);
reg_cpu_pcie_sync
reg_cpu_pcie_sync_isnt0
(
.cpu_bus_clk (s0_axi_aclk),
.nvme_csts_shst (w_nvme_csts_shst),
.nvme_csts_rdy (w_nvme_csts_rdy),
.sq_valid (w_sq_valid),
.io_sq1_size (w_io_sq1_size),
.io_sq2_size (w_io_sq2_size),
.io_sq3_size (w_io_sq3_size),
.io_sq4_size (w_io_sq4_size),
.io_sq5_size (w_io_sq5_size),
.io_sq6_size (w_io_sq6_size),
.io_sq7_size (w_io_sq7_size),
.io_sq8_size (w_io_sq8_size),
.io_sq1_bs_addr (w_io_sq1_bs_addr),
.io_sq2_bs_addr (w_io_sq2_bs_addr),
.io_sq3_bs_addr (w_io_sq3_bs_addr),
.io_sq4_bs_addr (w_io_sq4_bs_addr),
.io_sq5_bs_addr (w_io_sq5_bs_addr),
.io_sq6_bs_addr (w_io_sq6_bs_addr),
.io_sq7_bs_addr (w_io_sq7_bs_addr),
.io_sq8_bs_addr (w_io_sq8_bs_addr),
.io_sq1_cq_vec (w_io_sq1_cq_vec),
.io_sq2_cq_vec (w_io_sq2_cq_vec),
.io_sq3_cq_vec (w_io_sq3_cq_vec),
.io_sq4_cq_vec (w_io_sq4_cq_vec),
.io_sq5_cq_vec (w_io_sq5_cq_vec),
.io_sq6_cq_vec (w_io_sq6_cq_vec),
.io_sq7_cq_vec (w_io_sq7_cq_vec),
.io_sq8_cq_vec (w_io_sq8_cq_vec),
.cq_valid (w_cq_valid),
.io_cq1_size (w_io_cq1_size),
.io_cq2_size (w_io_cq2_size),
.io_cq3_size (w_io_cq3_size),
.io_cq4_size (w_io_cq4_size),
.io_cq5_size (w_io_cq5_size),
.io_cq6_size (w_io_cq6_size),
.io_cq7_size (w_io_cq7_size),
.io_cq8_size (w_io_cq8_size),
.io_cq1_bs_addr (w_io_cq1_bs_addr),
.io_cq2_bs_addr (w_io_cq2_bs_addr),
.io_cq3_bs_addr (w_io_cq3_bs_addr),
.io_cq4_bs_addr (w_io_cq4_bs_addr),
.io_cq5_bs_addr (w_io_cq5_bs_addr),
.io_cq6_bs_addr (w_io_cq6_bs_addr),
.io_cq7_bs_addr (w_io_cq7_bs_addr),
.io_cq8_bs_addr (w_io_cq8_bs_addr),
.io_cq_irq_en (w_io_cq_irq_en),
.io_cq1_iv (w_io_cq1_iv),
.io_cq2_iv (w_io_cq2_iv),
.io_cq3_iv (w_io_cq3_iv),
.io_cq4_iv (w_io_cq4_iv),
.io_cq5_iv (w_io_cq5_iv),
.io_cq6_iv (w_io_cq6_iv),
.io_cq7_iv (w_io_cq7_iv),
.io_cq8_iv (w_io_cq8_iv),
.pcie_link_up_sync (w_pcie_link_up_sync),
.pl_ltssm_state_sync (w_pl_ltssm_state_sync),
.cfg_command_sync (w_cfg_command_sync),
.cfg_interrupt_mmenable_sync (w_cfg_interrupt_mmenable_sync),
.cfg_interrupt_msienable_sync (w_cfg_interrupt_msienable_sync),
.cfg_interrupt_msixenable_sync (w_cfg_interrupt_msixenable_sync),
.pcie_mreq_err_sync (w_pcie_mreq_err_sync),
.pcie_cpld_err_sync (w_pcie_cpld_err_sync),
.pcie_cpld_len_err_sync (w_pcie_cpld_len_err_sync),
.nvme_cc_en_sync (w_nvme_cc_en_sync),
.nvme_cc_shn_sync (w_nvme_cc_shn_sync),
.pcie_user_clk (user_clk_out),
.pcie_link_up (user_lnk_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.pcie_mreq_err (w_pcie_mreq_err),
.pcie_cpld_err (w_pcie_cpld_err),
.pcie_cpld_len_err (w_pcie_cpld_len_err),
.nvme_cc_en (w_nvme_cc_en),
.nvme_cc_shn (w_nvme_cc_shn),
.nvme_csts_shst_sync (w_nvme_csts_shst_sync),
.nvme_csts_rdy_sync (w_nvme_csts_rdy_sync),
.sq_rst_n_sync (w_sq_rst_n_sync),
.sq_valid_sync (w_sq_valid_sync),
.io_sq1_size_sync (w_io_sq1_size_sync),
.io_sq2_size_sync (w_io_sq2_size_sync),
.io_sq3_size_sync (w_io_sq3_size_sync),
.io_sq4_size_sync (w_io_sq4_size_sync),
.io_sq5_size_sync (w_io_sq5_size_sync),
.io_sq6_size_sync (w_io_sq6_size_sync),
.io_sq7_size_sync (w_io_sq7_size_sync),
.io_sq8_size_sync (w_io_sq8_size_sync),
.io_sq1_bs_addr_sync (w_io_sq1_bs_addr_sync),
.io_sq2_bs_addr_sync (w_io_sq2_bs_addr_sync),
.io_sq3_bs_addr_sync (w_io_sq3_bs_addr_sync),
.io_sq4_bs_addr_sync (w_io_sq4_bs_addr_sync),
.io_sq5_bs_addr_sync (w_io_sq5_bs_addr_sync),
.io_sq6_bs_addr_sync (w_io_sq6_bs_addr_sync),
.io_sq7_bs_addr_sync (w_io_sq7_bs_addr_sync),
.io_sq8_bs_addr_sync (w_io_sq8_bs_addr_sync),
.io_sq1_cq_vec_sync (w_io_sq1_cq_vec_sync),
.io_sq2_cq_vec_sync (w_io_sq2_cq_vec_sync),
.io_sq3_cq_vec_sync (w_io_sq3_cq_vec_sync),
.io_sq4_cq_vec_sync (w_io_sq4_cq_vec_sync),
.io_sq5_cq_vec_sync (w_io_sq5_cq_vec_sync),
.io_sq6_cq_vec_sync (w_io_sq6_cq_vec_sync),
.io_sq7_cq_vec_sync (w_io_sq7_cq_vec_sync),
.io_sq8_cq_vec_sync (w_io_sq8_cq_vec_sync),
.cq_rst_n_sync (w_cq_rst_n_sync),
.cq_valid_sync (w_cq_valid_sync),
.io_cq1_size_sync (w_io_cq1_size_sync),
.io_cq2_size_sync (w_io_cq2_size_sync),
.io_cq3_size_sync (w_io_cq3_size_sync),
.io_cq4_size_sync (w_io_cq4_size_sync),
.io_cq5_size_sync (w_io_cq5_size_sync),
.io_cq6_size_sync (w_io_cq6_size_sync),
.io_cq7_size_sync (w_io_cq7_size_sync),
.io_cq8_size_sync (w_io_cq8_size_sync),
.io_cq1_bs_addr_sync (w_io_cq1_bs_addr_sync),
.io_cq2_bs_addr_sync (w_io_cq2_bs_addr_sync),
.io_cq3_bs_addr_sync (w_io_cq3_bs_addr_sync),
.io_cq4_bs_addr_sync (w_io_cq4_bs_addr_sync),
.io_cq5_bs_addr_sync (w_io_cq5_bs_addr_sync),
.io_cq6_bs_addr_sync (w_io_cq6_bs_addr_sync),
.io_cq7_bs_addr_sync (w_io_cq7_bs_addr_sync),
.io_cq8_bs_addr_sync (w_io_cq8_bs_addr_sync),
.io_cq_irq_en_sync (w_io_cq_irq_en_sync),
.io_cq1_iv_sync (w_io_cq1_iv_sync),
.io_cq2_iv_sync (w_io_cq2_iv_sync),
.io_cq3_iv_sync (w_io_cq3_iv_sync),
.io_cq4_iv_sync (w_io_cq4_iv_sync),
.io_cq5_iv_sync (w_io_cq5_iv_sync),
.io_cq6_iv_sync (w_io_cq6_iv_sync),
.io_cq7_iv_sync (w_io_cq7_iv_sync),
.io_cq8_iv_sync (w_io_cq8_iv_sync)
);
nvme_pcie # (
.C_PCIE_DATA_WIDTH (128)
)
nvme_pcie_inst0(
.pcie_ref_clk_p (pcie_ref_clk_p),
.pcie_ref_clk_n (pcie_ref_clk_n),
//PCIe user clock
.pcie_user_clk (user_clk_out),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (w_dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (w_dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (w_dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (w_dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (w_dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (w_dev_tx_cmd_full_n),
.cpu_bus_clk (s0_axi_aclk),
.cpu_bus_rst_n (s0_axi_aresetn),
.nvme_cc_en (w_nvme_cc_en),
.nvme_cc_shn (w_nvme_cc_shn),
.nvme_csts_shst (w_nvme_csts_shst_sync),
.nvme_csts_rdy (w_nvme_csts_rdy_sync),
.sq_rst_n (w_sq_rst_n_sync),
.sq_valid (w_sq_valid_sync),
.io_sq1_size (w_io_sq1_size_sync),
.io_sq2_size (w_io_sq2_size_sync),
.io_sq3_size (w_io_sq3_size_sync),
.io_sq4_size (w_io_sq4_size_sync),
.io_sq5_size (w_io_sq5_size_sync),
.io_sq6_size (w_io_sq6_size_sync),
.io_sq7_size (w_io_sq7_size_sync),
.io_sq8_size (w_io_sq8_size_sync),
.io_sq1_bs_addr (w_io_sq1_bs_addr_sync),
.io_sq2_bs_addr (w_io_sq2_bs_addr_sync),
.io_sq3_bs_addr (w_io_sq3_bs_addr_sync),
.io_sq4_bs_addr (w_io_sq4_bs_addr_sync),
.io_sq5_bs_addr (w_io_sq5_bs_addr_sync),
.io_sq6_bs_addr (w_io_sq6_bs_addr_sync),
.io_sq7_bs_addr (w_io_sq7_bs_addr_sync),
.io_sq8_bs_addr (w_io_sq8_bs_addr_sync),
.io_sq1_cq_vec (w_io_sq1_cq_vec_sync),
.io_sq2_cq_vec (w_io_sq2_cq_vec_sync),
.io_sq3_cq_vec (w_io_sq3_cq_vec_sync),
.io_sq4_cq_vec (w_io_sq4_cq_vec_sync),
.io_sq5_cq_vec (w_io_sq5_cq_vec_sync),
.io_sq6_cq_vec (w_io_sq6_cq_vec_sync),
.io_sq7_cq_vec (w_io_sq7_cq_vec_sync),
.io_sq8_cq_vec (w_io_sq8_cq_vec_sync),
.cq_rst_n (w_cq_rst_n_sync),
.cq_valid (w_cq_valid_sync),
.io_cq1_size (w_io_cq1_size_sync),
.io_cq2_size (w_io_cq2_size_sync),
.io_cq3_size (w_io_cq3_size_sync),
.io_cq4_size (w_io_cq4_size_sync),
.io_cq5_size (w_io_cq5_size_sync),
.io_cq6_size (w_io_cq6_size_sync),
.io_cq7_size (w_io_cq7_size_sync),
.io_cq8_size (w_io_cq8_size_sync),
.io_cq1_bs_addr (w_io_cq1_bs_addr_sync),
.io_cq2_bs_addr (w_io_cq2_bs_addr_sync),
.io_cq3_bs_addr (w_io_cq3_bs_addr_sync),
.io_cq4_bs_addr (w_io_cq4_bs_addr_sync),
.io_cq5_bs_addr (w_io_cq5_bs_addr_sync),
.io_cq6_bs_addr (w_io_cq6_bs_addr_sync),
.io_cq7_bs_addr (w_io_cq7_bs_addr_sync),
.io_cq8_bs_addr (w_io_cq8_bs_addr_sync),
.io_cq_irq_en (w_io_cq_irq_en_sync),
.io_cq1_iv (w_io_cq1_iv_sync),
.io_cq2_iv (w_io_cq2_iv_sync),
.io_cq3_iv (w_io_cq3_iv_sync),
.io_cq4_iv (w_io_cq4_iv_sync),
.io_cq5_iv (w_io_cq5_iv_sync),
.io_cq6_iv (w_io_cq6_iv_sync),
.io_cq7_iv (w_io_cq7_iv_sync),
.io_cq8_iv (w_io_cq8_iv_sync),
.hcmd_sq_rd_en (w_hcmd_sq_rd_en),
.hcmd_sq_rd_data (w_hcmd_sq_rd_data),
.hcmd_sq_empty_n (w_hcmd_sq_empty_n),
.hcmd_table_rd_addr (w_hcmd_table_rd_addr),
.hcmd_table_rd_data (w_hcmd_table_rd_data),
.hcmd_cq_wr1_en (w_hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (w_hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (w_hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (w_hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (w_dma_cmd_wr_en),
.dma_cmd_wr_data0 (w_dma_cmd_wr_data0),
.dma_cmd_wr_data1 (w_dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (w_dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (w_dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (w_dma_tx_direct_done_cnt),
.dma_rx_done_cnt (w_dma_rx_done_cnt),
.dma_tx_done_cnt (w_dma_tx_done_cnt),
.dma_bus_clk (m0_axi_aclk),
.dma_bus_rst_n (m0_axi_aresetn),
.pcie_rx_fifo_rd_en (w_pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (w_pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (w_pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (w_pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (w_pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (w_pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (w_pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (w_pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (w_pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (w_pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (w_dma_rx_done_wr_en),
.dma_rx_done_wr_data (w_dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (w_dma_rx_done_wr_rdy_n),
.pcie_mreq_err (w_pcie_mreq_err),
.pcie_cpld_err (w_pcie_cpld_err),
.pcie_cpld_len_err (w_pcie_cpld_len_err),
.tx_buf_av (tx_buf_av),
.tx_err_drop (tx_err_drop),
.tx_cfg_req (tx_cfg_req),
.s_axis_tx_tready (s_axis_tx_tready),
.s_axis_tx_tdata (s_axis_tx_tdata),
.s_axis_tx_tkeep (s_axis_tx_tkeep),
.s_axis_tx_tuser (s_axis_tx_tuser),
.s_axis_tx_tlast (s_axis_tx_tlast),
.s_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cfg_gnt (tx_cfg_gnt),
.m_axis_rx_tdata (m_axis_rx_tdata),
.m_axis_rx_tkeep (m_axis_rx_tkeep),
.m_axis_rx_tlast (m_axis_rx_tlast),
.m_axis_rx_tvalid (m_axis_rx_tvalid),
.m_axis_rx_tready (m_axis_rx_tready),
.m_axis_rx_tuser (m_axis_rx_tuser),
.rx_np_ok (rx_np_ok),
.rx_np_req (rx_np_req),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.cfg_bus_number (cfg_bus_number),
.cfg_device_number (cfg_device_number),
.cfg_function_number (cfg_function_number),
.cfg_to_turnoff (cfg_to_turnoff),
.cfg_turnoff_ok (cfg_turnoff_ok),
.cfg_command (cfg_command),
.cfg_dcommand (cfg_dcommand),
.cfg_lcommand (cfg_lcommand),
.sys_clk (sys_clk)
);
endmodule |
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk
);
input fastclk;
t_netlist tnetlist
(.also_fastclk (fastclk),
/*AUTOINST*/
// Inputs
.fastclk (fastclk));
endmodule
module t_netlist (/*AUTOARG*/
// Inputs
fastclk, also_fastclk
);
// surefire lint_off ASWEMB
input fastclk;
input also_fastclk;
integer _mode; initial _mode = 0;
// This entire module should optimize to nearly nothing...
// verilator lint_off UNOPTFLAT
reg [4:0] a,a2,b,c,d,e;
// verilator lint_on UNOPTFLAT
initial a=5'd1;
always @ (posedge fastclk) begin
b <= a+5'd1;
c <= b+5'd1; // Better for ordering if this moves before previous statement
end
// verilator lint_off UNOPT
always @ (d or /*AS*/a or c) begin
e = d+5'd1;
a2 = a+5'd1; // This can be pulled out of the middle of the always
d = c+5'd1; // Better for ordering if this moves before previous statement
end
// verilator lint_on UNOPT
always @ (posedge also_fastclk) begin
if (_mode==5) begin
if (a2 != 5'd2) $stop;
if (e != 5'd5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_V
`define SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_V |
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Examines TLB entries to authorize access. Purely combo logic. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_tlb_check ( // ZAP TLB Processing Logic.
i_mmu_en, // MMU enable.
// Dynamics
i_va, // Virtual address.
i_rd, // WB rd.
i_wr, // WB wr.
// Static almost.
i_cpsr,
i_sr,
i_dac_reg,
// Data from TLB dist RAMs.
i_sptlb_rdata, i_sptlb_rdav,
i_lptlb_rdata, i_lptlb_rdav,
i_setlb_rdata, i_setlb_rdav,
i_fptlb_rdata, i_fptlb_rdav,
// Outputs to other units.
o_walk, // Need to page walk.
o_fsr, // FSR.
o_far, // FAR. 0 means no fault. This is a 4-bit number.
o_cacheable, // Cacheable based on PTE.
o_phy_addr // Physical address.
);
// Pass this from top.
parameter LPAGE_TLB_ENTRIES = 8;
parameter SPAGE_TLB_ENTRIES = 8;
parameter SECTION_TLB_ENTRIES = 8;
parameter FPAGE_TLB_ENTRIES = 8;
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
input wire i_mmu_en; // MMU enable.
input wire [31:0] i_va; // Virtual address.
input wire i_rd; // Read request.
input wire i_wr; // Write request.
input wire [31:0] i_cpsr; // CPSR.
input wire [1:0] i_sr; // Status Register.
input wire [31:0] i_dac_reg; // Domain Access Control Register.
input wire [`SPAGE_TLB_WDT -1:0] i_sptlb_rdata; // Small page TLB.
input wire i_sptlb_rdav; // TLB entry valid.
input wire [`LPAGE_TLB_WDT -1:0] i_lptlb_rdata; // Large page TLB read data.
input wire i_lptlb_rdav; // Large page TLB valid.
input wire [`SECTION_TLB_WDT-1:0] i_setlb_rdata; // Small page TLB read data.
input wire i_setlb_rdav; // Small page TLB valid.
input wire [`FPAGE_TLB_WDT-1:0] i_fptlb_rdata; // Fine page TLB read data.
input wire i_fptlb_rdav; // Fine page TLB valid.
output reg o_walk; // Signal page walk.
output reg [7:0] o_fsr; // FSR. 0 means all OK.
output reg [31:0] o_far; // Fault Address Register.
output reg o_cacheable; // Cacheble stats of the PTE.
output reg [31:0] o_phy_addr; // Physical address.
// ----------------------------------------------------------------------------
always @*
begin
// Default values. Taken for MMU disabled esp.
o_fsr = 0; // No fault.
o_far = i_va; // Fault address.
o_phy_addr = i_va; // VA = PA
o_walk = 0; // Walk disabled.
o_cacheable = 0; // Uncacheable.
if ( i_mmu_en && (i_rd|i_wr) ) // MMU enabled.
begin
if ( (i_sptlb_rdata[`SPAGE_TLB__TAG] == i_va[`VA__SPAGE_TAG]) && i_sptlb_rdav )
begin
// Entry found in small page TLB.
o_fsr = get_fsr
(
1'd0, 1'd1, 1'd0, 1'd0, // Small page.
i_va[`VA__SPAGE_AP_SEL],
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_sptlb_rdata
) ;
o_phy_addr = {i_sptlb_rdata[`SPAGE_TLB__BASE],
i_va[11:0]};
o_cacheable = i_sptlb_rdata[`SECTION_TLB__CB] >> 1;
end
else if ( (i_lptlb_rdata[`LPAGE_TLB__TAG] == i_va[`VA__LPAGE_TAG]) && i_lptlb_rdav )
begin
// Entry found in large page TLB.
o_fsr = get_fsr
(
1'd0, 1'd0, 1'd1, 1'd0, // Large page.
i_va[`VA__LPAGE_AP_SEL],
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_lptlb_rdata
) ;
o_phy_addr = {i_lptlb_rdata[`LPAGE_TLB__BASE],
i_va[15:0]};
o_cacheable = i_lptlb_rdata[`LPAGE_TLB__CB] >> 1;
end
else if ( (i_setlb_rdata[`SECTION_TLB__TAG] == i_va[`VA__SECTION_TAG]) && i_setlb_rdav )
begin
// Entry found in section TLB.
o_fsr = get_fsr
(
1'd1, 1'd0, 1'd0, 1'd0, // Section.
2'd0, // DONT CARE. Sections do not further divisions in AP SEL.
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_setlb_rdata
) ;
o_phy_addr = {i_setlb_rdata[`SECTION_TLB__BASE],
i_va[19:0]};
o_cacheable = i_setlb_rdata[`SECTION_TLB__CB] >> 1;
end
else if( (i_fptlb_rdata[`FPAGE_TLB__TAG] == i_va[`VA__FPAGE_TAG]) && i_fptlb_rdav )
begin
// Entry found in fine page TLB.
o_fsr = get_fsr
(
1'd0, 1'd0, 1'd0, 1'd1,
2'd0,
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_fptlb_rdata
);
end
else
begin
// Trigger TLB walk.
o_walk = 1'd1;
end
end // Else MMU disabled.
end
// ----------------------------------------------------------------------------
function [7:0] get_fsr ( // Return 0 means OK to access else is a valid FSR.
input section, spage, lpage, fpage, // Select one.
input [1:0] ap_sel, // AP sel bits. dont care for sections or fine pages.
input user, rd, wr, // Access properties.
input [1:0] sr, // S and R bits.
input [31:0] dac_reg, // DAC register.
input [63:0] tlb // TLB entry.
);
reg [3:0] apsr; // Concat of AP and SR.
reg [1:0] dac; // DAC bits.
begin
// Get AP and DAC.
if ( section ) // section.
begin
apsr = (tlb [ `SECTION_TLB__AP ]);
dac = (dac_reg >> (tlb [ `SECTION_TLB__DAC_SEL ] << 1));
end
else if ( spage ) // small page.
begin
apsr = (tlb [ `SPAGE_TLB__AP ]) >> (ap_sel << 1);
dac = (dac_reg >> (tlb [ `SPAGE_TLB__DAC_SEL ] << 1));
end
else if ( fpage ) // fine page
begin
apsr = (tlb [ `FPAGE_TLB__AP ]);
dac = (dac_reg >> (tlb [ `FPAGE_TLB__DAC_SEL ] << 1));
end
else // large page.
begin
apsr = (tlb [ `LPAGE_TLB__AP ]) >> (ap_sel << 1);
dac = (dac_reg >> (tlb [ `LPAGE_TLB__DAC_SEL ] << 1));
end
// Concat AP and SR bits.
apsr[3:2] = apsr[1:0];
apsr[1:0] = sr[1:0];
case(dac)
DAC_MANAGER: get_fsr = 0; // No fault.
DAC_CLIENT : get_fsr = is_apsr_ok ( user, rd, wr, apsr ) ? 0 :
(
section ? {tlb[`SECTION_TLB__DAC_SEL], FSR_SECTION_PERMISSION_FAULT}:
spage ? {tlb[`SPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }:
fpage ? {tlb[`FPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }:
{tlb[`LPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }
);
default : get_fsr =
section ? {tlb[`SECTION_TLB__DAC_SEL], FSR_SECTION_DOMAIN_FAULT} :
spage ? {tlb[`SPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } :
fpage ? {tlb[`FPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } :
{tlb[`LPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } ;
endcase
end
endfunction
// ----------------------------------------------------------------------------
//
// Function to check APSR bits.
//
// Returns 0 for failure, 1 for okay.
// Checks AP and SR bits.
//
localparam APSR_BAD = 1'd0;
localparam APSR_OK = 1'd1;
function is_apsr_ok ( input user, input rd, input wr, input [3:0] apsr);
reg x;
begin
x = APSR_BAD; // Assume fail.
casez (apsr)
APSR_NA_NA: x = APSR_BAD; // No access.
APSR_RO_RO: x = !wr; // Reads allowed for all.
APSR_RO_NA: x = !user && rd; // Only kernel reads.
APSR_RW_NA: x = !user; // Only kernel access.
APSR_RW_RO: x = !user | (user && rd); // User RO, Kernel RW.
APSR_RW_RW: x = APSR_OK; // Grant all the time.
default : x = APSR_BAD; // Deny all the time.
endcase
// Assign to function. Return.
is_apsr_ok = x;
end
endfunction
endmodule // zap_tlb_check.v
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_cq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input [7:0] hcmd_prp_rd_addr,
output [44:0] hcmd_prp_rd_data,
input hcmd_nlb_wr1_en,
input [6:0] hcmd_nlb_wr1_addr,
input [18:0] hcmd_nlb_wr1_data,
output hcmd_nlb_wr1_rdy_n,
input [6:0] hcmd_nlb_rd_addr,
output [18:0] hcmd_nlb_rd_data,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_table_wr_en;
wire [8:0] w_hcmd_table_wr_addr;
wire [127:0] w_hcmd_table_wr_data;
wire w_hcmd_cid_wr_en;
wire [6:0] w_hcmd_cid_wr_addr;
wire [19:0] w_hcmd_cid_wr_data;
wire [6:0] w_hcmd_cid_rd_addr;
wire [19:0] w_hcmd_cid_rd_data;
wire w_hcmd_prp_wr_en;
wire [7:0] w_hcmd_prp_wr_addr;
wire [44:0] w_hcmd_prp_wr_data;
wire w_hcmd_nlb_wr0_en;
wire [6:0] w_hcmd_nlb_wr0_addr;
wire [18:0] w_hcmd_nlb_wr0_data;
wire w_hcmd_nlb_wr0_rdy_n;
wire w_hcmd_slot_rdy;
wire [6:0] w_hcmd_slot_tag;
wire w_hcmd_slot_alloc_en;
wire w_hcmd_slot_free_en;
wire [6:0] w_hcmd_slot_invalid_tag;
wire [7:0] w_admin_sq_head_ptr;
wire [7:0] w_io_sq1_head_ptr;
wire [7:0] w_io_sq2_head_ptr;
wire [7:0] w_io_sq3_head_ptr;
wire [7:0] w_io_sq4_head_ptr;
wire [7:0] w_io_sq5_head_ptr;
wire [7:0] w_io_sq6_head_ptr;
wire [7:0] w_io_sq7_head_ptr;
wire [7:0] w_io_sq8_head_ptr;
pcie_hcmd_table
pcie_hcmd_table_inst0(
.wr_clk (pcie_user_clk),
.wr_en (w_hcmd_table_wr_en),
.wr_addr (w_hcmd_table_wr_addr),
.wr_data (w_hcmd_table_wr_data),
.rd_clk (cpu_bus_clk),
.rd_addr (hcmd_table_rd_addr),
.rd_data (hcmd_table_rd_data)
);
pcie_hcmd_table_cid
pcie_hcmd_table_cid_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_cid_wr_en),
.wr_addr (w_hcmd_cid_wr_addr),
.wr_data (w_hcmd_cid_wr_data),
.rd_addr (w_hcmd_cid_rd_addr),
.rd_data (w_hcmd_cid_rd_data)
);
pcie_hcmd_table_prp
pcie_hcmd_table_prp_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_prp_wr_en),
.wr_addr (w_hcmd_prp_wr_addr),
.wr_data (w_hcmd_prp_wr_data),
.rd_addr (hcmd_prp_rd_addr),
.rd_data (hcmd_prp_rd_data)
);
pcie_hcmd_nlb
pcie_hcmd_nlb_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (w_hcmd_nlb_wr0_en),
.wr0_addr (w_hcmd_nlb_wr0_addr),
.wr0_data (w_hcmd_nlb_wr0_data),
.wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.wr1_en (hcmd_nlb_wr1_en),
.wr1_addr (hcmd_nlb_wr1_addr),
.wr1_data (hcmd_nlb_wr1_data),
.wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.rd_addr (hcmd_nlb_rd_addr),
.rd_data (hcmd_nlb_rd_data)
);
pcie_hcmd_slot_mgt
pcie_hcmd_slot_mgt_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag)
);
pcie_hcmd_sq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.cpld_sq_fifo_tag (cpld_sq_fifo_tag),
.cpld_sq_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_sq_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_sq_fifo_tag_last (cpld_sq_fifo_tag_last),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack),
.hcmd_table_wr_en (w_hcmd_table_wr_en),
.hcmd_table_wr_addr (w_hcmd_table_wr_addr),
.hcmd_table_wr_data (w_hcmd_table_wr_data),
.hcmd_cid_wr_en (w_hcmd_cid_wr_en),
.hcmd_cid_wr_addr (w_hcmd_cid_wr_addr),
.hcmd_cid_wr_data (w_hcmd_cid_wr_data),
.hcmd_prp_wr_en (w_hcmd_prp_wr_en),
.hcmd_prp_wr_addr (w_hcmd_prp_wr_addr),
.hcmd_prp_wr_data (w_hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (w_hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (w_hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (w_hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n)
);
pcie_hcmd_cq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cid_rd_addr (w_hcmd_cid_rd_addr),
.hcmd_cid_rd_data (w_hcmd_cid_rd_data),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_cq_size (admin_cq_size),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
endmodule |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_wrap_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_wrap_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
wire [11:0] axaddr_i;
wire [3:0] axlen_i;
reg [11:0] wrap_boundary_axaddr;
reg [3:0] axaddr_offset;
reg [3:0] wrap_second_len;
reg [11:0] wrap_boundary_axaddr_r;
reg [3:0] axaddr_offset_r;
reg [3:0] wrap_second_len_r;
reg [4:0] axlen_cnt;
reg [4:0] wrap_cnt_r;
wire [4:0] wrap_cnt;
reg [11:0] axaddr_wrap;
reg next_pending_r;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0];
end
endgenerate
assign axaddr_i = axaddr[11:0];
assign axlen_i = axlen[3:0];
// Mask bits based on transaction length to get wrap boundary low address
// Offset used to calculate the length of each transaction
always @( * ) begin
if(axhandshake) begin
wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]);
axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i;
end else begin
wrap_boundary_axaddr = wrap_boundary_axaddr_r;
axaddr_offset = axaddr_offset_r;
end
end
// case (axsize[1:0])
// 2'b00 : axaddr_offset = axaddr_i[4:0] & axlen_i;
// 2'b01 : axaddr_offset = axaddr_i[5:1] & axlen_i;
// 2'b10 : axaddr_offset = axaddr_i[6:2] & axlen_i;
// 2'b11 : axaddr_offset = axaddr_i[7:3] & axlen_i;
// default : axaddr_offset = axaddr_i[7:3] & axlen_i;
// endcase
// The first and the second command from the wrap transaction could
// be of odd length or even length with address offset. This will be
// an issue with BL8, extra transactions have to be issued.
// Rounding up the length to account for extra transactions.
always @( * ) begin
if(axhandshake) begin
wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0;
end else begin
wrap_second_len = wrap_second_len_r;
end
end
// registering to be used in the combo logic.
always @(posedge clk) begin
wrap_boundary_axaddr_r <= wrap_boundary_axaddr;
axaddr_offset_r <= axaddr_offset;
wrap_second_len_r <= wrap_second_len;
end
// determining if extra data is required for even offsets
// wrap_cnt used to switch the address for first and second transaction.
assign wrap_cnt = {1'b0, wrap_second_len + {3'b000, (|axaddr_offset)}};
always @(posedge clk)
wrap_cnt_r <= wrap_cnt;
always @(posedge clk) begin
if (axhandshake) begin
axaddr_wrap <= axaddr[11:0];
end if(next)begin
if(axlen_cnt == wrap_cnt_r) begin
axaddr_wrap <= wrap_boundary_axaddr_r;
end else begin
axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]);
end
end
end
// Even numbber of transactions with offset, inc len by 2 for BL8
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen_i;
next_pending_r <= axlen_i >= 1;
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= (axlen_cnt - 1) >= 1;
end else begin
axlen_cnt <= 5'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = axlen_i >= 1;
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = (axlen_cnt - 1) >= 1;
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/27/2015 03:47:45 PM
// Design Name:
// Module Name: wildcard_processer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wildcard_processor
#(parameter NUM_OUTPUT_QUEUES = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter RESULT_WIDTH = `OPENFLOW_ACTION_WIDTH,
parameter CURRENT_TABLE_ID = 0,
parameter TABLE_NUM=2
)
(
input [RESULT_WIDTH-1:0] result_fifo_dout,
output reg result_fifo_rd_en,
input result_fifo_empty,
input [CTRL_WIDTH-1:0] in_fifo_ctrl,
input [DATA_WIDTH-1:0] in_fifo_data,
output reg in_fifo_rd_en,
input in_fifo_empty,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
input wildcard_hit_dout,
output reg actions_en,
output reg actions_hit,
output reg [`OPENFLOW_ACTION_WIDTH-1:0] actions,
input clk,
input reset,
output reg [3:0] src_port,
input skip_lookup
);
reg [DATA_WIDTH-1:0] out_data_d1;
reg [CTRL_WIDTH-1:0] out_ctrl_d1;
reg [DATA_WIDTH-1:0] out_data_d2;
reg [CTRL_WIDTH-1:0] out_ctrl_d2;
reg out_wr_d1;
reg out_wr_d2;
reg out_wr_d3;
// assign out_data_d1=in_fifo_data;
// assign out_ctrl_d1=in_fifo_ctrl;
always@(posedge clk)
actions_hit<=wildcard_hit_dout;
always@(posedge clk)
begin
out_data_d1<=in_fifo_data;
out_ctrl_d1<=in_fifo_ctrl;
out_data_d2<=out_data_d1;
out_ctrl_d2<=out_ctrl_d1;
out_data<=out_data_d2;
out_ctrl<=out_ctrl_d2;
out_wr_d1<=in_fifo_rd_en;
out_wr_d2<=out_wr_d1;
out_wr_d3<=out_wr_d2;
out_wr<=out_wr_d3;
end
reg [`OPENFLOW_NEXT_TABLE_ID_WIDTH-1:0] pkt_dst_table_id;
reg [5:0]cur_st,nxt_st;
always@(posedge clk)
if(reset)
cur_st<=0;
else
cur_st<=nxt_st;
localparam IDLE=0,
WAIT_FOR_ACTION=1,
READ_ACTION=2,
READ_HEAD=3,
READ_DATA=4,
WAIT_EOP=5;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
IDLE:
nxt_st=WAIT_FOR_ACTION;
WAIT_FOR_ACTION:
if(!result_fifo_empty) nxt_st=READ_ACTION;
READ_ACTION:
nxt_st=READ_HEAD;
READ_HEAD:
if(out_rdy) nxt_st=READ_DATA;
READ_DATA:
if(in_fifo_ctrl==0 && out_rdy) nxt_st=WAIT_EOP;
WAIT_EOP:
if(in_fifo_ctrl!=0 && out_rdy) nxt_st=IDLE;
default:nxt_st=IDLE;
endcase
end
always@(*)
begin
result_fifo_rd_en=0;
in_fifo_rd_en=0;
if(cur_st==READ_ACTION)
result_fifo_rd_en=out_rdy;
else if(cur_st==READ_HEAD)
in_fifo_rd_en=out_rdy;
else if(cur_st==READ_DATA)
in_fifo_rd_en=out_rdy;
else if(cur_st==WAIT_EOP)
begin
if(in_fifo_ctrl!=0)
in_fifo_rd_en=0;
else in_fifo_rd_en=out_rdy;
end
end
always@(posedge clk)
if(reset)
src_port<=0;
else// if(cur_st==READ_HEAD)
if(in_fifo_ctrl==`IO_QUEUE_STAGE_NUM)
src_port<=in_fifo_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `IOQ_SRC_PORT_POS] ;
always@(posedge clk)
if(reset)
actions<=0;
else if(cur_st==READ_DATA)
actions<= result_fifo_dout;
always@(posedge clk)
if(reset)
actions_en<=0;
else if(in_fifo_ctrl==`IO_QUEUE_STAGE_NUM)
begin
if(in_fifo_data[`IOQ_DST_TABLE_ID_POS+8-1:`IOQ_DST_TABLE_ID_POS]==CURRENT_TABLE_ID)
actions_en<=1;
else actions_en<=0;
end
else if(cur_st==IDLE)
actions_en<=0;
endmodule
|
// mi_nios_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.05.20.08:55:19
`timescale 1 ps / 1 ps
module mi_nios_mm_interconnect_0 (
input wire clk_50_clk_clk, // clk_50_clk.clk
input wire pll_c0_clk, // pll_c0.clk
input wire cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
input wire flash_reset_reset_bridge_in_reset_reset, // flash_reset_reset_bridge_in_reset.reset
input wire jtag_reset_reset_bridge_in_reset_reset, // jtag_reset_reset_bridge_in_reset.reset
input wire [24:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [24:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [8:0] cpu_jtag_debug_module_address, // cpu_jtag_debug_module.address
output wire cpu_jtag_debug_module_write, // .write
output wire cpu_jtag_debug_module_read, // .read
input wire [31:0] cpu_jtag_debug_module_readdata, // .readdata
output wire [31:0] cpu_jtag_debug_module_writedata, // .writedata
output wire [3:0] cpu_jtag_debug_module_byteenable, // .byteenable
input wire cpu_jtag_debug_module_waitrequest, // .waitrequest
output wire cpu_jtag_debug_module_debugaccess, // .debugaccess
output wire [8:0] flash_epcs_control_port_address, // flash_epcs_control_port.address
output wire flash_epcs_control_port_write, // .write
output wire flash_epcs_control_port_read, // .read
input wire [31:0] flash_epcs_control_port_readdata, // .readdata
output wire [31:0] flash_epcs_control_port_writedata, // .writedata
output wire flash_epcs_control_port_chipselect, // .chipselect
output wire [0:0] jtag_avalon_jtag_slave_address, // jtag_avalon_jtag_slave.address
output wire jtag_avalon_jtag_slave_write, // .write
output wire jtag_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_avalon_jtag_slave_writedata, // .writedata
input wire jtag_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] LED_s1_address, // LED_s1.address
output wire LED_s1_write, // .write
input wire [31:0] LED_s1_readdata, // .readdata
output wire [31:0] LED_s1_writedata, // .writedata
output wire LED_s1_chipselect, // .chipselect
output wire [21:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [15:0] sdram_s1_readdata, // .readdata
output wire [15:0] sdram_s1_writedata, // .writedata
output wire [1:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect, // .chipselect
output wire [1:0] SW_s1_address, // SW_s1.address
input wire [31:0] SW_s1_readdata, // .readdata
output wire [0:0] sysid_control_slave_address, // sysid_control_slave.address
input wire [31:0] sysid_control_slave_readdata, // .readdata
output wire [2:0] timer_s1_address, // timer_s1.address
output wire timer_s1_write, // .write
input wire [15:0] timer_s1_readdata, // .readdata
output wire [15:0] timer_s1_writedata, // .writedata
output wire timer_s1_chipselect // .chipselect
);
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [24:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [7:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [24:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
wire [100:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [7:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_avalon_jtag_slave_agent_m0_readdata; // jtag_avalon_jtag_slave_translator:uav_readdata -> jtag_avalon_jtag_slave_agent:m0_readdata
wire jtag_avalon_jtag_slave_agent_m0_waitrequest; // jtag_avalon_jtag_slave_translator:uav_waitrequest -> jtag_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_avalon_jtag_slave_agent_m0_debugaccess; // jtag_avalon_jtag_slave_agent:m0_debugaccess -> jtag_avalon_jtag_slave_translator:uav_debugaccess
wire [24:0] jtag_avalon_jtag_slave_agent_m0_address; // jtag_avalon_jtag_slave_agent:m0_address -> jtag_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_avalon_jtag_slave_agent_m0_byteenable; // jtag_avalon_jtag_slave_agent:m0_byteenable -> jtag_avalon_jtag_slave_translator:uav_byteenable
wire jtag_avalon_jtag_slave_agent_m0_read; // jtag_avalon_jtag_slave_agent:m0_read -> jtag_avalon_jtag_slave_translator:uav_read
wire jtag_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_avalon_jtag_slave_agent_m0_lock; // jtag_avalon_jtag_slave_agent:m0_lock -> jtag_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_avalon_jtag_slave_agent_m0_writedata; // jtag_avalon_jtag_slave_agent:m0_writedata -> jtag_avalon_jtag_slave_translator:uav_writedata
wire jtag_avalon_jtag_slave_agent_m0_write; // jtag_avalon_jtag_slave_agent:m0_write -> jtag_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_avalon_jtag_slave_agent_m0_burstcount; // jtag_avalon_jtag_slave_agent:m0_burstcount -> jtag_avalon_jtag_slave_translator:uav_burstcount
wire jtag_avalon_jtag_slave_agent_rf_source_valid; // jtag_avalon_jtag_slave_agent:rf_source_valid -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [101:0] jtag_avalon_jtag_slave_agent_rf_source_data; // jtag_avalon_jtag_slave_agent:rf_source_data -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_avalon_jtag_slave_agent_rf_source_ready; // jtag_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_avalon_jtag_slave_agent:rf_source_ready
wire jtag_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_avalon_jtag_slave_agent:rf_sink_valid
wire [101:0] jtag_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_avalon_jtag_slave_agent:rf_sink_data
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_avalon_jtag_slave_agent:rf_sink_ready -> jtag_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_avalon_jtag_slave_agent_rdata_fifo:in_valid
wire [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_avalon_jtag_slave_agent_rdata_fifo:in_data
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire jtag_avalon_jtag_slave_agent_rdata_fifo_out_valid; // jtag_avalon_jtag_slave_agent_rdata_fifo:out_valid -> jtag_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_out_data; // jtag_avalon_jtag_slave_agent_rdata_fifo:out_data -> jtag_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_avalon_jtag_slave_agent_rdata_fifo_out_ready; // jtag_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_avalon_jtag_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_avalon_jtag_slave_agent:cp_valid
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [7:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] sysid_control_slave_agent_m0_readdata; // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_agent:m0_readdata
wire sysid_control_slave_agent_m0_waitrequest; // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_agent:m0_waitrequest
wire sysid_control_slave_agent_m0_debugaccess; // sysid_control_slave_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
wire [24:0] sysid_control_slave_agent_m0_address; // sysid_control_slave_agent:m0_address -> sysid_control_slave_translator:uav_address
wire [3:0] sysid_control_slave_agent_m0_byteenable; // sysid_control_slave_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
wire sysid_control_slave_agent_m0_read; // sysid_control_slave_agent:m0_read -> sysid_control_slave_translator:uav_read
wire sysid_control_slave_agent_m0_readdatavalid; // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_agent:m0_readdatavalid
wire sysid_control_slave_agent_m0_lock; // sysid_control_slave_agent:m0_lock -> sysid_control_slave_translator:uav_lock
wire [31:0] sysid_control_slave_agent_m0_writedata; // sysid_control_slave_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
wire sysid_control_slave_agent_m0_write; // sysid_control_slave_agent:m0_write -> sysid_control_slave_translator:uav_write
wire [2:0] sysid_control_slave_agent_m0_burstcount; // sysid_control_slave_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
wire sysid_control_slave_agent_rf_source_valid; // sysid_control_slave_agent:rf_source_valid -> sysid_control_slave_agent_rsp_fifo:in_valid
wire [101:0] sysid_control_slave_agent_rf_source_data; // sysid_control_slave_agent:rf_source_data -> sysid_control_slave_agent_rsp_fifo:in_data
wire sysid_control_slave_agent_rf_source_ready; // sysid_control_slave_agent_rsp_fifo:in_ready -> sysid_control_slave_agent:rf_source_ready
wire sysid_control_slave_agent_rf_source_startofpacket; // sysid_control_slave_agent:rf_source_startofpacket -> sysid_control_slave_agent_rsp_fifo:in_startofpacket
wire sysid_control_slave_agent_rf_source_endofpacket; // sysid_control_slave_agent:rf_source_endofpacket -> sysid_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_control_slave_agent_rsp_fifo_out_valid; // sysid_control_slave_agent_rsp_fifo:out_valid -> sysid_control_slave_agent:rf_sink_valid
wire [101:0] sysid_control_slave_agent_rsp_fifo_out_data; // sysid_control_slave_agent_rsp_fifo:out_data -> sysid_control_slave_agent:rf_sink_data
wire sysid_control_slave_agent_rsp_fifo_out_ready; // sysid_control_slave_agent:rf_sink_ready -> sysid_control_slave_agent_rsp_fifo:out_ready
wire sysid_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_agent:rf_sink_startofpacket
wire sysid_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_agent:rf_sink_endofpacket
wire sysid_control_slave_agent_rdata_fifo_src_valid; // sysid_control_slave_agent:rdata_fifo_src_valid -> sysid_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] sysid_control_slave_agent_rdata_fifo_src_data; // sysid_control_slave_agent:rdata_fifo_src_data -> sysid_control_slave_agent:rdata_fifo_sink_data
wire sysid_control_slave_agent_rdata_fifo_src_ready; // sysid_control_slave_agent:rdata_fifo_sink_ready -> sysid_control_slave_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sysid_control_slave_agent:cp_valid
wire [100:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sysid_control_slave_agent:cp_data
wire cmd_mux_001_src_ready; // sysid_control_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [7:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sysid_control_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sysid_control_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sysid_control_slave_agent:cp_endofpacket
wire [31:0] flash_epcs_control_port_agent_m0_readdata; // flash_epcs_control_port_translator:uav_readdata -> flash_epcs_control_port_agent:m0_readdata
wire flash_epcs_control_port_agent_m0_waitrequest; // flash_epcs_control_port_translator:uav_waitrequest -> flash_epcs_control_port_agent:m0_waitrequest
wire flash_epcs_control_port_agent_m0_debugaccess; // flash_epcs_control_port_agent:m0_debugaccess -> flash_epcs_control_port_translator:uav_debugaccess
wire [24:0] flash_epcs_control_port_agent_m0_address; // flash_epcs_control_port_agent:m0_address -> flash_epcs_control_port_translator:uav_address
wire [3:0] flash_epcs_control_port_agent_m0_byteenable; // flash_epcs_control_port_agent:m0_byteenable -> flash_epcs_control_port_translator:uav_byteenable
wire flash_epcs_control_port_agent_m0_read; // flash_epcs_control_port_agent:m0_read -> flash_epcs_control_port_translator:uav_read
wire flash_epcs_control_port_agent_m0_readdatavalid; // flash_epcs_control_port_translator:uav_readdatavalid -> flash_epcs_control_port_agent:m0_readdatavalid
wire flash_epcs_control_port_agent_m0_lock; // flash_epcs_control_port_agent:m0_lock -> flash_epcs_control_port_translator:uav_lock
wire [31:0] flash_epcs_control_port_agent_m0_writedata; // flash_epcs_control_port_agent:m0_writedata -> flash_epcs_control_port_translator:uav_writedata
wire flash_epcs_control_port_agent_m0_write; // flash_epcs_control_port_agent:m0_write -> flash_epcs_control_port_translator:uav_write
wire [2:0] flash_epcs_control_port_agent_m0_burstcount; // flash_epcs_control_port_agent:m0_burstcount -> flash_epcs_control_port_translator:uav_burstcount
wire flash_epcs_control_port_agent_rf_source_valid; // flash_epcs_control_port_agent:rf_source_valid -> flash_epcs_control_port_agent_rsp_fifo:in_valid
wire [101:0] flash_epcs_control_port_agent_rf_source_data; // flash_epcs_control_port_agent:rf_source_data -> flash_epcs_control_port_agent_rsp_fifo:in_data
wire flash_epcs_control_port_agent_rf_source_ready; // flash_epcs_control_port_agent_rsp_fifo:in_ready -> flash_epcs_control_port_agent:rf_source_ready
wire flash_epcs_control_port_agent_rf_source_startofpacket; // flash_epcs_control_port_agent:rf_source_startofpacket -> flash_epcs_control_port_agent_rsp_fifo:in_startofpacket
wire flash_epcs_control_port_agent_rf_source_endofpacket; // flash_epcs_control_port_agent:rf_source_endofpacket -> flash_epcs_control_port_agent_rsp_fifo:in_endofpacket
wire flash_epcs_control_port_agent_rsp_fifo_out_valid; // flash_epcs_control_port_agent_rsp_fifo:out_valid -> flash_epcs_control_port_agent:rf_sink_valid
wire [101:0] flash_epcs_control_port_agent_rsp_fifo_out_data; // flash_epcs_control_port_agent_rsp_fifo:out_data -> flash_epcs_control_port_agent:rf_sink_data
wire flash_epcs_control_port_agent_rsp_fifo_out_ready; // flash_epcs_control_port_agent:rf_sink_ready -> flash_epcs_control_port_agent_rsp_fifo:out_ready
wire flash_epcs_control_port_agent_rsp_fifo_out_startofpacket; // flash_epcs_control_port_agent_rsp_fifo:out_startofpacket -> flash_epcs_control_port_agent:rf_sink_startofpacket
wire flash_epcs_control_port_agent_rsp_fifo_out_endofpacket; // flash_epcs_control_port_agent_rsp_fifo:out_endofpacket -> flash_epcs_control_port_agent:rf_sink_endofpacket
wire flash_epcs_control_port_agent_rdata_fifo_src_valid; // flash_epcs_control_port_agent:rdata_fifo_src_valid -> flash_epcs_control_port_agent:rdata_fifo_sink_valid
wire [33:0] flash_epcs_control_port_agent_rdata_fifo_src_data; // flash_epcs_control_port_agent:rdata_fifo_src_data -> flash_epcs_control_port_agent:rdata_fifo_sink_data
wire flash_epcs_control_port_agent_rdata_fifo_src_ready; // flash_epcs_control_port_agent:rdata_fifo_sink_ready -> flash_epcs_control_port_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> flash_epcs_control_port_agent:cp_valid
wire [100:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> flash_epcs_control_port_agent:cp_data
wire cmd_mux_002_src_ready; // flash_epcs_control_port_agent:cp_ready -> cmd_mux_002:src_ready
wire [7:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> flash_epcs_control_port_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> flash_epcs_control_port_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> flash_epcs_control_port_agent:cp_endofpacket
wire [31:0] cpu_jtag_debug_module_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
wire cpu_jtag_debug_module_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
wire cpu_jtag_debug_module_agent_m0_debugaccess; // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
wire [24:0] cpu_jtag_debug_module_agent_m0_address; // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
wire [3:0] cpu_jtag_debug_module_agent_m0_byteenable; // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_agent_m0_read; // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
wire cpu_jtag_debug_module_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
wire cpu_jtag_debug_module_agent_m0_lock; // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
wire [31:0] cpu_jtag_debug_module_agent_m0_writedata; // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
wire cpu_jtag_debug_module_agent_m0_write; // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
wire [2:0] cpu_jtag_debug_module_agent_m0_burstcount; // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
wire cpu_jtag_debug_module_agent_rf_source_valid; // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
wire [101:0] cpu_jtag_debug_module_agent_rf_source_data; // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_agent_rf_source_ready; // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
wire cpu_jtag_debug_module_agent_rf_source_startofpacket; // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire cpu_jtag_debug_module_agent_rf_source_endofpacket; // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
wire [101:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
wire cpu_jtag_debug_module_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> cpu_jtag_debug_module_agent:cp_valid
wire [100:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> cpu_jtag_debug_module_agent:cp_data
wire cmd_mux_003_src_ready; // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux_003:src_ready
wire [7:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> cpu_jtag_debug_module_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
wire [31:0] timer_s1_agent_m0_readdata; // timer_s1_translator:uav_readdata -> timer_s1_agent:m0_readdata
wire timer_s1_agent_m0_waitrequest; // timer_s1_translator:uav_waitrequest -> timer_s1_agent:m0_waitrequest
wire timer_s1_agent_m0_debugaccess; // timer_s1_agent:m0_debugaccess -> timer_s1_translator:uav_debugaccess
wire [24:0] timer_s1_agent_m0_address; // timer_s1_agent:m0_address -> timer_s1_translator:uav_address
wire [3:0] timer_s1_agent_m0_byteenable; // timer_s1_agent:m0_byteenable -> timer_s1_translator:uav_byteenable
wire timer_s1_agent_m0_read; // timer_s1_agent:m0_read -> timer_s1_translator:uav_read
wire timer_s1_agent_m0_readdatavalid; // timer_s1_translator:uav_readdatavalid -> timer_s1_agent:m0_readdatavalid
wire timer_s1_agent_m0_lock; // timer_s1_agent:m0_lock -> timer_s1_translator:uav_lock
wire [31:0] timer_s1_agent_m0_writedata; // timer_s1_agent:m0_writedata -> timer_s1_translator:uav_writedata
wire timer_s1_agent_m0_write; // timer_s1_agent:m0_write -> timer_s1_translator:uav_write
wire [2:0] timer_s1_agent_m0_burstcount; // timer_s1_agent:m0_burstcount -> timer_s1_translator:uav_burstcount
wire timer_s1_agent_rf_source_valid; // timer_s1_agent:rf_source_valid -> timer_s1_agent_rsp_fifo:in_valid
wire [101:0] timer_s1_agent_rf_source_data; // timer_s1_agent:rf_source_data -> timer_s1_agent_rsp_fifo:in_data
wire timer_s1_agent_rf_source_ready; // timer_s1_agent_rsp_fifo:in_ready -> timer_s1_agent:rf_source_ready
wire timer_s1_agent_rf_source_startofpacket; // timer_s1_agent:rf_source_startofpacket -> timer_s1_agent_rsp_fifo:in_startofpacket
wire timer_s1_agent_rf_source_endofpacket; // timer_s1_agent:rf_source_endofpacket -> timer_s1_agent_rsp_fifo:in_endofpacket
wire timer_s1_agent_rsp_fifo_out_valid; // timer_s1_agent_rsp_fifo:out_valid -> timer_s1_agent:rf_sink_valid
wire [101:0] timer_s1_agent_rsp_fifo_out_data; // timer_s1_agent_rsp_fifo:out_data -> timer_s1_agent:rf_sink_data
wire timer_s1_agent_rsp_fifo_out_ready; // timer_s1_agent:rf_sink_ready -> timer_s1_agent_rsp_fifo:out_ready
wire timer_s1_agent_rsp_fifo_out_startofpacket; // timer_s1_agent_rsp_fifo:out_startofpacket -> timer_s1_agent:rf_sink_startofpacket
wire timer_s1_agent_rsp_fifo_out_endofpacket; // timer_s1_agent_rsp_fifo:out_endofpacket -> timer_s1_agent:rf_sink_endofpacket
wire timer_s1_agent_rdata_fifo_src_valid; // timer_s1_agent:rdata_fifo_src_valid -> timer_s1_agent_rdata_fifo:in_valid
wire [33:0] timer_s1_agent_rdata_fifo_src_data; // timer_s1_agent:rdata_fifo_src_data -> timer_s1_agent_rdata_fifo:in_data
wire timer_s1_agent_rdata_fifo_src_ready; // timer_s1_agent_rdata_fifo:in_ready -> timer_s1_agent:rdata_fifo_src_ready
wire timer_s1_agent_rdata_fifo_out_valid; // timer_s1_agent_rdata_fifo:out_valid -> timer_s1_agent:rdata_fifo_sink_valid
wire [33:0] timer_s1_agent_rdata_fifo_out_data; // timer_s1_agent_rdata_fifo:out_data -> timer_s1_agent:rdata_fifo_sink_data
wire timer_s1_agent_rdata_fifo_out_ready; // timer_s1_agent:rdata_fifo_sink_ready -> timer_s1_agent_rdata_fifo:out_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> timer_s1_agent:cp_valid
wire [100:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> timer_s1_agent:cp_data
wire cmd_mux_004_src_ready; // timer_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [7:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> timer_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> timer_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> timer_s1_agent:cp_endofpacket
wire [31:0] sw_s1_agent_m0_readdata; // SW_s1_translator:uav_readdata -> SW_s1_agent:m0_readdata
wire sw_s1_agent_m0_waitrequest; // SW_s1_translator:uav_waitrequest -> SW_s1_agent:m0_waitrequest
wire sw_s1_agent_m0_debugaccess; // SW_s1_agent:m0_debugaccess -> SW_s1_translator:uav_debugaccess
wire [24:0] sw_s1_agent_m0_address; // SW_s1_agent:m0_address -> SW_s1_translator:uav_address
wire [3:0] sw_s1_agent_m0_byteenable; // SW_s1_agent:m0_byteenable -> SW_s1_translator:uav_byteenable
wire sw_s1_agent_m0_read; // SW_s1_agent:m0_read -> SW_s1_translator:uav_read
wire sw_s1_agent_m0_readdatavalid; // SW_s1_translator:uav_readdatavalid -> SW_s1_agent:m0_readdatavalid
wire sw_s1_agent_m0_lock; // SW_s1_agent:m0_lock -> SW_s1_translator:uav_lock
wire [31:0] sw_s1_agent_m0_writedata; // SW_s1_agent:m0_writedata -> SW_s1_translator:uav_writedata
wire sw_s1_agent_m0_write; // SW_s1_agent:m0_write -> SW_s1_translator:uav_write
wire [2:0] sw_s1_agent_m0_burstcount; // SW_s1_agent:m0_burstcount -> SW_s1_translator:uav_burstcount
wire sw_s1_agent_rf_source_valid; // SW_s1_agent:rf_source_valid -> SW_s1_agent_rsp_fifo:in_valid
wire [101:0] sw_s1_agent_rf_source_data; // SW_s1_agent:rf_source_data -> SW_s1_agent_rsp_fifo:in_data
wire sw_s1_agent_rf_source_ready; // SW_s1_agent_rsp_fifo:in_ready -> SW_s1_agent:rf_source_ready
wire sw_s1_agent_rf_source_startofpacket; // SW_s1_agent:rf_source_startofpacket -> SW_s1_agent_rsp_fifo:in_startofpacket
wire sw_s1_agent_rf_source_endofpacket; // SW_s1_agent:rf_source_endofpacket -> SW_s1_agent_rsp_fifo:in_endofpacket
wire sw_s1_agent_rsp_fifo_out_valid; // SW_s1_agent_rsp_fifo:out_valid -> SW_s1_agent:rf_sink_valid
wire [101:0] sw_s1_agent_rsp_fifo_out_data; // SW_s1_agent_rsp_fifo:out_data -> SW_s1_agent:rf_sink_data
wire sw_s1_agent_rsp_fifo_out_ready; // SW_s1_agent:rf_sink_ready -> SW_s1_agent_rsp_fifo:out_ready
wire sw_s1_agent_rsp_fifo_out_startofpacket; // SW_s1_agent_rsp_fifo:out_startofpacket -> SW_s1_agent:rf_sink_startofpacket
wire sw_s1_agent_rsp_fifo_out_endofpacket; // SW_s1_agent_rsp_fifo:out_endofpacket -> SW_s1_agent:rf_sink_endofpacket
wire sw_s1_agent_rdata_fifo_src_valid; // SW_s1_agent:rdata_fifo_src_valid -> SW_s1_agent_rdata_fifo:in_valid
wire [33:0] sw_s1_agent_rdata_fifo_src_data; // SW_s1_agent:rdata_fifo_src_data -> SW_s1_agent_rdata_fifo:in_data
wire sw_s1_agent_rdata_fifo_src_ready; // SW_s1_agent_rdata_fifo:in_ready -> SW_s1_agent:rdata_fifo_src_ready
wire sw_s1_agent_rdata_fifo_out_valid; // SW_s1_agent_rdata_fifo:out_valid -> SW_s1_agent:rdata_fifo_sink_valid
wire [33:0] sw_s1_agent_rdata_fifo_out_data; // SW_s1_agent_rdata_fifo:out_data -> SW_s1_agent:rdata_fifo_sink_data
wire sw_s1_agent_rdata_fifo_out_ready; // SW_s1_agent:rdata_fifo_sink_ready -> SW_s1_agent_rdata_fifo:out_ready
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> SW_s1_agent:cp_valid
wire [100:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> SW_s1_agent:cp_data
wire cmd_mux_005_src_ready; // SW_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [7:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> SW_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> SW_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> SW_s1_agent:cp_endofpacket
wire [31:0] led_s1_agent_m0_readdata; // LED_s1_translator:uav_readdata -> LED_s1_agent:m0_readdata
wire led_s1_agent_m0_waitrequest; // LED_s1_translator:uav_waitrequest -> LED_s1_agent:m0_waitrequest
wire led_s1_agent_m0_debugaccess; // LED_s1_agent:m0_debugaccess -> LED_s1_translator:uav_debugaccess
wire [24:0] led_s1_agent_m0_address; // LED_s1_agent:m0_address -> LED_s1_translator:uav_address
wire [3:0] led_s1_agent_m0_byteenable; // LED_s1_agent:m0_byteenable -> LED_s1_translator:uav_byteenable
wire led_s1_agent_m0_read; // LED_s1_agent:m0_read -> LED_s1_translator:uav_read
wire led_s1_agent_m0_readdatavalid; // LED_s1_translator:uav_readdatavalid -> LED_s1_agent:m0_readdatavalid
wire led_s1_agent_m0_lock; // LED_s1_agent:m0_lock -> LED_s1_translator:uav_lock
wire [31:0] led_s1_agent_m0_writedata; // LED_s1_agent:m0_writedata -> LED_s1_translator:uav_writedata
wire led_s1_agent_m0_write; // LED_s1_agent:m0_write -> LED_s1_translator:uav_write
wire [2:0] led_s1_agent_m0_burstcount; // LED_s1_agent:m0_burstcount -> LED_s1_translator:uav_burstcount
wire led_s1_agent_rf_source_valid; // LED_s1_agent:rf_source_valid -> LED_s1_agent_rsp_fifo:in_valid
wire [101:0] led_s1_agent_rf_source_data; // LED_s1_agent:rf_source_data -> LED_s1_agent_rsp_fifo:in_data
wire led_s1_agent_rf_source_ready; // LED_s1_agent_rsp_fifo:in_ready -> LED_s1_agent:rf_source_ready
wire led_s1_agent_rf_source_startofpacket; // LED_s1_agent:rf_source_startofpacket -> LED_s1_agent_rsp_fifo:in_startofpacket
wire led_s1_agent_rf_source_endofpacket; // LED_s1_agent:rf_source_endofpacket -> LED_s1_agent_rsp_fifo:in_endofpacket
wire led_s1_agent_rsp_fifo_out_valid; // LED_s1_agent_rsp_fifo:out_valid -> LED_s1_agent:rf_sink_valid
wire [101:0] led_s1_agent_rsp_fifo_out_data; // LED_s1_agent_rsp_fifo:out_data -> LED_s1_agent:rf_sink_data
wire led_s1_agent_rsp_fifo_out_ready; // LED_s1_agent:rf_sink_ready -> LED_s1_agent_rsp_fifo:out_ready
wire led_s1_agent_rsp_fifo_out_startofpacket; // LED_s1_agent_rsp_fifo:out_startofpacket -> LED_s1_agent:rf_sink_startofpacket
wire led_s1_agent_rsp_fifo_out_endofpacket; // LED_s1_agent_rsp_fifo:out_endofpacket -> LED_s1_agent:rf_sink_endofpacket
wire led_s1_agent_rdata_fifo_src_valid; // LED_s1_agent:rdata_fifo_src_valid -> LED_s1_agent_rdata_fifo:in_valid
wire [33:0] led_s1_agent_rdata_fifo_src_data; // LED_s1_agent:rdata_fifo_src_data -> LED_s1_agent_rdata_fifo:in_data
wire led_s1_agent_rdata_fifo_src_ready; // LED_s1_agent_rdata_fifo:in_ready -> LED_s1_agent:rdata_fifo_src_ready
wire led_s1_agent_rdata_fifo_out_valid; // LED_s1_agent_rdata_fifo:out_valid -> LED_s1_agent:rdata_fifo_sink_valid
wire [33:0] led_s1_agent_rdata_fifo_out_data; // LED_s1_agent_rdata_fifo:out_data -> LED_s1_agent:rdata_fifo_sink_data
wire led_s1_agent_rdata_fifo_out_ready; // LED_s1_agent:rdata_fifo_sink_ready -> LED_s1_agent_rdata_fifo:out_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> LED_s1_agent:cp_valid
wire [100:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> LED_s1_agent:cp_data
wire cmd_mux_006_src_ready; // LED_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [7:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> LED_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> LED_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> LED_s1_agent:cp_endofpacket
wire [15:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [24:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire [1:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire [15:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire [1:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire [83:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire [83:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [17:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [17:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
wire sdram_s1_agent_rdata_fifo_out_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid
wire [100:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data
wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [7:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [100:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [100:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [7:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_avalon_jtag_slave_agent_rp_valid; // jtag_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [100:0] jtag_avalon_jtag_slave_agent_rp_data; // jtag_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_avalon_jtag_slave_agent:rp_ready
wire jtag_avalon_jtag_slave_agent_rp_startofpacket; // jtag_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rp_endofpacket; // jtag_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [100:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [7:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire sysid_control_slave_agent_rp_valid; // sysid_control_slave_agent:rp_valid -> router_003:sink_valid
wire [100:0] sysid_control_slave_agent_rp_data; // sysid_control_slave_agent:rp_data -> router_003:sink_data
wire sysid_control_slave_agent_rp_ready; // router_003:sink_ready -> sysid_control_slave_agent:rp_ready
wire sysid_control_slave_agent_rp_startofpacket; // sysid_control_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire sysid_control_slave_agent_rp_endofpacket; // sysid_control_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [100:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [7:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire flash_epcs_control_port_agent_rp_valid; // flash_epcs_control_port_agent:rp_valid -> router_004:sink_valid
wire [100:0] flash_epcs_control_port_agent_rp_data; // flash_epcs_control_port_agent:rp_data -> router_004:sink_data
wire flash_epcs_control_port_agent_rp_ready; // router_004:sink_ready -> flash_epcs_control_port_agent:rp_ready
wire flash_epcs_control_port_agent_rp_startofpacket; // flash_epcs_control_port_agent:rp_startofpacket -> router_004:sink_startofpacket
wire flash_epcs_control_port_agent_rp_endofpacket; // flash_epcs_control_port_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [100:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [7:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire cpu_jtag_debug_module_agent_rp_valid; // cpu_jtag_debug_module_agent:rp_valid -> router_005:sink_valid
wire [100:0] cpu_jtag_debug_module_agent_rp_data; // cpu_jtag_debug_module_agent:rp_data -> router_005:sink_data
wire cpu_jtag_debug_module_agent_rp_ready; // router_005:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
wire cpu_jtag_debug_module_agent_rp_startofpacket; // cpu_jtag_debug_module_agent:rp_startofpacket -> router_005:sink_startofpacket
wire cpu_jtag_debug_module_agent_rp_endofpacket; // cpu_jtag_debug_module_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [100:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [7:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire timer_s1_agent_rp_valid; // timer_s1_agent:rp_valid -> router_006:sink_valid
wire [100:0] timer_s1_agent_rp_data; // timer_s1_agent:rp_data -> router_006:sink_data
wire timer_s1_agent_rp_ready; // router_006:sink_ready -> timer_s1_agent:rp_ready
wire timer_s1_agent_rp_startofpacket; // timer_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire timer_s1_agent_rp_endofpacket; // timer_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [100:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [7:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sw_s1_agent_rp_valid; // SW_s1_agent:rp_valid -> router_007:sink_valid
wire [100:0] sw_s1_agent_rp_data; // SW_s1_agent:rp_data -> router_007:sink_data
wire sw_s1_agent_rp_ready; // router_007:sink_ready -> SW_s1_agent:rp_ready
wire sw_s1_agent_rp_startofpacket; // SW_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sw_s1_agent_rp_endofpacket; // SW_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [100:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [7:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire led_s1_agent_rp_valid; // LED_s1_agent:rp_valid -> router_008:sink_valid
wire [100:0] led_s1_agent_rp_data; // LED_s1_agent:rp_data -> router_008:sink_data
wire led_s1_agent_rp_ready; // router_008:sink_ready -> LED_s1_agent:rp_ready
wire led_s1_agent_rp_startofpacket; // LED_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire led_s1_agent_rp_endofpacket; // LED_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [100:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [7:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_009:sink_valid
wire [82:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_009:sink_data
wire sdram_s1_agent_rp_ready; // router_009:sink_ready -> sdram_s1_agent:rp_ready
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire sdram_s1_burst_adapter_source0_valid; // sdram_s1_burst_adapter:source0_valid -> sdram_s1_agent:cp_valid
wire [82:0] sdram_s1_burst_adapter_source0_data; // sdram_s1_burst_adapter:source0_data -> sdram_s1_agent:cp_data
wire sdram_s1_burst_adapter_source0_ready; // sdram_s1_agent:cp_ready -> sdram_s1_burst_adapter:source0_ready
wire [7:0] sdram_s1_burst_adapter_source0_channel; // sdram_s1_burst_adapter:source0_channel -> sdram_s1_agent:cp_channel
wire sdram_s1_burst_adapter_source0_startofpacket; // sdram_s1_burst_adapter:source0_startofpacket -> sdram_s1_agent:cp_startofpacket
wire sdram_s1_burst_adapter_source0_endofpacket; // sdram_s1_burst_adapter:source0_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [100:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [7:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [100:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [7:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [100:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [7:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [100:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [7:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_002:sink1_valid
wire [100:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src0_ready
wire [7:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_003:sink1_valid
wire [100:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src1_ready
wire [7:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_007:sink1_valid
wire [100:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_007:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src2_ready
wire [7:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_007:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [100:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [7:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [100:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [7:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink0_valid
wire [100:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_002:src1_ready
wire [7:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [100:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [7:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink1_valid
wire [100:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_003:src1_ready
wire [7:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [100:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [7:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink2_valid
wire [100:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_007_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_007:src1_ready
wire [7:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire router_009_src_valid; // router_009:src_valid -> sdram_s1_rsp_width_adapter:in_valid
wire [82:0] router_009_src_data; // router_009:src_data -> sdram_s1_rsp_width_adapter:in_data
wire router_009_src_ready; // sdram_s1_rsp_width_adapter:in_ready -> router_009:src_ready
wire [7:0] router_009_src_channel; // router_009:src_channel -> sdram_s1_rsp_width_adapter:in_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> sdram_s1_rsp_width_adapter:in_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> sdram_s1_rsp_width_adapter:in_endofpacket
wire sdram_s1_rsp_width_adapter_src_valid; // sdram_s1_rsp_width_adapter:out_valid -> rsp_demux_007:sink_valid
wire [100:0] sdram_s1_rsp_width_adapter_src_data; // sdram_s1_rsp_width_adapter:out_data -> rsp_demux_007:sink_data
wire sdram_s1_rsp_width_adapter_src_ready; // rsp_demux_007:sink_ready -> sdram_s1_rsp_width_adapter:out_ready
wire [7:0] sdram_s1_rsp_width_adapter_src_channel; // sdram_s1_rsp_width_adapter:out_channel -> rsp_demux_007:sink_channel
wire sdram_s1_rsp_width_adapter_src_startofpacket; // sdram_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_007:sink_startofpacket
wire sdram_s1_rsp_width_adapter_src_endofpacket; // sdram_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_007:sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sdram_s1_cmd_width_adapter:in_valid
wire [100:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sdram_s1_cmd_width_adapter:in_data
wire cmd_mux_007_src_ready; // sdram_s1_cmd_width_adapter:in_ready -> cmd_mux_007:src_ready
wire [7:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sdram_s1_cmd_width_adapter:in_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sdram_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sdram_s1_cmd_width_adapter:in_endofpacket
wire sdram_s1_cmd_width_adapter_src_valid; // sdram_s1_cmd_width_adapter:out_valid -> sdram_s1_burst_adapter:sink0_valid
wire [82:0] sdram_s1_cmd_width_adapter_src_data; // sdram_s1_cmd_width_adapter:out_data -> sdram_s1_burst_adapter:sink0_data
wire sdram_s1_cmd_width_adapter_src_ready; // sdram_s1_burst_adapter:sink0_ready -> sdram_s1_cmd_width_adapter:out_ready
wire [7:0] sdram_s1_cmd_width_adapter_src_channel; // sdram_s1_cmd_width_adapter:out_channel -> sdram_s1_burst_adapter:sink0_channel
wire sdram_s1_cmd_width_adapter_src_startofpacket; // sdram_s1_cmd_width_adapter:out_startofpacket -> sdram_s1_burst_adapter:sink0_startofpacket
wire sdram_s1_cmd_width_adapter_src_endofpacket; // sdram_s1_cmd_width_adapter:out_endofpacket -> sdram_s1_burst_adapter:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire [7:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire [100:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire [7:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> crosser_001:in_valid
wire [100:0] cmd_demux_src4_data; // cmd_demux:src4_data -> crosser_001:in_data
wire cmd_demux_src4_ready; // crosser_001:in_ready -> cmd_demux:src4_ready
wire [7:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> crosser_001:in_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> crosser_001:in_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_004:sink0_valid
wire [100:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_004:sink0_data
wire crosser_001_out_ready; // cmd_mux_004:sink0_ready -> crosser_001:out_ready
wire [7:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_004:sink0_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_004:sink0_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> crosser_002:in_valid
wire [100:0] cmd_demux_src5_data; // cmd_demux:src5_data -> crosser_002:in_data
wire cmd_demux_src5_ready; // crosser_002:in_ready -> cmd_demux:src5_ready
wire [7:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> crosser_002:in_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> crosser_002:in_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> crosser_002:in_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> cmd_mux_005:sink0_valid
wire [100:0] crosser_002_out_data; // crosser_002:out_data -> cmd_mux_005:sink0_data
wire crosser_002_out_ready; // cmd_mux_005:sink0_ready -> crosser_002:out_ready
wire [7:0] crosser_002_out_channel; // crosser_002:out_channel -> cmd_mux_005:sink0_channel
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> cmd_mux_005:sink0_startofpacket
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> crosser_003:in_valid
wire [100:0] cmd_demux_src6_data; // cmd_demux:src6_data -> crosser_003:in_data
wire cmd_demux_src6_ready; // crosser_003:in_ready -> cmd_demux:src6_ready
wire [7:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> crosser_003:in_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> crosser_003:in_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> crosser_003:in_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> cmd_mux_006:sink0_valid
wire [100:0] crosser_003_out_data; // crosser_003:out_data -> cmd_mux_006:sink0_data
wire crosser_003_out_ready; // cmd_mux_006:sink0_ready -> crosser_003:out_ready
wire [7:0] crosser_003_out_channel; // crosser_003:out_channel -> cmd_mux_006:sink0_channel
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> cmd_mux_006:sink0_startofpacket
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> cmd_mux_006:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_004:in_valid
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_004:in_data
wire rsp_demux_src0_ready; // crosser_004:in_ready -> rsp_demux:src0_ready
wire [7:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_004:in_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_004:in_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_004:in_endofpacket
wire crosser_004_out_valid; // crosser_004:out_valid -> rsp_mux:sink0_valid
wire [100:0] crosser_004_out_data; // crosser_004:out_data -> rsp_mux:sink0_data
wire crosser_004_out_ready; // rsp_mux:sink0_ready -> crosser_004:out_ready
wire [7:0] crosser_004_out_channel; // crosser_004:out_channel -> rsp_mux:sink0_channel
wire crosser_004_out_startofpacket; // crosser_004:out_startofpacket -> rsp_mux:sink0_startofpacket
wire crosser_004_out_endofpacket; // crosser_004:out_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> crosser_005:in_valid
wire [100:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> crosser_005:in_data
wire rsp_demux_004_src0_ready; // crosser_005:in_ready -> rsp_demux_004:src0_ready
wire [7:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> crosser_005:in_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> crosser_005:in_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> crosser_005:in_endofpacket
wire crosser_005_out_valid; // crosser_005:out_valid -> rsp_mux:sink4_valid
wire [100:0] crosser_005_out_data; // crosser_005:out_data -> rsp_mux:sink4_data
wire crosser_005_out_ready; // rsp_mux:sink4_ready -> crosser_005:out_ready
wire [7:0] crosser_005_out_channel; // crosser_005:out_channel -> rsp_mux:sink4_channel
wire crosser_005_out_startofpacket; // crosser_005:out_startofpacket -> rsp_mux:sink4_startofpacket
wire crosser_005_out_endofpacket; // crosser_005:out_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> crosser_006:in_valid
wire [100:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> crosser_006:in_data
wire rsp_demux_005_src0_ready; // crosser_006:in_ready -> rsp_demux_005:src0_ready
wire [7:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> crosser_006:in_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> crosser_006:in_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> crosser_006:in_endofpacket
wire crosser_006_out_valid; // crosser_006:out_valid -> rsp_mux:sink5_valid
wire [100:0] crosser_006_out_data; // crosser_006:out_data -> rsp_mux:sink5_data
wire crosser_006_out_ready; // rsp_mux:sink5_ready -> crosser_006:out_ready
wire [7:0] crosser_006_out_channel; // crosser_006:out_channel -> rsp_mux:sink5_channel
wire crosser_006_out_startofpacket; // crosser_006:out_startofpacket -> rsp_mux:sink5_startofpacket
wire crosser_006_out_endofpacket; // crosser_006:out_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> crosser_007:in_valid
wire [100:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> crosser_007:in_data
wire rsp_demux_006_src0_ready; // crosser_007:in_ready -> rsp_demux_006:src0_ready
wire [7:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> crosser_007:in_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> crosser_007:in_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> crosser_007:in_endofpacket
wire crosser_007_out_valid; // crosser_007:out_valid -> rsp_mux:sink6_valid
wire [100:0] crosser_007_out_data; // crosser_007:out_data -> rsp_mux:sink6_data
wire crosser_007_out_ready; // rsp_mux:sink6_ready -> crosser_007:out_ready
wire [7:0] crosser_007_out_channel; // crosser_007:out_channel -> rsp_mux:sink6_channel
wire crosser_007_out_startofpacket; // crosser_007:out_startofpacket -> rsp_mux:sink6_startofpacket
wire crosser_007_out_endofpacket; // crosser_007:out_endofpacket -> rsp_mux:sink6_endofpacket
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_avalon_jtag_slave_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_avalon_jtag_slave_write), // .write
.av_read (jtag_avalon_jtag_slave_read), // .read
.av_readdata (jtag_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_control_slave_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_control_slave_agent_m0_read), // .read
.uav_write (sysid_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) flash_epcs_control_port_translator (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (flash_epcs_control_port_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (flash_epcs_control_port_agent_m0_burstcount), // .burstcount
.uav_read (flash_epcs_control_port_agent_m0_read), // .read
.uav_write (flash_epcs_control_port_agent_m0_write), // .write
.uav_waitrequest (flash_epcs_control_port_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (flash_epcs_control_port_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (flash_epcs_control_port_agent_m0_byteenable), // .byteenable
.uav_readdata (flash_epcs_control_port_agent_m0_readdata), // .readdata
.uav_writedata (flash_epcs_control_port_agent_m0_writedata), // .writedata
.uav_lock (flash_epcs_control_port_agent_m0_lock), // .lock
.uav_debugaccess (flash_epcs_control_port_agent_m0_debugaccess), // .debugaccess
.av_address (flash_epcs_control_port_address), // avalon_anti_slave_0.address
.av_write (flash_epcs_control_port_write), // .write
.av_read (flash_epcs_control_port_read), // .read
.av_readdata (flash_epcs_control_port_readdata), // .readdata
.av_writedata (flash_epcs_control_port_writedata), // .writedata
.av_chipselect (flash_epcs_control_port_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_write), // .write
.av_read (cpu_jtag_debug_module_read), // .read
.av_readdata (cpu_jtag_debug_module_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_writedata), // .writedata
.av_byteenable (cpu_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (cpu_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (cpu_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_s1_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (timer_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_s1_agent_m0_burstcount), // .burstcount
.uav_read (timer_s1_agent_m0_read), // .read
.uav_write (timer_s1_agent_m0_write), // .write
.uav_waitrequest (timer_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_s1_agent_m0_readdata), // .readdata
.uav_writedata (timer_s1_agent_m0_writedata), // .writedata
.uav_lock (timer_s1_agent_m0_lock), // .lock
.uav_debugaccess (timer_s1_agent_m0_debugaccess), // .debugaccess
.av_address (timer_s1_address), // avalon_anti_slave_0.address
.av_write (timer_s1_write), // .write
.av_readdata (timer_s1_readdata), // .readdata
.av_writedata (timer_s1_writedata), // .writedata
.av_chipselect (timer_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_s1_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.uav_read (sw_s1_agent_m0_read), // .read
.uav_write (sw_s1_agent_m0_write), // .write
.uav_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_s1_agent_m0_readdata), // .readdata
.uav_writedata (sw_s1_agent_m0_writedata), // .writedata
.uav_lock (sw_s1_agent_m0_lock), // .lock
.uav_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SW_s1_address), // avalon_anti_slave_0.address
.av_readdata (SW_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_s1_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (led_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_s1_agent_m0_burstcount), // .burstcount
.uav_read (led_s1_agent_m0_read), // .read
.uav_write (led_s1_agent_m0_write), // .write
.uav_waitrequest (led_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (led_s1_agent_m0_readdata), // .readdata
.uav_writedata (led_s1_agent_m0_writedata), // .writedata
.uav_lock (led_s1_agent_m0_lock), // .lock
.uav_debugaccess (led_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LED_s1_address), // avalon_anti_slave_0.address
.av_write (LED_s1_write), // .write
.av_readdata (LED_s1_readdata), // .readdata
.av_writedata (LED_s1_writedata), // .writedata
.av_chipselect (LED_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (81),
.PKT_QOS_L (81),
.PKT_DATA_SIDEBAND_H (79),
.PKT_DATA_SIDEBAND_L (79),
.PKT_ADDR_SIDEBAND_H (78),
.PKT_ADDR_SIDEBAND_L (78),
.PKT_BURST_TYPE_H (77),
.PKT_BURST_TYPE_L (76),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_EXCLUSIVE (66),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.ST_DATA_W (101),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (81),
.PKT_QOS_L (81),
.PKT_DATA_SIDEBAND_H (79),
.PKT_DATA_SIDEBAND_L (79),
.PKT_ADDR_SIDEBAND_H (78),
.PKT_ADDR_SIDEBAND_L (78),
.PKT_BURST_TYPE_H (77),
.PKT_BURST_TYPE_L (76),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_EXCLUSIVE (66),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.ST_DATA_W (101),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_avalon_jtag_slave_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (jtag_avalon_jtag_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_avalon_jtag_slave_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (jtag_avalon_jtag_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_control_slave_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (sysid_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_control_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_control_slave_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) flash_epcs_control_port_agent (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (flash_epcs_control_port_agent_m0_address), // m0.address
.m0_burstcount (flash_epcs_control_port_agent_m0_burstcount), // .burstcount
.m0_byteenable (flash_epcs_control_port_agent_m0_byteenable), // .byteenable
.m0_debugaccess (flash_epcs_control_port_agent_m0_debugaccess), // .debugaccess
.m0_lock (flash_epcs_control_port_agent_m0_lock), // .lock
.m0_readdata (flash_epcs_control_port_agent_m0_readdata), // .readdata
.m0_readdatavalid (flash_epcs_control_port_agent_m0_readdatavalid), // .readdatavalid
.m0_read (flash_epcs_control_port_agent_m0_read), // .read
.m0_waitrequest (flash_epcs_control_port_agent_m0_waitrequest), // .waitrequest
.m0_writedata (flash_epcs_control_port_agent_m0_writedata), // .writedata
.m0_write (flash_epcs_control_port_agent_m0_write), // .write
.rp_endofpacket (flash_epcs_control_port_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (flash_epcs_control_port_agent_rp_ready), // .ready
.rp_valid (flash_epcs_control_port_agent_rp_valid), // .valid
.rp_data (flash_epcs_control_port_agent_rp_data), // .data
.rp_startofpacket (flash_epcs_control_port_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (flash_epcs_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (flash_epcs_control_port_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (flash_epcs_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (flash_epcs_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (flash_epcs_control_port_agent_rsp_fifo_out_data), // .data
.rf_source_ready (flash_epcs_control_port_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (flash_epcs_control_port_agent_rf_source_valid), // .valid
.rf_source_startofpacket (flash_epcs_control_port_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (flash_epcs_control_port_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (flash_epcs_control_port_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (flash_epcs_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (flash_epcs_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (flash_epcs_control_port_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (flash_epcs_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (flash_epcs_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (flash_epcs_control_port_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) flash_epcs_control_port_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (flash_epcs_control_port_agent_rf_source_data), // in.data
.in_valid (flash_epcs_control_port_agent_rf_source_valid), // .valid
.in_ready (flash_epcs_control_port_agent_rf_source_ready), // .ready
.in_startofpacket (flash_epcs_control_port_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (flash_epcs_control_port_agent_rf_source_endofpacket), // .endofpacket
.out_data (flash_epcs_control_port_agent_rsp_fifo_out_data), // out.data
.out_valid (flash_epcs_control_port_agent_rsp_fifo_out_valid), // .valid
.out_ready (flash_epcs_control_port_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (flash_epcs_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (flash_epcs_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_jtag_debug_module_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) timer_s1_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (timer_s1_agent_m0_address), // m0.address
.m0_burstcount (timer_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_s1_agent_m0_lock), // .lock
.m0_readdata (timer_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_s1_agent_m0_read), // .read
.m0_waitrequest (timer_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_s1_agent_m0_writedata), // .writedata
.m0_write (timer_s1_agent_m0_write), // .write
.rp_endofpacket (timer_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_s1_agent_rp_ready), // .ready
.rp_valid (timer_s1_agent_rp_valid), // .valid
.rp_data (timer_s1_agent_rp_data), // .data
.rp_startofpacket (timer_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (timer_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (timer_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (timer_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_s1_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (timer_s1_agent_rf_source_data), // in.data
.in_valid (timer_s1_agent_rf_source_valid), // .valid
.in_ready (timer_s1_agent_rf_source_ready), // .ready
.in_startofpacket (timer_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_s1_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (timer_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (timer_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (timer_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (timer_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (timer_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (timer_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_s1_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_s1_agent_m0_address), // m0.address
.m0_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_s1_agent_m0_lock), // .lock
.m0_readdata (sw_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_s1_agent_m0_read), // .read
.m0_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_s1_agent_m0_writedata), // .writedata
.m0_write (sw_s1_agent_m0_write), // .write
.rp_endofpacket (sw_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_s1_agent_rp_ready), // .ready
.rp_valid (sw_s1_agent_rp_valid), // .valid
.rp_data (sw_s1_agent_rp_data), // .data
.rp_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sw_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sw_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sw_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_agent_rf_source_data), // in.data
.in_valid (sw_s1_agent_rf_source_valid), // .valid
.in_ready (sw_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sw_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sw_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sw_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sw_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) led_s1_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (led_s1_agent_m0_address), // m0.address
.m0_burstcount (led_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_s1_agent_m0_lock), // .lock
.m0_readdata (led_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_s1_agent_m0_read), // .read
.m0_waitrequest (led_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_s1_agent_m0_writedata), // .writedata
.m0_write (led_s1_agent_m0_write), // .write
.rp_endofpacket (led_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_s1_agent_rp_ready), // .ready
.rp_valid (led_s1_agent_rp_valid), // .valid
.rp_data (led_s1_agent_rp_data), // .data
.rp_startofpacket (led_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (led_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (led_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (led_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (led_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (led_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_s1_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_s1_agent_rf_source_data), // in.data
.in_valid (led_s1_agent_rf_source_valid), // .valid
.in_ready (led_s1_agent_rf_source_ready), // .ready
.in_startofpacket (led_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (led_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_s1_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (led_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (led_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (led_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (led_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (led_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (82),
.PKT_ORI_BURST_SIZE_L (80),
.PKT_RESPONSE_STATUS_H (79),
.PKT_RESPONSE_STATUS_L (78),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.PKT_TRANS_LOCK (47),
.PKT_BEGIN_BURST (62),
.PKT_PROTECTION_H (73),
.PKT_PROTECTION_L (71),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (66),
.PKT_SRC_ID_L (64),
.PKT_DEST_ID_H (69),
.PKT_DEST_ID_L (67),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (83),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_agent (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (84),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
mi_nios_mm_interconnect_0_router router (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_003 (
.sink_ready (sysid_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_004 router_004 (
.sink_ready (flash_epcs_control_port_agent_rp_ready), // sink.ready
.sink_valid (flash_epcs_control_port_agent_rp_valid), // .valid
.sink_data (flash_epcs_control_port_agent_rp_data), // .data
.sink_startofpacket (flash_epcs_control_port_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (flash_epcs_control_port_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_004 router_005 (
.sink_ready (cpu_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_006 (
.sink_ready (timer_s1_agent_rp_ready), // sink.ready
.sink_valid (timer_s1_agent_rp_valid), // .valid
.sink_data (timer_s1_agent_rp_data), // .data
.sink_startofpacket (timer_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_007 (
.sink_ready (sw_s1_agent_rp_ready), // sink.ready
.sink_valid (sw_s1_agent_rp_valid), // .valid
.sink_data (sw_s1_agent_rp_data), // .data
.sink_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_008 (
.sink_ready (led_s1_agent_rp_ready), // sink.ready
.sink_valid (led_s1_agent_rp_valid), // .valid
.sink_data (led_s1_agent_rp_data), // .data
.sink_startofpacket (led_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_009 router_009 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (62),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.PKT_BURST_TYPE_H (59),
.PKT_BURST_TYPE_L (58),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (83),
.ST_CHANNEL_W (8),
.OUT_BYTE_CNT_H (50),
.OUT_BURSTWRAP_H (54),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3),
.ADAPTER_VERSION ("13.1")
) sdram_s1_burst_adapter (
.clk (pll_c0_clk), // cr0.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sdram_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sdram_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (sdram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_s1_burst_adapter_source0_ready) // .ready
);
mi_nios_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (crosser_003_out_ready), // sink0.ready
.sink0_valid (crosser_003_out_valid), // .valid
.sink0_channel (crosser_003_out_channel), // .channel
.sink0_data (crosser_003_out_data), // .data
.sink0_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux_002 cmd_mux_007 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_002 rsp_demux_007 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sdram_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sdram_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_004_out_ready), // sink0.ready
.sink0_valid (crosser_004_out_valid), // .valid
.sink0_channel (crosser_004_out_channel), // .channel
.sink0_data (crosser_004_out_data), // .data
.sink0_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (crosser_005_out_ready), // sink4.ready
.sink4_valid (crosser_005_out_valid), // .valid
.sink4_channel (crosser_005_out_channel), // .channel
.sink4_data (crosser_005_out_data), // .data
.sink4_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.sink4_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.sink5_ready (crosser_006_out_ready), // sink5.ready
.sink5_valid (crosser_006_out_valid), // .valid
.sink5_channel (crosser_006_out_channel), // .channel
.sink5_data (crosser_006_out_data), // .data
.sink5_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.sink5_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.sink6_ready (crosser_007_out_ready), // sink6.ready
.sink6_valid (crosser_007_out_valid), // .valid
.sink6_channel (crosser_007_out_channel), // .channel
.sink6_data (crosser_007_out_data), // .data
.sink6_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.sink6_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_002_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_002_src1_valid), // .valid
.sink0_channel (rsp_demux_002_src1_channel), // .channel
.sink0_data (rsp_demux_002_src1_data), // .data
.sink0_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src1_valid), // .valid
.sink1_channel (rsp_demux_003_src1_channel), // .channel
.sink1_data (rsp_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_007_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_007_src1_valid), // .valid
.sink2_channel (rsp_demux_007_src1_channel), // .channel
.sink2_data (rsp_demux_007_src1_data), // .data
.sink2_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (42),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (51),
.IN_PKT_BYTE_CNT_L (49),
.IN_PKT_TRANS_COMPRESSED_READ (43),
.IN_PKT_BURSTWRAP_H (54),
.IN_PKT_BURSTWRAP_L (52),
.IN_PKT_BURST_SIZE_H (57),
.IN_PKT_BURST_SIZE_L (55),
.IN_PKT_RESPONSE_STATUS_H (79),
.IN_PKT_RESPONSE_STATUS_L (78),
.IN_PKT_TRANS_EXCLUSIVE (48),
.IN_PKT_BURST_TYPE_H (59),
.IN_PKT_BURST_TYPE_L (58),
.IN_PKT_ORI_BURST_SIZE_L (80),
.IN_PKT_ORI_BURST_SIZE_H (82),
.IN_ST_DATA_W (83),
.OUT_PKT_ADDR_H (60),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (69),
.OUT_PKT_BYTE_CNT_L (67),
.OUT_PKT_TRANS_COMPRESSED_READ (61),
.OUT_PKT_BURST_SIZE_H (75),
.OUT_PKT_BURST_SIZE_L (73),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (66),
.OUT_PKT_BURST_TYPE_H (77),
.OUT_PKT_BURST_TYPE_L (76),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (8),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_rsp_width_adapter (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_009_src_valid), // sink.valid
.in_channel (router_009_src_channel), // .channel
.in_startofpacket (router_009_src_startofpacket), // .startofpacket
.in_endofpacket (router_009_src_endofpacket), // .endofpacket
.in_ready (router_009_src_ready), // .ready
.in_data (router_009_src_data), // .data
.out_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_rsp_width_adapter_src_data), // .data
.out_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (60),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (69),
.IN_PKT_BYTE_CNT_L (67),
.IN_PKT_TRANS_COMPRESSED_READ (61),
.IN_PKT_BURSTWRAP_H (72),
.IN_PKT_BURSTWRAP_L (70),
.IN_PKT_BURST_SIZE_H (75),
.IN_PKT_BURST_SIZE_L (73),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (66),
.IN_PKT_BURST_TYPE_H (77),
.IN_PKT_BURST_TYPE_L (76),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (42),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (51),
.OUT_PKT_BYTE_CNT_L (49),
.OUT_PKT_TRANS_COMPRESSED_READ (43),
.OUT_PKT_BURST_SIZE_H (57),
.OUT_PKT_BURST_SIZE_L (55),
.OUT_PKT_RESPONSE_STATUS_H (79),
.OUT_PKT_RESPONSE_STATUS_L (78),
.OUT_PKT_TRANS_EXCLUSIVE (48),
.OUT_PKT_BURST_TYPE_H (59),
.OUT_PKT_BURST_TYPE_L (58),
.OUT_PKT_ORI_BURST_SIZE_L (80),
.OUT_PKT_ORI_BURST_SIZE_H (82),
.OUT_ST_DATA_W (83),
.ST_CHANNEL_W (8),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_cmd_width_adapter (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_007_src_valid), // sink.valid
.in_channel (cmd_mux_007_src_channel), // .channel
.in_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_007_src_ready), // .ready
.in_data (cmd_mux_007_src_data), // .data
.out_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_cmd_width_adapter_src_data), // .data
.out_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src4_ready), // in.ready
.in_valid (cmd_demux_src4_valid), // .valid
.in_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.in_channel (cmd_demux_src4_channel), // .channel
.in_data (cmd_demux_src4_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src5_ready), // in.ready
.in_valid (cmd_demux_src5_valid), // .valid
.in_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.in_channel (cmd_demux_src5_channel), // .channel
.in_data (cmd_demux_src5_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src6_ready), // in.ready
.in_valid (cmd_demux_src6_valid), // .valid
.in_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.in_channel (cmd_demux_src6_channel), // .channel
.in_data (cmd_demux_src6_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_004 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_004_out_ready), // out.ready
.out_valid (crosser_004_out_valid), // .valid
.out_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.out_channel (crosser_004_out_channel), // .channel
.out_data (crosser_004_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_005 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_004_src0_ready), // in.ready
.in_valid (rsp_demux_004_src0_valid), // .valid
.in_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_004_src0_channel), // .channel
.in_data (rsp_demux_004_src0_data), // .data
.out_ready (crosser_005_out_ready), // out.ready
.out_valid (crosser_005_out_valid), // .valid
.out_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.out_channel (crosser_005_out_channel), // .channel
.out_data (crosser_005_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_006 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src0_ready), // in.ready
.in_valid (rsp_demux_005_src0_valid), // .valid
.in_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src0_channel), // .channel
.in_data (rsp_demux_005_src0_data), // .data
.out_ready (crosser_006_out_ready), // out.ready
.out_valid (crosser_006_out_valid), // .valid
.out_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.out_channel (crosser_006_out_channel), // .channel
.out_data (crosser_006_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_007 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_006_src0_ready), // in.ready
.in_valid (rsp_demux_006_src0_valid), // .valid
.in_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_006_src0_channel), // .channel
.in_data (rsp_demux_006_src0_data), // .data
.out_ready (crosser_007_out_ready), // out.ready
.out_valid (crosser_007_out_valid), // .valid
.out_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.out_channel (crosser_007_out_channel), // .channel
.out_data (crosser_007_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output wire [ 7:0 ] z
);
assign z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output reg [ 7:0 ] z
);
wire [7:0] zi;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/17.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2017/08/25 $
// $Author: nkrueger $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Tue May 13 22:55:34 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_6/ip/clk_base/clk_base_stub.v
// Design : clk_base
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_base(clk_raw, clk_250MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_raw,clk_250MHz,locked" */;
input clk_raw;
output clk_250MHz;
output locked;
endmodule
|
//
// Copyright (c) 2003 Launchbird Design Systems, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
// Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Overview:
//
// Performs a radix 2 Fast Fourier Transform.
// The FFT architecture is pipelined on a rank basis; each rank has its own butterfly and ranks are
// isolated from each other using memory interleavers. This FFT can perform calcualations on continuous
// streaming data (one data set right after another). More over, inputs and outputs are passed in pairs,
// doubling the bandwidth. For instance, a 2048 point FFT can perform a transform every 1024 cycles.
//
// Interface:
//
// Synchronization:
// clock_c : Clock input.
// enable_i : Synchronous enable.
// reset_i : Synchronous reset.
//
// Inputs:
// sync_i : Input sync pulse must occur one frame prior to data input.
// data_0_i : Input data 0. Width is 2 * precision. Real on the left, imag on the right.
// data_1_i : Input data 1. Width is 2 * precision. Real on the left, imag on the right.
//
// Outputs:
// sync_o : Output sync pulse occurs one frame before data output.
// data_0_o : Output data 0. Width is 2 * precision. Real on the left, imag on the right.
// data_1_o : Output data 1. Width is 2 * precision. Real on the left, imag on the right.
//
// Built In Parameters:
//
// FFT Points = 256
// Precision = 8
//
//
//
//
// Generated by Confluence 0.3.0 -- Launchbird Design Systems, Inc. -- www.launchbird.com
//
// Interface
//
// Build Name : cf_fft_256_8
// Clock Domains : clock_c
// Input : enable_i(1)
// Input : reset_i(1)
// Input : sync_i(1)
// Input : data_0_i(16)
// Input : data_1_i(16)
// Output : sync_o(1)
// Output : data_0_o(16)
// Output : data_1_o(16)
//
//
//
module cf_fft_256_8 (clock_c, enable_i, reset_i, sync_i, data_0_i, data_1_i, sync_o, data_0_o, data_1_o);
input clock_c;
input enable_i;
input reset_i;
input sync_i;
input [15:0] data_0_i;
input [15:0] data_1_i;
output sync_o;
output [15:0] data_0_o;
output [15:0] data_1_o;
wire [6:0] n4;
wire [6:0] n7;
wire n8;
wire [6:0] n12;
wire n13;
wire [1:0] n14;
wire n15;
wire [2:0] n17;
wire n18;
wire n19;
wire n27;
wire [31:0] n28;
wire n29;
wire n30;
wire [5:0] n31;
wire [5:0] n32;
wire [5:0] n33;
wire [5:0] n36;
wire [1:0] n41;
wire n42;
wire n43;
wire n47;
wire n53;
wire [1:0] n54;
wire [2:0] n55;
wire [3:0] n56;
wire [4:0] n57;
wire [5:0] n58;
wire n59;
wire n60;
wire n65;
wire [31:0] n73;
wire [5:0] n75;
wire [1:0] n80;
wire n81;
wire n82;
wire n86;
wire n98;
wire n102;
wire [31:0] n110;
wire [1:0] n111;
wire [2:0] n113;
wire n114;
wire n115;
wire [15:0] n119;
wire [15:0] n120;
wire [15:0] n121;
wire [15:0] n122;
wire [15:0] n123;
wire [15:0] n124;
wire [6:0] n126;
wire n130;
wire [1:0] n131;
wire [2:0] n133;
wire n134;
wire n135;
wire n143;
wire [7:0] n149;
wire [7:0] n150;
wire [7:0] n155;
wire [7:0] n156;
wire [7:0] n177;
wire [7:0] n178;
wire [15:0] n179;
wire [7:0] n180;
wire [15:0] n185;
wire [7:0] n186;
wire [7:0] n191;
wire [15:0] n196;
wire [7:0] n197;
wire [15:0] n202;
wire [7:0] n203;
wire [7:0] n208;
wire [7:0] n213;
wire [7:0] n214;
wire [15:0] n215;
wire [7:0] n220;
wire [7:0] n221;
wire [15:0] n222;
wire [31:0] n227;
wire [5:0] n244;
wire n261;
wire n278;
wire [5:0] n280;
wire [1:0] n285;
wire n286;
wire n287;
wire n291;
wire n296;
wire [1:0] n297;
wire [2:0] n298;
wire [3:0] n299;
wire [4:0] n300;
wire [5:0] n301;
wire n302;
wire n303;
wire n307;
wire [31:0] n315;
wire [5:0] n317;
wire [1:0] n322;
wire n323;
wire n324;
wire n328;
wire n340;
wire n344;
wire [31:0] n352;
wire [1:0] n353;
wire [2:0] n355;
wire n356;
wire n357;
wire [15:0] n361;
wire [15:0] n362;
wire [15:0] n363;
wire [15:0] n364;
wire [15:0] n365;
wire [15:0] n366;
wire [6:0] n368;
wire n372;
wire [1:0] n373;
wire [2:0] n375;
wire n376;
wire n377;
wire n385;
wire n386;
wire [7:0] n391;
wire [7:0] n392;
wire [7:0] n397;
wire [7:0] n398;
wire [7:0] n418;
wire [7:0] n419;
wire [15:0] n420;
wire [7:0] n421;
wire [15:0] n426;
wire [7:0] n427;
wire [7:0] n432;
wire [15:0] n437;
wire [7:0] n438;
wire [15:0] n443;
wire [7:0] n444;
wire [7:0] n449;
wire [7:0] n454;
wire [7:0] n455;
wire [15:0] n456;
wire [7:0] n461;
wire [7:0] n462;
wire [15:0] n463;
wire [31:0] n468;
wire [5:0] n485;
wire n502;
wire n519;
wire [5:0] n521;
wire [1:0] n526;
wire n527;
wire n528;
wire n532;
wire n537;
wire [1:0] n538;
wire [2:0] n539;
wire [3:0] n540;
wire [4:0] n541;
wire [5:0] n542;
wire n543;
wire n544;
wire n548;
wire [31:0] n556;
wire [5:0] n558;
wire [1:0] n563;
wire n564;
wire n565;
wire n569;
wire n581;
wire n585;
wire [31:0] n593;
wire [1:0] n594;
wire [2:0] n596;
wire n597;
wire n598;
wire [15:0] n602;
wire [15:0] n603;
wire [15:0] n604;
wire [15:0] n605;
wire [15:0] n606;
wire [15:0] n607;
wire [6:0] n609;
wire n613;
wire [1:0] n614;
wire [2:0] n616;
wire n617;
wire n618;
wire n626;
wire [1:0] n627;
wire [7:0] n632;
wire [7:0] n633;
wire [7:0] n638;
wire [7:0] n639;
wire [7:0] n659;
wire [7:0] n660;
wire [15:0] n661;
wire [7:0] n662;
wire [15:0] n667;
wire [7:0] n668;
wire [7:0] n673;
wire [15:0] n678;
wire [7:0] n679;
wire [15:0] n684;
wire [7:0] n685;
wire [7:0] n690;
wire [7:0] n695;
wire [7:0] n696;
wire [15:0] n697;
wire [7:0] n702;
wire [7:0] n703;
wire [15:0] n704;
wire [31:0] n709;
wire [5:0] n726;
wire n743;
wire n760;
wire [5:0] n762;
wire [1:0] n767;
wire n768;
wire n769;
wire n773;
wire n778;
wire [1:0] n779;
wire [2:0] n780;
wire [3:0] n781;
wire [4:0] n782;
wire [5:0] n783;
wire n784;
wire n785;
wire n789;
wire [31:0] n797;
wire [5:0] n799;
wire [1:0] n804;
wire n805;
wire n806;
wire n810;
wire n822;
wire n826;
wire [31:0] n834;
wire [1:0] n835;
wire [2:0] n837;
wire n838;
wire n839;
wire [15:0] n843;
wire [15:0] n844;
wire [15:0] n845;
wire [15:0] n846;
wire [15:0] n847;
wire [15:0] n848;
wire [6:0] n850;
wire n854;
wire [1:0] n855;
wire [2:0] n857;
wire n858;
wire n859;
wire n867;
wire [2:0] n868;
wire [7:0] n873;
wire [7:0] n874;
wire [7:0] n879;
wire [7:0] n880;
wire [7:0] n900;
wire [7:0] n901;
wire [15:0] n902;
wire [7:0] n903;
wire [15:0] n908;
wire [7:0] n909;
wire [7:0] n914;
wire [15:0] n919;
wire [7:0] n920;
wire [15:0] n925;
wire [7:0] n926;
wire [7:0] n931;
wire [7:0] n936;
wire [7:0] n937;
wire [15:0] n938;
wire [7:0] n943;
wire [7:0] n944;
wire [15:0] n945;
wire [31:0] n950;
wire [5:0] n967;
wire n984;
wire n1001;
wire [5:0] n1003;
wire [1:0] n1008;
wire n1009;
wire n1010;
wire n1014;
wire n1019;
wire [1:0] n1020;
wire [2:0] n1021;
wire [3:0] n1022;
wire [4:0] n1023;
wire [5:0] n1024;
wire n1025;
wire n1026;
wire n1030;
wire [31:0] n1038;
wire [5:0] n1040;
wire [1:0] n1045;
wire n1046;
wire n1047;
wire n1051;
wire n1063;
wire n1067;
wire [31:0] n1075;
wire [1:0] n1076;
wire [2:0] n1078;
wire n1079;
wire n1080;
wire [15:0] n1084;
wire [15:0] n1085;
wire [15:0] n1086;
wire [15:0] n1087;
wire [15:0] n1088;
wire [15:0] n1089;
wire [6:0] n1091;
wire n1095;
wire [1:0] n1096;
wire [2:0] n1098;
wire n1099;
wire n1100;
wire n1108;
wire [3:0] n1109;
wire [7:0] n1114;
wire [7:0] n1115;
wire [7:0] n1120;
wire [7:0] n1121;
wire [7:0] n1141;
wire [7:0] n1142;
wire [15:0] n1143;
wire [7:0] n1144;
wire [15:0] n1149;
wire [7:0] n1150;
wire [7:0] n1155;
wire [15:0] n1160;
wire [7:0] n1161;
wire [15:0] n1166;
wire [7:0] n1167;
wire [7:0] n1172;
wire [7:0] n1177;
wire [7:0] n1178;
wire [15:0] n1179;
wire [7:0] n1184;
wire [7:0] n1185;
wire [15:0] n1186;
wire [31:0] n1191;
wire [5:0] n1208;
wire n1225;
wire n1242;
wire [5:0] n1244;
wire [1:0] n1249;
wire n1250;
wire n1251;
wire n1255;
wire n1260;
wire [1:0] n1261;
wire [2:0] n1262;
wire [3:0] n1263;
wire [4:0] n1264;
wire [5:0] n1265;
wire n1266;
wire n1267;
wire n1271;
wire [31:0] n1279;
wire [5:0] n1281;
wire [1:0] n1286;
wire n1287;
wire n1288;
wire n1292;
wire n1304;
wire n1308;
wire [31:0] n1316;
wire [1:0] n1317;
wire [2:0] n1319;
wire n1320;
wire n1321;
wire [15:0] n1325;
wire [15:0] n1326;
wire [15:0] n1327;
wire [15:0] n1328;
wire [15:0] n1329;
wire [15:0] n1330;
wire [6:0] n1332;
wire n1336;
wire [1:0] n1337;
wire [2:0] n1339;
wire n1340;
wire n1341;
wire n1349;
wire [4:0] n1350;
wire [7:0] n1355;
wire [7:0] n1356;
wire [7:0] n1361;
wire [7:0] n1362;
wire [7:0] n1382;
wire [7:0] n1383;
wire [15:0] n1384;
wire [7:0] n1385;
wire [15:0] n1390;
wire [7:0] n1391;
wire [7:0] n1396;
wire [15:0] n1401;
wire [7:0] n1402;
wire [15:0] n1407;
wire [7:0] n1408;
wire [7:0] n1413;
wire [7:0] n1418;
wire [7:0] n1419;
wire [15:0] n1420;
wire [7:0] n1425;
wire [7:0] n1426;
wire [15:0] n1427;
wire [31:0] n1432;
wire [5:0] n1449;
wire n1466;
wire n1483;
wire [5:0] n1485;
wire [1:0] n1490;
wire n1491;
wire n1492;
wire n1496;
wire n1501;
wire [1:0] n1502;
wire [2:0] n1503;
wire [3:0] n1504;
wire [4:0] n1505;
wire [5:0] n1506;
wire n1507;
wire n1508;
wire n1512;
wire [31:0] n1520;
wire [5:0] n1522;
wire [1:0] n1527;
wire n1528;
wire n1529;
wire n1533;
wire n1545;
wire n1549;
wire [31:0] n1557;
wire [1:0] n1558;
wire [2:0] n1560;
wire n1561;
wire n1562;
wire [15:0] n1566;
wire [15:0] n1567;
wire [15:0] n1568;
wire [15:0] n1569;
wire [15:0] n1570;
wire [15:0] n1571;
wire [6:0] n1573;
wire n1577;
wire [1:0] n1578;
wire [2:0] n1580;
wire n1581;
wire n1582;
wire n1590;
wire [5:0] n1591;
wire [7:0] n1596;
wire [7:0] n1597;
wire [7:0] n1602;
wire [7:0] n1603;
wire [7:0] n1623;
wire [7:0] n1624;
wire [15:0] n1625;
wire [7:0] n1626;
wire [15:0] n1631;
wire [7:0] n1632;
wire [7:0] n1637;
wire [15:0] n1642;
wire [7:0] n1643;
wire [15:0] n1648;
wire [7:0] n1649;
wire [7:0] n1654;
wire [7:0] n1659;
wire [7:0] n1660;
wire [15:0] n1661;
wire [7:0] n1666;
wire [7:0] n1667;
wire [15:0] n1668;
wire [31:0] n1673;
wire [5:0] n1690;
wire n1707;
wire n1724;
wire [5:0] n1726;
wire [1:0] n1731;
wire n1732;
wire n1733;
wire n1737;
wire n1742;
wire [1:0] n1743;
wire [2:0] n1744;
wire [3:0] n1745;
wire [4:0] n1746;
wire [5:0] n1747;
wire n1748;
wire n1749;
wire n1753;
wire [31:0] n1761;
wire [5:0] n1763;
wire [1:0] n1768;
wire n1769;
wire n1770;
wire n1774;
wire n1786;
wire n1790;
wire [31:0] n1798;
wire [1:0] n1799;
wire [2:0] n1801;
wire n1802;
wire n1803;
wire [15:0] n1807;
wire [15:0] n1808;
wire [15:0] n1809;
wire [15:0] n1810;
wire [15:0] n1811;
wire [15:0] n1812;
wire [6:0] n1814;
wire n1818;
wire [1:0] n1819;
wire [2:0] n1821;
wire n1822;
wire n1823;
wire n1831;
wire [6:0] n1832;
wire [7:0] n1837;
wire [7:0] n1838;
wire [7:0] n1843;
wire [7:0] n1844;
wire [7:0] n1864;
wire [7:0] n1865;
wire [15:0] n1866;
wire [7:0] n1867;
wire [15:0] n1872;
wire [7:0] n1873;
wire [7:0] n1878;
wire [15:0] n1883;
wire [7:0] n1884;
wire [15:0] n1889;
wire [7:0] n1890;
wire [7:0] n1895;
wire [7:0] n1900;
wire [7:0] n1901;
wire [15:0] n1902;
wire [7:0] n1907;
wire [7:0] n1908;
wire [15:0] n1909;
wire [31:0] n1914;
wire [5:0] n1931;
wire n1948;
wire n1965;
wire [5:0] n1967;
wire [1:0] n1972;
wire n1973;
wire n1974;
wire n1978;
wire n1983;
wire [1:0] n1984;
wire [2:0] n1985;
wire [3:0] n1986;
wire [4:0] n1987;
wire [5:0] n1988;
wire n1989;
wire n1990;
wire n1994;
wire [31:0] n2002;
wire [5:0] n2004;
wire [1:0] n2009;
wire n2010;
wire n2011;
wire n2015;
wire n2027;
wire n2031;
wire [31:0] n2039;
wire [1:0] n2040;
wire [2:0] n2042;
wire n2043;
wire n2044;
wire [15:0] n2048;
wire [15:0] n2049;
wire [15:0] n2050;
wire [15:0] n2051;
wire [15:0] n2052;
wire [15:0] n2053;
wire n2059;
wire n2060;
wire n2061;
wire n2062;
wire n2063;
wire n2064;
wire n2065;
wire n2066;
wire n2067;
wire n2068;
wire n2069;
wire n2070;
wire n2071;
wire n2072;
wire n2073;
wire n2074;
wire n2075;
wire n2076;
wire n2077;
wire n2078;
wire n2079;
wire n2080;
wire n2081;
wire n2082;
wire n2083;
wire n2084;
wire n2085;
wire n2086;
wire n2087;
wire n2088;
wire n2089;
wire n2090;
wire n2091;
wire n2092;
wire n2093;
wire n2094;
wire n2095;
wire n2096;
wire n2097;
wire n2098;
wire n2099;
wire n2100;
wire n2101;
wire n2102;
wire n2103;
wire n2104;
wire n2105;
wire n2106;
wire n2107;
wire n2108;
wire n2109;
wire n2110;
wire n2111;
wire n2112;
wire n2113;
wire n2114;
wire n2115;
wire n2116;
reg [6:0] n11;
reg n22;
reg n26;
reg [5:0] n39;
reg n46;
reg n51;
wire [31:0] n64;
reg [5:0] n64ra;
reg [31:0] n64m ;
wire [31:0] n68;
reg [5:0] n68ra;
reg [31:0] n68m ;
reg n72;
reg [5:0] n78;
reg n85;
wire [31:0] n101;
reg [5:0] n101ra;
reg [31:0] n101m ;
wire [31:0] n105;
reg [5:0] n105ra;
reg [31:0] n105m ;
reg n109;
reg n118;
reg [6:0] n129;
reg n138;
reg n142;
reg [15:0] n148;
reg [15:0] n154;
reg [7:0] n161;
reg [7:0] n165;
reg [7:0] n169;
reg [7:0] n173;
reg [15:0] n176;
reg [7:0] n184;
reg [7:0] n190;
reg [7:0] n195;
reg [7:0] n201;
reg [7:0] n207;
reg [7:0] n212;
reg [15:0] n219;
reg [15:0] n226;
reg n231;
reg n235;
reg n239;
reg n243;
reg [5:0] n248;
reg [5:0] n252;
reg [5:0] n256;
reg [5:0] n260;
reg n265;
reg n269;
reg n273;
reg n277;
reg [5:0] n283;
reg n290;
reg n295;
wire [31:0] n306;
reg [5:0] n306ra;
reg [31:0] n306m ;
wire [31:0] n310;
reg [5:0] n310ra;
reg [31:0] n310m ;
reg n314;
reg [5:0] n320;
reg n327;
wire [31:0] n343;
reg [5:0] n343ra;
reg [31:0] n343m ;
wire [31:0] n347;
reg [5:0] n347ra;
reg [31:0] n347m ;
reg n351;
reg n360;
reg [6:0] n371;
reg n380;
reg n384;
reg [15:0] n390;
reg [15:0] n396;
reg [7:0] n402;
reg [7:0] n406;
reg [7:0] n410;
reg [7:0] n414;
reg [15:0] n417;
reg [7:0] n425;
reg [7:0] n431;
reg [7:0] n436;
reg [7:0] n442;
reg [7:0] n448;
reg [7:0] n453;
reg [15:0] n460;
reg [15:0] n467;
reg n472;
reg n476;
reg n480;
reg n484;
reg [5:0] n489;
reg [5:0] n493;
reg [5:0] n497;
reg [5:0] n501;
reg n506;
reg n510;
reg n514;
reg n518;
reg [5:0] n524;
reg n531;
reg n536;
wire [31:0] n547;
reg [5:0] n547ra;
reg [31:0] n547m ;
wire [31:0] n551;
reg [5:0] n551ra;
reg [31:0] n551m ;
reg n555;
reg [5:0] n561;
reg n568;
wire [31:0] n584;
reg [5:0] n584ra;
reg [31:0] n584m ;
wire [31:0] n588;
reg [5:0] n588ra;
reg [31:0] n588m ;
reg n592;
reg n601;
reg [6:0] n612;
reg n621;
reg n625;
reg [15:0] n631;
reg [15:0] n637;
reg [7:0] n643;
reg [7:0] n647;
reg [7:0] n651;
reg [7:0] n655;
reg [15:0] n658;
reg [7:0] n666;
reg [7:0] n672;
reg [7:0] n677;
reg [7:0] n683;
reg [7:0] n689;
reg [7:0] n694;
reg [15:0] n701;
reg [15:0] n708;
reg n713;
reg n717;
reg n721;
reg n725;
reg [5:0] n730;
reg [5:0] n734;
reg [5:0] n738;
reg [5:0] n742;
reg n747;
reg n751;
reg n755;
reg n759;
reg [5:0] n765;
reg n772;
reg n777;
wire [31:0] n788;
reg [5:0] n788ra;
reg [31:0] n788m ;
wire [31:0] n792;
reg [5:0] n792ra;
reg [31:0] n792m ;
reg n796;
reg [5:0] n802;
reg n809;
wire [31:0] n825;
reg [5:0] n825ra;
reg [31:0] n825m ;
wire [31:0] n829;
reg [5:0] n829ra;
reg [31:0] n829m ;
reg n833;
reg n842;
reg [6:0] n853;
reg n862;
reg n866;
reg [15:0] n872;
reg [15:0] n878;
reg [7:0] n884;
reg [7:0] n888;
reg [7:0] n892;
reg [7:0] n896;
reg [15:0] n899;
reg [7:0] n907;
reg [7:0] n913;
reg [7:0] n918;
reg [7:0] n924;
reg [7:0] n930;
reg [7:0] n935;
reg [15:0] n942;
reg [15:0] n949;
reg n954;
reg n958;
reg n962;
reg n966;
reg [5:0] n971;
reg [5:0] n975;
reg [5:0] n979;
reg [5:0] n983;
reg n988;
reg n992;
reg n996;
reg n1000;
reg [5:0] n1006;
reg n1013;
reg n1018;
wire [31:0] n1029;
reg [5:0] n1029ra;
reg [31:0] n1029m ;
wire [31:0] n1033;
reg [5:0] n1033ra;
reg [31:0] n1033m ;
reg n1037;
reg [5:0] n1043;
reg n1050;
wire [31:0] n1066;
reg [5:0] n1066ra;
reg [31:0] n1066m ;
wire [31:0] n1070;
reg [5:0] n1070ra;
reg [31:0] n1070m ;
reg n1074;
reg n1083;
reg [6:0] n1094;
reg n1103;
reg n1107;
reg [15:0] n1113;
reg [15:0] n1119;
reg [7:0] n1125;
reg [7:0] n1129;
reg [7:0] n1133;
reg [7:0] n1137;
reg [15:0] n1140;
reg [7:0] n1148;
reg [7:0] n1154;
reg [7:0] n1159;
reg [7:0] n1165;
reg [7:0] n1171;
reg [7:0] n1176;
reg [15:0] n1183;
reg [15:0] n1190;
reg n1195;
reg n1199;
reg n1203;
reg n1207;
reg [5:0] n1212;
reg [5:0] n1216;
reg [5:0] n1220;
reg [5:0] n1224;
reg n1229;
reg n1233;
reg n1237;
reg n1241;
reg [5:0] n1247;
reg n1254;
reg n1259;
wire [31:0] n1270;
reg [5:0] n1270ra;
reg [31:0] n1270m ;
wire [31:0] n1274;
reg [5:0] n1274ra;
reg [31:0] n1274m ;
reg n1278;
reg [5:0] n1284;
reg n1291;
wire [31:0] n1307;
reg [5:0] n1307ra;
reg [31:0] n1307m ;
wire [31:0] n1311;
reg [5:0] n1311ra;
reg [31:0] n1311m ;
reg n1315;
reg n1324;
reg [6:0] n1335;
reg n1344;
reg n1348;
reg [15:0] n1354;
reg [15:0] n1360;
reg [7:0] n1366;
reg [7:0] n1370;
reg [7:0] n1374;
reg [7:0] n1378;
reg [15:0] n1381;
reg [7:0] n1389;
reg [7:0] n1395;
reg [7:0] n1400;
reg [7:0] n1406;
reg [7:0] n1412;
reg [7:0] n1417;
reg [15:0] n1424;
reg [15:0] n1431;
reg n1436;
reg n1440;
reg n1444;
reg n1448;
reg [5:0] n1453;
reg [5:0] n1457;
reg [5:0] n1461;
reg [5:0] n1465;
reg n1470;
reg n1474;
reg n1478;
reg n1482;
reg [5:0] n1488;
reg n1495;
reg n1500;
wire [31:0] n1511;
reg [5:0] n1511ra;
reg [31:0] n1511m ;
wire [31:0] n1515;
reg [5:0] n1515ra;
reg [31:0] n1515m ;
reg n1519;
reg [5:0] n1525;
reg n1532;
wire [31:0] n1548;
reg [5:0] n1548ra;
reg [31:0] n1548m ;
wire [31:0] n1552;
reg [5:0] n1552ra;
reg [31:0] n1552m ;
reg n1556;
reg n1565;
reg [6:0] n1576;
reg n1585;
reg n1589;
reg [15:0] n1595;
reg [15:0] n1601;
reg [7:0] n1607;
reg [7:0] n1611;
reg [7:0] n1615;
reg [7:0] n1619;
reg [15:0] n1622;
reg [7:0] n1630;
reg [7:0] n1636;
reg [7:0] n1641;
reg [7:0] n1647;
reg [7:0] n1653;
reg [7:0] n1658;
reg [15:0] n1665;
reg [15:0] n1672;
reg n1677;
reg n1681;
reg n1685;
reg n1689;
reg [5:0] n1694;
reg [5:0] n1698;
reg [5:0] n1702;
reg [5:0] n1706;
reg n1711;
reg n1715;
reg n1719;
reg n1723;
reg [5:0] n1729;
reg n1736;
reg n1741;
wire [31:0] n1752;
reg [5:0] n1752ra;
reg [31:0] n1752m ;
wire [31:0] n1756;
reg [5:0] n1756ra;
reg [31:0] n1756m ;
reg n1760;
reg [5:0] n1766;
reg n1773;
wire [31:0] n1789;
reg [5:0] n1789ra;
reg [31:0] n1789m ;
wire [31:0] n1793;
reg [5:0] n1793ra;
reg [31:0] n1793m ;
reg n1797;
reg n1806;
reg [6:0] n1817;
reg n1826;
reg n1830;
reg [15:0] n1836;
reg [15:0] n1842;
reg [7:0] n1848;
reg [7:0] n1852;
reg [7:0] n1856;
reg [7:0] n1860;
reg [15:0] n1863;
reg [7:0] n1871;
reg [7:0] n1877;
reg [7:0] n1882;
reg [7:0] n1888;
reg [7:0] n1894;
reg [7:0] n1899;
reg [15:0] n1906;
reg [15:0] n1913;
reg n1918;
reg n1922;
reg n1926;
reg n1930;
reg [5:0] n1935;
reg [5:0] n1939;
reg [5:0] n1943;
reg [5:0] n1947;
reg n1952;
reg n1956;
reg n1960;
reg n1964;
reg [5:0] n1970;
reg n1977;
reg n1982;
wire [31:0] n1993;
reg [5:0] n1993ra;
reg [31:0] n1993m ;
wire [31:0] n1997;
reg [5:0] n1997ra;
reg [31:0] n1997m ;
reg n2001;
reg [5:0] n2007;
reg n2014;
wire [31:0] n2030;
reg [5:0] n2030ra;
reg [31:0] n2030m ;
wire [31:0] n2034;
reg [5:0] n2034ra;
reg [31:0] n2034m ;
reg n2038;
reg n2047;
assign n4 = 7'b0000001;
assign n7 = n11 + n4;
assign n8 = 1'b0;
assign n12 = 7'b1111111;
assign n13 = n11 == n12;
assign n14 = {sync_i, n13};
assign n15 = 1'b1;
assign n17 = {n14, n22};
assign n18 =
n17 == 3'b000 ? n8 :
n17 == 3'b010 ? n8 :
n17 == 3'b100 ? n15 :
n17 == 3'b110 ? n15 :
n17 == 3'b001 ? n15 :
n17 == 3'b011 ? n8 :
n17 == 3'b101 ? n15 :
n15;
assign n19 =
n17 == 3'b000 ? n8 :
n17 == 3'b010 ? n8 :
n17 == 3'b100 ? n15 :
n17 == 3'b110 ? n15 :
n17 == 3'b001 ? n15 :
n17 == 3'b011 ? n8 :
n17 == 3'b101 ? n15 :
n15;
assign n27 = n26 & n13;
assign n28 = {data_0_i, data_1_i};
assign n29 = n11[6];
assign n30 = ~n29;
assign n31 = {n11[5],
n11[4],
n11[3],
n11[2],
n11[1],
n11[0]};
assign n32 = {n31[0],
n31[1],
n31[2],
n31[3],
n31[4],
n31[5]};
assign n33 = 6'b000001;
assign n36 = n39 + n33;
assign n41 = {n27, n46};
assign n42 =
n41 == 2'b00 ? n8 :
n41 == 2'b10 ? n8 :
n41 == 2'b01 ? n15 :
n15;
assign n43 =
n41 == 2'b00 ? n8 :
n41 == 2'b10 ? n15 :
n41 == 2'b01 ? n15 :
n8;
assign n47 = ~n42;
assign n53 = n8;
assign n54 = {n8, n53};
assign n55 = {n8, n54};
assign n56 = {n8, n55};
assign n57 = {n8, n56};
assign n58 = {n8, n57};
assign n59 = n39 == n58;
assign n60 = n30 & n47;
assign n65 = n30 & n42;
assign n73 =
n72 == 1'b0 ? n64 :
n68;
assign n75 = n78 + n33;
assign n80 = {n27, n85};
assign n81 =
n80 == 2'b00 ? n8 :
n80 == 2'b10 ? n8 :
n80 == 2'b01 ? n15 :
n15;
assign n82 =
n80 == 2'b00 ? n8 :
n80 == 2'b10 ? n15 :
n80 == 2'b01 ? n15 :
n8;
assign n86 = ~n81;
assign n98 = n29 & n86;
assign n102 = n29 & n81;
assign n110 =
n109 == 1'b0 ? n101 :
n105;
assign n111 = {n59, n51};
assign n113 = {n111, n118};
assign n114 =
n113 == 3'b000 ? n8 :
n113 == 3'b010 ? n8 :
n113 == 3'b100 ? n8 :
n113 == 3'b110 ? n8 :
n113 == 3'b001 ? n15 :
n113 == 3'b011 ? n15 :
n113 == 3'b101 ? n15 :
n15;
assign n115 =
n113 == 3'b000 ? n8 :
n113 == 3'b010 ? n8 :
n113 == 3'b100 ? n15 :
n113 == 3'b110 ? n8 :
n113 == 3'b001 ? n15 :
n113 == 3'b011 ? n8 :
n113 == 3'b101 ? n15 :
n8;
assign n119 = {n73[31],
n73[30],
n73[29],
n73[28],
n73[27],
n73[26],
n73[25],
n73[24],
n73[23],
n73[22],
n73[21],
n73[20],
n73[19],
n73[18],
n73[17],
n73[16]};
assign n120 = {n73[15],
n73[14],
n73[13],
n73[12],
n73[11],
n73[10],
n73[9],
n73[8],
n73[7],
n73[6],
n73[5],
n73[4],
n73[3],
n73[2],
n73[1],
n73[0]};
assign n121 = {n110[31],
n110[30],
n110[29],
n110[28],
n110[27],
n110[26],
n110[25],
n110[24],
n110[23],
n110[22],
n110[21],
n110[20],
n110[19],
n110[18],
n110[17],
n110[16]};
assign n122 = {n110[15],
n110[14],
n110[13],
n110[12],
n110[11],
n110[10],
n110[9],
n110[8],
n110[7],
n110[6],
n110[5],
n110[4],
n110[3],
n110[2],
n110[1],
n110[0]};
assign n123 =
n114 == 1'b0 ? n119 :
n120;
assign n124 =
n114 == 1'b0 ? n121 :
n122;
assign n126 = n129 + n4;
assign n130 = n129 == n12;
assign n131 = {n51, n130};
assign n133 = {n131, n138};
assign n134 =
n133 == 3'b000 ? n8 :
n133 == 3'b010 ? n8 :
n133 == 3'b100 ? n15 :
n133 == 3'b110 ? n15 :
n133 == 3'b001 ? n15 :
n133 == 3'b011 ? n8 :
n133 == 3'b101 ? n15 :
n15;
assign n135 =
n133 == 3'b000 ? n8 :
n133 == 3'b010 ? n8 :
n133 == 3'b100 ? n15 :
n133 == 3'b110 ? n15 :
n133 == 3'b001 ? n15 :
n133 == 3'b011 ? n8 :
n133 == 3'b101 ? n15 :
n15;
assign n143 = n142 & n130;
assign n149 = {n148[15],
n148[14],
n148[13],
n148[12],
n148[11],
n148[10],
n148[9],
n148[8]};
assign n150 = {n148[7],
n148[6],
n148[5],
n148[4],
n148[3],
n148[2],
n148[1],
n148[0]};
assign n155 = {n154[15],
n154[14],
n154[13],
n154[12],
n154[11],
n154[10],
n154[9],
n154[8]};
assign n156 = {n154[7],
n154[6],
n154[5],
n154[4],
n154[3],
n154[2],
n154[1],
n154[0]};
assign n177 = {n176[15],
n176[14],
n176[13],
n176[12],
n176[11],
n176[10],
n176[9],
n176[8]};
assign n178 = {n176[7],
n176[6],
n176[5],
n176[4],
n176[3],
n176[2],
n176[1],
n176[0]};
assign n179 = {n155} * {n177};
assign n180 = {n179[14],
n179[13],
n179[12],
n179[11],
n179[10],
n179[9],
n179[8],
n179[7]};
assign n185 = {n156} * {n178};
assign n186 = {n185[14],
n185[13],
n185[12],
n185[11],
n185[10],
n185[9],
n185[8],
n185[7]};
assign n191 = n184 - n190;
assign n196 = {n155} * {n178};
assign n197 = {n196[14],
n196[13],
n196[12],
n196[11],
n196[10],
n196[9],
n196[8],
n196[7]};
assign n202 = {n156} * {n177};
assign n203 = {n202[14],
n202[13],
n202[12],
n202[11],
n202[10],
n202[9],
n202[8],
n202[7]};
assign n208 = n201 + n207;
assign n213 = n165 + n195;
assign n214 = n173 + n212;
assign n215 = {n213, n214};
assign n220 = n165 - n195;
assign n221 = n173 - n212;
assign n222 = {n220, n221};
assign n227 = {n219, n226};
assign n244 = {n129[6],
n129[5],
n129[4],
n129[3],
n129[2],
n129[1]};
assign n261 = n129[0];
assign n278 = ~n277;
assign n280 = n283 + n33;
assign n285 = {n243, n290};
assign n286 =
n285 == 2'b00 ? n8 :
n285 == 2'b10 ? n8 :
n285 == 2'b01 ? n15 :
n15;
assign n287 =
n285 == 2'b00 ? n8 :
n285 == 2'b10 ? n15 :
n285 == 2'b01 ? n15 :
n8;
assign n291 = ~n286;
assign n296 = n8;
assign n297 = {n8, n296};
assign n298 = {n8, n297};
assign n299 = {n8, n298};
assign n300 = {n8, n299};
assign n301 = {n8, n300};
assign n302 = n283 == n301;
assign n303 = n278 & n291;
assign n307 = n278 & n286;
assign n315 =
n314 == 1'b0 ? n306 :
n310;
assign n317 = n320 + n33;
assign n322 = {n243, n327};
assign n323 =
n322 == 2'b00 ? n8 :
n322 == 2'b10 ? n8 :
n322 == 2'b01 ? n15 :
n15;
assign n324 =
n322 == 2'b00 ? n8 :
n322 == 2'b10 ? n15 :
n322 == 2'b01 ? n15 :
n8;
assign n328 = ~n323;
assign n340 = n277 & n328;
assign n344 = n277 & n323;
assign n352 =
n351 == 1'b0 ? n343 :
n347;
assign n353 = {n302, n295};
assign n355 = {n353, n360};
assign n356 =
n355 == 3'b000 ? n8 :
n355 == 3'b010 ? n8 :
n355 == 3'b100 ? n8 :
n355 == 3'b110 ? n8 :
n355 == 3'b001 ? n15 :
n355 == 3'b011 ? n15 :
n355 == 3'b101 ? n15 :
n15;
assign n357 =
n355 == 3'b000 ? n8 :
n355 == 3'b010 ? n8 :
n355 == 3'b100 ? n15 :
n355 == 3'b110 ? n8 :
n355 == 3'b001 ? n15 :
n355 == 3'b011 ? n8 :
n355 == 3'b101 ? n15 :
n8;
assign n361 = {n315[31],
n315[30],
n315[29],
n315[28],
n315[27],
n315[26],
n315[25],
n315[24],
n315[23],
n315[22],
n315[21],
n315[20],
n315[19],
n315[18],
n315[17],
n315[16]};
assign n362 = {n315[15],
n315[14],
n315[13],
n315[12],
n315[11],
n315[10],
n315[9],
n315[8],
n315[7],
n315[6],
n315[5],
n315[4],
n315[3],
n315[2],
n315[1],
n315[0]};
assign n363 = {n352[31],
n352[30],
n352[29],
n352[28],
n352[27],
n352[26],
n352[25],
n352[24],
n352[23],
n352[22],
n352[21],
n352[20],
n352[19],
n352[18],
n352[17],
n352[16]};
assign n364 = {n352[15],
n352[14],
n352[13],
n352[12],
n352[11],
n352[10],
n352[9],
n352[8],
n352[7],
n352[6],
n352[5],
n352[4],
n352[3],
n352[2],
n352[1],
n352[0]};
assign n365 =
n356 == 1'b0 ? n361 :
n362;
assign n366 =
n356 == 1'b0 ? n363 :
n364;
assign n368 = n371 + n4;
assign n372 = n371 == n12;
assign n373 = {n295, n372};
assign n375 = {n373, n380};
assign n376 =
n375 == 3'b000 ? n8 :
n375 == 3'b010 ? n8 :
n375 == 3'b100 ? n15 :
n375 == 3'b110 ? n15 :
n375 == 3'b001 ? n15 :
n375 == 3'b011 ? n8 :
n375 == 3'b101 ? n15 :
n15;
assign n377 =
n375 == 3'b000 ? n8 :
n375 == 3'b010 ? n8 :
n375 == 3'b100 ? n15 :
n375 == 3'b110 ? n15 :
n375 == 3'b001 ? n15 :
n375 == 3'b011 ? n8 :
n375 == 3'b101 ? n15 :
n15;
assign n385 = n384 & n372;
assign n386 = n371[6];
assign n391 = {n390[15],
n390[14],
n390[13],
n390[12],
n390[11],
n390[10],
n390[9],
n390[8]};
assign n392 = {n390[7],
n390[6],
n390[5],
n390[4],
n390[3],
n390[2],
n390[1],
n390[0]};
assign n397 = {n396[15],
n396[14],
n396[13],
n396[12],
n396[11],
n396[10],
n396[9],
n396[8]};
assign n398 = {n396[7],
n396[6],
n396[5],
n396[4],
n396[3],
n396[2],
n396[1],
n396[0]};
assign n418 = {n417[15],
n417[14],
n417[13],
n417[12],
n417[11],
n417[10],
n417[9],
n417[8]};
assign n419 = {n417[7],
n417[6],
n417[5],
n417[4],
n417[3],
n417[2],
n417[1],
n417[0]};
assign n420 = {n397} * {n418};
assign n421 = {n420[14],
n420[13],
n420[12],
n420[11],
n420[10],
n420[9],
n420[8],
n420[7]};
assign n426 = {n398} * {n419};
assign n427 = {n426[14],
n426[13],
n426[12],
n426[11],
n426[10],
n426[9],
n426[8],
n426[7]};
assign n432 = n425 - n431;
assign n437 = {n397} * {n419};
assign n438 = {n437[14],
n437[13],
n437[12],
n437[11],
n437[10],
n437[9],
n437[8],
n437[7]};
assign n443 = {n398} * {n418};
assign n444 = {n443[14],
n443[13],
n443[12],
n443[11],
n443[10],
n443[9],
n443[8],
n443[7]};
assign n449 = n442 + n448;
assign n454 = n406 + n436;
assign n455 = n414 + n453;
assign n456 = {n454, n455};
assign n461 = n406 - n436;
assign n462 = n414 - n453;
assign n463 = {n461, n462};
assign n468 = {n460, n467};
assign n485 = {n371[6],
n371[5],
n371[4],
n371[3],
n371[2],
n371[1]};
assign n502 = n371[0];
assign n519 = ~n518;
assign n521 = n524 + n33;
assign n526 = {n484, n531};
assign n527 =
n526 == 2'b00 ? n8 :
n526 == 2'b10 ? n8 :
n526 == 2'b01 ? n15 :
n15;
assign n528 =
n526 == 2'b00 ? n8 :
n526 == 2'b10 ? n15 :
n526 == 2'b01 ? n15 :
n8;
assign n532 = ~n527;
assign n537 = n8;
assign n538 = {n8, n537};
assign n539 = {n8, n538};
assign n540 = {n8, n539};
assign n541 = {n8, n540};
assign n542 = {n8, n541};
assign n543 = n524 == n542;
assign n544 = n519 & n532;
assign n548 = n519 & n527;
assign n556 =
n555 == 1'b0 ? n547 :
n551;
assign n558 = n561 + n33;
assign n563 = {n484, n568};
assign n564 =
n563 == 2'b00 ? n8 :
n563 == 2'b10 ? n8 :
n563 == 2'b01 ? n15 :
n15;
assign n565 =
n563 == 2'b00 ? n8 :
n563 == 2'b10 ? n15 :
n563 == 2'b01 ? n15 :
n8;
assign n569 = ~n564;
assign n581 = n518 & n569;
assign n585 = n518 & n564;
assign n593 =
n592 == 1'b0 ? n584 :
n588;
assign n594 = {n543, n536};
assign n596 = {n594, n601};
assign n597 =
n596 == 3'b000 ? n8 :
n596 == 3'b010 ? n8 :
n596 == 3'b100 ? n8 :
n596 == 3'b110 ? n8 :
n596 == 3'b001 ? n15 :
n596 == 3'b011 ? n15 :
n596 == 3'b101 ? n15 :
n15;
assign n598 =
n596 == 3'b000 ? n8 :
n596 == 3'b010 ? n8 :
n596 == 3'b100 ? n15 :
n596 == 3'b110 ? n8 :
n596 == 3'b001 ? n15 :
n596 == 3'b011 ? n8 :
n596 == 3'b101 ? n15 :
n8;
assign n602 = {n556[31],
n556[30],
n556[29],
n556[28],
n556[27],
n556[26],
n556[25],
n556[24],
n556[23],
n556[22],
n556[21],
n556[20],
n556[19],
n556[18],
n556[17],
n556[16]};
assign n603 = {n556[15],
n556[14],
n556[13],
n556[12],
n556[11],
n556[10],
n556[9],
n556[8],
n556[7],
n556[6],
n556[5],
n556[4],
n556[3],
n556[2],
n556[1],
n556[0]};
assign n604 = {n593[31],
n593[30],
n593[29],
n593[28],
n593[27],
n593[26],
n593[25],
n593[24],
n593[23],
n593[22],
n593[21],
n593[20],
n593[19],
n593[18],
n593[17],
n593[16]};
assign n605 = {n593[15],
n593[14],
n593[13],
n593[12],
n593[11],
n593[10],
n593[9],
n593[8],
n593[7],
n593[6],
n593[5],
n593[4],
n593[3],
n593[2],
n593[1],
n593[0]};
assign n606 =
n597 == 1'b0 ? n602 :
n603;
assign n607 =
n597 == 1'b0 ? n604 :
n605;
assign n609 = n612 + n4;
assign n613 = n612 == n12;
assign n614 = {n536, n613};
assign n616 = {n614, n621};
assign n617 =
n616 == 3'b000 ? n8 :
n616 == 3'b010 ? n8 :
n616 == 3'b100 ? n15 :
n616 == 3'b110 ? n15 :
n616 == 3'b001 ? n15 :
n616 == 3'b011 ? n8 :
n616 == 3'b101 ? n15 :
n15;
assign n618 =
n616 == 3'b000 ? n8 :
n616 == 3'b010 ? n8 :
n616 == 3'b100 ? n15 :
n616 == 3'b110 ? n15 :
n616 == 3'b001 ? n15 :
n616 == 3'b011 ? n8 :
n616 == 3'b101 ? n15 :
n15;
assign n626 = n625 & n613;
assign n627 = {n612[6],
n612[5]};
assign n632 = {n631[15],
n631[14],
n631[13],
n631[12],
n631[11],
n631[10],
n631[9],
n631[8]};
assign n633 = {n631[7],
n631[6],
n631[5],
n631[4],
n631[3],
n631[2],
n631[1],
n631[0]};
assign n638 = {n637[15],
n637[14],
n637[13],
n637[12],
n637[11],
n637[10],
n637[9],
n637[8]};
assign n639 = {n637[7],
n637[6],
n637[5],
n637[4],
n637[3],
n637[2],
n637[1],
n637[0]};
assign n659 = {n658[15],
n658[14],
n658[13],
n658[12],
n658[11],
n658[10],
n658[9],
n658[8]};
assign n660 = {n658[7],
n658[6],
n658[5],
n658[4],
n658[3],
n658[2],
n658[1],
n658[0]};
assign n661 = {n638} * {n659};
assign n662 = {n661[14],
n661[13],
n661[12],
n661[11],
n661[10],
n661[9],
n661[8],
n661[7]};
assign n667 = {n639} * {n660};
assign n668 = {n667[14],
n667[13],
n667[12],
n667[11],
n667[10],
n667[9],
n667[8],
n667[7]};
assign n673 = n666 - n672;
assign n678 = {n638} * {n660};
assign n679 = {n678[14],
n678[13],
n678[12],
n678[11],
n678[10],
n678[9],
n678[8],
n678[7]};
assign n684 = {n639} * {n659};
assign n685 = {n684[14],
n684[13],
n684[12],
n684[11],
n684[10],
n684[9],
n684[8],
n684[7]};
assign n690 = n683 + n689;
assign n695 = n647 + n677;
assign n696 = n655 + n694;
assign n697 = {n695, n696};
assign n702 = n647 - n677;
assign n703 = n655 - n694;
assign n704 = {n702, n703};
assign n709 = {n701, n708};
assign n726 = {n612[6],
n612[5],
n612[4],
n612[3],
n612[2],
n612[1]};
assign n743 = n612[0];
assign n760 = ~n759;
assign n762 = n765 + n33;
assign n767 = {n725, n772};
assign n768 =
n767 == 2'b00 ? n8 :
n767 == 2'b10 ? n8 :
n767 == 2'b01 ? n15 :
n15;
assign n769 =
n767 == 2'b00 ? n8 :
n767 == 2'b10 ? n15 :
n767 == 2'b01 ? n15 :
n8;
assign n773 = ~n768;
assign n778 = n8;
assign n779 = {n8, n778};
assign n780 = {n8, n779};
assign n781 = {n8, n780};
assign n782 = {n8, n781};
assign n783 = {n8, n782};
assign n784 = n765 == n783;
assign n785 = n760 & n773;
assign n789 = n760 & n768;
assign n797 =
n796 == 1'b0 ? n788 :
n792;
assign n799 = n802 + n33;
assign n804 = {n725, n809};
assign n805 =
n804 == 2'b00 ? n8 :
n804 == 2'b10 ? n8 :
n804 == 2'b01 ? n15 :
n15;
assign n806 =
n804 == 2'b00 ? n8 :
n804 == 2'b10 ? n15 :
n804 == 2'b01 ? n15 :
n8;
assign n810 = ~n805;
assign n822 = n759 & n810;
assign n826 = n759 & n805;
assign n834 =
n833 == 1'b0 ? n825 :
n829;
assign n835 = {n784, n777};
assign n837 = {n835, n842};
assign n838 =
n837 == 3'b000 ? n8 :
n837 == 3'b010 ? n8 :
n837 == 3'b100 ? n8 :
n837 == 3'b110 ? n8 :
n837 == 3'b001 ? n15 :
n837 == 3'b011 ? n15 :
n837 == 3'b101 ? n15 :
n15;
assign n839 =
n837 == 3'b000 ? n8 :
n837 == 3'b010 ? n8 :
n837 == 3'b100 ? n15 :
n837 == 3'b110 ? n8 :
n837 == 3'b001 ? n15 :
n837 == 3'b011 ? n8 :
n837 == 3'b101 ? n15 :
n8;
assign n843 = {n797[31],
n797[30],
n797[29],
n797[28],
n797[27],
n797[26],
n797[25],
n797[24],
n797[23],
n797[22],
n797[21],
n797[20],
n797[19],
n797[18],
n797[17],
n797[16]};
assign n844 = {n797[15],
n797[14],
n797[13],
n797[12],
n797[11],
n797[10],
n797[9],
n797[8],
n797[7],
n797[6],
n797[5],
n797[4],
n797[3],
n797[2],
n797[1],
n797[0]};
assign n845 = {n834[31],
n834[30],
n834[29],
n834[28],
n834[27],
n834[26],
n834[25],
n834[24],
n834[23],
n834[22],
n834[21],
n834[20],
n834[19],
n834[18],
n834[17],
n834[16]};
assign n846 = {n834[15],
n834[14],
n834[13],
n834[12],
n834[11],
n834[10],
n834[9],
n834[8],
n834[7],
n834[6],
n834[5],
n834[4],
n834[3],
n834[2],
n834[1],
n834[0]};
assign n847 =
n838 == 1'b0 ? n843 :
n844;
assign n848 =
n838 == 1'b0 ? n845 :
n846;
assign n850 = n853 + n4;
assign n854 = n853 == n12;
assign n855 = {n777, n854};
assign n857 = {n855, n862};
assign n858 =
n857 == 3'b000 ? n8 :
n857 == 3'b010 ? n8 :
n857 == 3'b100 ? n15 :
n857 == 3'b110 ? n15 :
n857 == 3'b001 ? n15 :
n857 == 3'b011 ? n8 :
n857 == 3'b101 ? n15 :
n15;
assign n859 =
n857 == 3'b000 ? n8 :
n857 == 3'b010 ? n8 :
n857 == 3'b100 ? n15 :
n857 == 3'b110 ? n15 :
n857 == 3'b001 ? n15 :
n857 == 3'b011 ? n8 :
n857 == 3'b101 ? n15 :
n15;
assign n867 = n866 & n854;
assign n868 = {n853[6],
n853[5],
n853[4]};
assign n873 = {n872[15],
n872[14],
n872[13],
n872[12],
n872[11],
n872[10],
n872[9],
n872[8]};
assign n874 = {n872[7],
n872[6],
n872[5],
n872[4],
n872[3],
n872[2],
n872[1],
n872[0]};
assign n879 = {n878[15],
n878[14],
n878[13],
n878[12],
n878[11],
n878[10],
n878[9],
n878[8]};
assign n880 = {n878[7],
n878[6],
n878[5],
n878[4],
n878[3],
n878[2],
n878[1],
n878[0]};
assign n900 = {n899[15],
n899[14],
n899[13],
n899[12],
n899[11],
n899[10],
n899[9],
n899[8]};
assign n901 = {n899[7],
n899[6],
n899[5],
n899[4],
n899[3],
n899[2],
n899[1],
n899[0]};
assign n902 = {n879} * {n900};
assign n903 = {n902[14],
n902[13],
n902[12],
n902[11],
n902[10],
n902[9],
n902[8],
n902[7]};
assign n908 = {n880} * {n901};
assign n909 = {n908[14],
n908[13],
n908[12],
n908[11],
n908[10],
n908[9],
n908[8],
n908[7]};
assign n914 = n907 - n913;
assign n919 = {n879} * {n901};
assign n920 = {n919[14],
n919[13],
n919[12],
n919[11],
n919[10],
n919[9],
n919[8],
n919[7]};
assign n925 = {n880} * {n900};
assign n926 = {n925[14],
n925[13],
n925[12],
n925[11],
n925[10],
n925[9],
n925[8],
n925[7]};
assign n931 = n924 + n930;
assign n936 = n888 + n918;
assign n937 = n896 + n935;
assign n938 = {n936, n937};
assign n943 = n888 - n918;
assign n944 = n896 - n935;
assign n945 = {n943, n944};
assign n950 = {n942, n949};
assign n967 = {n853[6],
n853[5],
n853[4],
n853[3],
n853[2],
n853[1]};
assign n984 = n853[0];
assign n1001 = ~n1000;
assign n1003 = n1006 + n33;
assign n1008 = {n966, n1013};
assign n1009 =
n1008 == 2'b00 ? n8 :
n1008 == 2'b10 ? n8 :
n1008 == 2'b01 ? n15 :
n15;
assign n1010 =
n1008 == 2'b00 ? n8 :
n1008 == 2'b10 ? n15 :
n1008 == 2'b01 ? n15 :
n8;
assign n1014 = ~n1009;
assign n1019 = n8;
assign n1020 = {n8, n1019};
assign n1021 = {n8, n1020};
assign n1022 = {n8, n1021};
assign n1023 = {n8, n1022};
assign n1024 = {n8, n1023};
assign n1025 = n1006 == n1024;
assign n1026 = n1001 & n1014;
assign n1030 = n1001 & n1009;
assign n1038 =
n1037 == 1'b0 ? n1029 :
n1033;
assign n1040 = n1043 + n33;
assign n1045 = {n966, n1050};
assign n1046 =
n1045 == 2'b00 ? n8 :
n1045 == 2'b10 ? n8 :
n1045 == 2'b01 ? n15 :
n15;
assign n1047 =
n1045 == 2'b00 ? n8 :
n1045 == 2'b10 ? n15 :
n1045 == 2'b01 ? n15 :
n8;
assign n1051 = ~n1046;
assign n1063 = n1000 & n1051;
assign n1067 = n1000 & n1046;
assign n1075 =
n1074 == 1'b0 ? n1066 :
n1070;
assign n1076 = {n1025, n1018};
assign n1078 = {n1076, n1083};
assign n1079 =
n1078 == 3'b000 ? n8 :
n1078 == 3'b010 ? n8 :
n1078 == 3'b100 ? n8 :
n1078 == 3'b110 ? n8 :
n1078 == 3'b001 ? n15 :
n1078 == 3'b011 ? n15 :
n1078 == 3'b101 ? n15 :
n15;
assign n1080 =
n1078 == 3'b000 ? n8 :
n1078 == 3'b010 ? n8 :
n1078 == 3'b100 ? n15 :
n1078 == 3'b110 ? n8 :
n1078 == 3'b001 ? n15 :
n1078 == 3'b011 ? n8 :
n1078 == 3'b101 ? n15 :
n8;
assign n1084 = {n1038[31],
n1038[30],
n1038[29],
n1038[28],
n1038[27],
n1038[26],
n1038[25],
n1038[24],
n1038[23],
n1038[22],
n1038[21],
n1038[20],
n1038[19],
n1038[18],
n1038[17],
n1038[16]};
assign n1085 = {n1038[15],
n1038[14],
n1038[13],
n1038[12],
n1038[11],
n1038[10],
n1038[9],
n1038[8],
n1038[7],
n1038[6],
n1038[5],
n1038[4],
n1038[3],
n1038[2],
n1038[1],
n1038[0]};
assign n1086 = {n1075[31],
n1075[30],
n1075[29],
n1075[28],
n1075[27],
n1075[26],
n1075[25],
n1075[24],
n1075[23],
n1075[22],
n1075[21],
n1075[20],
n1075[19],
n1075[18],
n1075[17],
n1075[16]};
assign n1087 = {n1075[15],
n1075[14],
n1075[13],
n1075[12],
n1075[11],
n1075[10],
n1075[9],
n1075[8],
n1075[7],
n1075[6],
n1075[5],
n1075[4],
n1075[3],
n1075[2],
n1075[1],
n1075[0]};
assign n1088 =
n1079 == 1'b0 ? n1084 :
n1085;
assign n1089 =
n1079 == 1'b0 ? n1086 :
n1087;
assign n1091 = n1094 + n4;
assign n1095 = n1094 == n12;
assign n1096 = {n1018, n1095};
assign n1098 = {n1096, n1103};
assign n1099 =
n1098 == 3'b000 ? n8 :
n1098 == 3'b010 ? n8 :
n1098 == 3'b100 ? n15 :
n1098 == 3'b110 ? n15 :
n1098 == 3'b001 ? n15 :
n1098 == 3'b011 ? n8 :
n1098 == 3'b101 ? n15 :
n15;
assign n1100 =
n1098 == 3'b000 ? n8 :
n1098 == 3'b010 ? n8 :
n1098 == 3'b100 ? n15 :
n1098 == 3'b110 ? n15 :
n1098 == 3'b001 ? n15 :
n1098 == 3'b011 ? n8 :
n1098 == 3'b101 ? n15 :
n15;
assign n1108 = n1107 & n1095;
assign n1109 = {n1094[6],
n1094[5],
n1094[4],
n1094[3]};
assign n1114 = {n1113[15],
n1113[14],
n1113[13],
n1113[12],
n1113[11],
n1113[10],
n1113[9],
n1113[8]};
assign n1115 = {n1113[7],
n1113[6],
n1113[5],
n1113[4],
n1113[3],
n1113[2],
n1113[1],
n1113[0]};
assign n1120 = {n1119[15],
n1119[14],
n1119[13],
n1119[12],
n1119[11],
n1119[10],
n1119[9],
n1119[8]};
assign n1121 = {n1119[7],
n1119[6],
n1119[5],
n1119[4],
n1119[3],
n1119[2],
n1119[1],
n1119[0]};
assign n1141 = {n1140[15],
n1140[14],
n1140[13],
n1140[12],
n1140[11],
n1140[10],
n1140[9],
n1140[8]};
assign n1142 = {n1140[7],
n1140[6],
n1140[5],
n1140[4],
n1140[3],
n1140[2],
n1140[1],
n1140[0]};
assign n1143 = {n1120} * {n1141};
assign n1144 = {n1143[14],
n1143[13],
n1143[12],
n1143[11],
n1143[10],
n1143[9],
n1143[8],
n1143[7]};
assign n1149 = {n1121} * {n1142};
assign n1150 = {n1149[14],
n1149[13],
n1149[12],
n1149[11],
n1149[10],
n1149[9],
n1149[8],
n1149[7]};
assign n1155 = n1148 - n1154;
assign n1160 = {n1120} * {n1142};
assign n1161 = {n1160[14],
n1160[13],
n1160[12],
n1160[11],
n1160[10],
n1160[9],
n1160[8],
n1160[7]};
assign n1166 = {n1121} * {n1141};
assign n1167 = {n1166[14],
n1166[13],
n1166[12],
n1166[11],
n1166[10],
n1166[9],
n1166[8],
n1166[7]};
assign n1172 = n1165 + n1171;
assign n1177 = n1129 + n1159;
assign n1178 = n1137 + n1176;
assign n1179 = {n1177, n1178};
assign n1184 = n1129 - n1159;
assign n1185 = n1137 - n1176;
assign n1186 = {n1184, n1185};
assign n1191 = {n1183, n1190};
assign n1208 = {n1094[6],
n1094[5],
n1094[4],
n1094[3],
n1094[2],
n1094[1]};
assign n1225 = n1094[0];
assign n1242 = ~n1241;
assign n1244 = n1247 + n33;
assign n1249 = {n1207, n1254};
assign n1250 =
n1249 == 2'b00 ? n8 :
n1249 == 2'b10 ? n8 :
n1249 == 2'b01 ? n15 :
n15;
assign n1251 =
n1249 == 2'b00 ? n8 :
n1249 == 2'b10 ? n15 :
n1249 == 2'b01 ? n15 :
n8;
assign n1255 = ~n1250;
assign n1260 = n8;
assign n1261 = {n8, n1260};
assign n1262 = {n8, n1261};
assign n1263 = {n8, n1262};
assign n1264 = {n8, n1263};
assign n1265 = {n8, n1264};
assign n1266 = n1247 == n1265;
assign n1267 = n1242 & n1255;
assign n1271 = n1242 & n1250;
assign n1279 =
n1278 == 1'b0 ? n1270 :
n1274;
assign n1281 = n1284 + n33;
assign n1286 = {n1207, n1291};
assign n1287 =
n1286 == 2'b00 ? n8 :
n1286 == 2'b10 ? n8 :
n1286 == 2'b01 ? n15 :
n15;
assign n1288 =
n1286 == 2'b00 ? n8 :
n1286 == 2'b10 ? n15 :
n1286 == 2'b01 ? n15 :
n8;
assign n1292 = ~n1287;
assign n1304 = n1241 & n1292;
assign n1308 = n1241 & n1287;
assign n1316 =
n1315 == 1'b0 ? n1307 :
n1311;
assign n1317 = {n1266, n1259};
assign n1319 = {n1317, n1324};
assign n1320 =
n1319 == 3'b000 ? n8 :
n1319 == 3'b010 ? n8 :
n1319 == 3'b100 ? n8 :
n1319 == 3'b110 ? n8 :
n1319 == 3'b001 ? n15 :
n1319 == 3'b011 ? n15 :
n1319 == 3'b101 ? n15 :
n15;
assign n1321 =
n1319 == 3'b000 ? n8 :
n1319 == 3'b010 ? n8 :
n1319 == 3'b100 ? n15 :
n1319 == 3'b110 ? n8 :
n1319 == 3'b001 ? n15 :
n1319 == 3'b011 ? n8 :
n1319 == 3'b101 ? n15 :
n8;
assign n1325 = {n1279[31],
n1279[30],
n1279[29],
n1279[28],
n1279[27],
n1279[26],
n1279[25],
n1279[24],
n1279[23],
n1279[22],
n1279[21],
n1279[20],
n1279[19],
n1279[18],
n1279[17],
n1279[16]};
assign n1326 = {n1279[15],
n1279[14],
n1279[13],
n1279[12],
n1279[11],
n1279[10],
n1279[9],
n1279[8],
n1279[7],
n1279[6],
n1279[5],
n1279[4],
n1279[3],
n1279[2],
n1279[1],
n1279[0]};
assign n1327 = {n1316[31],
n1316[30],
n1316[29],
n1316[28],
n1316[27],
n1316[26],
n1316[25],
n1316[24],
n1316[23],
n1316[22],
n1316[21],
n1316[20],
n1316[19],
n1316[18],
n1316[17],
n1316[16]};
assign n1328 = {n1316[15],
n1316[14],
n1316[13],
n1316[12],
n1316[11],
n1316[10],
n1316[9],
n1316[8],
n1316[7],
n1316[6],
n1316[5],
n1316[4],
n1316[3],
n1316[2],
n1316[1],
n1316[0]};
assign n1329 =
n1320 == 1'b0 ? n1325 :
n1326;
assign n1330 =
n1320 == 1'b0 ? n1327 :
n1328;
assign n1332 = n1335 + n4;
assign n1336 = n1335 == n12;
assign n1337 = {n1259, n1336};
assign n1339 = {n1337, n1344};
assign n1340 =
n1339 == 3'b000 ? n8 :
n1339 == 3'b010 ? n8 :
n1339 == 3'b100 ? n15 :
n1339 == 3'b110 ? n15 :
n1339 == 3'b001 ? n15 :
n1339 == 3'b011 ? n8 :
n1339 == 3'b101 ? n15 :
n15;
assign n1341 =
n1339 == 3'b000 ? n8 :
n1339 == 3'b010 ? n8 :
n1339 == 3'b100 ? n15 :
n1339 == 3'b110 ? n15 :
n1339 == 3'b001 ? n15 :
n1339 == 3'b011 ? n8 :
n1339 == 3'b101 ? n15 :
n15;
assign n1349 = n1348 & n1336;
assign n1350 = {n1335[6],
n1335[5],
n1335[4],
n1335[3],
n1335[2]};
assign n1355 = {n1354[15],
n1354[14],
n1354[13],
n1354[12],
n1354[11],
n1354[10],
n1354[9],
n1354[8]};
assign n1356 = {n1354[7],
n1354[6],
n1354[5],
n1354[4],
n1354[3],
n1354[2],
n1354[1],
n1354[0]};
assign n1361 = {n1360[15],
n1360[14],
n1360[13],
n1360[12],
n1360[11],
n1360[10],
n1360[9],
n1360[8]};
assign n1362 = {n1360[7],
n1360[6],
n1360[5],
n1360[4],
n1360[3],
n1360[2],
n1360[1],
n1360[0]};
assign n1382 = {n1381[15],
n1381[14],
n1381[13],
n1381[12],
n1381[11],
n1381[10],
n1381[9],
n1381[8]};
assign n1383 = {n1381[7],
n1381[6],
n1381[5],
n1381[4],
n1381[3],
n1381[2],
n1381[1],
n1381[0]};
assign n1384 = {n1361} * {n1382};
assign n1385 = {n1384[14],
n1384[13],
n1384[12],
n1384[11],
n1384[10],
n1384[9],
n1384[8],
n1384[7]};
assign n1390 = {n1362} * {n1383};
assign n1391 = {n1390[14],
n1390[13],
n1390[12],
n1390[11],
n1390[10],
n1390[9],
n1390[8],
n1390[7]};
assign n1396 = n1389 - n1395;
assign n1401 = {n1361} * {n1383};
assign n1402 = {n1401[14],
n1401[13],
n1401[12],
n1401[11],
n1401[10],
n1401[9],
n1401[8],
n1401[7]};
assign n1407 = {n1362} * {n1382};
assign n1408 = {n1407[14],
n1407[13],
n1407[12],
n1407[11],
n1407[10],
n1407[9],
n1407[8],
n1407[7]};
assign n1413 = n1406 + n1412;
assign n1418 = n1370 + n1400;
assign n1419 = n1378 + n1417;
assign n1420 = {n1418, n1419};
assign n1425 = n1370 - n1400;
assign n1426 = n1378 - n1417;
assign n1427 = {n1425, n1426};
assign n1432 = {n1424, n1431};
assign n1449 = {n1335[6],
n1335[5],
n1335[4],
n1335[3],
n1335[2],
n1335[1]};
assign n1466 = n1335[0];
assign n1483 = ~n1482;
assign n1485 = n1488 + n33;
assign n1490 = {n1448, n1495};
assign n1491 =
n1490 == 2'b00 ? n8 :
n1490 == 2'b10 ? n8 :
n1490 == 2'b01 ? n15 :
n15;
assign n1492 =
n1490 == 2'b00 ? n8 :
n1490 == 2'b10 ? n15 :
n1490 == 2'b01 ? n15 :
n8;
assign n1496 = ~n1491;
assign n1501 = n8;
assign n1502 = {n8, n1501};
assign n1503 = {n8, n1502};
assign n1504 = {n8, n1503};
assign n1505 = {n8, n1504};
assign n1506 = {n8, n1505};
assign n1507 = n1488 == n1506;
assign n1508 = n1483 & n1496;
assign n1512 = n1483 & n1491;
assign n1520 =
n1519 == 1'b0 ? n1511 :
n1515;
assign n1522 = n1525 + n33;
assign n1527 = {n1448, n1532};
assign n1528 =
n1527 == 2'b00 ? n8 :
n1527 == 2'b10 ? n8 :
n1527 == 2'b01 ? n15 :
n15;
assign n1529 =
n1527 == 2'b00 ? n8 :
n1527 == 2'b10 ? n15 :
n1527 == 2'b01 ? n15 :
n8;
assign n1533 = ~n1528;
assign n1545 = n1482 & n1533;
assign n1549 = n1482 & n1528;
assign n1557 =
n1556 == 1'b0 ? n1548 :
n1552;
assign n1558 = {n1507, n1500};
assign n1560 = {n1558, n1565};
assign n1561 =
n1560 == 3'b000 ? n8 :
n1560 == 3'b010 ? n8 :
n1560 == 3'b100 ? n8 :
n1560 == 3'b110 ? n8 :
n1560 == 3'b001 ? n15 :
n1560 == 3'b011 ? n15 :
n1560 == 3'b101 ? n15 :
n15;
assign n1562 =
n1560 == 3'b000 ? n8 :
n1560 == 3'b010 ? n8 :
n1560 == 3'b100 ? n15 :
n1560 == 3'b110 ? n8 :
n1560 == 3'b001 ? n15 :
n1560 == 3'b011 ? n8 :
n1560 == 3'b101 ? n15 :
n8;
assign n1566 = {n1520[31],
n1520[30],
n1520[29],
n1520[28],
n1520[27],
n1520[26],
n1520[25],
n1520[24],
n1520[23],
n1520[22],
n1520[21],
n1520[20],
n1520[19],
n1520[18],
n1520[17],
n1520[16]};
assign n1567 = {n1520[15],
n1520[14],
n1520[13],
n1520[12],
n1520[11],
n1520[10],
n1520[9],
n1520[8],
n1520[7],
n1520[6],
n1520[5],
n1520[4],
n1520[3],
n1520[2],
n1520[1],
n1520[0]};
assign n1568 = {n1557[31],
n1557[30],
n1557[29],
n1557[28],
n1557[27],
n1557[26],
n1557[25],
n1557[24],
n1557[23],
n1557[22],
n1557[21],
n1557[20],
n1557[19],
n1557[18],
n1557[17],
n1557[16]};
assign n1569 = {n1557[15],
n1557[14],
n1557[13],
n1557[12],
n1557[11],
n1557[10],
n1557[9],
n1557[8],
n1557[7],
n1557[6],
n1557[5],
n1557[4],
n1557[3],
n1557[2],
n1557[1],
n1557[0]};
assign n1570 =
n1561 == 1'b0 ? n1566 :
n1567;
assign n1571 =
n1561 == 1'b0 ? n1568 :
n1569;
assign n1573 = n1576 + n4;
assign n1577 = n1576 == n12;
assign n1578 = {n1500, n1577};
assign n1580 = {n1578, n1585};
assign n1581 =
n1580 == 3'b000 ? n8 :
n1580 == 3'b010 ? n8 :
n1580 == 3'b100 ? n15 :
n1580 == 3'b110 ? n15 :
n1580 == 3'b001 ? n15 :
n1580 == 3'b011 ? n8 :
n1580 == 3'b101 ? n15 :
n15;
assign n1582 =
n1580 == 3'b000 ? n8 :
n1580 == 3'b010 ? n8 :
n1580 == 3'b100 ? n15 :
n1580 == 3'b110 ? n15 :
n1580 == 3'b001 ? n15 :
n1580 == 3'b011 ? n8 :
n1580 == 3'b101 ? n15 :
n15;
assign n1590 = n1589 & n1577;
assign n1591 = {n1576[6],
n1576[5],
n1576[4],
n1576[3],
n1576[2],
n1576[1]};
assign n1596 = {n1595[15],
n1595[14],
n1595[13],
n1595[12],
n1595[11],
n1595[10],
n1595[9],
n1595[8]};
assign n1597 = {n1595[7],
n1595[6],
n1595[5],
n1595[4],
n1595[3],
n1595[2],
n1595[1],
n1595[0]};
assign n1602 = {n1601[15],
n1601[14],
n1601[13],
n1601[12],
n1601[11],
n1601[10],
n1601[9],
n1601[8]};
assign n1603 = {n1601[7],
n1601[6],
n1601[5],
n1601[4],
n1601[3],
n1601[2],
n1601[1],
n1601[0]};
assign n1623 = {n1622[15],
n1622[14],
n1622[13],
n1622[12],
n1622[11],
n1622[10],
n1622[9],
n1622[8]};
assign n1624 = {n1622[7],
n1622[6],
n1622[5],
n1622[4],
n1622[3],
n1622[2],
n1622[1],
n1622[0]};
assign n1625 = {n1602} * {n1623};
assign n1626 = {n1625[14],
n1625[13],
n1625[12],
n1625[11],
n1625[10],
n1625[9],
n1625[8],
n1625[7]};
assign n1631 = {n1603} * {n1624};
assign n1632 = {n1631[14],
n1631[13],
n1631[12],
n1631[11],
n1631[10],
n1631[9],
n1631[8],
n1631[7]};
assign n1637 = n1630 - n1636;
assign n1642 = {n1602} * {n1624};
assign n1643 = {n1642[14],
n1642[13],
n1642[12],
n1642[11],
n1642[10],
n1642[9],
n1642[8],
n1642[7]};
assign n1648 = {n1603} * {n1623};
assign n1649 = {n1648[14],
n1648[13],
n1648[12],
n1648[11],
n1648[10],
n1648[9],
n1648[8],
n1648[7]};
assign n1654 = n1647 + n1653;
assign n1659 = n1611 + n1641;
assign n1660 = n1619 + n1658;
assign n1661 = {n1659, n1660};
assign n1666 = n1611 - n1641;
assign n1667 = n1619 - n1658;
assign n1668 = {n1666, n1667};
assign n1673 = {n1665, n1672};
assign n1690 = {n1576[6],
n1576[5],
n1576[4],
n1576[3],
n1576[2],
n1576[1]};
assign n1707 = n1576[0];
assign n1724 = ~n1723;
assign n1726 = n1729 + n33;
assign n1731 = {n1689, n1736};
assign n1732 =
n1731 == 2'b00 ? n8 :
n1731 == 2'b10 ? n8 :
n1731 == 2'b01 ? n15 :
n15;
assign n1733 =
n1731 == 2'b00 ? n8 :
n1731 == 2'b10 ? n15 :
n1731 == 2'b01 ? n15 :
n8;
assign n1737 = ~n1732;
assign n1742 = n8;
assign n1743 = {n8, n1742};
assign n1744 = {n8, n1743};
assign n1745 = {n8, n1744};
assign n1746 = {n8, n1745};
assign n1747 = {n8, n1746};
assign n1748 = n1729 == n1747;
assign n1749 = n1724 & n1737;
assign n1753 = n1724 & n1732;
assign n1761 =
n1760 == 1'b0 ? n1752 :
n1756;
assign n1763 = n1766 + n33;
assign n1768 = {n1689, n1773};
assign n1769 =
n1768 == 2'b00 ? n8 :
n1768 == 2'b10 ? n8 :
n1768 == 2'b01 ? n15 :
n15;
assign n1770 =
n1768 == 2'b00 ? n8 :
n1768 == 2'b10 ? n15 :
n1768 == 2'b01 ? n15 :
n8;
assign n1774 = ~n1769;
assign n1786 = n1723 & n1774;
assign n1790 = n1723 & n1769;
assign n1798 =
n1797 == 1'b0 ? n1789 :
n1793;
assign n1799 = {n1748, n1741};
assign n1801 = {n1799, n1806};
assign n1802 =
n1801 == 3'b000 ? n8 :
n1801 == 3'b010 ? n8 :
n1801 == 3'b100 ? n8 :
n1801 == 3'b110 ? n8 :
n1801 == 3'b001 ? n15 :
n1801 == 3'b011 ? n15 :
n1801 == 3'b101 ? n15 :
n15;
assign n1803 =
n1801 == 3'b000 ? n8 :
n1801 == 3'b010 ? n8 :
n1801 == 3'b100 ? n15 :
n1801 == 3'b110 ? n8 :
n1801 == 3'b001 ? n15 :
n1801 == 3'b011 ? n8 :
n1801 == 3'b101 ? n15 :
n8;
assign n1807 = {n1761[31],
n1761[30],
n1761[29],
n1761[28],
n1761[27],
n1761[26],
n1761[25],
n1761[24],
n1761[23],
n1761[22],
n1761[21],
n1761[20],
n1761[19],
n1761[18],
n1761[17],
n1761[16]};
assign n1808 = {n1761[15],
n1761[14],
n1761[13],
n1761[12],
n1761[11],
n1761[10],
n1761[9],
n1761[8],
n1761[7],
n1761[6],
n1761[5],
n1761[4],
n1761[3],
n1761[2],
n1761[1],
n1761[0]};
assign n1809 = {n1798[31],
n1798[30],
n1798[29],
n1798[28],
n1798[27],
n1798[26],
n1798[25],
n1798[24],
n1798[23],
n1798[22],
n1798[21],
n1798[20],
n1798[19],
n1798[18],
n1798[17],
n1798[16]};
assign n1810 = {n1798[15],
n1798[14],
n1798[13],
n1798[12],
n1798[11],
n1798[10],
n1798[9],
n1798[8],
n1798[7],
n1798[6],
n1798[5],
n1798[4],
n1798[3],
n1798[2],
n1798[1],
n1798[0]};
assign n1811 =
n1802 == 1'b0 ? n1807 :
n1808;
assign n1812 =
n1802 == 1'b0 ? n1809 :
n1810;
assign n1814 = n1817 + n4;
assign n1818 = n1817 == n12;
assign n1819 = {n1741, n1818};
assign n1821 = {n1819, n1826};
assign n1822 =
n1821 == 3'b000 ? n8 :
n1821 == 3'b010 ? n8 :
n1821 == 3'b100 ? n15 :
n1821 == 3'b110 ? n15 :
n1821 == 3'b001 ? n15 :
n1821 == 3'b011 ? n8 :
n1821 == 3'b101 ? n15 :
n15;
assign n1823 =
n1821 == 3'b000 ? n8 :
n1821 == 3'b010 ? n8 :
n1821 == 3'b100 ? n15 :
n1821 == 3'b110 ? n15 :
n1821 == 3'b001 ? n15 :
n1821 == 3'b011 ? n8 :
n1821 == 3'b101 ? n15 :
n15;
assign n1831 = n1830 & n1818;
assign n1832 = {n1817[6],
n1817[5],
n1817[4],
n1817[3],
n1817[2],
n1817[1],
n1817[0]};
assign n1837 = {n1836[15],
n1836[14],
n1836[13],
n1836[12],
n1836[11],
n1836[10],
n1836[9],
n1836[8]};
assign n1838 = {n1836[7],
n1836[6],
n1836[5],
n1836[4],
n1836[3],
n1836[2],
n1836[1],
n1836[0]};
assign n1843 = {n1842[15],
n1842[14],
n1842[13],
n1842[12],
n1842[11],
n1842[10],
n1842[9],
n1842[8]};
assign n1844 = {n1842[7],
n1842[6],
n1842[5],
n1842[4],
n1842[3],
n1842[2],
n1842[1],
n1842[0]};
assign n1864 = {n1863[15],
n1863[14],
n1863[13],
n1863[12],
n1863[11],
n1863[10],
n1863[9],
n1863[8]};
assign n1865 = {n1863[7],
n1863[6],
n1863[5],
n1863[4],
n1863[3],
n1863[2],
n1863[1],
n1863[0]};
assign n1866 = {n1843} * {n1864};
assign n1867 = {n1866[14],
n1866[13],
n1866[12],
n1866[11],
n1866[10],
n1866[9],
n1866[8],
n1866[7]};
assign n1872 = {n1844} * {n1865};
assign n1873 = {n1872[14],
n1872[13],
n1872[12],
n1872[11],
n1872[10],
n1872[9],
n1872[8],
n1872[7]};
assign n1878 = n1871 - n1877;
assign n1883 = {n1843} * {n1865};
assign n1884 = {n1883[14],
n1883[13],
n1883[12],
n1883[11],
n1883[10],
n1883[9],
n1883[8],
n1883[7]};
assign n1889 = {n1844} * {n1864};
assign n1890 = {n1889[14],
n1889[13],
n1889[12],
n1889[11],
n1889[10],
n1889[9],
n1889[8],
n1889[7]};
assign n1895 = n1888 + n1894;
assign n1900 = n1852 + n1882;
assign n1901 = n1860 + n1899;
assign n1902 = {n1900, n1901};
assign n1907 = n1852 - n1882;
assign n1908 = n1860 - n1899;
assign n1909 = {n1907, n1908};
assign n1914 = {n1906, n1913};
assign n1931 = {n1817[6],
n1817[5],
n1817[4],
n1817[3],
n1817[2],
n1817[1]};
assign n1948 = n1817[0];
assign n1965 = ~n1964;
assign n1967 = n1970 + n33;
assign n1972 = {n1930, n1977};
assign n1973 =
n1972 == 2'b00 ? n8 :
n1972 == 2'b10 ? n8 :
n1972 == 2'b01 ? n15 :
n15;
assign n1974 =
n1972 == 2'b00 ? n8 :
n1972 == 2'b10 ? n15 :
n1972 == 2'b01 ? n15 :
n8;
assign n1978 = ~n1973;
assign n1983 = n8;
assign n1984 = {n8, n1983};
assign n1985 = {n8, n1984};
assign n1986 = {n8, n1985};
assign n1987 = {n8, n1986};
assign n1988 = {n8, n1987};
assign n1989 = n1970 == n1988;
assign n1990 = n1965 & n1978;
assign n1994 = n1965 & n1973;
assign n2002 =
n2001 == 1'b0 ? n1993 :
n1997;
assign n2004 = n2007 + n33;
assign n2009 = {n1930, n2014};
assign n2010 =
n2009 == 2'b00 ? n8 :
n2009 == 2'b10 ? n8 :
n2009 == 2'b01 ? n15 :
n15;
assign n2011 =
n2009 == 2'b00 ? n8 :
n2009 == 2'b10 ? n15 :
n2009 == 2'b01 ? n15 :
n8;
assign n2015 = ~n2010;
assign n2027 = n1964 & n2015;
assign n2031 = n1964 & n2010;
assign n2039 =
n2038 == 1'b0 ? n2030 :
n2034;
assign n2040 = {n1989, n1982};
assign n2042 = {n2040, n2047};
assign n2043 =
n2042 == 3'b000 ? n8 :
n2042 == 3'b010 ? n8 :
n2042 == 3'b100 ? n8 :
n2042 == 3'b110 ? n8 :
n2042 == 3'b001 ? n15 :
n2042 == 3'b011 ? n15 :
n2042 == 3'b101 ? n15 :
n15;
assign n2044 =
n2042 == 3'b000 ? n8 :
n2042 == 3'b010 ? n8 :
n2042 == 3'b100 ? n15 :
n2042 == 3'b110 ? n8 :
n2042 == 3'b001 ? n15 :
n2042 == 3'b011 ? n8 :
n2042 == 3'b101 ? n15 :
n8;
assign n2048 = {n2002[31],
n2002[30],
n2002[29],
n2002[28],
n2002[27],
n2002[26],
n2002[25],
n2002[24],
n2002[23],
n2002[22],
n2002[21],
n2002[20],
n2002[19],
n2002[18],
n2002[17],
n2002[16]};
assign n2049 = {n2002[15],
n2002[14],
n2002[13],
n2002[12],
n2002[11],
n2002[10],
n2002[9],
n2002[8],
n2002[7],
n2002[6],
n2002[5],
n2002[4],
n2002[3],
n2002[2],
n2002[1],
n2002[0]};
assign n2050 = {n2039[31],
n2039[30],
n2039[29],
n2039[28],
n2039[27],
n2039[26],
n2039[25],
n2039[24],
n2039[23],
n2039[22],
n2039[21],
n2039[20],
n2039[19],
n2039[18],
n2039[17],
n2039[16]};
assign n2051 = {n2039[15],
n2039[14],
n2039[13],
n2039[12],
n2039[11],
n2039[10],
n2039[9],
n2039[8],
n2039[7],
n2039[6],
n2039[5],
n2039[4],
n2039[3],
n2039[2],
n2039[1],
n2039[0]};
assign n2052 =
n2043 == 1'b0 ? n2048 :
n2049;
assign n2053 =
n2043 == 1'b0 ? n2050 :
n2051;
assign sync_o = n1982;
assign data_0_o = n2052;
assign data_1_o = n2053;
assign n2059 = enable_i & n15;
assign n2060 = n8 | n2059;
assign n2061 = n15 & n2060;
assign n2062 = reset_i | n8;
assign n2063 = n1930 | n2062;
assign n2064 = n1930 | n2062;
assign n2065 = n1822 & n15;
assign n2066 = n2062 | n2065;
assign n2067 = n2061 & n2066;
assign n2068 = n1741 | n2062;
assign n2069 = n1689 | n2062;
assign n2070 = n1689 | n2062;
assign n2071 = n1581 & n15;
assign n2072 = n2062 | n2071;
assign n2073 = n2061 & n2072;
assign n2074 = n1500 | n2062;
assign n2075 = n1448 | n2062;
assign n2076 = n1448 | n2062;
assign n2077 = n1340 & n15;
assign n2078 = n2062 | n2077;
assign n2079 = n2061 & n2078;
assign n2080 = n1259 | n2062;
assign n2081 = n1207 | n2062;
assign n2082 = n1207 | n2062;
assign n2083 = n1099 & n15;
assign n2084 = n2062 | n2083;
assign n2085 = n2061 & n2084;
assign n2086 = n1018 | n2062;
assign n2087 = n966 | n2062;
assign n2088 = n966 | n2062;
assign n2089 = n858 & n15;
assign n2090 = n2062 | n2089;
assign n2091 = n2061 & n2090;
assign n2092 = n777 | n2062;
assign n2093 = n725 | n2062;
assign n2094 = n725 | n2062;
assign n2095 = n617 & n15;
assign n2096 = n2062 | n2095;
assign n2097 = n2061 & n2096;
assign n2098 = n536 | n2062;
assign n2099 = n484 | n2062;
assign n2100 = n484 | n2062;
assign n2101 = n376 & n15;
assign n2102 = n2062 | n2101;
assign n2103 = n2061 & n2102;
assign n2104 = n295 | n2062;
assign n2105 = n243 | n2062;
assign n2106 = n243 | n2062;
assign n2107 = n134 & n15;
assign n2108 = n2062 | n2107;
assign n2109 = n2061 & n2108;
assign n2110 = n51 | n2062;
assign n2111 = n27 | n2062;
assign n2112 = n27 | n2062;
assign n2113 = n18 & n15;
assign n2114 = n2062 | n2113;
assign n2115 = n2061 & n2114;
assign n2116 = sync_i | n2062;
always @ (posedge clock_c)
if (n2115 == 1'b1)
if (n2116 == 1'b1)
n11 <= 7'b0000000;
else
n11 <= n7;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n22 <= 1'b0;
else
n22 <= n19;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n26 <= 1'b0;
else
n26 <= n18;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2112 == 1'b1)
n39 <= 6'b000000;
else
n39 <= n36;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n46 <= 1'b0;
else
n46 <= n43;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n51 <= 1'b0;
else
n51 <= n27;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n60 == 1'b1)
n64m <= n28;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n64ra <= n39;
end
assign n64 = n64m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n65 == 1'b1)
n68m <= n28;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n68ra <= n39;
end
assign n68 = n68m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n72 <= 1'b0;
else
n72 <= n47;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2111 == 1'b1)
n78 <= 6'b000000;
else
n78 <= n75;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n85 <= 1'b0;
else
n85 <= n82;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n98 == 1'b1)
n101m <= n28;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n101ra <= n78;
end
assign n101 = n101m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n102 == 1'b1)
n105m <= n28;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n105ra <= n78;
end
assign n105 = n105m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n109 <= 1'b0;
else
n109 <= n86;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n118 <= 1'b0;
else
n118 <= n115;
always @ (posedge clock_c)
if (n2109 == 1'b1)
if (n2110 == 1'b1)
n129 <= 7'b0000000;
else
n129 <= n126;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n138 <= 1'b0;
else
n138 <= n135;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n142 <= 1'b0;
else
n142 <= n134;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n148 <= 16'b0000000000000000;
else
n148 <= n123;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n154 <= 16'b0000000000000000;
else
n154 <= n124;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n161 <= 8'b00000000;
else
n161 <= n149;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n165 <= 8'b00000000;
else
n165 <= n161;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n169 <= 8'b00000000;
else
n169 <= n150;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n173 <= 8'b00000000;
else
n173 <= n169;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n8)
1'b0 : n176 <= 16'b0111111100000000;
1'b1 : n176 <= 16'b0000000010000000;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n184 <= 8'b00000000;
else
n184 <= n180;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n190 <= 8'b00000000;
else
n190 <= n186;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n195 <= 8'b00000000;
else
n195 <= n191;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n201 <= 8'b00000000;
else
n201 <= n197;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n207 <= 8'b00000000;
else
n207 <= n203;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n212 <= 8'b00000000;
else
n212 <= n208;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n219 <= 16'b0000000000000000;
else
n219 <= n215;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n226 <= 16'b0000000000000000;
else
n226 <= n222;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n231 <= 1'b0;
else
n231 <= n143;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n235 <= 1'b0;
else
n235 <= n231;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n239 <= 1'b0;
else
n239 <= n235;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n243 <= 1'b0;
else
n243 <= n239;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n248 <= 6'b000000;
else
n248 <= n244;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n252 <= 6'b000000;
else
n252 <= n248;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n256 <= 6'b000000;
else
n256 <= n252;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n260 <= 6'b000000;
else
n260 <= n256;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n265 <= 1'b0;
else
n265 <= n261;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n269 <= 1'b0;
else
n269 <= n265;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n273 <= 1'b0;
else
n273 <= n269;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n277 <= 1'b0;
else
n277 <= n273;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2106 == 1'b1)
n283 <= 6'b000000;
else
n283 <= n280;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n290 <= 1'b0;
else
n290 <= n287;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n295 <= 1'b0;
else
n295 <= n243;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n303 == 1'b1)
n306m <= n227;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n306ra <= n283;
end
assign n306 = n306m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n307 == 1'b1)
n310m <= n227;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n310ra <= n283;
end
assign n310 = n310m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n314 <= 1'b0;
else
n314 <= n291;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2105 == 1'b1)
n320 <= 6'b000000;
else
n320 <= n317;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n327 <= 1'b0;
else
n327 <= n324;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n340 == 1'b1)
n343m <= n227;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n343ra <= n320;
end
assign n343 = n343m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n344 == 1'b1)
n347m <= n227;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n347ra <= n320;
end
assign n347 = n347m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n351 <= 1'b0;
else
n351 <= n328;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n360 <= 1'b0;
else
n360 <= n357;
always @ (posedge clock_c)
if (n2103 == 1'b1)
if (n2104 == 1'b1)
n371 <= 7'b0000000;
else
n371 <= n368;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n380 <= 1'b0;
else
n380 <= n377;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n384 <= 1'b0;
else
n384 <= n376;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n390 <= 16'b0000000000000000;
else
n390 <= n365;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n396 <= 16'b0000000000000000;
else
n396 <= n366;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n402 <= 8'b00000000;
else
n402 <= n391;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n406 <= 8'b00000000;
else
n406 <= n402;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n410 <= 8'b00000000;
else
n410 <= n392;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n414 <= 8'b00000000;
else
n414 <= n410;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n386)
1'b0 : n417 <= 16'b0111111100000000;
1'b1 : n417 <= 16'b0000000010000000;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n425 <= 8'b00000000;
else
n425 <= n421;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n431 <= 8'b00000000;
else
n431 <= n427;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n436 <= 8'b00000000;
else
n436 <= n432;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n442 <= 8'b00000000;
else
n442 <= n438;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n448 <= 8'b00000000;
else
n448 <= n444;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n453 <= 8'b00000000;
else
n453 <= n449;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n460 <= 16'b0000000000000000;
else
n460 <= n456;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n467 <= 16'b0000000000000000;
else
n467 <= n463;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n472 <= 1'b0;
else
n472 <= n385;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n476 <= 1'b0;
else
n476 <= n472;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n480 <= 1'b0;
else
n480 <= n476;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n484 <= 1'b0;
else
n484 <= n480;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n489 <= 6'b000000;
else
n489 <= n485;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n493 <= 6'b000000;
else
n493 <= n489;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n497 <= 6'b000000;
else
n497 <= n493;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n501 <= 6'b000000;
else
n501 <= n497;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n506 <= 1'b0;
else
n506 <= n502;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n510 <= 1'b0;
else
n510 <= n506;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n514 <= 1'b0;
else
n514 <= n510;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n518 <= 1'b0;
else
n518 <= n514;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2100 == 1'b1)
n524 <= 6'b000000;
else
n524 <= n521;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n531 <= 1'b0;
else
n531 <= n528;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n536 <= 1'b0;
else
n536 <= n484;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n544 == 1'b1)
n547m <= n468;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n547ra <= n524;
end
assign n547 = n547m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n548 == 1'b1)
n551m <= n468;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n551ra <= n524;
end
assign n551 = n551m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n555 <= 1'b0;
else
n555 <= n532;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2099 == 1'b1)
n561 <= 6'b000000;
else
n561 <= n558;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n568 <= 1'b0;
else
n568 <= n565;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n581 == 1'b1)
n584m <= n468;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n584ra <= n561;
end
assign n584 = n584m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n585 == 1'b1)
n588m <= n468;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n588ra <= n561;
end
assign n588 = n588m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n592 <= 1'b0;
else
n592 <= n569;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n601 <= 1'b0;
else
n601 <= n598;
always @ (posedge clock_c)
if (n2097 == 1'b1)
if (n2098 == 1'b1)
n612 <= 7'b0000000;
else
n612 <= n609;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n621 <= 1'b0;
else
n621 <= n618;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n625 <= 1'b0;
else
n625 <= n617;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n631 <= 16'b0000000000000000;
else
n631 <= n606;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n637 <= 16'b0000000000000000;
else
n637 <= n607;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n643 <= 8'b00000000;
else
n643 <= n632;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n647 <= 8'b00000000;
else
n647 <= n643;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n651 <= 8'b00000000;
else
n651 <= n633;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n655 <= 8'b00000000;
else
n655 <= n651;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n627)
2'b00 : n658 <= 16'b0111111100000000;
2'b01 : n658 <= 16'b0101101010100101;
2'b10 : n658 <= 16'b0000000010000000;
2'b11 : n658 <= 16'b1010010110100101;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n666 <= 8'b00000000;
else
n666 <= n662;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n672 <= 8'b00000000;
else
n672 <= n668;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n677 <= 8'b00000000;
else
n677 <= n673;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n683 <= 8'b00000000;
else
n683 <= n679;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n689 <= 8'b00000000;
else
n689 <= n685;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n694 <= 8'b00000000;
else
n694 <= n690;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n701 <= 16'b0000000000000000;
else
n701 <= n697;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n708 <= 16'b0000000000000000;
else
n708 <= n704;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n713 <= 1'b0;
else
n713 <= n626;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n717 <= 1'b0;
else
n717 <= n713;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n721 <= 1'b0;
else
n721 <= n717;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n725 <= 1'b0;
else
n725 <= n721;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n730 <= 6'b000000;
else
n730 <= n726;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n734 <= 6'b000000;
else
n734 <= n730;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n738 <= 6'b000000;
else
n738 <= n734;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n742 <= 6'b000000;
else
n742 <= n738;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n747 <= 1'b0;
else
n747 <= n743;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n751 <= 1'b0;
else
n751 <= n747;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n755 <= 1'b0;
else
n755 <= n751;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n759 <= 1'b0;
else
n759 <= n755;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2094 == 1'b1)
n765 <= 6'b000000;
else
n765 <= n762;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n772 <= 1'b0;
else
n772 <= n769;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n777 <= 1'b0;
else
n777 <= n725;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n785 == 1'b1)
n788m <= n709;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n788ra <= n765;
end
assign n788 = n788m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n789 == 1'b1)
n792m <= n709;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n792ra <= n765;
end
assign n792 = n792m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n796 <= 1'b0;
else
n796 <= n773;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2093 == 1'b1)
n802 <= 6'b000000;
else
n802 <= n799;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n809 <= 1'b0;
else
n809 <= n806;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n822 == 1'b1)
n825m <= n709;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n825ra <= n802;
end
assign n825 = n825m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n826 == 1'b1)
n829m <= n709;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n829ra <= n802;
end
assign n829 = n829m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n833 <= 1'b0;
else
n833 <= n810;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n842 <= 1'b0;
else
n842 <= n839;
always @ (posedge clock_c)
if (n2091 == 1'b1)
if (n2092 == 1'b1)
n853 <= 7'b0000000;
else
n853 <= n850;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n862 <= 1'b0;
else
n862 <= n859;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n866 <= 1'b0;
else
n866 <= n858;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n872 <= 16'b0000000000000000;
else
n872 <= n847;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n878 <= 16'b0000000000000000;
else
n878 <= n848;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n884 <= 8'b00000000;
else
n884 <= n873;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n888 <= 8'b00000000;
else
n888 <= n884;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n892 <= 8'b00000000;
else
n892 <= n874;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n896 <= 8'b00000000;
else
n896 <= n892;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n868)
3'b000 : n899 <= 16'b0111111100000000;
3'b001 : n899 <= 16'b0111011011001111;
3'b010 : n899 <= 16'b0101101010100101;
3'b011 : n899 <= 16'b0011000010001001;
3'b100 : n899 <= 16'b0000000010000000;
3'b101 : n899 <= 16'b1100111110001001;
3'b110 : n899 <= 16'b1010010110100101;
3'b111 : n899 <= 16'b1000100111001111;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n907 <= 8'b00000000;
else
n907 <= n903;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n913 <= 8'b00000000;
else
n913 <= n909;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n918 <= 8'b00000000;
else
n918 <= n914;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n924 <= 8'b00000000;
else
n924 <= n920;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n930 <= 8'b00000000;
else
n930 <= n926;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n935 <= 8'b00000000;
else
n935 <= n931;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n942 <= 16'b0000000000000000;
else
n942 <= n938;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n949 <= 16'b0000000000000000;
else
n949 <= n945;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n954 <= 1'b0;
else
n954 <= n867;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n958 <= 1'b0;
else
n958 <= n954;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n962 <= 1'b0;
else
n962 <= n958;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n966 <= 1'b0;
else
n966 <= n962;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n971 <= 6'b000000;
else
n971 <= n967;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n975 <= 6'b000000;
else
n975 <= n971;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n979 <= 6'b000000;
else
n979 <= n975;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n983 <= 6'b000000;
else
n983 <= n979;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n988 <= 1'b0;
else
n988 <= n984;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n992 <= 1'b0;
else
n992 <= n988;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n996 <= 1'b0;
else
n996 <= n992;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1000 <= 1'b0;
else
n1000 <= n996;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2088 == 1'b1)
n1006 <= 6'b000000;
else
n1006 <= n1003;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1013 <= 1'b0;
else
n1013 <= n1010;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1018 <= 1'b0;
else
n1018 <= n966;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1026 == 1'b1)
n1029m <= n950;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1029ra <= n1006;
end
assign n1029 = n1029m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1030 == 1'b1)
n1033m <= n950;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1033ra <= n1006;
end
assign n1033 = n1033m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1037 <= 1'b0;
else
n1037 <= n1014;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2087 == 1'b1)
n1043 <= 6'b000000;
else
n1043 <= n1040;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1050 <= 1'b0;
else
n1050 <= n1047;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1063 == 1'b1)
n1066m <= n950;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1066ra <= n1043;
end
assign n1066 = n1066m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1067 == 1'b1)
n1070m <= n950;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1070ra <= n1043;
end
assign n1070 = n1070m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1074 <= 1'b0;
else
n1074 <= n1051;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1083 <= 1'b0;
else
n1083 <= n1080;
always @ (posedge clock_c)
if (n2085 == 1'b1)
if (n2086 == 1'b1)
n1094 <= 7'b0000000;
else
n1094 <= n1091;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1103 <= 1'b0;
else
n1103 <= n1100;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1107 <= 1'b0;
else
n1107 <= n1099;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1113 <= 16'b0000000000000000;
else
n1113 <= n1088;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1119 <= 16'b0000000000000000;
else
n1119 <= n1089;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1125 <= 8'b00000000;
else
n1125 <= n1114;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1129 <= 8'b00000000;
else
n1129 <= n1125;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1133 <= 8'b00000000;
else
n1133 <= n1115;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1137 <= 8'b00000000;
else
n1137 <= n1133;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n1109)
4'b0000 : n1140 <= 16'b0111111100000000;
4'b0001 : n1140 <= 16'b0111110111100111;
4'b0010 : n1140 <= 16'b0111011011001111;
4'b0011 : n1140 <= 16'b0110101010111000;
4'b0100 : n1140 <= 16'b0101101010100101;
4'b0101 : n1140 <= 16'b0100011110010101;
4'b0110 : n1140 <= 16'b0011000010001001;
4'b0111 : n1140 <= 16'b0001100010000010;
4'b1000 : n1140 <= 16'b0000000010000000;
4'b1001 : n1140 <= 16'b1110011110000010;
4'b1010 : n1140 <= 16'b1100111110001001;
4'b1011 : n1140 <= 16'b1011100010010101;
4'b1100 : n1140 <= 16'b1010010110100101;
4'b1101 : n1140 <= 16'b1001010110111000;
4'b1110 : n1140 <= 16'b1000100111001111;
4'b1111 : n1140 <= 16'b1000001011100111;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1148 <= 8'b00000000;
else
n1148 <= n1144;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1154 <= 8'b00000000;
else
n1154 <= n1150;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1159 <= 8'b00000000;
else
n1159 <= n1155;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1165 <= 8'b00000000;
else
n1165 <= n1161;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1171 <= 8'b00000000;
else
n1171 <= n1167;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1176 <= 8'b00000000;
else
n1176 <= n1172;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1183 <= 16'b0000000000000000;
else
n1183 <= n1179;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1190 <= 16'b0000000000000000;
else
n1190 <= n1186;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1195 <= 1'b0;
else
n1195 <= n1108;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1199 <= 1'b0;
else
n1199 <= n1195;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1203 <= 1'b0;
else
n1203 <= n1199;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1207 <= 1'b0;
else
n1207 <= n1203;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1212 <= 6'b000000;
else
n1212 <= n1208;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1216 <= 6'b000000;
else
n1216 <= n1212;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1220 <= 6'b000000;
else
n1220 <= n1216;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1224 <= 6'b000000;
else
n1224 <= n1220;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1229 <= 1'b0;
else
n1229 <= n1225;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1233 <= 1'b0;
else
n1233 <= n1229;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1237 <= 1'b0;
else
n1237 <= n1233;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1241 <= 1'b0;
else
n1241 <= n1237;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2082 == 1'b1)
n1247 <= 6'b000000;
else
n1247 <= n1244;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1254 <= 1'b0;
else
n1254 <= n1251;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1259 <= 1'b0;
else
n1259 <= n1207;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1267 == 1'b1)
n1270m <= n1191;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1270ra <= n1247;
end
assign n1270 = n1270m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1271 == 1'b1)
n1274m <= n1191;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1274ra <= n1247;
end
assign n1274 = n1274m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1278 <= 1'b0;
else
n1278 <= n1255;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2081 == 1'b1)
n1284 <= 6'b000000;
else
n1284 <= n1281;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1291 <= 1'b0;
else
n1291 <= n1288;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1304 == 1'b1)
n1307m <= n1191;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1307ra <= n1284;
end
assign n1307 = n1307m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1308 == 1'b1)
n1311m <= n1191;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1311ra <= n1284;
end
assign n1311 = n1311m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1315 <= 1'b0;
else
n1315 <= n1292;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1324 <= 1'b0;
else
n1324 <= n1321;
always @ (posedge clock_c)
if (n2079 == 1'b1)
if (n2080 == 1'b1)
n1335 <= 7'b0000000;
else
n1335 <= n1332;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1344 <= 1'b0;
else
n1344 <= n1341;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1348 <= 1'b0;
else
n1348 <= n1340;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1354 <= 16'b0000000000000000;
else
n1354 <= n1329;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1360 <= 16'b0000000000000000;
else
n1360 <= n1330;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1366 <= 8'b00000000;
else
n1366 <= n1355;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1370 <= 8'b00000000;
else
n1370 <= n1366;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1374 <= 8'b00000000;
else
n1374 <= n1356;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1378 <= 8'b00000000;
else
n1378 <= n1374;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n1350)
5'b00000 : n1381 <= 16'b0111111100000000;
5'b00001 : n1381 <= 16'b0111111111110011;
5'b00010 : n1381 <= 16'b0111110111100111;
5'b00011 : n1381 <= 16'b0111101011011010;
5'b00100 : n1381 <= 16'b0111011011001111;
5'b00101 : n1381 <= 16'b0111000011000011;
5'b00110 : n1381 <= 16'b0110101010111000;
5'b00111 : n1381 <= 16'b0110001010101110;
5'b01000 : n1381 <= 16'b0101101010100101;
5'b01001 : n1381 <= 16'b0101000110011101;
5'b01010 : n1381 <= 16'b0100011110010101;
5'b01011 : n1381 <= 16'b0011110010001111;
5'b01100 : n1381 <= 16'b0011000010001001;
5'b01101 : n1381 <= 16'b0010010110000101;
5'b01110 : n1381 <= 16'b0001100010000010;
5'b01111 : n1381 <= 16'b0000110010000000;
5'b10000 : n1381 <= 16'b0000000010000000;
5'b10001 : n1381 <= 16'b1111001110000000;
5'b10010 : n1381 <= 16'b1110011110000010;
5'b10011 : n1381 <= 16'b1101101010000101;
5'b10100 : n1381 <= 16'b1100111110001001;
5'b10101 : n1381 <= 16'b1100001110001111;
5'b10110 : n1381 <= 16'b1011100010010101;
5'b10111 : n1381 <= 16'b1010111010011101;
5'b11000 : n1381 <= 16'b1010010110100101;
5'b11001 : n1381 <= 16'b1001110110101110;
5'b11010 : n1381 <= 16'b1001010110111000;
5'b11011 : n1381 <= 16'b1000111111000011;
5'b11100 : n1381 <= 16'b1000100111001111;
5'b11101 : n1381 <= 16'b1000010111011010;
5'b11110 : n1381 <= 16'b1000001011100111;
5'b11111 : n1381 <= 16'b1000000011110011;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1389 <= 8'b00000000;
else
n1389 <= n1385;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1395 <= 8'b00000000;
else
n1395 <= n1391;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1400 <= 8'b00000000;
else
n1400 <= n1396;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1406 <= 8'b00000000;
else
n1406 <= n1402;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1412 <= 8'b00000000;
else
n1412 <= n1408;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1417 <= 8'b00000000;
else
n1417 <= n1413;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1424 <= 16'b0000000000000000;
else
n1424 <= n1420;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1431 <= 16'b0000000000000000;
else
n1431 <= n1427;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1436 <= 1'b0;
else
n1436 <= n1349;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1440 <= 1'b0;
else
n1440 <= n1436;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1444 <= 1'b0;
else
n1444 <= n1440;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1448 <= 1'b0;
else
n1448 <= n1444;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1453 <= 6'b000000;
else
n1453 <= n1449;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1457 <= 6'b000000;
else
n1457 <= n1453;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1461 <= 6'b000000;
else
n1461 <= n1457;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1465 <= 6'b000000;
else
n1465 <= n1461;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1470 <= 1'b0;
else
n1470 <= n1466;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1474 <= 1'b0;
else
n1474 <= n1470;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1478 <= 1'b0;
else
n1478 <= n1474;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1482 <= 1'b0;
else
n1482 <= n1478;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2076 == 1'b1)
n1488 <= 6'b000000;
else
n1488 <= n1485;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1495 <= 1'b0;
else
n1495 <= n1492;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1500 <= 1'b0;
else
n1500 <= n1448;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1508 == 1'b1)
n1511m <= n1432;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1511ra <= n1488;
end
assign n1511 = n1511m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1512 == 1'b1)
n1515m <= n1432;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1515ra <= n1488;
end
assign n1515 = n1515m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1519 <= 1'b0;
else
n1519 <= n1496;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2075 == 1'b1)
n1525 <= 6'b000000;
else
n1525 <= n1522;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1532 <= 1'b0;
else
n1532 <= n1529;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1545 == 1'b1)
n1548m <= n1432;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1548ra <= n1525;
end
assign n1548 = n1548m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1549 == 1'b1)
n1552m <= n1432;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1552ra <= n1525;
end
assign n1552 = n1552m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1556 <= 1'b0;
else
n1556 <= n1533;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1565 <= 1'b0;
else
n1565 <= n1562;
always @ (posedge clock_c)
if (n2073 == 1'b1)
if (n2074 == 1'b1)
n1576 <= 7'b0000000;
else
n1576 <= n1573;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1585 <= 1'b0;
else
n1585 <= n1582;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1589 <= 1'b0;
else
n1589 <= n1581;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1595 <= 16'b0000000000000000;
else
n1595 <= n1570;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1601 <= 16'b0000000000000000;
else
n1601 <= n1571;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1607 <= 8'b00000000;
else
n1607 <= n1596;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1611 <= 8'b00000000;
else
n1611 <= n1607;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1615 <= 8'b00000000;
else
n1615 <= n1597;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1619 <= 8'b00000000;
else
n1619 <= n1615;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n1591)
6'b000000 : n1622 <= 16'b0111111100000000;
6'b000001 : n1622 <= 16'b0111111111111001;
6'b000010 : n1622 <= 16'b0111111111110011;
6'b000011 : n1622 <= 16'b0111111011101101;
6'b000100 : n1622 <= 16'b0111110111100111;
6'b000101 : n1622 <= 16'b0111110011100000;
6'b000110 : n1622 <= 16'b0111101011011010;
6'b000111 : n1622 <= 16'b0111100011010100;
6'b001000 : n1622 <= 16'b0111011011001111;
6'b001001 : n1622 <= 16'b0111001111001001;
6'b001010 : n1622 <= 16'b0111000011000011;
6'b001011 : n1622 <= 16'b0110110110111110;
6'b001100 : n1622 <= 16'b0110101010111000;
6'b001101 : n1622 <= 16'b0110011010110011;
6'b001110 : n1622 <= 16'b0110001010101110;
6'b001111 : n1622 <= 16'b0101111010101010;
6'b010000 : n1622 <= 16'b0101101010100101;
6'b010001 : n1622 <= 16'b0101010110100001;
6'b010010 : n1622 <= 16'b0101000110011101;
6'b010011 : n1622 <= 16'b0100110010011001;
6'b010100 : n1622 <= 16'b0100011110010101;
6'b010101 : n1622 <= 16'b0100000110010010;
6'b010110 : n1622 <= 16'b0011110010001111;
6'b010111 : n1622 <= 16'b0011011010001100;
6'b011000 : n1622 <= 16'b0011000010001001;
6'b011001 : n1622 <= 16'b0010101110000111;
6'b011010 : n1622 <= 16'b0010010110000101;
6'b011011 : n1622 <= 16'b0001111110000011;
6'b011100 : n1622 <= 16'b0001100010000010;
6'b011101 : n1622 <= 16'b0001001010000001;
6'b011110 : n1622 <= 16'b0000110010000000;
6'b011111 : n1622 <= 16'b0000011010000000;
6'b100000 : n1622 <= 16'b0000000010000000;
6'b100001 : n1622 <= 16'b1111100110000000;
6'b100010 : n1622 <= 16'b1111001110000000;
6'b100011 : n1622 <= 16'b1110110110000001;
6'b100100 : n1622 <= 16'b1110011110000010;
6'b100101 : n1622 <= 16'b1110000010000011;
6'b100110 : n1622 <= 16'b1101101010000101;
6'b100111 : n1622 <= 16'b1101010010000111;
6'b101000 : n1622 <= 16'b1100111110001001;
6'b101001 : n1622 <= 16'b1100100110001100;
6'b101010 : n1622 <= 16'b1100001110001111;
6'b101011 : n1622 <= 16'b1011111010010010;
6'b101100 : n1622 <= 16'b1011100010010101;
6'b101101 : n1622 <= 16'b1011001110011001;
6'b101110 : n1622 <= 16'b1010111010011101;
6'b101111 : n1622 <= 16'b1010101010100001;
6'b110000 : n1622 <= 16'b1010010110100101;
6'b110001 : n1622 <= 16'b1010000110101010;
6'b110010 : n1622 <= 16'b1001110110101110;
6'b110011 : n1622 <= 16'b1001100110110011;
6'b110100 : n1622 <= 16'b1001010110111000;
6'b110101 : n1622 <= 16'b1001001010111110;
6'b110110 : n1622 <= 16'b1000111111000011;
6'b110111 : n1622 <= 16'b1000110011001001;
6'b111000 : n1622 <= 16'b1000100111001111;
6'b111001 : n1622 <= 16'b1000011111010100;
6'b111010 : n1622 <= 16'b1000010111011010;
6'b111011 : n1622 <= 16'b1000001111100000;
6'b111100 : n1622 <= 16'b1000001011100111;
6'b111101 : n1622 <= 16'b1000000111101101;
6'b111110 : n1622 <= 16'b1000000011110011;
6'b111111 : n1622 <= 16'b1000000011111001;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1630 <= 8'b00000000;
else
n1630 <= n1626;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1636 <= 8'b00000000;
else
n1636 <= n1632;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1641 <= 8'b00000000;
else
n1641 <= n1637;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1647 <= 8'b00000000;
else
n1647 <= n1643;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1653 <= 8'b00000000;
else
n1653 <= n1649;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1658 <= 8'b00000000;
else
n1658 <= n1654;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1665 <= 16'b0000000000000000;
else
n1665 <= n1661;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1672 <= 16'b0000000000000000;
else
n1672 <= n1668;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1677 <= 1'b0;
else
n1677 <= n1590;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1681 <= 1'b0;
else
n1681 <= n1677;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1685 <= 1'b0;
else
n1685 <= n1681;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1689 <= 1'b0;
else
n1689 <= n1685;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1694 <= 6'b000000;
else
n1694 <= n1690;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1698 <= 6'b000000;
else
n1698 <= n1694;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1702 <= 6'b000000;
else
n1702 <= n1698;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1706 <= 6'b000000;
else
n1706 <= n1702;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1711 <= 1'b0;
else
n1711 <= n1707;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1715 <= 1'b0;
else
n1715 <= n1711;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1719 <= 1'b0;
else
n1719 <= n1715;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1723 <= 1'b0;
else
n1723 <= n1719;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2070 == 1'b1)
n1729 <= 6'b000000;
else
n1729 <= n1726;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1736 <= 1'b0;
else
n1736 <= n1733;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1741 <= 1'b0;
else
n1741 <= n1689;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1749 == 1'b1)
n1752m <= n1673;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1752ra <= n1729;
end
assign n1752 = n1752m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1753 == 1'b1)
n1756m <= n1673;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1756ra <= n1729;
end
assign n1756 = n1756m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1760 <= 1'b0;
else
n1760 <= n1737;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2069 == 1'b1)
n1766 <= 6'b000000;
else
n1766 <= n1763;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1773 <= 1'b0;
else
n1773 <= n1770;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1786 == 1'b1)
n1789m <= n1673;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1789ra <= n1766;
end
assign n1789 = n1789m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1790 == 1'b1)
n1793m <= n1673;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1793ra <= n1766;
end
assign n1793 = n1793m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1797 <= 1'b0;
else
n1797 <= n1774;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1806 <= 1'b0;
else
n1806 <= n1803;
always @ (posedge clock_c)
if (n2067 == 1'b1)
if (n2068 == 1'b1)
n1817 <= 7'b0000000;
else
n1817 <= n1814;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1826 <= 1'b0;
else
n1826 <= n1823;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1830 <= 1'b0;
else
n1830 <= n1822;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1836 <= 16'b0000000000000000;
else
n1836 <= n1811;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1842 <= 16'b0000000000000000;
else
n1842 <= n1812;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1848 <= 8'b00000000;
else
n1848 <= n1837;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1852 <= 8'b00000000;
else
n1852 <= n1848;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1856 <= 8'b00000000;
else
n1856 <= n1838;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1860 <= 8'b00000000;
else
n1860 <= n1856;
always @ (posedge clock_c)
if (n2061 == 1'b1)
case (n1832)
7'b0000000 : n1863 <= 16'b0111111100000000;
7'b0000001 : n1863 <= 16'b0111111111111100;
7'b0000010 : n1863 <= 16'b0111111111111001;
7'b0000011 : n1863 <= 16'b0111111111110110;
7'b0000100 : n1863 <= 16'b0111111111110011;
7'b0000101 : n1863 <= 16'b0111111111110000;
7'b0000110 : n1863 <= 16'b0111111011101101;
7'b0000111 : n1863 <= 16'b0111111011101010;
7'b0001000 : n1863 <= 16'b0111110111100111;
7'b0001001 : n1863 <= 16'b0111110011100011;
7'b0001010 : n1863 <= 16'b0111110011100000;
7'b0001011 : n1863 <= 16'b0111101111011101;
7'b0001100 : n1863 <= 16'b0111101011011010;
7'b0001101 : n1863 <= 16'b0111100111010111;
7'b0001110 : n1863 <= 16'b0111100011010100;
7'b0001111 : n1863 <= 16'b0111011111010001;
7'b0010000 : n1863 <= 16'b0111011011001111;
7'b0010001 : n1863 <= 16'b0111010111001100;
7'b0010010 : n1863 <= 16'b0111001111001001;
7'b0010011 : n1863 <= 16'b0111001011000110;
7'b0010100 : n1863 <= 16'b0111000011000011;
7'b0010101 : n1863 <= 16'b0110111111000000;
7'b0010110 : n1863 <= 16'b0110110110111110;
7'b0010111 : n1863 <= 16'b0110110010111011;
7'b0011000 : n1863 <= 16'b0110101010111000;
7'b0011001 : n1863 <= 16'b0110100010110110;
7'b0011010 : n1863 <= 16'b0110011010110011;
7'b0011011 : n1863 <= 16'b0110010010110001;
7'b0011100 : n1863 <= 16'b0110001010101110;
7'b0011101 : n1863 <= 16'b0110000010101100;
7'b0011110 : n1863 <= 16'b0101111010101010;
7'b0011111 : n1863 <= 16'b0101110010100111;
7'b0100000 : n1863 <= 16'b0101101010100101;
7'b0100001 : n1863 <= 16'b0101100010100011;
7'b0100010 : n1863 <= 16'b0101010110100001;
7'b0100011 : n1863 <= 16'b0101001110011111;
7'b0100100 : n1863 <= 16'b0101000110011101;
7'b0100101 : n1863 <= 16'b0100111010011011;
7'b0100110 : n1863 <= 16'b0100110010011001;
7'b0100111 : n1863 <= 16'b0100100110010111;
7'b0101000 : n1863 <= 16'b0100011110010101;
7'b0101001 : n1863 <= 16'b0100010010010011;
7'b0101010 : n1863 <= 16'b0100000110010010;
7'b0101011 : n1863 <= 16'b0011111110010000;
7'b0101100 : n1863 <= 16'b0011110010001111;
7'b0101101 : n1863 <= 16'b0011100110001101;
7'b0101110 : n1863 <= 16'b0011011010001100;
7'b0101111 : n1863 <= 16'b0011001110001010;
7'b0110000 : n1863 <= 16'b0011000010001001;
7'b0110001 : n1863 <= 16'b0010111010001000;
7'b0110010 : n1863 <= 16'b0010101110000111;
7'b0110011 : n1863 <= 16'b0010100010000110;
7'b0110100 : n1863 <= 16'b0010010110000101;
7'b0110101 : n1863 <= 16'b0010001010000100;
7'b0110110 : n1863 <= 16'b0001111110000011;
7'b0110111 : n1863 <= 16'b0001110010000011;
7'b0111000 : n1863 <= 16'b0001100010000010;
7'b0111001 : n1863 <= 16'b0001010110000001;
7'b0111010 : n1863 <= 16'b0001001010000001;
7'b0111011 : n1863 <= 16'b0000111110000000;
7'b0111100 : n1863 <= 16'b0000110010000000;
7'b0111101 : n1863 <= 16'b0000100110000000;
7'b0111110 : n1863 <= 16'b0000011010000000;
7'b0111111 : n1863 <= 16'b0000001110000000;
7'b1000000 : n1863 <= 16'b0000000010000000;
7'b1000001 : n1863 <= 16'b1111110010000000;
7'b1000010 : n1863 <= 16'b1111100110000000;
7'b1000011 : n1863 <= 16'b1111011010000000;
7'b1000100 : n1863 <= 16'b1111001110000000;
7'b1000101 : n1863 <= 16'b1111000010000000;
7'b1000110 : n1863 <= 16'b1110110110000001;
7'b1000111 : n1863 <= 16'b1110101010000001;
7'b1001000 : n1863 <= 16'b1110011110000010;
7'b1001001 : n1863 <= 16'b1110001110000011;
7'b1001010 : n1863 <= 16'b1110000010000011;
7'b1001011 : n1863 <= 16'b1101110110000100;
7'b1001100 : n1863 <= 16'b1101101010000101;
7'b1001101 : n1863 <= 16'b1101011110000110;
7'b1001110 : n1863 <= 16'b1101010010000111;
7'b1001111 : n1863 <= 16'b1101000110001000;
7'b1010000 : n1863 <= 16'b1100111110001001;
7'b1010001 : n1863 <= 16'b1100110010001010;
7'b1010010 : n1863 <= 16'b1100100110001100;
7'b1010011 : n1863 <= 16'b1100011010001101;
7'b1010100 : n1863 <= 16'b1100001110001111;
7'b1010101 : n1863 <= 16'b1100000010010000;
7'b1010110 : n1863 <= 16'b1011111010010010;
7'b1010111 : n1863 <= 16'b1011101110010011;
7'b1011000 : n1863 <= 16'b1011100010010101;
7'b1011001 : n1863 <= 16'b1011011010010111;
7'b1011010 : n1863 <= 16'b1011001110011001;
7'b1011011 : n1863 <= 16'b1011000110011011;
7'b1011100 : n1863 <= 16'b1010111010011101;
7'b1011101 : n1863 <= 16'b1010110010011111;
7'b1011110 : n1863 <= 16'b1010101010100001;
7'b1011111 : n1863 <= 16'b1010011110100011;
7'b1100000 : n1863 <= 16'b1010010110100101;
7'b1100001 : n1863 <= 16'b1010001110100111;
7'b1100010 : n1863 <= 16'b1010000110101010;
7'b1100011 : n1863 <= 16'b1001111110101100;
7'b1100100 : n1863 <= 16'b1001110110101110;
7'b1100101 : n1863 <= 16'b1001101110110001;
7'b1100110 : n1863 <= 16'b1001100110110011;
7'b1100111 : n1863 <= 16'b1001011110110110;
7'b1101000 : n1863 <= 16'b1001010110111000;
7'b1101001 : n1863 <= 16'b1001001110111011;
7'b1101010 : n1863 <= 16'b1001001010111110;
7'b1101011 : n1863 <= 16'b1001000011000000;
7'b1101100 : n1863 <= 16'b1000111111000011;
7'b1101101 : n1863 <= 16'b1000110111000110;
7'b1101110 : n1863 <= 16'b1000110011001001;
7'b1101111 : n1863 <= 16'b1000101011001100;
7'b1110000 : n1863 <= 16'b1000100111001111;
7'b1110001 : n1863 <= 16'b1000100011010001;
7'b1110010 : n1863 <= 16'b1000011111010100;
7'b1110011 : n1863 <= 16'b1000011011010111;
7'b1110100 : n1863 <= 16'b1000010111011010;
7'b1110101 : n1863 <= 16'b1000010011011101;
7'b1110110 : n1863 <= 16'b1000001111100000;
7'b1110111 : n1863 <= 16'b1000001111100011;
7'b1111000 : n1863 <= 16'b1000001011100111;
7'b1111001 : n1863 <= 16'b1000000111101010;
7'b1111010 : n1863 <= 16'b1000000111101101;
7'b1111011 : n1863 <= 16'b1000000011110000;
7'b1111100 : n1863 <= 16'b1000000011110011;
7'b1111101 : n1863 <= 16'b1000000011110110;
7'b1111110 : n1863 <= 16'b1000000011111001;
7'b1111111 : n1863 <= 16'b1000000011111100;
endcase
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1871 <= 8'b00000000;
else
n1871 <= n1867;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1877 <= 8'b00000000;
else
n1877 <= n1873;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1882 <= 8'b00000000;
else
n1882 <= n1878;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1888 <= 8'b00000000;
else
n1888 <= n1884;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1894 <= 8'b00000000;
else
n1894 <= n1890;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1899 <= 8'b00000000;
else
n1899 <= n1895;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1906 <= 16'b0000000000000000;
else
n1906 <= n1902;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1913 <= 16'b0000000000000000;
else
n1913 <= n1909;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1918 <= 1'b0;
else
n1918 <= n1831;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1922 <= 1'b0;
else
n1922 <= n1918;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1926 <= 1'b0;
else
n1926 <= n1922;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1930 <= 1'b0;
else
n1930 <= n1926;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1935 <= 6'b000000;
else
n1935 <= n1931;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1939 <= 6'b000000;
else
n1939 <= n1935;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1943 <= 6'b000000;
else
n1943 <= n1939;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1947 <= 6'b000000;
else
n1947 <= n1943;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1952 <= 1'b0;
else
n1952 <= n1948;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1956 <= 1'b0;
else
n1956 <= n1952;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1960 <= 1'b0;
else
n1960 <= n1956;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1964 <= 1'b0;
else
n1964 <= n1960;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2064 == 1'b1)
n1970 <= 6'b000000;
else
n1970 <= n1967;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1977 <= 1'b0;
else
n1977 <= n1974;
always @ (posedge clock_c)
begin
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n1982 <= 1'b0;
else
n1982 <= n1930;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1990 == 1'b1)
n1993m <= n1914;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1993ra <= n1970;
end
assign n1993 = n1993m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n1994 == 1'b1)
n1997m <= n1914;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n1997ra <= n1970;
end
assign n1997 = n1997m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n2001 <= 1'b0;
else
n2001 <= n1978;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2063 == 1'b1)
n2007 <= 6'b000000;
else
n2007 <= n2004;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n2014 <= 1'b0;
else
n2014 <= n2011;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n2027 == 1'b1)
n2030m <= n1914;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n2030ra <= n2007;
end
assign n2030 = n2030m;
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
if (n2031 == 1'b1)
n2034m <= n1914;
end
always @ (posedge clock_c)
if (n2061 == 1'b1) begin
n2034ra <= n2007;
end
assign n2034 = n2034m;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n2038 <= 1'b0;
else
n2038 <= n2015;
always @ (posedge clock_c)
if (n2061 == 1'b1)
if (n2062 == 1'b1)
n2047 <= 1'b0;
else
n2047 <= n2044;
endmodule
|
// Universal Shift Register
// Created by David Tran
// Version 0.0.0.0
// Last Modified 04-03-2014
`include "shift_register_4_beh.v"
`timescale 1 ns / 1 ps
//{{ Section below this comment is automatically maintained
// and may be overwritten
//{module {shift_register_4_beh_tb}}
module shift_register_4_beh_tb (clear);
input clear ;
wire clear ;
wire [3:0] a_par;
reg [3:0] i_par;
reg msb_in;
reg lsb_in;
reg [0:0] t_i_par_0[10000:0]; //10000 rows should be more than sufficient
reg [0:0] t_i_par_1[10000:0]; //10000 rows should be more than sufficient
reg [0:0] t_i_par_2[10000:0]; //10000 rows should be more than sufficient
reg [0:0] t_i_par_3[10000:0]; //10000 rows should be more than sufficient
reg [0:0] t_msb_in[10000:0]; //10000 rows should be more than sufficient
reg [0:0] t_lsb_in[10000:0]; //10000 rows should be more than sufficient
reg t_clock,s0,s1;
reg [31:0] vectornum;
//}} End of automatically maintained section
// -- Enter your statements here -- //
initial #20000 $finish;
initial
begin
t_clock=0;
forever #5 t_clock=~t_clock;
end
initial
begin
s1=0;
forever #100 s1=~s1;
end
initial
begin
s0=0;
forever #200 s0=~s0;
end
initial
begin
$readmemb("bit_str_i_par_0.txt",t_i_par_0);
$readmemb("bit_str_i_par_1.txt",t_i_par_1);
$readmemb("bit_str_i_par_2.txt",t_i_par_2);
$readmemb("bit_str_i_par_3.txt",t_i_par_3);
$readmemb("bit_str_msb_in.txt",t_msb_in);
$readmemb("bit_str_lsb_in.txt",t_lsb_in);
vectornum=0; //initialize the index of testvector to 0
end
always @(negedge t_clock)
begin
i_par[0]<=t_i_par_0[vectornum];
i_par[1]<=t_i_par_1[vectornum];
i_par[2]<=t_i_par_2[vectornum];
i_par[3]<=t_i_par_3[vectornum];
msb_in<=t_msb_in[vectornum];
lsb_in<=t_lsb_in[vectornum];
vectornum<=vectornum+1;
end
shift_register_4_beh M0 (a_par, i_par, s1, s0, msb_in, lsb_in, t_clock, clear);
initial
begin
$monitor("time=%05d",$time,,"| CurState:%04b Input:%b|%04b|%b S:%b%b Clear:%b", a_par, msb_in, i_par, lsb_in, s1, s0, clear);
#20000
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Memory Interface Top Level
// File : memif_toplevel.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the integration of all the memory
// interface modules described below.
//
// The signal which have the suffic as c_ indicates that
// this are generated from crt module, if g_ indicate
// that this are generated from graph module, if h_ indicates
// its generated from host module, if a_ indicates that
// this are generated from attribute module and if m_ then
// signals are generated from memory module.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
// cpu_rd.v
// cpu_wr.v (sm_cpuwr.v)
// sm_txt_crt.v
// sm_graphic_crt.v
// sm_data_comp.v
// sm_crt_ffwr_rd.v
// crt_fifo_logic.v
// crt_addr_gen.v
// att_text_blk.v
// sm_arb.v
// sm_ref.v
// memif_reg_dec.v
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module memif_toplevel
(
input t_data_ready_n,
input t_mem_clk,
input t_crt_clk,
input svga_ack,
input c_misc_b1,
input c_split_screen_pulse,
input c_vde,
input c_pre_vde,
input c_row_end,
input c_cr17_b0,
input c_cr17_b1,
input c_cr17_b5,
input c_cr17_b6,
input c_cr14_b6,
input [4:0] c_slc_op,
input c_crt_line_end,
input c_dclk_en,
input c_vdisp_end,
input c_crt_ff_read,
input c_vert_blank,
input c_cursory,
input c_uln_on,
input c_cr0c_f13_22_hit,
input g_memrd,
input h_reset_n,
input h_iord,
input h_iowr,
input h_io_16,
input [15:0] h_io_addr,
input h_svga_sel,
input [19:0] val_mrdwr_addr,
input [7:0] fin_plane_sel,
input [3:0] g_plane_sel,
input g_memwr,
input g_gr06_b0,
input g_gr05_b4,
input g_cpu_cycle_done,
input g_cpu_data_done,
input [31:0] m_t_mem_data_in,
input [31:0] g_graph_data_out,
input [15:0] h_io_dbus,
input color_mode,
input [5:0] c_crtc_index,
input [7:0] c_ext_index,
input [7:0] c_hde, // Numebr of characters on scan line
input color_256_mode, // We are in mode 13
input vga_en,
input mem_ready, // Ready signal from MC
// was h_io_dbus
output [7:0] memif_index_qout,
output [7:0] reg_sr0_qout,
output [7:0] reg_sr1_qout,
output [7:0] reg_sr2_qout,
output [7:0] reg_sr3_qout,
output [7:0] reg_sr4_qout,
output [7:0] reg_cr0c_qout,
output [7:0] reg_cr0d_qout,
output [7:0] reg_cr0e_qout,
output [7:0] reg_cr0f_qout,
output [7:0] reg_cr13_qout,
output [31:0] g_graph_data_in,
output [31:0] m_t_mem_data_out,
output reg [20:3] m_t_mem_addr,
output [7:0] m_t_mwe_n,
output m_t_svga_req,
output m_ready_n,
output [36:0] m_att_data,
output m_cpu_ff_full,
output m_sr00_b0,
output m_sr01_b1,
output [3:0] m_sr02_b,
output m_sr04_b3,
output m_sr01_b4,
output m_sr01_b3,
output m_sr01_b2,
output m_sr01_b0,
output m_sr01_b5,
output m_chain4,
output m_extend_mem,
output m_odd_even,
output m_planar,
output m_dec_sr00_sr06,
output m_dec_sr07,
output m_memrd_ready_n,
output m_cpurd_state1,
output m_mrd_mwr_n,
output m_soft_rst_n,
output m_cpurd_s0,
output cpu_rd_gnt,
output mem_mod_rd_en_hb,
output mem_mod_rd_en_lb
);
wire cpu_rd_req;
wire cpu_rd_svga_req;
wire cpu_wr_gnt;
wire crt_req;
wire cpu_wr_req;
wire cpu_wr_svga_req;
wire ff_writeable_crt;
wire crt_gnt;
wire text_mode;
wire dum_ff_rd_cnt0;
wire txt_crt_svga_req;
wire dum_ff_read;
wire enrd_tx_addr;
wire enrd_font_addr;
wire [2:0] tx_cnt_qout;
wire graphic_mode;
wire gra_crt_svga_req;
wire enrd_gra_addr;
wire cursor_addr_ok;
wire cursor_addr_ok1;
wire data_complete;
wire crt_ff_write;
wire cursorx;
wire crt_fwr0;
wire crt_fwr15;
wire crt_fwr16;
wire crt_fwr31;
wire crt_fwr0_low;
wire crt_fwr15_low;
wire crt_fwr16_low;
wire crt_fwr15_high;
wire crt_fwr31_low;
wire crt_fwr31_high;
wire crt_frd0;
wire crt_frd16;
wire crt_frd15;
wire crt_frd31;
wire crt_ff_rda;
wire crt_ff_rdb;
wire tx_ff_wra_low;
wire tx_ff_wra_high;
wire tx_ff_wrb_low;
wire tx_ff_wrb_high;
wire gr_ff_wra;
wire gr_ff_wrb;
wire [4:0] att_text_out;
wire sync_crt_line_end;
wire a_empty;
wire b_empty;
wire a_full_done;
wire b_full_done;
wire tx_cnt_inc;
wire gra_cnt_inc;
wire [8:0] ff_asic_out;
wire crt_fwr7_low;
wire crt_fwr7_high;
wire crt_fwr23_low;
wire crt_fwr23_high;
wire m_sr04_b1;
wire en_cpurd_addr;
wire enwr_cpu_ad_da_pl;
wire crt_frd1;
wire crt_frd17;
wire cpu_arb_wr;
wire start_txt_sm;
wire [31:0] cpuwr_mem_data_out;
wire [7:0] cpuwr_mwe_n;
wire [19:0] fin_crt_addr;
wire [19:0] font_addr;
wire [19:0] cpuwr_mem_addr;
wire sync_c_crt_line_end;
wire cpu_mem_wr;
wire extend_font_addr;
wire sync_pre_vde;
// From att_text_blk
wire decode_c0todf;
wire int_x5;
wire blank;
wire under_line;
wire reverse;
assign m_t_mem_data_out = cpuwr_mem_data_out;
assign m_t_mwe_n = cpuwr_mwe_n;
always @*
casex ({en_cpurd_addr, enwr_cpu_ad_da_pl, (enrd_tx_addr | enrd_gra_addr),
(enrd_font_addr & vga_en)}) // synopsys full_case parallel_case
4'b1xxx: m_t_mem_addr = val_mrdwr_addr[17:0];
4'b01xx: m_t_mem_addr = cpuwr_mem_addr[17:0];
4'b001x: m_t_mem_addr = fin_crt_addr[17:0];
4'b0001: m_t_mem_addr = font_addr[17:0];
// synopsys synthesis off
// in simulation, these addresses are read back from memory. If the
// memory has not been loaded, then they will be X and hose the
// memory. Thus turn this off only for synthesis to get better gates
// from the tools
default: m_t_mem_addr = 18'b0;
// synopsys synthesis on
endcase // casex({encpurd_addr, enwr_cpu_ad_da_pl, (enrd_tx_addr | enrd_gra_addr),...
cpu_rd CPURD
(
.g_memwr (g_memwr),
.g_cpu_cycle_done (g_cpu_cycle_done),
.g_cpu_data_done (g_cpu_data_done),
.c_misc_b1 (c_misc_b1),
.h_svga_sel (h_svga_sel),
.hreset_n (h_reset_n),
.g_memrd (g_memrd),
.cpu_rd_gnt (cpu_rd_gnt),
.svga_ack (svga_ack),
.t_data_ready_n (t_data_ready_n),
.mem_clk (t_mem_clk),
.cpu_rd_req (cpu_rd_req),
.cpu_rd_svga_req (cpu_rd_svga_req),
.m_t_mem_data_in (m_t_mem_data_in),
.g_graph_data_in (g_graph_data_in),
.m_memrd_ready_n (m_memrd_ready_n),
.m_cpurd_state1 (m_cpurd_state1),
.m_cpurd_s0 (m_cpurd_s0),
.en_cpurd_addr (en_cpurd_addr)
);
cpu_wr CPUWR
(
.cpu_rd_gnt (cpu_rd_gnt),
.hreset_n (h_reset_n),
.cpu_wr_gnt (cpu_wr_gnt),
.crt_req (crt_req),
.svga_ack (svga_ack),
.mem_clk (t_mem_clk),
.cpu_wr_req (cpu_wr_req),
.cpu_wr_svga_req (cpu_wr_svga_req),
.val_mrdwr_addr (val_mrdwr_addr),
.fin_plane_sel (fin_plane_sel),
.cpuwr_mwe_n (cpuwr_mwe_n),
.cpuwr_mem_addr (cpuwr_mem_addr),
.cpuwr_mem_data_out (cpuwr_mem_data_out),
.g_memwr (g_memwr),
.g_graph_data_out (g_graph_data_out),
.m_cpu_ff_full (m_cpu_ff_full),
.cpu_mem_wr (cpu_mem_wr),
.enwr_cpu_ad_da_pl (enwr_cpu_ad_da_pl),
.cpu_arb_wr (cpu_arb_wr)
);
sm_txt_crt SMTXT
(
.start_txt_sm (start_txt_sm),
.sync_c_crt_line_end (sync_crt_line_end),
.hreset_n (h_reset_n),
.crt_gnt (crt_gnt),
.svga_ack (svga_ack),
.mem_clk (t_mem_clk),
.text_mode (text_mode),
.data_complete (data_complete),
.c_hde (c_hde),
.dum_ff_rd_cnt0 (dum_ff_rd_cnt0),
.txt_crt_svga_req (txt_crt_svga_req),
.dum_ff_read (dum_ff_read),
.enrd_tx_addr (enrd_tx_addr),
.enrd_font_addr (enrd_font_addr),
.extend_font_addr (extend_font_addr),
.tx_cnt_inc (tx_cnt_inc)
);
sm_graphic_crt SMGRA
(
.sync_c_crt_line_end (sync_crt_line_end),
.hreset_n (h_reset_n),
.ff_writeable_crt (ff_writeable_crt),
.crt_gnt (crt_gnt),
.svga_ack (svga_ack),
.mem_clk (t_mem_clk),
.graphic_mode (graphic_mode),
.data_complete (data_complete),
.c_hde (c_hde),
.color_256_mode (color_256_mode),
.gra_crt_svga_req (gra_crt_svga_req),
.enrd_gra_addr (enrd_gra_addr),
.gra_cnt_inc (gra_cnt_inc)
// .probe (probe_crt[30:0])
);
sm_data_comp SMDATA
(
.sync_c_crt_line_end (sync_crt_line_end),
.cpu_arb_wr (cpu_arb_wr),
.t_data_ready_n (t_data_ready_n),
.h_reset_n (h_reset_n),
.t_mem_clk (t_mem_clk),
.gra_crt_svga_req (gra_crt_svga_req),
.txt_crt_svga_req (txt_crt_svga_req),
.cpu_rd_svga_req (cpu_rd_svga_req),
.cpu_wr_svga_req (cpu_wr_svga_req),
.text_mode (text_mode),
.cursor_addr_ok (cursor_addr_ok),
.cursor_addr_ok1 (cursor_addr_ok1),
.data_complete (data_complete),
.crt_ff_write (crt_ff_write),
.m_t_svga_req (m_t_svga_req),
.m_mrd_mwr_n (m_mrd_mwr_n)
);
sm_crt_ffwr_rd FFWRRD
(
.crt_frd1 (crt_frd1),
.crt_frd17 (crt_frd17),
.crt_fwr7_low (crt_fwr7_low),
.crt_fwr7_high (crt_fwr7_high),
.crt_fwr23_low (crt_fwr23_low),
.crt_fwr23_high (crt_fwr23_high),
.hreset_n (h_reset_n),
.sync_pre_vde (sync_pre_vde),
.crt_ff_write (crt_ff_write),
.c_crt_line_end (c_crt_line_end),
.crt_fwr0 (crt_fwr0),
.crt_fwr15 (crt_fwr15),
.crt_fwr16 (crt_fwr16),
.crt_fwr31 (crt_fwr31),
.crt_fwr0_low (crt_fwr0_low),
.crt_fwr15_low (crt_fwr15_low),
.crt_fwr16_low (crt_fwr16_low),
.crt_fwr15_high (crt_fwr15_high),
.crt_fwr31_low (crt_fwr31_low),
.crt_fwr31_high (crt_fwr31_high),
.graphic_mode (graphic_mode),
.text_mode (text_mode),
.mem_clk (t_mem_clk),
.t_crt_clk (t_crt_clk),
.c_dclk_en (c_dclk_en),
.c_vdisp_end (c_vdisp_end),
.c_crt_ff_read (c_crt_ff_read),
.crt_frd16 (crt_frd16),
.crt_frd15 (crt_frd15),
.crt_frd31 (crt_frd31),
.sync_crt_line_end (sync_crt_line_end),
.crt_ff_rda (crt_ff_rda),
.crt_ff_rdb (crt_ff_rdb),
.tx_ff_wra_low (tx_ff_wra_low),
.tx_ff_wra_high (tx_ff_wra_high),
.tx_ff_wrb_low (tx_ff_wrb_low),
.tx_ff_wrb_high (tx_ff_wrb_high),
.gr_ff_wra (gr_ff_wra),
.gr_ff_wrb (gr_ff_wrb),
.ff_writeable_crt (ff_writeable_crt),
.crt_req (crt_req),
.a_empty (a_empty),
.b_empty (b_empty),
.a_full_done (a_full_done),
.b_full_done (b_full_done),
.start_txt_sm (start_txt_sm)
);
crt_fifo_logic FFLOGIC
(
.sync_c_crt_line_end (sync_crt_line_end),
.hreset_n (h_reset_n),
.mem_clk (t_mem_clk),
.t_crt_clk (t_crt_clk),
.c_dclk_en (c_dclk_en),
.crt_ff_write (crt_ff_write),
.c_crt_line_end (c_crt_line_end),
.c_crt_ff_read (c_crt_ff_read),
.dum_ff_read (dum_ff_read),
.enrd_font_addr (enrd_font_addr),
.text_mode (text_mode),
.crt_ff_rda (crt_ff_rda),
.crt_ff_rdb (crt_ff_rdb),
.gr_ff_wra (gr_ff_wra),
.gr_ff_wrb (gr_ff_wrb),
.tx_ff_wra_high (tx_ff_wra_high),
.tx_ff_wra_low (tx_ff_wra_low),
.tx_ff_wrb_high (tx_ff_wrb_high),
.tx_ff_wrb_low (tx_ff_wrb_low),
.extend_font_addr (extend_font_addr),
.crt_frd0 (crt_frd0),
.crt_frd15 (crt_frd15),
.crt_frd16 (crt_frd16),
.crt_frd31 (crt_frd31),
.crt_fwr0 (crt_fwr0),
.crt_fwr15 (crt_fwr15),
.crt_fwr16 (crt_fwr16),
.crt_fwr31 (crt_fwr31),
.crt_fwr0_low (crt_fwr0_low),
.crt_fwr15_high (crt_fwr15_high),
.crt_fwr15_low (crt_fwr15_low),
.crt_fwr16_low (crt_fwr16_low),
.crt_fwr31_high (crt_fwr31_high),
.crt_fwr31_low (crt_fwr31_low),
.dum_ff_rd_cnt0 (dum_ff_rd_cnt0),
.att_text_out (att_text_out),
.m_att_data (m_att_data),
.m_t_mem_data_in (m_t_mem_data_in),
.ff_asic_out (ff_asic_out),
.crt_fwr7_low (crt_fwr7_low),
.crt_fwr7_high (crt_fwr7_high),
.crt_fwr23_low (crt_fwr23_low),
.crt_fwr23_high (crt_fwr23_high),
.crt_frd1 (crt_frd1),
.crt_frd17 (crt_frd17)
);
crt_addr_gen ADDGEN
(
.en_cpurd_addr (en_cpurd_addr),
.enwr_cpu_ad_da_pl (enwr_cpu_ad_da_pl),
.m_sr04_b1 (m_sr04_b1),
.tx_cnt_inc (tx_cnt_inc),
.gra_cnt_inc (gra_cnt_inc),
.hreset_n (h_reset_n),
.c_split_screen_pulse (c_split_screen_pulse),
.c_vde (c_vde),
.c_pre_vde (c_pre_vde),
.c_row_end (c_row_end),
.c_crt_line_end (c_crt_line_end),
.sync_c_crt_line_end (sync_crt_line_end),
.mem_clk (t_mem_clk),
.t_crt_clk (t_crt_clk),
.text_mode (text_mode),
.c_cr17_b0 (c_cr17_b0),
.c_cr17_b1 (c_cr17_b1),
.c_cr17_b5 (c_cr17_b5),
.c_cr17_b6 (c_cr17_b6),
.c_cr14_b6 (c_cr14_b6),
.reg_cr0c_qout (reg_cr0c_qout),
.reg_cr0d_qout (reg_cr0d_qout),
.reg_cr0e_qout (reg_cr0e_qout),
.reg_cr0f_qout (reg_cr0f_qout),
.reg_cr13_qout (reg_cr13_qout[7:0]),
.reg_sr3_qout (reg_sr3_qout),
.c_slc_op (c_slc_op[4:0]),
.ff_asic_out (ff_asic_out),
.enrd_font_addr (enrd_font_addr),
.enrd_tx_addr (enrd_tx_addr),
.enrd_gra_addr (enrd_gra_addr),
.crt_ff_write (crt_ff_write),
.font_addr (font_addr),
.fin_crt_addr (fin_crt_addr),
.cursorx (cursorx),
.sync_pre_vde (sync_pre_vde)
);
// Was att_test_blk
assign decode_c0todf = m_t_mem_data_in[7:5] == 3'b110;
assign int_x5 = cursorx & c_cursory;
assign blank = (m_t_mem_data_in[14:12] == 3'b000) &
(m_t_mem_data_in[10:8] == 3'b000);
assign under_line = (m_t_mem_data_in[14:12] == 3'b000) &
(m_t_mem_data_in[10:8] == 3'b001) &
c_uln_on;
assign reverse = (m_t_mem_data_in[14:12] == 3'b111) &
(m_t_mem_data_in[14:12] == 3'b000);
assign text_mode = ~g_gr06_b0;
assign graphic_mode = g_gr06_b0;
assign att_text_out = (text_mode) ? {decode_c0todf, reverse, under_line,
blank, int_x5} : m_t_mem_data_in[28:24];
sm_arb U_SM_ARB
(
.mem_clk (t_mem_clk),
.hreset_n (h_reset_n),
.crt_req (crt_req & mem_ready),
.cpu_rd_req (cpu_rd_req & mem_ready),
.cpu_wr_req (cpu_wr_req & mem_ready),
.a_empty (a_empty),
.b_empty (b_empty),
.a_full_done (a_full_done),
.b_full_done (b_full_done),
.sync_crt_line_end (sync_crt_line_end),
.crt_gnt (crt_gnt),
.cpu_wr_gnt (cpu_wr_gnt),
.cpu_rd_gnt (cpu_rd_gnt)
);
memif_reg_dec MREGDEC
(
.h_reset_n (h_reset_n),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_io_16 (h_io_16),
.h_io_addr (h_io_addr),
.h_io_dbus (h_io_dbus),
.h_hclk (t_mem_clk),
.color_mode (color_mode),
.c_crtc_index (c_crtc_index),
.c_ext_index (c_ext_index),
.g_gr05_b4 (g_gr05_b4),
.m_ready_n (m_ready_n),
.mem_mod_rd_en_hb (mem_mod_rd_en_hb),
.mem_mod_rd_en_lb (mem_mod_rd_en_lb),
.m_dec_sr00_sr06 (m_dec_sr00_sr06),
.m_dec_sr07 (m_dec_sr07),
.memif_index_qout (memif_index_qout),
.reg_sr0_qout (reg_sr0_qout),
.reg_sr1_qout (reg_sr1_qout),
.reg_sr2_qout (reg_sr2_qout),
.reg_sr3_qout (reg_sr3_qout),
.reg_sr4_qout (reg_sr4_qout),
.reg_cr0c_qout (reg_cr0c_qout), // screen start address high
.reg_cr0d_qout (reg_cr0d_qout),
.reg_cr0e_qout (reg_cr0e_qout),
.reg_cr0f_qout (reg_cr0f_qout),
.reg_cr13_qout (reg_cr13_qout),
.m_sr00_b0 (m_sr00_b0),
.m_sr01_b1 (m_sr01_b1),
.m_sr02_b (m_sr02_b),
.m_sr04_b3 (m_sr04_b3),
.m_chain4 (m_chain4),
.m_extend_mem (m_extend_mem),
.m_odd_even (m_odd_even),
.m_planar (m_planar),
.m_sr01_b4 (m_sr01_b4),
.m_sr01_b3 (m_sr01_b3),
.m_sr01_b2 (m_sr01_b2),
.m_sr01_b0 (m_sr01_b0),
.m_sr01_b5 (m_sr01_b5),
.m_soft_rst_n (m_soft_rst_n),
.m_sr04_b1 (m_sr04_b1)
);
endmodule
|
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
`define RAM_BLOCK cyclonev_ram_block
`define IBUF cyclonev_io_ibuf
`define OBUF cyclonev_io_obuf
`define CLKENA cyclonev_clkena
`endif
`ifdef arriav
`define LCELL arriav_lcell_comb
`define MAC arriav_mac
`define MLAB arriav_mlab_cell
`define RAM_BLOCK arriav_ram_block
`define IBUF arriav_io_ibuf
`define OBUF arriav_io_obuf
`define CLKENA arriav_clkena
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`define MAC cyclone10gx_mac
`define MLAB cyclone10gx_mlab_cell
`define RAM_BLOCK cyclone10gx_ram_block
`define IBUF cyclone10gx_io_ibuf
`define OBUF cyclone10gx_io_obuf
`define CLKENA cyclone10gx_clkena
`endif
module __MISTRAL_VCC(output Q);
MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module __MISTRAL_GND(output Q);
MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
endmodule
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter [31:0] LUT = 32'h0000_0000;
`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter [3:0] LUT = 4'h0;
`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
parameter _TECHMAP_CELLNAME_ = "";
// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
// which takes in a hexadecimal string that could be used to initialise RAM.
// In the vendor simulation models, this appears to work fine, but Quartus,
// either intentionally or not, forgets about this parameter and initialises the
// RAM to zero.
//
// Because of this, RAM initialisation is presently disabled, but the source
// used to generate mem_init0 is kept (commented out) in case this gets fixed
// or an undocumented way to get Quartus to initialise from mem_init0 is found.
`MLAB #(
.logical_ram_name(_TECHMAP_CELLNAME_),
.logical_ram_depth(32),
.logical_ram_width(1),
.mixed_port_feed_through_mode("Dont Care"),
.first_bit_number(0),
.first_address(0),
.last_address(31),
.address_width(5),
.data_width(1),
.byte_enable_mask_width(1),
.port_b_data_out_clock("NONE"),
// .mem_init0($sformatf("%08x", INIT))
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.ena0(A1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter _TECHMAP_CELLNAME_ = "";
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input CLK1, A1EN, B1EN;
output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware)
// but the Quartus primitive expects a normal write-enable, we add an inverter.
wire A1EN_N;
NOT wren_inv (.IN(A1EN), .OUT(A1EN_N));
`RAM_BLOCK #(
.operation_mode("dual_port"),
.logical_ram_name(_TECHMAP_CELLNAME_),
.port_a_address_width(CFG_ABITS),
.port_a_data_width(CFG_DBITS),
.port_a_logical_ram_depth(2**CFG_ABITS),
.port_a_logical_ram_width(CFG_DBITS),
.port_a_first_address(0),
.port_a_last_address(2**CFG_ABITS - 1),
.port_a_first_bit_number(0),
.port_b_address_width(CFG_ABITS),
.port_b_data_width(CFG_DBITS),
.port_b_logical_ram_depth(2**CFG_ABITS),
.port_b_logical_ram_width(CFG_DBITS),
.port_b_first_address(0),
.port_b_last_address(2**CFG_ABITS - 1),
.port_b_first_bit_number(0),
.port_b_address_clock("clock0"),
.port_b_read_enable_clock("clock0")
) ram_block (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portawe(A1EN_N),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.portbre(B1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(27),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(27),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(54),
.operation_mode("M27x27")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(18),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(18),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(36),
.operation_mode("M18x18_FULL")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(9),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(9),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(18),
.operation_mode("M9x9")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_IB(input PAD, output O);
`IBUF #(
.bus_hold("false"),
.differential_mode("false")
) _TECHMAP_REPLACE_ (
.i(PAD),
.o(O)
);
endmodule
module MISTRAL_OB(output PAD, input I, OE);
`OBUF #(
.bus_hold("false"),
.differential_mode("false")
) _TECHMAP_REPLACE_ (
.i(I),
.o(PAD),
.oe(OE)
);
endmodule
module MISTRAL_IO(output PAD, input I, OE, output O);
`IBUF #(
.bus_hold("false"),
.differential_mode("false")
) ibuf (
.i(PAD),
.o(O)
);
`OBUF #(
.bus_hold("false"),
.differential_mode("false")
) obuf (
.i(I),
.o(PAD),
.oe(OE)
);
endmodule
module MISTRAL_CLKBUF (input A, output Q);
`CLKENA #(
.clock_type("auto"),
.ena_register_mode("always enabled"),
.ena_register_power_up("high"),
.disable_mode("low"),
.test_syn("high")
) _TECHMAP_REPLACE_ (
.inclk(A),
.ena(1'b1),
.outclk(Q)
);
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 14
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 14;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 14;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 33333;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 200;
parameter gMEM_IF_TRCD_NS = 15.0;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 15.0;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
|
/* Memory mapped modules */
// Generate 25.00MHz
reg [1:0] clkdiv; // divider
always @(posedge sys_clk_in)
begin
case (clkdiv)
2'b11: clkdiv <= 2'b10;
2'b10: clkdiv <= 2'b00;
2'b00: clkdiv <= 2'b01;
2'b01: clkdiv <= 2'b11;
endcase
end
assign clk = clkdiv[1];
// Bi-directional SRAM data pins
wire [15:0] sram_in;
wire [15:0] sram_out;
wire data_we;
wire sram_vga_busy;
wire [2:0] rgb;
// AMBER: #ffff33
assign red=rgb[1]?4'he:4'b0;
assign green=rgb[0]?4'he:4'b0;
assign blue=rgb[2]?4'h3:4'b0;
SB_IO
#(
.PIN_TYPE(6'b 1010_01)
)
sram_data_pins [15:0]
(
.PACKAGE_PIN(DAT),
.OUTPUT_ENABLE(data_we_cpu),
.D_OUT_0(sram_out),
.D_IN_0(sram_in)
);
assign RAMCS_b = 1'b0;
assign RAMOE_b = !data_we;
assign RAMWE_b = (data_we);
assign RAMUB_b = 1'b0;
assign RAMLB_b = 1'b0;
wire [17:0] sram_adr_vga;
wire [17:0] sram_adr_cpu;
assign ADR = grant_vga?sram_adr_vga:grant_cpu?sram_adr_cpu:0;
wire data_we_cpu;
assign data_we = grant_vga?1:(!data_we_cpu);
wire data_rq_cpu;
wire data_rq_vga;
wire grant_cpu;
wire grant_vga;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(data_rq_cpu),
.req1(data_rq_vga),
.req2(0), .req3(0),
.gnt0(grant_cpu),
.gnt1(grant_vga),
.gnt2(gnt2_),
.gnt3(gnt3_));
wire vgaenable;
vga640x480ice vga1 (.clk(clk),
.clk25mhz(clk),
.rst(vgaenable),
.sram_adr_vga(sram_adr_vga),
.sram_in(sram_in),
.data_rq_vga(data_rq_vga),
.grant_vga(grant_vga),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb));
reg [9:0] reset_counter = 0;
reg hard_reset = 0;
always @(posedge clk) if (!hard_reset) begin
reset_counter <= reset_counter + 1;
if (reset_counter[9]) hard_reset <= 1;
end
assign rst = hard_reset;
wire [3:0] LED;
wire [3:0] LEDr;
outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(LED[0]), .rd(LEDr[0]));
outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(LED[1]), .rd(LEDr[1]));
outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(LED[2]), .rd(LEDr[2]));
outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(LED[3]), .rd(LEDr[3]));
ledwriter ledwr1 (.clk(clk),
.rst(rst),
.LED(LED),
.addr_b(ram_addr_in_b),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out));
wire [31:0] data_bus_in_uart;
wire data_bus_strobe_uart;
`ifdef ENABLE_UART
uartmm uart1(.clk(clk),
.rst(rst),
.TX(TX),
.RX(RX),
.data_b(data_bus_in_uart),
.addr_b(ram_addr_in_b),
.strobe_b(data_bus_strobe_uart),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out)
);
`else // !`ifdef ENABLE_UART
assign data_bus_strobe_uart = 0;
`endif // !`ifdef ENABLE_UART
|
// file: clk_wiz_v3_3.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0______206.578____237.727
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________25.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_3,clk_wiz_v3_3,{component_name=clk_wiz_v3_3,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk_wiz_v3_3
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (40.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (5.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (40.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
function int f_no_no ();
int st = 2; st++; return st;
endfunction
function int f_no_st ();
static int st = 2; st++; return st;
endfunction
function int f_no_au ();
automatic int st = 2; st++; return st;
endfunction
function static int f_st_no ();
int st = 2; st++; return st;
endfunction
function static int f_st_st ();
static int st = 2; st++; return st;
endfunction
function static int f_st_au ();
automatic int st = 2; st++; return st;
endfunction
function automatic int f_au_no ();
int st = 2; st++; return st;
endfunction
function automatic int f_au_st ();
static int st = 2; st++; return st;
endfunction
function automatic int f_au_au ();
automatic int st = 2; st++; return st;
endfunction
initial begin
if (f_no_no() != 3) $stop;
if (f_no_no() != 4) $stop;
if (f_no_st() != 3) $stop;
if (f_no_st() != 4) $stop;
if (f_no_au() != 3) $stop;
if (f_no_au() != 3) $stop;
//
if (f_st_no() != 3) $stop;
if (f_st_no() != 4) $stop;
if (f_st_st() != 3) $stop;
if (f_st_st() != 4) $stop;
if (f_st_au() != 3) $stop;
if (f_st_au() != 3) $stop;
//
if (f_au_no() != 3) $stop;
if (f_au_no() != 3) $stop;
if (f_au_st() != 3) $stop;
if (f_au_st() != 4) $stop;
if (f_au_au() != 3) $stop;
if (f_au_au() != 3) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_BLACKBOX_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Sine DDS look up table
*/
module sine_dds_lut #
(
parameter OUTPUT_WIDTH = 16,
parameter INPUT_WIDTH = OUTPUT_WIDTH+2
)
(
input wire clk,
input wire rst,
/*
* AXI stream phase input
*/
input wire [INPUT_WIDTH-1:0] input_phase_tdata,
input wire input_phase_tvalid,
output wire input_phase_tready,
/*
* AXI stream sample output
*/
output wire [OUTPUT_WIDTH-1:0] output_sample_i_tdata,
output wire [OUTPUT_WIDTH-1:0] output_sample_q_tdata,
output wire output_sample_tvalid,
input wire output_sample_tready
);
localparam W = (INPUT_WIDTH-2)/2;
reg [INPUT_WIDTH-1:0] phase_reg = 0;
integer i;
// coarse sine and cosine LUTs
reg [OUTPUT_WIDTH-1:0] coarse_c_lut[2**(W+1)-1:0];
reg [OUTPUT_WIDTH-1:0] coarse_s_lut[2**(W+1)-1:0];
initial begin
for (i = 0; i < 2**(W+1); i = i + 1) begin
coarse_c_lut[i] = $cos(2*3.1415926535*i/2**(W+2))*(2**(OUTPUT_WIDTH-1)-1);
coarse_s_lut[i] = $sin(2*3.1415926535*i/2**(W+2))*(2**(OUTPUT_WIDTH-1)-1);
end
end
// fine sine LUT
reg [(OUTPUT_WIDTH/2)-1:0] fine_s_lut[2**W-1:0];
initial begin
for (i = 0; i < 2**W; i = i + 1) begin
fine_s_lut[i] = $sin(2*3.1415926535*(i-2**(W-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1);
end
end
reg [OUTPUT_WIDTH-1:0] sample_i_reg = 0;
reg [OUTPUT_WIDTH-1:0] sample_q_reg = 0;
wire SIGN = phase_reg[INPUT_WIDTH-1];
wire SLOPE = phase_reg[INPUT_WIDTH-2];
wire [W:0] A = phase_reg[INPUT_WIDTH-2:W];
wire [W-1:0] B = phase_reg[W-1:0];
reg sign_reg_1 = 0;
reg sign_reg_2 = 0;
reg sign_reg_3 = 0;
reg sign_reg_4 = 0;
reg [OUTPUT_WIDTH-1:0] ccs_reg_1 = 0, ccs_reg_2 = 0, ccs_reg_3 = 0;
reg [OUTPUT_WIDTH-1:0] css_reg_1 = 0, css_reg_2 = 0, css_reg_3 = 0;
reg [(OUTPUT_WIDTH/2)-1:0] fss_reg_1 = 0, fss_reg_2 = 0;
reg [(OUTPUT_WIDTH*2)-1:0] cp_reg_1 = 0;
reg [(OUTPUT_WIDTH*2)-1:0] sp_reg_1 = 0;
reg [OUTPUT_WIDTH-1:0] cs_reg_1 = 0;
reg [OUTPUT_WIDTH-1:0] ss_reg_1 = 0;
assign input_phase_tready = output_sample_tready;
assign output_sample_i_tdata = sample_i_reg;
assign output_sample_q_tdata = sample_q_reg;
assign output_sample_tvalid = input_phase_tvalid;
always @(posedge clk) begin
if (rst) begin
phase_reg <= 0;
end else begin
if (input_phase_tready & input_phase_tvalid) begin
phase_reg <= input_phase_tdata;
end
end
if (input_phase_tready & input_phase_tvalid) begin
// pipeline sits primarily in DSP slice
// sin(A+B) = sin(A) + cos(A)*sin(B)
// cos(A+B) = cos(A) - sin(A)*sin(B)
// read samples
sign_reg_1 <= SIGN;
ccs_reg_1 <= coarse_c_lut[A];
css_reg_1 <= coarse_s_lut[A];
fss_reg_1 <= fine_s_lut[B];
// pipeline
sign_reg_2 <= sign_reg_1;
ccs_reg_2 <= ccs_reg_1;
css_reg_2 <= css_reg_1;
fss_reg_2 <= fss_reg_1;
// multiply
sign_reg_3 <= sign_reg_2;
ccs_reg_3 <= ccs_reg_2;
css_reg_3 <= css_reg_2;
cp_reg_1 <= $signed(css_reg_2) * $signed(fss_reg_2);
sp_reg_1 <= $signed(ccs_reg_2) * $signed(fss_reg_2);
// add
sign_reg_4 <= sign_reg_3;
cs_reg_1 <= ccs_reg_3 - (cp_reg_1 >> (OUTPUT_WIDTH-1));
ss_reg_1 <= css_reg_3 + (sp_reg_1 >> (OUTPUT_WIDTH-1));
// negate output samples
sample_i_reg <= sign_reg_4 ? -cs_reg_1 : cs_reg_1;
sample_q_reg <= sign_reg_4 ? -ss_reg_1 : ss_reg_1;
end
end
endmodule
|
//---------------------------------------------------------------------------------------
// uart transmit module
//
//---------------------------------------------------------------------------------------
module uart_tx
(
clock, reset,
ce_16, tx_data, new_tx_data,
ser_out, tx_busy
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
input clock; // global clock input
input reset; // global reset input
input ce_16; // baud rate multiplyed by 16 - generated by baud module
input [7:0] tx_data; // data byte to transmit
input new_tx_data; // asserted to indicate that there is a new data byte for transmission
output ser_out; // serial data output
output tx_busy; // signs that transmitter is busy
// internal wires
wire ce_1; // clock enable at bit rate
// internal registers
reg ser_out;
reg tx_busy;
reg [3:0] count16;
reg [3:0] bit_count;
reg [8:0] data_buf;
//---------------------------------------------------------------------------------------
// module implementation
// a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
always @ (posedge clock or posedge reset)
begin
if (reset)
count16 <= 4'b0;
else if (tx_busy & ce_16)
count16 <= count16 + 4'b1;
else if (~tx_busy)
count16 <= 4'b0;
end
// ce_1 pulse indicating output data bit should be updated
assign ce_1 = (count16 == 4'b1111) & ce_16;
// tx_busy flag
always @ (posedge clock or posedge reset)
begin
if (reset)
tx_busy <= 1'b0;
else if (~tx_busy & new_tx_data)
tx_busy <= 1'b1;
else if (tx_busy & (bit_count == 4'h9) & ce_1)
tx_busy <= 1'b0;
end
// output bit counter
always @ (posedge clock or posedge reset)
begin
if (reset)
bit_count <= 4'h0;
else if (tx_busy & ce_1)
bit_count <= bit_count + 4'h1;
else if (~tx_busy)
bit_count <= 4'h0;
end
// data shift register
always @ (posedge clock or posedge reset)
begin
if (reset)
data_buf <= 9'b0;
else if (~tx_busy)
data_buf <= {tx_data, 1'b0};
else if (tx_busy & ce_1)
data_buf <= {1'b1, data_buf[8:1]};
end
// output data bit
always @ (posedge clock or posedge reset)
begin
if (reset)
ser_out <= 1'b1;
else if (tx_busy)
ser_out <= data_buf[0];
else
ser_out <= 1'b1;
end
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_idelay8(
input [7:0] i,
output [7:0] o,
input clk,
input rst,
input ce,
input inc
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d0 (
.I(i[0]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[0])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d1 (
.I(i[1]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[1])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d2 (
.I(i[2]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[2])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d3 (
.I(i[3]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[3])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d4 (
.I(i[4]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[4])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d5 (
.I(i[5]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[5])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d6 (
.I(i[6]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[6])
);
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"),
.IOBDELAY_VALUE(0)
) d7 (
.I(i[7]),
.C(clk),
.INC(inc),
.CE(ce),
.RST(rst),
.O(o[7])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_SYMBOL_V
`define SKY130_FD_SC_MS__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern function int ext_f_i(int in);
extern task ext_t_np;
extern task ext_t_p();
extern task ext_t_i(int in);
endclass
function int Cls::ext_f_np;
return 1;
endfunction
function int Cls::ext_f_p();
return value;
endfunction
function int Cls::ext_f_i(int in);
return in+1;
endfunction
task Cls::ext_t_np();
$write("*-* All Finished *-*\n");
endtask
task Cls::ext_t_p();
$finish;
endtask
task Cls::ext_t_i(int in);
if (in != 2) $stop;
value = in;
endtask
module t (/*AUTOARG*/);
initial begin
Cls c = new;
c.ext_t_i(2);
c.ext_t_np();
c.ext_t_p();
if (c.ext_f_np() != 1) $stop;
if (c.ext_f_p() != 2) $stop;
if (c.ext_f_i(10) != 11) $stop;
end
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_5.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_5) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_5_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_5" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_5_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
// To match RTL : In RTL, write enable of the primitive is tied to all 1's and
// the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
// write operation depends on both enable and write enable. So, the below code
// which is actually doing the write operation only on enable ignoring the wea
// is removed to be in consistent with RTL.
// To Fix CR855535 (The fix to this CR is reverted to match RTL)
//assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt,
u.core.im08_a.imf.cnt, u.core.im09_a.imf.cnt, u.core.im10_a.imf.cnt, u.core.im11_a.imf.cnt,
u.core.im12_a.imf.cnt, u.core.im13_a.imf.cnt, u.core.im14_a.imf.cnt, u.core.im15_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt,
u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt,
u.core.im08_b.imf.cnt, u.core.im09_b.imf.cnt, u.core.im10_b.imf.cnt, u.core.im11_b.imf.cnt,
u.core.im12_b.imf.cnt, u.core.im13_b.imf.cnt, u.core.im14_b.imf.cnt, u.core.im15_b.imf.cnt);
if (u.core.im00_b.imf.cnt > 128) begin $write("\noverflow at im00_b"); $finish(); end
if (u.core.im01_b.imf.cnt > 128) begin $write("\noverflow at im01_b"); $finish(); end
if (u.core.im02_b.imf.cnt > 128) begin $write("\noverflow at im02_b"); $finish(); end
if (u.core.im03_b.imf.cnt > 128) begin $write("\noverflow at im03_b"); $finish(); end
if (u.core.im04_b.imf.cnt > 128) begin $write("\noverflow at im04_b"); $finish(); end
if (u.core.im05_b.imf.cnt > 128) begin $write("\noverflow at im05_b"); $finish(); end
if (u.core.im06_b.imf.cnt > 128) begin $write("\noverflow at im06_b"); $finish(); end
if (u.core.im07_b.imf.cnt > 128) begin $write("\noverflow at im07_b"); $finish(); end
if (u.core.im08_b.imf.cnt > 128) begin $write("\noverflow at im08_b"); $finish(); end
if (u.core.im09_b.imf.cnt > 128) begin $write("\noverflow at im09_b"); $finish(); end
if (u.core.im10_b.imf.cnt > 128) begin $write("\noverflow at im10_b"); $finish(); end
if (u.core.im11_b.imf.cnt > 128) begin $write("\noverflow at im11_b"); $finish(); end
if (u.core.im12_b.imf.cnt > 128) begin $write("\noverflow at im12_b"); $finish(); end
if (u.core.im13_b.imf.cnt > 128) begin $write("\noverflow at im13_b"); $finish(); end
if (u.core.im14_b.imf.cnt > 128) begin $write("\noverflow at im14_b"); $finish(); end
if (u.core.im15_b.imf.cnt > 128) begin $write("\noverflow at im15_b"); $finish(); end
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : ddr_phy_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_phy_top #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// This parameter must be set based on memory clock frequency
// It must be set to 4 for frequencies above 533 MHz?? (undecided)
// and set to 2 for 533 MHz and below
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter OUTPUT_DRV = "HIGH", // to calib_top
parameter REG_CTRL = "OFF", // to calib_top
parameter RTT_NOM = "60", // to calib_top
parameter RTT_WR = "120", // to calib_top
parameter tCK = 2500, // pS
parameter tRFC = 110000, // pS
parameter tREFI = 7800000, // pS
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter WRLVL = "OFF", // to calib_top
parameter DEBUG_PORT = "OFF", // to calib_top
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// Simulation /debug options
parameter SIM_BYPASS_INIT_CAL = "OFF",
// Parameter used to force skipping
// or abbreviation of initialization
// and calibration. Overrides
// SIM_INIT_OPTION, SIM_CAL_OPTION,
// and disables various other blocks
//parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps
//parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps
parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz)
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter RD_PATH_REG = 0, // optional registers in the read path
// to MC for timing improvement.
// =1 enabled, = 0 disabled
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter TAPSPERKCLK = 56,
parameter POC_USE_METASTABLE_SAMP = "FALSE"
)
(
input clk, // Fabric logic clock
// To MC, calib_top, hard PHY
input clk_ref, // Idelay_ctrl reference clock
// To hard PHY (external source)
input freq_refclk, // To hard PHY for Phasers
input mem_refclk, // Memory clock to hard PHY
input pll_lock, // System PLL lock signal
input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS
input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering
input poc_sample_pd, // Tell POC how to avoid metastability.
input error, // Support for TG error detect
output rst_tg_mc, // Support for TG error detect
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input rst,
input iddr_rst,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// From MC
input [nCK_PER_CLK-1:0] mc_ras_n,
input [nCK_PER_CLK-1:0] mc_cas_n,
input [nCK_PER_CLK-1:0] mc_we_n,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
input mc_reset_n,
input [1:0] mc_odt,
input [nCK_PER_CLK-1:0] mc_cke,
// AUX - For ODT and CKE assertion during reads and writes
input [3:0] mc_aux_out0,
input [3:0] mc_aux_out1,
input mc_cmd_wren,
input mc_ctl_wren,
input [2:0] mc_cmd,
input [1:0] mc_cas_slot,
input [5:0] mc_data_offset,
input [5:0] mc_data_offset_1,
input [5:0] mc_data_offset_2,
input [1:0] mc_rank_cnt,
// Write
input mc_wrdata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask,
input idle,
// DDR bus signals
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// Debug Port Outputs
output [255:0] dbg_calib_top,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output dbg_rddata_valid,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
// FIFO status flags
output phy_mc_ctl_full,
output phy_mc_cmd_full,
output phy_mc_data_full,
// Calibration status and resultant outputs
output init_calib_complete,
output init_wrcal_complete,
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps
);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Parameter used to force skipping or abbreviation of initialization
// and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
// disables various other blocks depending on the option selected
// This option should only be used during simulation. In the case of
// the "SKIP" option, the testbench used should also not be modeling
// propagation delays.
// Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
// "NONE" = options determined by the individual parameter settings
// "SIM_FULL" = skip power-up delay. FULL calibration performed without
// averaging algorithm turned ON during window detection.
// "SKIP" = skip power-up delay. Skip calibration not yet supported.
// "FAST" = skip power-up delay, and calibrate (read leveling, write
// leveling, and phase detector) only using one DQS group, and
// apply the results to all other DQS groups.
localparam SIM_INIT_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" :
((SIM_BYPASS_INIT_CAL == "FAST") ||
(SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" :
"NONE");
localparam SIM_CAL_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" :
(SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" :
((SIM_BYPASS_INIT_CAL == "SIM_FULL") ||
(SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" :
"NONE");
localparam WRLVL_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL;
localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 :
(BYTE_LANES_B2 != 0 ? 3 :
(BYTE_LANES_B1 != 0 ? 2 : 1))));
localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 :
BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 :
0;
localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 :
BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 :
0;
localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 :
BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 :
0;
localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 :
BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 :
0;
localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 :
BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 :
0;
localparam HIGHEST_LANE =
(HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) :
((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) :
((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) :
((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) :
HIGHEST_LANE_B0)));
localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) +
(0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) +
(0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) +
(0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) +
((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) +
(0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) +
(0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) +
(0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) +
((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) +
(0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) +
(0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) +
(0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) +
((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) +
(0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) +
(0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) +
(0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) +
((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) +
(0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) +
(0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) +
(0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]));
// Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
// This should be the case since the PLL should be placed adjacent
// to the same IO Bank as Ck/Addr/Cmd and Control
localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) |
((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ?
3'b000 :
(((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ?
3'b001 :
(((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ?
3'b010 :
(((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ?
3'b011 :
(((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) |
((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ?
3'b100 : 3'b000;
localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ?
8'b00_00_01_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_10 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_00 : 8'b11_10_01_00;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data;
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out;
wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk;
wire phy_mc_go;
wire phy_ctl_full;
wire phy_cmd_full;
wire phy_data_full;
wire phy_pre_data_a_full;
wire if_empty /* synthesis syn_maxfan = 3 */;
wire phy_write_calib;
wire phy_read_calib;
wire [HIGHEST_BANK-1:0] rst_stg1_cal;
wire [5:0] calib_sel;
wire calib_in_common /* synthesis syn_maxfan = 10 */;
wire [HIGHEST_BANK-1:0] calib_zero_inputs;
wire [HIGHEST_BANK-1:0] calib_zero_ctrl;
wire pi_phase_locked;
wire pi_phase_locked_all;
wire pi_found_dqs;
wire pi_dqs_found_all;
wire pi_dqs_out_of_range;
wire pi_enstg2_f;
wire pi_stg2_fincdec;
wire pi_stg2_load;
wire [5:0] pi_stg2_reg_l;
wire idelay_ce;
wire idelay_inc;
wire idelay_ld;
wire [2:0] po_sel_stg2stg3;
wire [2:0] po_stg2_cincdec;
wire [2:0] po_enstg2_c;
wire [2:0] po_stg2_fincdec;
wire [2:0] po_enstg2_f;
wire [8:0] po_counter_read_val;
wire [5:0] pi_counter_read_val;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata;
reg [nCK_PER_CLK-1:0] parity;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n;
wire [nCK_PER_CLK-1:0] phy_ras_n;
wire [nCK_PER_CLK-1:0] phy_cas_n;
wire [nCK_PER_CLK-1:0] phy_we_n;
wire phy_reset_n;
wire [3:0] calib_aux_out;
wire [nCK_PER_CLK-1:0] calib_cke;
wire [1:0] calib_odt;
wire calib_ctl_wren;
wire calib_cmd_wren;
wire calib_wrdata_en;
wire [2:0] calib_cmd;
wire [1:0] calib_seq;
wire [5:0] calib_data_offset_0;
wire [5:0] calib_data_offset_1;
wire [5:0] calib_data_offset_2;
wire [1:0] calib_rank_cnt;
wire [1:0] calib_cas_slot;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address;
wire [3:0] mux_aux_out;
wire [3:0] aux_out_map;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank;
wire [2:0] mux_cmd;
wire mux_cmd_wren;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n;
wire mux_ctl_wren;
wire [1:0] mux_cas_slot;
wire [5:0] mux_data_offset;
wire [5:0] mux_data_offset_1;
wire [5:0] mux_data_offset_2;
wire [nCK_PER_CLK-1:0] mux_ras_n;
wire [nCK_PER_CLK-1:0] mux_cas_n;
wire [1:0] mux_rank_cnt;
wire mux_reset_n;
wire [nCK_PER_CLK-1:0] mux_we_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata;
wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask;
wire mux_wrdata_en;
wire [nCK_PER_CLK-1:0] mux_cke ;
wire [1:0] mux_odt ;
wire phy_if_empty_def;
wire phy_if_reset;
wire phy_init_data_sel;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map;
wire phy_rddata_valid_w;
reg rddata_valid_reg;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg;
wire [4:0] idelaye2_init_val;
wire [5:0] oclkdelay_init_val;
wire po_counter_load_en;
wire [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb;
wire fine_delay_sel;
wire pd_out;
//***************************************************************************
assign dbg_rddata_valid = rddata_valid_reg;
assign dbg_rddata = rd_data_reg;
assign dbg_rd_data_offset = calib_rd_data_offset_0;
assign dbg_pi_phaselocked_done = pi_phase_locked_all;
assign dbg_po_counter_read_val = po_counter_read_val;
assign dbg_pi_counter_read_val = pi_counter_read_val;
//***************************************************************************
genvar i;
generate
for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen
assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i];
assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1];
end
endgenerate
//***************************************************************************
// During memory initialization and calibration the calibration logic drives
// the memory signals. After calibration is complete the memory controller
// drives the memory signals.
// Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
//***************************************************************************
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ;
genvar v ;
generate
if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm
for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin
if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin
assign mc_cs_n_temp[v] = mc_cs_n[v] ;
end else begin
assign mc_cs_n_temp[v] = 'b1 ;
end
end
end else begin
assign mc_cs_n_temp = mc_cs_n ;
end
endgenerate
assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata;
assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0;
assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address;
assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank;
assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n;
assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n;
assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n;
assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n;
assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n;
assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out;
assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ;
assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ;
assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren :
calib_cmd_wren;
assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren :
calib_ctl_wren;
assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en :
calib_wrdata_en;
assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd;
assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot;
assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset :
calib_data_offset_0;
assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 :
calib_data_offset_1;
assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 :
calib_data_offset_2;
// Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
assign mux_rank_cnt = 2'b00;
// Assigning cke & odt for DDR2 & DDR3
// No changes for DDR3 & DDR2 dual rank
// DDR2 single rank systems might potentially need 3 odt signals.
// Aux_out[2] will have the odt toggled by phy and controller
// wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
// all of the three odt bits or some of them might be used.
// mapping done in mc_phy_wrapper module
generate
if(CKE_ODT_AUX == "TRUE") begin
assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ?
{mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} :
mux_aux_out;
end else begin
assign aux_out_map = 4'b0000 ;
end
endgenerate
assign init_calib_complete = phy_init_data_sel;
assign phy_mc_ctl_full = phy_ctl_full;
assign phy_mc_cmd_full = phy_cmd_full;
assign phy_mc_data_full = phy_pre_data_a_full;
//***************************************************************************
// Generate parity for DDR3 RDIMM.
//***************************************************************************
generate
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3],
mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3],
mux_cas_n[3], mux_ras_n[3], mux_we_n[3]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0],mux_ras_n[0], mux_we_n[0]});
parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2],
mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2],
mux_cas_n[2],mux_ras_n[2], mux_we_n[2]});
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0],
mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0], mux_ras_n[0], mux_we_n[0]});
end
end
end else begin: gen_ddr3_noparity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
parity[2] <= #TCQ 1'b0;
parity[3] <= #TCQ 1'b0;
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
end
end
end
endgenerate
//***************************************************************************
// Code for optional register stage in read path to MC for timing
//***************************************************************************
generate
if(RD_PATH_REG == 1)begin:RD_REG_TIMING
always @(posedge clk)begin
rddata_valid_reg <= #TCQ phy_rddata_valid_w;
rd_data_reg <= #TCQ rd_data_map;
end // always @ (posedge clk)
end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING
always @(phy_rddata_valid_w or rd_data_map)begin
rddata_valid_reg = phy_rddata_valid_w;
rd_data_reg = rd_data_map;
end
end
endgenerate
assign phy_rddata_valid = rddata_valid_reg;
assign phy_rd_data = rd_data_reg;
//***************************************************************************
// Hard PHY and accompanying bit mapping logic
//***************************************************************************
mig_7series_v2_3_ddr_mc_phy_wrapper #
(
.TCQ (TCQ),
.tCK (tCK),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CK_WIDTH (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.CWL (CWL),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.HIGHEST_BANK (HIGHEST_BANK),
.HIGHEST_LANE (HIGHEST_LANE),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DRAM_WIDTH (DRAM_WIDTH),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_ddr_mc_phy_wrapper
(
.rst (rst),
.iddr_rst (iddr_rst),
.clk (clk),
// For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
// For memory frequencies below 400 MHz mem_refclk = mem_refclk and
// freq_refclk = 2x or 4x mem_refclk such that it remains in the
// 400~1066 MHz range
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.mmcm_ps_clk (mmcm_ps_clk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.idelayctrl_refclk (clk_ref),
.phy_cmd_wr_en (mux_cmd_wren),
.phy_data_wr_en (mux_wrdata_en),
// phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
// DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
// AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
// The fields ACTPRE, and BankCount are only used
// when the hard PHY counters are used by the MC.
.phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset,
mux_rank_cnt, 3'd0, aux_out_map,
5'd0, mux_cmd}),
.phy_ctl_wr (mux_ctl_wren),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
.data_offset_1 (mux_data_offset_1),
.data_offset_2 (mux_data_offset_2),
.aux_in_1 (aux_out_map),
.aux_in_2 (aux_out_map),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
.if_empty (if_empty),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.phy_pre_data_a_full (phy_pre_data_a_full),
.ddr_clk (ddr_clk),
.phy_mc_go (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.po_fine_enable (po_enstg2_f),
.po_coarse_enable (po_enstg2_c),
.po_fine_inc (po_stg2_fincdec),
.po_coarse_inc (po_stg2_cincdec),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_en (1'b1),
.po_sel_fine_oclk_delay (po_sel_stg2stg3),
.po_counter_load_val (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (rst_stg1_cal),
.pi_fine_enable (pi_enstg2_f),
.pi_fine_inc (pi_stg2_fincdec),
.pi_counter_load_en (pi_stg2_load),
.pi_counter_load_val (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
// Currently not being used. May be used in future if periodic reads
// become a requirement. This output could also be used to signal a
// catastrophic failure in read capture and the need for re-cal
.pi_dqs_out_of_range (pi_dqs_out_of_range),
.phy_init_data_sel (phy_init_data_sel),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.mux_address (mux_address),
.mux_bank (mux_bank),
.mux_cs_n (mux_cs_n),
.mux_ras_n (mux_ras_n),
.mux_cas_n (mux_cas_n),
.mux_we_n (mux_we_n),
.mux_reset_n (mux_reset_n),
.parity_in (parity),
.mux_wrdata (mux_wrdata),
.mux_wrdata_mask (mux_wrdata_mask),
.mux_odt (mux_odt),
.mux_cke (mux_cke),
.idle (idle),
.rd_data (rd_data_map),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_parity (ddr_parity),
.ddr_ras_n (ddr_ras_n),
.ddr_we_n (ddr_we_n),
.ddr_dq (ddr_dq),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_reset_n (ddr_reset_n),
.dbg_pi_counter_read_en (1'b1),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.byte_sel_cnt (byte_sel_cnt),
.pd_out (pd_out),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
//***************************************************************************
// Soft memory initialization and calibration logic
//***************************************************************************
mig_7series_v2_3_ddr_calib_top #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.nCK_PER_CLK (nCK_PER_CLK),
.PRE_REV3ES (PRE_REV3ES),
.tCK (tCK),
.CLK_PERIOD (CLK_PERIOD),
.N_CTL_LANES (N_CTL_LANES),
.CTL_BYTE_LANE (CTL_BYTE_LANE),
.CTL_BANK (CTL_BANK),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (8),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.HIGHEST_BANK (HIGHEST_BANK),
.BANK_TYPE (BANK_TYPE),
.HIGHEST_LANE (HIGHEST_LANE),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.CS_WIDTH (CS_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.PER_BIT_DESKEW ("OFF"),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (CL),
.nCWL (CWL),
.tRFC (tRFC),
.tREFI (tREFI),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL_W),
.USE_ODT_PORT (USE_ODT_PORT),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_ddr_calib_top
(
.clk (clk),
.rst (rst),
.tg_err (error),
.rst_tg_mc (rst_tg_mc),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
// PHY Control Block and IN_FIFO status
.phy_ctl_ready (phy_mc_go),
.phy_ctl_full (1'b0),
.phy_cmd_full (1'b0),
.phy_data_full (1'b0),
.phy_if_empty (if_empty),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
// From calib logic To data IN_FIFO
// DQ IDELAY tap value from Calib logic
// port to be added to mc_phy by Gary
.dlyval_dq (),
// hard PHY calibration modes
.write_calib (phy_write_calib),
.read_calib (phy_read_calib),
// DQS count and ck/addr/cmd to be mapped to calib_sel
// based on parameter that defines placement of ctl lanes
// and DQS byte groups in each bank. When phy_write_calib
// is de-asserted calib_sel should select CK/addr/cmd/ctl.
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
// Signals from calib logic to be MUXED with MC
// signals before sending to hard PHY
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_odt (calib_odt),
.calib_cke (calib_cke),
.calib_cmd (calib_cmd),
.calib_wrdata_en (calib_wrdata_en),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.phy_reset_n (phy_reset_n),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_cas_n (phy_cas_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
// DQS Phaser_IN calibration/status signals
.pi_phaselocked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_found_dqs (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.pi_rst_stg1_cal (rst_stg1_cal),
.pi_en_stg2_f (pi_enstg2_f),
.pi_stg2_f_incdec (pi_stg2_fincdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en),
// IDELAY tap enable and inc signals
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
// DQS Phaser_OUT calibration/status signals
.po_sel_stg2stg3 (po_sel_stg2stg3),
.po_stg2_c_incdec (po_stg2_cincdec),
.po_en_stg2_c (po_enstg2_c),
.po_stg2_f_incdec (po_stg2_fincdec),
.po_en_stg2_f (po_enstg2_f),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_val (po_counter_read_val),
// From data IN_FIFO To Calib logic and MC/UI
.phy_rddata (rd_data_map),
// From calib logic To MC
.phy_rddata_valid (phy_rddata_valid_w),
.calib_rd_data_offset_0 (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.calib_writes (),
// Mem Init and Calibration status To MC
.init_calib_complete (phy_init_data_sel),
.init_wrcal_complete (init_wrcal_complete),
// Debug Error signals
.pi_phase_locked_err (dbg_pi_phaselock_err),
.pi_dqsfound_err (dbg_pi_dqsfound_err),
.wrcal_err (dbg_wrcal_err),
//used for oclk stg3 centering
.pd_out (pd_out),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.poc_sample_pd (poc_sample_pd),
// Debug Signals
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_calib_top (dbg_calib_top),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.byte_sel_cnt (byte_sel_cnt),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 24925 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8192,
w8191,
w128,
w8319,
w32,
w8287,
w16638,
w24925;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w16638 = w8319 << 1;
assign w24925 = w8287 + w16638;
assign w32 = w1 << 5;
assign w8191 = w8192 - w1;
assign w8192 = w1 << 13;
assign w8287 = w8319 - w32;
assign w8319 = w8191 + w128;
assign o_data0 = w24925;
//multiplier_block area estimate = 7271.51040645588;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
`timescale 1ps / 1ps
module AXI_SPI_ROM_test(
);
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
localparam tries = 4;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;
// Autogen localparams
reg CLK = 1'b0;
reg RST;
// AXI4-lite master memory interfaces
reg axi_awvalid;
wire axi_awready;
reg [sword-1:0] axi_awaddr;
reg [3-1:0] axi_awprot;
reg axi_wvalid;
wire axi_wready;
reg [sword-1:0] axi_wdata;
reg [4-1:0] axi_wstrb;
wire axi_bvalid;
reg axi_bready;
reg axi_arvalid;
wire axi_arready;
reg [sword-1:0] axi_araddr;
reg [3-1:0] axi_arprot;
wire axi_rvalid;
reg axi_rready;
wire [sword-1:0] axi_rdata;
// DDR2 interface
wire ROM_CS;
wire ROM_SDI;
wire ROM_SDO;
wire ROM_WP;
wire ROM_HLD;
wire ROM_SCK;
//integer fd1, tmp1, ifstop;
integer PERIOD = 5000 ;
integer i, error;
AXI_SPI_ROM # (
.numbit_divisor(4))
inst_AXI_SPI_ROM (
.CLK(CLK),
.RST(RST),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_awaddr(axi_awaddr),
.axi_awprot(axi_awprot),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_araddr(axi_araddr),
.axi_arprot(axi_arprot),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.axi_rdata(axi_rdata),
.ROM_CS(ROM_CS),
.ROM_SDI(ROM_SDI),
.ROM_SDO(ROM_SDO),
.ROM_WP(ROM_WP),
.ROM_HLD(ROM_HLD),
.ROM_SCK(ROM_SCK)
);
s25fl128s inst_s25fl128s
(
.CSNeg(ROM_CS),
.SI(ROM_SDO),
.SO(ROM_SDI),
.RSTNeg(RST),
.WPNeg(ROM_WP),
.HOLDNeg(ROM_HLD),
.SCK(ROM_SCK)
);
always
begin #(PERIOD/2) CLK = ~CLK; end
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else
begin
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
initial begin
//$sdf_annotate("AXI_SRAM.sdf",AXI_SRAM);
CLK = 1'b0;
RST = 1'b0;
error = 0;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b1;
axi_arvalid = 1'b0;
axi_rready = 1'b1;
axi_awaddr = {sword{1'b0}};
axi_awprot = {3{1'b0}};
axi_wdata = {sword{1'b0}};
axi_wstrb = 4'b1111;
axi_araddr = {sword{1'b0}};
axi_arprot = {3{1'b0}};
#101000;
RST = 1'b1;
#38850000;
// WRITTING AND READING TEST
// BASICALLY, WHAT I READ, IS WHAT I WRITE
for(i = 0; i < tries; i = i+1) begin
#(PERIOD*8);
// WRITTING TEST
axi_awvalid = 1'b1;
axi_awaddr = i<<2;//xorshift64_state[sword*2-1:sword];
#PERIOD;
while(!axi_awready) begin
#PERIOD;
end
axi_awvalid = 1'b0;
axi_wvalid = 1'b1;
axi_wdata = xorshift64_state[sword-1:0];
#PERIOD;
while(!axi_wready) begin
#PERIOD;
end
axi_wvalid = 1'b0;
while(!axi_bvalid) begin
#PERIOD;
end
//axi_bready = 1'b1;
#PERIOD;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
//axi_bready = 1'b0;
// WRITTING TEST
axi_arvalid = 1'b1;
axi_araddr = i<<2;//xorshift64_state[sword*2-1:sword];
#PERIOD;
while(!axi_arready) begin
#PERIOD;
end
axi_arvalid = 1'b0;
while(!axi_rvalid) begin
#PERIOD;
end
//axi_rready = 1'b1;
#PERIOD;
axi_arvalid = 1'b0;
//axi_rready = 1'b0;
aexpect(axi_rdata, xorshift64_state[sword-1:0]);
xorshift64_next;
end
$timeformat(-9,0,"ns",7);
#(PERIOD*8) if (error == 0)
$display("All match");
else
$display("Mismatches = %d", error);
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.91
// \ \ Application: MIG
// / / Filename: phy_rdctrl_sync.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Synchronization of read control signal from MC/PHY rdlvl logic (clk) to
// read capture logic (clk_rsync) clock domain. Also adds additional delay
// to account for read latency
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_rdctrl_sync.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_rdctrl_sync.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_rdctrl_sync #
(
parameter TCQ = 100
)
(
input clk,
input rst_rsync, // Use only CLK_RSYNC[0] reset
// Control for control sync logic
input mc_data_sel,
input [4:0] rd_active_dly,
// DFI signals from MC/PHY rdlvl logic
input dfi_rddata_en,
input phy_rddata_en,
// Control for read logic, initialization logic
output reg dfi_rddata_valid,
output reg dfi_rddata_valid_phy,
output reg rdpath_rdy // asserted when read path
// ready for use
);
// # of clock cycles after RST_RSYNC has deasserted before init/cal logic
// is taken out of reset. This is only needed for simulation when the "no
// init/no cal" option is selected. In this case, PHY_INIT will assert
// DFI_INIT_COMPLETE signal almost instantaneously once it is taken out
// of reset - however, there are certain pipe stages that must "flush
// out" (related to circular buffer synchronization) for a few cycles after
// RST_RSYNC is deasserted - in particular, the one related to generating
// DFI_RDDATA_VALID must not drive an unknown value on the bus after
// DFI_INIT_COMPLETE is asserted.
// NOTE: # of cycles of delay required depends on the circular buffer
// depth for RD_ACTIVE - it should >= (0.5*depth + 1)
localparam RDPATH_RDY_DLY = 10;
wire rddata_en;
wire rddata_en_rsync;
wire rddata_en_srl_out;
reg [RDPATH_RDY_DLY-1:0] rdpath_rdy_dly_r;
//***************************************************************************
// Delay RDDATA_EN by an amount determined during read-leveling
// calibration to reflect the round trip delay from command issuance until
// when read data is returned
//***************************************************************************
assign rddata_en = (mc_data_sel) ? dfi_rddata_en : phy_rddata_en;
// May need to flop output of SRL for better timing
SRLC32E u_rddata_en_srl
(
.Q (rddata_en_srl_out),
.Q31 (),
.A (rd_active_dly),
.CE (1'b1),
.CLK (clk),
.D (rddata_en)
);
// Flop once more for better timing
always @(posedge clk) begin
// Only assert valid on DFI bus after initialization complete
dfi_rddata_valid <= #TCQ rddata_en_srl_out & mc_data_sel;
// Assert valid for PHY during initialization
dfi_rddata_valid_phy <= #TCQ rddata_en_srl_out;
end
//***************************************************************************
// Generate a signal that tells initialization logic that read path is
// ready for use (i.e. for read leveling). Use RST_RSYNC, and delay it by
// RDPATH_RDY_DLY clock cycles, then synchronize to CLK domain.
// NOTE: This logic only required for simulation; for final h/w, there will
// always be a long delay between RST_RSYNC deassertion and
// DFI_INIT_COMPLETE assertion (for DRAM init, and leveling)
//***************************************************************************
// First delay by X number of clock cycles to guarantee that RDPATH_RDY
// isn't asserted too soon after RST_RSYNC is deasserted (to allow various
// synchronization pipe stages to "flush"). NOTE: Only RST_RSYNC[0] (or
// any of the up to 4 RST_RSYNC's) is used - any of them is sufficient
// close enough in timing to use
always @(posedge clk or posedge rst_rsync) begin
if (rst_rsync)
rdpath_rdy_dly_r <= #TCQ {{RDPATH_RDY_DLY}{1'b0}};
else
rdpath_rdy_dly_r[RDPATH_RDY_DLY-1:1]
<= #TCQ {rdpath_rdy_dly_r[RDPATH_RDY_DLY-2:0], 1'b1};
end
// Flop once more to prevent ISE tools from analyzing asynchronous path
// through this flop to receiving logic
always @(posedge clk)
rdpath_rdy <= rdpath_rdy_dly_r[RDPATH_RDY_DLY-1];
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_FUNCTIONAL_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module nfa_accept_sample_multi (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address,
nfa_initials_buckets_datain,
nfa_initials_buckets_dataout,
nfa_initials_buckets_size,
nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address,
nfa_finals_buckets_datain,
nfa_finals_buckets_dataout,
nfa_finals_buckets_size,
nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address,
nfa_forward_buckets_datain,
nfa_forward_buckets_dataout,
nfa_forward_buckets_size,
nfa_symbols,
sample_req_din,
sample_req_full_n,
sample_req_write,
sample_rsp_empty_n,
sample_rsp_read,
sample_address,
sample_datain,
sample_dataout,
sample_size,
length_r,
start_indices_address0,
start_indices_ce0,
start_indices_q0,
stop_on_first,
accept,
units,
result_address0,
result_ce0,
result_we0,
result_d0,
result_q0,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 6'b000000;
parameter ap_ST_st2_fsm_1 = 6'b1;
parameter ap_ST_st3_fsm_2 = 6'b10;
parameter ap_ST_st4_fsm_3 = 6'b11;
parameter ap_ST_st5_fsm_4 = 6'b100;
parameter ap_ST_st6_fsm_5 = 6'b101;
parameter ap_ST_st7_fsm_6 = 6'b110;
parameter ap_ST_st8_fsm_7 = 6'b111;
parameter ap_ST_st9_fsm_8 = 6'b1000;
parameter ap_ST_st10_fsm_9 = 6'b1001;
parameter ap_ST_st11_fsm_10 = 6'b1010;
parameter ap_ST_st12_fsm_11 = 6'b1011;
parameter ap_ST_st13_fsm_12 = 6'b1100;
parameter ap_ST_st14_fsm_13 = 6'b1101;
parameter ap_ST_st15_fsm_14 = 6'b1110;
parameter ap_ST_st16_fsm_15 = 6'b1111;
parameter ap_ST_st17_fsm_16 = 6'b10000;
parameter ap_ST_st18_fsm_17 = 6'b10001;
parameter ap_ST_st19_fsm_18 = 6'b10010;
parameter ap_ST_st20_fsm_19 = 6'b10011;
parameter ap_ST_st21_fsm_20 = 6'b10100;
parameter ap_ST_st22_fsm_21 = 6'b10101;
parameter ap_ST_st23_fsm_22 = 6'b10110;
parameter ap_ST_st24_fsm_23 = 6'b10111;
parameter ap_ST_st25_fsm_24 = 6'b11000;
parameter ap_ST_st26_fsm_25 = 6'b11001;
parameter ap_ST_st27_fsm_26 = 6'b11010;
parameter ap_ST_st28_fsm_27 = 6'b11011;
parameter ap_ST_st29_fsm_28 = 6'b11100;
parameter ap_ST_st30_fsm_29 = 6'b11101;
parameter ap_ST_st31_fsm_30 = 6'b11110;
parameter ap_ST_st32_fsm_31 = 6'b11111;
parameter ap_ST_st33_fsm_32 = 6'b100000;
parameter ap_ST_st34_fsm_33 = 6'b100001;
parameter ap_ST_st35_fsm_34 = 6'b100010;
parameter ap_ST_st36_fsm_35 = 6'b100011;
parameter ap_ST_st37_fsm_36 = 6'b100100;
parameter ap_ST_st38_fsm_37 = 6'b100101;
parameter ap_ST_st39_fsm_38 = 6'b100110;
parameter ap_ST_st40_fsm_39 = 6'b100111;
parameter ap_ST_st41_fsm_40 = 6'b101000;
parameter ap_ST_st42_fsm_41 = 6'b101001;
parameter ap_ST_st43_fsm_42 = 6'b101010;
parameter ap_ST_st44_fsm_43 = 6'b101011;
parameter ap_ST_st45_fsm_44 = 6'b101100;
parameter ap_ST_st46_fsm_45 = 6'b101101;
parameter ap_ST_st47_fsm_46 = 6'b101110;
parameter ap_ST_st48_fsm_47 = 6'b101111;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv4_E = 4'b1110;
parameter ap_const_lv4_D = 4'b1101;
parameter ap_const_lv4_C = 4'b1100;
parameter ap_const_lv4_B = 4'b1011;
parameter ap_const_lv4_A = 4'b1010;
parameter ap_const_lv4_9 = 4'b1001;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_7 = 4'b111;
parameter ap_const_lv4_6 = 4'b110;
parameter ap_const_lv4_5 = 4'b101;
parameter ap_const_lv4_4 = 4'b100;
parameter ap_const_lv4_3 = 4'b11;
parameter ap_const_lv4_2 = 4'b10;
parameter ap_const_lv4_1 = 4'b1;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_20 = 32'b100000;
parameter ap_const_lv32_3F = 32'b111111;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv16_FFFF = 16'b1111111111111111;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv8_5 = 8'b101;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output nfa_initials_buckets_req_din;
input nfa_initials_buckets_req_full_n;
output nfa_initials_buckets_req_write;
input nfa_initials_buckets_rsp_empty_n;
output nfa_initials_buckets_rsp_read;
output [31:0] nfa_initials_buckets_address;
input [63:0] nfa_initials_buckets_datain;
output [63:0] nfa_initials_buckets_dataout;
output [31:0] nfa_initials_buckets_size;
output nfa_finals_buckets_req_din;
input nfa_finals_buckets_req_full_n;
output nfa_finals_buckets_req_write;
input nfa_finals_buckets_rsp_empty_n;
output nfa_finals_buckets_rsp_read;
output [31:0] nfa_finals_buckets_address;
input [63:0] nfa_finals_buckets_datain;
output [63:0] nfa_finals_buckets_dataout;
output [31:0] nfa_finals_buckets_size;
output nfa_forward_buckets_req_din;
input nfa_forward_buckets_req_full_n;
output nfa_forward_buckets_req_write;
input nfa_forward_buckets_rsp_empty_n;
output nfa_forward_buckets_rsp_read;
output [31:0] nfa_forward_buckets_address;
input [31:0] nfa_forward_buckets_datain;
output [31:0] nfa_forward_buckets_dataout;
output [31:0] nfa_forward_buckets_size;
input [7:0] nfa_symbols;
output sample_req_din;
input sample_req_full_n;
output sample_req_write;
input sample_rsp_empty_n;
output sample_rsp_read;
output [31:0] sample_address;
input [7:0] sample_datain;
output [7:0] sample_dataout;
output [31:0] sample_size;
input [15:0] length_r;
output [3:0] start_indices_address0;
output start_indices_ce0;
input [31:0] start_indices_q0;
input [0:0] stop_on_first;
input [0:0] accept;
input [4:0] units;
output [3:0] result_address0;
output result_ce0;
output result_we0;
output [0:0] result_d0;
input [0:0] result_q0;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg nfa_forward_buckets_req_write;
reg nfa_forward_buckets_rsp_read;
reg[31:0] nfa_forward_buckets_address;
reg sample_req_write;
reg sample_rsp_read;
reg start_indices_ce0;
reg[3:0] result_address0;
reg result_ce0;
reg result_we0;
reg[0:0] result_d0;
reg[0:0] ap_return;
reg [5:0] ap_CS_fsm = 6'b000000;
wire [4:0] k_4_fu_12996_p2;
reg [4:0] k_4_reg_13968;
wire [15:0] i_1_fu_13091_p2;
reg [15:0] i_1_reg_14270;
reg [7:0] j_15_bit_load_reg_14279;
reg [7:0] j_15_bit_1_load_reg_14284;
reg [7:0] j_15_bit_2_load_reg_14289;
reg [7:0] j_15_bit_3_load_reg_14294;
reg [7:0] j_15_bit_4_load_reg_14299;
reg [7:0] j_15_bit_5_load_reg_14304;
reg [7:0] j_15_bit_6_load_reg_14309;
reg [7:0] j_15_bit_7_load_reg_14314;
reg [7:0] j_15_bit_8_load_reg_14319;
reg [7:0] j_15_bit_9_load_reg_14324;
reg [7:0] j_15_bit_10_load_reg_14329;
reg [7:0] j_15_bit_11_load_reg_14334;
reg [7:0] j_15_bit_12_load_reg_14339;
reg [7:0] j_15_bit_13_load_reg_14344;
reg [7:0] j_15_bit_14_load_reg_14349;
reg [7:0] j_15_bit_15_load_reg_14354;
reg [7:0] j_bucket_index_0_load_reg_14359;
reg [7:0] j_bucket_index_1_load_reg_14364;
reg [7:0] j_bucket_index_2_load_reg_14369;
reg [7:0] j_bucket_index_3_load_reg_14374;
reg [7:0] j_bucket_index_4_load_reg_14379;
reg [7:0] j_bucket_index_5_load_reg_14384;
reg [7:0] j_bucket_index_6_load_reg_14389;
reg [7:0] j_bucket_index_7_load_reg_14394;
reg [7:0] j_bucket_index_8_load_reg_14399;
reg [7:0] j_bucket_index_9_load_reg_14404;
reg [7:0] j_bucket_index_10_load_reg_14409;
reg [7:0] j_bucket_index_11_load_reg_14414;
reg [7:0] j_bucket_index_12_load_reg_14419;
reg [7:0] j_bucket_index_13_load_reg_14424;
reg [7:0] j_bucket_index_14_load_reg_14429;
reg [7:0] j_bucket_index_15_load_reg_14434;
reg [0:0] j_15_end_load_reg_14439;
reg [0:0] j_15_end_1_load_reg_14444;
reg [0:0] j_15_end_2_load_reg_14449;
reg [0:0] j_15_end_3_load_reg_14454;
reg [0:0] j_15_end_4_load_reg_14459;
reg [0:0] j_15_end_5_load_reg_14464;
reg [0:0] j_15_end_6_load_reg_14469;
reg [0:0] j_15_end_7_load_reg_14474;
reg [0:0] j_15_end_8_load_reg_14479;
reg [0:0] j_15_end_9_load_reg_14484;
reg [0:0] j_15_end_10_load_reg_14489;
reg [0:0] j_15_end_11_load_reg_14494;
reg [0:0] j_15_end_12_load_reg_14499;
reg [0:0] j_15_end_13_load_reg_14504;
reg [0:0] j_15_end_14_load_reg_14509;
reg [0:0] j_15_end_15_load_reg_14514;
wire [4:0] k_5_fu_13252_p2;
reg [4:0] k_5_reg_14522;
wire [63:0] tmp_8_fu_13258_p1;
reg [63:0] tmp_8_reg_14527;
wire [0:0] exitcond2_fu_13247_p2;
wire [3:0] tmp_36_fu_13263_p1;
reg [3:0] tmp_36_reg_14538;
wire [0:0] tmp_7_fu_13267_p2;
reg [0:0] tmp_7_reg_14542;
wire [31:0] tmp_39_fu_13272_p1;
wire [31:0] tmp_13_fu_13282_p4;
wire [0:0] tmp_11_fu_13276_p2;
wire [1:0] r_1_0_i_lcssa3_cast_fu_13298_p1;
wire [7:0] j_0_bucket_index_cast_fu_13311_p1;
reg [7:0] j_0_bucket_index_cast_reg_14592;
wire [4:0] k_7_fu_13544_p2;
reg [4:0] k_7_reg_14615;
wire [63:0] tmp_5_fu_13550_p1;
reg [63:0] tmp_5_reg_14621;
wire [0:0] tmp_9_fu_13539_p2;
wire [3:0] tmp_37_fu_13557_p1;
reg [3:0] tmp_37_reg_14631;
reg [3:0] next_buckets_addr_3_reg_14635;
reg [0:0] end_0_phi_fu_5844_p32;
reg [0:0] end_string_0_phi_fu_6831_p4;
reg [3:0] current_buckets_addr_1_reg_14640;
wire [7:0] state_0_fu_13574_p2;
reg [3:0] next_buckets_addr_4_reg_14670;
wire [0:0] not_s_fu_13615_p2;
reg [0:0] not_s_reg_14675;
wire [0:0] brmerge_demorgan_fu_13621_p2;
reg [0:0] brmerge_demorgan_reg_14680;
wire [31:0] sym_offset_0_1_25_fu_13631_p2;
reg [7:0] sample_addr_read_reg_14718;
wire [13:0] tmp_8_i1_fu_13669_p2;
reg [13:0] tmp_8_i1_reg_14723;
reg [31:0] nfa_forward_buckets_addr_read_reg_14735;
reg [31:0] nfa_forward_buckets_addr_1_read_reg_14746;
wire [4:0] k_6_fu_13723_p2;
reg [4:0] k_6_reg_14754;
wire [63:0] tmp_10_fu_13729_p1;
reg [63:0] tmp_10_reg_14775;
wire [0:0] exitcond_fu_13718_p2;
wire [3:0] tmp_38_fu_13733_p1;
reg [3:0] tmp_38_reg_14781;
wire [0:0] end_load_phi_phi_fu_12756_p32;
reg [3:0] next_buckets_addr_2_reg_14790;
reg [3:0] next_buckets_address0;
reg next_buckets_ce0;
reg next_buckets_we0;
reg [63:0] next_buckets_d0;
wire [63:0] next_buckets_q0;
reg [3:0] current_buckets_address0;
reg current_buckets_ce0;
reg current_buckets_we0;
reg [63:0] current_buckets_d0;
wire [63:0] current_buckets_q0;
reg [3:0] tmp_buckets_address0;
reg tmp_buckets_ce0;
reg tmp_buckets_we0;
reg [63:0] tmp_buckets_d0;
wire [63:0] tmp_buckets_q0;
wire grp_nfa_get_initials_1_fu_12896_ap_start;
wire grp_nfa_get_initials_1_fu_12896_ap_done;
wire grp_nfa_get_initials_1_fu_12896_ap_idle;
wire grp_nfa_get_initials_1_fu_12896_ap_ready;
wire grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_din;
wire grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_full_n;
wire grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_write;
wire grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_empty_n;
wire grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_read;
wire [31:0] grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_address;
wire [63:0] grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_datain;
wire [63:0] grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_dataout;
wire [31:0] grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_size;
wire grp_nfa_get_initials_1_fu_12896_ap_ce;
wire [3:0] grp_nfa_get_initials_1_fu_12896_initials_buckets_address0;
wire grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0;
wire grp_nfa_get_initials_1_fu_12896_initials_buckets_we0;
wire [63:0] grp_nfa_get_initials_1_fu_12896_initials_buckets_d0;
wire [4:0] grp_nfa_get_initials_1_fu_12896_tmp_s;
wire grp_nfa_get_finals_1_fu_12905_ap_start;
wire grp_nfa_get_finals_1_fu_12905_ap_done;
wire grp_nfa_get_finals_1_fu_12905_ap_idle;
wire grp_nfa_get_finals_1_fu_12905_ap_ready;
wire grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_din;
wire grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_full_n;
wire grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_write;
wire grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_empty_n;
wire grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_read;
wire [31:0] grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_address;
wire [63:0] grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_datain;
wire [63:0] grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_dataout;
wire [31:0] grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_size;
wire grp_nfa_get_finals_1_fu_12905_ap_ce;
wire [3:0] grp_nfa_get_finals_1_fu_12905_finals_buckets_address0;
wire grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0;
wire grp_nfa_get_finals_1_fu_12905_finals_buckets_we0;
wire [63:0] grp_nfa_get_finals_1_fu_12905_finals_buckets_d0;
wire [4:0] grp_nfa_get_finals_1_fu_12905_tmp_28;
wire [31:0] r_bit_p_bsf32_hw_fu_12914_bus_r;
wire [5:0] r_bit_p_bsf32_hw_fu_12914_ap_return;
reg [4:0] k_reg_612;
reg [7:0] state_15_2_reg_4611;
reg [7:0] state_15_s_reg_624;
wire [0:0] all_end_phi_fu_12651_p36;
reg [7:0] state_14_2_reg_4626;
reg [7:0] state_14_s_reg_636;
reg [7:0] state_13_2_reg_4641;
reg [7:0] state_13_s_reg_648;
reg [7:0] state_12_2_reg_4656;
reg [7:0] state_12_s_reg_660;
reg [7:0] state_11_2_reg_4671;
reg [7:0] state_11_s_reg_672;
reg [7:0] state_10_2_reg_4686;
reg [7:0] state_10_s_reg_684;
reg [7:0] state_9_2_reg_4701;
reg [7:0] state_9_s_reg_696;
reg [7:0] state_8_2_reg_4716;
reg [7:0] state_8_s_reg_708;
reg [7:0] state_7_2_reg_4731;
reg [7:0] state_7_s_reg_720;
reg [7:0] state_6_2_reg_4746;
reg [7:0] state_6_s_reg_732;
reg [7:0] state_5_2_reg_4761;
reg [7:0] state_5_s_reg_744;
reg [7:0] state_4_2_reg_4776;
reg [7:0] state_4_s_reg_756;
reg [7:0] state_3_2_reg_4791;
reg [7:0] state_3_s_reg_768;
reg [7:0] state_2_2_reg_4806;
reg [7:0] state_2_s_reg_780;
reg [7:0] state_1_2_reg_4821;
reg [7:0] state_1_s_reg_792;
reg [7:0] state_0_2_reg_4836;
reg [7:0] state_0_s_reg_804;
reg [0:0] end_15_2_reg_4851;
reg [0:0] end_15_s_reg_816;
reg [0:0] end_14_2_reg_4866;
reg [0:0] end_14_s_reg_828;
reg [0:0] end_13_2_reg_4881;
reg [0:0] end_13_s_reg_840;
reg [0:0] end_12_2_reg_4896;
reg [0:0] end_12_s_reg_852;
reg [0:0] end_11_2_reg_4911;
reg [0:0] end_11_s_reg_864;
reg [0:0] end_10_2_reg_4926;
reg [0:0] end_10_s_reg_876;
reg [0:0] end_9_2_reg_4941;
reg [0:0] end_9_s_reg_888;
reg [0:0] end_8_2_reg_4956;
reg [0:0] end_8_s_reg_900;
reg [0:0] end_7_2_reg_4971;
reg [0:0] end_7_s_reg_912;
reg [0:0] end_6_2_reg_4986;
reg [0:0] end_6_s_reg_924;
reg [0:0] end_5_2_reg_5001;
reg [0:0] end_5_s_reg_936;
reg [0:0] end_4_2_reg_5016;
reg [0:0] end_4_s_reg_948;
reg [0:0] end_3_2_reg_5031;
reg [0:0] end_3_s_reg_960;
reg [0:0] end_2_2_reg_5046;
reg [0:0] end_2_s_reg_972;
reg [0:0] end_1_2_reg_5061;
reg [0:0] end_1_s_reg_984;
reg [0:0] end_0_2_reg_5076;
reg [0:0] end_0_s_reg_996;
reg [0:0] any_state_15_4_reg_5091;
reg [0:0] any_state_s_reg_1008;
reg [0:0] any_state_14_4_reg_5106;
reg [0:0] any_state_14_reg_1020;
reg [0:0] any_state_13_4_reg_5121;
reg [0:0] any_state_13_reg_1032;
reg [0:0] any_state_12_4_reg_5136;
reg [0:0] any_state_12_reg_1044;
reg [0:0] any_state_11_4_reg_5151;
reg [0:0] any_state_11_reg_1056;
reg [0:0] any_state_10_4_reg_5166;
reg [0:0] any_state_10_reg_1068;
reg [0:0] any_state_9_4_reg_5181;
reg [0:0] any_state_9_reg_1080;
reg [0:0] any_state_8_4_reg_5196;
reg [0:0] any_state_8_reg_1092;
reg [0:0] any_state_7_4_reg_5211;
reg [0:0] any_state_7_reg_1104;
reg [0:0] any_state_6_4_reg_5226;
reg [0:0] any_state_6_reg_1116;
reg [0:0] any_state_5_4_reg_5241;
reg [0:0] any_state_5_reg_1128;
reg [0:0] any_state_4_4_reg_5256;
reg [0:0] any_state_4_reg_1140;
reg [0:0] any_state_3_4_reg_5271;
reg [0:0] any_state_3_reg_1152;
reg [0:0] any_state_2_4_reg_5286;
reg [0:0] any_state_2_reg_1164;
reg [0:0] any_state_1_4_reg_5301;
reg [0:0] any_state_1_reg_1176;
reg [0:0] any_state_0_4_reg_5316;
reg [0:0] any_state_reg_1188;
reg [31:0] sym_offset_15_4_reg_5331;
reg [31:0] sym_offset_s_reg_1200;
reg [31:0] sym_offset_14_4_reg_5347;
reg [31:0] sym_offset_14_reg_1212;
reg [31:0] sym_offset_13_4_reg_5363;
reg [31:0] sym_offset_13_reg_1224;
reg [31:0] sym_offset_12_4_reg_5379;
reg [31:0] sym_offset_12_reg_1236;
reg [31:0] sym_offset_11_4_reg_5395;
reg [31:0] sym_offset_11_reg_1248;
reg [31:0] sym_offset_10_4_reg_5411;
reg [31:0] sym_offset_10_reg_1260;
reg [31:0] sym_offset_9_4_reg_5427;
reg [31:0] sym_offset_9_reg_1272;
reg [31:0] sym_offset_8_4_reg_5443;
reg [31:0] sym_offset_8_reg_1284;
reg [31:0] sym_offset_7_4_reg_5459;
reg [31:0] sym_offset_7_reg_1296;
reg [31:0] sym_offset_6_4_reg_5475;
reg [31:0] sym_offset_6_reg_1308;
reg [31:0] sym_offset_5_4_reg_5491;
reg [31:0] sym_offset_5_reg_1320;
reg [31:0] sym_offset_4_4_reg_5507;
reg [31:0] sym_offset_4_reg_1332;
reg [31:0] sym_offset_3_4_reg_5523;
reg [31:0] sym_offset_3_reg_1344;
reg [31:0] sym_offset_2_4_reg_5539;
reg [31:0] sym_offset_2_reg_1356;
reg [31:0] sym_offset_1_4_reg_5555;
reg [31:0] sym_offset_1_reg_1368;
reg [31:0] sym_offset_0_4_reg_5571;
reg [31:0] sym_offset_reg_1380;
reg [0:0] end_string_15_4_reg_5587;
reg [0:0] end_string_15_2_reg_1392;
wire [0:0] exitcond3_fu_12991_p2;
reg [0:0] end_string_14_4_reg_5602;
reg [0:0] end_string_14_2_reg_1402;
reg [0:0] end_string_13_4_reg_5617;
reg [0:0] end_string_13_2_reg_1412;
reg [0:0] end_string_12_4_reg_5632;
reg [0:0] end_string_12_2_reg_1422;
reg [0:0] end_string_11_4_reg_5647;
reg [0:0] end_string_11_2_reg_1432;
reg [0:0] end_string_10_4_reg_5662;
reg [0:0] end_string_10_2_reg_1442;
reg [0:0] end_string_9_4_reg_5677;
reg [0:0] end_string_9_2_reg_1452;
reg [0:0] end_string_8_4_reg_5692;
reg [0:0] end_string_8_2_reg_1462;
reg [0:0] end_string_7_4_reg_5707;
reg [0:0] end_string_7_2_reg_1472;
reg [0:0] end_string_6_4_reg_5722;
reg [0:0] end_string_6_2_reg_1482;
reg [0:0] end_string_5_4_reg_5737;
reg [0:0] end_string_5_2_reg_1492;
reg [0:0] end_string_4_4_reg_5752;
reg [0:0] end_string_4_2_reg_1502;
reg [0:0] end_string_3_4_reg_5767;
reg [0:0] end_string_3_2_reg_1512;
reg [0:0] end_string_2_4_reg_5782;
reg [0:0] end_string_2_2_reg_1522;
reg [0:0] end_string_1_4_reg_5797;
reg [0:0] end_string_1_2_reg_1532;
reg [0:0] end_string_0_4_reg_5812;
reg [0:0] end_string_0_2_reg_1542;
reg [15:0] i_reg_1552;
reg [0:0] any_state_15_1_reg_1561;
wire [0:0] tmp_6_fu_13097_p2;
reg [0:0] any_state_15_2_reg_2788;
reg [0:0] any_state_14_1_reg_1572;
reg [0:0] any_state_14_2_reg_2844;
reg [0:0] any_state_13_1_reg_1583;
reg [0:0] any_state_13_2_reg_2900;
reg [0:0] any_state_12_1_reg_1594;
reg [0:0] any_state_12_2_reg_2956;
reg [0:0] any_state_11_1_reg_1605;
reg [0:0] any_state_11_2_reg_3012;
reg [0:0] any_state_10_1_reg_1616;
reg [0:0] any_state_10_2_reg_3068;
reg [0:0] any_state_9_1_reg_1627;
reg [0:0] any_state_9_2_reg_3124;
reg [0:0] any_state_8_1_reg_1638;
reg [0:0] any_state_8_2_reg_3180;
reg [0:0] any_state_7_1_reg_1649;
reg [0:0] any_state_7_2_reg_3236;
reg [0:0] any_state_6_1_reg_1660;
reg [0:0] any_state_6_2_reg_3292;
reg [0:0] any_state_5_1_reg_1671;
reg [0:0] any_state_5_2_reg_3348;
reg [0:0] any_state_4_1_reg_1682;
reg [0:0] any_state_4_2_reg_3404;
reg [0:0] any_state_3_1_reg_1693;
reg [0:0] any_state_3_2_reg_3460;
reg [0:0] any_state_2_1_reg_1704;
reg [0:0] any_state_2_2_reg_3516;
reg [0:0] any_state_1_1_reg_1715;
reg [0:0] any_state_1_2_reg_3572;
reg [0:0] any_state_0_1_reg_1726;
reg [0:0] any_state_0_2_reg_3628;
reg [31:0] sym_offset_15_1_reg_1737;
reg [31:0] sym_offset_15_2_reg_1924;
reg [31:0] sym_offset_14_1_reg_1748;
reg [31:0] sym_offset_14_2_reg_1978;
reg [31:0] sym_offset_13_1_reg_1759;
reg [31:0] sym_offset_13_2_reg_2032;
reg [31:0] sym_offset_12_1_reg_1770;
reg [31:0] sym_offset_12_2_reg_2086;
reg [31:0] sym_offset_11_1_reg_1781;
reg [31:0] sym_offset_11_2_reg_2140;
reg [31:0] sym_offset_10_1_reg_1792;
reg [31:0] sym_offset_10_2_reg_2194;
reg [31:0] sym_offset_9_1_reg_1803;
reg [31:0] sym_offset_9_2_reg_2248;
reg [31:0] sym_offset_8_1_reg_1814;
reg [31:0] sym_offset_8_2_reg_2302;
reg [31:0] sym_offset_7_1_reg_1825;
reg [31:0] sym_offset_7_2_reg_2356;
reg [31:0] sym_offset_6_1_reg_1836;
reg [31:0] sym_offset_6_2_reg_2410;
reg [31:0] sym_offset_5_1_reg_1847;
reg [31:0] sym_offset_5_2_reg_2464;
reg [31:0] sym_offset_4_1_reg_1858;
reg [31:0] sym_offset_4_2_reg_2518;
reg [31:0] sym_offset_3_1_reg_1869;
reg [31:0] sym_offset_3_2_reg_2572;
reg [31:0] sym_offset_2_1_reg_1880;
reg [31:0] sym_offset_2_2_reg_2626;
reg [31:0] sym_offset_1_1_reg_1891;
reg [31:0] sym_offset_1_2_reg_2680;
reg [31:0] sym_offset_0_1_reg_1902;
reg [31:0] sym_offset_0_2_reg_2734;
reg [4:0] k_1_reg_1913;
reg [31:0] bus_assign_reg_3684;
wire [0:0] tmp_27_1_fu_13292_p2;
reg [0:0] r_1_0_i_lcssa3_reg_3693;
reg [1:0] j_0_bucket_index_reg_3706;
reg [0:0] j_0_end_reg_3717;
reg [7:0] state_15_1_reg_3731;
reg [7:0] state_14_1_reg_3742;
reg [7:0] state_13_1_reg_3753;
reg [7:0] state_12_1_reg_3764;
reg [7:0] state_11_1_reg_3775;
reg [7:0] state_10_1_reg_3786;
reg [7:0] state_9_1_reg_3797;
reg [7:0] state_8_1_reg_3808;
reg [7:0] state_7_1_reg_3819;
reg [7:0] state_6_1_reg_3830;
reg [7:0] state_5_1_reg_3841;
reg [7:0] state_4_1_reg_3852;
reg [7:0] state_3_1_reg_3863;
reg [7:0] state_2_1_reg_3874;
reg [7:0] state_1_1_reg_3885;
reg [7:0] state_0_1_reg_3896;
reg [0:0] end_15_1_reg_3907;
reg [0:0] end_14_1_reg_3918;
reg [0:0] end_13_1_reg_3929;
reg [0:0] end_12_1_reg_3940;
reg [0:0] end_11_1_reg_3951;
reg [0:0] end_10_1_reg_3962;
reg [0:0] end_9_1_reg_3973;
reg [0:0] end_8_1_reg_3984;
reg [0:0] end_7_1_reg_3995;
reg [0:0] end_6_1_reg_4006;
reg [0:0] end_5_1_reg_4017;
reg [0:0] end_4_1_reg_4028;
reg [0:0] end_3_1_reg_4039;
reg [0:0] end_2_1_reg_4050;
reg [0:0] end_1_1_reg_4061;
reg [0:0] end_0_1_reg_4072;
reg [0:0] any_state_15_3_reg_4083;
reg [0:0] any_state_14_3_reg_4094;
reg [0:0] any_state_13_3_reg_4105;
reg [0:0] any_state_12_3_reg_4116;
reg [0:0] any_state_11_3_reg_4127;
reg [0:0] any_state_10_3_reg_4138;
reg [0:0] any_state_9_3_reg_4149;
reg [0:0] any_state_8_3_reg_4160;
reg [0:0] any_state_7_3_reg_4171;
reg [0:0] any_state_6_3_reg_4182;
reg [0:0] any_state_5_3_reg_4193;
reg [0:0] any_state_4_3_reg_4204;
reg [0:0] any_state_3_3_reg_4215;
reg [0:0] any_state_2_3_reg_4226;
reg [0:0] any_state_1_3_reg_4237;
reg [0:0] any_state_0_3_reg_4248;
reg [31:0] sym_offset_15_3_reg_4259;
reg [31:0] sym_offset_14_3_reg_4270;
reg [31:0] sym_offset_13_3_reg_4281;
reg [31:0] sym_offset_12_3_reg_4292;
reg [31:0] sym_offset_11_3_reg_4303;
reg [31:0] sym_offset_10_3_reg_4314;
reg [31:0] sym_offset_9_3_reg_4325;
reg [31:0] sym_offset_8_3_reg_4336;
reg [31:0] sym_offset_7_3_reg_4347;
reg [31:0] sym_offset_6_3_reg_4358;
reg [31:0] sym_offset_5_3_reg_4369;
reg [31:0] sym_offset_4_3_reg_4380;
reg [31:0] sym_offset_3_3_reg_4391;
reg [31:0] sym_offset_2_3_reg_4402;
reg [31:0] sym_offset_1_3_reg_4413;
reg [31:0] sym_offset_0_3_reg_4424;
reg [0:0] end_string_15_3_reg_4435;
reg [0:0] end_string_14_3_reg_4446;
reg [0:0] end_string_13_3_reg_4457;
reg [0:0] end_string_12_3_reg_4468;
reg [0:0] end_string_11_3_reg_4479;
reg [0:0] end_string_10_3_reg_4490;
reg [0:0] end_string_9_3_reg_4501;
reg [0:0] end_string_8_3_reg_4512;
reg [0:0] end_string_7_3_reg_4523;
reg [0:0] end_string_6_3_reg_4534;
reg [0:0] end_string_5_3_reg_4545;
reg [0:0] end_string_4_3_reg_4556;
reg [0:0] end_string_3_3_reg_4567;
reg [0:0] end_string_2_3_reg_4578;
reg [0:0] end_string_1_3_reg_4589;
reg [0:0] end_string_0_3_reg_4600;
reg [7:0] state_15_4_reg_8712;
reg [0:0] end_load_3_phi_phi_fu_11584_p32;
wire [0:0] tmp1_fu_13626_p2;
reg [7:0] state_14_4_reg_8770;
reg [7:0] state_13_4_reg_8828;
reg [7:0] state_12_4_reg_8886;
reg [7:0] state_11_4_reg_8944;
reg [7:0] state_10_4_reg_9002;
reg [7:0] state_9_4_reg_9060;
reg [7:0] state_8_4_reg_9118;
reg [7:0] state_7_4_reg_9176;
reg [7:0] state_6_4_reg_9234;
reg [7:0] state_5_4_reg_9292;
reg [7:0] state_4_4_reg_9350;
reg [7:0] state_3_4_reg_9408;
reg [7:0] state_2_4_reg_9466;
reg [7:0] state_1_4_reg_9524;
reg [7:0] state_0_4_reg_9582;
reg [0:0] end_15_3_reg_5879;
reg [0:0] end_14_3_reg_5935;
reg [0:0] end_13_3_reg_5991;
reg [0:0] end_12_3_reg_6047;
reg [0:0] end_11_3_reg_6103;
reg [0:0] end_10_3_reg_6159;
reg [0:0] end_9_3_reg_6215;
reg [0:0] end_8_3_reg_6271;
reg [0:0] end_7_3_reg_6327;
reg [0:0] end_6_3_reg_6383;
reg [0:0] end_5_3_reg_6439;
reg [0:0] end_4_3_reg_6495;
reg [0:0] end_3_3_reg_6551;
reg [0:0] end_2_3_reg_6607;
reg [0:0] end_1_3_reg_6663;
reg [0:0] end_0_3_reg_6719;
reg [0:0] any_state_15_6_reg_9640;
reg [0:0] any_state_14_6_reg_9699;
reg [0:0] any_state_13_6_reg_9758;
reg [0:0] any_state_12_6_reg_9817;
reg [0:0] any_state_11_6_reg_9876;
reg [0:0] any_state_10_6_reg_9935;
reg [0:0] any_state_9_6_reg_9994;
reg [0:0] any_state_8_6_reg_10053;
reg [0:0] any_state_7_6_reg_10112;
reg [0:0] any_state_6_6_reg_10171;
reg [0:0] any_state_5_6_reg_10230;
reg [0:0] any_state_4_6_reg_10289;
reg [0:0] any_state_3_6_reg_10348;
reg [0:0] any_state_2_6_reg_10407;
reg [0:0] any_state_1_6_reg_10466;
reg [0:0] any_state_0_6_reg_10525;
reg [31:0] sym_offset_15_5_reg_11687;
reg [31:0] sym_offset_14_5_reg_11741;
reg [31:0] sym_offset_13_5_reg_11795;
reg [31:0] sym_offset_12_5_reg_11849;
reg [31:0] sym_offset_11_5_reg_11903;
reg [31:0] sym_offset_10_5_reg_11957;
reg [31:0] sym_offset_9_5_reg_12011;
reg [31:0] sym_offset_8_5_reg_12065;
reg [31:0] sym_offset_7_5_reg_12119;
reg [31:0] sym_offset_6_5_reg_12173;
reg [31:0] sym_offset_5_5_reg_12227;
reg [31:0] sym_offset_4_5_reg_12281;
reg [31:0] sym_offset_3_5_reg_12335;
reg [31:0] sym_offset_2_5_reg_12389;
reg [31:0] sym_offset_1_5_reg_12443;
reg [31:0] sym_offset_0_5_reg_12497;
reg [0:0] end_string_15_6_reg_10584;
reg [0:0] end_string_14_6_reg_10643;
reg [0:0] end_string_13_6_reg_10702;
reg [0:0] end_string_12_6_reg_10761;
reg [0:0] end_string_11_6_reg_10820;
reg [0:0] end_string_10_6_reg_10879;
reg [0:0] end_string_9_6_reg_10938;
reg [0:0] end_string_8_6_reg_10997;
reg [0:0] end_string_7_6_reg_11056;
reg [0:0] end_string_6_6_reg_11115;
reg [0:0] end_string_5_6_reg_11174;
reg [0:0] end_string_4_6_reg_11233;
reg [0:0] end_string_3_6_reg_11292;
reg [0:0] end_string_2_6_reg_11351;
reg [0:0] end_string_1_6_reg_11410;
reg [0:0] end_string_0_6_reg_11469;
reg [4:0] k_2_reg_5827;
reg [0:0] end_0_reg_5841;
reg [0:0] any_state_load_phi_phi_fu_6778_p32;
wire [0:0] tmp_12_fu_13561_p2;
reg [0:0] end_string_0_reg_6828;
reg [0:0] end_string_15_5_reg_6839;
reg [0:0] end_string_14_5_reg_6893;
reg [0:0] end_string_13_5_reg_6947;
reg [0:0] end_string_12_5_reg_7001;
reg [0:0] end_string_11_5_reg_7055;
reg [0:0] end_string_10_5_reg_7109;
reg [0:0] end_string_9_5_reg_7163;
reg [0:0] end_string_8_5_reg_7217;
reg [0:0] end_string_7_5_reg_7271;
reg [0:0] end_string_6_5_reg_7325;
reg [0:0] end_string_5_5_reg_7379;
reg [0:0] end_string_4_5_reg_7433;
reg [0:0] end_string_3_5_reg_7487;
reg [0:0] end_string_2_5_reg_7541;
reg [0:0] end_string_1_5_reg_7595;
reg [0:0] end_string_0_5_reg_7649;
reg [0:0] any_state_load_1_phi_phi_fu_7706_p32;
reg [0:0] any_state_load_1_phi_reg_7703;
reg [0:0] any_state_15_5_reg_7757;
reg [0:0] any_state_14_5_reg_7812;
reg [0:0] any_state_13_5_reg_7867;
reg [0:0] any_state_12_5_reg_7922;
reg [0:0] any_state_11_5_reg_7977;
reg [0:0] any_state_10_5_reg_8032;
reg [0:0] any_state_9_5_reg_8087;
reg [0:0] any_state_8_5_reg_8142;
reg [0:0] any_state_7_5_reg_8197;
reg [0:0] any_state_6_5_reg_8252;
reg [0:0] any_state_5_5_reg_8307;
reg [0:0] any_state_4_5_reg_8362;
reg [0:0] any_state_3_5_reg_8417;
reg [0:0] any_state_2_5_reg_8472;
reg [0:0] any_state_1_5_reg_8527;
reg [0:0] any_state_0_5_reg_8582;
reg [7:0] j_bit_addr12_phi_reg_8637;
reg [7:0] j_bucket_index_addr13_phi_reg_8675;
reg [0:0] end_string_15_6_phi_fu_10589_p34;
reg [0:0] end_string_14_6_phi_fu_10648_p34;
reg [0:0] end_string_13_6_phi_fu_10707_p34;
reg [0:0] end_string_12_6_phi_fu_10766_p34;
reg [0:0] end_string_11_6_phi_fu_10825_p34;
reg [0:0] end_string_10_6_phi_fu_10884_p34;
reg [0:0] end_string_9_6_phi_fu_10943_p34;
reg [0:0] end_string_8_6_phi_fu_11002_p34;
reg [0:0] end_string_7_6_phi_fu_11061_p34;
reg [0:0] end_string_6_6_phi_fu_11120_p34;
reg [0:0] end_string_5_6_phi_fu_11179_p34;
reg [0:0] end_string_4_6_phi_fu_11238_p34;
reg [0:0] end_string_3_6_phi_fu_11297_p34;
reg [0:0] end_string_2_6_phi_fu_11356_p34;
reg [0:0] end_string_1_6_phi_fu_11415_p34;
reg [0:0] end_string_0_6_phi_fu_11474_p34;
reg [0:0] end_string_load_phi_phi_fu_11531_p32;
reg [31:0] offset_reg_11634;
reg [7:0] state_assign_in_reg_12551;
reg [4:0] k_3_reg_12604;
reg [0:0] any_end_reg_12691;
reg [0:0] all_end_reg_12647;
reg [0:0] end_load_phi_reg_12753;
reg [0:0] all_end_1_reg_12807;
reg [0:0] p_0_reg_12882;
reg grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg = 1'b0;
reg [5:0] ap_NS_fsm;
reg grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg = 1'b0;
wire [63:0] tmp_s_fu_13002_p1;
wire [3:0] tmp_buckets_addr_1_gep_fu_547_p3;
wire [3:0] result_addr_gep_fu_575_p3;
wire [3:0] tmp_buckets_addr_3_gep_fu_591_p3;
wire [63:0] tmp_15_fu_13637_p1;
wire [63:0] tmp_82_i_cast_fu_13682_p1;
wire [63:0] tmp_83_i_cast_fu_13700_p1;
wire [0:0] end_string_fu_152;
wire [3:0] tmp_35_fu_13007_p1;
wire [0:0] end_string_1_fu_156;
wire [0:0] end_string_2_fu_160;
wire [0:0] end_string_3_fu_164;
wire [0:0] end_string_4_fu_168;
wire [0:0] end_string_5_fu_172;
wire [0:0] end_string_6_fu_176;
wire [0:0] end_string_7_fu_180;
wire [0:0] end_string_8_fu_184;
wire [0:0] end_string_9_fu_188;
wire [0:0] end_string_10_fu_192;
wire [0:0] end_string_11_fu_196;
wire [0:0] end_string_12_fu_200;
wire [0:0] end_string_13_fu_204;
wire [0:0] end_string_14_fu_208;
wire [0:0] end_string_s_fu_212;
reg [7:0] j_15_bit_17_fu_228;
wire [7:0] j_15_bit_16_fu_13302_p1;
reg [7:0] j_15_bit_fu_232;
reg [7:0] j_15_bit_1_fu_236;
reg [7:0] j_15_bit_2_fu_240;
reg [7:0] j_15_bit_3_fu_244;
reg [7:0] j_15_bit_4_fu_248;
reg [7:0] j_15_bit_5_fu_252;
reg [7:0] j_15_bit_6_fu_256;
reg [7:0] j_15_bit_7_fu_260;
reg [7:0] j_15_bit_8_fu_264;
reg [7:0] j_15_bit_9_fu_268;
reg [7:0] j_15_bit_10_fu_272;
reg [7:0] j_15_bit_11_fu_276;
reg [7:0] j_15_bit_12_fu_280;
reg [7:0] j_15_bit_13_fu_284;
reg [7:0] j_15_bit_14_fu_288;
reg [7:0] j_15_bit_15_fu_292;
reg [7:0] j_bucket_index_0_s_fu_296;
reg [7:0] j_bucket_index_1_s_fu_300;
reg [7:0] j_bucket_index_2_s_fu_304;
reg [7:0] j_bucket_index_3_s_fu_308;
reg [7:0] j_bucket_index_4_s_fu_312;
reg [7:0] j_bucket_index_5_s_fu_316;
reg [7:0] j_bucket_index_6_s_fu_320;
reg [7:0] j_bucket_index_7_s_fu_324;
reg [7:0] j_bucket_index_8_s_fu_328;
reg [7:0] j_bucket_index_9_s_fu_332;
reg [7:0] j_bucket_index_10_s_fu_336;
reg [7:0] j_bucket_index_11_s_fu_340;
reg [7:0] j_bucket_index_12_s_fu_344;
reg [7:0] j_bucket_index_13_s_fu_348;
reg [7:0] j_bucket_index_14_s_fu_352;
reg [7:0] j_bucket_index_15_s_fu_356;
reg [0:0] j_15_end_fu_360;
reg [0:0] j_15_end_1_fu_364;
reg [0:0] j_15_end_2_fu_368;
reg [0:0] j_15_end_3_fu_372;
reg [0:0] j_15_end_4_fu_376;
reg [0:0] j_15_end_5_fu_380;
reg [0:0] j_15_end_6_fu_384;
reg [0:0] j_15_end_7_fu_388;
reg [0:0] j_15_end_8_fu_392;
reg [0:0] j_15_end_9_fu_396;
reg [0:0] j_15_end_10_fu_400;
reg [0:0] j_15_end_11_fu_404;
reg [0:0] j_15_end_12_fu_408;
reg [0:0] j_15_end_13_fu_412;
reg [0:0] j_15_end_14_fu_416;
reg [0:0] j_15_end_15_fu_420;
wire [63:0] tmp_49_i_fu_13600_p3;
wire [63:0] tmp_68_i_fu_13757_p3;
wire [63:0] tmp_84_i_fu_13711_p3;
wire [7:0] tmp_42_fu_13568_p2;
wire [31:0] tmp_44_fu_13584_p1;
wire [31:0] tmp_43_fu_13580_p1;
wire [31:0] grp_fu_12923_p4;
wire [31:0] grp_fu_12933_p4;
wire [31:0] tmp_8_1_i_fu_13594_p2;
wire [31:0] tmp_8_i_fu_13588_p2;
wire [31:0] tmp_1_fu_13609_p2;
wire [5:0] tmp_45_fu_13648_p1;
wire [7:0] tmp_6_i_fu_13660_p0;
wire [5:0] tmp_6_i_fu_13660_p1;
wire [13:0] tmp_6_i_fu_13660_p2;
wire [13:0] tmp_7_i_cast_fu_13666_p1;
wire [14:0] tmp_82_i_fu_13675_p3;
wire [14:0] tmp_83_i_fu_13693_p3;
wire [31:0] tmp_41_fu_13741_p1;
wire [31:0] tmp_40_fu_13737_p1;
wire [31:0] tmp_6_1_i_fu_13751_p2;
wire [31:0] tmp_57_i_fu_13745_p2;
reg [0:0] ap_return_preg = 1'b0;
wire [13:0] tmp_6_i_fu_13660_p00;
wire [13:0] tmp_6_i_fu_13660_p10;
reg ap_sig_bdd_2953;
reg ap_sig_bdd_2955;
reg ap_sig_bdd_2957;
reg ap_sig_bdd_2959;
reg ap_sig_bdd_2961;
reg ap_sig_bdd_2963;
reg ap_sig_bdd_2965;
reg ap_sig_bdd_2967;
reg ap_sig_bdd_2969;
reg ap_sig_bdd_2971;
reg ap_sig_bdd_2973;
reg ap_sig_bdd_2975;
reg ap_sig_bdd_2977;
reg ap_sig_bdd_2979;
reg ap_sig_bdd_2981;
reg ap_sig_bdd_2983;
reg ap_sig_bdd_1962;
reg ap_sig_bdd_1739;
reg ap_sig_bdd_1202;
reg ap_sig_bdd_327;
reg ap_sig_bdd_2491;
reg ap_sig_bdd_2495;
reg ap_sig_bdd_2499;
reg ap_sig_bdd_2503;
reg ap_sig_bdd_2507;
reg ap_sig_bdd_2511;
reg ap_sig_bdd_2515;
reg ap_sig_bdd_2519;
reg ap_sig_bdd_2523;
reg ap_sig_bdd_2527;
reg ap_sig_bdd_2531;
reg ap_sig_bdd_2535;
reg ap_sig_bdd_2539;
reg ap_sig_bdd_2543;
reg ap_sig_bdd_2547;
reg ap_sig_bdd_2551;
reg ap_sig_bdd_395;
reg ap_sig_bdd_1793;
reg ap_sig_bdd_2557;
reg ap_sig_bdd_2561;
reg ap_sig_bdd_2565;
reg ap_sig_bdd_2569;
reg ap_sig_bdd_2573;
reg ap_sig_bdd_2577;
reg ap_sig_bdd_2581;
reg ap_sig_bdd_2585;
reg ap_sig_bdd_2589;
reg ap_sig_bdd_2593;
reg ap_sig_bdd_2597;
reg ap_sig_bdd_2601;
reg ap_sig_bdd_2605;
reg ap_sig_bdd_2609;
reg ap_sig_bdd_2613;
reg ap_sig_bdd_2617;
reg ap_sig_bdd_369;
nfa_accept_sample_multi_next_buckets #(
.DataWidth( 64 ),
.AddressRange( 16 ),
.AddressWidth( 4 ))
next_buckets_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( next_buckets_address0 ),
.ce0( next_buckets_ce0 ),
.we0( next_buckets_we0 ),
.d0( next_buckets_d0 ),
.q0( next_buckets_q0 )
);
nfa_accept_sample_multi_next_buckets #(
.DataWidth( 64 ),
.AddressRange( 16 ),
.AddressWidth( 4 ))
current_buckets_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( current_buckets_address0 ),
.ce0( current_buckets_ce0 ),
.we0( current_buckets_we0 ),
.d0( current_buckets_d0 ),
.q0( current_buckets_q0 )
);
nfa_accept_sample_multi_next_buckets #(
.DataWidth( 64 ),
.AddressRange( 16 ),
.AddressWidth( 4 ))
tmp_buckets_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( tmp_buckets_address0 ),
.ce0( tmp_buckets_ce0 ),
.we0( tmp_buckets_we0 ),
.d0( tmp_buckets_d0 ),
.q0( tmp_buckets_q0 )
);
nfa_get_initials_1 grp_nfa_get_initials_1_fu_12896(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_initials_1_fu_12896_ap_start ),
.ap_done( grp_nfa_get_initials_1_fu_12896_ap_done ),
.ap_idle( grp_nfa_get_initials_1_fu_12896_ap_idle ),
.ap_ready( grp_nfa_get_initials_1_fu_12896_ap_ready ),
.nfa_initials_buckets_req_din( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_din ),
.nfa_initials_buckets_req_full_n( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_full_n ),
.nfa_initials_buckets_req_write( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_write ),
.nfa_initials_buckets_rsp_empty_n( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_empty_n ),
.nfa_initials_buckets_rsp_read( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_read ),
.nfa_initials_buckets_address( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_address ),
.nfa_initials_buckets_datain( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_datain ),
.nfa_initials_buckets_dataout( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_dataout ),
.nfa_initials_buckets_size( grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_size ),
.ap_ce( grp_nfa_get_initials_1_fu_12896_ap_ce ),
.initials_buckets_address0( grp_nfa_get_initials_1_fu_12896_initials_buckets_address0 ),
.initials_buckets_ce0( grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0 ),
.initials_buckets_we0( grp_nfa_get_initials_1_fu_12896_initials_buckets_we0 ),
.initials_buckets_d0( grp_nfa_get_initials_1_fu_12896_initials_buckets_d0 ),
.tmp_s( grp_nfa_get_initials_1_fu_12896_tmp_s )
);
nfa_get_finals_1 grp_nfa_get_finals_1_fu_12905(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_finals_1_fu_12905_ap_start ),
.ap_done( grp_nfa_get_finals_1_fu_12905_ap_done ),
.ap_idle( grp_nfa_get_finals_1_fu_12905_ap_idle ),
.ap_ready( grp_nfa_get_finals_1_fu_12905_ap_ready ),
.nfa_finals_buckets_req_din( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_din ),
.nfa_finals_buckets_req_full_n( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_full_n ),
.nfa_finals_buckets_req_write( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_write ),
.nfa_finals_buckets_rsp_empty_n( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_empty_n ),
.nfa_finals_buckets_rsp_read( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_read ),
.nfa_finals_buckets_address( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_address ),
.nfa_finals_buckets_datain( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_datain ),
.nfa_finals_buckets_dataout( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_dataout ),
.nfa_finals_buckets_size( grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_size ),
.ap_ce( grp_nfa_get_finals_1_fu_12905_ap_ce ),
.finals_buckets_address0( grp_nfa_get_finals_1_fu_12905_finals_buckets_address0 ),
.finals_buckets_ce0( grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0 ),
.finals_buckets_we0( grp_nfa_get_finals_1_fu_12905_finals_buckets_we0 ),
.finals_buckets_d0( grp_nfa_get_finals_1_fu_12905_finals_buckets_d0 ),
.tmp_28( grp_nfa_get_finals_1_fu_12905_tmp_28 )
);
p_bsf32_hw r_bit_p_bsf32_hw_fu_12914(
.bus_r( r_bit_p_bsf32_hw_fu_12914_bus_r ),
.ap_return( r_bit_p_bsf32_hw_fu_12914_ap_return )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_return_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_preg
if (ap_rst == 1'b1) begin
ap_return_preg <= ap_const_lv1_0;
end else begin
if ((ap_ST_st48_fsm_47 == ap_CS_fsm)) begin
ap_return_preg <= p_0_reg_12882;
end
end
end
/// grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & (ap_ST_st24_fsm_23 == ap_NS_fsm))) begin
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_finals_1_fu_12905_ap_ready)) begin
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & (ap_ST_st3_fsm_2 == ap_NS_fsm))) begin
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_initials_1_fu_12896_ap_ready)) begin
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st46_fsm_45 == ap_CS_fsm)) begin
if ((ap_const_lv1_0 == all_end_reg_12647)) begin
all_end_1_reg_12807 <= ap_const_lv1_0;
end else if (ap_sig_bdd_2983) begin
all_end_1_reg_12807 <= end_0_2_reg_5076;
end else if (ap_sig_bdd_2981) begin
all_end_1_reg_12807 <= end_15_2_reg_4851;
end else if (ap_sig_bdd_2979) begin
all_end_1_reg_12807 <= end_14_2_reg_4866;
end else if (ap_sig_bdd_2977) begin
all_end_1_reg_12807 <= end_13_2_reg_4881;
end else if (ap_sig_bdd_2975) begin
all_end_1_reg_12807 <= end_12_2_reg_4896;
end else if (ap_sig_bdd_2973) begin
all_end_1_reg_12807 <= end_11_2_reg_4911;
end else if (ap_sig_bdd_2971) begin
all_end_1_reg_12807 <= end_10_2_reg_4926;
end else if (ap_sig_bdd_2969) begin
all_end_1_reg_12807 <= end_9_2_reg_4941;
end else if (ap_sig_bdd_2967) begin
all_end_1_reg_12807 <= end_8_2_reg_4956;
end else if (ap_sig_bdd_2965) begin
all_end_1_reg_12807 <= end_7_2_reg_4971;
end else if (ap_sig_bdd_2963) begin
all_end_1_reg_12807 <= end_6_2_reg_4986;
end else if (ap_sig_bdd_2961) begin
all_end_1_reg_12807 <= end_5_2_reg_5001;
end else if (ap_sig_bdd_2959) begin
all_end_1_reg_12807 <= end_4_2_reg_5016;
end else if (ap_sig_bdd_2957) begin
all_end_1_reg_12807 <= end_3_2_reg_5031;
end else if (ap_sig_bdd_2955) begin
all_end_1_reg_12807 <= end_2_2_reg_5046;
end else if (ap_sig_bdd_2953) begin
all_end_1_reg_12807 <= end_1_2_reg_5061;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_9_fu_13539_p2))) begin
all_end_reg_12647 <= ap_const_lv1_1;
end else if ((((ap_ST_st47_fsm_46 == ap_CS_fsm) & ~(tmp_38_reg_14781 == ap_const_lv4_E) & ~(tmp_38_reg_14781 == ap_const_lv4_D) & ~(tmp_38_reg_14781 == ap_const_lv4_C) & ~(tmp_38_reg_14781 == ap_const_lv4_B) & ~(tmp_38_reg_14781 == ap_const_lv4_A) & ~(tmp_38_reg_14781 == ap_const_lv4_9) & ~(tmp_38_reg_14781 == ap_const_lv4_8) & ~(tmp_38_reg_14781 == ap_const_lv4_7) & ~(tmp_38_reg_14781 == ap_const_lv4_6) & ~(tmp_38_reg_14781 == ap_const_lv4_5) & ~(tmp_38_reg_14781 == ap_const_lv4_4) & ~(tmp_38_reg_14781 == ap_const_lv4_3) & ~(tmp_38_reg_14781 == ap_const_lv4_2) & ~(tmp_38_reg_14781 == ap_const_lv4_1) & ~(tmp_38_reg_14781 == ap_const_lv4_0) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_E) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_D) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_C) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_B) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_A) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_9) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_8) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_7) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_6) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_5) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_4) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_3) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_2) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_1) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_0) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & ~(ap_const_lv1_0 == any_end_reg_12691)))) begin
all_end_reg_12647 <= all_end_1_reg_12807;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & ~(ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= ap_const_lv1_1;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_9_fu_13539_p2))) begin
any_end_reg_12691 <= ap_const_lv1_0;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_0) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_0_2_reg_5076;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & ~(tmp_38_reg_14781 == ap_const_lv4_E) & ~(tmp_38_reg_14781 == ap_const_lv4_D) & ~(tmp_38_reg_14781 == ap_const_lv4_C) & ~(tmp_38_reg_14781 == ap_const_lv4_B) & ~(tmp_38_reg_14781 == ap_const_lv4_A) & ~(tmp_38_reg_14781 == ap_const_lv4_9) & ~(tmp_38_reg_14781 == ap_const_lv4_8) & ~(tmp_38_reg_14781 == ap_const_lv4_7) & ~(tmp_38_reg_14781 == ap_const_lv4_6) & ~(tmp_38_reg_14781 == ap_const_lv4_5) & ~(tmp_38_reg_14781 == ap_const_lv4_4) & ~(tmp_38_reg_14781 == ap_const_lv4_3) & ~(tmp_38_reg_14781 == ap_const_lv4_2) & ~(tmp_38_reg_14781 == ap_const_lv4_1) & ~(tmp_38_reg_14781 == ap_const_lv4_0) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_15_2_reg_4851;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_E) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_14_2_reg_4866;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_D) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_13_2_reg_4881;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_C) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_12_2_reg_4896;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_B) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_11_2_reg_4911;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_A) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_10_2_reg_4926;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_9) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_9_2_reg_4941;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_8) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_8_2_reg_4956;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_7) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_7_2_reg_4971;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_6) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_6_2_reg_4986;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_5) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_5_2_reg_5001;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_4) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_4_2_reg_5016;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_3) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_3_2_reg_5031;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_2) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_2_2_reg_5046;
end else if (((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_1) & (ap_const_lv1_0 == any_end_reg_12691))) begin
any_end_reg_12691 <= end_1_2_reg_5061;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_0_1_reg_1726 <= any_state_0_2_reg_3628;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_0_1_reg_1726 <= any_state_reg_1188;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_0_2_reg_3628 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_0_2_reg_3628 <= any_state_0_1_reg_1726;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_0_3_reg_4248 <= any_state_0_4_reg_5316;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_0_3_reg_4248 <= any_state_0_1_reg_1726;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_0_4_reg_5316 <= any_state_0_6_reg_10525;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_0_4_reg_5316 <= any_state_0_3_reg_4248;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0))) begin
any_state_0_5_reg_8582 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)))) begin
any_state_0_5_reg_8582 <= any_state_0_4_reg_5316;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_0_6_reg_10525 <= any_state_0_4_reg_5316;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_0_6_reg_10525 <= any_state_0_5_reg_8582;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_10_1_reg_1616 <= any_state_10_2_reg_3068;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_10_1_reg_1616 <= any_state_10_reg_1068;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_10_2_reg_3068 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_10_2_reg_3068 <= any_state_10_1_reg_1616;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_10_3_reg_4138 <= any_state_10_4_reg_5166;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_10_3_reg_4138 <= any_state_10_1_reg_1616;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_10_4_reg_5166 <= any_state_10_6_reg_9935;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_10_4_reg_5166 <= any_state_10_3_reg_4138;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A))) begin
any_state_10_5_reg_8032 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_10_5_reg_8032 <= any_state_10_4_reg_5166;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_10_6_reg_9935 <= any_state_10_4_reg_5166;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_10_6_reg_9935 <= any_state_10_5_reg_8032;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_11_1_reg_1605 <= any_state_11_2_reg_3012;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_11_1_reg_1605 <= any_state_11_reg_1056;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_11_2_reg_3012 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_11_2_reg_3012 <= any_state_11_1_reg_1605;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_11_3_reg_4127 <= any_state_11_4_reg_5151;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_11_3_reg_4127 <= any_state_11_1_reg_1605;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_11_4_reg_5151 <= any_state_11_6_reg_9876;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_11_4_reg_5151 <= any_state_11_3_reg_4127;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B))) begin
any_state_11_5_reg_7977 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_11_5_reg_7977 <= any_state_11_4_reg_5151;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_11_6_reg_9876 <= any_state_11_4_reg_5151;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_11_6_reg_9876 <= any_state_11_5_reg_7977;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_12_1_reg_1594 <= any_state_12_2_reg_2956;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_12_1_reg_1594 <= any_state_12_reg_1044;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_12_2_reg_2956 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_12_2_reg_2956 <= any_state_12_1_reg_1594;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_12_3_reg_4116 <= any_state_12_4_reg_5136;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_12_3_reg_4116 <= any_state_12_1_reg_1594;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_12_4_reg_5136 <= any_state_12_6_reg_9817;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_12_4_reg_5136 <= any_state_12_3_reg_4116;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C))) begin
any_state_12_5_reg_7922 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_12_5_reg_7922 <= any_state_12_4_reg_5136;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_12_6_reg_9817 <= any_state_12_4_reg_5136;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_12_6_reg_9817 <= any_state_12_5_reg_7922;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_13_1_reg_1583 <= any_state_13_2_reg_2900;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_13_1_reg_1583 <= any_state_13_reg_1032;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_13_2_reg_2900 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_13_2_reg_2900 <= any_state_13_1_reg_1583;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_13_3_reg_4105 <= any_state_13_4_reg_5121;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_13_3_reg_4105 <= any_state_13_1_reg_1583;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_13_4_reg_5121 <= any_state_13_6_reg_9758;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_13_4_reg_5121 <= any_state_13_3_reg_4105;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D))) begin
any_state_13_5_reg_7867 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_13_5_reg_7867 <= any_state_13_4_reg_5121;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_13_6_reg_9758 <= any_state_13_4_reg_5121;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_13_6_reg_9758 <= any_state_13_5_reg_7867;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_14_1_reg_1572 <= any_state_14_2_reg_2844;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_14_1_reg_1572 <= any_state_14_reg_1020;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_14_2_reg_2844 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_14_2_reg_2844 <= any_state_14_1_reg_1572;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_14_3_reg_4094 <= any_state_14_4_reg_5106;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_14_3_reg_4094 <= any_state_14_1_reg_1572;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_14_4_reg_5106 <= any_state_14_6_reg_9699;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_14_4_reg_5106 <= any_state_14_3_reg_4094;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_E))) begin
any_state_14_5_reg_7812 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_14_5_reg_7812 <= any_state_14_4_reg_5106;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_14_6_reg_9699 <= any_state_14_4_reg_5106;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_14_6_reg_9699 <= any_state_14_5_reg_7812;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_15_1_reg_1561 <= any_state_15_2_reg_2788;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_15_1_reg_1561 <= any_state_s_reg_1008;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_15_2_reg_2788 <= any_state_15_1_reg_1561;
end else if ((ap_ST_st10_fsm_9 == ap_CS_fsm)) begin
any_state_15_2_reg_2788 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_15_3_reg_4083 <= any_state_15_4_reg_5091;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_15_3_reg_4083 <= any_state_15_1_reg_1561;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_15_4_reg_5091 <= any_state_15_6_reg_9640;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_15_4_reg_5091 <= any_state_15_3_reg_4083;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_E)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_15_5_reg_7757 <= any_state_15_4_reg_5091;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32))) begin
any_state_15_5_reg_7757 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_15_6_reg_9640 <= any_state_15_4_reg_5091;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_15_6_reg_9640 <= any_state_15_5_reg_7757;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_1_1_reg_1715 <= any_state_1_2_reg_3572;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_1_1_reg_1715 <= any_state_1_reg_1176;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_1_2_reg_3572 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_1_2_reg_3572 <= any_state_1_1_reg_1715;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_1_3_reg_4237 <= any_state_1_4_reg_5301;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_1_3_reg_4237 <= any_state_1_1_reg_1715;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_1_4_reg_5301 <= any_state_1_6_reg_10466;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_1_4_reg_5301 <= any_state_1_3_reg_4237;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1))) begin
any_state_1_5_reg_8527 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_1_5_reg_8527 <= any_state_1_4_reg_5301;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_1_6_reg_10466 <= any_state_1_4_reg_5301;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_1_6_reg_10466 <= any_state_1_5_reg_8527;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_2_1_reg_1704 <= any_state_2_2_reg_3516;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_2_1_reg_1704 <= any_state_2_reg_1164;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_2_2_reg_3516 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_2_2_reg_3516 <= any_state_2_1_reg_1704;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_2_3_reg_4226 <= any_state_2_4_reg_5286;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_2_3_reg_4226 <= any_state_2_1_reg_1704;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_2_4_reg_5286 <= any_state_2_6_reg_10407;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_2_4_reg_5286 <= any_state_2_3_reg_4226;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2))) begin
any_state_2_5_reg_8472 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_2_5_reg_8472 <= any_state_2_4_reg_5286;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_2_6_reg_10407 <= any_state_2_4_reg_5286;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_2_6_reg_10407 <= any_state_2_5_reg_8472;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_3_1_reg_1693 <= any_state_3_2_reg_3460;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_3_1_reg_1693 <= any_state_3_reg_1152;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_3_2_reg_3460 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_3_2_reg_3460 <= any_state_3_1_reg_1693;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_3_3_reg_4215 <= any_state_3_4_reg_5271;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_3_3_reg_4215 <= any_state_3_1_reg_1693;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_3_4_reg_5271 <= any_state_3_6_reg_10348;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_3_4_reg_5271 <= any_state_3_3_reg_4215;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3))) begin
any_state_3_5_reg_8417 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_3_5_reg_8417 <= any_state_3_4_reg_5271;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_3_6_reg_10348 <= any_state_3_4_reg_5271;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_3_6_reg_10348 <= any_state_3_5_reg_8417;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_4_1_reg_1682 <= any_state_4_2_reg_3404;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_4_1_reg_1682 <= any_state_4_reg_1140;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_4_2_reg_3404 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_4_2_reg_3404 <= any_state_4_1_reg_1682;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_4_3_reg_4204 <= any_state_4_4_reg_5256;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_4_3_reg_4204 <= any_state_4_1_reg_1682;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_4_4_reg_5256 <= any_state_4_6_reg_10289;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_4_4_reg_5256 <= any_state_4_3_reg_4204;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4))) begin
any_state_4_5_reg_8362 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_4_5_reg_8362 <= any_state_4_4_reg_5256;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_4_6_reg_10289 <= any_state_4_4_reg_5256;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_4_6_reg_10289 <= any_state_4_5_reg_8362;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_5_1_reg_1671 <= any_state_5_2_reg_3348;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_5_1_reg_1671 <= any_state_5_reg_1128;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_5_2_reg_3348 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_5_2_reg_3348 <= any_state_5_1_reg_1671;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_5_3_reg_4193 <= any_state_5_4_reg_5241;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_5_3_reg_4193 <= any_state_5_1_reg_1671;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_5_4_reg_5241 <= any_state_5_6_reg_10230;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_5_4_reg_5241 <= any_state_5_3_reg_4193;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5))) begin
any_state_5_5_reg_8307 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_5_5_reg_8307 <= any_state_5_4_reg_5241;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_5_6_reg_10230 <= any_state_5_4_reg_5241;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_5_6_reg_10230 <= any_state_5_5_reg_8307;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_6_1_reg_1660 <= any_state_6_2_reg_3292;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_6_1_reg_1660 <= any_state_6_reg_1116;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_6_2_reg_3292 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_6_2_reg_3292 <= any_state_6_1_reg_1660;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_6_3_reg_4182 <= any_state_6_4_reg_5226;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_6_3_reg_4182 <= any_state_6_1_reg_1660;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_6_4_reg_5226 <= any_state_6_6_reg_10171;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_6_4_reg_5226 <= any_state_6_3_reg_4182;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6))) begin
any_state_6_5_reg_8252 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_6_5_reg_8252 <= any_state_6_4_reg_5226;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_6_6_reg_10171 <= any_state_6_4_reg_5226;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_6_6_reg_10171 <= any_state_6_5_reg_8252;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_7_1_reg_1649 <= any_state_7_2_reg_3236;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_7_1_reg_1649 <= any_state_7_reg_1104;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_7_2_reg_3236 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_7_2_reg_3236 <= any_state_7_1_reg_1649;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_7_3_reg_4171 <= any_state_7_4_reg_5211;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_7_3_reg_4171 <= any_state_7_1_reg_1649;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_7_4_reg_5211 <= any_state_7_6_reg_10112;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_7_4_reg_5211 <= any_state_7_3_reg_4171;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7))) begin
any_state_7_5_reg_8197 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_7_5_reg_8197 <= any_state_7_4_reg_5211;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_7_6_reg_10112 <= any_state_7_4_reg_5211;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_7_6_reg_10112 <= any_state_7_5_reg_8197;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_8_1_reg_1638 <= any_state_8_2_reg_3180;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_8_1_reg_1638 <= any_state_8_reg_1092;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_8_2_reg_3180 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_8_2_reg_3180 <= any_state_8_1_reg_1638;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_8_3_reg_4160 <= any_state_8_4_reg_5196;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_8_3_reg_4160 <= any_state_8_1_reg_1638;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_8_4_reg_5196 <= any_state_8_6_reg_10053;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_8_4_reg_5196 <= any_state_8_3_reg_4160;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8))) begin
any_state_8_5_reg_8142 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_8_5_reg_8142 <= any_state_8_4_reg_5196;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_8_6_reg_10053 <= any_state_8_4_reg_5196;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_8_6_reg_10053 <= any_state_8_5_reg_8142;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
any_state_9_1_reg_1627 <= any_state_9_2_reg_3124;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
any_state_9_1_reg_1627 <= any_state_9_reg_1080;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st10_fsm_9 == ap_CS_fsm))) begin
any_state_9_2_reg_3124 <= ap_const_lv1_0;
end else if (((ap_ST_st10_fsm_9 == ap_CS_fsm) | ((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st10_fsm_9 == ap_CS_fsm)) | ((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st10_fsm_9 == ap_CS_fsm)))) begin
any_state_9_2_reg_3124 <= any_state_9_1_reg_1627;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_9_3_reg_4149 <= any_state_9_4_reg_5181;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
any_state_9_3_reg_4149 <= any_state_9_1_reg_1627;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
any_state_9_4_reg_5181 <= any_state_9_6_reg_9994;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
any_state_9_4_reg_5181 <= any_state_9_3_reg_4149;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9))) begin
any_state_9_5_reg_8087 <= ap_const_lv1_1;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
any_state_9_5_reg_8087 <= any_state_9_4_reg_5181;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
any_state_9_6_reg_9994 <= any_state_9_4_reg_5181;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
any_state_9_6_reg_9994 <= any_state_9_5_reg_8087;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_1962) begin
if ((tmp_37_fu_13557_p1 == ap_const_lv4_0)) begin
any_state_load_1_phi_reg_7703 <= any_state_0_4_reg_5316;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_E)) begin
any_state_load_1_phi_reg_7703 <= any_state_14_4_reg_5106;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_D)) begin
any_state_load_1_phi_reg_7703 <= any_state_13_4_reg_5121;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_C)) begin
any_state_load_1_phi_reg_7703 <= any_state_12_4_reg_5136;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_B)) begin
any_state_load_1_phi_reg_7703 <= any_state_11_4_reg_5151;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_A)) begin
any_state_load_1_phi_reg_7703 <= any_state_10_4_reg_5166;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_9)) begin
any_state_load_1_phi_reg_7703 <= any_state_9_4_reg_5181;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_8)) begin
any_state_load_1_phi_reg_7703 <= any_state_8_4_reg_5196;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_7)) begin
any_state_load_1_phi_reg_7703 <= any_state_7_4_reg_5211;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_6)) begin
any_state_load_1_phi_reg_7703 <= any_state_6_4_reg_5226;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_5)) begin
any_state_load_1_phi_reg_7703 <= any_state_5_4_reg_5241;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_4)) begin
any_state_load_1_phi_reg_7703 <= any_state_4_4_reg_5256;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_3)) begin
any_state_load_1_phi_reg_7703 <= any_state_3_4_reg_5271;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_2)) begin
any_state_load_1_phi_reg_7703 <= any_state_2_4_reg_5286;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_1)) begin
any_state_load_1_phi_reg_7703 <= any_state_1_4_reg_5301;
end else if ((ap_true == ap_true)) begin
any_state_load_1_phi_reg_7703 <= any_state_15_4_reg_5091;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
if (ap_sig_bdd_1202) begin
bus_assign_reg_3684 <= {{current_buckets_q0[ap_const_lv32_3F : ap_const_lv32_20]}};
end else if ((ap_const_lv1_0 == tmp_11_fu_13276_p2)) begin
bus_assign_reg_3684 <= tmp_39_fu_13272_p1;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_0_1_reg_4072 <= end_0_2_reg_5076;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_0_1_reg_4072 <= end_0_s_reg_996;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_0_2_reg_5076 <= end_0_3_reg_6719;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_0_2_reg_5076 <= end_0_1_reg_4072;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0))) begin
end_0_3_reg_6719 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)))) begin
end_0_3_reg_6719 <= end_0_2_reg_5076;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_327) begin
if ((tmp_37_fu_13557_p1 == ap_const_lv4_0)) begin
end_0_reg_5841 <= j_15_end_load_reg_14439;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_E)) begin
end_0_reg_5841 <= j_15_end_14_load_reg_14509;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_D)) begin
end_0_reg_5841 <= j_15_end_13_load_reg_14504;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_C)) begin
end_0_reg_5841 <= j_15_end_12_load_reg_14499;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_B)) begin
end_0_reg_5841 <= j_15_end_11_load_reg_14494;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_A)) begin
end_0_reg_5841 <= j_15_end_10_load_reg_14489;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_9)) begin
end_0_reg_5841 <= j_15_end_9_load_reg_14484;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_8)) begin
end_0_reg_5841 <= j_15_end_8_load_reg_14479;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_7)) begin
end_0_reg_5841 <= j_15_end_7_load_reg_14474;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_6)) begin
end_0_reg_5841 <= j_15_end_6_load_reg_14469;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_5)) begin
end_0_reg_5841 <= j_15_end_5_load_reg_14464;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_4)) begin
end_0_reg_5841 <= j_15_end_4_load_reg_14459;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_3)) begin
end_0_reg_5841 <= j_15_end_3_load_reg_14454;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_2)) begin
end_0_reg_5841 <= j_15_end_2_load_reg_14449;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_1)) begin
end_0_reg_5841 <= j_15_end_1_load_reg_14444;
end else if ((ap_true == ap_true)) begin
end_0_reg_5841 <= j_15_end_15_load_reg_14514;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_10_1_reg_3962 <= end_10_2_reg_4926;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_10_1_reg_3962 <= end_10_s_reg_876;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_10_2_reg_4926 <= end_10_3_reg_6159;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_10_2_reg_4926 <= end_10_1_reg_3962;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A))) begin
end_10_3_reg_6159 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_10_3_reg_6159 <= end_10_2_reg_4926;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_11_1_reg_3951 <= end_11_2_reg_4911;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_11_1_reg_3951 <= end_11_s_reg_864;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_11_2_reg_4911 <= end_11_3_reg_6103;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_11_2_reg_4911 <= end_11_1_reg_3951;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B))) begin
end_11_3_reg_6103 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_11_3_reg_6103 <= end_11_2_reg_4911;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_12_1_reg_3940 <= end_12_2_reg_4896;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_12_1_reg_3940 <= end_12_s_reg_852;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_12_2_reg_4896 <= end_12_3_reg_6047;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_12_2_reg_4896 <= end_12_1_reg_3940;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C))) begin
end_12_3_reg_6047 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_12_3_reg_6047 <= end_12_2_reg_4896;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_13_1_reg_3929 <= end_13_2_reg_4881;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_13_1_reg_3929 <= end_13_s_reg_840;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_13_2_reg_4881 <= end_13_3_reg_5991;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_13_2_reg_4881 <= end_13_1_reg_3929;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D))) begin
end_13_3_reg_5991 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_13_3_reg_5991 <= end_13_2_reg_4881;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_14_1_reg_3918 <= end_14_2_reg_4866;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_14_1_reg_3918 <= end_14_s_reg_828;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_14_2_reg_4866 <= end_14_3_reg_5935;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_14_2_reg_4866 <= end_14_1_reg_3918;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_E))) begin
end_14_3_reg_5935 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_14_3_reg_5935 <= end_14_2_reg_4866;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_15_1_reg_3907 <= end_15_2_reg_4851;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_15_1_reg_3907 <= end_15_s_reg_816;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_15_2_reg_4851 <= end_15_3_reg_5879;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_15_2_reg_4851 <= end_15_1_reg_3907;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_E)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_15_3_reg_5879 <= end_15_2_reg_4851;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2))) begin
end_15_3_reg_5879 <= end_0_phi_fu_5844_p32;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_1_1_reg_4061 <= end_1_2_reg_5061;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_1_1_reg_4061 <= end_1_s_reg_984;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_1_2_reg_5061 <= end_1_3_reg_6663;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_1_2_reg_5061 <= end_1_1_reg_4061;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1))) begin
end_1_3_reg_6663 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_1_3_reg_6663 <= end_1_2_reg_5061;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_2_1_reg_4050 <= end_2_2_reg_5046;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_2_1_reg_4050 <= end_2_s_reg_972;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_2_2_reg_5046 <= end_2_3_reg_6607;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_2_2_reg_5046 <= end_2_1_reg_4050;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2))) begin
end_2_3_reg_6607 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_2_3_reg_6607 <= end_2_2_reg_5046;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_3_1_reg_4039 <= end_3_2_reg_5031;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_3_1_reg_4039 <= end_3_s_reg_960;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_3_2_reg_5031 <= end_3_3_reg_6551;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_3_2_reg_5031 <= end_3_1_reg_4039;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3))) begin
end_3_3_reg_6551 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_3_3_reg_6551 <= end_3_2_reg_5031;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_4_1_reg_4028 <= end_4_2_reg_5016;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_4_1_reg_4028 <= end_4_s_reg_948;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_4_2_reg_5016 <= end_4_3_reg_6495;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_4_2_reg_5016 <= end_4_1_reg_4028;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4))) begin
end_4_3_reg_6495 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_4_3_reg_6495 <= end_4_2_reg_5016;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_5_1_reg_4017 <= end_5_2_reg_5001;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_5_1_reg_4017 <= end_5_s_reg_936;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_5_2_reg_5001 <= end_5_3_reg_6439;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_5_2_reg_5001 <= end_5_1_reg_4017;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5))) begin
end_5_3_reg_6439 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_5_3_reg_6439 <= end_5_2_reg_5001;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_6_1_reg_4006 <= end_6_2_reg_4986;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_6_1_reg_4006 <= end_6_s_reg_924;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_6_2_reg_4986 <= end_6_3_reg_6383;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_6_2_reg_4986 <= end_6_1_reg_4006;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6))) begin
end_6_3_reg_6383 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_6_3_reg_6383 <= end_6_2_reg_4986;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_7_1_reg_3995 <= end_7_2_reg_4971;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_7_1_reg_3995 <= end_7_s_reg_912;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_7_2_reg_4971 <= end_7_3_reg_6327;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_7_2_reg_4971 <= end_7_1_reg_3995;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7))) begin
end_7_3_reg_6327 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_7_3_reg_6327 <= end_7_2_reg_4971;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_8_1_reg_3984 <= end_8_2_reg_4956;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_8_1_reg_3984 <= end_8_s_reg_900;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_8_2_reg_4956 <= end_8_3_reg_6271;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_8_2_reg_4956 <= end_8_1_reg_3984;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8))) begin
end_8_3_reg_6271 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_8_3_reg_6271 <= end_8_2_reg_4956;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_9_1_reg_3973 <= end_9_2_reg_4941;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_9_1_reg_3973 <= end_9_s_reg_888;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_9_2_reg_4941 <= end_9_3_reg_6215;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_9_2_reg_4941 <= end_9_1_reg_3973;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_9))) begin
end_9_3_reg_6215 <= end_0_phi_fu_5844_p32;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_9_3_reg_6215 <= end_9_2_reg_4941;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_395) begin
if ((tmp_38_fu_13733_p1 == ap_const_lv4_0)) begin
end_load_phi_reg_12753 <= end_0_2_reg_5076;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_E)) begin
end_load_phi_reg_12753 <= end_14_2_reg_4866;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_D)) begin
end_load_phi_reg_12753 <= end_13_2_reg_4881;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_C)) begin
end_load_phi_reg_12753 <= end_12_2_reg_4896;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_B)) begin
end_load_phi_reg_12753 <= end_11_2_reg_4911;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_A)) begin
end_load_phi_reg_12753 <= end_10_2_reg_4926;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_9)) begin
end_load_phi_reg_12753 <= end_9_2_reg_4941;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_8)) begin
end_load_phi_reg_12753 <= end_8_2_reg_4956;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_7)) begin
end_load_phi_reg_12753 <= end_7_2_reg_4971;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_6)) begin
end_load_phi_reg_12753 <= end_6_2_reg_4986;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_5)) begin
end_load_phi_reg_12753 <= end_5_2_reg_5001;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_4)) begin
end_load_phi_reg_12753 <= end_4_2_reg_5016;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_3)) begin
end_load_phi_reg_12753 <= end_3_2_reg_5031;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_2)) begin
end_load_phi_reg_12753 <= end_2_2_reg_5046;
end else if ((tmp_38_fu_13733_p1 == ap_const_lv4_1)) begin
end_load_phi_reg_12753 <= end_1_2_reg_5061;
end else if ((ap_true == ap_true)) begin
end_load_phi_reg_12753 <= end_15_2_reg_4851;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_0_2_reg_1542 <= end_string_fu_152;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_0_2_reg_1542 <= end_string_0_4_reg_5812;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_0_3_reg_4600 <= end_string_0_4_reg_5812;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_0_3_reg_4600 <= end_string_0_2_reg_1542;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_0_4_reg_5812 <= end_string_0_6_reg_11469;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_0_4_reg_5812 <= end_string_0_3_reg_4600;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0))) begin
end_string_0_5_reg_7649 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)))) begin
end_string_0_5_reg_7649 <= end_string_0_4_reg_5812;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_0_6_reg_11469 <= end_string_0_5_reg_7649;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_0_6_reg_11469 <= end_string_0_4_reg_5812;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_1793) begin
if (~(ap_const_lv1_0 == tmp_7_reg_14542)) begin
end_string_0_reg_6828 <= ap_const_lv1_1;
end else if ((ap_const_lv1_0 == tmp_7_reg_14542)) begin
end_string_0_reg_6828 <= tmp_12_fu_13561_p2;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_10_2_reg_1442 <= end_string_10_fu_192;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_10_2_reg_1442 <= end_string_10_4_reg_5662;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_10_3_reg_4490 <= end_string_10_4_reg_5662;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_10_3_reg_4490 <= end_string_10_2_reg_1442;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_10_4_reg_5662 <= end_string_10_6_reg_10879;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_10_4_reg_5662 <= end_string_10_3_reg_4490;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A))) begin
end_string_10_5_reg_7109 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_10_5_reg_7109 <= end_string_10_4_reg_5662;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_10_6_reg_10879 <= end_string_10_5_reg_7109;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_10_6_reg_10879 <= end_string_10_4_reg_5662;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_11_2_reg_1432 <= end_string_11_fu_196;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_11_2_reg_1432 <= end_string_11_4_reg_5647;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_11_3_reg_4479 <= end_string_11_4_reg_5647;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_11_3_reg_4479 <= end_string_11_2_reg_1432;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_11_4_reg_5647 <= end_string_11_6_reg_10820;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_11_4_reg_5647 <= end_string_11_3_reg_4479;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B))) begin
end_string_11_5_reg_7055 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_11_5_reg_7055 <= end_string_11_4_reg_5647;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_11_6_reg_10820 <= end_string_11_5_reg_7055;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_11_6_reg_10820 <= end_string_11_4_reg_5647;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_12_2_reg_1422 <= end_string_12_fu_200;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_12_2_reg_1422 <= end_string_12_4_reg_5632;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_12_3_reg_4468 <= end_string_12_4_reg_5632;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_12_3_reg_4468 <= end_string_12_2_reg_1422;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_12_4_reg_5632 <= end_string_12_6_reg_10761;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_12_4_reg_5632 <= end_string_12_3_reg_4468;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C))) begin
end_string_12_5_reg_7001 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_12_5_reg_7001 <= end_string_12_4_reg_5632;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_12_6_reg_10761 <= end_string_12_5_reg_7001;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_12_6_reg_10761 <= end_string_12_4_reg_5632;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_13_2_reg_1412 <= end_string_13_fu_204;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_13_2_reg_1412 <= end_string_13_4_reg_5617;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_13_3_reg_4457 <= end_string_13_4_reg_5617;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_13_3_reg_4457 <= end_string_13_2_reg_1412;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_13_4_reg_5617 <= end_string_13_6_reg_10702;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_13_4_reg_5617 <= end_string_13_3_reg_4457;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D))) begin
end_string_13_5_reg_6947 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_13_5_reg_6947 <= end_string_13_4_reg_5617;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_13_6_reg_10702 <= end_string_13_5_reg_6947;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_13_6_reg_10702 <= end_string_13_4_reg_5617;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_14_2_reg_1402 <= end_string_14_fu_208;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_14_2_reg_1402 <= end_string_14_4_reg_5602;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_14_3_reg_4446 <= end_string_14_4_reg_5602;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_14_3_reg_4446 <= end_string_14_2_reg_1402;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_14_4_reg_5602 <= end_string_14_6_reg_10643;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_14_4_reg_5602 <= end_string_14_3_reg_4446;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_E))) begin
end_string_14_5_reg_6893 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_14_5_reg_6893 <= end_string_14_4_reg_5602;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_14_6_reg_10643 <= end_string_14_5_reg_6893;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_14_6_reg_10643 <= end_string_14_4_reg_5602;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_15_2_reg_1392 <= end_string_s_fu_212;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_15_2_reg_1392 <= end_string_15_4_reg_5587;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_15_3_reg_4435 <= end_string_15_4_reg_5587;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_15_3_reg_4435 <= end_string_15_2_reg_1392;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_15_4_reg_5587 <= end_string_15_6_reg_10584;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_15_4_reg_5587 <= end_string_15_3_reg_4435;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_E)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_15_5_reg_6839 <= end_string_15_4_reg_5587;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32))) begin
end_string_15_5_reg_6839 <= end_string_0_phi_fu_6831_p4;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_15_6_reg_10584 <= end_string_15_5_reg_6839;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_15_6_reg_10584 <= end_string_15_4_reg_5587;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_1_2_reg_1532 <= end_string_1_fu_156;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_1_2_reg_1532 <= end_string_1_4_reg_5797;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_1_3_reg_4589 <= end_string_1_4_reg_5797;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_1_3_reg_4589 <= end_string_1_2_reg_1532;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_1_4_reg_5797 <= end_string_1_6_reg_11410;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_1_4_reg_5797 <= end_string_1_3_reg_4589;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1))) begin
end_string_1_5_reg_7595 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_1_5_reg_7595 <= end_string_1_4_reg_5797;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_1_6_reg_11410 <= end_string_1_5_reg_7595;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_1_6_reg_11410 <= end_string_1_4_reg_5797;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_2_2_reg_1522 <= end_string_2_fu_160;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_2_2_reg_1522 <= end_string_2_4_reg_5782;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_2_3_reg_4578 <= end_string_2_4_reg_5782;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_2_3_reg_4578 <= end_string_2_2_reg_1522;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_2_4_reg_5782 <= end_string_2_6_reg_11351;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_2_4_reg_5782 <= end_string_2_3_reg_4578;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2))) begin
end_string_2_5_reg_7541 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_2_5_reg_7541 <= end_string_2_4_reg_5782;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_2_6_reg_11351 <= end_string_2_5_reg_7541;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_2_6_reg_11351 <= end_string_2_4_reg_5782;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_3_2_reg_1512 <= end_string_3_fu_164;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_3_2_reg_1512 <= end_string_3_4_reg_5767;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_3_3_reg_4567 <= end_string_3_4_reg_5767;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_3_3_reg_4567 <= end_string_3_2_reg_1512;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_3_4_reg_5767 <= end_string_3_6_reg_11292;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_3_4_reg_5767 <= end_string_3_3_reg_4567;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3))) begin
end_string_3_5_reg_7487 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_3_5_reg_7487 <= end_string_3_4_reg_5767;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_3_6_reg_11292 <= end_string_3_5_reg_7487;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_3_6_reg_11292 <= end_string_3_4_reg_5767;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_4_2_reg_1502 <= end_string_4_fu_168;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_4_2_reg_1502 <= end_string_4_4_reg_5752;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_4_3_reg_4556 <= end_string_4_4_reg_5752;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_4_3_reg_4556 <= end_string_4_2_reg_1502;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_4_4_reg_5752 <= end_string_4_6_reg_11233;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_4_4_reg_5752 <= end_string_4_3_reg_4556;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4))) begin
end_string_4_5_reg_7433 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_4_5_reg_7433 <= end_string_4_4_reg_5752;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_4_6_reg_11233 <= end_string_4_5_reg_7433;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_4_6_reg_11233 <= end_string_4_4_reg_5752;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_5_2_reg_1492 <= end_string_5_fu_172;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_5_2_reg_1492 <= end_string_5_4_reg_5737;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_5_3_reg_4545 <= end_string_5_4_reg_5737;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_5_3_reg_4545 <= end_string_5_2_reg_1492;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_5_4_reg_5737 <= end_string_5_6_reg_11174;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_5_4_reg_5737 <= end_string_5_3_reg_4545;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5))) begin
end_string_5_5_reg_7379 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_5_5_reg_7379 <= end_string_5_4_reg_5737;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_5_6_reg_11174 <= end_string_5_5_reg_7379;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_5_6_reg_11174 <= end_string_5_4_reg_5737;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_6_2_reg_1482 <= end_string_6_fu_176;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_6_2_reg_1482 <= end_string_6_4_reg_5722;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_6_3_reg_4534 <= end_string_6_4_reg_5722;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_6_3_reg_4534 <= end_string_6_2_reg_1482;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_6_4_reg_5722 <= end_string_6_6_reg_11115;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_6_4_reg_5722 <= end_string_6_3_reg_4534;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6))) begin
end_string_6_5_reg_7325 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_6_5_reg_7325 <= end_string_6_4_reg_5722;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_6_6_reg_11115 <= end_string_6_5_reg_7325;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_6_6_reg_11115 <= end_string_6_4_reg_5722;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_7_2_reg_1472 <= end_string_7_fu_180;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_7_2_reg_1472 <= end_string_7_4_reg_5707;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_7_3_reg_4523 <= end_string_7_4_reg_5707;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_7_3_reg_4523 <= end_string_7_2_reg_1472;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_7_4_reg_5707 <= end_string_7_6_reg_11056;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_7_4_reg_5707 <= end_string_7_3_reg_4523;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7))) begin
end_string_7_5_reg_7271 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_7_5_reg_7271 <= end_string_7_4_reg_5707;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_7_6_reg_11056 <= end_string_7_5_reg_7271;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_7_6_reg_11056 <= end_string_7_4_reg_5707;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_8_2_reg_1462 <= end_string_8_fu_184;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_8_2_reg_1462 <= end_string_8_4_reg_5692;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_8_3_reg_4512 <= end_string_8_4_reg_5692;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_8_3_reg_4512 <= end_string_8_2_reg_1462;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_8_4_reg_5692 <= end_string_8_6_reg_10997;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_8_4_reg_5692 <= end_string_8_3_reg_4512;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8))) begin
end_string_8_5_reg_7217 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_8_5_reg_7217 <= end_string_8_4_reg_5692;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_8_6_reg_10997 <= end_string_8_5_reg_7217;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_8_6_reg_10997 <= end_string_8_4_reg_5692;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
end_string_9_2_reg_1452 <= end_string_9_fu_188;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_9_2_reg_1452 <= end_string_9_4_reg_5677;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
end_string_9_3_reg_4501 <= end_string_9_4_reg_5677;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
end_string_9_3_reg_4501 <= end_string_9_2_reg_1452;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
end_string_9_4_reg_5677 <= end_string_9_6_reg_10938;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
end_string_9_4_reg_5677 <= end_string_9_3_reg_4501;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_9))) begin
end_string_9_5_reg_7163 <= end_string_0_phi_fu_6831_p4;
end else if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_D)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_C)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_B)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_A)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_8)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_7)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_6)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_5)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_4)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_3)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_2)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_1)) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (tmp_37_fu_13557_p1 == ap_const_lv4_0)))) begin
end_string_9_5_reg_7163 <= end_string_9_4_reg_5677;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_9_6_reg_10938 <= end_string_9_5_reg_7163;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
end_string_9_6_reg_10938 <= end_string_9_4_reg_5677;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_12991_p2))) begin
i_reg_1552 <= length_r;
end else if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
i_reg_1552 <= i_1_reg_14270;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_11_fu_13276_p2) & ~(ap_const_lv1_0 == tmp_27_1_fu_13292_p2))) begin
j_0_bucket_index_reg_3706 <= ap_const_lv2_2;
end else if ((ap_ST_st13_fsm_12 == ap_CS_fsm)) begin
j_0_bucket_index_reg_3706 <= r_1_0_i_lcssa3_cast_fu_13298_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_11_fu_13276_p2) & ~(ap_const_lv1_0 == tmp_27_1_fu_13292_p2))) begin
j_0_end_reg_3717 <= ap_const_lv1_1;
end else if ((ap_ST_st13_fsm_12 == ap_CS_fsm)) begin
j_0_end_reg_3717 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st20_fsm_19 == ap_CS_fsm)) begin
if ((tmp_37_reg_14631 == ap_const_lv4_0)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_load_reg_14279;
end else if ((tmp_37_reg_14631 == ap_const_lv4_E)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_14_load_reg_14349;
end else if ((tmp_37_reg_14631 == ap_const_lv4_D)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_13_load_reg_14344;
end else if ((tmp_37_reg_14631 == ap_const_lv4_C)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_12_load_reg_14339;
end else if ((tmp_37_reg_14631 == ap_const_lv4_B)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_11_load_reg_14334;
end else if ((tmp_37_reg_14631 == ap_const_lv4_A)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_10_load_reg_14329;
end else if ((tmp_37_reg_14631 == ap_const_lv4_9)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_9_load_reg_14324;
end else if ((tmp_37_reg_14631 == ap_const_lv4_8)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_8_load_reg_14319;
end else if ((tmp_37_reg_14631 == ap_const_lv4_7)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_7_load_reg_14314;
end else if ((tmp_37_reg_14631 == ap_const_lv4_6)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_6_load_reg_14309;
end else if ((tmp_37_reg_14631 == ap_const_lv4_5)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_5_load_reg_14304;
end else if ((tmp_37_reg_14631 == ap_const_lv4_4)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_4_load_reg_14299;
end else if ((tmp_37_reg_14631 == ap_const_lv4_3)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_3_load_reg_14294;
end else if ((tmp_37_reg_14631 == ap_const_lv4_2)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_2_load_reg_14289;
end else if ((tmp_37_reg_14631 == ap_const_lv4_1)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_1_load_reg_14284;
end else if ((ap_true == ap_true)) begin
j_bit_addr12_phi_reg_8637 <= j_15_bit_15_load_reg_14354;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st21_fsm_20 == ap_CS_fsm)) begin
if ((tmp_37_reg_14631 == ap_const_lv4_0)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_0_load_reg_14359[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_0_load_reg_14359[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_E)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_14_load_reg_14429[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_14_load_reg_14429[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_D)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_13_load_reg_14424[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_13_load_reg_14424[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_C)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_12_load_reg_14419[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_12_load_reg_14419[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_B)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_11_load_reg_14414[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_11_load_reg_14414[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_A)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_10_load_reg_14409[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_10_load_reg_14409[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_9)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_9_load_reg_14404[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_9_load_reg_14404[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_8)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_8_load_reg_14399[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_8_load_reg_14399[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_7)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_7_load_reg_14394[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_7_load_reg_14394[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_6)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_6_load_reg_14389[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_6_load_reg_14389[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_5)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_5_load_reg_14384[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_5_load_reg_14384[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_4)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_4_load_reg_14379[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_4_load_reg_14379[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_3)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_3_load_reg_14374[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_3_load_reg_14374[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_2)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_2_load_reg_14369[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_2_load_reg_14369[1];
end else if ((tmp_37_reg_14631 == ap_const_lv4_1)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_1_load_reg_14364[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_1_load_reg_14364[1];
end else if ((ap_true == ap_true)) begin
j_bucket_index_addr13_phi_reg_8675[0] <= j_bucket_index_15_load_reg_14434[0];
j_bucket_index_addr13_phi_reg_8675[1] <= j_bucket_index_15_load_reg_14434[1];
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
k_1_reg_1913 <= k_5_reg_14522;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
k_1_reg_1913 <= ap_const_lv5_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
k_2_reg_5827 <= k_7_reg_14615;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
k_2_reg_5827 <= ap_const_lv5_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_9_fu_13539_p2))) begin
k_3_reg_12604 <= ap_const_lv5_0;
end else if ((((ap_ST_st47_fsm_46 == ap_CS_fsm) & ~(tmp_38_reg_14781 == ap_const_lv4_E) & ~(tmp_38_reg_14781 == ap_const_lv4_D) & ~(tmp_38_reg_14781 == ap_const_lv4_C) & ~(tmp_38_reg_14781 == ap_const_lv4_B) & ~(tmp_38_reg_14781 == ap_const_lv4_A) & ~(tmp_38_reg_14781 == ap_const_lv4_9) & ~(tmp_38_reg_14781 == ap_const_lv4_8) & ~(tmp_38_reg_14781 == ap_const_lv4_7) & ~(tmp_38_reg_14781 == ap_const_lv4_6) & ~(tmp_38_reg_14781 == ap_const_lv4_5) & ~(tmp_38_reg_14781 == ap_const_lv4_4) & ~(tmp_38_reg_14781 == ap_const_lv4_3) & ~(tmp_38_reg_14781 == ap_const_lv4_2) & ~(tmp_38_reg_14781 == ap_const_lv4_1) & ~(tmp_38_reg_14781 == ap_const_lv4_0) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_E) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_D) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_C) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_B) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_A) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_9) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_8) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_7) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_6) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_5) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_4) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_3) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_2) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_1) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & (tmp_38_reg_14781 == ap_const_lv4_0) & (ap_const_lv1_0 == any_end_reg_12691)) | ((ap_ST_st47_fsm_46 == ap_CS_fsm) & ~(ap_const_lv1_0 == any_end_reg_12691)))) begin
k_3_reg_12604 <= k_6_reg_14754;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st6_fsm_5 == ap_CS_fsm)) begin
k_reg_612 <= k_4_reg_13968;
end else if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
k_reg_612 <= ap_const_lv5_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st32_fsm_31 == ap_CS_fsm)) begin
if (ap_sig_bdd_2617) begin
offset_reg_11634 <= sym_offset_0_4_reg_5571;
end else if (ap_sig_bdd_2613) begin
offset_reg_11634 <= sym_offset_14_4_reg_5347;
end else if (ap_sig_bdd_2609) begin
offset_reg_11634 <= sym_offset_13_4_reg_5363;
end else if (ap_sig_bdd_2605) begin
offset_reg_11634 <= sym_offset_12_4_reg_5379;
end else if (ap_sig_bdd_2601) begin
offset_reg_11634 <= sym_offset_11_4_reg_5395;
end else if (ap_sig_bdd_2597) begin
offset_reg_11634 <= sym_offset_10_4_reg_5411;
end else if (ap_sig_bdd_2593) begin
offset_reg_11634 <= sym_offset_9_4_reg_5427;
end else if (ap_sig_bdd_2589) begin
offset_reg_11634 <= sym_offset_8_4_reg_5443;
end else if (ap_sig_bdd_2585) begin
offset_reg_11634 <= sym_offset_7_4_reg_5459;
end else if (ap_sig_bdd_2581) begin
offset_reg_11634 <= sym_offset_6_4_reg_5475;
end else if (ap_sig_bdd_2577) begin
offset_reg_11634 <= sym_offset_5_4_reg_5491;
end else if (ap_sig_bdd_2573) begin
offset_reg_11634 <= sym_offset_4_4_reg_5507;
end else if (ap_sig_bdd_2569) begin
offset_reg_11634 <= sym_offset_3_4_reg_5523;
end else if (ap_sig_bdd_2565) begin
offset_reg_11634 <= sym_offset_2_4_reg_5539;
end else if (ap_sig_bdd_2561) begin
offset_reg_11634 <= sym_offset_1_4_reg_5555;
end else if (ap_sig_bdd_2557) begin
offset_reg_11634 <= sym_offset_15_4_reg_5331;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
p_0_reg_12882 <= ap_const_lv1_0;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & (ap_const_lv1_0 == tmp1_fu_13626_p2) & ~(ap_const_lv1_0 == brmerge_demorgan_reg_14680))) begin
p_0_reg_12882 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
if (ap_sig_bdd_1202) begin
r_1_0_i_lcssa3_reg_3693 <= ap_const_lv1_1;
end else if ((ap_const_lv1_0 == tmp_11_fu_13276_p2)) begin
r_1_0_i_lcssa3_reg_3693 <= ap_const_lv1_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_0_1_reg_3896 <= state_0_2_reg_4836;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_0_1_reg_3896 <= state_0_s_reg_804;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_0_2_reg_4836 <= state_0_4_reg_9582;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_0_2_reg_4836 <= state_0_1_reg_3896;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0))) begin
state_0_4_reg_9582 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_0_4_reg_9582 <= state_0_2_reg_4836;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_10_1_reg_3786 <= state_10_2_reg_4686;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_10_1_reg_3786 <= state_10_s_reg_684;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_10_2_reg_4686 <= state_10_4_reg_9002;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_10_2_reg_4686 <= state_10_1_reg_3786;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A))) begin
state_10_4_reg_9002 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_10_4_reg_9002 <= state_10_2_reg_4686;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_11_1_reg_3775 <= state_11_2_reg_4671;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_11_1_reg_3775 <= state_11_s_reg_672;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_11_2_reg_4671 <= state_11_4_reg_8944;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_11_2_reg_4671 <= state_11_1_reg_3775;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B))) begin
state_11_4_reg_8944 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_11_4_reg_8944 <= state_11_2_reg_4671;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_12_1_reg_3764 <= state_12_2_reg_4656;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_12_1_reg_3764 <= state_12_s_reg_660;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_12_2_reg_4656 <= state_12_4_reg_8886;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_12_2_reg_4656 <= state_12_1_reg_3764;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C))) begin
state_12_4_reg_8886 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_12_4_reg_8886 <= state_12_2_reg_4656;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_13_1_reg_3753 <= state_13_2_reg_4641;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_13_1_reg_3753 <= state_13_s_reg_648;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_13_2_reg_4641 <= state_13_4_reg_8828;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_13_2_reg_4641 <= state_13_1_reg_3753;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D))) begin
state_13_4_reg_8828 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_13_4_reg_8828 <= state_13_2_reg_4641;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_14_1_reg_3742 <= state_14_2_reg_4626;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_14_1_reg_3742 <= state_14_s_reg_636;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_14_2_reg_4626 <= state_14_4_reg_8770;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_14_2_reg_4626 <= state_14_1_reg_3742;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E))) begin
state_14_4_reg_8770 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_14_4_reg_8770 <= state_14_2_reg_4626;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_15_1_reg_3731 <= state_15_2_reg_4611;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_15_1_reg_3731 <= state_15_s_reg_624;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_15_2_reg_4611 <= state_15_4_reg_8712;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_15_2_reg_4611 <= state_15_1_reg_3731;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_15_4_reg_8712 <= state_15_2_reg_4611;
end else if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0))) begin
state_15_4_reg_8712 <= state_0_fu_13574_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_1_1_reg_3885 <= state_1_2_reg_4821;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_1_1_reg_3885 <= state_1_s_reg_792;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_1_2_reg_4821 <= state_1_4_reg_9524;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_1_2_reg_4821 <= state_1_1_reg_3885;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1))) begin
state_1_4_reg_9524 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_1_4_reg_9524 <= state_1_2_reg_4821;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_2_1_reg_3874 <= state_2_2_reg_4806;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_2_1_reg_3874 <= state_2_s_reg_780;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_2_2_reg_4806 <= state_2_4_reg_9466;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_2_2_reg_4806 <= state_2_1_reg_3874;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2))) begin
state_2_4_reg_9466 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_2_4_reg_9466 <= state_2_2_reg_4806;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_3_1_reg_3863 <= state_3_2_reg_4791;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_3_1_reg_3863 <= state_3_s_reg_768;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_3_2_reg_4791 <= state_3_4_reg_9408;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_3_2_reg_4791 <= state_3_1_reg_3863;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3))) begin
state_3_4_reg_9408 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_3_4_reg_9408 <= state_3_2_reg_4791;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_4_1_reg_3852 <= state_4_2_reg_4776;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_4_1_reg_3852 <= state_4_s_reg_756;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_4_2_reg_4776 <= state_4_4_reg_9350;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_4_2_reg_4776 <= state_4_1_reg_3852;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4))) begin
state_4_4_reg_9350 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_4_4_reg_9350 <= state_4_2_reg_4776;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_5_1_reg_3841 <= state_5_2_reg_4761;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_5_1_reg_3841 <= state_5_s_reg_744;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_5_2_reg_4761 <= state_5_4_reg_9292;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_5_2_reg_4761 <= state_5_1_reg_3841;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5))) begin
state_5_4_reg_9292 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_5_4_reg_9292 <= state_5_2_reg_4761;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_6_1_reg_3830 <= state_6_2_reg_4746;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_6_1_reg_3830 <= state_6_s_reg_732;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_6_2_reg_4746 <= state_6_4_reg_9234;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_6_2_reg_4746 <= state_6_1_reg_3830;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6))) begin
state_6_4_reg_9234 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_6_4_reg_9234 <= state_6_2_reg_4746;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_7_1_reg_3819 <= state_7_2_reg_4731;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_7_1_reg_3819 <= state_7_s_reg_720;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_7_2_reg_4731 <= state_7_4_reg_9176;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_7_2_reg_4731 <= state_7_1_reg_3819;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7))) begin
state_7_4_reg_9176 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_7_4_reg_9176 <= state_7_2_reg_4731;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_8_1_reg_3808 <= state_8_2_reg_4716;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_8_1_reg_3808 <= state_8_s_reg_708;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_8_2_reg_4716 <= state_8_4_reg_9118;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_8_2_reg_4716 <= state_8_1_reg_3808;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8))) begin
state_8_4_reg_9118 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_8_4_reg_9118 <= state_8_2_reg_4716;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
state_9_1_reg_3797 <= state_9_2_reg_4701;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
state_9_1_reg_3797 <= state_9_s_reg_696;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | ((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))))) begin
state_9_2_reg_4701 <= state_9_4_reg_9060;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
state_9_2_reg_4701 <= state_9_1_reg_3797;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9))) begin
state_9_4_reg_9060 <= state_0_fu_13574_p2;
end else if ((((ap_ST_st22_fsm_21 == ap_CS_fsm) & ~(tmp_37_reg_14631 == ap_const_lv4_E) & ~(tmp_37_reg_14631 == ap_const_lv4_D) & ~(tmp_37_reg_14631 == ap_const_lv4_C) & ~(tmp_37_reg_14631 == ap_const_lv4_B) & ~(tmp_37_reg_14631 == ap_const_lv4_A) & ~(tmp_37_reg_14631 == ap_const_lv4_9) & ~(tmp_37_reg_14631 == ap_const_lv4_8) & ~(tmp_37_reg_14631 == ap_const_lv4_7) & ~(tmp_37_reg_14631 == ap_const_lv4_6) & ~(tmp_37_reg_14631 == ap_const_lv4_5) & ~(tmp_37_reg_14631 == ap_const_lv4_4) & ~(tmp_37_reg_14631 == ap_const_lv4_3) & ~(tmp_37_reg_14631 == ap_const_lv4_2) & ~(tmp_37_reg_14631 == ap_const_lv4_1) & ~(tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st22_fsm_21 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841)))) begin
state_9_4_reg_9060 <= state_9_2_reg_4701;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_369) begin
if ((tmp_37_reg_14631 == ap_const_lv4_0)) begin
state_assign_in_reg_12551 <= state_0_4_reg_9582;
end else if ((tmp_37_reg_14631 == ap_const_lv4_E)) begin
state_assign_in_reg_12551 <= state_14_4_reg_8770;
end else if ((tmp_37_reg_14631 == ap_const_lv4_D)) begin
state_assign_in_reg_12551 <= state_13_4_reg_8828;
end else if ((tmp_37_reg_14631 == ap_const_lv4_C)) begin
state_assign_in_reg_12551 <= state_12_4_reg_8886;
end else if ((tmp_37_reg_14631 == ap_const_lv4_B)) begin
state_assign_in_reg_12551 <= state_11_4_reg_8944;
end else if ((tmp_37_reg_14631 == ap_const_lv4_A)) begin
state_assign_in_reg_12551 <= state_10_4_reg_9002;
end else if ((tmp_37_reg_14631 == ap_const_lv4_9)) begin
state_assign_in_reg_12551 <= state_9_4_reg_9060;
end else if ((tmp_37_reg_14631 == ap_const_lv4_8)) begin
state_assign_in_reg_12551 <= state_8_4_reg_9118;
end else if ((tmp_37_reg_14631 == ap_const_lv4_7)) begin
state_assign_in_reg_12551 <= state_7_4_reg_9176;
end else if ((tmp_37_reg_14631 == ap_const_lv4_6)) begin
state_assign_in_reg_12551 <= state_6_4_reg_9234;
end else if ((tmp_37_reg_14631 == ap_const_lv4_5)) begin
state_assign_in_reg_12551 <= state_5_4_reg_9292;
end else if ((tmp_37_reg_14631 == ap_const_lv4_4)) begin
state_assign_in_reg_12551 <= state_4_4_reg_9350;
end else if ((tmp_37_reg_14631 == ap_const_lv4_3)) begin
state_assign_in_reg_12551 <= state_3_4_reg_9408;
end else if ((tmp_37_reg_14631 == ap_const_lv4_2)) begin
state_assign_in_reg_12551 <= state_2_4_reg_9466;
end else if ((tmp_37_reg_14631 == ap_const_lv4_1)) begin
state_assign_in_reg_12551 <= state_1_4_reg_9524;
end else if ((ap_true == ap_true)) begin
state_assign_in_reg_12551 <= state_15_4_reg_8712;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_0_1_reg_1902 <= sym_offset_0_2_reg_2734;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_0_1_reg_1902 <= sym_offset_reg_1380;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0))) begin
sym_offset_0_2_reg_2734 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)))) begin
sym_offset_0_2_reg_2734 <= sym_offset_0_1_reg_1902;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_0_3_reg_4424 <= sym_offset_0_4_reg_5571;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_0_3_reg_4424 <= sym_offset_0_1_reg_1902;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_0_4_reg_5571 <= sym_offset_0_5_reg_12497;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_0_4_reg_5571 <= sym_offset_0_4_reg_5571;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_0_4_reg_5571 <= sym_offset_0_3_reg_4424;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0))) begin
sym_offset_0_5_reg_12497 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)))) begin
sym_offset_0_5_reg_12497 <= sym_offset_0_4_reg_5571;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_10_1_reg_1792 <= sym_offset_10_2_reg_2194;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_10_1_reg_1792 <= sym_offset_10_reg_1260;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A))) begin
sym_offset_10_2_reg_2194 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_10_2_reg_2194 <= sym_offset_10_1_reg_1792;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_10_3_reg_4314 <= sym_offset_10_4_reg_5411;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_10_3_reg_4314 <= sym_offset_10_1_reg_1792;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_10_4_reg_5411 <= sym_offset_10_5_reg_11957;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_10_4_reg_5411 <= sym_offset_10_4_reg_5411;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_10_4_reg_5411 <= sym_offset_10_3_reg_4314;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A))) begin
sym_offset_10_5_reg_11957 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_10_5_reg_11957 <= sym_offset_10_4_reg_5411;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_11_1_reg_1781 <= sym_offset_11_2_reg_2140;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_11_1_reg_1781 <= sym_offset_11_reg_1248;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B))) begin
sym_offset_11_2_reg_2140 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_11_2_reg_2140 <= sym_offset_11_1_reg_1781;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_11_3_reg_4303 <= sym_offset_11_4_reg_5395;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_11_3_reg_4303 <= sym_offset_11_1_reg_1781;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_11_4_reg_5395 <= sym_offset_11_5_reg_11903;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_11_4_reg_5395 <= sym_offset_11_4_reg_5395;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_11_4_reg_5395 <= sym_offset_11_3_reg_4303;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B))) begin
sym_offset_11_5_reg_11903 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_11_5_reg_11903 <= sym_offset_11_4_reg_5395;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_12_1_reg_1770 <= sym_offset_12_2_reg_2086;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_12_1_reg_1770 <= sym_offset_12_reg_1236;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C))) begin
sym_offset_12_2_reg_2086 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_12_2_reg_2086 <= sym_offset_12_1_reg_1770;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_12_3_reg_4292 <= sym_offset_12_4_reg_5379;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_12_3_reg_4292 <= sym_offset_12_1_reg_1770;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_12_4_reg_5379 <= sym_offset_12_5_reg_11849;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_12_4_reg_5379 <= sym_offset_12_4_reg_5379;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_12_4_reg_5379 <= sym_offset_12_3_reg_4292;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C))) begin
sym_offset_12_5_reg_11849 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_12_5_reg_11849 <= sym_offset_12_4_reg_5379;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_13_1_reg_1759 <= sym_offset_13_2_reg_2032;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_13_1_reg_1759 <= sym_offset_13_reg_1224;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D))) begin
sym_offset_13_2_reg_2032 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_13_2_reg_2032 <= sym_offset_13_1_reg_1759;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_13_3_reg_4281 <= sym_offset_13_4_reg_5363;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_13_3_reg_4281 <= sym_offset_13_1_reg_1759;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_13_4_reg_5363 <= sym_offset_13_5_reg_11795;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_13_4_reg_5363 <= sym_offset_13_4_reg_5363;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_13_4_reg_5363 <= sym_offset_13_3_reg_4281;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D))) begin
sym_offset_13_5_reg_11795 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_13_5_reg_11795 <= sym_offset_13_4_reg_5363;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_14_1_reg_1748 <= sym_offset_14_2_reg_1978;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_14_1_reg_1748 <= sym_offset_14_reg_1212;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E))) begin
sym_offset_14_2_reg_1978 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_14_2_reg_1978 <= sym_offset_14_1_reg_1748;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_14_3_reg_4270 <= sym_offset_14_4_reg_5347;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_14_3_reg_4270 <= sym_offset_14_1_reg_1748;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_14_4_reg_5347 <= sym_offset_14_5_reg_11741;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_14_4_reg_5347 <= sym_offset_14_4_reg_5347;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_14_4_reg_5347 <= sym_offset_14_3_reg_4270;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E))) begin
sym_offset_14_5_reg_11741 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_14_5_reg_11741 <= sym_offset_14_4_reg_5347;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_15_1_reg_1737 <= sym_offset_15_2_reg_1924;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_15_1_reg_1737 <= sym_offset_s_reg_1200;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_15_2_reg_1924 <= sym_offset_15_1_reg_1737;
end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
sym_offset_15_2_reg_1924 <= start_indices_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_15_3_reg_4259 <= sym_offset_15_4_reg_5331;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_15_3_reg_4259 <= sym_offset_15_1_reg_1737;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_15_4_reg_5331 <= sym_offset_15_5_reg_11687;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_15_4_reg_5331 <= sym_offset_15_4_reg_5331;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_15_4_reg_5331 <= sym_offset_15_3_reg_4259;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_15_5_reg_11687 <= sym_offset_15_4_reg_5331;
end else if ((ap_ST_st33_fsm_32 == ap_CS_fsm)) begin
sym_offset_15_5_reg_11687 <= sym_offset_0_1_25_fu_13631_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_1_1_reg_1891 <= sym_offset_1_2_reg_2680;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_1_1_reg_1891 <= sym_offset_1_reg_1368;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1))) begin
sym_offset_1_2_reg_2680 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_1_2_reg_2680 <= sym_offset_1_1_reg_1891;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_1_3_reg_4413 <= sym_offset_1_4_reg_5555;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_1_3_reg_4413 <= sym_offset_1_1_reg_1891;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_1_4_reg_5555 <= sym_offset_1_5_reg_12443;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_1_4_reg_5555 <= sym_offset_1_4_reg_5555;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_1_4_reg_5555 <= sym_offset_1_3_reg_4413;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1))) begin
sym_offset_1_5_reg_12443 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_1_5_reg_12443 <= sym_offset_1_4_reg_5555;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_2_1_reg_1880 <= sym_offset_2_2_reg_2626;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_2_1_reg_1880 <= sym_offset_2_reg_1356;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2))) begin
sym_offset_2_2_reg_2626 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_2_2_reg_2626 <= sym_offset_2_1_reg_1880;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_2_3_reg_4402 <= sym_offset_2_4_reg_5539;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_2_3_reg_4402 <= sym_offset_2_1_reg_1880;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_2_4_reg_5539 <= sym_offset_2_5_reg_12389;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_2_4_reg_5539 <= sym_offset_2_4_reg_5539;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_2_4_reg_5539 <= sym_offset_2_3_reg_4402;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2))) begin
sym_offset_2_5_reg_12389 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_2_5_reg_12389 <= sym_offset_2_4_reg_5539;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_3_1_reg_1869 <= sym_offset_3_2_reg_2572;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_3_1_reg_1869 <= sym_offset_3_reg_1344;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3))) begin
sym_offset_3_2_reg_2572 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_3_2_reg_2572 <= sym_offset_3_1_reg_1869;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_3_3_reg_4391 <= sym_offset_3_4_reg_5523;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_3_3_reg_4391 <= sym_offset_3_1_reg_1869;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_3_4_reg_5523 <= sym_offset_3_5_reg_12335;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_3_4_reg_5523 <= sym_offset_3_4_reg_5523;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_3_4_reg_5523 <= sym_offset_3_3_reg_4391;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3))) begin
sym_offset_3_5_reg_12335 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_3_5_reg_12335 <= sym_offset_3_4_reg_5523;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_4_1_reg_1858 <= sym_offset_4_2_reg_2518;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_4_1_reg_1858 <= sym_offset_4_reg_1332;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4))) begin
sym_offset_4_2_reg_2518 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_4_2_reg_2518 <= sym_offset_4_1_reg_1858;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_4_3_reg_4380 <= sym_offset_4_4_reg_5507;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_4_3_reg_4380 <= sym_offset_4_1_reg_1858;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_4_4_reg_5507 <= sym_offset_4_5_reg_12281;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_4_4_reg_5507 <= sym_offset_4_4_reg_5507;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_4_4_reg_5507 <= sym_offset_4_3_reg_4380;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4))) begin
sym_offset_4_5_reg_12281 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_4_5_reg_12281 <= sym_offset_4_4_reg_5507;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_5_1_reg_1847 <= sym_offset_5_2_reg_2464;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_5_1_reg_1847 <= sym_offset_5_reg_1320;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5))) begin
sym_offset_5_2_reg_2464 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_5_2_reg_2464 <= sym_offset_5_1_reg_1847;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_5_3_reg_4369 <= sym_offset_5_4_reg_5491;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_5_3_reg_4369 <= sym_offset_5_1_reg_1847;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_5_4_reg_5491 <= sym_offset_5_5_reg_12227;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_5_4_reg_5491 <= sym_offset_5_4_reg_5491;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_5_4_reg_5491 <= sym_offset_5_3_reg_4369;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5))) begin
sym_offset_5_5_reg_12227 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_5_5_reg_12227 <= sym_offset_5_4_reg_5491;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_6_1_reg_1836 <= sym_offset_6_2_reg_2410;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_6_1_reg_1836 <= sym_offset_6_reg_1308;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6))) begin
sym_offset_6_2_reg_2410 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_6_2_reg_2410 <= sym_offset_6_1_reg_1836;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_6_3_reg_4358 <= sym_offset_6_4_reg_5475;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_6_3_reg_4358 <= sym_offset_6_1_reg_1836;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_6_4_reg_5475 <= sym_offset_6_5_reg_12173;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_6_4_reg_5475 <= sym_offset_6_4_reg_5475;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_6_4_reg_5475 <= sym_offset_6_3_reg_4358;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6))) begin
sym_offset_6_5_reg_12173 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_6_5_reg_12173 <= sym_offset_6_4_reg_5475;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_7_1_reg_1825 <= sym_offset_7_2_reg_2356;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_7_1_reg_1825 <= sym_offset_7_reg_1296;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7))) begin
sym_offset_7_2_reg_2356 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_7_2_reg_2356 <= sym_offset_7_1_reg_1825;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_7_3_reg_4347 <= sym_offset_7_4_reg_5459;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_7_3_reg_4347 <= sym_offset_7_1_reg_1825;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_7_4_reg_5459 <= sym_offset_7_5_reg_12119;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_7_4_reg_5459 <= sym_offset_7_4_reg_5459;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_7_4_reg_5459 <= sym_offset_7_3_reg_4347;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7))) begin
sym_offset_7_5_reg_12119 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_7_5_reg_12119 <= sym_offset_7_4_reg_5459;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_8_1_reg_1814 <= sym_offset_8_2_reg_2302;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_8_1_reg_1814 <= sym_offset_8_reg_1284;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8))) begin
sym_offset_8_2_reg_2302 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_8_2_reg_2302 <= sym_offset_8_1_reg_1814;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_8_3_reg_4336 <= sym_offset_8_4_reg_5443;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_8_3_reg_4336 <= sym_offset_8_1_reg_1814;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_8_4_reg_5443 <= sym_offset_8_5_reg_12065;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_8_4_reg_5443 <= sym_offset_8_4_reg_5443;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_8_4_reg_5443 <= sym_offset_8_3_reg_4336;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8))) begin
sym_offset_8_5_reg_12065 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_8_5_reg_12065 <= sym_offset_8_4_reg_5443;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
sym_offset_9_1_reg_1803 <= sym_offset_9_2_reg_2248;
end else if (((ap_ST_st7_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_13097_p2))) begin
sym_offset_9_1_reg_1803 <= sym_offset_9_reg_1272;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9))) begin
sym_offset_9_2_reg_2248 <= start_indices_q0;
end else if (((ap_ST_st9_fsm_8 == ap_CS_fsm) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1)) | ((ap_ST_st9_fsm_8 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0)))) begin
sym_offset_9_2_reg_2248 <= sym_offset_9_1_reg_1803;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
sym_offset_9_3_reg_4325 <= sym_offset_9_4_reg_5427;
end else if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
sym_offset_9_3_reg_4325 <= sym_offset_9_1_reg_1803;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
sym_offset_9_4_reg_5427 <= sym_offset_9_5_reg_12011;
end else if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2))))) begin
sym_offset_9_4_reg_5427 <= sym_offset_9_4_reg_5427;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sym_offset_9_4_reg_5427 <= sym_offset_9_3_reg_4325;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_9))) begin
sym_offset_9_5_reg_12011 <= sym_offset_0_1_25_fu_13631_p2;
end else if (((ap_ST_st33_fsm_32 == ap_CS_fsm) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_ST_st33_fsm_32 == ap_CS_fsm) & (tmp_37_reg_14631 == ap_const_lv4_0)))) begin
sym_offset_9_5_reg_12011 <= sym_offset_9_4_reg_5427;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
any_state_10_reg_1068 <= any_state_10_4_reg_5166;
any_state_11_reg_1056 <= any_state_11_4_reg_5151;
any_state_12_reg_1044 <= any_state_12_4_reg_5136;
any_state_13_reg_1032 <= any_state_13_4_reg_5121;
any_state_14_reg_1020 <= any_state_14_4_reg_5106;
any_state_1_reg_1176 <= any_state_1_4_reg_5301;
any_state_2_reg_1164 <= any_state_2_4_reg_5286;
any_state_3_reg_1152 <= any_state_3_4_reg_5271;
any_state_4_reg_1140 <= any_state_4_4_reg_5256;
any_state_5_reg_1128 <= any_state_5_4_reg_5241;
any_state_6_reg_1116 <= any_state_6_4_reg_5226;
any_state_7_reg_1104 <= any_state_7_4_reg_5211;
any_state_8_reg_1092 <= any_state_8_4_reg_5196;
any_state_9_reg_1080 <= any_state_9_4_reg_5181;
any_state_reg_1188 <= any_state_0_4_reg_5316;
any_state_s_reg_1008 <= any_state_15_4_reg_5091;
end_0_s_reg_996 <= end_0_2_reg_5076;
end_10_s_reg_876 <= end_10_2_reg_4926;
end_11_s_reg_864 <= end_11_2_reg_4911;
end_12_s_reg_852 <= end_12_2_reg_4896;
end_13_s_reg_840 <= end_13_2_reg_4881;
end_14_s_reg_828 <= end_14_2_reg_4866;
end_15_s_reg_816 <= end_15_2_reg_4851;
end_1_s_reg_984 <= end_1_2_reg_5061;
end_2_s_reg_972 <= end_2_2_reg_5046;
end_3_s_reg_960 <= end_3_2_reg_5031;
end_4_s_reg_948 <= end_4_2_reg_5016;
end_5_s_reg_936 <= end_5_2_reg_5001;
end_6_s_reg_924 <= end_6_2_reg_4986;
end_7_s_reg_912 <= end_7_2_reg_4971;
end_8_s_reg_900 <= end_8_2_reg_4956;
end_9_s_reg_888 <= end_9_2_reg_4941;
state_0_s_reg_804 <= state_0_2_reg_4836;
state_10_s_reg_684 <= state_10_2_reg_4686;
state_11_s_reg_672 <= state_11_2_reg_4671;
state_12_s_reg_660 <= state_12_2_reg_4656;
state_13_s_reg_648 <= state_13_2_reg_4641;
state_14_s_reg_636 <= state_14_2_reg_4626;
state_15_s_reg_624 <= state_15_2_reg_4611;
state_1_s_reg_792 <= state_1_2_reg_4821;
state_2_s_reg_780 <= state_2_2_reg_4806;
state_3_s_reg_768 <= state_3_2_reg_4791;
state_4_s_reg_756 <= state_4_2_reg_4776;
state_5_s_reg_744 <= state_5_2_reg_4761;
state_6_s_reg_732 <= state_6_2_reg_4746;
state_7_s_reg_720 <= state_7_2_reg_4731;
state_8_s_reg_708 <= state_8_2_reg_4716;
state_9_s_reg_696 <= state_9_2_reg_4701;
sym_offset_10_reg_1260 <= sym_offset_10_4_reg_5411;
sym_offset_11_reg_1248 <= sym_offset_11_4_reg_5395;
sym_offset_12_reg_1236 <= sym_offset_12_4_reg_5379;
sym_offset_13_reg_1224 <= sym_offset_13_4_reg_5363;
sym_offset_14_reg_1212 <= sym_offset_14_4_reg_5347;
sym_offset_1_reg_1368 <= sym_offset_1_4_reg_5555;
sym_offset_2_reg_1356 <= sym_offset_2_4_reg_5539;
sym_offset_3_reg_1344 <= sym_offset_3_4_reg_5523;
sym_offset_4_reg_1332 <= sym_offset_4_4_reg_5507;
sym_offset_5_reg_1320 <= sym_offset_5_4_reg_5491;
sym_offset_6_reg_1308 <= sym_offset_6_4_reg_5475;
sym_offset_7_reg_1296 <= sym_offset_7_4_reg_5459;
sym_offset_8_reg_1284 <= sym_offset_8_4_reg_5443;
sym_offset_9_reg_1272 <= sym_offset_9_4_reg_5427;
sym_offset_reg_1380 <= sym_offset_0_4_reg_5571;
sym_offset_s_reg_1200 <= sym_offset_15_4_reg_5331;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st30_fsm_29 == ap_CS_fsm)) begin
brmerge_demorgan_reg_14680 <= brmerge_demorgan_fu_13621_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (ap_const_lv1_0 == end_string_0_phi_fu_6831_p4))) begin
current_buckets_addr_1_reg_14640 <= tmp_5_fu_13550_p1;
next_buckets_addr_3_reg_14635 <= tmp_5_fu_13550_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st7_fsm_6 == ap_CS_fsm)) begin
i_1_reg_14270 <= i_1_fu_13091_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st14_fsm_13 == ap_CS_fsm)) begin
j_0_bucket_index_cast_reg_14592[0] <= j_0_bucket_index_cast_fu_13311_p1[0];
j_0_bucket_index_cast_reg_14592[1] <= j_0_bucket_index_cast_fu_13311_p1[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_A))) begin
j_15_bit_10_fu_272 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
j_15_bit_10_load_reg_14329 <= j_15_bit_10_fu_272;
j_15_bit_11_load_reg_14334 <= j_15_bit_11_fu_276;
j_15_bit_12_load_reg_14339 <= j_15_bit_12_fu_280;
j_15_bit_13_load_reg_14344 <= j_15_bit_13_fu_284;
j_15_bit_14_load_reg_14349 <= j_15_bit_14_fu_288;
j_15_bit_15_load_reg_14354 <= j_15_bit_15_fu_292;
j_15_bit_1_load_reg_14284 <= j_15_bit_1_fu_236;
j_15_bit_2_load_reg_14289 <= j_15_bit_2_fu_240;
j_15_bit_3_load_reg_14294 <= j_15_bit_3_fu_244;
j_15_bit_4_load_reg_14299 <= j_15_bit_4_fu_248;
j_15_bit_5_load_reg_14304 <= j_15_bit_5_fu_252;
j_15_bit_6_load_reg_14309 <= j_15_bit_6_fu_256;
j_15_bit_7_load_reg_14314 <= j_15_bit_7_fu_260;
j_15_bit_8_load_reg_14319 <= j_15_bit_8_fu_264;
j_15_bit_9_load_reg_14324 <= j_15_bit_9_fu_268;
j_15_bit_load_reg_14279 <= j_15_bit_fu_232;
j_15_end_10_load_reg_14489 <= j_15_end_10_fu_400;
j_15_end_11_load_reg_14494 <= j_15_end_11_fu_404;
j_15_end_12_load_reg_14499 <= j_15_end_12_fu_408;
j_15_end_13_load_reg_14504 <= j_15_end_13_fu_412;
j_15_end_14_load_reg_14509 <= j_15_end_14_fu_416;
j_15_end_15_load_reg_14514 <= j_15_end_15_fu_420;
j_15_end_1_load_reg_14444 <= j_15_end_1_fu_364;
j_15_end_2_load_reg_14449 <= j_15_end_2_fu_368;
j_15_end_3_load_reg_14454 <= j_15_end_3_fu_372;
j_15_end_4_load_reg_14459 <= j_15_end_4_fu_376;
j_15_end_5_load_reg_14464 <= j_15_end_5_fu_380;
j_15_end_6_load_reg_14469 <= j_15_end_6_fu_384;
j_15_end_7_load_reg_14474 <= j_15_end_7_fu_388;
j_15_end_8_load_reg_14479 <= j_15_end_8_fu_392;
j_15_end_9_load_reg_14484 <= j_15_end_9_fu_396;
j_15_end_load_reg_14439 <= j_15_end_fu_360;
j_bucket_index_0_load_reg_14359[0] <= j_bucket_index_0_s_fu_296[0];
j_bucket_index_0_load_reg_14359[1] <= j_bucket_index_0_s_fu_296[1];
j_bucket_index_10_load_reg_14409[0] <= j_bucket_index_10_s_fu_336[0];
j_bucket_index_10_load_reg_14409[1] <= j_bucket_index_10_s_fu_336[1];
j_bucket_index_11_load_reg_14414[0] <= j_bucket_index_11_s_fu_340[0];
j_bucket_index_11_load_reg_14414[1] <= j_bucket_index_11_s_fu_340[1];
j_bucket_index_12_load_reg_14419[0] <= j_bucket_index_12_s_fu_344[0];
j_bucket_index_12_load_reg_14419[1] <= j_bucket_index_12_s_fu_344[1];
j_bucket_index_13_load_reg_14424[0] <= j_bucket_index_13_s_fu_348[0];
j_bucket_index_13_load_reg_14424[1] <= j_bucket_index_13_s_fu_348[1];
j_bucket_index_14_load_reg_14429[0] <= j_bucket_index_14_s_fu_352[0];
j_bucket_index_14_load_reg_14429[1] <= j_bucket_index_14_s_fu_352[1];
j_bucket_index_15_load_reg_14434[0] <= j_bucket_index_15_s_fu_356[0];
j_bucket_index_15_load_reg_14434[1] <= j_bucket_index_15_s_fu_356[1];
j_bucket_index_1_load_reg_14364[0] <= j_bucket_index_1_s_fu_300[0];
j_bucket_index_1_load_reg_14364[1] <= j_bucket_index_1_s_fu_300[1];
j_bucket_index_2_load_reg_14369[0] <= j_bucket_index_2_s_fu_304[0];
j_bucket_index_2_load_reg_14369[1] <= j_bucket_index_2_s_fu_304[1];
j_bucket_index_3_load_reg_14374[0] <= j_bucket_index_3_s_fu_308[0];
j_bucket_index_3_load_reg_14374[1] <= j_bucket_index_3_s_fu_308[1];
j_bucket_index_4_load_reg_14379[0] <= j_bucket_index_4_s_fu_312[0];
j_bucket_index_4_load_reg_14379[1] <= j_bucket_index_4_s_fu_312[1];
j_bucket_index_5_load_reg_14384[0] <= j_bucket_index_5_s_fu_316[0];
j_bucket_index_5_load_reg_14384[1] <= j_bucket_index_5_s_fu_316[1];
j_bucket_index_6_load_reg_14389[0] <= j_bucket_index_6_s_fu_320[0];
j_bucket_index_6_load_reg_14389[1] <= j_bucket_index_6_s_fu_320[1];
j_bucket_index_7_load_reg_14394[0] <= j_bucket_index_7_s_fu_324[0];
j_bucket_index_7_load_reg_14394[1] <= j_bucket_index_7_s_fu_324[1];
j_bucket_index_8_load_reg_14399[0] <= j_bucket_index_8_s_fu_328[0];
j_bucket_index_8_load_reg_14399[1] <= j_bucket_index_8_s_fu_328[1];
j_bucket_index_9_load_reg_14404[0] <= j_bucket_index_9_s_fu_332[0];
j_bucket_index_9_load_reg_14404[1] <= j_bucket_index_9_s_fu_332[1];
k_5_reg_14522 <= k_5_fu_13252_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_B))) begin
j_15_bit_11_fu_276 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_C))) begin
j_15_bit_12_fu_280 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_D))) begin
j_15_bit_13_fu_284 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_E))) begin
j_15_bit_14_fu_288 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & ~(tmp_36_reg_14538 == ap_const_lv4_E) & ~(tmp_36_reg_14538 == ap_const_lv4_D) & ~(tmp_36_reg_14538 == ap_const_lv4_C) & ~(tmp_36_reg_14538 == ap_const_lv4_B) & ~(tmp_36_reg_14538 == ap_const_lv4_A) & ~(tmp_36_reg_14538 == ap_const_lv4_9) & ~(tmp_36_reg_14538 == ap_const_lv4_8) & ~(tmp_36_reg_14538 == ap_const_lv4_7) & ~(tmp_36_reg_14538 == ap_const_lv4_6) & ~(tmp_36_reg_14538 == ap_const_lv4_5) & ~(tmp_36_reg_14538 == ap_const_lv4_4) & ~(tmp_36_reg_14538 == ap_const_lv4_3) & ~(tmp_36_reg_14538 == ap_const_lv4_2) & ~(tmp_36_reg_14538 == ap_const_lv4_1) & ~(tmp_36_reg_14538 == ap_const_lv4_0))) begin
j_15_bit_15_fu_292 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st13_fsm_12 == ap_CS_fsm)) begin
j_15_bit_17_fu_228 <= j_15_bit_16_fu_13302_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_1))) begin
j_15_bit_1_fu_236 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_2))) begin
j_15_bit_2_fu_240 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_3))) begin
j_15_bit_3_fu_244 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_4))) begin
j_15_bit_4_fu_248 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_5))) begin
j_15_bit_5_fu_252 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_6))) begin
j_15_bit_6_fu_256 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_7))) begin
j_15_bit_7_fu_260 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_8))) begin
j_15_bit_8_fu_264 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_9))) begin
j_15_bit_9_fu_268 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st14_fsm_13 == ap_CS_fsm) & (tmp_36_reg_14538 == ap_const_lv4_0))) begin
j_15_bit_fu_232 <= j_15_bit_17_fu_228;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_10_fu_400 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_11_fu_404 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_12_fu_408 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_13_fu_412 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_14_fu_416 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(tmp_36_reg_14538 == ap_const_lv4_E) & ~(tmp_36_reg_14538 == ap_const_lv4_D) & ~(tmp_36_reg_14538 == ap_const_lv4_C) & ~(tmp_36_reg_14538 == ap_const_lv4_B) & ~(tmp_36_reg_14538 == ap_const_lv4_A) & ~(tmp_36_reg_14538 == ap_const_lv4_9) & ~(tmp_36_reg_14538 == ap_const_lv4_8) & ~(tmp_36_reg_14538 == ap_const_lv4_7) & ~(tmp_36_reg_14538 == ap_const_lv4_6) & ~(tmp_36_reg_14538 == ap_const_lv4_5) & ~(tmp_36_reg_14538 == ap_const_lv4_4) & ~(tmp_36_reg_14538 == ap_const_lv4_3) & ~(tmp_36_reg_14538 == ap_const_lv4_2) & ~(tmp_36_reg_14538 == ap_const_lv4_1) & ~(tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_15_fu_420 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_1_fu_364 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_2_fu_368 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_3_fu_372 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_4_fu_376 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_5_fu_380 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_6_fu_384 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_7_fu_388 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_8_fu_392 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_9_fu_396 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st16_fsm_15 == ap_CS_fsm))) begin
j_15_end_fu_360 <= j_0_end_reg_3717;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_0_s_fu_296[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_0_s_fu_296[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_A) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_10_s_fu_336[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_10_s_fu_336[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_B) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_11_s_fu_340[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_11_s_fu_340[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_C) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_12_s_fu_344[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_12_s_fu_344[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_D) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_13_s_fu_348[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_13_s_fu_348[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_E) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_14_s_fu_352[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_14_s_fu_352[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(tmp_36_reg_14538 == ap_const_lv4_E) & ~(tmp_36_reg_14538 == ap_const_lv4_D) & ~(tmp_36_reg_14538 == ap_const_lv4_C) & ~(tmp_36_reg_14538 == ap_const_lv4_B) & ~(tmp_36_reg_14538 == ap_const_lv4_A) & ~(tmp_36_reg_14538 == ap_const_lv4_9) & ~(tmp_36_reg_14538 == ap_const_lv4_8) & ~(tmp_36_reg_14538 == ap_const_lv4_7) & ~(tmp_36_reg_14538 == ap_const_lv4_6) & ~(tmp_36_reg_14538 == ap_const_lv4_5) & ~(tmp_36_reg_14538 == ap_const_lv4_4) & ~(tmp_36_reg_14538 == ap_const_lv4_3) & ~(tmp_36_reg_14538 == ap_const_lv4_2) & ~(tmp_36_reg_14538 == ap_const_lv4_1) & ~(tmp_36_reg_14538 == ap_const_lv4_0) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_15_s_fu_356[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_15_s_fu_356[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_1) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_1_s_fu_300[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_1_s_fu_300[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_2) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_2_s_fu_304[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_2_s_fu_304[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_3) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_3_s_fu_308[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_3_s_fu_308[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_4) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_4_s_fu_312[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_4_s_fu_312[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_5) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_5_s_fu_316[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_5_s_fu_316[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_6) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_6_s_fu_320[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_6_s_fu_320[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_7) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_7_s_fu_324[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_7_s_fu_324[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_8) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_8_s_fu_328[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_8_s_fu_328[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_36_reg_14538 == ap_const_lv4_9) & (ap_ST_st15_fsm_14 == ap_CS_fsm))) begin
j_bucket_index_9_s_fu_332[0] <= j_0_bucket_index_cast_reg_14592[0];
j_bucket_index_9_s_fu_332[1] <= j_0_bucket_index_cast_reg_14592[1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin
k_4_reg_13968 <= k_4_fu_12996_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st44_fsm_43 == ap_CS_fsm)) begin
k_6_reg_14754 <= k_6_fu_13723_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st19_fsm_18 == ap_CS_fsm)) begin
k_7_reg_14615 <= k_7_fu_13544_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st45_fsm_44 == ap_CS_fsm) & (ap_const_lv1_0 == end_load_phi_phi_fu_12756_p32))) begin
next_buckets_addr_2_reg_14790 <= tmp_10_reg_14775;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st28_fsm_27 == ap_CS_fsm)) begin
next_buckets_addr_4_reg_14670 <= tmp_5_reg_14621;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm))) begin
nfa_forward_buckets_addr_1_read_reg_14746 <= nfa_forward_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st39_fsm_38 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0))) begin
nfa_forward_buckets_addr_read_reg_14735 <= nfa_forward_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st29_fsm_28 == ap_CS_fsm)) begin
not_s_reg_14675 <= not_s_fu_13615_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st35_fsm_34 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
sample_addr_read_reg_14718 <= sample_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st44_fsm_43 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_13718_p2))) begin
tmp_10_reg_14775[0] <= tmp_10_fu_13729_p1[0];
tmp_10_reg_14775[1] <= tmp_10_fu_13729_p1[1];
tmp_10_reg_14775[2] <= tmp_10_fu_13729_p1[2];
tmp_10_reg_14775[3] <= tmp_10_fu_13729_p1[3];
tmp_10_reg_14775[4] <= tmp_10_fu_13729_p1[4];
tmp_38_reg_14781 <= tmp_38_fu_13733_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & (exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
tmp_36_reg_14538 <= tmp_36_fu_13263_p1;
tmp_8_reg_14527[0] <= tmp_8_fu_13258_p1[0];
tmp_8_reg_14527[1] <= tmp_8_fu_13258_p1[1];
tmp_8_reg_14527[2] <= tmp_8_fu_13258_p1[2];
tmp_8_reg_14527[3] <= tmp_8_fu_13258_p1[3];
tmp_8_reg_14527[4] <= tmp_8_fu_13258_p1[4];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2))) begin
tmp_37_reg_14631 <= tmp_37_fu_13557_p1;
tmp_5_reg_14621[0] <= tmp_5_fu_13550_p1[0];
tmp_5_reg_14621[1] <= tmp_5_fu_13550_p1[1];
tmp_5_reg_14621[2] <= tmp_5_fu_13550_p1[2];
tmp_5_reg_14621[3] <= tmp_5_fu_13550_p1[3];
tmp_5_reg_14621[4] <= tmp_5_fu_13550_p1[4];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) & ~(exitcond2_fu_13247_p2 == ap_const_lv1_0))) begin
tmp_7_reg_14542 <= tmp_7_fu_13267_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st36_fsm_35 == ap_CS_fsm)) begin
tmp_8_i1_reg_14723 <= tmp_8_i1_fu_13669_p2;
end
end
/// any_state_load_1_phi_phi_fu_7706_p32 assign process. ///
always @ (tmp_37_fu_13557_p1 or any_state_15_4_reg_5091 or any_state_14_4_reg_5106 or any_state_13_4_reg_5121 or any_state_12_4_reg_5136 or any_state_11_4_reg_5151 or any_state_10_4_reg_5166 or any_state_9_4_reg_5181 or any_state_8_4_reg_5196 or any_state_7_4_reg_5211 or any_state_6_4_reg_5226 or any_state_5_4_reg_5241 or any_state_4_4_reg_5256 or any_state_3_4_reg_5271 or any_state_2_4_reg_5286 or any_state_1_4_reg_5301 or any_state_0_4_reg_5316 or ap_sig_bdd_1962)
begin
if (ap_sig_bdd_1962) begin
if ((tmp_37_fu_13557_p1 == ap_const_lv4_0)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_0_4_reg_5316;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_E)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_14_4_reg_5106;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_D)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_13_4_reg_5121;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_C)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_12_4_reg_5136;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_B)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_11_4_reg_5151;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_A)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_10_4_reg_5166;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_9)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_9_4_reg_5181;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_8)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_8_4_reg_5196;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_7)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_7_4_reg_5211;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_6)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_6_4_reg_5226;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_5)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_5_4_reg_5241;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_4)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_4_4_reg_5256;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_3)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_3_4_reg_5271;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_2)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_2_4_reg_5286;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_1)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_1_4_reg_5301;
end else if ((ap_true == ap_true)) begin
any_state_load_1_phi_phi_fu_7706_p32 = any_state_15_4_reg_5091;
end else begin
any_state_load_1_phi_phi_fu_7706_p32 = 'bx;
end
end else begin
any_state_load_1_phi_phi_fu_7706_p32 = 'bx;
end
end
/// any_state_load_phi_phi_fu_6778_p32 assign process. ///
always @ (tmp_37_fu_13557_p1 or any_state_15_4_reg_5091 or any_state_14_4_reg_5106 or any_state_13_4_reg_5121 or any_state_12_4_reg_5136 or any_state_11_4_reg_5151 or any_state_10_4_reg_5166 or any_state_9_4_reg_5181 or any_state_8_4_reg_5196 or any_state_7_4_reg_5211 or any_state_6_4_reg_5226 or any_state_5_4_reg_5241 or any_state_4_4_reg_5256 or any_state_3_4_reg_5271 or any_state_2_4_reg_5286 or any_state_1_4_reg_5301 or any_state_0_4_reg_5316 or ap_sig_bdd_1739)
begin
if (ap_sig_bdd_1739) begin
if ((tmp_37_fu_13557_p1 == ap_const_lv4_0)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_0_4_reg_5316;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_E)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_14_4_reg_5106;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_D)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_13_4_reg_5121;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_C)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_12_4_reg_5136;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_B)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_11_4_reg_5151;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_A)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_10_4_reg_5166;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_9)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_9_4_reg_5181;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_8)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_8_4_reg_5196;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_7)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_7_4_reg_5211;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_6)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_6_4_reg_5226;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_5)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_5_4_reg_5241;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_4)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_4_4_reg_5256;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_3)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_3_4_reg_5271;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_2)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_2_4_reg_5286;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_1)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_1_4_reg_5301;
end else if ((ap_true == ap_true)) begin
any_state_load_phi_phi_fu_6778_p32 = any_state_15_4_reg_5091;
end else begin
any_state_load_phi_phi_fu_6778_p32 = 'bx;
end
end else begin
any_state_load_phi_phi_fu_6778_p32 = 'bx;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm)) | (ap_ST_st48_fsm_47 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st48_fsm_47 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_return assign process. ///
always @ (ap_CS_fsm or p_0_reg_12882 or ap_return_preg)
begin
if ((ap_ST_st48_fsm_47 == ap_CS_fsm)) begin
ap_return = p_0_reg_12882;
end else begin
ap_return = ap_return_preg;
end
end
/// current_buckets_address0 assign process. ///
always @ (ap_CS_fsm or tmp_8_reg_14527 or tmp_5_fu_13550_p1 or current_buckets_addr_1_reg_14640 or grp_nfa_get_initials_1_fu_12896_initials_buckets_address0)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
current_buckets_address0 = current_buckets_addr_1_reg_14640;
end else if ((ap_ST_st19_fsm_18 == ap_CS_fsm)) begin
current_buckets_address0 = tmp_5_fu_13550_p1;
end else if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
current_buckets_address0 = tmp_8_reg_14527;
end else if (((ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st3_fsm_2 == ap_CS_fsm) | (ap_ST_st4_fsm_3 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
current_buckets_address0 = grp_nfa_get_initials_1_fu_12896_initials_buckets_address0;
end else begin
current_buckets_address0 = 'bx;
end
end
/// current_buckets_ce0 assign process. ///
always @ (ap_CS_fsm or grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0)
begin
if (((ap_ST_st11_fsm_10 == ap_CS_fsm) | (ap_ST_st19_fsm_18 == ap_CS_fsm) | (ap_ST_st23_fsm_22 == ap_CS_fsm))) begin
current_buckets_ce0 = ap_const_logic_1;
end else if (((ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st3_fsm_2 == ap_CS_fsm) | (ap_ST_st4_fsm_3 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
current_buckets_ce0 = grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0;
end else begin
current_buckets_ce0 = ap_const_logic_0;
end
end
/// current_buckets_d0 assign process. ///
always @ (ap_CS_fsm or next_buckets_q0 or grp_nfa_get_initials_1_fu_12896_initials_buckets_d0)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
current_buckets_d0 = next_buckets_q0;
end else if (((ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st3_fsm_2 == ap_CS_fsm) | (ap_ST_st4_fsm_3 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
current_buckets_d0 = grp_nfa_get_initials_1_fu_12896_initials_buckets_d0;
end else begin
current_buckets_d0 = 'bx;
end
end
/// current_buckets_we0 assign process. ///
always @ (ap_CS_fsm or grp_nfa_get_initials_1_fu_12896_initials_buckets_we0)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
current_buckets_we0 = ap_const_logic_1;
end else if (((ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st3_fsm_2 == ap_CS_fsm) | (ap_ST_st4_fsm_3 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
current_buckets_we0 = grp_nfa_get_initials_1_fu_12896_initials_buckets_we0;
end else begin
current_buckets_we0 = ap_const_logic_0;
end
end
/// end_0_phi_fu_5844_p32 assign process. ///
always @ (j_15_end_load_reg_14439 or j_15_end_1_load_reg_14444 or j_15_end_2_load_reg_14449 or j_15_end_3_load_reg_14454 or j_15_end_4_load_reg_14459 or j_15_end_5_load_reg_14464 or j_15_end_6_load_reg_14469 or j_15_end_7_load_reg_14474 or j_15_end_8_load_reg_14479 or j_15_end_9_load_reg_14484 or j_15_end_10_load_reg_14489 or j_15_end_11_load_reg_14494 or j_15_end_12_load_reg_14499 or j_15_end_13_load_reg_14504 or j_15_end_14_load_reg_14509 or j_15_end_15_load_reg_14514 or tmp_37_fu_13557_p1 or ap_sig_bdd_327)
begin
if (ap_sig_bdd_327) begin
if ((tmp_37_fu_13557_p1 == ap_const_lv4_0)) begin
end_0_phi_fu_5844_p32 = j_15_end_load_reg_14439;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_E)) begin
end_0_phi_fu_5844_p32 = j_15_end_14_load_reg_14509;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_D)) begin
end_0_phi_fu_5844_p32 = j_15_end_13_load_reg_14504;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_C)) begin
end_0_phi_fu_5844_p32 = j_15_end_12_load_reg_14499;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_B)) begin
end_0_phi_fu_5844_p32 = j_15_end_11_load_reg_14494;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_A)) begin
end_0_phi_fu_5844_p32 = j_15_end_10_load_reg_14489;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_9)) begin
end_0_phi_fu_5844_p32 = j_15_end_9_load_reg_14484;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_8)) begin
end_0_phi_fu_5844_p32 = j_15_end_8_load_reg_14479;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_7)) begin
end_0_phi_fu_5844_p32 = j_15_end_7_load_reg_14474;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_6)) begin
end_0_phi_fu_5844_p32 = j_15_end_6_load_reg_14469;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_5)) begin
end_0_phi_fu_5844_p32 = j_15_end_5_load_reg_14464;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_4)) begin
end_0_phi_fu_5844_p32 = j_15_end_4_load_reg_14459;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_3)) begin
end_0_phi_fu_5844_p32 = j_15_end_3_load_reg_14454;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_2)) begin
end_0_phi_fu_5844_p32 = j_15_end_2_load_reg_14449;
end else if ((tmp_37_fu_13557_p1 == ap_const_lv4_1)) begin
end_0_phi_fu_5844_p32 = j_15_end_1_load_reg_14444;
end else if ((ap_true == ap_true)) begin
end_0_phi_fu_5844_p32 = j_15_end_15_load_reg_14514;
end else begin
end_0_phi_fu_5844_p32 = 'bx;
end
end else begin
end_0_phi_fu_5844_p32 = 'bx;
end
end
/// end_load_3_phi_phi_fu_11584_p32 assign process. ///
always @ (ap_CS_fsm or end_15_3_reg_5879 or end_14_3_reg_5935 or end_13_3_reg_5991 or end_12_3_reg_6047 or end_11_3_reg_6103 or end_10_3_reg_6159 or end_9_3_reg_6215 or end_8_3_reg_6271 or end_7_3_reg_6327 or end_6_3_reg_6383 or end_5_3_reg_6439 or end_4_3_reg_6495 or end_3_3_reg_6551 or end_2_3_reg_6607 or end_1_3_reg_6663 or end_0_3_reg_6719 or ap_sig_bdd_2491 or ap_sig_bdd_2495 or ap_sig_bdd_2499 or ap_sig_bdd_2503 or ap_sig_bdd_2507 or ap_sig_bdd_2511 or ap_sig_bdd_2515 or ap_sig_bdd_2519 or ap_sig_bdd_2523 or ap_sig_bdd_2527 or ap_sig_bdd_2531 or ap_sig_bdd_2535 or ap_sig_bdd_2539 or ap_sig_bdd_2543 or ap_sig_bdd_2547 or ap_sig_bdd_2551)
begin
if ((ap_ST_st32_fsm_31 == ap_CS_fsm)) begin
if (ap_sig_bdd_2551) begin
end_load_3_phi_phi_fu_11584_p32 = end_0_3_reg_6719;
end else if (ap_sig_bdd_2547) begin
end_load_3_phi_phi_fu_11584_p32 = end_14_3_reg_5935;
end else if (ap_sig_bdd_2543) begin
end_load_3_phi_phi_fu_11584_p32 = end_13_3_reg_5991;
end else if (ap_sig_bdd_2539) begin
end_load_3_phi_phi_fu_11584_p32 = end_12_3_reg_6047;
end else if (ap_sig_bdd_2535) begin
end_load_3_phi_phi_fu_11584_p32 = end_11_3_reg_6103;
end else if (ap_sig_bdd_2531) begin
end_load_3_phi_phi_fu_11584_p32 = end_10_3_reg_6159;
end else if (ap_sig_bdd_2527) begin
end_load_3_phi_phi_fu_11584_p32 = end_9_3_reg_6215;
end else if (ap_sig_bdd_2523) begin
end_load_3_phi_phi_fu_11584_p32 = end_8_3_reg_6271;
end else if (ap_sig_bdd_2519) begin
end_load_3_phi_phi_fu_11584_p32 = end_7_3_reg_6327;
end else if (ap_sig_bdd_2515) begin
end_load_3_phi_phi_fu_11584_p32 = end_6_3_reg_6383;
end else if (ap_sig_bdd_2511) begin
end_load_3_phi_phi_fu_11584_p32 = end_5_3_reg_6439;
end else if (ap_sig_bdd_2507) begin
end_load_3_phi_phi_fu_11584_p32 = end_4_3_reg_6495;
end else if (ap_sig_bdd_2503) begin
end_load_3_phi_phi_fu_11584_p32 = end_3_3_reg_6551;
end else if (ap_sig_bdd_2499) begin
end_load_3_phi_phi_fu_11584_p32 = end_2_3_reg_6607;
end else if (ap_sig_bdd_2495) begin
end_load_3_phi_phi_fu_11584_p32 = end_1_3_reg_6663;
end else if (ap_sig_bdd_2491) begin
end_load_3_phi_phi_fu_11584_p32 = end_15_3_reg_5879;
end else begin
end_load_3_phi_phi_fu_11584_p32 = 'bx;
end
end else begin
end_load_3_phi_phi_fu_11584_p32 = 'bx;
end
end
/// end_string_0_6_phi_fu_11474_p34 assign process. ///
always @ (ap_CS_fsm or end_string_0_6_reg_11469 or end_0_reg_5841 or end_string_0_5_reg_7649)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_0_6_phi_fu_11474_p34 = end_string_0_5_reg_7649;
end else begin
end_string_0_6_phi_fu_11474_p34 = end_string_0_6_reg_11469;
end
end
/// end_string_0_phi_fu_6831_p4 assign process. ///
always @ (tmp_7_reg_14542 or tmp_12_fu_13561_p2 or ap_sig_bdd_1793)
begin
if (ap_sig_bdd_1793) begin
if (~(ap_const_lv1_0 == tmp_7_reg_14542)) begin
end_string_0_phi_fu_6831_p4 = ap_const_lv1_1;
end else if ((ap_const_lv1_0 == tmp_7_reg_14542)) begin
end_string_0_phi_fu_6831_p4 = tmp_12_fu_13561_p2;
end else begin
end_string_0_phi_fu_6831_p4 = 'bx;
end
end else begin
end_string_0_phi_fu_6831_p4 = 'bx;
end
end
/// end_string_10_6_phi_fu_10884_p34 assign process. ///
always @ (ap_CS_fsm or end_string_10_6_reg_10879 or end_0_reg_5841 or end_string_10_5_reg_7109)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_10_6_phi_fu_10884_p34 = end_string_10_5_reg_7109;
end else begin
end_string_10_6_phi_fu_10884_p34 = end_string_10_6_reg_10879;
end
end
/// end_string_11_6_phi_fu_10825_p34 assign process. ///
always @ (ap_CS_fsm or end_string_11_6_reg_10820 or end_0_reg_5841 or end_string_11_5_reg_7055)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_11_6_phi_fu_10825_p34 = end_string_11_5_reg_7055;
end else begin
end_string_11_6_phi_fu_10825_p34 = end_string_11_6_reg_10820;
end
end
/// end_string_12_6_phi_fu_10766_p34 assign process. ///
always @ (ap_CS_fsm or end_string_12_6_reg_10761 or end_0_reg_5841 or end_string_12_5_reg_7001)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_12_6_phi_fu_10766_p34 = end_string_12_5_reg_7001;
end else begin
end_string_12_6_phi_fu_10766_p34 = end_string_12_6_reg_10761;
end
end
/// end_string_13_6_phi_fu_10707_p34 assign process. ///
always @ (ap_CS_fsm or end_string_13_6_reg_10702 or end_0_reg_5841 or end_string_13_5_reg_6947)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_13_6_phi_fu_10707_p34 = end_string_13_5_reg_6947;
end else begin
end_string_13_6_phi_fu_10707_p34 = end_string_13_6_reg_10702;
end
end
/// end_string_14_6_phi_fu_10648_p34 assign process. ///
always @ (ap_CS_fsm or end_string_14_6_reg_10643 or end_0_reg_5841 or end_string_14_5_reg_6893)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_14_6_phi_fu_10648_p34 = end_string_14_5_reg_6893;
end else begin
end_string_14_6_phi_fu_10648_p34 = end_string_14_6_reg_10643;
end
end
/// end_string_15_6_phi_fu_10589_p34 assign process. ///
always @ (ap_CS_fsm or end_string_15_6_reg_10584 or end_0_reg_5841 or end_string_15_5_reg_6839)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_15_6_phi_fu_10589_p34 = end_string_15_5_reg_6839;
end else begin
end_string_15_6_phi_fu_10589_p34 = end_string_15_6_reg_10584;
end
end
/// end_string_1_6_phi_fu_11415_p34 assign process. ///
always @ (ap_CS_fsm or end_string_1_6_reg_11410 or end_0_reg_5841 or end_string_1_5_reg_7595)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_1_6_phi_fu_11415_p34 = end_string_1_5_reg_7595;
end else begin
end_string_1_6_phi_fu_11415_p34 = end_string_1_6_reg_11410;
end
end
/// end_string_2_6_phi_fu_11356_p34 assign process. ///
always @ (ap_CS_fsm or end_string_2_6_reg_11351 or end_0_reg_5841 or end_string_2_5_reg_7541)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_2_6_phi_fu_11356_p34 = end_string_2_5_reg_7541;
end else begin
end_string_2_6_phi_fu_11356_p34 = end_string_2_6_reg_11351;
end
end
/// end_string_3_6_phi_fu_11297_p34 assign process. ///
always @ (ap_CS_fsm or end_string_3_6_reg_11292 or end_0_reg_5841 or end_string_3_5_reg_7487)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_3_6_phi_fu_11297_p34 = end_string_3_5_reg_7487;
end else begin
end_string_3_6_phi_fu_11297_p34 = end_string_3_6_reg_11292;
end
end
/// end_string_4_6_phi_fu_11238_p34 assign process. ///
always @ (ap_CS_fsm or end_string_4_6_reg_11233 or end_0_reg_5841 or end_string_4_5_reg_7433)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_4_6_phi_fu_11238_p34 = end_string_4_5_reg_7433;
end else begin
end_string_4_6_phi_fu_11238_p34 = end_string_4_6_reg_11233;
end
end
/// end_string_5_6_phi_fu_11179_p34 assign process. ///
always @ (ap_CS_fsm or end_string_5_6_reg_11174 or end_0_reg_5841 or end_string_5_5_reg_7379)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_5_6_phi_fu_11179_p34 = end_string_5_5_reg_7379;
end else begin
end_string_5_6_phi_fu_11179_p34 = end_string_5_6_reg_11174;
end
end
/// end_string_6_6_phi_fu_11120_p34 assign process. ///
always @ (ap_CS_fsm or end_string_6_6_reg_11115 or end_0_reg_5841 or end_string_6_5_reg_7325)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_6_6_phi_fu_11120_p34 = end_string_6_5_reg_7325;
end else begin
end_string_6_6_phi_fu_11120_p34 = end_string_6_6_reg_11115;
end
end
/// end_string_7_6_phi_fu_11061_p34 assign process. ///
always @ (ap_CS_fsm or end_string_7_6_reg_11056 or end_0_reg_5841 or end_string_7_5_reg_7271)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_7_6_phi_fu_11061_p34 = end_string_7_5_reg_7271;
end else begin
end_string_7_6_phi_fu_11061_p34 = end_string_7_6_reg_11056;
end
end
/// end_string_8_6_phi_fu_11002_p34 assign process. ///
always @ (ap_CS_fsm or end_string_8_6_reg_10997 or end_0_reg_5841 or end_string_8_5_reg_7217)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_8_6_phi_fu_11002_p34 = end_string_8_5_reg_7217;
end else begin
end_string_8_6_phi_fu_11002_p34 = end_string_8_6_reg_10997;
end
end
/// end_string_9_6_phi_fu_10943_p34 assign process. ///
always @ (ap_CS_fsm or end_string_9_6_reg_10938 or end_0_reg_5841 or end_string_9_5_reg_7163)
begin
if (((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841))) begin
end_string_9_6_phi_fu_10943_p34 = end_string_9_5_reg_7163;
end else begin
end_string_9_6_phi_fu_10943_p34 = end_string_9_6_reg_10938;
end
end
/// end_string_load_phi_phi_fu_11531_p32 assign process. ///
always @ (ap_CS_fsm or tmp_37_reg_14631 or end_string_15_6_phi_fu_10589_p34 or end_string_14_6_phi_fu_10648_p34 or end_string_13_6_phi_fu_10707_p34 or end_string_12_6_phi_fu_10766_p34 or end_string_11_6_phi_fu_10825_p34 or end_string_10_6_phi_fu_10884_p34 or end_string_9_6_phi_fu_10943_p34 or end_string_8_6_phi_fu_11002_p34 or end_string_7_6_phi_fu_11061_p34 or end_string_6_6_phi_fu_11120_p34 or end_string_5_6_phi_fu_11179_p34 or end_string_4_6_phi_fu_11238_p34 or end_string_3_6_phi_fu_11297_p34 or end_string_2_6_phi_fu_11356_p34 or end_string_1_6_phi_fu_11415_p34 or end_string_0_6_phi_fu_11474_p34)
begin
if ((ap_ST_st30_fsm_29 == ap_CS_fsm)) begin
if ((tmp_37_reg_14631 == ap_const_lv4_0)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_0_6_phi_fu_11474_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_E)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_14_6_phi_fu_10648_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_D)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_13_6_phi_fu_10707_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_C)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_12_6_phi_fu_10766_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_B)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_11_6_phi_fu_10825_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_A)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_10_6_phi_fu_10884_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_9)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_9_6_phi_fu_10943_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_8)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_8_6_phi_fu_11002_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_7)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_7_6_phi_fu_11061_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_6)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_6_6_phi_fu_11120_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_5)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_5_6_phi_fu_11179_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_4)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_4_6_phi_fu_11238_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_3)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_3_6_phi_fu_11297_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_2)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_2_6_phi_fu_11356_p34;
end else if ((tmp_37_reg_14631 == ap_const_lv4_1)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_1_6_phi_fu_11415_p34;
end else if ((ap_true == ap_true)) begin
end_string_load_phi_phi_fu_11531_p32 = end_string_15_6_phi_fu_10589_p34;
end else begin
end_string_load_phi_phi_fu_11531_p32 = 'bx;
end
end else begin
end_string_load_phi_phi_fu_11531_p32 = 'bx;
end
end
/// next_buckets_address0 assign process. ///
always @ (ap_CS_fsm or tmp_8_reg_14527 or tmp_5_fu_13550_p1 or tmp_5_reg_14621 or next_buckets_addr_3_reg_14635 or next_buckets_addr_4_reg_14670 or tmp_10_reg_14775 or next_buckets_addr_2_reg_14790 or tmp_s_fu_13002_p1)
begin
if ((ap_ST_st46_fsm_45 == ap_CS_fsm)) begin
next_buckets_address0 = next_buckets_addr_2_reg_14790;
end else if ((ap_ST_st29_fsm_28 == ap_CS_fsm)) begin
next_buckets_address0 = next_buckets_addr_4_reg_14670;
end else if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
next_buckets_address0 = next_buckets_addr_3_reg_14635;
end else if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
next_buckets_address0 = tmp_8_reg_14527;
end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin
next_buckets_address0 = tmp_s_fu_13002_p1;
end else if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
next_buckets_address0 = tmp_10_reg_14775;
end else if ((ap_ST_st28_fsm_27 == ap_CS_fsm)) begin
next_buckets_address0 = tmp_5_reg_14621;
end else if ((ap_ST_st19_fsm_18 == ap_CS_fsm)) begin
next_buckets_address0 = tmp_5_fu_13550_p1;
end else begin
next_buckets_address0 = 'bx;
end
end
/// next_buckets_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) | (ap_ST_st11_fsm_10 == ap_CS_fsm) | (ap_ST_st19_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_28 == ap_CS_fsm) | (ap_ST_st45_fsm_44 == ap_CS_fsm) | (ap_ST_st46_fsm_45 == ap_CS_fsm) | (ap_ST_st23_fsm_22 == ap_CS_fsm))) begin
next_buckets_ce0 = ap_const_logic_1;
end else begin
next_buckets_ce0 = ap_const_logic_0;
end
end
/// next_buckets_d0 assign process. ///
always @ (ap_CS_fsm or current_buckets_q0 or tmp_49_i_fu_13600_p3 or tmp_68_i_fu_13757_p3)
begin
if ((ap_ST_st46_fsm_45 == ap_CS_fsm)) begin
next_buckets_d0 = tmp_68_i_fu_13757_p3;
end else if ((ap_ST_st29_fsm_28 == ap_CS_fsm)) begin
next_buckets_d0 = tmp_49_i_fu_13600_p3;
end else if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
next_buckets_d0 = current_buckets_q0;
end else if (((ap_ST_st2_fsm_1 == ap_CS_fsm) | (ap_ST_st11_fsm_10 == ap_CS_fsm))) begin
next_buckets_d0 = ap_const_lv64_0;
end else begin
next_buckets_d0 = 'bx;
end
end
/// next_buckets_we0 assign process. ///
always @ (ap_CS_fsm or exitcond3_fu_12991_p2 or end_load_phi_reg_12753)
begin
if (((ap_ST_st11_fsm_10 == ap_CS_fsm) | (ap_ST_st29_fsm_28 == ap_CS_fsm) | ((ap_ST_st2_fsm_1 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_12991_p2)) | (ap_ST_st23_fsm_22 == ap_CS_fsm) | ((ap_ST_st46_fsm_45 == ap_CS_fsm) & (ap_const_lv1_0 == end_load_phi_reg_12753)))) begin
next_buckets_we0 = ap_const_logic_1;
end else begin
next_buckets_we0 = ap_const_logic_0;
end
end
/// nfa_forward_buckets_address assign process. ///
always @ (ap_CS_fsm or tmp_82_i_cast_fu_13682_p1 or tmp_83_i_cast_fu_13700_p1)
begin
if ((ap_ST_st40_fsm_39 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_83_i_cast_fu_13700_p1;
end else if ((ap_ST_st37_fsm_36 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_82_i_cast_fu_13682_p1;
end else begin
nfa_forward_buckets_address = 'bx;
end
end
/// nfa_forward_buckets_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_39 == ap_CS_fsm))) begin
nfa_forward_buckets_req_write = ap_const_logic_1;
end else begin
nfa_forward_buckets_req_write = ap_const_logic_0;
end
end
/// nfa_forward_buckets_rsp_read assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st39_fsm_38 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm)))) begin
nfa_forward_buckets_rsp_read = ap_const_logic_1;
end else begin
nfa_forward_buckets_rsp_read = ap_const_logic_0;
end
end
/// result_address0 assign process. ///
always @ (ap_CS_fsm or tmp_5_fu_13550_p1 or tmp_5_reg_14621 or result_addr_gep_fu_575_p3)
begin
if ((ap_ST_st30_fsm_29 == ap_CS_fsm)) begin
result_address0 = result_addr_gep_fu_575_p3;
end else if ((ap_ST_st19_fsm_18 == ap_CS_fsm)) begin
result_address0 = tmp_5_fu_13550_p1;
end else if ((ap_ST_st31_fsm_30 == ap_CS_fsm)) begin
result_address0 = tmp_5_reg_14621;
end else begin
result_address0 = 'bx;
end
end
/// result_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) | (ap_ST_st30_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_30 == ap_CS_fsm))) begin
result_ce0 = ap_const_logic_1;
end else begin
result_ce0 = ap_const_logic_0;
end
end
/// result_d0 assign process. ///
always @ (ap_CS_fsm or not_s_reg_14675)
begin
if ((ap_ST_st30_fsm_29 == ap_CS_fsm)) begin
result_d0 = not_s_reg_14675;
end else if ((ap_ST_st19_fsm_18 == ap_CS_fsm)) begin
result_d0 = ap_const_lv1_0;
end else begin
result_d0 = 'bx;
end
end
/// result_we0 assign process. ///
always @ (ap_CS_fsm or tmp_9_fu_13539_p2 or end_0_phi_fu_5844_p32 or end_string_0_phi_fu_6831_p4 or end_0_reg_5841 or end_string_0_reg_6828 or any_state_load_1_phi_phi_fu_7706_p32 or any_state_load_1_phi_reg_7703)
begin
if ((((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & ~(ap_const_lv1_0 == end_string_0_phi_fu_6831_p4) & (ap_const_lv1_0 == any_state_load_1_phi_phi_fu_7706_p32)) | ((ap_ST_st30_fsm_29 == ap_CS_fsm) & ~(ap_const_lv1_0 == end_0_reg_5841) & ~(ap_const_lv1_0 == end_string_0_reg_6828) & ~(ap_const_lv1_0 == any_state_load_1_phi_reg_7703)))) begin
result_we0 = ap_const_logic_1;
end else begin
result_we0 = ap_const_logic_0;
end
end
/// sample_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st33_fsm_32 == ap_CS_fsm)) begin
sample_req_write = ap_const_logic_1;
end else begin
sample_req_write = ap_const_logic_0;
end
end
/// sample_rsp_read assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n)
begin
if (((ap_ST_st35_fsm_34 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
sample_rsp_read = ap_const_logic_1;
end else begin
sample_rsp_read = ap_const_logic_0;
end
end
/// start_indices_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
start_indices_ce0 = ap_const_logic_1;
end else begin
start_indices_ce0 = ap_const_logic_0;
end
end
/// tmp_buckets_address0 assign process. ///
always @ (ap_CS_fsm or tmp_5_reg_14621 or tmp_10_reg_14775 or grp_nfa_get_finals_1_fu_12905_finals_buckets_address0 or tmp_buckets_addr_1_gep_fu_547_p3 or tmp_buckets_addr_3_gep_fu_591_p3)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_buckets_address0 = tmp_buckets_addr_3_gep_fu_591_p3;
end else if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
tmp_buckets_address0 = tmp_buckets_addr_1_gep_fu_547_p3;
end else if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
tmp_buckets_address0 = tmp_10_reg_14775;
end else if ((ap_ST_st28_fsm_27 == ap_CS_fsm)) begin
tmp_buckets_address0 = tmp_5_reg_14621;
end else if (((ap_ST_st24_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_24 == ap_CS_fsm) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm))) begin
tmp_buckets_address0 = grp_nfa_get_finals_1_fu_12905_finals_buckets_address0;
end else begin
tmp_buckets_address0 = 'bx;
end
end
/// tmp_buckets_ce0 assign process. ///
always @ (ap_CS_fsm or grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0)
begin
if (((ap_ST_st28_fsm_27 == ap_CS_fsm) | (ap_ST_st45_fsm_44 == ap_CS_fsm) | (ap_ST_st43_fsm_42 == ap_CS_fsm) | (ap_ST_st23_fsm_22 == ap_CS_fsm))) begin
tmp_buckets_ce0 = ap_const_logic_1;
end else if (((ap_ST_st24_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_24 == ap_CS_fsm) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm))) begin
tmp_buckets_ce0 = grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0;
end else begin
tmp_buckets_ce0 = ap_const_logic_0;
end
end
/// tmp_buckets_d0 assign process. ///
always @ (ap_CS_fsm or next_buckets_q0 or grp_nfa_get_finals_1_fu_12905_finals_buckets_d0 or tmp_84_i_fu_13711_p3)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_buckets_d0 = tmp_84_i_fu_13711_p3;
end else if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
tmp_buckets_d0 = next_buckets_q0;
end else if (((ap_ST_st24_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_24 == ap_CS_fsm) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm))) begin
tmp_buckets_d0 = grp_nfa_get_finals_1_fu_12905_finals_buckets_d0;
end else begin
tmp_buckets_d0 = 'bx;
end
end
/// tmp_buckets_we0 assign process. ///
always @ (ap_CS_fsm or grp_nfa_get_finals_1_fu_12905_finals_buckets_we0)
begin
if (((ap_ST_st43_fsm_42 == ap_CS_fsm) | (ap_ST_st23_fsm_22 == ap_CS_fsm))) begin
tmp_buckets_we0 = ap_const_logic_1;
end else if (((ap_ST_st24_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_24 == ap_CS_fsm) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm))) begin
tmp_buckets_we0 = grp_nfa_get_finals_1_fu_12905_finals_buckets_we0;
end else begin
tmp_buckets_we0 = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or sample_rsp_empty_n or exitcond2_fu_13247_p2 or tmp_11_fu_13276_p2 or tmp_9_fu_13539_p2 or end_0_phi_fu_5844_p32 or end_string_0_phi_fu_6831_p4 or brmerge_demorgan_fu_13621_p2 or brmerge_demorgan_reg_14680 or exitcond_fu_13718_p2 or all_end_phi_fu_12651_p36 or exitcond3_fu_12991_p2 or tmp_6_fu_13097_p2 or tmp_27_1_fu_13292_p2 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2 or any_state_load_1_phi_phi_fu_7706_p32)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
if (~(ap_const_lv1_0 == exitcond3_fu_12991_p2)) begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
ap_ST_st3_fsm_2 :
ap_NS_fsm = ap_ST_st4_fsm_3;
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st5_fsm_4;
ap_ST_st5_fsm_4 :
ap_NS_fsm = ap_ST_st6_fsm_5;
ap_ST_st6_fsm_5 :
ap_NS_fsm = ap_ST_st2_fsm_1;
ap_ST_st7_fsm_6 :
if ((ap_const_lv1_0 == tmp_6_fu_13097_p2)) begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end else begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end
ap_ST_st8_fsm_7 :
if (~(exitcond2_fu_13247_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end else begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end
ap_ST_st9_fsm_8 :
ap_NS_fsm = ap_ST_st10_fsm_9;
ap_ST_st10_fsm_9 :
ap_NS_fsm = ap_ST_st11_fsm_10;
ap_ST_st11_fsm_10 :
ap_NS_fsm = ap_ST_st12_fsm_11;
ap_ST_st12_fsm_11 :
if ((~(ap_const_lv1_0 == tmp_11_fu_13276_p2) & ~(ap_const_lv1_0 == tmp_27_1_fu_13292_p2))) begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end else begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
ap_NS_fsm = ap_ST_st14_fsm_13;
ap_ST_st14_fsm_13 :
ap_NS_fsm = ap_ST_st15_fsm_14;
ap_ST_st15_fsm_14 :
ap_NS_fsm = ap_ST_st16_fsm_15;
ap_ST_st16_fsm_15 :
ap_NS_fsm = ap_ST_st17_fsm_16;
ap_ST_st17_fsm_16 :
ap_NS_fsm = ap_ST_st8_fsm_7;
ap_ST_st18_fsm_17 :
ap_NS_fsm = ap_ST_st19_fsm_18;
ap_ST_st19_fsm_18 :
if ((~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & ~(ap_const_lv1_0 == end_string_0_phi_fu_6831_p4) & (ap_const_lv1_0 == any_state_load_1_phi_phi_fu_7706_p32))) begin
ap_NS_fsm = ap_ST_st30_fsm_29;
end else if ((~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & ~(ap_const_lv1_0 == end_string_0_phi_fu_6831_p4) & ~(ap_const_lv1_0 == any_state_load_1_phi_phi_fu_7706_p32))) begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end else if ((~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (ap_const_lv1_0 == end_string_0_phi_fu_6831_p4))) begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end else if ((~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & (ap_const_lv1_0 == end_0_phi_fu_5844_p32))) begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end else begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end
ap_ST_st20_fsm_19 :
ap_NS_fsm = ap_ST_st21_fsm_20;
ap_ST_st21_fsm_20 :
ap_NS_fsm = ap_ST_st22_fsm_21;
ap_ST_st22_fsm_21 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st23_fsm_22 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st24_fsm_23 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st25_fsm_24 :
ap_NS_fsm = ap_ST_st26_fsm_25;
ap_ST_st26_fsm_25 :
ap_NS_fsm = ap_ST_st27_fsm_26;
ap_ST_st27_fsm_26 :
ap_NS_fsm = ap_ST_st28_fsm_27;
ap_ST_st28_fsm_27 :
ap_NS_fsm = ap_ST_st29_fsm_28;
ap_ST_st29_fsm_28 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st30_fsm_29 :
if ((ap_const_lv1_0 == brmerge_demorgan_fu_13621_p2)) begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end else begin
ap_NS_fsm = ap_ST_st31_fsm_30;
end
ap_ST_st31_fsm_30 :
ap_NS_fsm = ap_ST_st32_fsm_31;
ap_ST_st32_fsm_31 :
if ((((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))) begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end else if (((~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | (~(ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)))) begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end else begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end
ap_ST_st33_fsm_32 :
ap_NS_fsm = ap_ST_st34_fsm_33;
ap_ST_st34_fsm_33 :
ap_NS_fsm = ap_ST_st35_fsm_34;
ap_ST_st35_fsm_34 :
if (~(sample_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end else begin
ap_NS_fsm = ap_ST_st35_fsm_34;
end
ap_ST_st36_fsm_35 :
ap_NS_fsm = ap_ST_st37_fsm_36;
ap_ST_st37_fsm_36 :
ap_NS_fsm = ap_ST_st38_fsm_37;
ap_ST_st38_fsm_37 :
ap_NS_fsm = ap_ST_st39_fsm_38;
ap_ST_st39_fsm_38 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st40_fsm_39;
end else begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end
ap_ST_st40_fsm_39 :
ap_NS_fsm = ap_ST_st41_fsm_40;
ap_ST_st41_fsm_40 :
ap_NS_fsm = ap_ST_st42_fsm_41;
ap_ST_st42_fsm_41 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end else begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
ap_ST_st43_fsm_42 :
ap_NS_fsm = ap_ST_st19_fsm_18;
ap_ST_st44_fsm_43 :
if ((~(ap_const_lv1_0 == exitcond_fu_13718_p2) & ~(ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end else if ((~(ap_const_lv1_0 == exitcond_fu_13718_p2) & (ap_const_lv1_0 == all_end_phi_fu_12651_p36))) begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end else begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end
ap_ST_st45_fsm_44 :
ap_NS_fsm = ap_ST_st46_fsm_45;
ap_ST_st46_fsm_45 :
ap_NS_fsm = ap_ST_st47_fsm_46;
ap_ST_st47_fsm_46 :
ap_NS_fsm = ap_ST_st44_fsm_43;
ap_ST_st48_fsm_47 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign all_end_phi_fu_12651_p36 = all_end_reg_12647;
/// ap_sig_bdd_1202 assign process. ///
always @ (tmp_11_fu_13276_p2 or tmp_27_1_fu_13292_p2)
begin
ap_sig_bdd_1202 = (~(ap_const_lv1_0 == tmp_11_fu_13276_p2) & (ap_const_lv1_0 == tmp_27_1_fu_13292_p2));
end
/// ap_sig_bdd_1739 assign process. ///
always @ (ap_CS_fsm or tmp_7_reg_14542 or tmp_9_fu_13539_p2 or end_0_phi_fu_5844_p32)
begin
ap_sig_bdd_1739 = ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & (ap_const_lv1_0 == tmp_7_reg_14542));
end
/// ap_sig_bdd_1793 assign process. ///
always @ (ap_CS_fsm or tmp_9_fu_13539_p2 or end_0_phi_fu_5844_p32)
begin
ap_sig_bdd_1793 = ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32));
end
/// ap_sig_bdd_1962 assign process. ///
always @ (ap_CS_fsm or tmp_9_fu_13539_p2 or end_0_phi_fu_5844_p32 or end_string_0_phi_fu_6831_p4)
begin
ap_sig_bdd_1962 = ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2) & ~(ap_const_lv1_0 == end_0_phi_fu_5844_p32) & ~(ap_const_lv1_0 == end_string_0_phi_fu_6831_p4));
end
/// ap_sig_bdd_2491 assign process. ///
always @ (brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2491 = ((ap_const_lv1_0 == brmerge_demorgan_reg_14680) | ~(ap_const_lv1_0 == tmp1_fu_13626_p2));
end
/// ap_sig_bdd_2495 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2495 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_1)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_1)));
end
/// ap_sig_bdd_2499 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2499 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_2)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_2)));
end
/// ap_sig_bdd_2503 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2503 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_3)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_3)));
end
/// ap_sig_bdd_2507 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2507 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_4)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_4)));
end
/// ap_sig_bdd_2511 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2511 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_5)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_5)));
end
/// ap_sig_bdd_2515 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2515 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_6)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_6)));
end
/// ap_sig_bdd_2519 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2519 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_7)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_7)));
end
/// ap_sig_bdd_2523 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2523 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_8)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_8)));
end
/// ap_sig_bdd_2527 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2527 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_9)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_9)));
end
/// ap_sig_bdd_2531 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2531 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_A)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_A)));
end
/// ap_sig_bdd_2535 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2535 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_B)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_B)));
end
/// ap_sig_bdd_2539 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2539 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_C)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_C)));
end
/// ap_sig_bdd_2543 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2543 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_D)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_D)));
end
/// ap_sig_bdd_2547 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2547 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_E)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_E)));
end
/// ap_sig_bdd_2551 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2551 = (((ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_0)) | (~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_0)));
end
/// ap_sig_bdd_2557 assign process. ///
always @ (brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2557 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2)));
end
/// ap_sig_bdd_2561 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2561 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_1)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_1)));
end
/// ap_sig_bdd_2565 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2565 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_2)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_2)));
end
/// ap_sig_bdd_2569 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2569 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_3)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_3)));
end
/// ap_sig_bdd_2573 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2573 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_4)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_4)));
end
/// ap_sig_bdd_2577 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2577 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_5)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_5)));
end
/// ap_sig_bdd_2581 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2581 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_6)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_6)));
end
/// ap_sig_bdd_2585 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2585 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_7)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_7)));
end
/// ap_sig_bdd_2589 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2589 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_8)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_8)));
end
/// ap_sig_bdd_2593 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2593 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_9)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_9)));
end
/// ap_sig_bdd_2597 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2597 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_A)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_A)));
end
/// ap_sig_bdd_2601 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2601 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_B)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_B)));
end
/// ap_sig_bdd_2605 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2605 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_C)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_C)));
end
/// ap_sig_bdd_2609 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2609 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_D)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_D)));
end
/// ap_sig_bdd_2613 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2613 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_E)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_E)));
end
/// ap_sig_bdd_2617 assign process. ///
always @ (tmp_37_reg_14631 or brmerge_demorgan_reg_14680 or end_load_3_phi_phi_fu_11584_p32 or tmp1_fu_13626_p2)
begin
ap_sig_bdd_2617 = (((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & (ap_const_lv1_0 == brmerge_demorgan_reg_14680) & (tmp_37_reg_14631 == ap_const_lv4_0)) | ((ap_const_lv1_0 == end_load_3_phi_phi_fu_11584_p32) & ~(ap_const_lv1_0 == tmp1_fu_13626_p2) & (tmp_37_reg_14631 == ap_const_lv4_0)));
end
/// ap_sig_bdd_2953 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2953 = ((tmp_38_reg_14781 == ap_const_lv4_1) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2955 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2955 = ((tmp_38_reg_14781 == ap_const_lv4_2) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2957 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2957 = ((tmp_38_reg_14781 == ap_const_lv4_3) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2959 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2959 = ((tmp_38_reg_14781 == ap_const_lv4_4) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2961 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2961 = ((tmp_38_reg_14781 == ap_const_lv4_5) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2963 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2963 = ((tmp_38_reg_14781 == ap_const_lv4_6) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2965 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2965 = ((tmp_38_reg_14781 == ap_const_lv4_7) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2967 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2967 = ((tmp_38_reg_14781 == ap_const_lv4_8) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2969 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2969 = ((tmp_38_reg_14781 == ap_const_lv4_9) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2971 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2971 = ((tmp_38_reg_14781 == ap_const_lv4_A) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2973 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2973 = ((tmp_38_reg_14781 == ap_const_lv4_B) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2975 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2975 = ((tmp_38_reg_14781 == ap_const_lv4_C) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2977 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2977 = ((tmp_38_reg_14781 == ap_const_lv4_D) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2979 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2979 = ((tmp_38_reg_14781 == ap_const_lv4_E) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2981 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2981 = (~(tmp_38_reg_14781 == ap_const_lv4_E) & ~(tmp_38_reg_14781 == ap_const_lv4_D) & ~(tmp_38_reg_14781 == ap_const_lv4_C) & ~(tmp_38_reg_14781 == ap_const_lv4_B) & ~(tmp_38_reg_14781 == ap_const_lv4_A) & ~(tmp_38_reg_14781 == ap_const_lv4_9) & ~(tmp_38_reg_14781 == ap_const_lv4_8) & ~(tmp_38_reg_14781 == ap_const_lv4_7) & ~(tmp_38_reg_14781 == ap_const_lv4_6) & ~(tmp_38_reg_14781 == ap_const_lv4_5) & ~(tmp_38_reg_14781 == ap_const_lv4_4) & ~(tmp_38_reg_14781 == ap_const_lv4_3) & ~(tmp_38_reg_14781 == ap_const_lv4_2) & ~(tmp_38_reg_14781 == ap_const_lv4_1) & ~(tmp_38_reg_14781 == ap_const_lv4_0) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_2983 assign process. ///
always @ (tmp_38_reg_14781 or all_end_reg_12647)
begin
ap_sig_bdd_2983 = ((tmp_38_reg_14781 == ap_const_lv4_0) & ~(ap_const_lv1_0 == all_end_reg_12647));
end
/// ap_sig_bdd_327 assign process. ///
always @ (ap_CS_fsm or tmp_9_fu_13539_p2)
begin
ap_sig_bdd_327 = ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_9_fu_13539_p2));
end
/// ap_sig_bdd_369 assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n)
begin
ap_sig_bdd_369 = ((ap_ST_st35_fsm_34 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0));
end
/// ap_sig_bdd_395 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_13718_p2)
begin
ap_sig_bdd_395 = ((ap_ST_st44_fsm_43 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_13718_p2));
end
assign brmerge_demorgan_fu_13621_p2 = (end_string_load_phi_phi_fu_11531_p32 & stop_on_first);
assign end_load_phi_phi_fu_12756_p32 = end_load_phi_reg_12753;
assign end_string_10_fu_192 = ap_const_lv1_0;
assign end_string_11_fu_196 = ap_const_lv1_0;
assign end_string_12_fu_200 = ap_const_lv1_0;
assign end_string_13_fu_204 = ap_const_lv1_0;
assign end_string_14_fu_208 = ap_const_lv1_0;
assign end_string_1_fu_156 = ap_const_lv1_0;
assign end_string_2_fu_160 = ap_const_lv1_0;
assign end_string_3_fu_164 = ap_const_lv1_0;
assign end_string_4_fu_168 = ap_const_lv1_0;
assign end_string_5_fu_172 = ap_const_lv1_0;
assign end_string_6_fu_176 = ap_const_lv1_0;
assign end_string_7_fu_180 = ap_const_lv1_0;
assign end_string_8_fu_184 = ap_const_lv1_0;
assign end_string_9_fu_188 = ap_const_lv1_0;
assign end_string_fu_152 = ap_const_lv1_0;
assign end_string_s_fu_212 = ap_const_lv1_0;
assign exitcond2_fu_13247_p2 = (k_1_reg_1913 == units? 1'b1: 1'b0);
assign exitcond3_fu_12991_p2 = (k_reg_612 == units? 1'b1: 1'b0);
assign exitcond_fu_13718_p2 = (k_3_reg_12604 == units? 1'b1: 1'b0);
assign grp_fu_12923_p4 = {{next_buckets_q0[ap_const_lv32_3F : ap_const_lv32_20]}};
assign grp_fu_12933_p4 = {{tmp_buckets_q0[ap_const_lv32_3F : ap_const_lv32_20]}};
assign grp_nfa_get_finals_1_fu_12905_ap_ce = ap_const_logic_1;
assign grp_nfa_get_finals_1_fu_12905_ap_start = grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg;
assign grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_datain = nfa_finals_buckets_datain;
assign grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_full_n = nfa_finals_buckets_req_full_n;
assign grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_empty_n = nfa_finals_buckets_rsp_empty_n;
assign grp_nfa_get_finals_1_fu_12905_tmp_28 = k_2_reg_5827;
assign grp_nfa_get_initials_1_fu_12896_ap_ce = ap_const_logic_1;
assign grp_nfa_get_initials_1_fu_12896_ap_start = grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg;
assign grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_datain = nfa_initials_buckets_datain;
assign grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_full_n = nfa_initials_buckets_req_full_n;
assign grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_empty_n = nfa_initials_buckets_rsp_empty_n;
assign grp_nfa_get_initials_1_fu_12896_tmp_s = k_reg_612;
assign i_1_fu_13091_p2 = (i_reg_1552 + ap_const_lv16_FFFF);
assign j_0_bucket_index_cast_fu_13311_p1 = $unsigned(j_0_bucket_index_reg_3706);
assign j_15_bit_16_fu_13302_p1 = $signed(r_bit_p_bsf32_hw_fu_12914_ap_return);
assign k_4_fu_12996_p2 = (k_reg_612 + ap_const_lv5_1);
assign k_5_fu_13252_p2 = (k_1_reg_1913 + ap_const_lv5_1);
assign k_6_fu_13723_p2 = (k_3_reg_12604 + ap_const_lv5_1);
assign k_7_fu_13544_p2 = (k_2_reg_5827 + ap_const_lv5_1);
assign nfa_finals_buckets_address = grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_address;
assign nfa_finals_buckets_dataout = grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_dataout;
assign nfa_finals_buckets_req_din = grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_din;
assign nfa_finals_buckets_req_write = grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_write;
assign nfa_finals_buckets_rsp_read = grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_read;
assign nfa_finals_buckets_size = grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_size;
assign nfa_forward_buckets_dataout = ap_const_lv32_0;
assign nfa_forward_buckets_req_din = ap_const_logic_0;
assign nfa_forward_buckets_size = ap_const_lv32_1;
assign nfa_initials_buckets_address = grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_address;
assign nfa_initials_buckets_dataout = grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_dataout;
assign nfa_initials_buckets_req_din = grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_din;
assign nfa_initials_buckets_req_write = grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_write;
assign nfa_initials_buckets_rsp_read = grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_read;
assign nfa_initials_buckets_size = grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_size;
assign not_s_fu_13615_p2 = (tmp_1_fu_13609_p2 != ap_const_lv32_0? 1'b1: 1'b0);
assign r_1_0_i_lcssa3_cast_fu_13298_p1 = $unsigned(r_1_0_i_lcssa3_reg_3693);
assign r_bit_p_bsf32_hw_fu_12914_bus_r = bus_assign_reg_3684;
assign result_addr_gep_fu_575_p3 = tmp_5_reg_14621;
assign sample_address = tmp_15_fu_13637_p1;
assign sample_dataout = ap_const_lv8_0;
assign sample_req_din = ap_const_logic_0;
assign sample_size = ap_const_lv32_1;
assign start_indices_address0 = tmp_8_fu_13258_p1;
assign state_0_fu_13574_p2 = (tmp_42_fu_13568_p2 + j_bit_addr12_phi_reg_8637);
assign sym_offset_0_1_25_fu_13631_p2 = (offset_reg_11634 + ap_const_lv32_1);
assign tmp1_fu_13626_p2 = (result_q0 ^ accept);
assign tmp_10_fu_13729_p1 = $unsigned(k_3_reg_12604);
assign tmp_11_fu_13276_p2 = (tmp_39_fu_13272_p1 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_12_fu_13561_p2 = (any_state_load_phi_phi_fu_6778_p32 ^ ap_const_lv1_1);
assign tmp_13_fu_13282_p4 = {{current_buckets_q0[ap_const_lv32_3F : ap_const_lv32_20]}};
assign tmp_15_fu_13637_p1 = $unsigned(offset_reg_11634);
assign tmp_1_fu_13609_p2 = (tmp_8_i_fu_13588_p2 | tmp_8_1_i_fu_13594_p2);
assign tmp_27_1_fu_13292_p2 = (tmp_13_fu_13282_p4 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_35_fu_13007_p1 = k_reg_612[3:0];
assign tmp_36_fu_13263_p1 = k_1_reg_1913[3:0];
assign tmp_37_fu_13557_p1 = k_2_reg_5827[3:0];
assign tmp_38_fu_13733_p1 = k_3_reg_12604[3:0];
assign tmp_39_fu_13272_p1 = current_buckets_q0[31:0];
assign tmp_40_fu_13737_p1 = tmp_buckets_q0[31:0];
assign tmp_41_fu_13741_p1 = next_buckets_q0[31:0];
assign tmp_42_fu_13568_p2 = j_bucket_index_addr13_phi_reg_8675 << ap_const_lv8_5;
assign tmp_43_fu_13580_p1 = tmp_buckets_q0[31:0];
assign tmp_44_fu_13584_p1 = next_buckets_q0[31:0];
assign tmp_45_fu_13648_p1 = state_assign_in_reg_12551[5:0];
assign tmp_49_i_fu_13600_p3 = {{tmp_8_1_i_fu_13594_p2}, {tmp_8_i_fu_13588_p2}};
assign tmp_57_i_fu_13745_p2 = (tmp_41_fu_13741_p1 | tmp_40_fu_13737_p1);
assign tmp_5_fu_13550_p1 = $unsigned(k_2_reg_5827);
assign tmp_68_i_fu_13757_p3 = {{tmp_6_1_i_fu_13751_p2}, {tmp_57_i_fu_13745_p2}};
assign tmp_6_1_i_fu_13751_p2 = (grp_fu_12923_p4 | grp_fu_12933_p4);
assign tmp_6_fu_13097_p2 = (i_reg_1552 == ap_const_lv16_0? 1'b1: 1'b0);
assign tmp_6_i_fu_13660_p0 = tmp_6_i_fu_13660_p00;
assign tmp_6_i_fu_13660_p00 = $unsigned(nfa_symbols);
assign tmp_6_i_fu_13660_p1 = tmp_6_i_fu_13660_p10;
assign tmp_6_i_fu_13660_p10 = $unsigned(tmp_45_fu_13648_p1);
assign tmp_6_i_fu_13660_p2 = ($signed({{1'b0}, {tmp_6_i_fu_13660_p0}}) * $signed({{1'b0}, {tmp_6_i_fu_13660_p1}}));
assign tmp_7_fu_13267_p2 = (i_1_reg_14270 == ap_const_lv16_0? 1'b1: 1'b0);
assign tmp_7_i_cast_fu_13666_p1 = $unsigned(sample_addr_read_reg_14718);
assign tmp_82_i_cast_fu_13682_p1 = $unsigned(tmp_82_i_fu_13675_p3);
assign tmp_82_i_fu_13675_p3 = {{tmp_8_i1_reg_14723}, {ap_const_lv1_0}};
assign tmp_83_i_cast_fu_13700_p1 = $unsigned(tmp_83_i_fu_13693_p3);
assign tmp_83_i_fu_13693_p3 = {{tmp_8_i1_reg_14723}, {ap_const_lv1_1}};
assign tmp_84_i_fu_13711_p3 = {{nfa_forward_buckets_addr_1_read_reg_14746}, {nfa_forward_buckets_addr_read_reg_14735}};
assign tmp_8_1_i_fu_13594_p2 = (grp_fu_12923_p4 & grp_fu_12933_p4);
assign tmp_8_fu_13258_p1 = $unsigned(k_1_reg_1913);
assign tmp_8_i1_fu_13669_p2 = (tmp_6_i_fu_13660_p2 + tmp_7_i_cast_fu_13666_p1);
assign tmp_8_i_fu_13588_p2 = (tmp_44_fu_13584_p1 & tmp_43_fu_13580_p1);
assign tmp_9_fu_13539_p2 = (k_2_reg_5827 < units? 1'b1: 1'b0);
assign tmp_buckets_addr_1_gep_fu_547_p3 = tmp_5_reg_14621;
assign tmp_buckets_addr_3_gep_fu_591_p3 = tmp_5_reg_14621;
assign tmp_s_fu_13002_p1 = $unsigned(k_reg_612);
always @ (posedge ap_clk)
begin
j_bucket_index_0_load_reg_14359[7:2] <= 6'b000000;
j_bucket_index_1_load_reg_14364[7:2] <= 6'b000000;
j_bucket_index_2_load_reg_14369[7:2] <= 6'b000000;
j_bucket_index_3_load_reg_14374[7:2] <= 6'b000000;
j_bucket_index_4_load_reg_14379[7:2] <= 6'b000000;
j_bucket_index_5_load_reg_14384[7:2] <= 6'b000000;
j_bucket_index_6_load_reg_14389[7:2] <= 6'b000000;
j_bucket_index_7_load_reg_14394[7:2] <= 6'b000000;
j_bucket_index_8_load_reg_14399[7:2] <= 6'b000000;
j_bucket_index_9_load_reg_14404[7:2] <= 6'b000000;
j_bucket_index_10_load_reg_14409[7:2] <= 6'b000000;
j_bucket_index_11_load_reg_14414[7:2] <= 6'b000000;
j_bucket_index_12_load_reg_14419[7:2] <= 6'b000000;
j_bucket_index_13_load_reg_14424[7:2] <= 6'b000000;
j_bucket_index_14_load_reg_14429[7:2] <= 6'b000000;
j_bucket_index_15_load_reg_14434[7:2] <= 6'b000000;
tmp_8_reg_14527[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000;
j_0_bucket_index_cast_reg_14592[7:2] <= 6'b000000;
tmp_5_reg_14621[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000;
tmp_10_reg_14775[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000;
j_bucket_index_addr13_phi_reg_8675[7:2] <= 6'b000000;
j_bucket_index_0_s_fu_296[7:2] <= 6'b000000;
j_bucket_index_1_s_fu_300[7:2] <= 6'b000000;
j_bucket_index_2_s_fu_304[7:2] <= 6'b000000;
j_bucket_index_3_s_fu_308[7:2] <= 6'b000000;
j_bucket_index_4_s_fu_312[7:2] <= 6'b000000;
j_bucket_index_5_s_fu_316[7:2] <= 6'b000000;
j_bucket_index_6_s_fu_320[7:2] <= 6'b000000;
j_bucket_index_7_s_fu_324[7:2] <= 6'b000000;
j_bucket_index_8_s_fu_328[7:2] <= 6'b000000;
j_bucket_index_9_s_fu_332[7:2] <= 6'b000000;
j_bucket_index_10_s_fu_336[7:2] <= 6'b000000;
j_bucket_index_11_s_fu_340[7:2] <= 6'b000000;
j_bucket_index_12_s_fu_344[7:2] <= 6'b000000;
j_bucket_index_13_s_fu_348[7:2] <= 6'b000000;
j_bucket_index_14_s_fu_352[7:2] <= 6'b000000;
j_bucket_index_15_s_fu_356[7:2] <= 6'b000000;
end
endmodule //nfa_accept_sample_multi
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 10 01:06:40 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381,
DP_OP_110J126_122_4535_n1142, DP_OP_110J126_122_4535_n1138,
DP_OP_110J126_122_4535_n1130, DP_OP_110J126_122_4535_n1129,
DP_OP_110J126_122_4535_n1126, DP_OP_110J126_122_4535_n1125,
DP_OP_110J126_122_4535_n1123, DP_OP_110J126_122_4535_n1122,
DP_OP_110J126_122_4535_n1121, DP_OP_110J126_122_4535_n1118,
DP_OP_110J126_122_4535_n1117, DP_OP_110J126_122_4535_n1116,
DP_OP_110J126_122_4535_n1115, DP_OP_110J126_122_4535_n1114,
DP_OP_110J126_122_4535_n1113, DP_OP_110J126_122_4535_n1112,
DP_OP_110J126_122_4535_n1110, DP_OP_110J126_122_4535_n1109,
DP_OP_110J126_122_4535_n1108, DP_OP_110J126_122_4535_n1107,
DP_OP_110J126_122_4535_n1106, DP_OP_110J126_122_4535_n1105,
DP_OP_110J126_122_4535_n1104, DP_OP_110J126_122_4535_n1102,
DP_OP_110J126_122_4535_n1101, DP_OP_110J126_122_4535_n1100,
DP_OP_110J126_122_4535_n1099, DP_OP_110J126_122_4535_n1096,
DP_OP_110J126_122_4535_n1095, DP_OP_110J126_122_4535_n1093,
DP_OP_110J126_122_4535_n1090, DP_OP_110J126_122_4535_n1089,
DP_OP_110J126_122_4535_n1088, DP_OP_110J126_122_4535_n1086,
DP_OP_110J126_122_4535_n1085, DP_OP_110J126_122_4535_n1084,
DP_OP_110J126_122_4535_n1083, DP_OP_110J126_122_4535_n1080,
DP_OP_110J126_122_4535_n1079, DP_OP_110J126_122_4535_n1078,
DP_OP_110J126_122_4535_n1077, DP_OP_110J126_122_4535_n1076,
DP_OP_110J126_122_4535_n1075, DP_OP_110J126_122_4535_n1074,
DP_OP_110J126_122_4535_n1073, DP_OP_110J126_122_4535_n1072,
DP_OP_110J126_122_4535_n1071, DP_OP_110J126_122_4535_n1070,
DP_OP_110J126_122_4535_n1069, DP_OP_110J126_122_4535_n1068,
DP_OP_110J126_122_4535_n1067, DP_OP_110J126_122_4535_n1047,
DP_OP_110J126_122_4535_n1044, DP_OP_110J126_122_4535_n1043,
DP_OP_110J126_122_4535_n1042, DP_OP_110J126_122_4535_n1041,
DP_OP_110J126_122_4535_n1040, DP_OP_110J126_122_4535_n1039,
DP_OP_110J126_122_4535_n1038, DP_OP_110J126_122_4535_n1037,
DP_OP_110J126_122_4535_n1036, DP_OP_110J126_122_4535_n1035,
DP_OP_110J126_122_4535_n1034, DP_OP_110J126_122_4535_n1033,
DP_OP_110J126_122_4535_n1032, DP_OP_110J126_122_4535_n1031,
DP_OP_110J126_122_4535_n1030, DP_OP_110J126_122_4535_n1029,
DP_OP_110J126_122_4535_n1028, DP_OP_110J126_122_4535_n1027,
DP_OP_110J126_122_4535_n1026, DP_OP_110J126_122_4535_n1025,
DP_OP_110J126_122_4535_n1024, DP_OP_110J126_122_4535_n1023,
DP_OP_110J126_122_4535_n1022, DP_OP_110J126_122_4535_n1021,
DP_OP_110J126_122_4535_n1020, DP_OP_110J126_122_4535_n1019,
DP_OP_110J126_122_4535_n1018, DP_OP_110J126_122_4535_n1017,
DP_OP_110J126_122_4535_n1016, DP_OP_110J126_122_4535_n1015,
DP_OP_110J126_122_4535_n1014, DP_OP_110J126_122_4535_n1013,
DP_OP_110J126_122_4535_n1012, DP_OP_110J126_122_4535_n1011,
DP_OP_110J126_122_4535_n1010, DP_OP_110J126_122_4535_n1009,
DP_OP_110J126_122_4535_n1008, DP_OP_110J126_122_4535_n1007,
DP_OP_110J126_122_4535_n1006, DP_OP_110J126_122_4535_n1005,
DP_OP_110J126_122_4535_n1004, DP_OP_110J126_122_4535_n1003,
DP_OP_110J126_122_4535_n1001, DP_OP_110J126_122_4535_n1000,
DP_OP_110J126_122_4535_n999, DP_OP_110J126_122_4535_n998,
DP_OP_110J126_122_4535_n997, DP_OP_110J126_122_4535_n996,
DP_OP_110J126_122_4535_n995, DP_OP_110J126_122_4535_n994,
DP_OP_110J126_122_4535_n991, DP_OP_110J126_122_4535_n990,
DP_OP_110J126_122_4535_n989, DP_OP_110J126_122_4535_n988,
DP_OP_110J126_122_4535_n987, DP_OP_110J126_122_4535_n986,
DP_OP_110J126_122_4535_n985, DP_OP_110J126_122_4535_n984,
DP_OP_110J126_122_4535_n983, DP_OP_110J126_122_4535_n982,
DP_OP_110J126_122_4535_n981, DP_OP_110J126_122_4535_n980,
DP_OP_110J126_122_4535_n979, DP_OP_110J126_122_4535_n978,
DP_OP_110J126_122_4535_n977, DP_OP_110J126_122_4535_n976,
DP_OP_110J126_122_4535_n973, DP_OP_110J126_122_4535_n972,
DP_OP_110J126_122_4535_n971, DP_OP_110J126_122_4535_n970,
DP_OP_110J126_122_4535_n969, DP_OP_110J126_122_4535_n968,
DP_OP_110J126_122_4535_n967, DP_OP_110J126_122_4535_n966,
DP_OP_110J126_122_4535_n965, DP_OP_110J126_122_4535_n964,
DP_OP_110J126_122_4535_n963, DP_OP_110J126_122_4535_n962,
DP_OP_110J126_122_4535_n959, DP_OP_110J126_122_4535_n958,
DP_OP_110J126_122_4535_n957, DP_OP_110J126_122_4535_n956,
DP_OP_110J126_122_4535_n955, DP_OP_110J126_122_4535_n954,
DP_OP_110J126_122_4535_n953, DP_OP_110J126_122_4535_n952,
DP_OP_110J126_122_4535_n951, DP_OP_110J126_122_4535_n950,
DP_OP_110J126_122_4535_n947, DP_OP_110J126_122_4535_n946,
DP_OP_110J126_122_4535_n945, DP_OP_110J126_122_4535_n944,
DP_OP_110J126_122_4535_n943, DP_OP_110J126_122_4535_n942,
DP_OP_110J126_122_4535_n761, DP_OP_110J126_122_4535_n757,
DP_OP_110J126_122_4535_n749, DP_OP_110J126_122_4535_n748,
DP_OP_110J126_122_4535_n745, DP_OP_110J126_122_4535_n744,
DP_OP_110J126_122_4535_n742, DP_OP_110J126_122_4535_n741,
DP_OP_110J126_122_4535_n740, DP_OP_110J126_122_4535_n737,
DP_OP_110J126_122_4535_n736, DP_OP_110J126_122_4535_n735,
DP_OP_110J126_122_4535_n734, DP_OP_110J126_122_4535_n733,
DP_OP_110J126_122_4535_n732, DP_OP_110J126_122_4535_n731,
DP_OP_110J126_122_4535_n729, DP_OP_110J126_122_4535_n728,
DP_OP_110J126_122_4535_n727, DP_OP_110J126_122_4535_n726,
DP_OP_110J126_122_4535_n725, DP_OP_110J126_122_4535_n724,
DP_OP_110J126_122_4535_n723, DP_OP_110J126_122_4535_n721,
DP_OP_110J126_122_4535_n720, DP_OP_110J126_122_4535_n719,
DP_OP_110J126_122_4535_n718, DP_OP_110J126_122_4535_n715,
DP_OP_110J126_122_4535_n714, DP_OP_110J126_122_4535_n712,
DP_OP_110J126_122_4535_n709, DP_OP_110J126_122_4535_n708,
DP_OP_110J126_122_4535_n707, DP_OP_110J126_122_4535_n705,
DP_OP_110J126_122_4535_n704, DP_OP_110J126_122_4535_n703,
DP_OP_110J126_122_4535_n702, DP_OP_110J126_122_4535_n699,
DP_OP_110J126_122_4535_n698, DP_OP_110J126_122_4535_n697,
DP_OP_110J126_122_4535_n696, DP_OP_110J126_122_4535_n695,
DP_OP_110J126_122_4535_n694, DP_OP_110J126_122_4535_n693,
DP_OP_110J126_122_4535_n692, DP_OP_110J126_122_4535_n691,
DP_OP_110J126_122_4535_n690, DP_OP_110J126_122_4535_n689,
DP_OP_110J126_122_4535_n688, DP_OP_110J126_122_4535_n687,
DP_OP_110J126_122_4535_n686, DP_OP_110J126_122_4535_n680,
DP_OP_110J126_122_4535_n678, DP_OP_110J126_122_4535_n665,
DP_OP_110J126_122_4535_n662, DP_OP_110J126_122_4535_n661,
DP_OP_110J126_122_4535_n660, DP_OP_110J126_122_4535_n659,
DP_OP_110J126_122_4535_n658, DP_OP_110J126_122_4535_n657,
DP_OP_110J126_122_4535_n656, DP_OP_110J126_122_4535_n655,
DP_OP_110J126_122_4535_n654, DP_OP_110J126_122_4535_n653,
DP_OP_110J126_122_4535_n652, DP_OP_110J126_122_4535_n651,
DP_OP_110J126_122_4535_n650, DP_OP_110J126_122_4535_n649,
DP_OP_110J126_122_4535_n648, DP_OP_110J126_122_4535_n647,
DP_OP_110J126_122_4535_n646, DP_OP_110J126_122_4535_n645,
DP_OP_110J126_122_4535_n644, DP_OP_110J126_122_4535_n643,
DP_OP_110J126_122_4535_n642, DP_OP_110J126_122_4535_n641,
DP_OP_110J126_122_4535_n640, DP_OP_110J126_122_4535_n639,
DP_OP_110J126_122_4535_n638, DP_OP_110J126_122_4535_n637,
DP_OP_110J126_122_4535_n636, DP_OP_110J126_122_4535_n635,
DP_OP_110J126_122_4535_n634, DP_OP_110J126_122_4535_n633,
DP_OP_110J126_122_4535_n632, DP_OP_110J126_122_4535_n631,
DP_OP_110J126_122_4535_n630, DP_OP_110J126_122_4535_n629,
DP_OP_110J126_122_4535_n628, DP_OP_110J126_122_4535_n627,
DP_OP_110J126_122_4535_n626, DP_OP_110J126_122_4535_n625,
DP_OP_110J126_122_4535_n624, DP_OP_110J126_122_4535_n623,
DP_OP_110J126_122_4535_n622, DP_OP_110J126_122_4535_n621,
DP_OP_110J126_122_4535_n619, DP_OP_110J126_122_4535_n618,
DP_OP_110J126_122_4535_n617, DP_OP_110J126_122_4535_n616,
DP_OP_110J126_122_4535_n615, DP_OP_110J126_122_4535_n614,
DP_OP_110J126_122_4535_n613, DP_OP_110J126_122_4535_n612,
DP_OP_110J126_122_4535_n609, DP_OP_110J126_122_4535_n608,
DP_OP_110J126_122_4535_n607, DP_OP_110J126_122_4535_n606,
DP_OP_110J126_122_4535_n605, DP_OP_110J126_122_4535_n604,
DP_OP_110J126_122_4535_n603, DP_OP_110J126_122_4535_n602,
DP_OP_110J126_122_4535_n601, DP_OP_110J126_122_4535_n600,
DP_OP_110J126_122_4535_n599, DP_OP_110J126_122_4535_n598,
DP_OP_110J126_122_4535_n597, DP_OP_110J126_122_4535_n596,
DP_OP_110J126_122_4535_n595, DP_OP_110J126_122_4535_n594,
DP_OP_110J126_122_4535_n593, DP_OP_110J126_122_4535_n592,
DP_OP_110J126_122_4535_n591, DP_OP_110J126_122_4535_n590,
DP_OP_110J126_122_4535_n589, DP_OP_110J126_122_4535_n588,
DP_OP_110J126_122_4535_n587, DP_OP_110J126_122_4535_n586,
DP_OP_110J126_122_4535_n585, DP_OP_110J126_122_4535_n584,
DP_OP_110J126_122_4535_n583, DP_OP_110J126_122_4535_n582,
DP_OP_110J126_122_4535_n581, DP_OP_110J126_122_4535_n580,
DP_OP_110J126_122_4535_n577, DP_OP_110J126_122_4535_n576,
DP_OP_110J126_122_4535_n575, DP_OP_110J126_122_4535_n574,
DP_OP_110J126_122_4535_n573, DP_OP_110J126_122_4535_n572,
DP_OP_110J126_122_4535_n571, DP_OP_110J126_122_4535_n570,
DP_OP_110J126_122_4535_n569, DP_OP_110J126_122_4535_n568,
DP_OP_110J126_122_4535_n567, DP_OP_110J126_122_4535_n566,
DP_OP_110J126_122_4535_n565, DP_OP_110J126_122_4535_n564,
DP_OP_110J126_122_4535_n563, DP_OP_110J126_122_4535_n562,
DP_OP_110J126_122_4535_n561, DP_OP_110J126_122_4535_n560,
DP_OP_110J126_122_4535_n528, DP_OP_110J126_122_4535_n527,
DP_OP_110J126_122_4535_n525, DP_OP_110J126_122_4535_n524,
DP_OP_110J126_122_4535_n523, DP_OP_110J126_122_4535_n522,
DP_OP_110J126_122_4535_n521, DP_OP_110J126_122_4535_n520,
DP_OP_110J126_122_4535_n519, DP_OP_110J126_122_4535_n518,
DP_OP_110J126_122_4535_n517, DP_OP_110J126_122_4535_n516,
DP_OP_110J126_122_4535_n515, DP_OP_110J126_122_4535_n514,
DP_OP_110J126_122_4535_n513, DP_OP_110J126_122_4535_n512,
DP_OP_110J126_122_4535_n511, DP_OP_110J126_122_4535_n510,
DP_OP_110J126_122_4535_n509, DP_OP_110J126_122_4535_n508,
DP_OP_110J126_122_4535_n507, DP_OP_110J126_122_4535_n506,
DP_OP_110J126_122_4535_n346, DP_OP_110J126_122_4535_n345,
DP_OP_110J126_122_4535_n342, DP_OP_110J126_122_4535_n341,
DP_OP_110J126_122_4535_n340, DP_OP_110J126_122_4535_n339,
DP_OP_110J126_122_4535_n338, DP_OP_110J126_122_4535_n337,
DP_OP_110J126_122_4535_n336, DP_OP_110J126_122_4535_n335,
DP_OP_110J126_122_4535_n333, DP_OP_110J126_122_4535_n332,
DP_OP_110J126_122_4535_n329, DP_OP_110J126_122_4535_n325,
DP_OP_110J126_122_4535_n324, DP_OP_110J126_122_4535_n323,
DP_OP_110J126_122_4535_n322, DP_OP_110J126_122_4535_n321,
DP_OP_110J126_122_4535_n317, DP_OP_110J126_122_4535_n316,
DP_OP_110J126_122_4535_n312, DP_OP_110J126_122_4535_n308,
DP_OP_110J126_122_4535_n307, DP_OP_110J126_122_4535_n306,
DP_OP_110J126_122_4535_n305, DP_OP_110J126_122_4535_n304,
DP_OP_110J126_122_4535_n303, DP_OP_110J126_122_4535_n302,
DP_OP_110J126_122_4535_n301, DP_OP_110J126_122_4535_n299,
DP_OP_110J126_122_4535_n292, DP_OP_110J126_122_4535_n291,
DP_OP_110J126_122_4535_n288, DP_OP_110J126_122_4535_n287,
DP_OP_110J126_122_4535_n286, DP_OP_110J126_122_4535_n285,
DP_OP_110J126_122_4535_n284, DP_OP_110J126_122_4535_n283,
DP_OP_110J126_122_4535_n279, DP_OP_110J126_122_4535_n278,
DP_OP_110J126_122_4535_n275, DP_OP_110J126_122_4535_n274,
DP_OP_110J126_122_4535_n273, DP_OP_110J126_122_4535_n272,
DP_OP_110J126_122_4535_n271, DP_OP_110J126_122_4535_n270,
DP_OP_110J126_122_4535_n269, DP_OP_110J126_122_4535_n268,
DP_OP_110J126_122_4535_n267, DP_OP_110J126_122_4535_n266,
DP_OP_110J126_122_4535_n265, DP_OP_110J126_122_4535_n264,
DP_OP_110J126_122_4535_n263, DP_OP_110J126_122_4535_n262,
DP_OP_110J126_122_4535_n261, DP_OP_110J126_122_4535_n259,
DP_OP_110J126_122_4535_n258, DP_OP_110J126_122_4535_n257,
DP_OP_110J126_122_4535_n256, DP_OP_110J126_122_4535_n255,
DP_OP_110J126_122_4535_n254, DP_OP_110J126_122_4535_n253,
DP_OP_110J126_122_4535_n252, DP_OP_110J126_122_4535_n249,
DP_OP_110J126_122_4535_n248, DP_OP_110J126_122_4535_n246,
DP_OP_110J126_122_4535_n243, DP_OP_110J126_122_4535_n242,
DP_OP_110J126_122_4535_n241, DP_OP_110J126_122_4535_n240,
DP_OP_110J126_122_4535_n239, DP_OP_110J126_122_4535_n236,
DP_OP_110J126_122_4535_n235, DP_OP_110J126_122_4535_n234,
DP_OP_110J126_122_4535_n232, DP_OP_110J126_122_4535_n231,
DP_OP_110J126_122_4535_n230, DP_OP_110J126_122_4535_n229,
DP_OP_110J126_122_4535_n228, DP_OP_110J126_122_4535_n227,
DP_OP_110J126_122_4535_n226, DP_OP_110J126_122_4535_n225,
DP_OP_110J126_122_4535_n224, DP_OP_110J126_122_4535_n223,
DP_OP_110J126_122_4535_n222, DP_OP_110J126_122_4535_n221,
DP_OP_110J126_122_4535_n220, DP_OP_110J126_122_4535_n219,
DP_OP_110J126_122_4535_n218, DP_OP_110J126_122_4535_n217,
DP_OP_110J126_122_4535_n216, DP_OP_110J126_122_4535_n212,
DP_OP_110J126_122_4535_n211, DP_OP_110J126_122_4535_n210,
DP_OP_110J126_122_4535_n208, DP_OP_110J126_122_4535_n207,
DP_OP_110J126_122_4535_n206, DP_OP_110J126_122_4535_n205,
DP_OP_110J126_122_4535_n204, DP_OP_110J126_122_4535_n202,
DP_OP_110J126_122_4535_n201, DP_OP_110J126_122_4535_n200,
DP_OP_110J126_122_4535_n199, DP_OP_110J126_122_4535_n198,
DP_OP_110J126_122_4535_n196, DP_OP_110J126_122_4535_n195,
DP_OP_110J126_122_4535_n194, DP_OP_110J126_122_4535_n193,
DP_OP_110J126_122_4535_n192, DP_OP_110J126_122_4535_n191,
DP_OP_110J126_122_4535_n190, DP_OP_110J126_122_4535_n189,
DP_OP_110J126_122_4535_n188, DP_OP_110J126_122_4535_n187,
DP_OP_110J126_122_4535_n186, DP_OP_110J126_122_4535_n184,
DP_OP_110J126_122_4535_n183, DP_OP_110J126_122_4535_n182,
DP_OP_110J126_122_4535_n181, DP_OP_110J126_122_4535_n180,
DP_OP_110J126_122_4535_n179, DP_OP_110J126_122_4535_n178,
DP_OP_110J126_122_4535_n176, DP_OP_110J126_122_4535_n175,
DP_OP_110J126_122_4535_n174, DP_OP_110J126_122_4535_n173,
DP_OP_110J126_122_4535_n172, DP_OP_110J126_122_4535_n171,
DP_OP_110J126_122_4535_n169, DP_OP_110J126_122_4535_n168,
DP_OP_110J126_122_4535_n167, DP_OP_110J126_122_4535_n166,
DP_OP_110J126_122_4535_n165, DP_OP_110J126_122_4535_n164,
DP_OP_110J126_122_4535_n163, DP_OP_110J126_122_4535_n162,
DP_OP_110J126_122_4535_n161, DP_OP_110J126_122_4535_n160,
DP_OP_110J126_122_4535_n159, DP_OP_110J126_122_4535_n158,
DP_OP_110J126_122_4535_n157, DP_OP_110J126_122_4535_n156,
DP_OP_110J126_122_4535_n155, DP_OP_110J126_122_4535_n154,
DP_OP_110J126_122_4535_n153, DP_OP_110J126_122_4535_n152,
DP_OP_110J126_122_4535_n151, DP_OP_110J126_122_4535_n149,
DP_OP_110J126_122_4535_n148, DP_OP_110J126_122_4535_n147,
DP_OP_110J126_122_4535_n146, DP_OP_110J126_122_4535_n145,
DP_OP_110J126_122_4535_n144, DP_OP_110J126_122_4535_n143,
DP_OP_110J126_122_4535_n142, DP_OP_110J126_122_4535_n141,
DP_OP_110J126_122_4535_n140, DP_OP_110J126_122_4535_n138,
DP_OP_110J126_122_4535_n137, DP_OP_110J126_122_4535_n136,
DP_OP_110J126_122_4535_n135, DP_OP_110J126_122_4535_n134,
DP_OP_110J126_122_4535_n133, DP_OP_110J126_122_4535_n132,
DP_OP_110J126_122_4535_n131, DP_OP_110J126_122_4535_n130,
DP_OP_110J126_122_4535_n129, DP_OP_110J126_122_4535_n128,
DP_OP_110J126_122_4535_n127, DP_OP_110J126_122_4535_n126,
DP_OP_110J126_122_4535_n125, DP_OP_110J126_122_4535_n124,
DP_OP_110J126_122_4535_n123, DP_OP_110J126_122_4535_n122,
DP_OP_110J126_122_4535_n121, DP_OP_110J126_122_4535_n120,
DP_OP_110J126_122_4535_n119, DP_OP_110J126_122_4535_n118,
DP_OP_110J126_122_4535_n117, DP_OP_110J126_122_4535_n116,
DP_OP_110J126_122_4535_n115, DP_OP_110J126_122_4535_n114,
DP_OP_110J126_122_4535_n113, DP_OP_110J126_122_4535_n112,
DP_OP_110J126_122_4535_n111, DP_OP_110J126_122_4535_n110,
DP_OP_110J126_122_4535_n109, DP_OP_110J126_122_4535_n108,
DP_OP_110J126_122_4535_n107, DP_OP_110J126_122_4535_n106,
DP_OP_110J126_122_4535_n105, DP_OP_110J126_122_4535_n104,
DP_OP_110J126_122_4535_n103, DP_OP_110J126_122_4535_n102,
DP_OP_110J126_122_4535_n101, DP_OP_110J126_122_4535_n100,
DP_OP_110J126_122_4535_n99, DP_OP_110J126_122_4535_n98,
DP_OP_110J126_122_4535_n97, DP_OP_110J126_122_4535_n96,
DP_OP_110J126_122_4535_n95, DP_OP_110J126_122_4535_n94,
DP_OP_110J126_122_4535_n93, DP_OP_110J126_122_4535_n92,
DP_OP_110J126_122_4535_n91, DP_OP_110J126_122_4535_n90,
DP_OP_110J126_122_4535_n89, DP_OP_110J126_122_4535_n88,
DP_OP_110J126_122_4535_n87, DP_OP_110J126_122_4535_n86,
DP_OP_110J126_122_4535_n85, DP_OP_110J126_122_4535_n84,
DP_OP_110J126_122_4535_n83, DP_OP_110J126_122_4535_n82,
DP_OP_110J126_122_4535_n81, DP_OP_110J126_122_4535_n80,
DP_OP_110J126_122_4535_n79, DP_OP_110J126_122_4535_n78,
DP_OP_110J126_122_4535_n77, DP_OP_110J126_122_4535_n76,
DP_OP_110J126_122_4535_n75, DP_OP_110J126_122_4535_n74,
DP_OP_110J126_122_4535_n73, DP_OP_110J126_122_4535_n72,
DP_OP_110J126_122_4535_n71, DP_OP_110J126_122_4535_n70,
DP_OP_110J126_122_4535_n69, DP_OP_110J126_122_4535_n68,
DP_OP_110J126_122_4535_n67, DP_OP_110J126_122_4535_n66,
DP_OP_110J126_122_4535_n65, DP_OP_110J126_122_4535_n64,
DP_OP_110J126_122_4535_n63, DP_OP_110J126_122_4535_n62,
DP_OP_110J126_122_4535_n61, DP_OP_110J126_122_4535_n60,
DP_OP_110J126_122_4535_n59, DP_OP_110J126_122_4535_n58,
DP_OP_110J126_122_4535_n57, DP_OP_110J126_122_4535_n56,
DP_OP_110J126_122_4535_n55, DP_OP_110J126_122_4535_n54,
DP_OP_110J126_122_4535_n53, DP_OP_110J126_122_4535_n52,
DP_OP_110J126_122_4535_n51, DP_OP_110J126_122_4535_n50,
DP_OP_110J126_122_4535_n49, DP_OP_110J126_122_4535_n48,
DP_OP_110J126_122_4535_n47, DP_OP_110J126_122_4535_n46,
DP_OP_110J126_122_4535_n45, DP_OP_110J126_122_4535_n44,
DP_OP_110J126_122_4535_n43, DP_OP_110J126_122_4535_n42,
DP_OP_110J126_122_4535_n41, DP_OP_110J126_122_4535_n40,
DP_OP_110J126_122_4535_n39, DP_OP_110J126_122_4535_n38,
DP_OP_110J126_122_4535_n37, DP_OP_110J126_122_4535_n36,
DP_OP_110J126_122_4535_n35, DP_OP_110J126_122_4535_n34,
DP_OP_110J126_122_4535_n33, DP_OP_110J126_122_4535_n32,
DP_OP_36J126_123_9196_n33, DP_OP_36J126_123_9196_n22,
DP_OP_36J126_123_9196_n21, DP_OP_36J126_123_9196_n20,
DP_OP_36J126_123_9196_n19, DP_OP_36J126_123_9196_n18,
DP_OP_36J126_123_9196_n17, DP_OP_36J126_123_9196_n16,
DP_OP_36J126_123_9196_n15, DP_OP_36J126_123_9196_n9,
DP_OP_36J126_123_9196_n8, DP_OP_36J126_123_9196_n7,
DP_OP_36J126_123_9196_n6, DP_OP_36J126_123_9196_n5,
DP_OP_36J126_123_9196_n4, DP_OP_36J126_123_9196_n3,
DP_OP_36J126_123_9196_n2, DP_OP_36J126_123_9196_n1, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [23:14] Sgf_operation_EVEN1_Q_left;
CMPR42X1TS DP_OP_110J126_122_4535_U800 ( .A(DP_OP_110J126_122_4535_n1106),
.B(DP_OP_110J126_122_4535_n1142), .C(DP_OP_110J126_122_4535_n1130),
.D(DP_OP_110J126_122_4535_n1118), .ICI(DP_OP_110J126_122_4535_n1047),
.S(DP_OP_110J126_122_4535_n1044), .ICO(DP_OP_110J126_122_4535_n1042),
.CO(DP_OP_110J126_122_4535_n1043) );
CMPR42X1TS DP_OP_110J126_122_4535_U798 ( .A(DP_OP_110J126_122_4535_n1129),
.B(DP_OP_110J126_122_4535_n1105), .C(DP_OP_110J126_122_4535_n1117),
.D(DP_OP_110J126_122_4535_n1042), .ICI(DP_OP_110J126_122_4535_n1041),
.S(DP_OP_110J126_122_4535_n1039), .ICO(DP_OP_110J126_122_4535_n1037),
.CO(DP_OP_110J126_122_4535_n1038) );
CMPR42X1TS DP_OP_110J126_122_4535_U796 ( .A(DP_OP_110J126_122_4535_n1116),
.B(DP_OP_110J126_122_4535_n1104), .C(DP_OP_110J126_122_4535_n1040),
.D(DP_OP_110J126_122_4535_n1037), .ICI(DP_OP_110J126_122_4535_n1036),
.S(DP_OP_110J126_122_4535_n1034), .ICO(DP_OP_110J126_122_4535_n1032),
.CO(DP_OP_110J126_122_4535_n1033) );
CMPR42X1TS DP_OP_110J126_122_4535_U793 ( .A(DP_OP_110J126_122_4535_n1115),
.B(DP_OP_110J126_122_4535_n1035), .C(DP_OP_110J126_122_4535_n1031),
.D(DP_OP_110J126_122_4535_n1029), .ICI(DP_OP_110J126_122_4535_n1032),
.S(DP_OP_110J126_122_4535_n1027), .ICO(DP_OP_110J126_122_4535_n1025),
.CO(DP_OP_110J126_122_4535_n1026) );
CMPR42X1TS DP_OP_110J126_122_4535_U792 ( .A(DP_OP_110J126_122_4535_n1078),
.B(DP_OP_110J126_122_4535_n1138), .C(DP_OP_110J126_122_4535_n1126),
.D(DP_OP_110J126_122_4535_n1114), .ICI(DP_OP_110J126_122_4535_n1090),
.S(DP_OP_110J126_122_4535_n1024), .ICO(DP_OP_110J126_122_4535_n1022),
.CO(DP_OP_110J126_122_4535_n1023) );
CMPR42X1TS DP_OP_110J126_122_4535_U791 ( .A(DP_OP_110J126_122_4535_n1102),
.B(DP_OP_110J126_122_4535_n1030), .C(DP_OP_110J126_122_4535_n1028),
.D(DP_OP_110J126_122_4535_n1025), .ICI(DP_OP_110J126_122_4535_n1024),
.S(DP_OP_110J126_122_4535_n1021), .ICO(DP_OP_110J126_122_4535_n1019),
.CO(DP_OP_110J126_122_4535_n1020) );
CMPR42X1TS DP_OP_110J126_122_4535_U789 ( .A(DP_OP_110J126_122_4535_n1125),
.B(DP_OP_110J126_122_4535_n1077), .C(DP_OP_110J126_122_4535_n1113),
.D(DP_OP_110J126_122_4535_n1089), .ICI(DP_OP_110J126_122_4535_n1018),
.S(DP_OP_110J126_122_4535_n1016), .ICO(DP_OP_110J126_122_4535_n1014),
.CO(DP_OP_110J126_122_4535_n1015) );
CMPR42X1TS DP_OP_110J126_122_4535_U788 ( .A(DP_OP_110J126_122_4535_n1101),
.B(DP_OP_110J126_122_4535_n1022), .C(DP_OP_110J126_122_4535_n1019),
.D(DP_OP_110J126_122_4535_n1023), .ICI(DP_OP_110J126_122_4535_n1016),
.S(DP_OP_110J126_122_4535_n1013), .ICO(DP_OP_110J126_122_4535_n1011),
.CO(DP_OP_110J126_122_4535_n1012) );
CMPR42X1TS DP_OP_110J126_122_4535_U786 ( .A(DP_OP_110J126_122_4535_n1112),
.B(DP_OP_110J126_122_4535_n1076), .C(DP_OP_110J126_122_4535_n1100),
.D(DP_OP_110J126_122_4535_n1088), .ICI(DP_OP_110J126_122_4535_n1010),
.S(DP_OP_110J126_122_4535_n1008), .ICO(DP_OP_110J126_122_4535_n1006),
.CO(DP_OP_110J126_122_4535_n1007) );
CMPR42X1TS DP_OP_110J126_122_4535_U785 ( .A(DP_OP_110J126_122_4535_n1017),
.B(DP_OP_110J126_122_4535_n1014), .C(DP_OP_110J126_122_4535_n1015),
.D(DP_OP_110J126_122_4535_n1008), .ICI(DP_OP_110J126_122_4535_n1011),
.S(DP_OP_110J126_122_4535_n1005), .ICO(DP_OP_110J126_122_4535_n1003),
.CO(DP_OP_110J126_122_4535_n1004) );
CMPR42X1TS DP_OP_110J126_122_4535_U782 ( .A(DP_OP_110J126_122_4535_n1099),
.B(DP_OP_110J126_122_4535_n1075), .C(DP_OP_110J126_122_4535_n1123),
.D(n1668), .ICI(DP_OP_110J126_122_4535_n1001), .S(
DP_OP_110J126_122_4535_n999), .ICO(DP_OP_110J126_122_4535_n997), .CO(
DP_OP_110J126_122_4535_n998) );
CMPR42X1TS DP_OP_110J126_122_4535_U781 ( .A(DP_OP_110J126_122_4535_n1006),
.B(DP_OP_110J126_122_4535_n1009), .C(DP_OP_110J126_122_4535_n1007),
.D(DP_OP_110J126_122_4535_n999), .ICI(DP_OP_110J126_122_4535_n1003),
.S(DP_OP_110J126_122_4535_n996), .ICO(DP_OP_110J126_122_4535_n994),
.CO(DP_OP_110J126_122_4535_n995) );
CMPR42X1TS DP_OP_110J126_122_4535_U778 ( .A(DP_OP_110J126_122_4535_n1086),
.B(DP_OP_110J126_122_4535_n1122), .C(DP_OP_110J126_122_4535_n1110),
.D(DP_OP_110J126_122_4535_n1074), .ICI(DP_OP_110J126_122_4535_n1000),
.S(DP_OP_110J126_122_4535_n989), .ICO(DP_OP_110J126_122_4535_n987),
.CO(DP_OP_110J126_122_4535_n988) );
CMPR42X1TS DP_OP_110J126_122_4535_U777 ( .A(DP_OP_110J126_122_4535_n997),
.B(DP_OP_110J126_122_4535_n991), .C(DP_OP_110J126_122_4535_n998), .D(
DP_OP_110J126_122_4535_n989), .ICI(DP_OP_110J126_122_4535_n994), .S(
DP_OP_110J126_122_4535_n986), .ICO(DP_OP_110J126_122_4535_n984), .CO(
DP_OP_110J126_122_4535_n985) );
CMPR42X1TS DP_OP_110J126_122_4535_U775 ( .A(DP_OP_110J126_122_4535_n1085),
.B(DP_OP_110J126_122_4535_n1073), .C(DP_OP_110J126_122_4535_n1109),
.D(DP_OP_110J126_122_4535_n1121), .ICI(DP_OP_110J126_122_4535_n983),
.S(DP_OP_110J126_122_4535_n981), .ICO(DP_OP_110J126_122_4535_n979),
.CO(DP_OP_110J126_122_4535_n980) );
CMPR42X1TS DP_OP_110J126_122_4535_U774 ( .A(DP_OP_110J126_122_4535_n987),
.B(DP_OP_110J126_122_4535_n990), .C(DP_OP_110J126_122_4535_n988), .D(
DP_OP_110J126_122_4535_n981), .ICI(DP_OP_110J126_122_4535_n984), .S(
DP_OP_110J126_122_4535_n978), .ICO(DP_OP_110J126_122_4535_n976), .CO(
DP_OP_110J126_122_4535_n977) );
CMPR42X1TS DP_OP_110J126_122_4535_U772 ( .A(n1685), .B(
DP_OP_110J126_122_4535_n1084), .C(DP_OP_110J126_122_4535_n1096), .D(
DP_OP_110J126_122_4535_n1072), .ICI(DP_OP_110J126_122_4535_n1108), .S(
DP_OP_110J126_122_4535_n973), .ICO(DP_OP_110J126_122_4535_n971), .CO(
DP_OP_110J126_122_4535_n972) );
CMPR42X1TS DP_OP_110J126_122_4535_U771 ( .A(DP_OP_110J126_122_4535_n979),
.B(DP_OP_110J126_122_4535_n982), .C(DP_OP_110J126_122_4535_n980), .D(
DP_OP_110J126_122_4535_n973), .ICI(DP_OP_110J126_122_4535_n976), .S(
DP_OP_110J126_122_4535_n970), .ICO(DP_OP_110J126_122_4535_n968), .CO(
DP_OP_110J126_122_4535_n969) );
CMPR42X1TS DP_OP_110J126_122_4535_U770 ( .A(n644), .B(Op_MY[17]), .C(
DP_OP_110J126_122_4535_n1095), .D(DP_OP_110J126_122_4535_n1083), .ICI(
DP_OP_110J126_122_4535_n1071), .S(DP_OP_110J126_122_4535_n967), .ICO(
DP_OP_110J126_122_4535_n965), .CO(DP_OP_110J126_122_4535_n966) );
CMPR42X1TS DP_OP_110J126_122_4535_U769 ( .A(DP_OP_110J126_122_4535_n1107),
.B(DP_OP_110J126_122_4535_n971), .C(DP_OP_110J126_122_4535_n972), .D(
DP_OP_110J126_122_4535_n967), .ICI(DP_OP_110J126_122_4535_n968), .S(
DP_OP_110J126_122_4535_n964), .ICO(DP_OP_110J126_122_4535_n962), .CO(
DP_OP_110J126_122_4535_n963) );
CMPR42X1TS DP_OP_110J126_122_4535_U766 ( .A(DP_OP_110J126_122_4535_n1070),
.B(DP_OP_110J126_122_4535_n965), .C(DP_OP_110J126_122_4535_n959), .D(
DP_OP_110J126_122_4535_n966), .ICI(DP_OP_110J126_122_4535_n962), .S(
DP_OP_110J126_122_4535_n957), .ICO(DP_OP_110J126_122_4535_n955), .CO(
DP_OP_110J126_122_4535_n956) );
CMPR42X1TS DP_OP_110J126_122_4535_U764 ( .A(DP_OP_110J126_122_4535_n1069),
.B(DP_OP_110J126_122_4535_n1093), .C(DP_OP_110J126_122_4535_n954), .D(
DP_OP_110J126_122_4535_n958), .ICI(DP_OP_110J126_122_4535_n955), .S(
DP_OP_110J126_122_4535_n952), .ICO(DP_OP_110J126_122_4535_n950), .CO(
DP_OP_110J126_122_4535_n951) );
CMPR42X1TS DP_OP_110J126_122_4535_U762 ( .A(n1684), .B(
DP_OP_110J126_122_4535_n1080), .C(DP_OP_110J126_122_4535_n1068), .D(
DP_OP_110J126_122_4535_n953), .ICI(DP_OP_110J126_122_4535_n950), .S(
DP_OP_110J126_122_4535_n947), .ICO(DP_OP_110J126_122_4535_n945), .CO(
DP_OP_110J126_122_4535_n946) );
CMPR42X1TS DP_OP_110J126_122_4535_U761 ( .A(n643), .B(Op_MY[21]), .C(
DP_OP_110J126_122_4535_n1067), .D(DP_OP_110J126_122_4535_n1079), .ICI(
DP_OP_110J126_122_4535_n945), .S(DP_OP_110J126_122_4535_n944), .ICO(
DP_OP_110J126_122_4535_n942), .CO(DP_OP_110J126_122_4535_n943) );
CMPR42X1TS DP_OP_110J126_122_4535_U481 ( .A(DP_OP_110J126_122_4535_n725),
.B(DP_OP_110J126_122_4535_n761), .C(DP_OP_110J126_122_4535_n749), .D(
DP_OP_110J126_122_4535_n737), .ICI(DP_OP_110J126_122_4535_n665), .S(
DP_OP_110J126_122_4535_n662), .ICO(DP_OP_110J126_122_4535_n660), .CO(
DP_OP_110J126_122_4535_n661) );
CMPR42X1TS DP_OP_110J126_122_4535_U479 ( .A(DP_OP_110J126_122_4535_n748),
.B(DP_OP_110J126_122_4535_n724), .C(DP_OP_110J126_122_4535_n736), .D(
DP_OP_110J126_122_4535_n660), .ICI(DP_OP_110J126_122_4535_n659), .S(
DP_OP_110J126_122_4535_n657), .ICO(DP_OP_110J126_122_4535_n655), .CO(
DP_OP_110J126_122_4535_n656) );
CMPR42X1TS DP_OP_110J126_122_4535_U477 ( .A(DP_OP_110J126_122_4535_n735),
.B(DP_OP_110J126_122_4535_n723), .C(DP_OP_110J126_122_4535_n658), .D(
DP_OP_110J126_122_4535_n655), .ICI(DP_OP_110J126_122_4535_n654), .S(
DP_OP_110J126_122_4535_n652), .ICO(DP_OP_110J126_122_4535_n650), .CO(
DP_OP_110J126_122_4535_n651) );
CMPR42X1TS DP_OP_110J126_122_4535_U474 ( .A(DP_OP_110J126_122_4535_n734),
.B(DP_OP_110J126_122_4535_n653), .C(DP_OP_110J126_122_4535_n649), .D(
DP_OP_110J126_122_4535_n647), .ICI(DP_OP_110J126_122_4535_n650), .S(
DP_OP_110J126_122_4535_n645), .ICO(DP_OP_110J126_122_4535_n643), .CO(
DP_OP_110J126_122_4535_n644) );
CMPR42X1TS DP_OP_110J126_122_4535_U473 ( .A(DP_OP_110J126_122_4535_n697),
.B(DP_OP_110J126_122_4535_n757), .C(DP_OP_110J126_122_4535_n745), .D(
DP_OP_110J126_122_4535_n733), .ICI(DP_OP_110J126_122_4535_n709), .S(
DP_OP_110J126_122_4535_n642), .ICO(DP_OP_110J126_122_4535_n640), .CO(
DP_OP_110J126_122_4535_n641) );
CMPR42X1TS DP_OP_110J126_122_4535_U472 ( .A(DP_OP_110J126_122_4535_n721),
.B(DP_OP_110J126_122_4535_n648), .C(DP_OP_110J126_122_4535_n646), .D(
DP_OP_110J126_122_4535_n643), .ICI(DP_OP_110J126_122_4535_n642), .S(
DP_OP_110J126_122_4535_n639), .ICO(DP_OP_110J126_122_4535_n637), .CO(
DP_OP_110J126_122_4535_n638) );
CMPR42X1TS DP_OP_110J126_122_4535_U470 ( .A(DP_OP_110J126_122_4535_n744),
.B(DP_OP_110J126_122_4535_n696), .C(DP_OP_110J126_122_4535_n732), .D(
DP_OP_110J126_122_4535_n708), .ICI(DP_OP_110J126_122_4535_n636), .S(
DP_OP_110J126_122_4535_n634), .ICO(DP_OP_110J126_122_4535_n632), .CO(
DP_OP_110J126_122_4535_n633) );
CMPR42X1TS DP_OP_110J126_122_4535_U469 ( .A(DP_OP_110J126_122_4535_n720),
.B(DP_OP_110J126_122_4535_n640), .C(DP_OP_110J126_122_4535_n637), .D(
DP_OP_110J126_122_4535_n641), .ICI(DP_OP_110J126_122_4535_n634), .S(
DP_OP_110J126_122_4535_n631), .ICO(DP_OP_110J126_122_4535_n629), .CO(
DP_OP_110J126_122_4535_n630) );
CMPR42X1TS DP_OP_110J126_122_4535_U467 ( .A(DP_OP_110J126_122_4535_n731),
.B(DP_OP_110J126_122_4535_n695), .C(DP_OP_110J126_122_4535_n719), .D(
DP_OP_110J126_122_4535_n707), .ICI(DP_OP_110J126_122_4535_n628), .S(
DP_OP_110J126_122_4535_n626), .ICO(DP_OP_110J126_122_4535_n624), .CO(
DP_OP_110J126_122_4535_n625) );
CMPR42X1TS DP_OP_110J126_122_4535_U466 ( .A(DP_OP_110J126_122_4535_n635),
.B(DP_OP_110J126_122_4535_n632), .C(DP_OP_110J126_122_4535_n633), .D(
DP_OP_110J126_122_4535_n626), .ICI(DP_OP_110J126_122_4535_n629), .S(
DP_OP_110J126_122_4535_n623), .ICO(DP_OP_110J126_122_4535_n621), .CO(
DP_OP_110J126_122_4535_n622) );
CMPR42X1TS DP_OP_110J126_122_4535_U463 ( .A(DP_OP_110J126_122_4535_n718),
.B(DP_OP_110J126_122_4535_n694), .C(DP_OP_110J126_122_4535_n742), .D(
n1669), .ICI(DP_OP_110J126_122_4535_n619), .S(
DP_OP_110J126_122_4535_n617), .ICO(DP_OP_110J126_122_4535_n615), .CO(
DP_OP_110J126_122_4535_n616) );
CMPR42X1TS DP_OP_110J126_122_4535_U462 ( .A(DP_OP_110J126_122_4535_n624),
.B(DP_OP_110J126_122_4535_n627), .C(DP_OP_110J126_122_4535_n625), .D(
DP_OP_110J126_122_4535_n617), .ICI(DP_OP_110J126_122_4535_n621), .S(
DP_OP_110J126_122_4535_n614), .ICO(DP_OP_110J126_122_4535_n612), .CO(
DP_OP_110J126_122_4535_n613) );
CMPR42X1TS DP_OP_110J126_122_4535_U459 ( .A(DP_OP_110J126_122_4535_n705),
.B(DP_OP_110J126_122_4535_n741), .C(DP_OP_110J126_122_4535_n729), .D(
DP_OP_110J126_122_4535_n693), .ICI(DP_OP_110J126_122_4535_n618), .S(
DP_OP_110J126_122_4535_n607), .ICO(DP_OP_110J126_122_4535_n605), .CO(
DP_OP_110J126_122_4535_n606) );
CMPR42X1TS DP_OP_110J126_122_4535_U458 ( .A(DP_OP_110J126_122_4535_n615),
.B(DP_OP_110J126_122_4535_n609), .C(DP_OP_110J126_122_4535_n616), .D(
DP_OP_110J126_122_4535_n607), .ICI(DP_OP_110J126_122_4535_n612), .S(
DP_OP_110J126_122_4535_n604), .ICO(DP_OP_110J126_122_4535_n602), .CO(
DP_OP_110J126_122_4535_n603) );
CMPR42X1TS DP_OP_110J126_122_4535_U456 ( .A(DP_OP_110J126_122_4535_n704),
.B(DP_OP_110J126_122_4535_n692), .C(DP_OP_110J126_122_4535_n728), .D(
DP_OP_110J126_122_4535_n740), .ICI(DP_OP_110J126_122_4535_n601), .S(
DP_OP_110J126_122_4535_n599), .ICO(DP_OP_110J126_122_4535_n597), .CO(
DP_OP_110J126_122_4535_n598) );
CMPR42X1TS DP_OP_110J126_122_4535_U455 ( .A(DP_OP_110J126_122_4535_n605),
.B(DP_OP_110J126_122_4535_n608), .C(DP_OP_110J126_122_4535_n606), .D(
DP_OP_110J126_122_4535_n599), .ICI(DP_OP_110J126_122_4535_n602), .S(
DP_OP_110J126_122_4535_n596), .ICO(DP_OP_110J126_122_4535_n594), .CO(
DP_OP_110J126_122_4535_n595) );
CMPR42X1TS DP_OP_110J126_122_4535_U453 ( .A(DP_OP_110J126_122_4535_n593),
.B(DP_OP_110J126_122_4535_n703), .C(DP_OP_110J126_122_4535_n715), .D(
DP_OP_110J126_122_4535_n691), .ICI(DP_OP_110J126_122_4535_n727), .S(
DP_OP_110J126_122_4535_n591), .ICO(DP_OP_110J126_122_4535_n589), .CO(
DP_OP_110J126_122_4535_n590) );
CMPR42X1TS DP_OP_110J126_122_4535_U452 ( .A(DP_OP_110J126_122_4535_n597),
.B(DP_OP_110J126_122_4535_n600), .C(DP_OP_110J126_122_4535_n598), .D(
DP_OP_110J126_122_4535_n591), .ICI(DP_OP_110J126_122_4535_n594), .S(
DP_OP_110J126_122_4535_n588), .ICO(DP_OP_110J126_122_4535_n586), .CO(
DP_OP_110J126_122_4535_n587) );
CMPR42X1TS DP_OP_110J126_122_4535_U451 ( .A(DP_OP_110J126_122_4535_n592),
.B(DP_OP_110J126_122_4535_n680), .C(DP_OP_110J126_122_4535_n714), .D(
DP_OP_110J126_122_4535_n702), .ICI(DP_OP_110J126_122_4535_n690), .S(
DP_OP_110J126_122_4535_n585), .ICO(DP_OP_110J126_122_4535_n583), .CO(
DP_OP_110J126_122_4535_n584) );
CMPR42X1TS DP_OP_110J126_122_4535_U450 ( .A(DP_OP_110J126_122_4535_n726),
.B(DP_OP_110J126_122_4535_n589), .C(DP_OP_110J126_122_4535_n590), .D(
DP_OP_110J126_122_4535_n585), .ICI(DP_OP_110J126_122_4535_n586), .S(
DP_OP_110J126_122_4535_n582), .ICO(DP_OP_110J126_122_4535_n580), .CO(
DP_OP_110J126_122_4535_n581) );
CMPR42X1TS DP_OP_110J126_122_4535_U447 ( .A(DP_OP_110J126_122_4535_n689),
.B(DP_OP_110J126_122_4535_n583), .C(DP_OP_110J126_122_4535_n577), .D(
DP_OP_110J126_122_4535_n584), .ICI(DP_OP_110J126_122_4535_n580), .S(
DP_OP_110J126_122_4535_n575), .ICO(DP_OP_110J126_122_4535_n573), .CO(
DP_OP_110J126_122_4535_n574) );
CMPR42X1TS DP_OP_110J126_122_4535_U445 ( .A(DP_OP_110J126_122_4535_n688),
.B(DP_OP_110J126_122_4535_n712), .C(DP_OP_110J126_122_4535_n572), .D(
DP_OP_110J126_122_4535_n576), .ICI(DP_OP_110J126_122_4535_n573), .S(
DP_OP_110J126_122_4535_n570), .ICO(DP_OP_110J126_122_4535_n568), .CO(
DP_OP_110J126_122_4535_n569) );
CMPR42X1TS DP_OP_110J126_122_4535_U443 ( .A(DP_OP_110J126_122_4535_n567),
.B(DP_OP_110J126_122_4535_n699), .C(DP_OP_110J126_122_4535_n687), .D(
DP_OP_110J126_122_4535_n571), .ICI(DP_OP_110J126_122_4535_n568), .S(
DP_OP_110J126_122_4535_n565), .ICO(DP_OP_110J126_122_4535_n563), .CO(
DP_OP_110J126_122_4535_n564) );
CMPR42X1TS DP_OP_110J126_122_4535_U442 ( .A(DP_OP_110J126_122_4535_n566),
.B(DP_OP_110J126_122_4535_n678), .C(DP_OP_110J126_122_4535_n686), .D(
DP_OP_110J126_122_4535_n698), .ICI(DP_OP_110J126_122_4535_n563), .S(
DP_OP_110J126_122_4535_n562), .ICO(DP_OP_110J126_122_4535_n560), .CO(
DP_OP_110J126_122_4535_n561) );
CMPR42X1TS DP_OP_110J126_122_4535_U98 ( .A(DP_OP_110J126_122_4535_n528), .B(
DP_OP_110J126_122_4535_n346), .C(DP_OP_110J126_122_4535_n527), .D(
DP_OP_110J126_122_4535_n236), .ICI(DP_OP_110J126_122_4535_n333), .S(
DP_OP_110J126_122_4535_n212), .ICO(DP_OP_110J126_122_4535_n210), .CO(
DP_OP_110J126_122_4535_n211) );
CMPR42X1TS DP_OP_110J126_122_4535_U96 ( .A(DP_OP_110J126_122_4535_n345), .B(
DP_OP_110J126_122_4535_n235), .C(DP_OP_110J126_122_4535_n332), .D(
DP_OP_110J126_122_4535_n243), .ICI(DP_OP_110J126_122_4535_n211), .S(
DP_OP_110J126_122_4535_n207), .ICO(DP_OP_110J126_122_4535_n205), .CO(
DP_OP_110J126_122_4535_n206) );
CMPR42X1TS DP_OP_110J126_122_4535_U94 ( .A(DP_OP_110J126_122_4535_n208), .B(
DP_OP_110J126_122_4535_n234), .C(DP_OP_110J126_122_4535_n525), .D(
DP_OP_110J126_122_4535_n205), .ICI(DP_OP_110J126_122_4535_n204), .S(
DP_OP_110J126_122_4535_n202), .ICO(DP_OP_110J126_122_4535_n200), .CO(
DP_OP_110J126_122_4535_n201) );
CMPR42X1TS DP_OP_110J126_122_4535_U91 ( .A(DP_OP_110J126_122_4535_n524), .B(
DP_OP_110J126_122_4535_n242), .C(DP_OP_110J126_122_4535_n317), .D(
DP_OP_110J126_122_4535_n199), .ICI(DP_OP_110J126_122_4535_n201), .S(
DP_OP_110J126_122_4535_n195), .ICO(DP_OP_110J126_122_4535_n193), .CO(
DP_OP_110J126_122_4535_n194) );
CMPR42X1TS DP_OP_110J126_122_4535_U90 ( .A(DP_OP_110J126_122_4535_n329), .B(
DP_OP_110J126_122_4535_n316), .C(DP_OP_110J126_122_4535_n198), .D(
DP_OP_110J126_122_4535_n342), .ICI(DP_OP_110J126_122_4535_n523), .S(
DP_OP_110J126_122_4535_n192), .ICO(DP_OP_110J126_122_4535_n190), .CO(
DP_OP_110J126_122_4535_n191) );
CMPR42X1TS DP_OP_110J126_122_4535_U89 ( .A(DP_OP_110J126_122_4535_n232), .B(
DP_OP_110J126_122_4535_n303), .C(DP_OP_110J126_122_4535_n196), .D(
DP_OP_110J126_122_4535_n193), .ICI(DP_OP_110J126_122_4535_n194), .S(
DP_OP_110J126_122_4535_n189), .ICO(DP_OP_110J126_122_4535_n187), .CO(
DP_OP_110J126_122_4535_n188) );
CMPR42X1TS DP_OP_110J126_122_4535_U87 ( .A(DP_OP_110J126_122_4535_n190), .B(
DP_OP_110J126_122_4535_n341), .C(DP_OP_110J126_122_4535_n231), .D(
DP_OP_110J126_122_4535_n187), .ICI(DP_OP_110J126_122_4535_n191), .S(
DP_OP_110J126_122_4535_n184), .ICO(DP_OP_110J126_122_4535_n182), .CO(
DP_OP_110J126_122_4535_n183) );
CMPR42X1TS DP_OP_110J126_122_4535_U86 ( .A(DP_OP_110J126_122_4535_n186), .B(
DP_OP_110J126_122_4535_n522), .C(DP_OP_110J126_122_4535_n302), .D(
DP_OP_110J126_122_4535_n241), .ICI(DP_OP_110J126_122_4535_n188), .S(
DP_OP_110J126_122_4535_n181), .ICO(DP_OP_110J126_122_4535_n179), .CO(
DP_OP_110J126_122_4535_n180) );
CMPR42X1TS DP_OP_110J126_122_4535_U84 ( .A(DP_OP_110J126_122_4535_n301), .B(
DP_OP_110J126_122_4535_n178), .C(DP_OP_110J126_122_4535_n340), .D(
DP_OP_110J126_122_4535_n288), .ICI(DP_OP_110J126_122_4535_n179), .S(
DP_OP_110J126_122_4535_n176), .ICO(DP_OP_110J126_122_4535_n174), .CO(
DP_OP_110J126_122_4535_n175) );
CMPR42X1TS DP_OP_110J126_122_4535_U83 ( .A(DP_OP_110J126_122_4535_n182), .B(
DP_OP_110J126_122_4535_n230), .C(DP_OP_110J126_122_4535_n521), .D(
DP_OP_110J126_122_4535_n183), .ICI(DP_OP_110J126_122_4535_n180), .S(
DP_OP_110J126_122_4535_n173), .ICO(DP_OP_110J126_122_4535_n171), .CO(
DP_OP_110J126_122_4535_n172) );
CMPR42X1TS DP_OP_110J126_122_4535_U80 ( .A(DP_OP_110J126_122_4535_n174), .B(
DP_OP_110J126_122_4535_n339), .C(DP_OP_110J126_122_4535_n229), .D(
DP_OP_110J126_122_4535_n520), .ICI(DP_OP_110J126_122_4535_n175), .S(
DP_OP_110J126_122_4535_n166), .ICO(DP_OP_110J126_122_4535_n164), .CO(
DP_OP_110J126_122_4535_n165) );
CMPR42X1TS DP_OP_110J126_122_4535_U79 ( .A(DP_OP_110J126_122_4535_n171), .B(
DP_OP_110J126_122_4535_n168), .C(DP_OP_110J126_122_4535_n287), .D(
DP_OP_110J126_122_4535_n240), .ICI(DP_OP_110J126_122_4535_n172), .S(
DP_OP_110J126_122_4535_n163), .ICO(DP_OP_110J126_122_4535_n161), .CO(
DP_OP_110J126_122_4535_n162) );
CMPR42X1TS DP_OP_110J126_122_4535_U78 ( .A(DP_OP_110J126_122_4535_n312), .B(
DP_OP_110J126_122_4535_n299), .C(DP_OP_110J126_122_4535_n169), .D(
DP_OP_110J126_122_4535_n325), .ICI(DP_OP_110J126_122_4535_n167), .S(
DP_OP_110J126_122_4535_n160), .ICO(DP_OP_110J126_122_4535_n158), .CO(
DP_OP_110J126_122_4535_n159) );
CMPR42X1TS DP_OP_110J126_122_4535_U77 ( .A(DP_OP_110J126_122_4535_n286), .B(
DP_OP_110J126_122_4535_n164), .C(DP_OP_110J126_122_4535_n338), .D(
DP_OP_110J126_122_4535_n273), .ICI(DP_OP_110J126_122_4535_n161), .S(
DP_OP_110J126_122_4535_n157), .ICO(DP_OP_110J126_122_4535_n155), .CO(
DP_OP_110J126_122_4535_n156) );
CMPR42X1TS DP_OP_110J126_122_4535_U76 ( .A(DP_OP_110J126_122_4535_n228), .B(
DP_OP_110J126_122_4535_n519), .C(DP_OP_110J126_122_4535_n160), .D(
DP_OP_110J126_122_4535_n165), .ICI(DP_OP_110J126_122_4535_n162), .S(
DP_OP_110J126_122_4535_n154), .ICO(DP_OP_110J126_122_4535_n152), .CO(
DP_OP_110J126_122_4535_n153) );
CMPR42X1TS DP_OP_110J126_122_4535_U74 ( .A(DP_OP_110J126_122_4535_n158), .B(
DP_OP_110J126_122_4535_n324), .C(DP_OP_110J126_122_4535_n151), .D(
DP_OP_110J126_122_4535_n285), .ICI(DP_OP_110J126_122_4535_n159), .S(
DP_OP_110J126_122_4535_n149), .ICO(DP_OP_110J126_122_4535_n147), .CO(
DP_OP_110J126_122_4535_n148) );
CMPR42X1TS DP_OP_110J126_122_4535_U73 ( .A(DP_OP_110J126_122_4535_n155), .B(
DP_OP_110J126_122_4535_n227), .C(DP_OP_110J126_122_4535_n518), .D(
DP_OP_110J126_122_4535_n152), .ICI(DP_OP_110J126_122_4535_n156), .S(
DP_OP_110J126_122_4535_n146), .ICO(DP_OP_110J126_122_4535_n144), .CO(
DP_OP_110J126_122_4535_n145) );
CMPR42X1TS DP_OP_110J126_122_4535_U72 ( .A(DP_OP_110J126_122_4535_n149), .B(
DP_OP_110J126_122_4535_n337), .C(DP_OP_110J126_122_4535_n272), .D(
DP_OP_110J126_122_4535_n239), .ICI(DP_OP_110J126_122_4535_n153), .S(
DP_OP_110J126_122_4535_n143), .ICO(DP_OP_110J126_122_4535_n141), .CO(
DP_OP_110J126_122_4535_n142) );
CMPR42X1TS DP_OP_110J126_122_4535_U70 ( .A(DP_OP_110J126_122_4535_n284), .B(
DP_OP_110J126_122_4535_n140), .C(DP_OP_110J126_122_4535_n147), .D(
DP_OP_110J126_122_4535_n323), .ICI(DP_OP_110J126_122_4535_n148), .S(
DP_OP_110J126_122_4535_n138), .ICO(DP_OP_110J126_122_4535_n136), .CO(
DP_OP_110J126_122_4535_n137) );
CMPR42X1TS DP_OP_110J126_122_4535_U69 ( .A(DP_OP_110J126_122_4535_n336), .B(
DP_OP_110J126_122_4535_n258), .C(DP_OP_110J126_122_4535_n226), .D(
DP_OP_110J126_122_4535_n517), .ICI(DP_OP_110J126_122_4535_n138), .S(
DP_OP_110J126_122_4535_n135), .ICO(DP_OP_110J126_122_4535_n133), .CO(
DP_OP_110J126_122_4535_n134) );
CMPR42X1TS DP_OP_110J126_122_4535_U68 ( .A(DP_OP_110J126_122_4535_n144), .B(
DP_OP_110J126_122_4535_n271), .C(DP_OP_110J126_122_4535_n145), .D(
DP_OP_110J126_122_4535_n141), .ICI(DP_OP_110J126_122_4535_n135), .S(
DP_OP_110J126_122_4535_n132), .ICO(DP_OP_110J126_122_4535_n130), .CO(
DP_OP_110J126_122_4535_n131) );
CMPR42X1TS DP_OP_110J126_122_4535_U66 ( .A(DP_OP_110J126_122_4535_n283), .B(
DP_OP_110J126_122_4535_n335), .C(DP_OP_110J126_122_4535_n129), .D(
DP_OP_110J126_122_4535_n136), .ICI(DP_OP_110J126_122_4535_n322), .S(
DP_OP_110J126_122_4535_n127), .ICO(DP_OP_110J126_122_4535_n125), .CO(
DP_OP_110J126_122_4535_n126) );
CMPR42X1TS DP_OP_110J126_122_4535_U65 ( .A(DP_OP_110J126_122_4535_n137), .B(
DP_OP_110J126_122_4535_n257), .C(DP_OP_110J126_122_4535_n270), .D(
DP_OP_110J126_122_4535_n133), .ICI(DP_OP_110J126_122_4535_n127), .S(
DP_OP_110J126_122_4535_n124), .ICO(DP_OP_110J126_122_4535_n122), .CO(
DP_OP_110J126_122_4535_n123) );
CMPR42X1TS DP_OP_110J126_122_4535_U64 ( .A(DP_OP_110J126_122_4535_n516), .B(
DP_OP_110J126_122_4535_n225), .C(DP_OP_110J126_122_4535_n130), .D(
DP_OP_110J126_122_4535_n134), .ICI(DP_OP_110J126_122_4535_n124), .S(
DP_OP_110J126_122_4535_n121), .ICO(DP_OP_110J126_122_4535_n119), .CO(
DP_OP_110J126_122_4535_n120) );
CMPR42X1TS DP_OP_110J126_122_4535_U62 ( .A(DP_OP_110J126_122_4535_n308), .B(
DP_OP_110J126_122_4535_n128), .C(DP_OP_110J126_122_4535_n118), .D(
DP_OP_110J126_122_4535_n125), .ICI(DP_OP_110J126_122_4535_n321), .S(
DP_OP_110J126_122_4535_n116), .ICO(DP_OP_110J126_122_4535_n114), .CO(
DP_OP_110J126_122_4535_n115) );
CMPR42X1TS DP_OP_110J126_122_4535_U61 ( .A(DP_OP_110J126_122_4535_n256), .B(
DP_OP_110J126_122_4535_n269), .C(DP_OP_110J126_122_4535_n126), .D(
DP_OP_110J126_122_4535_n122), .ICI(Sgf_operation_EVEN1_Q_left[14]),
.S(DP_OP_110J126_122_4535_n113), .ICO(DP_OP_110J126_122_4535_n111),
.CO(DP_OP_110J126_122_4535_n112) );
CMPR42X1TS DP_OP_110J126_122_4535_U60 ( .A(DP_OP_110J126_122_4535_n116), .B(
DP_OP_110J126_122_4535_n224), .C(DP_OP_110J126_122_4535_n123), .D(
DP_OP_110J126_122_4535_n119), .ICI(DP_OP_110J126_122_4535_n113), .S(
DP_OP_110J126_122_4535_n110), .ICO(DP_OP_110J126_122_4535_n108), .CO(
DP_OP_110J126_122_4535_n109) );
CMPR42X1TS DP_OP_110J126_122_4535_U58 ( .A(DP_OP_110J126_122_4535_n117), .B(
DP_OP_110J126_122_4535_n114), .C(DP_OP_110J126_122_4535_n107), .D(
DP_OP_110J126_122_4535_n307), .ICI(DP_OP_110J126_122_4535_n255), .S(
DP_OP_110J126_122_4535_n105), .ICO(DP_OP_110J126_122_4535_n103), .CO(
DP_OP_110J126_122_4535_n104) );
CMPR42X1TS DP_OP_110J126_122_4535_U57 ( .A(DP_OP_110J126_122_4535_n268), .B(
DP_OP_110J126_122_4535_n115), .C(DP_OP_110J126_122_4535_n111), .D(
DP_OP_110J126_122_4535_n515), .ICI(DP_OP_110J126_122_4535_n105), .S(
DP_OP_110J126_122_4535_n102), .ICO(DP_OP_110J126_122_4535_n100), .CO(
DP_OP_110J126_122_4535_n101) );
CMPR42X1TS DP_OP_110J126_122_4535_U56 ( .A(Sgf_operation_EVEN1_Q_left[15]),
.B(DP_OP_110J126_122_4535_n223), .C(DP_OP_110J126_122_4535_n112), .D(
DP_OP_110J126_122_4535_n108), .ICI(DP_OP_110J126_122_4535_n102), .S(
DP_OP_110J126_122_4535_n99), .ICO(DP_OP_110J126_122_4535_n97), .CO(
DP_OP_110J126_122_4535_n98) );
CMPR42X1TS DP_OP_110J126_122_4535_U54 ( .A(DP_OP_110J126_122_4535_n96), .B(
DP_OP_110J126_122_4535_n106), .C(DP_OP_110J126_122_4535_n306), .D(
DP_OP_110J126_122_4535_n254), .ICI(DP_OP_110J126_122_4535_n267), .S(
DP_OP_110J126_122_4535_n94), .ICO(DP_OP_110J126_122_4535_n92), .CO(
DP_OP_110J126_122_4535_n93) );
CMPR42X1TS DP_OP_110J126_122_4535_U53 ( .A(DP_OP_110J126_122_4535_n103), .B(
DP_OP_110J126_122_4535_n104), .C(DP_OP_110J126_122_4535_n100), .D(
DP_OP_110J126_122_4535_n94), .ICI(DP_OP_110J126_122_4535_n514), .S(
DP_OP_110J126_122_4535_n91), .ICO(DP_OP_110J126_122_4535_n89), .CO(
DP_OP_110J126_122_4535_n90) );
CMPR42X1TS DP_OP_110J126_122_4535_U52 ( .A(DP_OP_110J126_122_4535_n101), .B(
DP_OP_110J126_122_4535_n513), .C(DP_OP_110J126_122_4535_n222), .D(
DP_OP_110J126_122_4535_n97), .ICI(DP_OP_110J126_122_4535_n91), .S(
DP_OP_110J126_122_4535_n88), .ICO(DP_OP_110J126_122_4535_n86), .CO(
DP_OP_110J126_122_4535_n87) );
CMPR42X1TS DP_OP_110J126_122_4535_U51 ( .A(DP_OP_110J126_122_4535_n279), .B(
DP_OP_110J126_122_4535_n305), .C(DP_OP_110J126_122_4535_n95), .D(
DP_OP_110J126_122_4535_n292), .ICI(DP_OP_110J126_122_4535_n253), .S(
DP_OP_110J126_122_4535_n85), .ICO(DP_OP_110J126_122_4535_n83), .CO(
DP_OP_110J126_122_4535_n84) );
CMPR42X1TS DP_OP_110J126_122_4535_U50 ( .A(DP_OP_110J126_122_4535_n266), .B(
DP_OP_110J126_122_4535_n92), .C(DP_OP_110J126_122_4535_n85), .D(
DP_OP_110J126_122_4535_n93), .ICI(DP_OP_110J126_122_4535_n89), .S(
DP_OP_110J126_122_4535_n82), .ICO(DP_OP_110J126_122_4535_n80), .CO(
DP_OP_110J126_122_4535_n81) );
CMPR42X1TS DP_OP_110J126_122_4535_U49 ( .A(DP_OP_110J126_122_4535_n90), .B(
DP_OP_110J126_122_4535_n82), .C(Sgf_operation_EVEN1_Q_left[17]), .D(
DP_OP_110J126_122_4535_n86), .ICI(DP_OP_110J126_122_4535_n221), .S(
DP_OP_110J126_122_4535_n79), .ICO(DP_OP_110J126_122_4535_n77), .CO(
DP_OP_110J126_122_4535_n78) );
CMPR42X1TS DP_OP_110J126_122_4535_U48 ( .A(DP_OP_110J126_122_4535_n304), .B(
DP_OP_110J126_122_4535_n278), .C(DP_OP_110J126_122_4535_n291), .D(
DP_OP_110J126_122_4535_n83), .ICI(DP_OP_110J126_122_4535_n252), .S(
DP_OP_110J126_122_4535_n76), .ICO(DP_OP_110J126_122_4535_n74), .CO(
DP_OP_110J126_122_4535_n75) );
CMPR42X1TS DP_OP_110J126_122_4535_U47 ( .A(DP_OP_110J126_122_4535_n265), .B(
DP_OP_110J126_122_4535_n84), .C(DP_OP_110J126_122_4535_n76), .D(
DP_OP_110J126_122_4535_n80), .ICI(DP_OP_110J126_122_4535_n81), .S(
DP_OP_110J126_122_4535_n73), .ICO(DP_OP_110J126_122_4535_n71), .CO(
DP_OP_110J126_122_4535_n72) );
CMPR42X1TS DP_OP_110J126_122_4535_U46 ( .A(DP_OP_110J126_122_4535_n512), .B(
DP_OP_110J126_122_4535_n73), .C(DP_OP_110J126_122_4535_n77), .D(
DP_OP_110J126_122_4535_n511), .ICI(DP_OP_110J126_122_4535_n220), .S(
DP_OP_110J126_122_4535_n70), .ICO(DP_OP_110J126_122_4535_n68), .CO(
DP_OP_110J126_122_4535_n69) );
CMPR42X1TS DP_OP_110J126_122_4535_U44 ( .A(DP_OP_110J126_122_4535_n264), .B(
DP_OP_110J126_122_4535_n74), .C(DP_OP_110J126_122_4535_n67), .D(
DP_OP_110J126_122_4535_n75), .ICI(DP_OP_110J126_122_4535_n71), .S(
DP_OP_110J126_122_4535_n65), .ICO(DP_OP_110J126_122_4535_n63), .CO(
DP_OP_110J126_122_4535_n64) );
CMPR42X1TS DP_OP_110J126_122_4535_U43 ( .A(DP_OP_110J126_122_4535_n65), .B(
DP_OP_110J126_122_4535_n72), .C(DP_OP_110J126_122_4535_n68), .D(
Sgf_operation_EVEN1_Q_left[19]), .ICI(DP_OP_110J126_122_4535_n219),
.S(DP_OP_110J126_122_4535_n62), .ICO(DP_OP_110J126_122_4535_n60), .CO(
DP_OP_110J126_122_4535_n61) );
CMPR42X1TS DP_OP_110J126_122_4535_U41 ( .A(DP_OP_110J126_122_4535_n263), .B(
DP_OP_110J126_122_4535_n66), .C(DP_OP_110J126_122_4535_n59), .D(
DP_OP_110J126_122_4535_n63), .ICI(DP_OP_110J126_122_4535_n64), .S(
DP_OP_110J126_122_4535_n57), .ICO(DP_OP_110J126_122_4535_n55), .CO(
DP_OP_110J126_122_4535_n56) );
CMPR42X1TS DP_OP_110J126_122_4535_U40 ( .A(DP_OP_110J126_122_4535_n57), .B(
DP_OP_110J126_122_4535_n510), .C(DP_OP_110J126_122_4535_n60), .D(
DP_OP_110J126_122_4535_n509), .ICI(DP_OP_110J126_122_4535_n218), .S(
DP_OP_110J126_122_4535_n54), .ICO(DP_OP_110J126_122_4535_n52), .CO(
DP_OP_110J126_122_4535_n53) );
CMPR42X1TS DP_OP_110J126_122_4535_U39 ( .A(DP_OP_110J126_122_4535_n275), .B(
DP_OP_110J126_122_4535_n249), .C(DP_OP_110J126_122_4535_n262), .D(
DP_OP_110J126_122_4535_n58), .ICI(DP_OP_110J126_122_4535_n55), .S(
DP_OP_110J126_122_4535_n51), .ICO(DP_OP_110J126_122_4535_n49), .CO(
DP_OP_110J126_122_4535_n50) );
CMPR42X1TS DP_OP_110J126_122_4535_U38 ( .A(DP_OP_110J126_122_4535_n51), .B(
DP_OP_110J126_122_4535_n56), .C(DP_OP_110J126_122_4535_n52), .D(
Sgf_operation_EVEN1_Q_left[21]), .ICI(DP_OP_110J126_122_4535_n217),
.S(DP_OP_110J126_122_4535_n48), .ICO(DP_OP_110J126_122_4535_n46), .CO(
DP_OP_110J126_122_4535_n47) );
CMPR42X1TS DP_OP_110J126_122_4535_U37 ( .A(DP_OP_110J126_122_4535_n274), .B(
DP_OP_110J126_122_4535_n248), .C(DP_OP_110J126_122_4535_n261), .D(
DP_OP_110J126_122_4535_n49), .ICI(DP_OP_110J126_122_4535_n50), .S(
DP_OP_110J126_122_4535_n45), .ICO(DP_OP_110J126_122_4535_n43), .CO(
DP_OP_110J126_122_4535_n44) );
CMPR42X1TS DP_OP_110J126_122_4535_U36 ( .A(DP_OP_110J126_122_4535_n45), .B(
DP_OP_110J126_122_4535_n508), .C(DP_OP_110J126_122_4535_n46), .D(
DP_OP_110J126_122_4535_n507), .ICI(DP_OP_110J126_122_4535_n216), .S(
DP_OP_110J126_122_4535_n42), .ICO(DP_OP_110J126_122_4535_n40), .CO(
DP_OP_110J126_122_4535_n41) );
CMPR42X1TS DP_OP_110J126_122_4535_U34 ( .A(DP_OP_110J126_122_4535_n39), .B(
DP_OP_110J126_122_4535_n44), .C(DP_OP_110J126_122_4535_n40), .D(
DP_OP_110J126_122_4535_n41), .ICI(Sgf_operation_EVEN1_Q_left[23]), .S(
DP_OP_110J126_122_4535_n37), .ICO(DP_OP_110J126_122_4535_n35), .CO(
DP_OP_110J126_122_4535_n36) );
CMPR42X1TS DP_OP_110J126_122_4535_U33 ( .A(DP_OP_110J126_122_4535_n246), .B(
DP_OP_110J126_122_4535_n259), .C(DP_OP_110J126_122_4535_n38), .D(
DP_OP_110J126_122_4535_n35), .ICI(DP_OP_110J126_122_4535_n506), .S(
DP_OP_110J126_122_4535_n34), .ICO(DP_OP_110J126_122_4535_n32), .CO(
DP_OP_110J126_122_4535_n33) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(n1762), .RN(n1755), .Q(
FS_Module_state_reg[0]), .QN(n1733) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(n1772), .RN(n1740), .Q(
FSM_selector_B[0]), .QN(n1732) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(n606), .RN(n1734), .Q(final_result_ieee[31]), .QN(n1731) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n262), .CK(n1762), .RN(
n1752), .Q(P_Sgf[24]), .QN(n1730) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(n1764), .RN(n167), .Q(
FS_Module_state_reg[3]), .QN(n1729) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(n1760), .RN(n1744),
.Q(Add_result[2]), .QN(n1728) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(n1760),
.RN(n1739), .Q(Sgf_normalized_result[23]), .QN(n1727) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(n606), .RN(
n1748), .Q(Op_MX[14]), .QN(n1726) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(n1761), .RN(
n1749), .Q(Op_MX[21]), .QN(n1724) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(n1770), .RN(
n1747), .Q(Op_MX[7]), .QN(n1723) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(n605),
.RN(n1737), .Q(Sgf_normalized_result[4]), .QN(n1722) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n263), .CK(n1758), .RN(
n1752), .Q(P_Sgf[25]), .QN(n1720) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(n1770),
.RN(n1739), .Q(Sgf_normalized_result[22]), .QN(n1719) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(n1770), .RN(
n1747), .Q(Op_MX[2]), .QN(n1718) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(n1768),
.RN(n1739), .Q(Sgf_normalized_result[20]), .QN(n1717) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(n1771),
.RN(n1739), .Q(Sgf_normalized_result[18]), .QN(n1716) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(n1771),
.RN(n1739), .Q(Sgf_normalized_result[16]), .QN(n1715) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(n1771),
.RN(n1738), .Q(Sgf_normalized_result[14]), .QN(n1714) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(n1771),
.RN(n1738), .Q(Sgf_normalized_result[12]), .QN(n1713) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(n1771),
.RN(n1738), .Q(Sgf_normalized_result[10]), .QN(n1712) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(n1772),
.RN(n1738), .Q(Sgf_normalized_result[8]), .QN(n1711) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(n1769),
.RN(n1738), .Q(Sgf_normalized_result[6]), .QN(n1710) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(n1768), .RN(
n1754), .QN(n1709) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n283), .CK(n1773), .RN(
n1755), .Q(P_Sgf[45]), .QN(n1708) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(n1768), .RN(
n1747), .Q(Op_MX[5]), .QN(n1707) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n265), .CK(n606), .RN(
n1752), .QN(n1705) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n267), .CK(n1758), .RN(
n1752), .QN(n1704) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n269), .CK(n1765), .RN(
n1751), .QN(n1703) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n271), .CK(n1765), .RN(
n1751), .QN(n1702) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n273), .CK(n1758), .RN(
n1751), .QN(n1701) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n275), .CK(n1756), .RN(
n1751), .QN(n1700) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(n1757), .RN(
n1747), .Q(Op_MX[10]), .QN(n1699) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n277), .CK(n1762), .RN(
n1751), .QN(n1698) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n279), .CK(n1761), .RN(
n1755), .QN(n1697) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n281), .CK(n605), .RN(
n167), .QN(n1696) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(n1764),
.RN(n1734), .QN(n1695) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(n1759), .RN(
n1746), .Q(Op_MX[0]), .QN(n1693) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(n1763), .RN(n1740), .Q(
FSM_selector_B[1]), .QN(n1692) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(n605), .RN(
n1748), .Q(Op_MX[16]), .QN(n1672) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(n1764), .RN(
n1747), .Q(Op_MX[9]), .QN(n1671) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(n1765), .RN(n1755), .Q(
FS_Module_state_reg[1]), .QN(n1670) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(n1756), .RN(
n1748), .Q(Op_MX[13]), .QN(n1668) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(n464), .RN(n1755), .Q(
FS_Module_state_reg[2]), .QN(n1667) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(n1774), .RN(n1737), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(n1757), .RN(n1737), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(n627), .RN(n1737), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(n1774), .RN(n1736), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(n1774), .RN(n1736), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(n626), .RN(n1736), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(n1757), .RN(n1736), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(n1774), .RN(n1736), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(n626), .RN(n1736), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(n1773), .RN(n1736), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(n606), .RN(n1736), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(n464), .RN(n1736), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(n627), .RN(n1736), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(n627), .RN(n1735), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(n1757), .RN(n1735), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n1735), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(n464), .RN(n1735), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(n606), .RN(n1735), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(n1773), .RN(n1735), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(n1773), .RN(n1735), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(n1757), .RN(n1735), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(n1773), .RN(n1735), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(n626), .RN(n1735), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(n606), .RN(n1734), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(n606), .RN(n1734), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(n464), .RN(n1734), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(n1773), .RN(n1734), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(n626), .RN(n1734), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(n627), .RN(n1734), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(n1767), .RN(n1734), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(n1765), .RN(n1734), .Q(final_result_ieee[28]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(n1770), .RN(
n1754), .Q(P_Sgf[3]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(n1760), .RN(n1741),
.Q(Exp_module_Overflow_flag_A) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(n1756), .RN(
n1742), .Q(Op_MY[31]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n258), .CK(n1763), .RN(
n1752), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n254), .CK(n1760), .RN(
n1753), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(
n1753), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(
n1754), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(
n1754), .Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n257), .CK(n1767), .RN(
n1753), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n253), .CK(n1767), .RN(
n1753), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(
n1753), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(
n1754), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n239), .CK(n1772), .RN(
n1754), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n259), .CK(n1767), .RN(
n1752), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(
n1754), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(n1772), .RN(
n1754), .Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n255), .CK(n1767), .RN(
n1753), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n250), .CK(n1767), .RN(
n1753), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n256), .CK(n1767), .RN(
n1753), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n252), .CK(n1767), .RN(
n1753), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n244), .CK(n1769), .RN(
n1754), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n251), .CK(n1767), .RN(
n1753), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(n1769), .RN(
n1754), .Q(P_Sgf[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(n1765), .RN(n1744), .Q(Add_result[23]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(n1764), .RN(n1744),
.Q(Add_result[0]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n261), .CK(n605), .RN(
n1752), .Q(P_Sgf[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(n1761), .RN(
n1744), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(n1757), .RN(
n1743), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(n1762), .RN(
n1743), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(n1758), .RN(
n1744), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(n464), .RN(
n1743), .Q(Op_MY[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(n605), .RN(
n1743), .Q(Op_MY[27]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n237), .CK(n1769), .RN(
n1755), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(n606), .RN(
n1744), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(n1756), .RN(
n1749), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(n1764), .RN(
n1749), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(n1762), .RN(
n1749), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(n606), .RN(
n1749), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(n1761), .RN(
n1749), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(n1763), .RN(
n1749), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(n1763), .RN(
n1749), .Q(Op_MX[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(n1759), .RN(n1739),
.Q(exp_oper_result[8]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(n1762), .RN(
n1749), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(n1774), .RN(
n1743), .Q(Op_MY[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(n1760), .RN(n1740),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(n1763), .RN(n1740),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(n1772), .RN(n1740),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(n1769), .RN(n1740),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(n1770), .RN(n1740),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(n1768), .RN(n1740),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(n1759), .RN(n1740),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(n1770), .RN(n1740),
.Q(exp_oper_result[7]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(n1763), .RN(
n1744), .Q(FSM_add_overflow_flag) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(n605), .RN(n1745),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(n1772), .RN(n1744),
.Q(Add_result[3]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n274), .CK(n626), .RN(
n1751), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n272), .CK(n464), .RN(
n1751), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n270), .CK(n1764), .RN(
n1751), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n268), .CK(n1756), .RN(
n1751), .Q(P_Sgf[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(n1770), .RN(n1746), .Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(n1759), .RN(n1746), .Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(n1768), .RN(n1746), .Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(n1770), .RN(n1746), .Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(n1759), .RN(n1745), .Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(n1769), .RN(n1745), .Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(n1760), .RN(n1745),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(n1764), .RN(n1745),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(n605), .RN(n1744),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(n1768), .RN(n1746), .Q(Add_result[22]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n266), .CK(n1756), .RN(
n1752), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n264), .CK(n1758), .RN(
n1752), .Q(P_Sgf[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(n1772), .RN(n1744),
.Q(Add_result[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n282), .CK(n1756), .RN(
n167), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n280), .CK(n1762), .RN(
n1755), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n278), .CK(n1764), .RN(
n1755), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n276), .CK(n1758), .RN(
n1751), .Q(P_Sgf[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(n1768), .RN(n1746), .Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(n1759), .RN(n1746), .Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(n1770), .RN(n1746), .Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(n1768), .RN(n1745), .Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(n1759), .RN(n1745), .Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(n1769), .RN(n1745), .Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(n1760), .RN(n1745),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(n1763), .RN(n1745),
.Q(Add_result[6]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(n1774), .RN(n1737),
.Q(underflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(n1760),
.RN(n1737), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(n1759),
.RN(n1739), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(n1771),
.RN(n1739), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(n1771),
.RN(n1739), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(n1771),
.RN(n1738), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(n1771),
.RN(n1738), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(n1771),
.RN(n1738), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(n1764),
.RN(n1738), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(n1772),
.RN(n1738), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(n1769),
.RN(n1737), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(n1760),
.RN(n1737), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(n1761), .RN(
n1749), .Q(Op_MX[22]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(n1765), .RN(
n1747), .Q(Op_MX[8]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(n1772),
.RN(n1737), .Q(Sgf_normalized_result[1]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(n1765), .RN(
n1748), .Q(Op_MX[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(n1768), .RN(
n1747), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(n605), .RN(
n1748), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(n1759), .RN(
n1747), .Q(Op_MX[4]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(n1769),
.RN(n1737), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(n1761), .RN(
n1741), .Q(Op_MY[0]), .QN(n1661) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(n1763), .RN(n1750), .Q(
FSM_selector_A), .QN(n647) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(n1758), .RN(
n1748), .Q(Op_MX[11]), .QN(n1666) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(n1762), .RN(
n1742), .Q(Op_MY[16]), .QN(n1685) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(n1756), .RN(
n1743), .Q(Op_MY[20]), .QN(n1684) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(n626), .RN(
n1743), .Q(Op_MY[18]), .QN(n1690) );
CMPR32X2TS DP_OP_36J126_123_9196_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J126_123_9196_n33), .C(DP_OP_36J126_123_9196_n22), .CO(
DP_OP_36J126_123_9196_n9), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J126_123_9196_U9 ( .A(DP_OP_36J126_123_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J126_123_9196_n9), .CO(
DP_OP_36J126_123_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J126_123_9196_U8 ( .A(DP_OP_36J126_123_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J126_123_9196_n8), .CO(
DP_OP_36J126_123_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J126_123_9196_U7 ( .A(DP_OP_36J126_123_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J126_123_9196_n7), .CO(
DP_OP_36J126_123_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J126_123_9196_U6 ( .A(DP_OP_36J126_123_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J126_123_9196_n6), .CO(
DP_OP_36J126_123_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J126_123_9196_U5 ( .A(DP_OP_36J126_123_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J126_123_9196_n5), .CO(
DP_OP_36J126_123_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J126_123_9196_U4 ( .A(DP_OP_36J126_123_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J126_123_9196_n4), .CO(
DP_OP_36J126_123_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J126_123_9196_U3 ( .A(DP_OP_36J126_123_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J126_123_9196_n3), .CO(
DP_OP_36J126_123_9196_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J126_123_9196_U2 ( .A(DP_OP_36J126_123_9196_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J126_123_9196_n2), .CO(
DP_OP_36J126_123_9196_n1), .S(Exp_module_Data_S[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(n1766), .RN(
n1742), .Q(Op_MY[13]), .QN(n1683) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(n1761), .RN(
n1742), .Q(Op_MY[11]), .QN(n1676) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n1747), .Q(Op_MX[3]), .QN(n1721) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(n1759), .RN(
n1746), .Q(Op_MX[31]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(n1757), .RN(
n1743), .Q(Op_MY[22]), .QN(n1689) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(n1766), .RN(
n1741), .Q(Op_MY[4]), .QN(n1678) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(n463), .RN(
n1741), .Q(Op_MY[3]), .QN(n1682) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(n1766), .RN(
n1741), .Q(Op_MY[6]), .QN(n1680) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(n1774), .RN(
n1741), .Q(Op_MY[8]), .QN(n1679) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(n1762), .RN(
n1741), .Q(Op_MY[7]), .QN(n1681) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(n1766), .RN(
n1742), .Q(Op_MY[14]), .QN(n1677) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(n1766), .RN(
n1748), .Q(Op_MX[12]), .QN(n1664) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n260), .CK(n605), .RN(
n1752), .Q(P_Sgf[22]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(n1763), .RN(
n1741), .Q(Op_MY[1]), .QN(n1665) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(n1758), .RN(
n1741), .Q(Op_MY[2]), .QN(n1673) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(n627), .RN(
n1742), .Q(Op_MY[12]), .QN(n1662) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(n464), .RN(
n1742), .Q(Op_MY[9]), .QN(n1675) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(n1765), .RN(
n1741), .Q(Op_MY[5]), .QN(n1674) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(n1766), .RN(
n1742), .Q(Op_MY[10]), .QN(n1663) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(n1768), .RN(n1739), .Q(
FSM_selector_C), .QN(n404) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(n1756), .RN(
n1743), .Q(Op_MY[21]), .QN(n1687) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(n606), .RN(
n1743), .Q(n394), .QN(n1691) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(n1761), .RN(
n1742), .Q(Op_MY[17]), .QN(n1688) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(n1756), .RN(
n1742), .Q(Op_MY[15]), .QN(n1686) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n284), .CK(n1758), .RN(
n167), .Q(P_Sgf[46]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(n1765), .RN(
n1748), .Q(Op_MX[15]), .QN(n1694) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(n1762), .RN(
n1748), .Q(Op_MX[19]), .QN(n1725) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(n1761), .RN(
n1748), .Q(Op_MX[17]), .QN(n1706) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(n1770), .RN(
n1747), .Q(Op_MX[1]), .QN(n1669) );
CMPR32X2TS U406 ( .A(n588), .B(n868), .C(n497), .CO(n873), .S(n870) );
CMPR32X2TS U407 ( .A(n645), .B(n589), .C(n1512), .CO(
DP_OP_110J126_122_4535_n953), .S(DP_OP_110J126_122_4535_n954) );
CMPR32X2TS U408 ( .A(n645), .B(n1128), .C(n1127), .CO(n1053), .S(n1129) );
CMPR32X2TS U409 ( .A(Op_MY[13]), .B(n572), .C(n1517), .CO(
DP_OP_110J126_122_4535_n982), .S(DP_OP_110J126_122_4535_n983) );
CMPR32X2TS U410 ( .A(n559), .B(n1520), .C(n1519), .CO(
DP_OP_110J126_122_4535_n1009), .S(DP_OP_110J126_122_4535_n1010) );
CMPR32X2TS U411 ( .A(Op_MY[13]), .B(n1050), .C(n1049), .CO(n1043), .S(n1051)
);
CMPR32X2TS U412 ( .A(n588), .B(n585), .C(n679), .CO(n680), .S(n1568) );
CMPR32X2TS U413 ( .A(Op_MY[21]), .B(n565), .C(n677), .CO(n679), .S(n1297) );
CMPR32X2TS U414 ( .A(n643), .B(n582), .C(n676), .CO(n677), .S(n1295) );
CMPR32X2TS U415 ( .A(Op_MX[19]), .B(Op_MX[7]), .C(n670), .CO(n669), .S(n1076) );
CMPR32X2TS U416 ( .A(n581), .B(n589), .C(n663), .CO(n676), .S(n1292) );
CMPR32X2TS U417 ( .A(n583), .B(n645), .C(n982), .CO(n663), .S(n1560) );
CMPR32X2TS U418 ( .A(Op_MX[17]), .B(Op_MX[5]), .C(n683), .CO(n687), .S(n1007) );
CMPR32X2TS U419 ( .A(Op_MY[17]), .B(n563), .C(n978), .CO(n982), .S(n1564) );
CMPR32X2TS U420 ( .A(n644), .B(n587), .C(n894), .CO(n978), .S(n1279) );
CMPR32X2TS U421 ( .A(n584), .B(n572), .C(n667), .CO(n894), .S(n1260) );
CMPR32X2TS U422 ( .A(n567), .B(n569), .C(n672), .CO(n667), .S(n1270) );
CMPR32X2TS U423 ( .A(n561), .B(Op_MY[13]), .C(n898), .CO(n672), .S(n1268) );
ADDFX2TS U424 ( .A(Op_MX[13]), .B(Op_MX[1]), .CI(n895), .CO(n661), .S(n1274)
);
XOR2X1TS U425 ( .A(n1635), .B(n1634), .Y(n1636) );
INVX4TS U426 ( .A(n462), .Y(n463) );
INVX4TS U427 ( .A(n462), .Y(n464) );
ADDFX1TS U428 ( .A(DP_OP_110J126_122_4535_n43), .B(n1014), .CI(n1013), .CO(
DP_OP_110J126_122_4535_n38), .S(DP_OP_110J126_122_4535_n39) );
CLKBUFX3TS U429 ( .A(n1562), .Y(n534) );
INVX2TS U430 ( .A(n417), .Y(n598) );
OR3X2TS U431 ( .A(underflow_flag), .B(overflow_flag), .C(n1331), .Y(n1658)
);
CLKBUFX3TS U432 ( .A(n1580), .Y(n607) );
INVX2TS U433 ( .A(n438), .Y(n447) );
INVX2TS U434 ( .A(n422), .Y(n457) );
INVX2TS U435 ( .A(n420), .Y(n446) );
INVX2TS U436 ( .A(n421), .Y(n602) );
CLKBUFX2TS U437 ( .A(n1575), .Y(n600) );
INVX2TS U438 ( .A(n418), .Y(n456) );
INVX2TS U439 ( .A(n432), .Y(n484) );
NAND2X1TS U440 ( .A(n1722), .B(n1585), .Y(n1589) );
OA21X2TS U441 ( .A0(n1071), .A1(n1582), .B0(FS_Module_state_reg[1]), .Y(n692) );
INVX2TS U442 ( .A(n1102), .Y(n1097) );
CLKINVX3TS U443 ( .A(n402), .Y(n391) );
NOR2X1TS U444 ( .A(n620), .B(n1038), .Y(DP_OP_110J126_122_4535_n725) );
CLKBUFX3TS U445 ( .A(n1581), .Y(n499) );
INVX2TS U446 ( .A(n430), .Y(n503) );
CLKBUFX3TS U447 ( .A(n1554), .Y(n615) );
INVX2TS U448 ( .A(n399), .Y(n488) );
INVX2TS U449 ( .A(n423), .Y(n443) );
INVX2TS U450 ( .A(n423), .Y(n444) );
INVX2TS U451 ( .A(n428), .Y(n596) );
INVX2TS U452 ( .A(n401), .Y(n500) );
INVX2TS U453 ( .A(n430), .Y(n502) );
INVX2TS U454 ( .A(n1234), .Y(n1241) );
INVX2TS U455 ( .A(n429), .Y(n452) );
INVX2TS U456 ( .A(n425), .Y(n482) );
NAND3X2TS U457 ( .A(n1539), .B(n1729), .C(FS_Module_state_reg[0]), .Y(n1498)
);
INVX2TS U458 ( .A(n427), .Y(n476) );
INVX2TS U459 ( .A(n424), .Y(n478) );
NAND3X2TS U460 ( .A(FS_Module_state_reg[3]), .B(n1537), .C(n1667), .Y(n1081)
);
CLKINVX3TS U461 ( .A(n403), .Y(n392) );
NOR2X1TS U462 ( .A(n1671), .B(n1348), .Y(n988) );
INVX2TS U463 ( .A(n408), .Y(n517) );
INVX2TS U464 ( .A(n437), .Y(n440) );
INVX2TS U465 ( .A(n415), .Y(n442) );
NAND2X4TS U466 ( .A(n1537), .B(n1321), .Y(n1414) );
INVX2TS U467 ( .A(n433), .Y(n480) );
INVX2TS U468 ( .A(n414), .Y(n454) );
INVX2TS U469 ( .A(n415), .Y(n441) );
CLKBUFX3TS U470 ( .A(Op_MY[15]), .Y(n572) );
CLKBUFX3TS U471 ( .A(Op_MY[14]), .Y(n569) );
CLKBUFX3TS U472 ( .A(Op_MY[22]), .Y(n588) );
CLKBUFX3TS U473 ( .A(Op_MY[8]), .Y(n582) );
CLKBUFX3TS U474 ( .A(Op_MY[7]), .Y(n581) );
CLKBUFX3TS U475 ( .A(Op_MY[4]), .Y(n587) );
CLKBUFX3TS U476 ( .A(Op_MY[6]), .Y(n583) );
CLKBUFX3TS U477 ( .A(Op_MY[17]), .Y(n574) );
CLKBUFX3TS U478 ( .A(Op_MY[21]), .Y(n573) );
CLKBUFX3TS U479 ( .A(Op_MY[3]), .Y(n584) );
CLKBUFX3TS U480 ( .A(n463), .Y(n393) );
AOI221X1TS U481 ( .A0(n536), .A1(n1297), .B0(n558), .B1(n544), .C0(n1154),
.Y(n1283) );
AOI221X1TS U482 ( .A0(n625), .A1(n1292), .B0(n531), .B1(n461), .C0(n1155),
.Y(n1282) );
AOI221X1TS U483 ( .A0(n448), .A1(n564), .B0(n604), .B1(n466), .C0(n1016),
.Y(n1029) );
AOI221X1TS U484 ( .A0(n538), .A1(n550), .B0(n533), .B1(n511), .C0(n993), .Y(
n1018) );
AOI221X1TS U485 ( .A0(n623), .A1(n1560), .B0(n556), .B1(n510), .C0(n994),
.Y(n1019) );
CLKAND2X2TS U486 ( .A(n1522), .B(n689), .Y(n413) );
CLKAND2X2TS U487 ( .A(Op_MX[21]), .B(n1351), .Y(n401) );
AOI221X1TS U488 ( .A0(n531), .A1(n613), .B0(n625), .B1(n1571), .C0(n1075),
.Y(n1161) );
OAI221X1TS U489 ( .A0(n1568), .A1(n1301), .B0(n541), .B1(n490), .C0(n1203),
.Y(DP_OP_110J126_122_4535_n278) );
AOI221X1TS U490 ( .A0(n557), .A1(n577), .B0(n536), .B1(n512), .C0(n1250),
.Y(n1199) );
AOI221X1TS U491 ( .A0(n625), .A1(n525), .B0(n531), .B1(n524), .C0(n1146),
.Y(n1200) );
OAI221X1TS U492 ( .A0(n1297), .A1(n1301), .B0(n544), .B1(n490), .C0(n1288),
.Y(DP_OP_110J126_122_4535_n279) );
AOI221X1TS U493 ( .A0(n536), .A1(n548), .B0(n558), .B1(n513), .C0(n1169),
.Y(n1204) );
AOI221X1TS U494 ( .A0(n556), .A1(n577), .B0(n623), .B1(n512), .C0(n1332),
.Y(n1206) );
AOI221X1TS U495 ( .A0(n625), .A1(n554), .B0(n531), .B1(n510), .C0(n1168),
.Y(n1205) );
CLKAND2X2TS U496 ( .A(n1312), .B(n664), .Y(n435) );
CLKAND2X2TS U497 ( .A(n1337), .B(n673), .Y(n412) );
AOI221X1TS U498 ( .A0(n536), .A1(n1564), .B0(n558), .B1(n509), .C0(n1148),
.Y(n1216) );
AOI221X1TS U499 ( .A0(n1689), .A1(n476), .B0(Op_MY[22]), .B1(n597), .C0(
n1132), .Y(n1133) );
CLKAND2X2TS U500 ( .A(n996), .B(n615), .Y(n431) );
CLKAND2X2TS U501 ( .A(n899), .B(n684), .Y(n411) );
AOI221X1TS U502 ( .A0(n536), .A1(n1270), .B0(n558), .B1(n543), .C0(n1020),
.Y(n1222) );
OAI221X1TS U503 ( .A0(n1564), .A1(n1570), .B0(n509), .B1(n492), .C0(n999),
.Y(n1000) );
OAI221X1TS U504 ( .A0(n1260), .A1(n639), .B0(n542), .B1(n494), .C0(n998),
.Y(n1001) );
CLKAND2X2TS U505 ( .A(Op_MX[7]), .B(n1353), .Y(n399) );
AOI221X1TS U506 ( .A0(n458), .A1(Op_MY[8]), .B0(n602), .B1(n1679), .C0(n1236), .Y(n1240) );
OAI221X1TS U507 ( .A0(n566), .A1(n507), .B0(n468), .B1(n1581), .C0(n1108),
.Y(DP_OP_110J126_122_4535_n729) );
OAI221X1TS U508 ( .A0(n564), .A1(n1580), .B0(n466), .B1(n632), .C0(n1306),
.Y(DP_OP_110J126_122_4535_n705) );
OAI221X1TS U509 ( .A0(n473), .A1(n1263), .B0(n474), .B1(n611), .C0(n396),
.Y(DP_OP_110J126_122_4535_n741) );
AOI221X1TS U510 ( .A0(n448), .A1(n586), .B0(n604), .B1(n472), .C0(n1065),
.Y(n1096) );
AOI221X1TS U511 ( .A0(n623), .A1(n1564), .B0(n556), .B1(n509), .C0(n1022),
.Y(n1226) );
AOI221X1TS U512 ( .A0(n538), .A1(n1260), .B0(n533), .B1(n542), .C0(n1021),
.Y(n1228) );
AOI221X1TS U513 ( .A0(n391), .A1(n574), .B0(n484), .B1(n1688), .C0(n1042),
.Y(n1049) );
AOI221X1TS U514 ( .A0(n392), .A1(n573), .B0(n482), .B1(n1687), .C0(n1041),
.Y(n1050) );
OAI221X1TS U515 ( .A0(Op_MY[20]), .A1(n503), .B0(n1684), .B1(n444), .C0(
n1167), .Y(DP_OP_110J126_122_4535_n1126) );
AOI221X1TS U516 ( .A0(n597), .A1(Op_MY[14]), .B0(n476), .B1(n1677), .C0(
n1056), .Y(n1136) );
AOI221X1TS U517 ( .A0(n391), .A1(n646), .B0(n484), .B1(n1683), .C0(n1057),
.Y(n1135) );
OAI221X1TS U518 ( .A0(n554), .A1(n1563), .B0(n510), .B1(n1562), .C0(n1289),
.Y(DP_OP_110J126_122_4535_n266) );
CLKAND2X2TS U519 ( .A(n750), .B(n1694), .Y(n423) );
AOI221X1TS U520 ( .A0(n536), .A1(n1560), .B0(n558), .B1(n510), .C0(n1151),
.Y(n1209) );
AOI221X1TS U521 ( .A0(n538), .A1(n1295), .B0(n533), .B1(n513), .C0(n1150),
.Y(n1210) );
AOI221X1TS U522 ( .A0(n625), .A1(n552), .B0(n531), .B1(n509), .C0(n1142),
.Y(n1272) );
AOI221X1TS U523 ( .A0(n536), .A1(n571), .B0(n558), .B1(n570), .C0(n1141),
.Y(n1273) );
OAI221X1TS U524 ( .A0(n1564), .A1(n1301), .B0(n509), .B1(n490), .C0(n1259),
.Y(DP_OP_110J126_122_4535_n283) );
OAI221X1TS U525 ( .A0(n1560), .A1(n640), .B0(n510), .B1(n494), .C0(n1251),
.Y(DP_OP_110J126_122_4535_n312) );
OAI221X1TS U526 ( .A0(n1279), .A1(n634), .B0(n511), .B1(n496), .C0(n1220),
.Y(DP_OP_110J126_122_4535_n299) );
OAI221X1TS U527 ( .A0(n1292), .A1(n640), .B0(n461), .B1(n494), .C0(n983),
.Y(n984) );
OAI221X1TS U528 ( .A0(n552), .A1(n634), .B0(n509), .B1(n496), .C0(n981), .Y(
n985) );
AOI221X1TS U529 ( .A0(n597), .A1(n394), .B0(n476), .B1(n1691), .C0(n1188),
.Y(n1191) );
OAI221X1TS U530 ( .A0(n573), .A1(n460), .B0(n1687), .B1(n478), .C0(n1153),
.Y(DP_OP_110J126_122_4535_n1110) );
OAI221X1TS U531 ( .A0(n574), .A1(n501), .B0(n1688), .B1(n480), .C0(n1264),
.Y(DP_OP_110J126_122_4535_n1086) );
OAI221X1TS U532 ( .A0(Op_MY[22]), .A1(n460), .B0(n1689), .B1(n478), .C0(n403), .Y(DP_OP_110J126_122_4535_n1109) );
OAI221X1TS U533 ( .A0(Op_MY[18]), .A1(n501), .B0(n1690), .B1(n480), .C0(
n1258), .Y(DP_OP_110J126_122_4535_n1085) );
OAI221X1TS U534 ( .A0(Op_MY[22]), .A1(n1516), .B0(n1689), .B1(n1515), .C0(
n1140), .Y(DP_OP_110J126_122_4535_n1096) );
OAI221X1TS U535 ( .A0(n394), .A1(n501), .B0(n1691), .B1(n480), .C0(n1180),
.Y(DP_OP_110J126_122_4535_n1084) );
AOI221X1TS U536 ( .A0(n391), .A1(Op_MY[22]), .B0(n484), .B1(n1689), .C0(
n1052), .Y(n1127) );
OAI221X1TS U537 ( .A0(n1270), .A1(n1301), .B0(n543), .B1(n490), .C0(n1269),
.Y(DP_OP_110J126_122_4535_n286) );
AOI221X1TS U538 ( .A0(n456), .A1(n586), .B0(n486), .B1(n472), .C0(n1036),
.Y(n1196) );
OAI221X1TS U539 ( .A0(n586), .A1(n642), .B0(n472), .B1(n611), .C0(n1109),
.Y(DP_OP_110J126_122_4535_n742) );
OAI221X1TS U540 ( .A0(Op_MY[6]), .A1(n487), .B0(n1680), .B1(n637), .C0(n1303), .Y(DP_OP_110J126_122_4535_n718) );
OAI221X1TS U541 ( .A0(Op_MY[3]), .A1(n1576), .B0(n1682), .B1(n600), .C0(
n1193), .Y(DP_OP_110J126_122_4535_n694) );
OAI221X1TS U542 ( .A0(n1279), .A1(n1570), .B0(n511), .B1(n492), .C0(n1261),
.Y(DP_OP_110J126_122_4535_n329) );
OAI221X1TS U543 ( .A0(n523), .A1(n639), .B0(n543), .B1(n494), .C0(n1231),
.Y(DP_OP_110J126_122_4535_n316) );
OAI221X1TS U544 ( .A0(n564), .A1(n488), .B0(n466), .B1(n637), .C0(n1093),
.Y(DP_OP_110J126_122_4535_n719) );
OAI221X1TS U545 ( .A0(Op_MY[7]), .A1(n507), .B0(n1681), .B1(n1581), .C0(
n1286), .Y(DP_OP_110J126_122_4535_n731) );
OAI221X1TS U546 ( .A0(n568), .A1(n1576), .B0(n470), .B1(n600), .C0(n1187),
.Y(DP_OP_110J126_122_4535_n695) );
AOI221X1TS U547 ( .A0(n458), .A1(n566), .B0(n602), .B1(n468), .C0(n1039),
.Y(n1233) );
OAI221X1TS U548 ( .A0(n586), .A1(n508), .B0(n471), .B1(n499), .C0(n1107),
.Y(DP_OP_110J126_122_4535_n728) );
OAI221X1TS U549 ( .A0(Op_MY[6]), .A1(n607), .B0(n1680), .B1(n1579), .C0(
n1290), .Y(DP_OP_110J126_122_4535_n704) );
OAI221X1TS U550 ( .A0(n564), .A1(n1576), .B0(n466), .B1(n600), .C0(n1243),
.Y(DP_OP_110J126_122_4535_n692) );
OAI221X1TS U551 ( .A0(n566), .A1(n488), .B0(n468), .B1(n637), .C0(n1112),
.Y(DP_OP_110J126_122_4535_n715) );
OAI221X1TS U552 ( .A0(Op_MY[7]), .A1(n607), .B0(n1681), .B1(n1579), .C0(
n1238), .Y(DP_OP_110J126_122_4535_n703) );
OAI221X1TS U553 ( .A0(n586), .A1(n488), .B0(n472), .B1(n637), .C0(n1104),
.Y(DP_OP_110J126_122_4535_n714) );
AOI221X1TS U554 ( .A0(n1567), .A1(n546), .B0(n556), .B1(n609), .C0(n897),
.Y(n1033) );
AOI221X1TS U555 ( .A0(n623), .A1(n523), .B0(n556), .B1(n543), .C0(n977), .Y(
n1540) );
OAI221X1TS U556 ( .A0(n473), .A1(n1576), .B0(n474), .B1(n1575), .C0(n1110),
.Y(DP_OP_110J126_122_4535_n686) );
OAI221X1TS U557 ( .A0(n1268), .A1(n1301), .B0(n609), .B1(n490), .C0(n1131),
.Y(DP_OP_110J126_122_4535_n287) );
CLKAND2X2TS U558 ( .A(Op_MX[0]), .B(Op_MX[1]), .Y(n415) );
OAI221X1TS U559 ( .A0(Op_MY[8]), .A1(n1576), .B0(n1679), .B1(n600), .C0(
n1254), .Y(DP_OP_110J126_122_4535_n689) );
OAI221X1TS U560 ( .A0(n1268), .A1(n635), .B0(n609), .B1(n496), .C0(n1125),
.Y(DP_OP_110J126_122_4535_n302) );
AOI221X1TS U561 ( .A0(n456), .A1(Op_MY[6]), .B0(n486), .B1(n1680), .C0(n1024), .Y(n1178) );
AOI221X1TS U562 ( .A0(n456), .A1(Op_MY[7]), .B0(n486), .B1(n1681), .C0(n1062), .Y(n1116) );
AOI221X1TS U563 ( .A0(n458), .A1(Op_MY[3]), .B0(n602), .B1(n1682), .C0(n1060), .Y(n1118) );
AOI221X1TS U564 ( .A0(n448), .A1(n562), .B0(n1577), .B1(n521), .C0(n1061),
.Y(n1117) );
OAI221X1TS U565 ( .A0(n564), .A1(n508), .B0(n466), .B1(n499), .C0(n649), .Y(
DP_OP_110J126_122_4535_n733) );
OAI221X1TS U566 ( .A0(Op_MY[7]), .A1(n642), .B0(n1681), .B1(n611), .C0(n1105), .Y(DP_OP_110J126_122_4535_n745) );
OAI221X1TS U567 ( .A0(Op_MY[6]), .A1(n508), .B0(n1680), .B1(n499), .C0(n1095), .Y(DP_OP_110J126_122_4535_n732) );
OAI221X1TS U568 ( .A0(Op_MY[8]), .A1(n642), .B0(n1679), .B1(n610), .C0(n1262), .Y(DP_OP_110J126_122_4535_n744) );
OAI221X1TS U569 ( .A0(n562), .A1(n1576), .B0(n521), .B1(n1575), .C0(n1182),
.Y(DP_OP_110J126_122_4535_n696) );
OAI221X1TS U570 ( .A0(n1268), .A1(n1570), .B0(n609), .B1(n492), .C0(n1094),
.Y(DP_OP_110J126_122_4535_n332) );
OAI221X1TS U571 ( .A0(n566), .A1(n1576), .B0(n468), .B1(n600), .C0(n1252),
.Y(DP_OP_110J126_122_4535_n688) );
OAI221X1TS U572 ( .A0(n586), .A1(n1576), .B0(n472), .B1(n600), .C0(n1106),
.Y(DP_OP_110J126_122_4535_n687) );
OAI221X1TS U573 ( .A0(n473), .A1(n607), .B0(n474), .B1(n1579), .C0(n603),
.Y(DP_OP_110J126_122_4535_n699) );
OAI221X1TS U574 ( .A0(n1270), .A1(n635), .B0(n543), .B1(n496), .C0(n1249),
.Y(DP_OP_110J126_122_4535_n301) );
OAI221X1TS U575 ( .A0(Op_MY[14]), .A1(n501), .B0(n1677), .B1(n480), .C0(n657), .Y(DP_OP_110J126_122_4535_n1089) );
OAI221X1TS U576 ( .A0(Op_MY[18]), .A1(n460), .B0(n1690), .B1(n478), .C0(
n1165), .Y(DP_OP_110J126_122_4535_n1113) );
OAI221X1TS U577 ( .A0(Op_MY[22]), .A1(n503), .B0(n1689), .B1(n444), .C0(
n1518), .Y(n1519) );
OAI221X1TS U578 ( .A0(Op_MY[18]), .A1(n1516), .B0(n1690), .B1(n1515), .C0(
n1145), .Y(DP_OP_110J126_122_4535_n1100) );
OAI221X1TS U579 ( .A0(n394), .A1(n460), .B0(n1691), .B1(n478), .C0(n1276),
.Y(DP_OP_110J126_122_4535_n1112) );
OAI221X1TS U580 ( .A0(n394), .A1(n1516), .B0(n1691), .B1(n1515), .C0(n1267),
.Y(DP_OP_110J126_122_4535_n1099) );
OAI221X1TS U581 ( .A0(Op_MY[16]), .A1(n1516), .B0(n1685), .B1(n1515), .C0(
n1287), .Y(DP_OP_110J126_122_4535_n1102) );
OAI221X1TS U582 ( .A0(Op_MY[15]), .A1(n460), .B0(n1686), .B1(n478), .C0(
n1299), .Y(DP_OP_110J126_122_4535_n1116) );
OAI221X1TS U583 ( .A0(Op_MY[14]), .A1(n460), .B0(n1677), .B1(n477), .C0(
n1171), .Y(DP_OP_110J126_122_4535_n1117) );
AOI221X1TS U584 ( .A0(n392), .A1(Op_MY[13]), .B0(n482), .B1(n1683), .C0(n736), .Y(n743) );
AOI221X1TS U585 ( .A0(n452), .A1(Op_MY[14]), .B0(n515), .B1(n1677), .C0(n737), .Y(n742) );
CLKAND2X2TS U586 ( .A(Op_MX[15]), .B(n750), .Y(n430) );
OAI221X1TS U587 ( .A0(n525), .A1(n639), .B0(n524), .B1(n494), .C0(n1265),
.Y(DP_OP_110J126_122_4535_n308) );
OAI221X1TS U588 ( .A0(n527), .A1(n1563), .B0(n542), .B1(n1562), .C0(n1208),
.Y(DP_OP_110J126_122_4535_n269) );
OAI221X1TS U589 ( .A0(n550), .A1(n1563), .B0(n511), .B1(n1562), .C0(n1278),
.Y(DP_OP_110J126_122_4535_n268) );
OAI221X1TS U590 ( .A0(n1270), .A1(n1563), .B0(n543), .B1(n1562), .C0(n1159),
.Y(DP_OP_110J126_122_4535_n270) );
OAI221X1TS U591 ( .A0(n529), .A1(n1570), .B0(n544), .B1(n492), .C0(n1219),
.Y(DP_OP_110J126_122_4535_n324) );
AOI221X1TS U592 ( .A0(n456), .A1(Op_MY[3]), .B0(n486), .B1(n1682), .C0(n799),
.Y(n804) );
OAI221X1TS U593 ( .A0(n546), .A1(n640), .B0(n609), .B1(n494), .C0(n1120),
.Y(DP_OP_110J126_122_4535_n317) );
OAI221X1TS U594 ( .A0(Op_MY[3]), .A1(n642), .B0(n1682), .B1(n611), .C0(n1124), .Y(DP_OP_110J126_122_4535_n749) );
OAI221X1TS U595 ( .A0(Op_MY[4]), .A1(n508), .B0(n1678), .B1(n499), .C0(n1248), .Y(DP_OP_110J126_122_4535_n734) );
AOI221X1TS U596 ( .A0(n456), .A1(n568), .B0(n486), .B1(n470), .C0(n801), .Y(
n813) );
NAND2BXLTS U597 ( .AN(n802), .B(Op_MY[0]), .Y(n812) );
OAI221X1TS U598 ( .A0(n568), .A1(n507), .B0(n470), .B1(n499), .C0(n1111),
.Y(DP_OP_110J126_122_4535_n736) );
OAI221X1TS U599 ( .A0(Op_MY[4]), .A1(n642), .B0(n1678), .B1(n611), .C0(n1247), .Y(DP_OP_110J126_122_4535_n748) );
OAI221X1TS U600 ( .A0(Op_MY[0]), .A1(n488), .B0(n1661), .B1(n637), .C0(n1172), .Y(DP_OP_110J126_122_4535_n724) );
OAI221X1TS U601 ( .A0(Op_MY[3]), .A1(n508), .B0(n1682), .B1(n499), .C0(n1271), .Y(DP_OP_110J126_122_4535_n735) );
OAI221X1TS U602 ( .A0(n562), .A1(n488), .B0(n521), .B1(n637), .C0(n1244),
.Y(DP_OP_110J126_122_4535_n723) );
OAI221X1TS U603 ( .A0(Op_MY[3]), .A1(n487), .B0(n1682), .B1(n1304), .C0(
n1298), .Y(DP_OP_110J126_122_4535_n721) );
OAI221X1TS U604 ( .A0(Op_MY[4]), .A1(n488), .B0(n1678), .B1(n1304), .C0(
n1280), .Y(DP_OP_110J126_122_4535_n720) );
OAI221X1TS U605 ( .A0(Op_MY[0]), .A1(n642), .B0(n621), .B1(n611), .C0(n806),
.Y(n809) );
OAI221X1TS U606 ( .A0(n646), .A1(n503), .B0(n1683), .B1(n444), .C0(n744),
.Y(n747) );
OAI221X1TS U607 ( .A0(n617), .A1(n1563), .B0(n1557), .B1(n1562), .C0(n1130),
.Y(DP_OP_110J126_122_4535_n272) );
OAI221X1TS U608 ( .A0(n1268), .A1(n1563), .B0(n609), .B1(n1562), .C0(n1213),
.Y(DP_OP_110J126_122_4535_n271) );
AO22XLTS U609 ( .A0(n1510), .A1(Data_MX[31]), .B0(n1478), .B1(Op_MX[31]),
.Y(n343) );
NAND2BX2TS U610 ( .AN(n1524), .B(n1707), .Y(n1581) );
OR3X1TS U611 ( .A(Op_MX[13]), .B(Op_MX[14]), .C(n1694), .Y(n395) );
OR2X1TS U612 ( .A(n811), .B(n1721), .Y(n396) );
OR2X1TS U613 ( .A(n1007), .B(n1006), .Y(n397) );
OR2X1TS U614 ( .A(n1707), .B(n802), .Y(n398) );
NOR2X1TS U615 ( .A(Op_MY[11]), .B(n680), .Y(n1566) );
OR3X1TS U616 ( .A(n1076), .B(n674), .C(n673), .Y(n400) );
BUFX4TS U617 ( .A(n626), .Y(n1758) );
OR2X1TS U618 ( .A(Op_MX[21]), .B(n1045), .Y(n402) );
OR2X1TS U619 ( .A(Op_MX[17]), .B(n740), .Y(n403) );
NAND3BX2TS U620 ( .AN(n1122), .B(n1011), .C(n1012), .Y(n1562) );
OR2X1TS U621 ( .A(n1328), .B(n404), .Y(n405) );
OR2X1TS U622 ( .A(n404), .B(n693), .Y(n406) );
AO21X1TS U623 ( .A0(n518), .A1(n620), .B0(n898), .Y(n407) );
BUFX4TS U624 ( .A(n1774), .Y(n1772) );
BUFX4TS U625 ( .A(n1757), .Y(n1769) );
BUFX4TS U626 ( .A(n626), .Y(n1760) );
CLKBUFX3TS U627 ( .A(n1386), .Y(n1657) );
CLKBUFX3TS U628 ( .A(n1386), .Y(n1493) );
OR3X1TS U629 ( .A(Op_MX[10]), .B(Op_MX[9]), .C(n1666), .Y(n408) );
OR2X1TS U630 ( .A(FSM_selector_C), .B(n1328), .Y(n409) );
NOR2X1TS U631 ( .A(n1325), .B(Op_MX[3]), .Y(n410) );
OR2X1TS U632 ( .A(Op_MX[1]), .B(n1693), .Y(n414) );
OR2X1TS U633 ( .A(n1076), .B(n1077), .Y(n416) );
OR2X1TS U634 ( .A(n1274), .B(n1573), .Y(n417) );
OR2X1TS U635 ( .A(Op_MX[3]), .B(n811), .Y(n418) );
OR3X1TS U636 ( .A(n1156), .B(n685), .C(n684), .Y(n419) );
OR2X1TS U637 ( .A(Op_MX[5]), .B(n802), .Y(n420) );
OR2X1TS U638 ( .A(n1723), .B(n1038), .Y(n421) );
OR2X1TS U639 ( .A(Op_MX[7]), .B(n1038), .Y(n422) );
AND3X1TS U640 ( .A(Op_MX[16]), .B(Op_MX[15]), .C(n1706), .Y(n424) );
OR2X1TS U641 ( .A(n1706), .B(n740), .Y(n425) );
OR3X1TS U642 ( .A(n1007), .B(n690), .C(n689), .Y(n426) );
OR3X1TS U643 ( .A(Op_MX[17]), .B(Op_MX[18]), .C(n1725), .Y(n427) );
OR2X1TS U644 ( .A(Op_MX[19]), .B(n1513), .Y(n428) );
OR2X1TS U645 ( .A(Op_MX[15]), .B(n1314), .Y(n429) );
OR2X1TS U646 ( .A(n1724), .B(n1045), .Y(n432) );
AND3X1TS U647 ( .A(Op_MX[19]), .B(Op_MX[20]), .C(n1724), .Y(n433) );
NAND2X1TS U648 ( .A(n991), .B(Op_MX[11]), .Y(n1556) );
OR3X1TS U649 ( .A(n1274), .B(n665), .C(n664), .Y(n434) );
AO21X1TS U650 ( .A0(n680), .A1(Op_MY[11]), .B0(n576), .Y(n436) );
OR3X1TS U651 ( .A(Op_MX[11]), .B(n1699), .C(n1671), .Y(n437) );
OR2X1TS U652 ( .A(Op_MX[9]), .B(n1025), .Y(n438) );
INVX2TS U653 ( .A(n437), .Y(n439) );
INVX2TS U654 ( .A(n420), .Y(n445) );
INVX2TS U655 ( .A(n438), .Y(n448) );
INVX2TS U656 ( .A(n409), .Y(n449) );
INVX2TS U657 ( .A(n409), .Y(n450) );
INVX2TS U658 ( .A(n429), .Y(n451) );
INVX2TS U659 ( .A(n414), .Y(n453) );
INVX2TS U660 ( .A(n418), .Y(n455) );
INVX2TS U661 ( .A(n422), .Y(n458) );
INVX2TS U662 ( .A(n735), .Y(n459) );
INVX2TS U663 ( .A(n735), .Y(n460) );
INVX2TS U664 ( .A(n1292), .Y(n461) );
INVX2TS U665 ( .A(clk), .Y(n462) );
INVX2TS U666 ( .A(Op_MY[5]), .Y(n465) );
INVX2TS U667 ( .A(Op_MY[5]), .Y(n466) );
INVX2TS U668 ( .A(Op_MY[9]), .Y(n467) );
INVX2TS U669 ( .A(Op_MY[9]), .Y(n468) );
INVX2TS U670 ( .A(Op_MY[2]), .Y(n469) );
INVX2TS U671 ( .A(Op_MY[2]), .Y(n470) );
INVX2TS U672 ( .A(Op_MY[10]), .Y(n471) );
INVX2TS U673 ( .A(Op_MY[10]), .Y(n472) );
INVX2TS U674 ( .A(n1676), .Y(n473) );
INVX2TS U675 ( .A(n473), .Y(n474) );
INVX2TS U676 ( .A(n427), .Y(n475) );
INVX2TS U677 ( .A(n424), .Y(n477) );
INVX2TS U678 ( .A(n433), .Y(n479) );
INVX2TS U679 ( .A(n425), .Y(n481) );
INVX2TS U680 ( .A(n432), .Y(n483) );
INVX2TS U681 ( .A(n396), .Y(n485) );
INVX2TS U682 ( .A(n396), .Y(n486) );
INVX2TS U683 ( .A(n399), .Y(n487) );
INVX2TS U684 ( .A(n412), .Y(n489) );
INVX2TS U685 ( .A(n412), .Y(n490) );
INVX2TS U686 ( .A(n435), .Y(n491) );
INVX2TS U687 ( .A(n435), .Y(n492) );
INVX2TS U688 ( .A(n411), .Y(n493) );
INVX2TS U689 ( .A(n411), .Y(n494) );
INVX2TS U690 ( .A(n413), .Y(n495) );
INVX2TS U691 ( .A(n413), .Y(n496) );
INVX2TS U692 ( .A(n431), .Y(n497) );
INVX2TS U693 ( .A(n431), .Y(n498) );
INVX2TS U694 ( .A(n401), .Y(n501) );
INVX2TS U695 ( .A(n1559), .Y(n504) );
INVX2TS U696 ( .A(n504), .Y(n505) );
INVX2TS U697 ( .A(n504), .Y(n506) );
INVX2TS U698 ( .A(n766), .Y(n507) );
INVX2TS U699 ( .A(n766), .Y(n508) );
INVX2TS U700 ( .A(n1564), .Y(n509) );
INVX2TS U701 ( .A(n1560), .Y(n510) );
INVX2TS U702 ( .A(n1279), .Y(n511) );
INVX2TS U703 ( .A(n1566), .Y(n512) );
INVX2TS U704 ( .A(n1295), .Y(n513) );
INVX2TS U705 ( .A(n395), .Y(n514) );
INVX2TS U706 ( .A(n395), .Y(n515) );
INVX2TS U707 ( .A(n408), .Y(n516) );
INVX2TS U708 ( .A(Op_MY[12]), .Y(n518) );
INVX2TS U709 ( .A(Op_MY[12]), .Y(n519) );
INVX2TS U710 ( .A(Op_MY[1]), .Y(n520) );
INVX2TS U711 ( .A(Op_MY[1]), .Y(n521) );
INVX2TS U712 ( .A(n1270), .Y(n522) );
INVX2TS U713 ( .A(n522), .Y(n523) );
INVX2TS U714 ( .A(n1568), .Y(n524) );
INVX2TS U715 ( .A(n524), .Y(n525) );
INVX2TS U716 ( .A(n1260), .Y(n526) );
INVX2TS U717 ( .A(n526), .Y(n527) );
INVX2TS U718 ( .A(n1297), .Y(n528) );
INVX2TS U719 ( .A(n528), .Y(n529) );
INVX2TS U720 ( .A(n400), .Y(n530) );
INVX2TS U721 ( .A(n400), .Y(n531) );
INVX2TS U722 ( .A(n419), .Y(n532) );
INVX2TS U723 ( .A(n419), .Y(n533) );
INVX2TS U724 ( .A(n416), .Y(n535) );
INVX2TS U725 ( .A(n416), .Y(n536) );
INVX2TS U726 ( .A(n397), .Y(n537) );
INVX2TS U727 ( .A(n397), .Y(n538) );
INVX2TS U728 ( .A(n398), .Y(n539) );
INVX2TS U729 ( .A(n398), .Y(n540) );
INVX2TS U730 ( .A(n1568), .Y(n541) );
INVX2TS U731 ( .A(n1260), .Y(n542) );
INVX2TS U732 ( .A(n1270), .Y(n543) );
INVX2TS U733 ( .A(n1297), .Y(n544) );
INVX2TS U734 ( .A(n1268), .Y(n545) );
INVX2TS U735 ( .A(n545), .Y(n546) );
INVX2TS U736 ( .A(n1295), .Y(n547) );
INVX2TS U737 ( .A(n547), .Y(n548) );
INVX2TS U738 ( .A(n1279), .Y(n549) );
INVX2TS U739 ( .A(n549), .Y(n550) );
INVX2TS U740 ( .A(n1564), .Y(n551) );
INVX2TS U741 ( .A(n551), .Y(n552) );
INVX2TS U742 ( .A(n1560), .Y(n553) );
INVX2TS U743 ( .A(n553), .Y(n554) );
INVX2TS U744 ( .A(n434), .Y(n555) );
INVX2TS U745 ( .A(n434), .Y(n556) );
INVX2TS U746 ( .A(n426), .Y(n557) );
INVX2TS U747 ( .A(n426), .Y(n558) );
INVX2TS U748 ( .A(n1662), .Y(n559) );
INVX2TS U749 ( .A(n1662), .Y(n560) );
INVX2TS U750 ( .A(n1665), .Y(n561) );
INVX2TS U751 ( .A(n1665), .Y(n562) );
INVX2TS U752 ( .A(n1674), .Y(n563) );
INVX2TS U753 ( .A(n1674), .Y(n564) );
INVX2TS U754 ( .A(n1675), .Y(n565) );
INVX2TS U755 ( .A(n1675), .Y(n566) );
INVX2TS U756 ( .A(n1673), .Y(n567) );
INVX2TS U757 ( .A(n1673), .Y(n568) );
INVX2TS U758 ( .A(n1292), .Y(n570) );
INVX2TS U759 ( .A(n570), .Y(n571) );
INVX2TS U760 ( .A(n1566), .Y(n575) );
INVX2TS U761 ( .A(n575), .Y(n576) );
INVX2TS U762 ( .A(n575), .Y(n577) );
INVX2TS U763 ( .A(n1556), .Y(n578) );
INVX2TS U764 ( .A(n578), .Y(n579) );
INVX2TS U765 ( .A(n578), .Y(n580) );
INVX2TS U766 ( .A(n1663), .Y(n585) );
INVX2TS U767 ( .A(n1663), .Y(n586) );
INVX2TS U768 ( .A(n1691), .Y(n589) );
INVX2TS U769 ( .A(n405), .Y(n590) );
INVX2TS U770 ( .A(n405), .Y(n591) );
INVX2TS U771 ( .A(n405), .Y(n592) );
INVX2TS U772 ( .A(n406), .Y(n593) );
INVX2TS U773 ( .A(n406), .Y(n594) );
INVX2TS U774 ( .A(n406), .Y(n595) );
NOR2X1TS U775 ( .A(Op_MY[22]), .B(n1554), .Y(DP_OP_110J126_122_4535_n1067)
);
NOR2X1TS U776 ( .A(n621), .B(n997), .Y(DP_OP_110J126_122_4535_n697) );
NAND2X2TS U777 ( .A(n907), .B(n1274), .Y(n1069) );
BUFX4TS U778 ( .A(n626), .Y(n1763) );
CLKBUFX3TS U779 ( .A(n463), .Y(n627) );
OAI221X1TS U780 ( .A0(n588), .A1(n500), .B0(n1689), .B1(n479), .C0(n402),
.Y(n1512) );
OAI221X1TS U781 ( .A0(Op_MY[21]), .A1(n1516), .B0(n1687), .B1(n1515), .C0(
n1514), .Y(n1517) );
OAI221X1TS U782 ( .A0(n569), .A1(n1516), .B0(n1677), .B1(n1515), .C0(n1190),
.Y(DP_OP_110J126_122_4535_n1104) );
OAI221X1TS U783 ( .A0(Op_MY[17]), .A1(n1516), .B0(n1688), .B1(n1515), .C0(
n1277), .Y(DP_OP_110J126_122_4535_n1101) );
CLKINVX3TS U784 ( .A(n1055), .Y(n1516) );
CLKINVX3TS U785 ( .A(n1132), .Y(n1515) );
OAI221X1TS U786 ( .A0(n613), .A1(n496), .B0(n608), .B1(n634), .C0(n691), .Y(
DP_OP_110J126_122_4535_n292) );
OAI221X1TS U787 ( .A0(n613), .A1(n493), .B0(n608), .B1(n640), .C0(n686), .Y(
DP_OP_110J126_122_4535_n307) );
OAI221X1TS U788 ( .A0(Op_MY[20]), .A1(n500), .B0(n1684), .B1(n479), .C0(n650), .Y(DP_OP_110J126_122_4535_n1083) );
OAI221X1TS U789 ( .A0(Op_MY[17]), .A1(n459), .B0(n1688), .B1(n477), .C0(n655), .Y(DP_OP_110J126_122_4535_n1114) );
OAI221X1TS U790 ( .A0(n572), .A1(n500), .B0(n1686), .B1(n479), .C0(n651),
.Y(DP_OP_110J126_122_4535_n1088) );
OAI221X1TS U791 ( .A0(n584), .A1(n607), .B0(n1682), .B1(n632), .C0(n653),
.Y(DP_OP_110J126_122_4535_n707) );
OAI221X1TS U792 ( .A0(n646), .A1(n459), .B0(n1683), .B1(n477), .C0(n658),
.Y(DP_OP_110J126_122_4535_n1118) );
OAI221X1TS U793 ( .A0(n583), .A1(n622), .B0(n1680), .B1(n1575), .C0(n659),
.Y(DP_OP_110J126_122_4535_n691) );
OAI221X1TS U794 ( .A0(n587), .A1(n1576), .B0(n1678), .B1(n1575), .C0(n656),
.Y(DP_OP_110J126_122_4535_n693) );
OAI221X1TS U795 ( .A0(n582), .A1(n607), .B0(n1679), .B1(n632), .C0(n660),
.Y(DP_OP_110J126_122_4535_n702) );
OAI221X1TS U796 ( .A0(n567), .A1(n607), .B0(n469), .B1(n632), .C0(n654), .Y(
DP_OP_110J126_122_4535_n708) );
OAI221X1TS U797 ( .A0(n561), .A1(n507), .B0(n520), .B1(n1581), .C0(n652),
.Y(DP_OP_110J126_122_4535_n737) );
OAI221X1TS U798 ( .A0(n548), .A1(n633), .B0(n547), .B1(n491), .C0(n666), .Y(
DP_OP_110J126_122_4535_n325) );
OAI221X1TS U799 ( .A0(n527), .A1(n638), .B0(n526), .B1(n489), .C0(n675), .Y(
DP_OP_110J126_122_4535_n285) );
OAI221X1TS U800 ( .A0(n525), .A1(n633), .B0(n541), .B1(n491), .C0(n678), .Y(
DP_OP_110J126_122_4535_n323) );
OAI221X1TS U801 ( .A0(n576), .A1(n534), .B0(n512), .B1(n636), .C0(n1121),
.Y(n1013) );
CLKINVX3TS U802 ( .A(n616), .Y(n1557) );
NOR2X2TS U803 ( .A(n620), .B(n1693), .Y(n1491) );
OAI221X1TS U804 ( .A0(n613), .A1(n534), .B0(n608), .B1(n636), .C0(n1166),
.Y(DP_OP_110J126_122_4535_n261) );
OAI221X1TS U805 ( .A0(Op_MY[16]), .A1(n502), .B0(n1685), .B1(n443), .C0(
n1144), .Y(DP_OP_110J126_122_4535_n1130) );
OAI221X1TS U806 ( .A0(n525), .A1(n636), .B0(n541), .B1(n534), .C0(n1123),
.Y(DP_OP_110J126_122_4535_n262) );
OAI221X1TS U807 ( .A0(Op_MY[16]), .A1(n459), .B0(n1685), .B1(n477), .C0(
n1293), .Y(DP_OP_110J126_122_4535_n1115) );
OAI221X1TS U808 ( .A0(n550), .A1(n638), .B0(n549), .B1(n489), .C0(n1253),
.Y(DP_OP_110J126_122_4535_n284) );
AOI21X2TS U809 ( .A0(n1012), .A1(n1011), .B0(n1010), .Y(n1338) );
NOR2X1TS U810 ( .A(n1011), .B(n1012), .Y(n1010) );
NOR4X1TS U811 ( .A(n581), .B(Op_MY[20]), .C(n582), .D(Op_MY[21]), .Y(n1340)
);
NOR4X1TS U812 ( .A(n572), .B(n569), .C(n565), .D(Op_MY[18]), .Y(n1341) );
OAI211XLTS U813 ( .A0(Sgf_normalized_result[9]), .A1(n1595), .B0(n1613),
.C0(n1594), .Y(n1596) );
NOR2X2TS U814 ( .A(n1711), .B(n1591), .Y(n1595) );
OAI211XLTS U815 ( .A0(Sgf_normalized_result[13]), .A1(n1601), .B0(n1613),
.C0(n1600), .Y(n1602) );
NOR2X2TS U816 ( .A(n1713), .B(n1597), .Y(n1601) );
OAI211XLTS U817 ( .A0(Sgf_normalized_result[17]), .A1(n1607), .B0(n1613),
.C0(n1606), .Y(n1608) );
NOR2X2TS U818 ( .A(n1715), .B(n1603), .Y(n1607) );
OAI211XLTS U819 ( .A0(Sgf_normalized_result[21]), .A1(n1614), .B0(n1613),
.C0(n1612), .Y(n1615) );
NOR2X2TS U820 ( .A(n1717), .B(n1609), .Y(n1614) );
NOR2X2TS U821 ( .A(n1387), .B(DP_OP_110J126_122_4535_n515), .Y(n1631) );
NOR4X1TS U822 ( .A(n587), .B(Op_MY[17]), .C(n563), .D(n583), .Y(n1343) );
NOR2X2TS U823 ( .A(DP_OP_110J126_122_4535_n509), .B(n1624), .Y(n1622) );
NOR2X2TS U824 ( .A(DP_OP_110J126_122_4535_n513), .B(n1630), .Y(n1628) );
NOR4X1TS U825 ( .A(n641), .B(Op_MX[1]), .C(n1355), .D(n1354), .Y(n1356) );
NOR4X1TS U826 ( .A(Op_MY[11]), .B(n588), .C(n589), .D(n1339), .Y(n1347) );
CLKINVX3TS U827 ( .A(n1657), .Y(n1656) );
INVX2TS U828 ( .A(n428), .Y(n597) );
CLKINVX3TS U829 ( .A(n692), .Y(n1326) );
INVX2TS U830 ( .A(n417), .Y(n599) );
BUFX4TS U831 ( .A(n1774), .Y(n1764) );
OAI31X4TS U832 ( .A0(n620), .A1(n922), .A2(n1664), .B0(n921), .Y(n1464) );
AOI21X2TS U833 ( .A0(n1664), .A1(n1693), .B0(n895), .Y(n907) );
NOR3X6TS U834 ( .A(n1085), .B(n1670), .C(n1733), .Y(n1660) );
NOR3X2TS U835 ( .A(Op_MX[15]), .B(Op_MX[16]), .C(n1706), .Y(n735) );
NOR3X2TS U836 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
n1667), .Y(n876) );
BUFX4TS U837 ( .A(n393), .Y(n1765) );
OAI21X2TS U838 ( .A0(Op_MX[1]), .A1(Op_MX[2]), .B0(n1325), .Y(n811) );
CLKBUFX3TS U839 ( .A(n1414), .Y(n1426) );
CLKBUFX3TS U840 ( .A(n1414), .Y(n1478) );
CLKBUFX3TS U841 ( .A(n1414), .Y(n1511) );
NOR2BX1TS U842 ( .AN(n1338), .B(n1122), .Y(n1559) );
INVX2TS U843 ( .A(n421), .Y(n601) );
INVX2TS U844 ( .A(n1577), .Y(n603) );
INVX2TS U845 ( .A(n603), .Y(n604) );
BUFX6TS U846 ( .A(n393), .Y(n1771) );
BUFX4TS U847 ( .A(n1757), .Y(n605) );
BUFX4TS U848 ( .A(n393), .Y(n1767) );
BUFX6TS U849 ( .A(n463), .Y(n626) );
BUFX6TS U850 ( .A(n393), .Y(n1768) );
BUFX6TS U851 ( .A(n393), .Y(n1759) );
BUFX6TS U852 ( .A(n393), .Y(n1770) );
BUFX4TS U853 ( .A(n393), .Y(n1761) );
BUFX4TS U854 ( .A(n463), .Y(n1757) );
CLKINVX6TS U855 ( .A(n462), .Y(n606) );
BUFX6TS U856 ( .A(n393), .Y(n1762) );
BUFX6TS U857 ( .A(n393), .Y(n1756) );
NOR3X2TS U858 ( .A(Op_MX[3]), .B(Op_MX[4]), .C(n1707), .Y(n766) );
INVX2TS U859 ( .A(n613), .Y(n608) );
INVX2TS U860 ( .A(n1268), .Y(n609) );
INVX2TS U861 ( .A(n410), .Y(n610) );
INVX2TS U862 ( .A(n410), .Y(n611) );
NOR2X2TS U863 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n1353) );
INVX2TS U864 ( .A(n436), .Y(n612) );
INVX2TS U865 ( .A(n436), .Y(n613) );
INVX2TS U866 ( .A(n1556), .Y(n614) );
INVX2TS U867 ( .A(n407), .Y(n616) );
INVX2TS U868 ( .A(n407), .Y(n617) );
INVX2TS U869 ( .A(n407), .Y(n618) );
INVX2TS U870 ( .A(n1661), .Y(n619) );
INVX2TS U871 ( .A(n619), .Y(n620) );
INVX2TS U872 ( .A(n619), .Y(n621) );
NOR2X1TS U873 ( .A(n518), .B(n498), .Y(DP_OP_110J126_122_4535_n1078) );
NOR2X2TS U874 ( .A(n1719), .B(n1612), .Y(n1618) );
AOI21X2TS U875 ( .A0(n1369), .A1(n1366), .B0(n1367), .Y(n1362) );
OAI211XLTS U876 ( .A0(Sgf_normalized_result[19]), .A1(n1610), .B0(n1613),
.C0(n1609), .Y(n1611) );
NOR2X2TS U877 ( .A(n1716), .B(n1606), .Y(n1610) );
OAI211XLTS U878 ( .A0(Sgf_normalized_result[15]), .A1(n1604), .B0(n1613),
.C0(n1603), .Y(n1605) );
NOR2X2TS U879 ( .A(n1714), .B(n1600), .Y(n1604) );
OAI211XLTS U880 ( .A0(Sgf_normalized_result[11]), .A1(n1598), .B0(n1613),
.C0(n1597), .Y(n1599) );
NOR2X2TS U881 ( .A(n1712), .B(n1594), .Y(n1598) );
OAI211XLTS U882 ( .A0(Sgf_normalized_result[7]), .A1(n1592), .B0(n1613),
.C0(n1591), .Y(n1593) );
NOR2X2TS U883 ( .A(n1710), .B(n1588), .Y(n1592) );
NOR2X2TS U884 ( .A(DP_OP_110J126_122_4535_n511), .B(n1627), .Y(n1625) );
NOR2X1TS U885 ( .A(n518), .B(n1054), .Y(DP_OP_110J126_122_4535_n1106) );
NOR2X2TS U886 ( .A(n1725), .B(n1054), .Y(n1055) );
OAI21X2TS U887 ( .A0(Op_MX[17]), .A1(Op_MX[18]), .B0(n1513), .Y(n1054) );
NOR2X2TS U888 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1351) );
CLKINVX3TS U889 ( .A(n1493), .Y(n1648) );
CLKINVX3TS U890 ( .A(n692), .Y(n974) );
OAI22X2TS U891 ( .A0(beg_FSM), .A1(n1750), .B0(ack_FSM), .B1(n1079), .Y(
n1333) );
XNOR2X2TS U892 ( .A(DP_OP_110J126_122_4535_n32), .B(n915), .Y(n1635) );
AOI22X2TS U893 ( .A0(Op_MX[13]), .A1(Op_MX[14]), .B0(n1726), .B1(n1668), .Y(
n750) );
OAI21X2TS U894 ( .A0(Op_MX[3]), .A1(Op_MX[4]), .B0(n1524), .Y(n802) );
AOI22X2TS U895 ( .A0(Op_MX[15]), .A1(n1672), .B0(Op_MX[16]), .B1(n1694), .Y(
n740) );
INVX2TS U896 ( .A(n1009), .Y(n622) );
NOR2X2TS U897 ( .A(n1666), .B(n997), .Y(n1009) );
NOR2X2TS U898 ( .A(FS_Module_state_reg[1]), .B(n1733), .Y(n1537) );
CLKBUFX2TS U899 ( .A(n1567), .Y(n623) );
INVX2TS U900 ( .A(n1335), .Y(n624) );
NAND2X2TS U901 ( .A(n876), .B(n1670), .Y(n1335) );
INVX2TS U902 ( .A(n1302), .Y(n625) );
NOR2X2TS U903 ( .A(n1011), .B(n1005), .Y(n1300) );
BUFX4TS U904 ( .A(n463), .Y(n1774) );
CLKBUFX2TS U905 ( .A(n1558), .Y(n628) );
OR2X1TS U906 ( .A(FSM_selector_C), .B(n693), .Y(n1089) );
INVX2TS U907 ( .A(n1089), .Y(n629) );
INVX2TS U908 ( .A(n1089), .Y(n630) );
INVX2TS U909 ( .A(n629), .Y(n715) );
CLKBUFX2TS U910 ( .A(n1257), .Y(n631) );
CLKBUFX2TS U911 ( .A(n1579), .Y(n632) );
NAND2X2TS U912 ( .A(n1156), .B(n1312), .Y(n633) );
AOI21X2TS U913 ( .A0(n665), .A1(n1274), .B0(n662), .Y(n1312) );
CMPR32X4TS U914 ( .A(Op_MX[15]), .B(Op_MX[3]), .C(n668), .CO(n681), .S(n1156) );
CLKAND2X2TS U915 ( .A(n1522), .B(n1076), .Y(n1250) );
INVX2TS U916 ( .A(n1250), .Y(n634) );
INVX2TS U917 ( .A(n1250), .Y(n635) );
AOI21X2TS U918 ( .A0(n690), .A1(n1007), .B0(n688), .Y(n1522) );
CLKBUFX2TS U919 ( .A(n1563), .Y(n636) );
NAND2X4TS U920 ( .A(n1010), .B(n1122), .Y(n1563) );
INVX2TS U921 ( .A(n1064), .Y(n637) );
NAND3X1TS U922 ( .A(Op_MX[5]), .B(Op_MX[6]), .C(n1723), .Y(n1304) );
NAND2X2TS U923 ( .A(n1011), .B(n1337), .Y(n638) );
AOI21X2TS U924 ( .A0(n674), .A1(n1076), .B0(n671), .Y(n1337) );
CMPR32X4TS U925 ( .A(Op_MX[21]), .B(Op_MX[9]), .C(n912), .CO(n990), .S(n1011) );
CLKAND2X2TS U926 ( .A(n899), .B(n1007), .Y(n1266) );
INVX2TS U927 ( .A(n1266), .Y(n639) );
INVX2TS U928 ( .A(n1266), .Y(n640) );
AOI21X2TS U929 ( .A0(n685), .A1(n1156), .B0(n682), .Y(n899) );
INVX2TS U930 ( .A(n1666), .Y(n641) );
OAI21X2TS U931 ( .A0(n991), .A1(Op_MX[11]), .B0(n579), .Y(n1122) );
NAND3X2TS U932 ( .A(Op_MX[3]), .B(n1669), .C(n1718), .Y(n642) );
CLKBUFX3TS U933 ( .A(Op_MY[20]), .Y(n643) );
CLKBUFX3TS U934 ( .A(Op_MY[16]), .Y(n644) );
CLKBUFX3TS U935 ( .A(Op_MY[18]), .Y(n645) );
CLKBUFX3TS U936 ( .A(Op_MY[13]), .Y(n646) );
NOR2XLTS U937 ( .A(n1666), .B(n472), .Y(n877) );
INVX2TS U938 ( .A(DP_OP_110J126_122_4535_n977), .Y(n761) );
OAI21XLTS U939 ( .A0(FSM_selector_B[0]), .A1(n1416), .B0(n1423), .Y(n1417)
);
OAI21XLTS U940 ( .A0(n1618), .A1(Sgf_normalized_result[23]), .B0(n1617), .Y(
n1619) );
OAI211XLTS U941 ( .A0(n1695), .A1(n1335), .B0(n1326), .C0(n1087), .Y(n380)
);
INVX2TS U942 ( .A(rst), .Y(n167) );
BUFX3TS U943 ( .A(n167), .Y(n1751) );
BUFX3TS U944 ( .A(n167), .Y(n1754) );
BUFX3TS U945 ( .A(n167), .Y(n1753) );
NOR2X1TS U946 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1321) );
NAND3X2TS U947 ( .A(n1733), .B(n1321), .C(n1670), .Y(n648) );
BUFX3TS U948 ( .A(n648), .Y(n1735) );
CLKBUFX2TS U949 ( .A(n648), .Y(n712) );
BUFX3TS U950 ( .A(n712), .Y(n1746) );
BUFX3TS U951 ( .A(n712), .Y(n1744) );
BUFX3TS U952 ( .A(n167), .Y(n1752) );
BUFX3TS U953 ( .A(n648), .Y(n1734) );
BUFX3TS U954 ( .A(n712), .Y(n1740) );
BUFX3TS U955 ( .A(n712), .Y(n1745) );
BUFX3TS U956 ( .A(n648), .Y(n1747) );
BUFX3TS U957 ( .A(n648), .Y(n1749) );
BUFX3TS U958 ( .A(n648), .Y(n1748) );
BUFX3TS U959 ( .A(n648), .Y(n1737) );
BUFX3TS U960 ( .A(n712), .Y(n1742) );
BUFX3TS U961 ( .A(n712), .Y(n1741) );
NAND2X1TS U962 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n1524) );
AOI22X1TS U963 ( .A0(n583), .A1(n445), .B0(n539), .B1(n1680), .Y(n649) );
AO21X1TS U964 ( .A0(Op_MX[20]), .A1(Op_MX[19]), .B0(n1351), .Y(n1045) );
AOI22X1TS U965 ( .A0(n573), .A1(n391), .B0(n483), .B1(n1687), .Y(n650) );
AOI22X1TS U966 ( .A0(n644), .A1(n391), .B0(n483), .B1(n1685), .Y(n651) );
AOI22X1TS U967 ( .A0(n567), .A1(n445), .B0(n539), .B1(n469), .Y(n652) );
OR2X1TS U968 ( .A(Op_MX[8]), .B(Op_MX[7]), .Y(n1348) );
INVX2TS U969 ( .A(n988), .Y(n1580) );
NAND2X1TS U970 ( .A(Op_MX[7]), .B(Op_MX[8]), .Y(n1330) );
NAND2BX2TS U971 ( .AN(n1330), .B(n1671), .Y(n1579) );
NAND2X1TS U972 ( .A(n1348), .B(n1330), .Y(n1025) );
NOR2X4TS U973 ( .A(n1671), .B(n1025), .Y(n1577) );
AOI22X1TS U974 ( .A0(n587), .A1(n447), .B0(n604), .B1(n1678), .Y(n653) );
AOI22X1TS U975 ( .A0(n584), .A1(n447), .B0(n604), .B1(n1682), .Y(n654) );
AOI22X1TS U976 ( .A0(n645), .A1(n392), .B0(n481), .B1(n1690), .Y(n655) );
NOR2X1TS U977 ( .A(Op_MX[10]), .B(Op_MX[9]), .Y(n1350) );
NAND2X1TS U978 ( .A(Op_MX[10]), .B(Op_MX[9]), .Y(n881) );
NAND2BX1TS U979 ( .AN(n1350), .B(n881), .Y(n997) );
INVX2TS U980 ( .A(n1009), .Y(n1576) );
NAND2BX2TS U981 ( .AN(n997), .B(n1666), .Y(n1575) );
AOI22X1TS U982 ( .A0(n584), .A1(n439), .B0(n516), .B1(n1682), .Y(n656) );
AOI22X1TS U983 ( .A0(n572), .A1(n391), .B0(n483), .B1(n1686), .Y(n657) );
AOI22X1TS U984 ( .A0(n569), .A1(n392), .B0(n481), .B1(n1677), .Y(n658) );
AOI22X1TS U985 ( .A0(n563), .A1(n439), .B0(n517), .B1(n465), .Y(n659) );
AOI22X1TS U986 ( .A0(n565), .A1(n447), .B0(n604), .B1(n467), .Y(n660) );
NOR2X1TS U987 ( .A(n518), .B(n621), .Y(n898) );
NOR2X1TS U988 ( .A(n1664), .B(n1693), .Y(n895) );
CMPR32X2TS U989 ( .A(Op_MX[14]), .B(Op_MX[2]), .C(n661), .CO(n668), .S(n665)
);
NOR2XLTS U990 ( .A(n1274), .B(n665), .Y(n662) );
NAND2X2TS U991 ( .A(n1156), .B(n1312), .Y(n1570) );
INVX2TS U992 ( .A(n1156), .Y(n664) );
NAND2X1TS U993 ( .A(n1274), .B(n665), .Y(n1157) );
NOR2X4TS U994 ( .A(n1156), .B(n1157), .Y(n1567) );
AOI22X1TS U995 ( .A0(n571), .A1(n1567), .B0(n555), .B1(n461), .Y(n666) );
CMPR32X2TS U996 ( .A(Op_MX[20]), .B(Op_MX[8]), .C(n669), .CO(n912), .S(n674)
);
NOR2XLTS U997 ( .A(n1076), .B(n674), .Y(n671) );
NAND2X2TS U998 ( .A(n1011), .B(n1337), .Y(n1301) );
INVX2TS U999 ( .A(n1011), .Y(n673) );
NAND2X1TS U1000 ( .A(n1076), .B(n674), .Y(n1005) );
AOI22X1TS U1001 ( .A0(n523), .A1(n1300), .B0(n530), .B1(n522), .Y(n675) );
AOI22X1TS U1002 ( .A0(n529), .A1(n1567), .B0(n555), .B1(n528), .Y(n678) );
CMPR32X2TS U1003 ( .A(Op_MX[16]), .B(Op_MX[4]), .C(n681), .CO(n683), .S(n685) );
NOR2XLTS U1004 ( .A(n1156), .B(n685), .Y(n682) );
INVX2TS U1005 ( .A(n1007), .Y(n684) );
INVX2TS U1006 ( .A(n612), .Y(n1571) );
NAND2X1TS U1007 ( .A(n1156), .B(n685), .Y(n1006) );
AOI22X1TS U1008 ( .A0(n525), .A1(n537), .B0(n532), .B1(n541), .Y(n686) );
CMPR32X2TS U1009 ( .A(Op_MX[18]), .B(Op_MX[6]), .C(n687), .CO(n670), .S(n690) );
NOR2XLTS U1010 ( .A(n1007), .B(n690), .Y(n688) );
INVX2TS U1011 ( .A(n1076), .Y(n689) );
NAND2X1TS U1012 ( .A(n1007), .B(n690), .Y(n1077) );
AOI22X1TS U1013 ( .A0(n525), .A1(n535), .B0(n557), .B1(n541), .Y(n691) );
NOR2X1TS U1014 ( .A(FS_Module_state_reg[3]), .B(n1667), .Y(n1071) );
NAND2X1TS U1015 ( .A(FS_Module_state_reg[3]), .B(n1667), .Y(n1085) );
NOR2X2TS U1016 ( .A(FS_Module_state_reg[0]), .B(n1085), .Y(n1582) );
AOI32X2TS U1017 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1582), .B0(n876), .B1(FS_Module_state_reg[1]), .Y(n1328) );
NAND2X1TS U1018 ( .A(n692), .B(n1328), .Y(n693) );
AOI22X1TS U1019 ( .A0(Sgf_normalized_result[6]), .A1(n1326), .B0(
Add_result[7]), .B1(n590), .Y(n695) );
AOI22X1TS U1020 ( .A0(Add_result[6]), .A1(n593), .B0(n449), .B1(P_Sgf[30]),
.Y(n694) );
OAI211XLTS U1021 ( .A0(n715), .A1(n1704), .B0(n695), .C0(n694), .Y(n208) );
AOI22X1TS U1022 ( .A0(Sgf_normalized_result[8]), .A1(n974), .B0(
Add_result[9]), .B1(n590), .Y(n697) );
AOI22X1TS U1023 ( .A0(Add_result[8]), .A1(n593), .B0(n449), .B1(P_Sgf[32]),
.Y(n696) );
OAI211XLTS U1024 ( .A0(n715), .A1(n1703), .B0(n697), .C0(n696), .Y(n210) );
AOI22X1TS U1025 ( .A0(Sgf_normalized_result[10]), .A1(n974), .B0(
Add_result[11]), .B1(n591), .Y(n699) );
AOI22X1TS U1026 ( .A0(Add_result[10]), .A1(n593), .B0(n449), .B1(P_Sgf[34]),
.Y(n698) );
OAI211XLTS U1027 ( .A0(n715), .A1(n1702), .B0(n699), .C0(n698), .Y(n212) );
AOI22X1TS U1028 ( .A0(Sgf_normalized_result[12]), .A1(n974), .B0(
Add_result[13]), .B1(n592), .Y(n701) );
AOI22X1TS U1029 ( .A0(Add_result[12]), .A1(n593), .B0(n449), .B1(P_Sgf[36]),
.Y(n700) );
OAI211XLTS U1030 ( .A0(n715), .A1(n1701), .B0(n701), .C0(n700), .Y(n214) );
AOI22X1TS U1031 ( .A0(Sgf_normalized_result[14]), .A1(n974), .B0(
Add_result[15]), .B1(n591), .Y(n703) );
AOI22X1TS U1032 ( .A0(Add_result[14]), .A1(n593), .B0(P_Sgf[38]), .B1(n450),
.Y(n702) );
OAI211XLTS U1033 ( .A0(n715), .A1(n1700), .B0(n703), .C0(n702), .Y(n216) );
AOI22X1TS U1034 ( .A0(Sgf_normalized_result[16]), .A1(n974), .B0(
Add_result[17]), .B1(n592), .Y(n705) );
AOI22X1TS U1035 ( .A0(Add_result[16]), .A1(n594), .B0(P_Sgf[40]), .B1(n450),
.Y(n704) );
OAI211XLTS U1036 ( .A0(n1698), .A1(n715), .B0(n705), .C0(n704), .Y(n218) );
INVX2TS U1037 ( .A(n692), .Y(n1088) );
AOI22X1TS U1038 ( .A0(Sgf_normalized_result[18]), .A1(n1088), .B0(
Add_result[19]), .B1(n591), .Y(n707) );
AOI22X1TS U1039 ( .A0(Add_result[18]), .A1(n595), .B0(P_Sgf[42]), .B1(n450),
.Y(n706) );
OAI211XLTS U1040 ( .A0(n1697), .A1(n715), .B0(n707), .C0(n706), .Y(n220) );
AOI22X1TS U1041 ( .A0(Sgf_normalized_result[20]), .A1(n1088), .B0(
Add_result[21]), .B1(n591), .Y(n709) );
AOI22X1TS U1042 ( .A0(Add_result[20]), .A1(n594), .B0(P_Sgf[44]), .B1(n450),
.Y(n708) );
OAI211XLTS U1043 ( .A0(n1696), .A1(n715), .B0(n709), .C0(n708), .Y(n222) );
AOI22X1TS U1044 ( .A0(Sgf_normalized_result[4]), .A1(n1326), .B0(n590), .B1(
Add_result[5]), .Y(n711) );
AOI22X1TS U1045 ( .A0(n593), .A1(Add_result[4]), .B0(n450), .B1(P_Sgf[28]),
.Y(n710) );
OAI211XLTS U1046 ( .A0(n715), .A1(n1705), .B0(n711), .C0(n710), .Y(n206) );
CLKBUFX2TS U1047 ( .A(n712), .Y(n1750) );
AOI22X1TS U1048 ( .A0(Sgf_normalized_result[2]), .A1(n1326), .B0(n590), .B1(
Add_result[3]), .Y(n714) );
AOI22X1TS U1049 ( .A0(n593), .A1(Add_result[2]), .B0(n450), .B1(P_Sgf[26]),
.Y(n713) );
OAI211XLTS U1050 ( .A0(n1720), .A1(n715), .B0(n714), .C0(n713), .Y(n204) );
INVX2TS U1051 ( .A(n449), .Y(n1092) );
AOI22X1TS U1052 ( .A0(Sgf_normalized_result[19]), .A1(n1088), .B0(
Add_result[20]), .B1(n592), .Y(n717) );
AOI22X1TS U1053 ( .A0(Add_result[19]), .A1(n595), .B0(P_Sgf[42]), .B1(n630),
.Y(n716) );
OAI211XLTS U1054 ( .A0(n1696), .A1(n1092), .B0(n717), .C0(n716), .Y(n221) );
AOI22X1TS U1055 ( .A0(Sgf_normalized_result[17]), .A1(n1088), .B0(
Add_result[18]), .B1(n592), .Y(n719) );
AOI22X1TS U1056 ( .A0(Add_result[17]), .A1(n594), .B0(P_Sgf[40]), .B1(n629),
.Y(n718) );
OAI211XLTS U1057 ( .A0(n1697), .A1(n1092), .B0(n719), .C0(n718), .Y(n219) );
INVX2TS U1058 ( .A(n1335), .Y(DP_OP_36J126_123_9196_n33) );
AOI22X1TS U1059 ( .A0(Sgf_normalized_result[15]), .A1(n974), .B0(
Add_result[16]), .B1(n591), .Y(n721) );
AOI22X1TS U1060 ( .A0(Add_result[15]), .A1(n595), .B0(P_Sgf[38]), .B1(n630),
.Y(n720) );
OAI211XLTS U1061 ( .A0(n1698), .A1(n409), .B0(n721), .C0(n720), .Y(n217) );
AOI22X1TS U1062 ( .A0(Sgf_normalized_result[13]), .A1(n974), .B0(
Add_result[14]), .B1(n592), .Y(n723) );
AOI22X1TS U1063 ( .A0(Add_result[13]), .A1(n594), .B0(n630), .B1(P_Sgf[36]),
.Y(n722) );
OAI211XLTS U1064 ( .A0(n1092), .A1(n1700), .B0(n723), .C0(n722), .Y(n215) );
AOI22X1TS U1065 ( .A0(Sgf_normalized_result[11]), .A1(n974), .B0(
Add_result[12]), .B1(n591), .Y(n725) );
AOI22X1TS U1066 ( .A0(Add_result[11]), .A1(n595), .B0(n629), .B1(P_Sgf[34]),
.Y(n724) );
OAI211XLTS U1067 ( .A0(n1092), .A1(n1701), .B0(n725), .C0(n724), .Y(n213) );
AOI22X1TS U1068 ( .A0(Sgf_normalized_result[9]), .A1(n974), .B0(
Add_result[10]), .B1(n592), .Y(n727) );
AOI22X1TS U1069 ( .A0(Add_result[9]), .A1(n594), .B0(n630), .B1(P_Sgf[32]),
.Y(n726) );
OAI211XLTS U1070 ( .A0(n1092), .A1(n1702), .B0(n727), .C0(n726), .Y(n211) );
AOI22X1TS U1071 ( .A0(Sgf_normalized_result[7]), .A1(n1326), .B0(
Add_result[8]), .B1(n591), .Y(n729) );
AOI22X1TS U1072 ( .A0(Add_result[7]), .A1(n595), .B0(n629), .B1(P_Sgf[30]),
.Y(n728) );
OAI211XLTS U1073 ( .A0(n1092), .A1(n1703), .B0(n729), .C0(n728), .Y(n209) );
AOI22X1TS U1074 ( .A0(Sgf_normalized_result[5]), .A1(n1326), .B0(
Add_result[6]), .B1(n591), .Y(n731) );
AOI22X1TS U1075 ( .A0(n630), .A1(P_Sgf[28]), .B0(n595), .B1(Add_result[5]),
.Y(n730) );
OAI211XLTS U1076 ( .A0(n1092), .A1(n1704), .B0(n731), .C0(n730), .Y(n207) );
AOI22X1TS U1077 ( .A0(Sgf_normalized_result[3]), .A1(n1326), .B0(n590), .B1(
Add_result[4]), .Y(n733) );
AOI22X1TS U1078 ( .A0(n629), .A1(P_Sgf[26]), .B0(n594), .B1(Add_result[3]),
.Y(n732) );
OAI211XLTS U1079 ( .A0(n1092), .A1(n1705), .B0(n733), .C0(n732), .Y(n205) );
NOR2X4TS U1080 ( .A(Op_MX[13]), .B(n1664), .Y(n1309) );
NAND2X2TS U1081 ( .A(Op_MX[13]), .B(n1664), .Y(n1046) );
NOR2X2TS U1082 ( .A(n1664), .B(n1668), .Y(n1520) );
INVX2TS U1083 ( .A(n1520), .Y(n1311) );
OAI22X1TS U1084 ( .A0(Op_MY[16]), .A1(n1046), .B0(Op_MY[17]), .B1(n1311),
.Y(n734) );
AOI21X1TS U1085 ( .A0(n1309), .A1(n574), .B0(n734), .Y(n754) );
AOI21X1TS U1086 ( .A0(n482), .A1(n519), .B0(n735), .Y(n755) );
NOR2X1TS U1087 ( .A(n754), .B(n755), .Y(DP_OP_110J126_122_4535_n1047) );
INVX2TS U1088 ( .A(DP_OP_110J126_122_4535_n947), .Y(n864) );
INVX2TS U1089 ( .A(DP_OP_110J126_122_4535_n951), .Y(n863) );
INVX2TS U1090 ( .A(DP_OP_110J126_122_4535_n952), .Y(n861) );
INVX2TS U1091 ( .A(DP_OP_110J126_122_4535_n956), .Y(n860) );
INVX2TS U1092 ( .A(DP_OP_110J126_122_4535_n963), .Y(n758) );
INVX2TS U1093 ( .A(DP_OP_110J126_122_4535_n957), .Y(n757) );
INVX2TS U1094 ( .A(DP_OP_110J126_122_4535_n969), .Y(n858) );
INVX2TS U1095 ( .A(DP_OP_110J126_122_4535_n964), .Y(n857) );
INVX2TS U1096 ( .A(DP_OP_110J126_122_4535_n970), .Y(n760) );
INVX2TS U1097 ( .A(DP_OP_110J126_122_4535_n985), .Y(n855) );
INVX2TS U1098 ( .A(DP_OP_110J126_122_4535_n978), .Y(n854) );
INVX2TS U1099 ( .A(DP_OP_110J126_122_4535_n995), .Y(n852) );
INVX2TS U1100 ( .A(DP_OP_110J126_122_4535_n986), .Y(n851) );
INVX2TS U1101 ( .A(DP_OP_110J126_122_4535_n1004), .Y(n764) );
INVX2TS U1102 ( .A(DP_OP_110J126_122_4535_n996), .Y(n763) );
INVX2TS U1103 ( .A(DP_OP_110J126_122_4535_n1012), .Y(n773) );
INVX2TS U1104 ( .A(DP_OP_110J126_122_4535_n1005), .Y(n772) );
INVX2TS U1105 ( .A(DP_OP_110J126_122_4535_n1020), .Y(n776) );
INVX2TS U1106 ( .A(DP_OP_110J126_122_4535_n1013), .Y(n775) );
INVX2TS U1107 ( .A(DP_OP_110J126_122_4535_n1026), .Y(n779) );
INVX2TS U1108 ( .A(DP_OP_110J126_122_4535_n1021), .Y(n778) );
INVX2TS U1109 ( .A(DP_OP_110J126_122_4535_n1033), .Y(n782) );
INVX2TS U1110 ( .A(DP_OP_110J126_122_4535_n1027), .Y(n781) );
INVX2TS U1111 ( .A(DP_OP_110J126_122_4535_n1038), .Y(n785) );
INVX2TS U1112 ( .A(DP_OP_110J126_122_4535_n1034), .Y(n784) );
INVX2TS U1113 ( .A(DP_OP_110J126_122_4535_n1043), .Y(n788) );
INVX2TS U1114 ( .A(DP_OP_110J126_122_4535_n1039), .Y(n787) );
INVX2TS U1115 ( .A(DP_OP_110J126_122_4535_n1044), .Y(n849) );
AOI22X1TS U1116 ( .A0(n559), .A1(n477), .B0(n459), .B1(n518), .Y(n736) );
NAND2X1TS U1117 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n1314) );
AOI22X1TS U1118 ( .A0(Op_MY[15]), .A1(n443), .B0(n502), .B1(n1686), .Y(n737)
);
OAI22X1TS U1119 ( .A0(Op_MY[15]), .A1(n1046), .B0(n644), .B1(n1311), .Y(n738) );
AOI21X1TS U1120 ( .A0(n1309), .A1(Op_MY[16]), .B0(n738), .Y(n753) );
AOI22X1TS U1121 ( .A0(n569), .A1(n443), .B0(n502), .B1(n1677), .Y(n739) );
AOI221X1TS U1122 ( .A0(n451), .A1(n646), .B0(n514), .B1(n1683), .C0(n739),
.Y(n752) );
NAND2BXLTS U1123 ( .AN(n740), .B(n560), .Y(n751) );
CMPR32X2TS U1124 ( .A(n743), .B(n742), .C(n741), .CO(n848), .S(n791) );
AOI22X1TS U1125 ( .A0(n559), .A1(n451), .B0(n515), .B1(n518), .Y(n744) );
AOI22X1TS U1126 ( .A0(Op_MY[15]), .A1(n1309), .B0(n1520), .B1(n1686), .Y(
n745) );
OAI21X1TS U1127 ( .A0(Op_MY[14]), .A1(n1046), .B0(n745), .Y(n746) );
NAND2X1TS U1128 ( .A(n746), .B(n747), .Y(n793) );
OAI21XLTS U1129 ( .A0(n747), .A1(n746), .B0(n793), .Y(n768) );
AOI2BB1XLTS U1130 ( .A0N(n503), .A1N(n560), .B0(n515), .Y(n767) );
AOI22X1TS U1131 ( .A0(n569), .A1(n1309), .B0(n1520), .B1(n1677), .Y(n748) );
OAI21X1TS U1132 ( .A0(n646), .A1(n1046), .B0(n748), .Y(n796) );
AOI211XLTS U1133 ( .A0(Op_MX[12]), .A1(n646), .B0(n560), .C0(n1668), .Y(n749) );
AO21XLTS U1134 ( .A0(n560), .A1(n750), .B0(n749), .Y(n797) );
NAND2X1TS U1135 ( .A(n796), .B(n797), .Y(n795) );
CMPR32X2TS U1136 ( .A(n753), .B(n752), .C(n751), .CO(n741), .S(n792) );
AO21XLTS U1137 ( .A0(n755), .A1(n754), .B0(DP_OP_110J126_122_4535_n1047),
.Y(n789) );
CMPR32X2TS U1138 ( .A(n758), .B(n757), .C(n756), .CO(n859), .S(
DP_OP_110J126_122_4535_n511) );
CMPR32X2TS U1139 ( .A(n761), .B(n760), .C(n759), .CO(n856), .S(
DP_OP_110J126_122_4535_n513) );
CMPR32X2TS U1140 ( .A(n764), .B(n763), .C(n762), .CO(n850), .S(
DP_OP_110J126_122_4535_n516) );
NOR2X2TS U1141 ( .A(Op_MX[0]), .B(n1669), .Y(n1174) );
INVX2TS U1142 ( .A(n1174), .Y(n1026) );
OAI22X1TS U1143 ( .A0(Op_MY[4]), .A1(n1026), .B0(n563), .B1(n441), .Y(n765)
);
AOI21X1TS U1144 ( .A0(n453), .A1(n564), .B0(n765), .Y(n815) );
AOI21X1TS U1145 ( .A0(n540), .A1(n621), .B0(n766), .Y(n816) );
NOR2X1TS U1146 ( .A(n815), .B(n816), .Y(DP_OP_110J126_122_4535_n665) );
CMPR32X2TS U1147 ( .A(n768), .B(n767), .C(n795), .CO(n794), .S(n1651) );
CLKAND2X2TS U1148 ( .A(n1651), .B(DP_OP_110J126_122_4535_n210), .Y(
DP_OP_110J126_122_4535_n208) );
NAND2X1TS U1149 ( .A(n560), .B(Op_MX[13]), .Y(n770) );
OAI21XLTS U1150 ( .A0(n1683), .A1(n1664), .B0(n770), .Y(n769) );
OAI31X4TS U1151 ( .A0(n1683), .A1(n770), .A2(n1664), .B0(n769), .Y(
DP_OP_110J126_122_4535_n528) );
CMPR32X2TS U1152 ( .A(n773), .B(n772), .C(n771), .CO(n762), .S(
DP_OP_110J126_122_4535_n517) );
CMPR32X2TS U1153 ( .A(n776), .B(n775), .C(n774), .CO(n771), .S(
DP_OP_110J126_122_4535_n518) );
CMPR32X2TS U1154 ( .A(n779), .B(n778), .C(n777), .CO(n774), .S(
DP_OP_110J126_122_4535_n519) );
CMPR32X2TS U1155 ( .A(n782), .B(n781), .C(n780), .CO(n777), .S(
DP_OP_110J126_122_4535_n520) );
CMPR32X2TS U1156 ( .A(n785), .B(n784), .C(n783), .CO(n780), .S(
DP_OP_110J126_122_4535_n521) );
CMPR32X2TS U1157 ( .A(n788), .B(n787), .C(n786), .CO(n783), .S(
DP_OP_110J126_122_4535_n522) );
CMPR32X2TS U1158 ( .A(n791), .B(n790), .C(n789), .CO(n847), .S(
DP_OP_110J126_122_4535_n524) );
CMPR32X2TS U1159 ( .A(n794), .B(n793), .C(n792), .CO(n790), .S(
DP_OP_110J126_122_4535_n525) );
OAI21X1TS U1160 ( .A0(n797), .A1(n796), .B0(n795), .Y(
DP_OP_110J126_122_4535_n527) );
INVX2TS U1161 ( .A(DP_OP_110J126_122_4535_n561), .Y(n885) );
INVX2TS U1162 ( .A(DP_OP_110J126_122_4535_n562), .Y(n819) );
INVX2TS U1163 ( .A(DP_OP_110J126_122_4535_n564), .Y(n818) );
INVX2TS U1164 ( .A(DP_OP_110J126_122_4535_n565), .Y(n822) );
INVX2TS U1165 ( .A(DP_OP_110J126_122_4535_n569), .Y(n821) );
INVX2TS U1166 ( .A(DP_OP_110J126_122_4535_n570), .Y(n825) );
INVX2TS U1167 ( .A(DP_OP_110J126_122_4535_n574), .Y(n824) );
INVX2TS U1168 ( .A(DP_OP_110J126_122_4535_n581), .Y(n828) );
INVX2TS U1169 ( .A(DP_OP_110J126_122_4535_n575), .Y(n827) );
INVX2TS U1170 ( .A(DP_OP_110J126_122_4535_n587), .Y(n846) );
INVX2TS U1171 ( .A(DP_OP_110J126_122_4535_n582), .Y(n845) );
INVX2TS U1172 ( .A(DP_OP_110J126_122_4535_n595), .Y(n831) );
INVX2TS U1173 ( .A(DP_OP_110J126_122_4535_n588), .Y(n830) );
INVX2TS U1174 ( .A(DP_OP_110J126_122_4535_n603), .Y(n834) );
INVX2TS U1175 ( .A(DP_OP_110J126_122_4535_n596), .Y(n833) );
INVX2TS U1176 ( .A(DP_OP_110J126_122_4535_n613), .Y(n837) );
INVX2TS U1177 ( .A(DP_OP_110J126_122_4535_n604), .Y(n836) );
INVX2TS U1178 ( .A(DP_OP_110J126_122_4535_n622), .Y(n843) );
INVX2TS U1179 ( .A(DP_OP_110J126_122_4535_n614), .Y(n842) );
INVX2TS U1180 ( .A(DP_OP_110J126_122_4535_n630), .Y(n840) );
INVX2TS U1181 ( .A(DP_OP_110J126_122_4535_n623), .Y(n839) );
INVX2TS U1182 ( .A(DP_OP_110J126_122_4535_n638), .Y(n1433) );
INVX2TS U1183 ( .A(DP_OP_110J126_122_4535_n631), .Y(n1432) );
INVX2TS U1184 ( .A(DP_OP_110J126_122_4535_n644), .Y(n1445) );
INVX2TS U1185 ( .A(DP_OP_110J126_122_4535_n639), .Y(n1444) );
INVX2TS U1186 ( .A(DP_OP_110J126_122_4535_n651), .Y(n1458) );
INVX2TS U1187 ( .A(DP_OP_110J126_122_4535_n645), .Y(n1457) );
INVX2TS U1188 ( .A(DP_OP_110J126_122_4535_n656), .Y(n1436) );
INVX2TS U1189 ( .A(DP_OP_110J126_122_4535_n652), .Y(n1435) );
INVX2TS U1190 ( .A(DP_OP_110J126_122_4535_n661), .Y(n1448) );
INVX2TS U1191 ( .A(DP_OP_110J126_122_4535_n657), .Y(n1447) );
INVX2TS U1192 ( .A(DP_OP_110J126_122_4535_n662), .Y(n1475) );
AOI22X1TS U1193 ( .A0(Op_MY[0]), .A1(n1581), .B0(n507), .B1(n620), .Y(n798)
);
AOI221X1TS U1194 ( .A0(n445), .A1(n561), .B0(n539), .B1(n520), .C0(n798),
.Y(n805) );
NAND2X1TS U1195 ( .A(Op_MX[1]), .B(Op_MX[2]), .Y(n1325) );
NAND3X2TS U1196 ( .A(Op_MX[3]), .B(n1669), .C(n1718), .Y(n1263) );
AOI22X1TS U1197 ( .A0(n567), .A1(n610), .B0(n1263), .B1(n469), .Y(n799) );
OAI22X1TS U1198 ( .A0(n584), .A1(n1026), .B0(n587), .B1(n441), .Y(n800) );
AOI21X1TS U1199 ( .A0(n454), .A1(Op_MY[4]), .B0(n800), .Y(n814) );
AOI22X1TS U1200 ( .A0(n561), .A1(n610), .B0(n1263), .B1(n520), .Y(n801) );
CMPR32X2TS U1201 ( .A(n805), .B(n804), .C(n803), .CO(n1474), .S(n892) );
AOI22X1TS U1202 ( .A0(n561), .A1(n455), .B0(n485), .B1(n520), .Y(n806) );
AOI22X1TS U1203 ( .A0(n453), .A1(n584), .B0(n1174), .B1(n469), .Y(n807) );
OAI21X1TS U1204 ( .A0(Op_MY[3]), .A1(n442), .B0(n807), .Y(n808) );
NAND2X1TS U1205 ( .A(n808), .B(n809), .Y(n1003) );
OAI21XLTS U1206 ( .A0(n809), .A1(n808), .B0(n1003), .Y(n1319) );
OA21XLTS U1207 ( .A0(n396), .A1(Op_MY[0]), .B0(n642), .Y(n1318) );
AOI22X1TS U1208 ( .A0(n453), .A1(n568), .B0(n1174), .B1(n520), .Y(n810) );
OAI21X1TS U1209 ( .A0(n568), .A1(n442), .B0(n810), .Y(n1073) );
OAI211X1TS U1210 ( .A0(n1693), .A1(n520), .B0(Op_MX[1]), .C0(n620), .Y(n902)
);
OAI21X1TS U1211 ( .A0(n620), .A1(n811), .B0(n902), .Y(n1074) );
NAND2X1TS U1212 ( .A(n1073), .B(n1074), .Y(n1317) );
CMPR32X2TS U1213 ( .A(n814), .B(n813), .C(n812), .CO(n803), .S(n1002) );
AO21XLTS U1214 ( .A0(n816), .A1(n815), .B0(DP_OP_110J126_122_4535_n665), .Y(
n890) );
INVX2TS U1215 ( .A(DP_OP_110J126_122_4535_n560), .Y(n879) );
AOI221X1TS U1216 ( .A0(n439), .A1(Op_MY[11]), .B0(n516), .B1(n1676), .C0(
n1009), .Y(n878) );
CMPR32X2TS U1217 ( .A(n819), .B(n818), .C(n817), .CO(n884), .S(
DP_OP_110J126_122_4535_n217) );
CMPR32X2TS U1218 ( .A(n822), .B(n821), .C(n820), .CO(n817), .S(
DP_OP_110J126_122_4535_n218) );
CMPR32X2TS U1219 ( .A(n825), .B(n824), .C(n823), .CO(n820), .S(
DP_OP_110J126_122_4535_n219) );
CMPR32X2TS U1220 ( .A(n828), .B(n827), .C(n826), .CO(n823), .S(
DP_OP_110J126_122_4535_n220) );
CMPR32X2TS U1221 ( .A(n831), .B(n830), .C(n829), .CO(n844), .S(
DP_OP_110J126_122_4535_n222) );
CMPR32X2TS U1222 ( .A(n834), .B(n833), .C(n832), .CO(n829), .S(
DP_OP_110J126_122_4535_n223) );
CMPR32X2TS U1223 ( .A(n837), .B(n836), .C(n835), .CO(n832), .S(
DP_OP_110J126_122_4535_n224) );
CMPR32X2TS U1224 ( .A(n840), .B(n839), .C(n838), .CO(n841), .S(
DP_OP_110J126_122_4535_n226) );
CMPR32X2TS U1225 ( .A(n843), .B(n842), .C(n841), .CO(n835), .S(
DP_OP_110J126_122_4535_n225) );
CMPR32X2TS U1226 ( .A(n846), .B(n845), .C(n844), .CO(n826), .S(
DP_OP_110J126_122_4535_n221) );
CMPR32X2TS U1227 ( .A(n849), .B(n848), .C(n847), .CO(n786), .S(
DP_OP_110J126_122_4535_n523) );
CMPR32X2TS U1228 ( .A(n852), .B(n851), .C(n850), .CO(n853), .S(
DP_OP_110J126_122_4535_n515) );
CMPR32X2TS U1229 ( .A(n855), .B(n854), .C(n853), .CO(n759), .S(
DP_OP_110J126_122_4535_n514) );
INVX2TS U1230 ( .A(DP_OP_110J126_122_4535_n514), .Y(
Sgf_operation_EVEN1_Q_left[15]) );
CMPR32X2TS U1231 ( .A(n858), .B(n857), .C(n856), .CO(n756), .S(
DP_OP_110J126_122_4535_n512) );
INVX2TS U1232 ( .A(DP_OP_110J126_122_4535_n512), .Y(
Sgf_operation_EVEN1_Q_left[17]) );
CMPR32X2TS U1233 ( .A(n861), .B(n860), .C(n859), .CO(n862), .S(
DP_OP_110J126_122_4535_n510) );
INVX2TS U1234 ( .A(DP_OP_110J126_122_4535_n510), .Y(
Sgf_operation_EVEN1_Q_left[19]) );
INVX2TS U1235 ( .A(DP_OP_110J126_122_4535_n944), .Y(n867) );
INVX2TS U1236 ( .A(DP_OP_110J126_122_4535_n946), .Y(n866) );
CMPR32X2TS U1237 ( .A(n864), .B(n863), .C(n862), .CO(n865), .S(
DP_OP_110J126_122_4535_n509) );
INVX2TS U1238 ( .A(DP_OP_110J126_122_4535_n508), .Y(
Sgf_operation_EVEN1_Q_left[21]) );
INVX2TS U1239 ( .A(DP_OP_110J126_122_4535_n943), .Y(n871) );
INVX2TS U1240 ( .A(DP_OP_110J126_122_4535_n942), .Y(n868) );
NAND2X1TS U1241 ( .A(Op_MX[22]), .B(Op_MX[21]), .Y(n996) );
NOR2X1TS U1242 ( .A(Op_MX[22]), .B(Op_MX[21]), .Y(n995) );
INVX2TS U1243 ( .A(n995), .Y(n1554) );
CMPR32X2TS U1244 ( .A(n867), .B(n866), .C(n865), .CO(n869), .S(
DP_OP_110J126_122_4535_n508) );
CMPR32X2TS U1245 ( .A(n871), .B(n870), .C(n869), .CO(n872), .S(
DP_OP_110J126_122_4535_n507) );
XNOR2X1TS U1246 ( .A(n873), .B(n872), .Y(n874) );
XOR2X1TS U1247 ( .A(n996), .B(n874), .Y(n875) );
CLKXOR2X2TS U1248 ( .A(n588), .B(n875), .Y(DP_OP_110J126_122_4535_n506) );
AOI31X4TS U1249 ( .A0(n1582), .A1(FS_Module_state_reg[1]), .A2(
FSM_add_overflow_flag), .B0(n876), .Y(n1386) );
INVX2TS U1250 ( .A(n1493), .Y(n1484) );
CMPR32X2TS U1251 ( .A(n879), .B(n878), .C(n877), .CO(n889), .S(n883) );
AOI22X1TS U1252 ( .A0(Op_MY[11]), .A1(n585), .B0(n471), .B1(n1676), .Y(n882)
);
OAI21XLTS U1253 ( .A0(n882), .A1(n881), .B0(n641), .Y(n880) );
AOI21X1TS U1254 ( .A0(n882), .A1(n881), .B0(n880), .Y(n887) );
CMPR32X2TS U1255 ( .A(n885), .B(n884), .C(n883), .CO(n886), .S(
DP_OP_110J126_122_4535_n216) );
XOR2X1TS U1256 ( .A(n887), .B(n886), .Y(n888) );
CLKXOR2X2TS U1257 ( .A(n889), .B(n888), .Y(n1502) );
INVX2TS U1258 ( .A(DP_OP_110J126_122_4535_n200), .Y(n1114) );
CMPR32X2TS U1259 ( .A(n892), .B(n891), .C(n890), .CO(n1473), .S(n893) );
INVX2TS U1260 ( .A(n893), .Y(n1459) );
INVX2TS U1261 ( .A(n907), .Y(n1573) );
NAND2X2TS U1262 ( .A(n1274), .B(n1573), .Y(n1257) );
OAI22X1TS U1263 ( .A0(n527), .A1(n1257), .B0(n550), .B1(n1069), .Y(n896) );
AOI21X1TS U1264 ( .A0(n1279), .A1(n599), .B0(n896), .Y(n1034) );
AOI22X1TS U1265 ( .A0(n523), .A1(n491), .B0(n1570), .B1(n522), .Y(n897) );
NAND2X1TS U1266 ( .A(n618), .B(n899), .Y(n1032) );
INVX2TS U1267 ( .A(n900), .Y(n920) );
AOI2BB1XLTS U1268 ( .A0N(n1651), .A1N(DP_OP_110J126_122_4535_n210), .B0(
DP_OP_110J126_122_4535_n208), .Y(n931) );
NOR2XLTS U1269 ( .A(n1491), .B(n1669), .Y(n904) );
NAND2X1TS U1270 ( .A(n454), .B(n562), .Y(n901) );
OAI21XLTS U1271 ( .A0(n562), .A1(n442), .B0(n901), .Y(n903) );
OA21XLTS U1272 ( .A0(n904), .A1(n903), .B0(n902), .Y(n1449) );
OAI22X1TS U1273 ( .A0(n617), .A1(n1257), .B0(n546), .B1(n1069), .Y(n905) );
AOI21X1TS U1274 ( .A0(n599), .A1(n1268), .B0(n905), .Y(n909) );
INVX2TS U1275 ( .A(n906), .Y(n925) );
INVX2TS U1276 ( .A(n1274), .Y(n1572) );
AOI21X1TS U1277 ( .A0(n617), .A1(n907), .B0(n1572), .Y(n924) );
NAND2X1TS U1278 ( .A(Op_MX[12]), .B(n559), .Y(n946) );
INVX2TS U1279 ( .A(n946), .Y(n908) );
OAI22X1TS U1280 ( .A0(n908), .A1(n1491), .B0(n1573), .B1(n1557), .Y(n923) );
CMPR32X2TS U1281 ( .A(DP_OP_110J126_122_4535_n528), .B(n1449), .C(n909),
.CO(n910), .S(n906) );
INVX2TS U1282 ( .A(n910), .Y(n927) );
XOR2X1TS U1283 ( .A(DP_OP_110J126_122_4535_n33), .B(n911), .Y(n914) );
OAI21XLTS U1284 ( .A0(n577), .A1(n580), .B0(n914), .Y(n913) );
OAI31X1TS U1285 ( .A0(n914), .A1(n577), .A2(n579), .B0(n913), .Y(n915) );
CMPR32X2TS U1286 ( .A(DP_OP_110J126_122_4535_n131), .B(
DP_OP_110J126_122_4535_n121), .C(n916), .CO(n949), .S(n1364) );
CMPR32X2TS U1287 ( .A(DP_OP_110J126_122_4535_n142), .B(
DP_OP_110J126_122_4535_n132), .C(n917), .CO(n916), .S(n1369) );
CMPR32X2TS U1288 ( .A(DP_OP_110J126_122_4535_n143), .B(
DP_OP_110J126_122_4535_n146), .C(n918), .CO(n917), .S(n1504) );
CMPR32X2TS U1289 ( .A(DP_OP_110J126_122_4535_n195), .B(n920), .C(n919), .CO(
n936), .S(n1460) );
NAND2X1TS U1290 ( .A(Op_MX[0]), .B(n560), .Y(n922) );
OAI21XLTS U1291 ( .A0(n1661), .A1(n1664), .B0(n922), .Y(n921) );
NOR2X2TS U1292 ( .A(DP_OP_110J126_122_4535_n226), .B(n1464), .Y(n1487) );
CMPR32X2TS U1293 ( .A(n925), .B(n924), .C(n923), .CO(n928), .S(n1489) );
INVX2TS U1294 ( .A(DP_OP_110J126_122_4535_n225), .Y(n926) );
AOI222X1TS U1295 ( .A0(n1487), .A1(n1489), .B0(n1487), .B1(n926), .C0(n1489),
.C1(n926), .Y(n1470) );
CMPR32X2TS U1296 ( .A(DP_OP_110J126_122_4535_n212), .B(n928), .C(n927), .CO(
n930), .S(n929) );
INVX2TS U1297 ( .A(n929), .Y(n1469) );
CMPR32X2TS U1298 ( .A(DP_OP_110J126_122_4535_n207), .B(n931), .C(n930), .CO(
n933), .S(n932) );
INVX2TS U1299 ( .A(n932), .Y(n1440) );
CMPR32X2TS U1300 ( .A(DP_OP_110J126_122_4535_n206), .B(
DP_OP_110J126_122_4535_n202), .C(n933), .CO(n919), .S(n934) );
INVX2TS U1301 ( .A(n934), .Y(n1373) );
NOR2XLTS U1302 ( .A(n1462), .B(DP_OP_110J126_122_4535_n221), .Y(n935) );
OAI2BB2XLTS U1303 ( .B0(n1460), .B1(n935), .A0N(n1462), .A1N(
DP_OP_110J126_122_4535_n221), .Y(n1467) );
CMPR32X2TS U1304 ( .A(DP_OP_110J126_122_4535_n192), .B(
DP_OP_110J126_122_4535_n189), .C(n936), .CO(n938), .S(n937) );
INVX2TS U1305 ( .A(n937), .Y(n1466) );
CMPR32X2TS U1306 ( .A(DP_OP_110J126_122_4535_n184), .B(
DP_OP_110J126_122_4535_n181), .C(n938), .CO(n940), .S(n939) );
INVX2TS U1307 ( .A(n939), .Y(n1437) );
CMPR32X2TS U1308 ( .A(DP_OP_110J126_122_4535_n176), .B(
DP_OP_110J126_122_4535_n173), .C(n940), .CO(n942), .S(n941) );
INVX2TS U1309 ( .A(n941), .Y(n1322) );
CMPR32X2TS U1310 ( .A(DP_OP_110J126_122_4535_n166), .B(
DP_OP_110J126_122_4535_n163), .C(n942), .CO(n944), .S(n943) );
INVX2TS U1311 ( .A(n943), .Y(n1453) );
CMPR32X2TS U1312 ( .A(DP_OP_110J126_122_4535_n157), .B(
DP_OP_110J126_122_4535_n154), .C(n944), .CO(n918), .S(n945) );
INVX2TS U1313 ( .A(n945), .Y(n1450) );
NAND2X1TS U1314 ( .A(n1502), .B(n1501), .Y(n1500) );
AOI2BB2X1TS U1315 ( .B0(n1504), .B1(n1500), .A0N(n1502), .A1N(n1501), .Y(
n947) );
NAND2X1TS U1316 ( .A(n947), .B(n946), .Y(n1366) );
NOR2X1TS U1317 ( .A(n947), .B(n946), .Y(n1367) );
NOR2XLTS U1318 ( .A(DP_OP_110J126_122_4535_n528), .B(n1362), .Y(n948) );
OAI2BB2XLTS U1319 ( .B0(n1364), .B1(n948), .A0N(DP_OP_110J126_122_4535_n528),
.A1N(n1362), .Y(n1378) );
CMPR32X2TS U1320 ( .A(DP_OP_110J126_122_4535_n120), .B(
DP_OP_110J126_122_4535_n110), .C(n949), .CO(n951), .S(n950) );
INVX2TS U1321 ( .A(n950), .Y(n1377) );
NOR2X1TS U1322 ( .A(n1651), .B(n1652), .Y(n1650) );
CMPR32X2TS U1323 ( .A(DP_OP_110J126_122_4535_n109), .B(
DP_OP_110J126_122_4535_n99), .C(n951), .CO(n952), .S(n1653) );
OAI2BB2XLTS U1324 ( .B0(n1650), .B1(n1653), .A0N(n1651), .A1N(n1652), .Y(
n1429) );
CMPR32X2TS U1325 ( .A(DP_OP_110J126_122_4535_n98), .B(
DP_OP_110J126_122_4535_n88), .C(n952), .CO(n954), .S(n953) );
INVX2TS U1326 ( .A(n953), .Y(n1428) );
CMPR32X2TS U1327 ( .A(DP_OP_110J126_122_4535_n87), .B(
DP_OP_110J126_122_4535_n79), .C(n954), .CO(n956), .S(n955) );
INVX2TS U1328 ( .A(n955), .Y(n1646) );
CMPR32X2TS U1329 ( .A(DP_OP_110J126_122_4535_n78), .B(
DP_OP_110J126_122_4535_n70), .C(n956), .CO(n958), .S(n957) );
INVX2TS U1330 ( .A(n957), .Y(n1390) );
CMPR32X2TS U1331 ( .A(DP_OP_110J126_122_4535_n69), .B(
DP_OP_110J126_122_4535_n62), .C(n958), .CO(n960), .S(n959) );
INVX2TS U1332 ( .A(n959), .Y(n1643) );
CMPR32X2TS U1333 ( .A(DP_OP_110J126_122_4535_n61), .B(
DP_OP_110J126_122_4535_n54), .C(n960), .CO(n962), .S(n961) );
INVX2TS U1334 ( .A(n961), .Y(n1393) );
CMPR32X2TS U1335 ( .A(DP_OP_110J126_122_4535_n53), .B(
DP_OP_110J126_122_4535_n48), .C(n962), .CO(n964), .S(n963) );
INVX2TS U1336 ( .A(n963), .Y(n1640) );
CMPR32X2TS U1337 ( .A(DP_OP_110J126_122_4535_n47), .B(
DP_OP_110J126_122_4535_n42), .C(n964), .CO(n966), .S(n965) );
INVX2TS U1338 ( .A(n965), .Y(n1397) );
CMPR32X2TS U1339 ( .A(DP_OP_110J126_122_4535_n37), .B(n1502), .C(n966), .CO(
n968), .S(n967) );
INVX2TS U1340 ( .A(n967), .Y(n1637) );
CMPR32X2TS U1341 ( .A(DP_OP_110J126_122_4535_n36), .B(
DP_OP_110J126_122_4535_n34), .C(n968), .CO(n911), .S(n969) );
INVX2TS U1342 ( .A(n969), .Y(n1401) );
OAI21XLTS U1343 ( .A0(n1635), .A1(DP_OP_110J126_122_4535_n516), .B0(n1633),
.Y(n970) );
OAI2BB1X1TS U1344 ( .A0N(DP_OP_110J126_122_4535_n516), .A1N(n1635), .B0(n970), .Y(n1387) );
NAND2X1TS U1345 ( .A(n1631), .B(Sgf_operation_EVEN1_Q_left[15]), .Y(n1630)
);
NAND2X1TS U1346 ( .A(n1628), .B(Sgf_operation_EVEN1_Q_left[17]), .Y(n1627)
);
NAND2X1TS U1347 ( .A(n1625), .B(Sgf_operation_EVEN1_Q_left[19]), .Y(n1624)
);
NAND2X1TS U1348 ( .A(n1622), .B(Sgf_operation_EVEN1_Q_left[21]), .Y(n1621)
);
NOR2X1TS U1349 ( .A(DP_OP_110J126_122_4535_n507), .B(n1621), .Y(n1482) );
XNOR2X1TS U1350 ( .A(n1482), .B(DP_OP_110J126_122_4535_n506), .Y(n971) );
AO22XLTS U1351 ( .A0(n1657), .A1(P_Sgf[47]), .B0(n1484), .B1(n971), .Y(n237)
);
AOI22X1TS U1352 ( .A0(Sgf_normalized_result[1]), .A1(n1326), .B0(n590), .B1(
Add_result[2]), .Y(n973) );
AOI22X1TS U1353 ( .A0(P_Sgf[24]), .A1(n630), .B0(n595), .B1(Add_result[1]),
.Y(n972) );
OAI211XLTS U1354 ( .A0(n1720), .A1(n409), .B0(n973), .C0(n972), .Y(n203) );
AOI22X1TS U1355 ( .A0(Sgf_normalized_result[0]), .A1(n974), .B0(n590), .B1(
Add_result[1]), .Y(n976) );
AOI22X1TS U1356 ( .A0(P_Sgf[23]), .A1(n629), .B0(n594), .B1(Add_result[0]),
.Y(n975) );
OAI211XLTS U1357 ( .A0(n1730), .A1(n1092), .B0(n976), .C0(n975), .Y(n202) );
OR2X1TS U1358 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX3TS U1359 ( .A(n463), .Y(n1773) );
BUFX3TS U1360 ( .A(n626), .Y(n1766) );
AOI22X1TS U1361 ( .A0(n527), .A1(n491), .B0(n633), .B1(n526), .Y(n977) );
OAI22X1TS U1362 ( .A0(n1279), .A1(n1257), .B0(n552), .B1(n1069), .Y(n979) );
AOI21X1TS U1363 ( .A0(n552), .A1(n599), .B0(n979), .Y(n1541) );
NOR2X1TS U1364 ( .A(n1540), .B(n1541), .Y(DP_OP_110J126_122_4535_n198) );
OAI22X1TS U1365 ( .A0(Op_MY[6]), .A1(n1026), .B0(n581), .B1(n441), .Y(n980)
);
AOI21X1TS U1366 ( .A0(n454), .A1(Op_MY[7]), .B0(n980), .Y(n1546) );
AO21X1TS U1367 ( .A0(Op_MX[6]), .A1(Op_MX[5]), .B0(n1353), .Y(n1038) );
AOI21X1TS U1368 ( .A0(n602), .A1(n1661), .B0(n399), .Y(n1547) );
NOR2X1TS U1369 ( .A(n1546), .B(n1547), .Y(DP_OP_110J126_122_4535_n658) );
AOI22X1TS U1370 ( .A0(n550), .A1(n535), .B0(n557), .B1(n549), .Y(n981) );
AOI22X1TS U1371 ( .A0(n554), .A1(n537), .B0(n532), .B1(n553), .Y(n983) );
NAND2X1TS U1372 ( .A(n984), .B(n985), .Y(n1215) );
OA21XLTS U1373 ( .A0(n985), .A1(n984), .B0(n1215), .Y(
DP_OP_110J126_122_4535_n151) );
OAI22X1TS U1374 ( .A0(n394), .A1(n1311), .B0(n645), .B1(n1046), .Y(n986) );
AOI21X1TS U1375 ( .A0(n1309), .A1(n394), .B0(n986), .Y(n1552) );
NAND2X1TS U1376 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n1513) );
AOI21X1TS U1377 ( .A0(n1055), .A1(n519), .B0(n476), .Y(n1553) );
NOR2X1TS U1378 ( .A(n1552), .B(n1553), .Y(DP_OP_110J126_122_4535_n1040) );
OAI22X1TS U1379 ( .A0(Op_MY[8]), .A1(n1026), .B0(n565), .B1(n441), .Y(n987)
);
AOI21X1TS U1380 ( .A0(n454), .A1(n566), .B0(n987), .Y(n1544) );
AOI21X1TS U1381 ( .A0(n1577), .A1(n621), .B0(n988), .Y(n1545) );
NOR2X1TS U1382 ( .A(n1544), .B(n1545), .Y(DP_OP_110J126_122_4535_n648) );
OAI22X1TS U1383 ( .A0(Op_MY[20]), .A1(n1046), .B0(Op_MY[21]), .B1(n1311),
.Y(n989) );
AOI21X1TS U1384 ( .A0(n1309), .A1(n573), .B0(n989), .Y(n1550) );
AOI21X1TS U1385 ( .A0(n484), .A1(n519), .B0(n401), .Y(n1551) );
NOR2X1TS U1386 ( .A(n1550), .B(n1551), .Y(DP_OP_110J126_122_4535_n1030) );
CMPR32X2TS U1387 ( .A(Op_MX[22]), .B(Op_MX[10]), .C(n990), .CO(n991), .S(
n1012) );
NAND2X1TS U1388 ( .A(n1011), .B(n1012), .Y(n992) );
NAND2X1TS U1389 ( .A(n992), .B(n1122), .Y(DP_OP_110J126_122_4535_n259) );
AOI22X1TS U1390 ( .A0(n552), .A1(n493), .B0(n640), .B1(n551), .Y(n993) );
AOI22X1TS U1391 ( .A0(n571), .A1(n491), .B0(n633), .B1(n461), .Y(n994) );
NOR2X1TS U1392 ( .A(n1018), .B(n1019), .Y(DP_OP_110J126_122_4535_n169) );
AOI21X1TS U1393 ( .A0(n996), .A1(n519), .B0(n995), .Y(n1548) );
INVX2TS U1394 ( .A(n1046), .Y(n1308) );
AOI21X1TS U1395 ( .A0(n1308), .A1(n1689), .B0(n1309), .Y(n1549) );
NOR2X1TS U1396 ( .A(n1548), .B(n1549), .Y(DP_OP_110J126_122_4535_n1017) );
AOI22X1TS U1397 ( .A0(n523), .A1(n537), .B0(n532), .B1(n522), .Y(n998) );
AOI22X1TS U1398 ( .A0(n550), .A1(n1567), .B0(n555), .B1(n511), .Y(n999) );
NAND2X1TS U1399 ( .A(n1000), .B(n1001), .Y(n1227) );
OA21XLTS U1400 ( .A0(n1001), .A1(n1000), .B0(n1227), .Y(
DP_OP_110J126_122_4535_n186) );
CMPR32X2TS U1401 ( .A(n1004), .B(n1003), .C(n1002), .CO(n891), .S(
DP_OP_110J126_122_4535_n234) );
NAND2X1TS U1402 ( .A(Op_MX[11]), .B(Op_MY[8]), .Y(
DP_OP_110J126_122_4535_n567) );
NAND2X1TS U1403 ( .A(n1011), .B(n1005), .Y(DP_OP_110J126_122_4535_n274) );
NAND2X1TS U1404 ( .A(n1007), .B(n1006), .Y(DP_OP_110J126_122_4535_n304) );
OAI22X1TS U1405 ( .A0(n586), .A1(n1026), .B0(Op_MY[11]), .B1(n441), .Y(n1008) );
AOI21X1TS U1406 ( .A0(n473), .A1(n454), .B0(n1008), .Y(n1542) );
AOI21X1TS U1407 ( .A0(n1009), .A1(n1661), .B0(n517), .Y(n1543) );
NOR2X1TS U1408 ( .A(n1542), .B(n1543), .Y(DP_OP_110J126_122_4535_n635) );
AOI22X1TS U1409 ( .A0(n614), .A1(n541), .B0(n613), .B1(n579), .Y(n1014) );
NAND2X1TS U1410 ( .A(n1338), .B(n1122), .Y(n1121) );
NAND2X1TS U1411 ( .A(Op_MX[11]), .B(Op_MY[4]), .Y(
DP_OP_110J126_122_4535_n593) );
BUFX3TS U1412 ( .A(n1750), .Y(n1736) );
CLKBUFX3TS U1413 ( .A(n167), .Y(n1755) );
BUFX3TS U1414 ( .A(n1750), .Y(n1739) );
BUFX3TS U1415 ( .A(n1750), .Y(n1738) );
BUFX3TS U1416 ( .A(n1750), .Y(n1743) );
AOI22X1TS U1417 ( .A0(n582), .A1(n1581), .B0(n507), .B1(n1679), .Y(n1015) );
AOI221X1TS U1418 ( .A0(n445), .A1(n565), .B0(n539), .B1(n467), .C0(n1015),
.Y(n1030) );
NAND2X1TS U1419 ( .A(Op_MX[11]), .B(n562), .Y(n1234) );
AOI22X1TS U1420 ( .A0(n587), .A1(n1579), .B0(n1580), .B1(n1678), .Y(n1016)
);
INVX2TS U1421 ( .A(n1017), .Y(DP_OP_110J126_122_4535_n619) );
AO21XLTS U1422 ( .A0(n1019), .A1(n1018), .B0(DP_OP_110J126_122_4535_n169),
.Y(n1223) );
AOI22X1TS U1423 ( .A0(n527), .A1(n495), .B0(n634), .B1(n526), .Y(n1020) );
AOI22X1TS U1424 ( .A0(n550), .A1(n493), .B0(n639), .B1(n549), .Y(n1021) );
AOI22X1TS U1425 ( .A0(n554), .A1(n491), .B0(n633), .B1(n553), .Y(n1022) );
INVX2TS U1426 ( .A(n1023), .Y(DP_OP_110J126_122_4535_n167) );
AOI22X1TS U1427 ( .A0(n563), .A1(n610), .B0(n1263), .B1(n465), .Y(n1024) );
NAND2BXLTS U1428 ( .AN(n1025), .B(Op_MY[0]), .Y(n1177) );
OAI22X1TS U1429 ( .A0(Op_MY[7]), .A1(n1026), .B0(n582), .B1(n442), .Y(n1027)
);
AOI21X1TS U1430 ( .A0(n454), .A1(Op_MY[8]), .B0(n1027), .Y(n1176) );
INVX2TS U1431 ( .A(n1028), .Y(DP_OP_110J126_122_4535_n654) );
CMPR32X2TS U1432 ( .A(n1030), .B(n1241), .C(n1029), .CO(n1031), .S(n1017) );
INVX2TS U1433 ( .A(n1031), .Y(DP_OP_110J126_122_4535_n618) );
INVX2TS U1434 ( .A(DP_OP_110J126_122_4535_n515), .Y(
Sgf_operation_EVEN1_Q_left[14]) );
CMPR32X2TS U1435 ( .A(n1034), .B(n1033), .C(n1032), .CO(n1113), .S(n1035) );
INVX2TS U1436 ( .A(n1035), .Y(DP_OP_110J126_122_4535_n204) );
NAND2X1TS U1437 ( .A(n641), .B(Op_MY[0]), .Y(n1197) );
AOI22X1TS U1438 ( .A0(n565), .A1(n610), .B0(n1263), .B1(n467), .Y(n1036) );
OAI21XLTS U1439 ( .A0(Op_MX[0]), .A1(n474), .B0(Op_MX[1]), .Y(n1195) );
INVX2TS U1440 ( .A(n1037), .Y(DP_OP_110J126_122_4535_n628) );
AOI22X1TS U1441 ( .A0(n582), .A1(n637), .B0(n487), .B1(n1679), .Y(n1039) );
NAND2X1TS U1442 ( .A(n641), .B(Op_MY[3]), .Y(n1232) );
INVX2TS U1443 ( .A(n1040), .Y(DP_OP_110J126_122_4535_n601) );
AOI22X1TS U1444 ( .A0(n643), .A1(n477), .B0(n459), .B1(n1684), .Y(n1041) );
AOI22X1TS U1445 ( .A0(n644), .A1(n479), .B0(n500), .B1(n1685), .Y(n1042) );
INVX2TS U1446 ( .A(n1043), .Y(DP_OP_110J126_122_4535_n1000) );
AOI22X1TS U1447 ( .A0(n645), .A1(n444), .B0(n502), .B1(n1690), .Y(n1044) );
AOI221X1TS U1448 ( .A0(n451), .A1(n574), .B0(n514), .B1(n1688), .C0(n1044),
.Y(n1185) );
NAND2BXLTS U1449 ( .AN(n1045), .B(n560), .Y(n1184) );
OAI22X1TS U1450 ( .A0(n394), .A1(n1046), .B0(n643), .B1(n1311), .Y(n1047) );
AOI21X1TS U1451 ( .A0(n1309), .A1(Op_MY[20]), .B0(n1047), .Y(n1183) );
INVX2TS U1452 ( .A(n1048), .Y(DP_OP_110J126_122_4535_n1036) );
INVX2TS U1453 ( .A(DP_OP_110J126_122_4535_n506), .Y(
Sgf_operation_EVEN1_Q_left[23]) );
INVX2TS U1454 ( .A(n1051), .Y(DP_OP_110J126_122_4535_n1001) );
NOR2XLTS U1455 ( .A(n1055), .B(n597), .Y(n1128) );
AOI22X1TS U1456 ( .A0(Op_MY[21]), .A1(n479), .B0(n500), .B1(n1687), .Y(n1052) );
INVX2TS U1457 ( .A(n1053), .Y(DP_OP_110J126_122_4535_n958) );
NOR2X1TS U1458 ( .A(n1054), .B(Op_MX[19]), .Y(n1132) );
AOI22X1TS U1459 ( .A0(Op_MY[15]), .A1(n1515), .B0(n1516), .B1(n1686), .Y(
n1056) );
AOI22X1TS U1460 ( .A0(n559), .A1(n479), .B0(n501), .B1(n519), .Y(n1057) );
AOI22X1TS U1461 ( .A0(n589), .A1(n444), .B0(n503), .B1(n1691), .Y(n1058) );
AOI221X1TS U1462 ( .A0(n451), .A1(n645), .B0(n514), .B1(n1690), .C0(n1058),
.Y(n1134) );
INVX2TS U1463 ( .A(n1059), .Y(DP_OP_110J126_122_4535_n1029) );
AOI22X1TS U1464 ( .A0(n567), .A1(n637), .B0(n487), .B1(n469), .Y(n1060) );
AOI22X1TS U1465 ( .A0(Op_MY[0]), .A1(n1579), .B0(n1580), .B1(n621), .Y(n1061) );
AOI22X1TS U1466 ( .A0(n583), .A1(n610), .B0(n1263), .B1(n1680), .Y(n1062) );
INVX2TS U1467 ( .A(n1063), .Y(DP_OP_110J126_122_4535_n647) );
INVX2TS U1468 ( .A(n1304), .Y(n1064) );
AOI221X1TS U1469 ( .A0(n1064), .A1(Op_MY[11]), .B0(n399), .B1(n1676), .C0(
n601), .Y(n1098) );
NAND2X1TS U1470 ( .A(n641), .B(Op_MY[6]), .Y(n1102) );
AOI22X1TS U1471 ( .A0(n565), .A1(n1579), .B0(n1580), .B1(n467), .Y(n1065) );
INVX2TS U1472 ( .A(n1066), .Y(DP_OP_110J126_122_4535_n576) );
AOI22X1TS U1473 ( .A0(n585), .A1(n1579), .B0(n1580), .B1(n471), .Y(n1067) );
AOI221X1TS U1474 ( .A0(n447), .A1(Op_MY[11]), .B0(n604), .B1(n1676), .C0(
n1067), .Y(n1101) );
NAND2X1TS U1475 ( .A(n641), .B(Op_MY[7]), .Y(n1100) );
INVX2TS U1476 ( .A(n1068), .Y(DP_OP_110J126_122_4535_n571) );
INVX2TS U1477 ( .A(n1069), .Y(n1255) );
AOI22X1TS U1478 ( .A0(n554), .A1(n598), .B0(n1255), .B1(n553), .Y(n1070) );
OAI21XLTS U1479 ( .A0(n1564), .A1(n631), .B0(n1070), .Y(
DP_OP_110J126_122_4535_n342) );
OAI21XLTS U1480 ( .A0(n618), .A1(n638), .B0(n400), .Y(
DP_OP_110J126_122_4535_n240) );
NOR2X1TS U1481 ( .A(FS_Module_state_reg[2]), .B(n1670), .Y(n1539) );
INVX2TS U1482 ( .A(n1498), .Y(n1406) );
INVX2TS U1483 ( .A(n1081), .Y(n1486) );
NAND2X1TS U1484 ( .A(n1537), .B(n1071), .Y(n1334) );
NOR2BX1TS U1485 ( .AN(P_Sgf[47]), .B(n1334), .Y(n1082) );
INVX2TS U1486 ( .A(n1082), .Y(n1072) );
OAI31X1TS U1487 ( .A0(n1406), .A1(n1486), .A2(n1692), .B0(n1072), .Y(n235)
);
OAI21XLTS U1488 ( .A0(n617), .A1(n1121), .B0(n636), .Y(
DP_OP_110J126_122_4535_n239) );
OAI21X1TS U1489 ( .A0(n1074), .A1(n1073), .B0(n1317), .Y(
DP_OP_110J126_122_4535_n236) );
AOI22X1TS U1490 ( .A0(n578), .A1(n1292), .B0(n1295), .B1(n579), .Y(n1162) );
AOI22X1TS U1491 ( .A0(n577), .A1(n1301), .B0(n489), .B1(n512), .Y(n1075) );
CLKAND2X2TS U1492 ( .A(n1077), .B(n1076), .Y(n1160) );
INVX2TS U1493 ( .A(n1078), .Y(DP_OP_110J126_122_4535_n58) );
NAND2X1TS U1494 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1536) );
NOR3X1TS U1495 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1536), .Y(ready) );
AOI22X1TS U1496 ( .A0(DP_OP_36J126_123_9196_n33), .A1(n1695), .B0(n1667),
.B1(n1733), .Y(n1080) );
INVX2TS U1497 ( .A(ready), .Y(n1079) );
OAI22X1TS U1498 ( .A0(n1080), .A1(n1333), .B0(P_Sgf[47]), .B1(n1334), .Y(
n379) );
CLKBUFX3TS U1499 ( .A(n1081), .Y(n1408) );
OAI211XLTS U1500 ( .A0(n1082), .A1(n1732), .B0(n1408), .C0(n1498), .Y(n236)
);
AOI22X1TS U1501 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n404), .Y(n1327) );
AOI22X1TS U1502 ( .A0(Sgf_normalized_result[22]), .A1(n1326), .B0(
Add_result[22]), .B1(n595), .Y(n1084) );
NAND2X1TS U1503 ( .A(P_Sgf[45]), .B(n630), .Y(n1083) );
OAI211XLTS U1504 ( .A0(n1328), .A1(n1327), .B0(n1084), .C0(n1083), .Y(n224)
);
INVX2TS U1505 ( .A(n1660), .Y(n1329) );
CLKBUFX3TS U1506 ( .A(n1329), .Y(n1331) );
CLKXOR2X2TS U1507 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1532) );
NOR2XLTS U1508 ( .A(n1532), .B(underflow_flag), .Y(n1086) );
OAI32X1TS U1509 ( .A0(n1331), .A1(n1086), .A2(overflow_flag), .B0(n1660),
.B1(n1731), .Y(n168) );
OAI21XLTS U1510 ( .A0(n1667), .A1(n1333), .B0(FS_Module_state_reg[3]), .Y(
n1087) );
AOI22X1TS U1511 ( .A0(Sgf_normalized_result[21]), .A1(n1088), .B0(
Add_result[22]), .B1(n592), .Y(n1091) );
AOI22X1TS U1512 ( .A0(Add_result[21]), .A1(n594), .B0(P_Sgf[44]), .B1(n629),
.Y(n1090) );
OAI211XLTS U1513 ( .A0(n1708), .A1(n1092), .B0(n1091), .C0(n1090), .Y(n223)
);
AOI22X1TS U1514 ( .A0(n583), .A1(n457), .B0(n601), .B1(n1680), .Y(n1093) );
AOI22X1TS U1515 ( .A0(n616), .A1(n1567), .B0(n555), .B1(n1557), .Y(n1094) );
AOI22X1TS U1516 ( .A0(n581), .A1(n445), .B0(n539), .B1(n1681), .Y(n1095) );
CMPR32X2TS U1517 ( .A(n1098), .B(n1097), .C(n1096), .CO(n1066), .S(n1099) );
INVX2TS U1518 ( .A(n1099), .Y(DP_OP_110J126_122_4535_n577) );
CMPR32X2TS U1519 ( .A(n1102), .B(n1101), .C(n1100), .CO(n1068), .S(n1103) );
INVX2TS U1520 ( .A(n1103), .Y(DP_OP_110J126_122_4535_n572) );
AOI22X1TS U1521 ( .A0(Op_MY[11]), .A1(n457), .B0(n601), .B1(n1676), .Y(n1104) );
AOI22X1TS U1522 ( .A0(n582), .A1(n455), .B0(n485), .B1(n1679), .Y(n1105) );
AOI22X1TS U1523 ( .A0(n566), .A1(n439), .B0(n517), .B1(n467), .Y(n1106) );
AOI22X1TS U1524 ( .A0(n473), .A1(n446), .B0(n540), .B1(n474), .Y(n1107) );
AOI22X1TS U1525 ( .A0(n585), .A1(n446), .B0(n540), .B1(n471), .Y(n1108) );
AOI22X1TS U1526 ( .A0(n473), .A1(n455), .B0(n485), .B1(n474), .Y(n1109) );
AOI22X1TS U1527 ( .A0(n585), .A1(n439), .B0(n517), .B1(n471), .Y(n1110) );
AOI22X1TS U1528 ( .A0(n584), .A1(n446), .B0(n540), .B1(n1682), .Y(n1111) );
AOI22X1TS U1529 ( .A0(n585), .A1(n457), .B0(n601), .B1(n471), .Y(n1112) );
CMPR32X2TS U1530 ( .A(n1114), .B(n1459), .C(n1113), .CO(n1115), .S(n900) );
INVX2TS U1531 ( .A(n1115), .Y(DP_OP_110J126_122_4535_n196) );
CMPR32X2TS U1532 ( .A(n1118), .B(n1117), .C(n1116), .CO(n1119), .S(n1063) );
INVX2TS U1533 ( .A(n1119), .Y(DP_OP_110J126_122_4535_n646) );
AOI22X1TS U1534 ( .A0(n616), .A1(n537), .B0(n533), .B1(n1557), .Y(n1120) );
INVX2TS U1535 ( .A(n1121), .Y(n1558) );
AOI22X1TS U1536 ( .A0(n612), .A1(n1558), .B0(n506), .B1(n436), .Y(n1123) );
AOI22X1TS U1537 ( .A0(n587), .A1(n455), .B0(n485), .B1(n1678), .Y(n1124) );
AOI22X1TS U1538 ( .A0(n616), .A1(n535), .B0(n557), .B1(n1557), .Y(n1125) );
AOI22X1TS U1539 ( .A0(n548), .A1(n598), .B0(n1255), .B1(n547), .Y(n1126) );
OAI21X1TS U1540 ( .A0(n571), .A1(n1257), .B0(n1126), .Y(
DP_OP_110J126_122_4535_n340) );
INVX2TS U1541 ( .A(n1129), .Y(DP_OP_110J126_122_4535_n959) );
AOI22X1TS U1542 ( .A0(n546), .A1(n506), .B0(n1558), .B1(n545), .Y(n1130) );
AOI22X1TS U1543 ( .A0(n616), .A1(n1300), .B0(n530), .B1(n1557), .Y(n1131) );
INVX2TS U1544 ( .A(n1133), .Y(DP_OP_110J126_122_4535_n1095) );
CMPR32X2TS U1545 ( .A(n1136), .B(n1135), .C(n1134), .CO(n1137), .S(n1059) );
INVX2TS U1546 ( .A(n1137), .Y(DP_OP_110J126_122_4535_n1028) );
AOI22X1TS U1547 ( .A0(n525), .A1(n598), .B0(n1255), .B1(n524), .Y(n1138) );
OAI21X1TS U1548 ( .A0(n529), .A1(n1257), .B0(n1138), .Y(
DP_OP_110J126_122_4535_n338) );
AOI22X1TS U1549 ( .A0(n612), .A1(n532), .B0(n538), .B1(n1571), .Y(n1139) );
OAI221X1TS U1550 ( .A0(n576), .A1(n493), .B0(n575), .B1(n639), .C0(n1139),
.Y(DP_OP_110J126_122_4535_n306) );
AOI22X1TS U1551 ( .A0(n573), .A1(n596), .B0(n475), .B1(n1687), .Y(n1140) );
AOI22X1TS U1552 ( .A0(n548), .A1(n495), .B0(n635), .B1(n513), .Y(n1141) );
AOI22X1TS U1553 ( .A0(n554), .A1(n489), .B0(n638), .B1(n553), .Y(n1142) );
INVX2TS U1554 ( .A(n1143), .Y(DP_OP_110J126_122_4535_n118) );
AOI22X1TS U1555 ( .A0(Op_MY[15]), .A1(n452), .B0(n515), .B1(n1686), .Y(n1144) );
AOI22X1TS U1556 ( .A0(n574), .A1(n596), .B0(n475), .B1(n1688), .Y(n1145) );
AOI22X1TS U1557 ( .A0(n578), .A1(n1560), .B0(n1292), .B1(n579), .Y(n1201) );
AOI22X1TS U1558 ( .A0(n612), .A1(n1301), .B0(n490), .B1(n1571), .Y(n1146) );
INVX2TS U1559 ( .A(n1147), .Y(DP_OP_110J126_122_4535_n67) );
AOI22X1TS U1560 ( .A0(n554), .A1(n495), .B0(n634), .B1(n510), .Y(n1148) );
AOI22X1TS U1561 ( .A0(n548), .A1(n493), .B0(n640), .B1(n547), .Y(n1149) );
AOI221X1TS U1562 ( .A0(n537), .A1(n571), .B0(n532), .B1(n461), .C0(n1149),
.Y(n1214) );
AOI22X1TS U1563 ( .A0(n529), .A1(n493), .B0(n639), .B1(n528), .Y(n1150) );
AOI22X1TS U1564 ( .A0(n571), .A1(n495), .B0(n635), .B1(n461), .Y(n1151) );
INVX2TS U1565 ( .A(n1152), .Y(DP_OP_110J126_122_4535_n129) );
AOI22X1TS U1566 ( .A0(n588), .A1(n392), .B0(n481), .B1(n1689), .Y(n1153) );
AOI22X1TS U1567 ( .A0(n1568), .A1(n495), .B0(n634), .B1(n524), .Y(n1154) );
AOI22X1TS U1568 ( .A0(n548), .A1(n489), .B0(n638), .B1(n513), .Y(n1155) );
CLKAND2X2TS U1569 ( .A(n1157), .B(n1156), .Y(n1281) );
INVX2TS U1570 ( .A(n1158), .Y(DP_OP_110J126_122_4535_n95) );
AOI22X1TS U1571 ( .A0(n527), .A1(n505), .B0(n1558), .B1(n542), .Y(n1159) );
CMPR32X2TS U1572 ( .A(n1162), .B(n1161), .C(n1160), .CO(n1078), .S(n1163) );
INVX2TS U1573 ( .A(n1163), .Y(DP_OP_110J126_122_4535_n59) );
INVX2TS U1574 ( .A(n451), .Y(n1521) );
OAI221X1TS U1575 ( .A0(n588), .A1(n395), .B0(n1689), .B1(n1521), .C0(n444),
.Y(DP_OP_110J126_122_4535_n1123) );
AOI22X1TS U1576 ( .A0(n612), .A1(n557), .B0(n535), .B1(n1571), .Y(n1164) );
OAI221X1TS U1577 ( .A0(n576), .A1(n496), .B0(n575), .B1(n635), .C0(n1164),
.Y(DP_OP_110J126_122_4535_n291) );
AOI22X1TS U1578 ( .A0(n589), .A1(n392), .B0(n481), .B1(n1691), .Y(n1165) );
AOI22X1TS U1579 ( .A0(n577), .A1(n1558), .B0(n506), .B1(n512), .Y(n1166) );
AOI22X1TS U1580 ( .A0(n589), .A1(n452), .B0(n514), .B1(n1691), .Y(n1167) );
INVX2TS U1581 ( .A(n1570), .Y(n1332) );
AOI22X1TS U1582 ( .A0(n571), .A1(n489), .B0(n638), .B1(n570), .Y(n1168) );
AOI22X1TS U1583 ( .A0(n529), .A1(n495), .B0(n635), .B1(n544), .Y(n1169) );
INVX2TS U1584 ( .A(n1170), .Y(DP_OP_110J126_122_4535_n107) );
AOI22X1TS U1585 ( .A0(Op_MY[15]), .A1(n392), .B0(n481), .B1(n1686), .Y(n1171) );
AOI22X1TS U1586 ( .A0(n561), .A1(n457), .B0(n601), .B1(n521), .Y(n1172) );
AOI22X1TS U1587 ( .A0(n453), .A1(Op_MY[6]), .B0(n1174), .B1(n465), .Y(n1173)
);
OAI21X1TS U1588 ( .A0(Op_MY[6]), .A1(n442), .B0(n1173), .Y(
DP_OP_110J126_122_4535_n761) );
AOI22X1TS U1589 ( .A0(n585), .A1(n453), .B0(n1174), .B1(n467), .Y(n1175) );
OAI21X1TS U1590 ( .A0(n586), .A1(n442), .B0(n1175), .Y(
DP_OP_110J126_122_4535_n757) );
CMPR32X2TS U1591 ( .A(n1178), .B(n1177), .C(n1176), .CO(n1179), .S(n1028) );
INVX2TS U1592 ( .A(n1179), .Y(DP_OP_110J126_122_4535_n653) );
AOI22X1TS U1593 ( .A0(n643), .A1(n391), .B0(n483), .B1(n1684), .Y(n1180) );
AOI22X1TS U1594 ( .A0(Op_MX[9]), .A1(n1699), .B0(n1666), .B1(n1661), .Y(
n1181) );
OAI221XLTS U1595 ( .A0(n621), .A1(Op_MX[9]), .B0(n1666), .B1(n1699), .C0(
n1181), .Y(n1182) );
CMPR32X2TS U1596 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1186), .S(n1048) );
INVX2TS U1597 ( .A(n1186), .Y(DP_OP_110J126_122_4535_n1035) );
AOI22X1TS U1598 ( .A0(n561), .A1(n440), .B0(n517), .B1(n521), .Y(n1187) );
AOI22X1TS U1599 ( .A0(n643), .A1(n1515), .B0(n1516), .B1(n1684), .Y(n1188)
);
INVX2TS U1600 ( .A(n1189), .Y(DP_OP_110J126_122_4535_n991) );
AOI22X1TS U1601 ( .A0(n646), .A1(n596), .B0(n475), .B1(n1683), .Y(n1190) );
CMPR32X2TS U1602 ( .A(n1677), .B(Op_MY[13]), .C(n1191), .CO(n1192), .S(n1189) );
INVX2TS U1603 ( .A(n1192), .Y(DP_OP_110J126_122_4535_n990) );
AOI22X1TS U1604 ( .A0(n567), .A1(n440), .B0(n516), .B1(n469), .Y(n1193) );
AOI22X1TS U1605 ( .A0(n559), .A1(n596), .B0(n475), .B1(n519), .Y(n1194) );
OAI221X1TS U1606 ( .A0(Op_MY[13]), .A1(n1516), .B0(n1683), .B1(n1515), .C0(
n1194), .Y(DP_OP_110J126_122_4535_n1105) );
CMPR32X2TS U1607 ( .A(n1197), .B(n1196), .C(n1195), .CO(n1198), .S(n1037) );
INVX2TS U1608 ( .A(n1198), .Y(DP_OP_110J126_122_4535_n627) );
CMPR32X2TS U1609 ( .A(n1201), .B(n1200), .C(n1199), .CO(n1202), .S(n1147) );
INVX2TS U1610 ( .A(n1202), .Y(DP_OP_110J126_122_4535_n66) );
AOI22X1TS U1611 ( .A0(n529), .A1(n1300), .B0(n530), .B1(n544), .Y(n1203) );
OAI221X1TS U1612 ( .A0(n576), .A1(n397), .B0(n575), .B1(n419), .C0(n639),
.Y(DP_OP_110J126_122_4535_n305) );
CMPR32X2TS U1613 ( .A(n1206), .B(n1205), .C(n1204), .CO(n1207), .S(n1170) );
INVX2TS U1614 ( .A(n1207), .Y(DP_OP_110J126_122_4535_n106) );
AOI22X1TS U1615 ( .A0(n550), .A1(n505), .B0(n1558), .B1(n511), .Y(n1208) );
CMPR32X2TS U1616 ( .A(n1211), .B(n1210), .C(n1209), .CO(n1212), .S(n1152) );
INVX2TS U1617 ( .A(n1212), .Y(DP_OP_110J126_122_4535_n128) );
AOI22X1TS U1618 ( .A0(n523), .A1(n505), .B0(n1558), .B1(n543), .Y(n1213) );
NOR2X1TS U1619 ( .A(n614), .B(n1557), .Y(DP_OP_110J126_122_4535_n258) );
CMPR32X2TS U1620 ( .A(n1216), .B(n1215), .C(n1214), .CO(n1211), .S(n1217) );
INVX2TS U1621 ( .A(n1217), .Y(DP_OP_110J126_122_4535_n140) );
AOI22X1TS U1622 ( .A0(n612), .A1(n1255), .B0(n599), .B1(n608), .Y(n1218) );
OAI21X1TS U1623 ( .A0(n1568), .A1(n1257), .B0(n1218), .Y(
DP_OP_110J126_122_4535_n337) );
AOI22X1TS U1624 ( .A0(n1295), .A1(n1567), .B0(n555), .B1(n513), .Y(n1219) );
AOI22X1TS U1625 ( .A0(n527), .A1(n535), .B0(n557), .B1(n542), .Y(n1220) );
CMPR32X2TS U1626 ( .A(n1223), .B(n1222), .C(n1221), .CO(n1023), .S(n1224) );
INVX2TS U1627 ( .A(n1224), .Y(DP_OP_110J126_122_4535_n168) );
AOI22X1TS U1628 ( .A0(n1297), .A1(n598), .B0(n1255), .B1(n544), .Y(n1225) );
OAI21X1TS U1629 ( .A0(n548), .A1(n631), .B0(n1225), .Y(
DP_OP_110J126_122_4535_n339) );
CMPR32X2TS U1630 ( .A(n1228), .B(n1227), .C(n1226), .CO(n1221), .S(n1229) );
INVX2TS U1631 ( .A(n1229), .Y(DP_OP_110J126_122_4535_n178) );
AOI22X1TS U1632 ( .A0(n1292), .A1(n598), .B0(n1255), .B1(n570), .Y(n1230) );
OAI21X1TS U1633 ( .A0(n1560), .A1(n631), .B0(n1230), .Y(
DP_OP_110J126_122_4535_n341) );
AOI22X1TS U1634 ( .A0(n546), .A1(n538), .B0(n533), .B1(n609), .Y(n1231) );
OAI21X1TS U1635 ( .A0(n618), .A1(n640), .B0(n419), .Y(
DP_OP_110J126_122_4535_n242) );
CMPR32X2TS U1636 ( .A(n1234), .B(n1233), .C(n1232), .CO(n1235), .S(n1040) );
INVX2TS U1637 ( .A(n1235), .Y(DP_OP_110J126_122_4535_n600) );
AOI22X1TS U1638 ( .A0(n581), .A1(n637), .B0(n487), .B1(n1681), .Y(n1236) );
NAND2X1TS U1639 ( .A(n641), .B(n568), .Y(n1239) );
INVX2TS U1640 ( .A(n1237), .Y(DP_OP_110J126_122_4535_n609) );
AOI22X1TS U1641 ( .A0(n582), .A1(n447), .B0(n604), .B1(n1679), .Y(n1238) );
CMPR32X2TS U1642 ( .A(n1241), .B(n1240), .C(n1239), .CO(n1242), .S(n1237) );
INVX2TS U1643 ( .A(n1242), .Y(DP_OP_110J126_122_4535_n608) );
AOI22X1TS U1644 ( .A0(n587), .A1(n440), .B0(n516), .B1(n1678), .Y(n1243) );
AOI22X1TS U1645 ( .A0(n567), .A1(n457), .B0(n601), .B1(n470), .Y(n1244) );
AOI22X1TS U1646 ( .A0(n523), .A1(n598), .B0(n1255), .B1(n543), .Y(n1245) );
OAI21X1TS U1647 ( .A0(n546), .A1(n631), .B0(n1245), .Y(
DP_OP_110J126_122_4535_n346) );
NOR2X1TS U1648 ( .A(n1666), .B(n466), .Y(DP_OP_110J126_122_4535_n680) );
NOR2X1TS U1649 ( .A(n1666), .B(n468), .Y(DP_OP_110J126_122_4535_n678) );
AOI22X1TS U1650 ( .A0(n1260), .A1(n599), .B0(n1255), .B1(n542), .Y(n1246) );
OAI21X1TS U1651 ( .A0(n1270), .A1(n631), .B0(n1246), .Y(
DP_OP_110J126_122_4535_n345) );
AOI22X1TS U1652 ( .A0(n563), .A1(n455), .B0(n485), .B1(n465), .Y(n1247) );
OAI21X1TS U1653 ( .A0(n1694), .A1(n1672), .B0(Op_MX[17]), .Y(
DP_OP_110J126_122_4535_n1107) );
AOI22X1TS U1654 ( .A0(n563), .A1(n446), .B0(n540), .B1(n465), .Y(n1248) );
AOI22X1TS U1655 ( .A0(n546), .A1(n535), .B0(n557), .B1(n545), .Y(n1249) );
AOI22X1TS U1656 ( .A0(n552), .A1(n538), .B0(n533), .B1(n551), .Y(n1251) );
AOI22X1TS U1657 ( .A0(Op_MY[8]), .A1(n440), .B0(n516), .B1(n1679), .Y(n1252)
);
AOI22X1TS U1658 ( .A0(n1260), .A1(n1300), .B0(n530), .B1(n542), .Y(n1253) );
AOI22X1TS U1659 ( .A0(n581), .A1(n440), .B0(n516), .B1(n1681), .Y(n1254) );
AOI22X1TS U1660 ( .A0(n577), .A1(n1255), .B0(n599), .B1(n512), .Y(n1256) );
OAI21X1TS U1661 ( .A0(n1257), .A1(n1571), .B0(n1256), .Y(
DP_OP_110J126_122_4535_n336) );
AOI22X1TS U1662 ( .A0(n394), .A1(n391), .B0(n483), .B1(n1691), .Y(n1258) );
AOI22X1TS U1663 ( .A0(n1279), .A1(n625), .B0(n530), .B1(n511), .Y(n1259) );
AOI22X1TS U1664 ( .A0(n1260), .A1(n1567), .B0(n555), .B1(n542), .Y(n1261) );
AOI22X1TS U1665 ( .A0(n566), .A1(n456), .B0(n486), .B1(n468), .Y(n1262) );
AOI22X1TS U1666 ( .A0(n645), .A1(n391), .B0(n483), .B1(n1690), .Y(n1264) );
AOI22X1TS U1667 ( .A0(n1297), .A1(n538), .B0(n533), .B1(n544), .Y(n1265) );
AOI22X1TS U1668 ( .A0(n645), .A1(n596), .B0(n475), .B1(n1690), .Y(n1267) );
AOI22X1TS U1669 ( .A0(n546), .A1(n625), .B0(n531), .B1(n545), .Y(n1269) );
AOI22X1TS U1670 ( .A0(Op_MY[4]), .A1(n446), .B0(n540), .B1(n1678), .Y(n1271)
);
CMPR32X2TS U1671 ( .A(n1274), .B(n1273), .C(n1272), .CO(n1275), .S(n1143) );
INVX2TS U1672 ( .A(n1275), .Y(DP_OP_110J126_122_4535_n117) );
AOI22X1TS U1673 ( .A0(n643), .A1(n392), .B0(n481), .B1(n1684), .Y(n1276) );
AOI22X1TS U1674 ( .A0(n644), .A1(n596), .B0(n475), .B1(n1685), .Y(n1277) );
AOI22X1TS U1675 ( .A0(n552), .A1(n505), .B0(n1558), .B1(n551), .Y(n1278) );
AOI22X1TS U1676 ( .A0(n564), .A1(n458), .B0(n602), .B1(n465), .Y(n1280) );
CMPR32X2TS U1677 ( .A(n1283), .B(n1282), .C(n1281), .CO(n1158), .S(n1284) );
INVX2TS U1678 ( .A(n1284), .Y(DP_OP_110J126_122_4535_n96) );
AOI22X1TS U1679 ( .A0(Op_MY[20]), .A1(n452), .B0(n515), .B1(n1684), .Y(n1285) );
OAI221X1TS U1680 ( .A0(Op_MY[21]), .A1(n502), .B0(n1687), .B1(n443), .C0(
n1285), .Y(DP_OP_110J126_122_4535_n1125) );
AOI22X1TS U1681 ( .A0(Op_MY[8]), .A1(n446), .B0(n540), .B1(n1679), .Y(n1286)
);
INVX2TS U1682 ( .A(DP_OP_110J126_122_4535_n567), .Y(
DP_OP_110J126_122_4535_n566) );
AOI22X1TS U1683 ( .A0(Op_MY[15]), .A1(n597), .B0(n476), .B1(n1686), .Y(n1287) );
AOI22X1TS U1684 ( .A0(n1295), .A1(n625), .B0(n531), .B1(n513), .Y(n1288) );
AOI22X1TS U1685 ( .A0(n1292), .A1(n505), .B0(n628), .B1(n570), .Y(n1289) );
AOI22X1TS U1686 ( .A0(n581), .A1(n448), .B0(n1577), .B1(n1681), .Y(n1290) );
AOI22X1TS U1687 ( .A0(n1295), .A1(n506), .B0(n628), .B1(n513), .Y(n1291) );
OAI221X1TS U1688 ( .A0(n571), .A1(n1563), .B0(n461), .B1(n534), .C0(n1291),
.Y(DP_OP_110J126_122_4535_n265) );
AOI22X1TS U1689 ( .A0(n574), .A1(n392), .B0(n482), .B1(n1688), .Y(n1293) );
AOI22X1TS U1690 ( .A0(n1297), .A1(n506), .B0(n628), .B1(n544), .Y(n1294) );
OAI221X1TS U1691 ( .A0(n548), .A1(n1563), .B0(n547), .B1(n534), .C0(n1294),
.Y(DP_OP_110J126_122_4535_n264) );
AOI22X1TS U1692 ( .A0(n525), .A1(n506), .B0(n628), .B1(n524), .Y(n1296) );
OAI221X1TS U1693 ( .A0(n529), .A1(n1563), .B0(n528), .B1(n534), .C0(n1296),
.Y(DP_OP_110J126_122_4535_n263) );
AOI22X1TS U1694 ( .A0(Op_MY[4]), .A1(n458), .B0(n602), .B1(n1678), .Y(n1298)
);
AOI22X1TS U1695 ( .A0(Op_MY[16]), .A1(n392), .B0(n482), .B1(n1685), .Y(n1299) );
INVX2TS U1696 ( .A(n1300), .Y(n1302) );
OAI221X1TS U1697 ( .A0(n576), .A1(n1302), .B0(n575), .B1(n400), .C0(n638),
.Y(DP_OP_110J126_122_4535_n275) );
AOI22X1TS U1698 ( .A0(n581), .A1(n458), .B0(n602), .B1(n1681), .Y(n1303) );
AOI22X1TS U1699 ( .A0(Op_MY[16]), .A1(n452), .B0(n515), .B1(n1685), .Y(n1305) );
OAI221X1TS U1700 ( .A0(Op_MY[17]), .A1(n502), .B0(n1688), .B1(n443), .C0(
n1305), .Y(DP_OP_110J126_122_4535_n1129) );
INVX2TS U1701 ( .A(DP_OP_110J126_122_4535_n593), .Y(
DP_OP_110J126_122_4535_n592) );
AOI22X1TS U1702 ( .A0(n583), .A1(n448), .B0(n1577), .B1(n1680), .Y(n1306) );
AOI22X1TS U1703 ( .A0(Op_MY[22]), .A1(n1309), .B0(n1308), .B1(n1687), .Y(
n1307) );
OAI21X1TS U1704 ( .A0(Op_MY[22]), .A1(n1311), .B0(n1307), .Y(
DP_OP_110J126_122_4535_n1138) );
AOI22X1TS U1705 ( .A0(n1309), .A1(Op_MY[18]), .B0(n1308), .B1(n1688), .Y(
n1310) );
OAI21X1TS U1706 ( .A0(Op_MY[18]), .A1(n1311), .B0(n1310), .Y(
DP_OP_110J126_122_4535_n1142) );
CLKAND2X2TS U1707 ( .A(n1312), .B(n618), .Y(DP_OP_110J126_122_4535_n333) );
NAND2BXLTS U1708 ( .AN(n482), .B(n478), .Y(DP_OP_110J126_122_4535_n1108) );
INVX2TS U1709 ( .A(n1658), .Y(n1313) );
AO22XLTS U1710 ( .A0(Sgf_normalized_result[20]), .A1(n1313), .B0(
final_result_ieee[20]), .B1(n1331), .Y(n180) );
AO22XLTS U1711 ( .A0(Sgf_normalized_result[21]), .A1(n1313), .B0(
final_result_ieee[21]), .B1(n1331), .Y(n179) );
AO22XLTS U1712 ( .A0(Sgf_normalized_result[22]), .A1(n1313), .B0(
final_result_ieee[22]), .B1(n1331), .Y(n178) );
INVX2TS U1713 ( .A(n1658), .Y(n1316) );
AO22XLTS U1714 ( .A0(Sgf_normalized_result[18]), .A1(n1316), .B0(
final_result_ieee[18]), .B1(n1331), .Y(n182) );
AO22XLTS U1715 ( .A0(Sgf_normalized_result[19]), .A1(n1316), .B0(
final_result_ieee[19]), .B1(n1331), .Y(n181) );
AO22XLTS U1716 ( .A0(Sgf_normalized_result[15]), .A1(n1316), .B0(
final_result_ieee[15]), .B1(n1331), .Y(n185) );
AO22XLTS U1717 ( .A0(Sgf_normalized_result[16]), .A1(n1316), .B0(
final_result_ieee[16]), .B1(n1331), .Y(n184) );
NAND2X1TS U1718 ( .A(Op_MX[15]), .B(n1314), .Y(DP_OP_110J126_122_4535_n1121)
);
CLKBUFX3TS U1719 ( .A(n1329), .Y(n1480) );
AO22XLTS U1720 ( .A0(Sgf_normalized_result[17]), .A1(n1316), .B0(
final_result_ieee[17]), .B1(n1480), .Y(n183) );
AO22XLTS U1721 ( .A0(Sgf_normalized_result[13]), .A1(n1316), .B0(
final_result_ieee[13]), .B1(n1480), .Y(n187) );
AO22XLTS U1722 ( .A0(Sgf_normalized_result[12]), .A1(n1316), .B0(
final_result_ieee[12]), .B1(n1480), .Y(n188) );
NAND2X1TS U1723 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1315) );
NAND2X1TS U1724 ( .A(Op_MX[21]), .B(n1315), .Y(DP_OP_110J126_122_4535_n1079)
);
AO22XLTS U1725 ( .A0(Sgf_normalized_result[14]), .A1(n1316), .B0(
final_result_ieee[14]), .B1(n1480), .Y(n186) );
AO22XLTS U1726 ( .A0(Sgf_normalized_result[11]), .A1(n1316), .B0(
final_result_ieee[11]), .B1(n1480), .Y(n189) );
AO22XLTS U1727 ( .A0(Sgf_normalized_result[10]), .A1(n1316), .B0(
final_result_ieee[10]), .B1(n1480), .Y(n190) );
CMPR32X2TS U1728 ( .A(n1319), .B(n1318), .C(n1317), .CO(n1004), .S(
DP_OP_110J126_122_4535_n235) );
INVX2TS U1729 ( .A(n1657), .Y(n1477) );
INVX2TS U1730 ( .A(n1493), .Y(n1476) );
AOI2BB2XLTS U1731 ( .B0(DP_OP_110J126_122_4535_n235), .B1(n1477), .A0N(n1476), .A1N(P_Sgf[3]), .Y(n241) );
INVX2TS U1732 ( .A(n1658), .Y(n1481) );
AO22XLTS U1733 ( .A0(Sgf_normalized_result[9]), .A1(n1481), .B0(
final_result_ieee[9]), .B1(n1480), .Y(n191) );
XNOR2X1TS U1734 ( .A(DP_OP_36J126_123_9196_n1), .B(n1335), .Y(n1320) );
INVX2TS U1735 ( .A(n1657), .Y(n1471) );
AO22XLTS U1736 ( .A0(n1320), .A1(n1471), .B0(n1657), .B1(
Exp_module_Overflow_flag_A), .Y(n225) );
AO22XLTS U1737 ( .A0(Sgf_normalized_result[8]), .A1(n1481), .B0(
final_result_ieee[8]), .B1(n1480), .Y(n192) );
INVX2TS U1738 ( .A(n1426), .Y(n1427) );
AO22XLTS U1739 ( .A0(n1427), .A1(Data_MY[31]), .B0(n1479), .B1(Op_MY[31]),
.Y(n381) );
CMPR32X2TS U1740 ( .A(DP_OP_110J126_122_4535_n218), .B(n1323), .C(n1322),
.CO(n1454), .S(n1324) );
AOI2BB2XLTS U1741 ( .B0(n1324), .B1(n1471), .A0N(n1656), .A1N(P_Sgf[20]),
.Y(n258) );
NAND2X1TS U1742 ( .A(Op_MX[3]), .B(n1325), .Y(DP_OP_110J126_122_4535_n740)
);
AOI32X1TS U1743 ( .A0(n1328), .A1(n692), .A2(n1327), .B0(n1727), .B1(n1326),
.Y(n310) );
AO22XLTS U1744 ( .A0(Sgf_normalized_result[6]), .A1(n1481), .B0(
final_result_ieee[6]), .B1(n1480), .Y(n194) );
AO22XLTS U1745 ( .A0(Sgf_normalized_result[5]), .A1(n1481), .B0(
final_result_ieee[5]), .B1(n1329), .Y(n195) );
AO22XLTS U1746 ( .A0(Sgf_normalized_result[4]), .A1(n1481), .B0(
final_result_ieee[4]), .B1(n1329), .Y(n196) );
AO22XLTS U1747 ( .A0(Sgf_normalized_result[3]), .A1(n1481), .B0(
final_result_ieee[3]), .B1(n1329), .Y(n197) );
AO22XLTS U1748 ( .A0(Sgf_normalized_result[2]), .A1(n1481), .B0(
final_result_ieee[2]), .B1(n1329), .Y(n198) );
AO22XLTS U1749 ( .A0(Sgf_normalized_result[1]), .A1(n1481), .B0(
final_result_ieee[1]), .B1(n1329), .Y(n199) );
NAND2X1TS U1750 ( .A(Op_MX[9]), .B(n1330), .Y(DP_OP_110J126_122_4535_n698)
);
AO22XLTS U1751 ( .A0(Sgf_normalized_result[0]), .A1(n1481), .B0(
final_result_ieee[0]), .B1(n1331), .Y(n200) );
CLKBUFX3TS U1752 ( .A(n1414), .Y(n1479) );
INVX2TS U1753 ( .A(n1426), .Y(n1494) );
AO22XLTS U1754 ( .A0(n1497), .A1(Op_MX[12]), .B0(n1494), .B1(Data_MX[12]),
.Y(n356) );
AO21XLTS U1755 ( .A0(n1557), .A1(n1332), .B0(n556), .Y(
DP_OP_110J126_122_4535_n243) );
AOI32X1TS U1756 ( .A0(FS_Module_state_reg[1]), .A1(n1667), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1333), .Y(
n1336) );
NAND3XLTS U1757 ( .A(n1336), .B(n1335), .C(n1334), .Y(n377) );
AO22XLTS U1758 ( .A0(n1495), .A1(Op_MX[13]), .B0(n1494), .B1(Data_MX[13]),
.Y(n357) );
CLKBUFX3TS U1759 ( .A(n1414), .Y(n1495) );
INVX2TS U1760 ( .A(n1426), .Y(n1496) );
AO22XLTS U1761 ( .A0(n1479), .A1(Op_MX[1]), .B0(n1496), .B1(Data_MX[1]), .Y(
n345) );
AO21XLTS U1762 ( .A0(n1557), .A1(n1250), .B0(n558), .Y(
DP_OP_110J126_122_4535_n241) );
AO22XLTS U1763 ( .A0(n1497), .A1(Op_MX[9]), .B0(n1494), .B1(Data_MX[9]), .Y(
n353) );
CLKAND2X2TS U1764 ( .A(n1337), .B(n617), .Y(DP_OP_110J126_122_4535_n288) );
INVX2TS U1765 ( .A(n1426), .Y(n1372) );
AO22XLTS U1766 ( .A0(n1511), .A1(Op_MX[16]), .B0(n1372), .B1(Data_MX[16]),
.Y(n360) );
AO22XLTS U1767 ( .A0(n1495), .A1(Op_MX[0]), .B0(n1496), .B1(Data_MX[0]), .Y(
n344) );
CLKAND2X2TS U1768 ( .A(n1338), .B(n618), .Y(DP_OP_110J126_122_4535_n273) );
AO22XLTS U1769 ( .A0(n1479), .A1(Op_MX[15]), .B0(n1372), .B1(Data_MX[15]),
.Y(n359) );
NAND4XLTS U1770 ( .A(n519), .B(n1661), .C(n470), .D(n521), .Y(n1339) );
NOR4X1TS U1771 ( .A(Op_MY[27]), .B(Op_MY[26]), .C(Op_MY[25]), .D(Op_MY[24]),
.Y(n1346) );
NOR4X1TS U1772 ( .A(Op_MY[13]), .B(n585), .C(Op_MY[29]), .D(Op_MY[28]), .Y(
n1345) );
NOR4X1TS U1773 ( .A(n584), .B(Op_MY[23]), .C(Op_MY[30]), .D(n644), .Y(n1342)
);
AND4X1TS U1774 ( .A(n1343), .B(n1342), .C(n1341), .D(n1340), .Y(n1344) );
NAND4XLTS U1775 ( .A(n1347), .B(n1346), .C(n1345), .D(n1344), .Y(n1361) );
NAND2X1TS U1776 ( .A(n1664), .B(n1693), .Y(n1349) );
NOR4X1TS U1777 ( .A(Op_MX[14]), .B(n1349), .C(n615), .D(n1348), .Y(n1359) );
NOR4X1TS U1778 ( .A(Op_MX[15]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n1358) );
NOR4X1TS U1779 ( .A(Op_MX[29]), .B(Op_MX[28]), .C(Op_MX[27]), .D(Op_MX[24]),
.Y(n1357) );
NAND4XLTS U1780 ( .A(n1351), .B(n1350), .C(n1668), .D(n1718), .Y(n1355) );
NOR4X1TS U1781 ( .A(Op_MX[4]), .B(Op_MX[17]), .C(Op_MX[18]), .D(Op_MX[30]),
.Y(n1352) );
NAND4XLTS U1782 ( .A(n1353), .B(n1352), .C(n1721), .D(n1672), .Y(n1354) );
NAND4XLTS U1783 ( .A(n1359), .B(n1358), .C(n1357), .D(n1356), .Y(n1360) );
AOI32X1TS U1784 ( .A0(n1361), .A1(n1406), .A2(n1360), .B0(n1695), .B1(n1498),
.Y(n311) );
AO22XLTS U1785 ( .A0(n1511), .A1(Op_MX[10]), .B0(n1494), .B1(Data_MX[10]),
.Y(n354) );
AO22XLTS U1786 ( .A0(n1478), .A1(Op_MX[17]), .B0(n1372), .B1(Data_MX[17]),
.Y(n361) );
AO22XLTS U1787 ( .A0(n1479), .A1(Op_MX[5]), .B0(n1494), .B1(Data_MX[5]), .Y(
n349) );
AO22XLTS U1788 ( .A0(n1478), .A1(Op_MX[2]), .B0(n1494), .B1(Data_MX[2]), .Y(
n346) );
CLKBUFX3TS U1789 ( .A(n1386), .Y(n1507) );
INVX2TS U1790 ( .A(n1493), .Y(n1506) );
XNOR2X1TS U1791 ( .A(n1362), .B(DP_OP_110J126_122_4535_n528), .Y(n1363) );
XNOR2X1TS U1792 ( .A(n1364), .B(n1363), .Y(n1365) );
AO22XLTS U1793 ( .A0(n1507), .A1(P_Sgf[25]), .B0(n1506), .B1(n1365), .Y(n263) );
AO22XLTS U1794 ( .A0(n1497), .A1(Op_MX[3]), .B0(n1494), .B1(Data_MX[3]), .Y(
n347) );
INVX2TS U1795 ( .A(n1493), .Y(n1492) );
NAND2BXLTS U1796 ( .AN(n1367), .B(n1366), .Y(n1368) );
XNOR2X1TS U1797 ( .A(n1369), .B(n1368), .Y(n1370) );
AO22XLTS U1798 ( .A0(n1507), .A1(P_Sgf[24]), .B0(n1492), .B1(n1370), .Y(n262) );
AO22XLTS U1799 ( .A0(n1495), .A1(Op_MX[7]), .B0(n1494), .B1(Data_MX[7]), .Y(
n351) );
INVX2TS U1800 ( .A(n1426), .Y(n1510) );
AO22XLTS U1801 ( .A0(n1497), .A1(Op_MX[21]), .B0(n1510), .B1(Data_MX[21]),
.Y(n365) );
OR3X1TS U1802 ( .A(Sgf_normalized_result[2]), .B(Sgf_normalized_result[1]),
.C(Sgf_normalized_result[0]), .Y(n1586) );
OAI21XLTS U1803 ( .A0(Sgf_normalized_result[1]), .A1(
Sgf_normalized_result[0]), .B0(Sgf_normalized_result[2]), .Y(n1371) );
AOI32X1TS U1804 ( .A0(n1586), .A1(n1486), .A2(n1371), .B0(n1728), .B1(n1408),
.Y(n307) );
AO22XLTS U1805 ( .A0(n1495), .A1(Op_MX[19]), .B0(n1372), .B1(Data_MX[19]),
.Y(n363) );
AO22XLTS U1806 ( .A0(n1511), .A1(Op_MX[14]), .B0(n1494), .B1(Data_MX[14]),
.Y(n358) );
CMPR32X2TS U1807 ( .A(DP_OP_110J126_122_4535_n222), .B(n1374), .C(n1373),
.CO(n1462), .S(n1375) );
AOI2BB2XLTS U1808 ( .B0(n1375), .B1(n1648), .A0N(n1506), .A1N(P_Sgf[16]),
.Y(n254) );
CLKBUFX3TS U1809 ( .A(n1081), .Y(n1620) );
NAND2X1TS U1810 ( .A(Sgf_normalized_result[3]), .B(n1586), .Y(n1585) );
NAND2X1TS U1811 ( .A(Sgf_normalized_result[5]), .B(n1589), .Y(n1588) );
NAND2X1TS U1812 ( .A(Sgf_normalized_result[7]), .B(n1592), .Y(n1591) );
NAND2X1TS U1813 ( .A(Sgf_normalized_result[9]), .B(n1595), .Y(n1594) );
NAND2X1TS U1814 ( .A(Sgf_normalized_result[11]), .B(n1598), .Y(n1597) );
NAND2X1TS U1815 ( .A(Sgf_normalized_result[13]), .B(n1601), .Y(n1600) );
NAND2X1TS U1816 ( .A(Sgf_normalized_result[15]), .B(n1604), .Y(n1603) );
NAND2X1TS U1817 ( .A(Sgf_normalized_result[17]), .B(n1607), .Y(n1606) );
NAND2X1TS U1818 ( .A(Sgf_normalized_result[19]), .B(n1610), .Y(n1609) );
NAND2X1TS U1819 ( .A(Sgf_normalized_result[21]), .B(n1614), .Y(n1612) );
AOI211XLTS U1820 ( .A0(n1719), .A1(n1612), .B0(n1618), .C0(n1408), .Y(n1376)
);
AO21XLTS U1821 ( .A0(Add_result[22]), .A1(n1620), .B0(n1376), .Y(n287) );
CMPR32X2TS U1822 ( .A(DP_OP_110J126_122_4535_n527), .B(n1378), .C(n1377),
.CO(n1652), .S(n1379) );
AOI2BB2XLTS U1823 ( .B0(n1379), .B1(n1471), .A0N(n1506), .A1N(P_Sgf[26]),
.Y(n264) );
NOR2XLTS U1824 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n1380) );
AOI21X1TS U1825 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1380), .Y(n1381) );
INVX2TS U1826 ( .A(n1081), .Y(n1485) );
AOI2BB2XLTS U1827 ( .B0(n1486), .B1(n1381), .A0N(Add_result[1]), .A1N(n1485),
.Y(n308) );
OAI21XLTS U1828 ( .A0(n1585), .A1(n1722), .B0(n1589), .Y(n1382) );
AO22XLTS U1829 ( .A0(n1486), .A1(n1382), .B0(n1620), .B1(Add_result[4]), .Y(
n305) );
AOI21X1TS U1830 ( .A0(DP_OP_110J126_122_4535_n509), .A1(n1624), .B0(n1622),
.Y(n1383) );
AO22XLTS U1831 ( .A0(n1386), .A1(P_Sgf[44]), .B0(n1492), .B1(n1383), .Y(n282) );
AOI21X1TS U1832 ( .A0(DP_OP_110J126_122_4535_n511), .A1(n1627), .B0(n1625),
.Y(n1384) );
AO22XLTS U1833 ( .A0(n1507), .A1(P_Sgf[42]), .B0(n1492), .B1(n1384), .Y(n280) );
AOI21X1TS U1834 ( .A0(DP_OP_110J126_122_4535_n513), .A1(n1630), .B0(n1628),
.Y(n1385) );
AO22XLTS U1835 ( .A0(n1507), .A1(P_Sgf[40]), .B0(n1492), .B1(n1385), .Y(n278) );
AOI21X1TS U1836 ( .A0(DP_OP_110J126_122_4535_n515), .A1(n1387), .B0(n1631),
.Y(n1388) );
AO22XLTS U1837 ( .A0(n1657), .A1(P_Sgf[38]), .B0(n1492), .B1(n1388), .Y(n276) );
AOI21X1TS U1838 ( .A0(n1717), .A1(n1609), .B0(n1614), .Y(n1389) );
AO22XLTS U1839 ( .A0(n1486), .A1(n1389), .B0(n1081), .B1(Add_result[20]),
.Y(n289) );
CMPR32X2TS U1840 ( .A(n1391), .B(n1390), .C(DP_OP_110J126_122_4535_n523),
.CO(n1644), .S(n1392) );
AOI2BB2XLTS U1841 ( .B0(n1392), .B1(n1471), .A0N(n1476), .A1N(P_Sgf[30]),
.Y(n268) );
CMPR32X2TS U1842 ( .A(DP_OP_110J126_122_4535_n521), .B(n1394), .C(n1393),
.CO(n1641), .S(n1395) );
AOI2BB2XLTS U1843 ( .B0(n1395), .B1(n1471), .A0N(n1476), .A1N(P_Sgf[32]),
.Y(n270) );
AOI21X1TS U1844 ( .A0(n1716), .A1(n1606), .B0(n1610), .Y(n1396) );
AO22XLTS U1845 ( .A0(n1485), .A1(n1396), .B0(n1408), .B1(Add_result[18]),
.Y(n291) );
CMPR32X2TS U1846 ( .A(DP_OP_110J126_122_4535_n519), .B(n1398), .C(n1397),
.CO(n1638), .S(n1399) );
AOI2BB2XLTS U1847 ( .B0(n1399), .B1(n1477), .A0N(n1506), .A1N(P_Sgf[34]),
.Y(n272) );
AOI21X1TS U1848 ( .A0(n1715), .A1(n1603), .B0(n1607), .Y(n1400) );
AO22XLTS U1849 ( .A0(n1485), .A1(n1400), .B0(n1408), .B1(Add_result[16]),
.Y(n293) );
CMPR32X2TS U1850 ( .A(DP_OP_110J126_122_4535_n517), .B(n1402), .C(n1401),
.CO(n1633), .S(n1403) );
AOI2BB2XLTS U1851 ( .B0(n1403), .B1(n1477), .A0N(n1476), .A1N(P_Sgf[36]),
.Y(n274) );
AOI21X1TS U1852 ( .A0(n1714), .A1(n1600), .B0(n1604), .Y(n1404) );
AO22XLTS U1853 ( .A0(n1485), .A1(n1404), .B0(n1408), .B1(Add_result[14]),
.Y(n295) );
AOI21X1TS U1854 ( .A0(n1713), .A1(n1597), .B0(n1601), .Y(n1405) );
AO22XLTS U1855 ( .A0(n1485), .A1(n1405), .B0(n1408), .B1(Add_result[12]),
.Y(n297) );
AOI21X1TS U1856 ( .A0(n1618), .A1(Sgf_normalized_result[23]), .B0(n1408),
.Y(n1617) );
AOI2BB1XLTS U1857 ( .A0N(n1486), .A1N(FSM_add_overflow_flag), .B0(n1617),
.Y(n285) );
NOR2X4TS U1858 ( .A(n1406), .B(n1656), .Y(n1415) );
MX2X1TS U1859 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1415),
.Y(n227) );
AOI21X1TS U1860 ( .A0(n1712), .A1(n1594), .B0(n1598), .Y(n1407) );
AO22XLTS U1861 ( .A0(n1486), .A1(n1407), .B0(n1408), .B1(Add_result[10]),
.Y(n299) );
MX2X1TS U1862 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1415),
.Y(n228) );
AOI21X1TS U1863 ( .A0(n1711), .A1(n1591), .B0(n1595), .Y(n1409) );
AO22XLTS U1864 ( .A0(n1486), .A1(n1409), .B0(n1408), .B1(Add_result[8]), .Y(
n301) );
MX2X1TS U1865 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1415),
.Y(n229) );
AOI21X1TS U1866 ( .A0(n1710), .A1(n1588), .B0(n1592), .Y(n1410) );
AO22XLTS U1867 ( .A0(n1486), .A1(n1410), .B0(n1620), .B1(Add_result[6]), .Y(
n303) );
MX2X1TS U1868 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1415),
.Y(n230) );
MX2X1TS U1869 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1415),
.Y(n231) );
NOR3XLTS U1870 ( .A(Exp_module_Data_S[7]), .B(Exp_module_Data_S[8]), .C(
n1498), .Y(n1413) );
AND4X1TS U1871 ( .A(Exp_module_Data_S[6]), .B(Exp_module_Data_S[3]), .C(
Exp_module_Data_S[2]), .D(Exp_module_Data_S[1]), .Y(n1411) );
NAND4XLTS U1872 ( .A(Exp_module_Data_S[0]), .B(Exp_module_Data_S[5]), .C(
Exp_module_Data_S[4]), .D(n1411), .Y(n1412) );
AO22XLTS U1873 ( .A0(n1413), .A1(n1412), .B0(underflow_flag), .B1(n1498),
.Y(n201) );
MX2X1TS U1874 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1415),
.Y(n232) );
MX2X1TS U1875 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1415),
.Y(n233) );
MX2X1TS U1876 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1415),
.Y(n234) );
CLKBUFX2TS U1877 ( .A(n1414), .Y(n1508) );
INVX2TS U1878 ( .A(n1508), .Y(n1509) );
MX2X1TS U1879 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1509), .Y(n335) );
AO22XLTS U1880 ( .A0(n1427), .A1(Data_MX[29]), .B0(n1497), .B1(Op_MX[29]),
.Y(n373) );
MX2X1TS U1881 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1415),
.Y(n226) );
NOR2XLTS U1882 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1416) );
NAND2X2TS U1883 ( .A(FSM_selector_B[0]), .B(n1692), .Y(n1423) );
XOR2X1TS U1884 ( .A(DP_OP_36J126_123_9196_n33), .B(n1417), .Y(
DP_OP_36J126_123_9196_n22) );
MX2X1TS U1885 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U1886 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
OAI2BB1X1TS U1887 ( .A0N(Op_MY[24]), .A1N(n1692), .B0(n1423), .Y(n1418) );
XOR2X1TS U1888 ( .A(DP_OP_36J126_123_9196_n33), .B(n1418), .Y(
DP_OP_36J126_123_9196_n21) );
MX2X1TS U1889 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
OAI2BB1X1TS U1890 ( .A0N(Op_MY[25]), .A1N(n1692), .B0(n1423), .Y(n1419) );
XOR2X1TS U1891 ( .A(DP_OP_36J126_123_9196_n33), .B(n1419), .Y(
DP_OP_36J126_123_9196_n20) );
MX2X1TS U1892 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
OAI2BB1X1TS U1893 ( .A0N(Op_MY[26]), .A1N(n1692), .B0(n1423), .Y(n1420) );
XOR2X1TS U1894 ( .A(DP_OP_36J126_123_9196_n33), .B(n1420), .Y(
DP_OP_36J126_123_9196_n19) );
MX2X1TS U1895 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
OAI2BB1X1TS U1896 ( .A0N(Op_MY[27]), .A1N(n1692), .B0(n1423), .Y(n1421) );
XOR2X1TS U1897 ( .A(DP_OP_36J126_123_9196_n33), .B(n1421), .Y(
DP_OP_36J126_123_9196_n18) );
MX2X1TS U1898 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
OAI2BB1X1TS U1899 ( .A0N(Op_MY[28]), .A1N(n1692), .B0(n1423), .Y(n1422) );
XOR2X1TS U1900 ( .A(n624), .B(n1422), .Y(DP_OP_36J126_123_9196_n17) );
MX2X1TS U1901 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
OAI2BB1X1TS U1902 ( .A0N(Op_MY[29]), .A1N(n1692), .B0(n1423), .Y(n1424) );
XOR2X1TS U1903 ( .A(n624), .B(n1424), .Y(DP_OP_36J126_123_9196_n16) );
MX2X1TS U1904 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
NOR3BX1TS U1905 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n1425) );
XOR2X1TS U1906 ( .A(n624), .B(n1425), .Y(DP_OP_36J126_123_9196_n15) );
CLKAND2X2TS U1907 ( .A(FSM_selector_A), .B(exp_oper_result[8]), .Y(
S_Oper_A_exp[8]) );
AO22XLTS U1908 ( .A0(n1427), .A1(Data_MX[23]), .B0(n1495), .B1(Op_MX[23]),
.Y(n367) );
AO22XLTS U1909 ( .A0(n1427), .A1(Data_MX[24]), .B0(n1511), .B1(Op_MX[24]),
.Y(n368) );
AO22XLTS U1910 ( .A0(n1427), .A1(Data_MX[30]), .B0(n1479), .B1(Op_MX[30]),
.Y(n374) );
AO22XLTS U1911 ( .A0(n1509), .A1(Data_MX[26]), .B0(n1478), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U1912 ( .A0(n1427), .A1(Data_MX[28]), .B0(n1497), .B1(Op_MX[28]),
.Y(n372) );
AO22XLTS U1913 ( .A0(n1509), .A1(Data_MX[25]), .B0(n1495), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U1914 ( .A0(n1427), .A1(Data_MX[27]), .B0(n1511), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U1915 ( .A0(n1427), .A1(Data_MX[22]), .B0(n1497), .B1(Op_MX[22]),
.Y(n366) );
AO22XLTS U1916 ( .A0(n1509), .A1(Data_MY[30]), .B0(n1479), .B1(Op_MY[30]),
.Y(n342) );
AO22XLTS U1917 ( .A0(n1510), .A1(Data_MX[8]), .B0(n1478), .B1(Op_MX[8]), .Y(
n352) );
AO22XLTS U1918 ( .A0(n1509), .A1(Data_MY[27]), .B0(Op_MY[27]), .B1(n1508),
.Y(n339) );
AO22XLTS U1919 ( .A0(n1427), .A1(Data_MX[20]), .B0(n1495), .B1(Op_MX[20]),
.Y(n364) );
AO22XLTS U1920 ( .A0(n1509), .A1(Data_MY[24]), .B0(n1508), .B1(Op_MY[24]),
.Y(n336) );
AO22XLTS U1921 ( .A0(n1510), .A1(Data_MX[6]), .B0(n1414), .B1(Op_MX[6]), .Y(
n350) );
AO22XLTS U1922 ( .A0(n1509), .A1(Data_MY[28]), .B0(n1508), .B1(Op_MY[28]),
.Y(n340) );
AO22XLTS U1923 ( .A0(n1427), .A1(Data_MX[18]), .B0(n1478), .B1(Op_MX[18]),
.Y(n362) );
AO22XLTS U1924 ( .A0(n1510), .A1(Data_MX[4]), .B0(n1511), .B1(Op_MX[4]), .Y(
n348) );
AO22XLTS U1925 ( .A0(n1509), .A1(Data_MY[26]), .B0(n1508), .B1(Op_MY[26]),
.Y(n338) );
CMPR32X2TS U1926 ( .A(DP_OP_110J126_122_4535_n525), .B(n1429), .C(n1428),
.CO(n1647), .S(n1430) );
AOI2BB2XLTS U1927 ( .B0(n1430), .B1(n1471), .A0N(n1506), .A1N(P_Sgf[28]),
.Y(n266) );
CLKBUFX3TS U1928 ( .A(n1414), .Y(n1497) );
AO22XLTS U1929 ( .A0(n1511), .A1(n645), .B0(n1496), .B1(Data_MY[18]), .Y(
n330) );
CMPR32X2TS U1930 ( .A(n1433), .B(n1432), .C(n1431), .CO(n838), .S(
DP_OP_110J126_122_4535_n227) );
AOI2BB2XLTS U1931 ( .B0(DP_OP_110J126_122_4535_n227), .B1(n1477), .A0N(n1506), .A1N(P_Sgf[11]), .Y(n249) );
INVX2TS U1932 ( .A(n1426), .Y(n1499) );
AO22XLTS U1933 ( .A0(n1478), .A1(n646), .B0(n1499), .B1(Data_MY[13]), .Y(
n325) );
CMPR32X2TS U1934 ( .A(n1436), .B(n1435), .C(n1434), .CO(n1456), .S(
DP_OP_110J126_122_4535_n230) );
AOI2BB2XLTS U1935 ( .B0(DP_OP_110J126_122_4535_n230), .B1(n1477), .A0N(n1656), .A1N(P_Sgf[8]), .Y(n246) );
AO22XLTS U1936 ( .A0(n1497), .A1(n643), .B0(n1496), .B1(Data_MY[20]), .Y(
n332) );
AOI2BB2XLTS U1937 ( .B0(DP_OP_110J126_122_4535_n234), .B1(n1477), .A0N(n1476), .A1N(P_Sgf[4]), .Y(n242) );
AO22XLTS U1938 ( .A0(n1495), .A1(n644), .B0(n1499), .B1(Data_MY[16]), .Y(
n328) );
CMPR32X2TS U1939 ( .A(DP_OP_110J126_122_4535_n219), .B(n1438), .C(n1437),
.CO(n1323), .S(n1439) );
AOI2BB2XLTS U1940 ( .B0(n1439), .B1(n1648), .A0N(n1656), .A1N(P_Sgf[19]),
.Y(n257) );
AO22XLTS U1941 ( .A0(n1479), .A1(n394), .B0(n1496), .B1(Data_MY[19]), .Y(
n331) );
CMPR32X2TS U1942 ( .A(DP_OP_110J126_122_4535_n223), .B(n1441), .C(n1440),
.CO(n1374), .S(n1442) );
AOI2BB2XLTS U1943 ( .B0(n1442), .B1(n1471), .A0N(n1476), .A1N(P_Sgf[15]),
.Y(n253) );
AO22XLTS U1944 ( .A0(n1414), .A1(n587), .B0(n1510), .B1(Data_MY[4]), .Y(n316) );
CMPR32X2TS U1945 ( .A(n1445), .B(n1444), .C(n1443), .CO(n1431), .S(
DP_OP_110J126_122_4535_n228) );
AOI2BB2XLTS U1946 ( .B0(DP_OP_110J126_122_4535_n228), .B1(n1477), .A0N(n1506), .A1N(P_Sgf[10]), .Y(n248) );
AO22XLTS U1947 ( .A0(n1414), .A1(n582), .B0(n1499), .B1(Data_MY[8]), .Y(n320) );
CMPR32X2TS U1948 ( .A(n1448), .B(n1447), .C(n1446), .CO(n1434), .S(
DP_OP_110J126_122_4535_n231) );
AOI2BB2XLTS U1949 ( .B0(DP_OP_110J126_122_4535_n231), .B1(n1477), .A0N(n1476), .A1N(P_Sgf[7]), .Y(n245) );
AO22XLTS U1950 ( .A0(n1426), .A1(n581), .B0(n1499), .B1(Data_MY[7]), .Y(n319) );
AO22XLTS U1951 ( .A0(n1507), .A1(P_Sgf[1]), .B0(n1492), .B1(n1449), .Y(n239)
);
AO22XLTS U1952 ( .A0(n1478), .A1(n583), .B0(n1510), .B1(Data_MY[6]), .Y(n318) );
CMPR32X2TS U1953 ( .A(DP_OP_110J126_122_4535_n216), .B(n1451), .C(n1450),
.CO(n1501), .S(n1452) );
AOI2BB2XLTS U1954 ( .B0(n1452), .B1(n1648), .A0N(n1656), .A1N(P_Sgf[22]),
.Y(n260) );
AO22XLTS U1955 ( .A0(n1511), .A1(n586), .B0(n1499), .B1(Data_MY[10]), .Y(
n322) );
CMPR32X2TS U1956 ( .A(DP_OP_110J126_122_4535_n217), .B(n1454), .C(n1453),
.CO(n1451), .S(n1455) );
AOI2BB2XLTS U1957 ( .B0(n1455), .B1(n1471), .A0N(n1656), .A1N(P_Sgf[21]),
.Y(n259) );
CMPR32X2TS U1958 ( .A(n1458), .B(n1457), .C(n1456), .CO(n1443), .S(
DP_OP_110J126_122_4535_n229) );
AOI2BB2XLTS U1959 ( .B0(DP_OP_110J126_122_4535_n229), .B1(n1477), .A0N(n1476), .A1N(P_Sgf[9]), .Y(n247) );
AO22XLTS U1960 ( .A0(n1497), .A1(Op_MY[22]), .B0(n1496), .B1(Data_MY[22]),
.Y(n334) );
AO22XLTS U1961 ( .A0(n1506), .A1(n1459), .B0(n1493), .B1(P_Sgf[5]), .Y(n243)
);
AO22XLTS U1962 ( .A0(n1426), .A1(n584), .B0(n1510), .B1(Data_MY[3]), .Y(n315) );
XOR2XLTS U1963 ( .A(DP_OP_110J126_122_4535_n221), .B(n1460), .Y(n1461) );
XOR2XLTS U1964 ( .A(n1462), .B(n1461), .Y(n1463) );
AO22XLTS U1965 ( .A0(n1507), .A1(P_Sgf[17]), .B0(n1492), .B1(n1463), .Y(n255) );
AO22XLTS U1966 ( .A0(n1478), .A1(Op_MY[11]), .B0(n1499), .B1(Data_MY[11]),
.Y(n323) );
AOI21X1TS U1967 ( .A0(DP_OP_110J126_122_4535_n226), .A1(n1464), .B0(n1487),
.Y(n1465) );
AO22XLTS U1968 ( .A0(n1507), .A1(P_Sgf[12]), .B0(n1492), .B1(n1465), .Y(n250) );
AO22XLTS U1969 ( .A0(n1495), .A1(n573), .B0(n1496), .B1(Data_MY[21]), .Y(
n333) );
CMPR32X2TS U1970 ( .A(DP_OP_110J126_122_4535_n220), .B(n1467), .C(n1466),
.CO(n1438), .S(n1468) );
AOI2BB2XLTS U1971 ( .B0(n1468), .B1(n1471), .A0N(n1476), .A1N(P_Sgf[18]),
.Y(n256) );
AO22XLTS U1972 ( .A0(n1479), .A1(n572), .B0(n1499), .B1(Data_MY[15]), .Y(
n327) );
CMPR32X2TS U1973 ( .A(DP_OP_110J126_122_4535_n224), .B(n1470), .C(n1469),
.CO(n1441), .S(n1472) );
AOI2BB2XLTS U1974 ( .B0(n1472), .B1(n1471), .A0N(n1506), .A1N(P_Sgf[14]),
.Y(n252) );
AO22XLTS U1975 ( .A0(n1497), .A1(n574), .B0(n1496), .B1(Data_MY[17]), .Y(
n329) );
CMPR32X2TS U1976 ( .A(n1475), .B(n1474), .C(n1473), .CO(n1446), .S(
DP_OP_110J126_122_4535_n232) );
AOI2BB2XLTS U1977 ( .B0(DP_OP_110J126_122_4535_n232), .B1(n1477), .A0N(n1476), .A1N(P_Sgf[6]), .Y(n244) );
AO22XLTS U1978 ( .A0(n1479), .A1(n568), .B0(n1510), .B1(Data_MY[2]), .Y(n314) );
AO22XLTS U1979 ( .A0(Sgf_normalized_result[7]), .A1(n1481), .B0(
final_result_ieee[7]), .B1(n1480), .Y(n193) );
AOI21X1TS U1980 ( .A0(DP_OP_110J126_122_4535_n507), .A1(n1621), .B0(n1482),
.Y(n1483) );
AO22XLTS U1981 ( .A0(n1507), .A1(P_Sgf[46]), .B0(n1484), .B1(n1483), .Y(n284) );
AOI2BB2XLTS U1982 ( .B0(n1486), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1485), .Y(n309) );
AO22XLTS U1983 ( .A0(n1511), .A1(Op_MY[0]), .B0(n1496), .B1(Data_MY[0]), .Y(
n312) );
AO22XLTS U1984 ( .A0(n1511), .A1(n564), .B0(n1499), .B1(Data_MY[5]), .Y(n317) );
AO22XLTS U1985 ( .A0(n1509), .A1(Data_MY[25]), .B0(n1508), .B1(Op_MY[25]),
.Y(n337) );
AO22XLTS U1986 ( .A0(n1426), .A1(n560), .B0(n1499), .B1(Data_MY[12]), .Y(
n324) );
XOR2XLTS U1987 ( .A(n1487), .B(DP_OP_110J126_122_4535_n225), .Y(n1488) );
XNOR2X1TS U1988 ( .A(n1489), .B(n1488), .Y(n1490) );
AO22XLTS U1989 ( .A0(n1507), .A1(P_Sgf[13]), .B0(n1492), .B1(n1490), .Y(n251) );
AO22XLTS U1990 ( .A0(n1493), .A1(P_Sgf[0]), .B0(n1492), .B1(n1491), .Y(n238)
);
AO22XLTS U1991 ( .A0(n1479), .A1(n641), .B0(n1494), .B1(Data_MX[11]), .Y(
n355) );
AO22XLTS U1992 ( .A0(n1495), .A1(n569), .B0(n1496), .B1(Data_MY[14]), .Y(
n326) );
NAND2X1TS U1993 ( .A(n1498), .B(n647), .Y(n376) );
AO22XLTS U1994 ( .A0(n1426), .A1(n566), .B0(n1499), .B1(Data_MY[9]), .Y(n321) );
OAI21XLTS U1995 ( .A0(n1502), .A1(n1501), .B0(n1500), .Y(n1503) );
XNOR2X1TS U1996 ( .A(n1504), .B(n1503), .Y(n1505) );
AO22XLTS U1997 ( .A0(n1507), .A1(P_Sgf[23]), .B0(n1506), .B1(n1505), .Y(n261) );
AO22XLTS U1998 ( .A0(n1509), .A1(Data_MY[29]), .B0(n1508), .B1(Op_MY[29]),
.Y(n341) );
AO22XLTS U1999 ( .A0(n1478), .A1(n562), .B0(n1510), .B1(Data_MY[1]), .Y(n313) );
NAND2BXLTS U2000 ( .AN(n484), .B(n480), .Y(DP_OP_110J126_122_4535_n1080) );
NAND2X1TS U2001 ( .A(Op_MX[19]), .B(n1513), .Y(DP_OP_110J126_122_4535_n1093)
);
AOI22X1TS U2002 ( .A0(Op_MY[20]), .A1(n597), .B0(n476), .B1(n1684), .Y(n1514) );
AOI22X1TS U2003 ( .A0(n573), .A1(n452), .B0(n514), .B1(n1687), .Y(n1518) );
NAND2X1TS U2004 ( .A(n503), .B(n1521), .Y(DP_OP_110J126_122_4535_n1122) );
CLKAND2X2TS U2005 ( .A(n1522), .B(n617), .Y(DP_OP_110J126_122_4535_n303) );
NAND2X1TS U2006 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n1523) );
NAND2X1TS U2007 ( .A(Op_MX[7]), .B(n1523), .Y(DP_OP_110J126_122_4535_n712)
);
NAND2X1TS U2008 ( .A(Op_MX[5]), .B(n1524), .Y(DP_OP_110J126_122_4535_n726)
);
NOR4X1TS U2009 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n1525) );
NAND3BXLTS U2010 ( .AN(P_Sgf[3]), .B(n1525), .C(n1709), .Y(n1535) );
NOR4X1TS U2011 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[17]),
.Y(n1529) );
NOR4X1TS U2012 ( .A(P_Sgf[18]), .B(P_Sgf[19]), .C(P_Sgf[20]), .D(P_Sgf[21]),
.Y(n1528) );
NOR4X1TS U2013 ( .A(P_Sgf[13]), .B(P_Sgf[10]), .C(P_Sgf[11]), .D(P_Sgf[12]),
.Y(n1527) );
NOR4X1TS U2014 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n1526) );
NAND4XLTS U2015 ( .A(n1529), .B(n1528), .C(n1527), .D(n1526), .Y(n1534) );
INVX2TS U2016 ( .A(round_mode[1]), .Y(n1531) );
NAND3XLTS U2017 ( .A(round_mode[0]), .B(n1532), .C(n1531), .Y(n1530) );
OAI31X1TS U2018 ( .A0(round_mode[0]), .A1(n1532), .A2(n1531), .B0(n1530),
.Y(n1533) );
OAI31X1TS U2019 ( .A0(P_Sgf[22]), .A1(n1535), .A2(n1534), .B0(n1533), .Y(
n1583) );
AOI22X1TS U2020 ( .A0(n1537), .A1(n1536), .B0(n1582), .B1(n1583), .Y(n1538)
);
OAI2BB1X1TS U2021 ( .A0N(n1539), .A1N(n1733), .B0(n1538), .Y(n378) );
AOI21X1TS U2022 ( .A0(n1541), .A1(n1540), .B0(DP_OP_110J126_122_4535_n198),
.Y(DP_OP_110J126_122_4535_n199) );
AOI21X1TS U2023 ( .A0(n1543), .A1(n1542), .B0(DP_OP_110J126_122_4535_n635),
.Y(DP_OP_110J126_122_4535_n636) );
AOI21X1TS U2024 ( .A0(n1545), .A1(n1544), .B0(DP_OP_110J126_122_4535_n648),
.Y(DP_OP_110J126_122_4535_n649) );
AOI21X1TS U2025 ( .A0(n1547), .A1(n1546), .B0(DP_OP_110J126_122_4535_n658),
.Y(DP_OP_110J126_122_4535_n659) );
AOI21X1TS U2026 ( .A0(n1549), .A1(n1548), .B0(DP_OP_110J126_122_4535_n1017),
.Y(DP_OP_110J126_122_4535_n1018) );
AOI21X1TS U2027 ( .A0(n1551), .A1(n1550), .B0(DP_OP_110J126_122_4535_n1030),
.Y(DP_OP_110J126_122_4535_n1031) );
AOI21X1TS U2028 ( .A0(n1553), .A1(n1552), .B0(DP_OP_110J126_122_4535_n1040),
.Y(DP_OP_110J126_122_4535_n1041) );
OAI22X1TS U2029 ( .A0(n573), .A1(n615), .B0(n588), .B1(n498), .Y(
DP_OP_110J126_122_4535_n1068) );
OAI22X1TS U2030 ( .A0(n573), .A1(n497), .B0(n643), .B1(n1554), .Y(
DP_OP_110J126_122_4535_n1069) );
OAI22X1TS U2031 ( .A0(Op_MY[20]), .A1(n497), .B0(n589), .B1(n1554), .Y(
DP_OP_110J126_122_4535_n1070) );
OAI22X1TS U2032 ( .A0(Op_MY[18]), .A1(n615), .B0(n589), .B1(n498), .Y(
DP_OP_110J126_122_4535_n1071) );
OAI22X1TS U2033 ( .A0(Op_MY[18]), .A1(n497), .B0(n574), .B1(n1554), .Y(
DP_OP_110J126_122_4535_n1072) );
OAI22X1TS U2034 ( .A0(n574), .A1(n497), .B0(n644), .B1(n1554), .Y(
DP_OP_110J126_122_4535_n1073) );
OAI22X1TS U2035 ( .A0(Op_MY[16]), .A1(n497), .B0(n572), .B1(n1554), .Y(
DP_OP_110J126_122_4535_n1074) );
OAI22X1TS U2036 ( .A0(Op_MY[14]), .A1(n615), .B0(n572), .B1(n498), .Y(
DP_OP_110J126_122_4535_n1075) );
OAI22X1TS U2037 ( .A0(Op_MY[14]), .A1(n498), .B0(Op_MY[13]), .B1(n615), .Y(
DP_OP_110J126_122_4535_n1076) );
OAI22X1TS U2038 ( .A0(n559), .A1(n615), .B0(Op_MY[13]), .B1(n498), .Y(
DP_OP_110J126_122_4535_n1077) );
AOI22X1TS U2039 ( .A0(n569), .A1(n391), .B0(n484), .B1(n1677), .Y(n1555) );
OAI221XLTS U2040 ( .A0(n646), .A1(n501), .B0(n1683), .B1(n480), .C0(n1555),
.Y(DP_OP_110J126_122_4535_n1090) );
AOI22X1TS U2041 ( .A0(n578), .A1(n613), .B0(n577), .B1(n579), .Y(
DP_OP_110J126_122_4535_n246) );
AOI22X1TS U2042 ( .A0(n578), .A1(n528), .B0(n541), .B1(n579), .Y(
DP_OP_110J126_122_4535_n248) );
AOI22X1TS U2043 ( .A0(n578), .A1(n547), .B0(n528), .B1(n580), .Y(
DP_OP_110J126_122_4535_n249) );
AOI22X1TS U2044 ( .A0(n614), .A1(n551), .B0(n553), .B1(n580), .Y(
DP_OP_110J126_122_4535_n252) );
AOI22X1TS U2045 ( .A0(n614), .A1(n549), .B0(n551), .B1(n580), .Y(
DP_OP_110J126_122_4535_n253) );
AOI22X1TS U2046 ( .A0(n614), .A1(n526), .B0(n549), .B1(n580), .Y(
DP_OP_110J126_122_4535_n254) );
AOI22X1TS U2047 ( .A0(n614), .A1(n522), .B0(n526), .B1(n580), .Y(
DP_OP_110J126_122_4535_n255) );
AOI22X1TS U2048 ( .A0(n614), .A1(n545), .B0(n522), .B1(n580), .Y(
DP_OP_110J126_122_4535_n256) );
AOI22X1TS U2049 ( .A0(n614), .A1(n1557), .B0(n545), .B1(n580), .Y(
DP_OP_110J126_122_4535_n257) );
AOI22X1TS U2050 ( .A0(n554), .A1(n505), .B0(n628), .B1(n510), .Y(n1561) );
OAI221XLTS U2051 ( .A0(n552), .A1(n636), .B0(n509), .B1(n534), .C0(n1561),
.Y(DP_OP_110J126_122_4535_n267) );
AOI22X1TS U2052 ( .A0(n612), .A1(n555), .B0(n1567), .B1(n608), .Y(n1565) );
OAI221XLTS U2053 ( .A0(n577), .A1(n492), .B0(n512), .B1(n633), .C0(n1565),
.Y(DP_OP_110J126_122_4535_n321) );
AOI22X1TS U2054 ( .A0(n1568), .A1(n1567), .B0(n556), .B1(n524), .Y(n1569) );
OAI221XLTS U2055 ( .A0(n613), .A1(n492), .B0(n608), .B1(n633), .C0(n1569),
.Y(DP_OP_110J126_122_4535_n322) );
AOI21X1TS U2056 ( .A0(n575), .A1(n1573), .B0(n1572), .Y(
DP_OP_110J126_122_4535_n335) );
AOI22X1TS U2057 ( .A0(n583), .A1(n440), .B0(n517), .B1(n1680), .Y(n1574) );
OAI221XLTS U2058 ( .A0(Op_MY[7]), .A1(n622), .B0(n1681), .B1(n1575), .C0(
n1574), .Y(DP_OP_110J126_122_4535_n690) );
AOI22X1TS U2059 ( .A0(n568), .A1(n448), .B0(n1577), .B1(n470), .Y(n1578) );
OAI221XLTS U2060 ( .A0(n562), .A1(n607), .B0(n521), .B1(n632), .C0(n1578),
.Y(DP_OP_110J126_122_4535_n709) );
OAI221XLTS U2061 ( .A0(n473), .A1(n508), .B0(n474), .B1(n499), .C0(n398),
.Y(DP_OP_110J126_122_4535_n727) );
INVX2TS U2062 ( .A(n1582), .Y(n1584) );
OAI31X1TS U2063 ( .A0(FS_Module_state_reg[1]), .A1(n1584), .A2(n1583), .B0(
n404), .Y(n375) );
CLKBUFX2TS U2064 ( .A(n1081), .Y(n1616) );
INVX2TS U2065 ( .A(n1081), .Y(n1613) );
OAI211XLTS U2066 ( .A0(Sgf_normalized_result[3]), .A1(n1586), .B0(n1613),
.C0(n1585), .Y(n1587) );
OAI2BB1X1TS U2067 ( .A0N(Add_result[3]), .A1N(n1616), .B0(n1587), .Y(n306)
);
OAI211XLTS U2068 ( .A0(Sgf_normalized_result[5]), .A1(n1589), .B0(n1613),
.C0(n1588), .Y(n1590) );
OAI2BB1X1TS U2069 ( .A0N(Add_result[5]), .A1N(n1616), .B0(n1590), .Y(n304)
);
OAI2BB1X1TS U2070 ( .A0N(Add_result[7]), .A1N(n1620), .B0(n1593), .Y(n302)
);
OAI2BB1X1TS U2071 ( .A0N(Add_result[9]), .A1N(n1620), .B0(n1596), .Y(n300)
);
OAI2BB1X1TS U2072 ( .A0N(Add_result[11]), .A1N(n1620), .B0(n1599), .Y(n298)
);
OAI2BB1X1TS U2073 ( .A0N(Add_result[13]), .A1N(n1620), .B0(n1602), .Y(n296)
);
OAI2BB1X1TS U2074 ( .A0N(Add_result[15]), .A1N(n1620), .B0(n1605), .Y(n294)
);
OAI2BB1X1TS U2075 ( .A0N(Add_result[17]), .A1N(n1620), .B0(n1608), .Y(n292)
);
OAI2BB1X1TS U2076 ( .A0N(Add_result[19]), .A1N(n1616), .B0(n1611), .Y(n290)
);
OAI2BB1X1TS U2077 ( .A0N(Add_result[21]), .A1N(n1616), .B0(n1615), .Y(n288)
);
OAI2BB1X1TS U2078 ( .A0N(Add_result[23]), .A1N(n1620), .B0(n1619), .Y(n286)
);
OAI21XLTS U2079 ( .A0(n1622), .A1(Sgf_operation_EVEN1_Q_left[21]), .B0(n1621), .Y(n1623) );
AOI22X1TS U2080 ( .A0(n1657), .A1(n1708), .B0(n1623), .B1(n1648), .Y(n283)
);
OAI21XLTS U2081 ( .A0(n1625), .A1(Sgf_operation_EVEN1_Q_left[19]), .B0(n1624), .Y(n1626) );
AOI22X1TS U2082 ( .A0(n1386), .A1(n1696), .B0(n1626), .B1(n1648), .Y(n281)
);
OAI21XLTS U2083 ( .A0(n1628), .A1(Sgf_operation_EVEN1_Q_left[17]), .B0(n1627), .Y(n1629) );
AOI22X1TS U2084 ( .A0(n1386), .A1(n1697), .B0(n1629), .B1(n1648), .Y(n279)
);
OAI21XLTS U2085 ( .A0(n1631), .A1(Sgf_operation_EVEN1_Q_left[15]), .B0(n1630), .Y(n1632) );
AOI22X1TS U2086 ( .A0(n1386), .A1(n1698), .B0(n1632), .B1(n1648), .Y(n277)
);
XOR2XLTS U2087 ( .A(n1633), .B(DP_OP_110J126_122_4535_n516), .Y(n1634) );
AOI22X1TS U2088 ( .A0(n1657), .A1(n1700), .B0(n1636), .B1(n1648), .Y(n275)
);
CMPR32X2TS U2089 ( .A(DP_OP_110J126_122_4535_n518), .B(n1638), .C(n1637),
.CO(n1402), .S(n1639) );
AOI22X1TS U2090 ( .A0(n1386), .A1(n1701), .B0(n1639), .B1(n1656), .Y(n273)
);
CMPR32X2TS U2091 ( .A(DP_OP_110J126_122_4535_n520), .B(n1641), .C(n1640),
.CO(n1398), .S(n1642) );
AOI22X1TS U2092 ( .A0(n1493), .A1(n1702), .B0(n1642), .B1(n1648), .Y(n271)
);
CMPR32X2TS U2093 ( .A(DP_OP_110J126_122_4535_n522), .B(n1644), .C(n1643),
.CO(n1394), .S(n1645) );
AOI22X1TS U2094 ( .A0(n1657), .A1(n1703), .B0(n1645), .B1(n1656), .Y(n269)
);
CMPR32X2TS U2095 ( .A(DP_OP_110J126_122_4535_n524), .B(n1647), .C(n1646),
.CO(n1391), .S(n1649) );
AOI22X1TS U2096 ( .A0(n1386), .A1(n1704), .B0(n1649), .B1(n1648), .Y(n267)
);
AOI21X1TS U2097 ( .A0(n1652), .A1(n1651), .B0(n1650), .Y(n1654) );
XNOR2X1TS U2098 ( .A(n1654), .B(n1653), .Y(n1655) );
AOI22X1TS U2099 ( .A0(n1493), .A1(n1705), .B0(n1655), .B1(n1656), .Y(n265)
);
AOI22X1TS U2100 ( .A0(n1657), .A1(n1709), .B0(DP_OP_110J126_122_4535_n236),
.B1(n1656), .Y(n240) );
OA22X1TS U2101 ( .A0(n1660), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1658), .Y(n177) );
CLKBUFX2TS U2102 ( .A(n1658), .Y(n1659) );
OA22X1TS U2103 ( .A0(n1660), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1659), .Y(n176) );
OA22X1TS U2104 ( .A0(n1660), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1659), .Y(n175) );
OA22X1TS U2105 ( .A0(n1660), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1659), .Y(n174) );
OA22X1TS U2106 ( .A0(n1660), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1659), .Y(n173) );
OA22X1TS U2107 ( .A0(n1660), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1659), .Y(n172) );
OA22X1TS U2108 ( .A0(n1660), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1659), .Y(n171) );
OA22X1TS U2109 ( .A0(n1660), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1659), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_noclk.tcl_KOA_1STAGE_syn.sdf");
endmodule
|
/*
* This is a post-synthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire QE, QN, QGT, QGE;
cmpN ucmp(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]),
.\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]),
.QE(QE), .QN(QN), .QGT(QGT), .QGE(QGE));
int adx;
int bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
A <= adx[WID-1:0];
B <= bdx[WID-1:0];
#1 ;
if (QE !== (adx[WID-1:0]==bdx[WID-1:0])) begin
$display("FAILED -- A=%b, B=%b, QE=%b", A, B, QE);
$finish;
end
if (QN !== (adx[WID-1:0]!=bdx[WID-1:0])) begin
$display("FAILED -- A=%b, B=%b, QN=%b", A, B, QN);
$finish;
end
if (QGT !== (adx[WID-1:0] > bdx[WID-1:0])) begin
$display("FAILED -- A=%b, B=%b, QGT=%b", A, B, QGT);
$finish;
end
if (QGE !== (adx[WID-1:0] >= bdx[WID-1:0])) begin
$display("FAILED -- A=%b, B=%b, QGE=%b", A, B, QGE);
$finish;
end
end
end
$display("PASSED");
end
endmodule // main
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
module altera_up_video_dma_to_stream (
// Inputs
clk,
reset,
stream_ready,
master_readdata,
master_readdatavalid,
master_waitrequest,
reading_first_pixel_in_frame,
reading_last_pixel_in_frame,
// Bidirectional
// Outputs
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_arbiterlock,
master_read,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input stream_ready;
input [MDW:0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input reading_first_pixel_in_frame;
input reading_last_pixel_in_frame;
// Bidirectional
// Outputs
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
output master_arbiterlock;
output master_read;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam STATE_0_IDLE = 2'h0,
STATE_1_WAIT_FOR_LAST_PIXEL = 2'h1,
STATE_2_READ_BUFFER = 2'h2,
STATE_3_MAX_PENDING_READS_STALL = 2'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW+2):0] fifo_data_in;
wire fifo_read;
wire fifo_write;
wire [(DW+2):0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_almost_empty;
wire fifo_almost_full;
// Internal Registers
reg [ 3: 0] pending_reads;
reg startofpacket;
// State Machine Registers
reg [ 1: 0] s_dma_to_stream;
reg [ 1: 0] ns_dma_to_stream;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_dma_to_stream <= STATE_0_IDLE;
else
s_dma_to_stream <= ns_dma_to_stream;
end
always @(*)
begin
case (s_dma_to_stream)
STATE_0_IDLE:
begin
if (fifo_almost_empty)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else
ns_dma_to_stream = STATE_0_IDLE;
end
STATE_1_WAIT_FOR_LAST_PIXEL:
begin
if (pending_reads == 4'h0)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
end
STATE_2_READ_BUFFER:
begin
if (~master_waitrequest)
begin
if (reading_last_pixel_in_frame)
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else if (pending_reads >= 4'hC)
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
STATE_3_MAX_PENDING_READS_STALL:
begin
if (pending_reads <= 4'h7)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
end
default:
begin
ns_dma_to_stream = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
pending_reads <= 4'h0;
else if (master_read & ~master_waitrequest)
begin
if (~master_readdatavalid)
pending_reads <= pending_reads + 1'h1;
end
else if (master_readdatavalid & (pending_reads != 4'h0))
pending_reads <= pending_reads - 1'h1;
end
always @(posedge clk)
begin
if (reset)
startofpacket <= 1'b0;
else if ((s_dma_to_stream == STATE_0_IDLE) & (reading_first_pixel_in_frame))
startofpacket <= 1'b1;
else if (master_readdatavalid)
startofpacket <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_data = fifo_data_out[DW:0];
assign stream_startofpacket = fifo_data_out[DW+1];
assign stream_endofpacket = fifo_data_out[DW+2];
assign stream_empty = 'h0;
assign stream_valid = ~fifo_empty;
assign master_arbiterlock = !((s_dma_to_stream == STATE_2_READ_BUFFER) |
(s_dma_to_stream == STATE_3_MAX_PENDING_READS_STALL));
assign master_read = (s_dma_to_stream == STATE_2_READ_BUFFER);
assign inc_address = master_read & ~master_waitrequest;
assign reset_address = inc_address & reading_last_pixel_in_frame;
// Internal Assignments
assign fifo_data_in[DW:0] = master_readdata[DW:0];
assign fifo_data_in[DW+1] = startofpacket;
assign fifo_data_in[DW+2] = (s_dma_to_stream == STATE_1_WAIT_FOR_LAST_PIXEL) &
(pending_reads == 4'h1);
assign fifo_write = master_readdatavalid & ~fifo_full;
assign fifo_read = stream_ready & stream_valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Image_Buffer (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_empty (fifo_almost_empty),
.almost_full (fifo_almost_full),
// synopsys translate_off
.aclr (),
.usedw ()
// synopsys translate_on
);
defparam
Image_Buffer.add_ram_output_register = "OFF",
Image_Buffer.almost_empty_value = 32,
Image_Buffer.almost_full_value = 96,
Image_Buffer.intended_device_family = "Cyclone II",
Image_Buffer.lpm_numwords = 128,
Image_Buffer.lpm_showahead = "ON",
Image_Buffer.lpm_type = "scfifo",
Image_Buffer.lpm_width = DW + 3,
Image_Buffer.lpm_widthu = 7,
Image_Buffer.overflow_checking = "OFF",
Image_Buffer.underflow_checking = "OFF",
Image_Buffer.use_eab = "ON";
endmodule
|
`timescale 1ns / 100ps
module uartlib(
input UART_CLK, output reg UART_TX
);
integer counter;
initial
UART_TX = 1;
task write_byte;
input [7:0] data;
begin
//start bit
$display("write_byte: 0x%x (0b%b) [%c]", data, data, data);
repeat(2) @(posedge UART_CLK) UART_TX <= 1;
@(posedge UART_CLK) UART_TX <= 0;
//data
@(posedge UART_CLK) UART_TX <= data[0];
@(posedge UART_CLK) UART_TX <= data[1];
@(posedge UART_CLK) UART_TX <= data[2];
@(posedge UART_CLK) UART_TX <= data[3];
@(posedge UART_CLK) UART_TX <= data[4];
@(posedge UART_CLK) UART_TX <= data[5];
@(posedge UART_CLK) UART_TX <= data[6];
@(posedge UART_CLK) UART_TX <= data[7];
//stop bit
@(posedge UART_CLK) UART_TX <= 1;
repeat(2) @(posedge UART_CLK);
end
endtask
task write;
input [31:0] addr;
input [31:0] size;
begin
repeat (40) @(posedge UART_CLK);
write_byte(8'h61); // 0x61 = a
write_byte(addr[7:0]);
write_byte(addr[15:8]);
write_byte(addr[23:16]);
write_byte(addr[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h6c); // 0x6c = l
write_byte(size[7:0]);
write_byte(size[15:8]);
write_byte(size[23:16]);
write_byte(size[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h77); //0x77 = w
repeat(40) @(posedge UART_CLK) ;
end
endtask
task read;
input [31:0] addr;
input [31:0] size;
begin
repeat (40) @(posedge UART_CLK);
write_byte(8'h61); // 0x61 = a
write_byte(addr[7:0]);
write_byte(addr[15:8]);
write_byte(addr[23:16]);
write_byte(addr[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h6c); // 0x6c = l
write_byte(size[7:0]);
write_byte(size[15:8]);
write_byte(size[23:16]);
write_byte(size[31:24]);
repeat(40) @(posedge UART_CLK) ;//wait for receiving OK
write_byte(8'h72); // 0x72 = r
repeat(40) @(posedge UART_CLK) ;
end
endtask
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Thu May 28 19:32:19 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Geometry/Scale/HDL/Scale.srcs/sources_1/ip/Multiplier12x24SCL/Multiplier12x24SCL_funcsim.v
// Design : Multiplier12x24SCL
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x24SCL,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x24SCL,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=24,C_B_TYPE=1,C_OUT_HIGH=35,C_OUT_LOW=17,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x24SCL
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [23:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [18:0]P;
wire [11:0]A;
wire [23:0]B;
wire CLK;
wire [18:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "24" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "35" *)
(* C_OUT_LOW = "17" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x24SCL_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "24" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "35" *) (* C_OUT_LOW = "17" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x24SCL_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [23:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [18:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [23:0]B;
wire CE;
wire CLK;
wire [18:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "24" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "35" *)
(* C_OUT_LOW = "17" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x24SCL_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8768)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module EXMEM_Reg (
input clk,
input flush,
input stall,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] ALU_output_i,
output [32-1:0] ALU_output_o,
input [32-1:0] ALU_data_2_i,
output [32-1:0] ALU_data_2_o,
input [5-1:0] RegFwd_i,
output [5-1:0] RegFwd_o
);
Latch #(.width(2)) EXMEM_MEM_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (MEM_ctrl_i),
.data_o (MEM_ctrl_o)
);
Latch #(.width(2)) EXMEM_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch EXMEM_ALU_output (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (ALU_output_i),
.data_o (ALU_output_o)
);
Latch EXMEM_ALU_data_2 (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (ALU_data_2_i),
.data_o (ALU_data_2_o)
);
Latch #(.width(5)) EXMEM_RegFwd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (RegFwd_i),
.data_o (RegFwd_o)
);
endmodule
|
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 32-bit"
// VERSION "Version 12.0 Build 263 08/02/2012 Service Pack 2.16 SJ Full Version"
// CREATED "Thu Feb 07 14:48:08 2013"
/*
Warning (275043): Pin "ADC_clk" is missing source
Warning (275043): Pin "UI_GPIO1" is missing source
Warning (275043): Pin "ADC_pdwn" is missing source
Warning (275043): Pin "RAM_addr[12..0]" is missing source
Warning (275009): Pin "CPS_dataout" not connected
Warning (275009): Pin "LVDS2LCDS_sdo" not connected
Warning (275009): Pin "ADC_dco" not connected
Warning (275009): Pin "Ethernet_rx_clk" not connected
Warning (275009): Pin "Ethernet_rx_dv" not connected
Warning (275009): Pin "Ethernet_int_n" not connected
Warning (275009): Pin "SD_miso" not connected
Warning (275009): Pin "SD_cd" not connected
Warning (275009): Pin "clk40_2" not connected
Warning (275009): Pin "Ethernet_rxd" not connected
*/
module dtb
(
// --- EPCS
output EPCS_DCLK,
output EPCS_nCSO,
output EPCS_ASDO,
input EPCS_DATA0,
// --- clock
input clk50,
input clk50_2,
input CPS_dataout,
input LVDS2LCDS_tout,
input LVDS2LCDS_sdata_I,
input LVDS2LCDS_sdo,
input ADC_dco,
input ADC_or,
input USB_clk,
input USB_rxf_n,
input USB_txe_n,
input Ethernet_rx_clk,
input Ethernet_rx_dv,
input Ethernet_int_n,
input SD_miso,
input SD_cd,
input UI_clk,
input LVDS2LCDS_sdata_II,
input LVDS2LCDS_sdata_III,
input LVDS2LCDS_sdata_IV,
input CRC_error_in,
input UI_GPIO0,
input [11:0] ADC_data,
input [3:0] Ethernet_rxd,
input [1:0] Switches,
output ADC_clk,
output SD_clk,
output SD_cs,
output SD_mosi,
output RAM_cke,
output RAM_cs_n,
output RAM_ras_n,
output RAM_cas_n,
output RAM_we_n,
output RAM_odt,
output Ethernet_tx_en,
output Ethernet_mdc,
output Ethernet_gtx_clk,
output Ethernet_reset_n,
output UI_GPIO1,
output USB_rd_n,
output USB_wr_n,
output USB_siwua,
output USB_oe_n,
output LVDS2LCDS_reset_n,
output LVDS2LCDS_scl,
output LVDS2LCDS_sdi,
output LVDS2LCDS_sld,
output CPS_clk,
output CPS_ce_n,
output CPS_datain,
output CPS_reset_n,
output CPS_update_n,
output ADC_pdwn,
output LVDS2LCDS_clk,
output LVDS2LCDS_ctr,
output LVDS2LCDS_sda,
output LVDS2LCDS_tin,
output Power_run,
output Chip_HV,
output Chip_reset_n,
output Chip_term,
inout Plug_scl2,
inout Plug_sda2,
inout RAM_clk,
inout RAM_clk_n,
inout Ethernet_mdio,
inout UI_GPIO2,
inout Power_scl,
inout Power_sda,
output [3:0] Chip_addr,
output [3:0] Ethernet_txd,
output [3:0] LEDs,
output [7:0] Plug_IOs,
output [12:0] RAM_addr,
output [1:0] RAM_ba,
output [3:0] RAM_dm,
inout [31:0] RAM_dq,
inout [3:0] RAM_dqs,
inout [15:0] UI_IOs,
inout [7:0] USB_data
);
wire clk_daq;
wire clk_good;
wire clk_present;
wire clk_select_ext;
wire clk_sys;
reg clkena;
wire [2:0] daq_addr;
wire daq_read;
wire [31:0] daq_readdata;
wire daq_write;
wire [31:0] daq_writedata;
wire [1:0] LEDs_ALTERA_SYNTHESIZED;
wire res;
wire res_n;
wire [7:0] sclk;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire [3:0] SYNTHESIZED_WIRE_7;
wire [4:0] SYNTHESIZED_WIRE_11;
assign SD_clk = 0;
assign SD_cs = 0;
assign SD_mosi = 0;
assign Ethernet_tx_en = 0;
assign Ethernet_mdc = 0;
assign Ethernet_gtx_clk = 0;
assign Ethernet_reset_n = 0;
assign Ethernet_txd = 4'b0000;
assign Power_run = SYNTHESIZED_WIRE_11[1];
assign Chip_HV = SYNTHESIZED_WIRE_11[2];
assign Chip_reset_n = SYNTHESIZED_WIRE_11[3];
assign Chip_term = SYNTHESIZED_WIRE_11[4];
assign SYNTHESIZED_WIRE_6 = 1;
wire [2:0] GDFX_TEMP_SIGNAL_0;
assign GDFX_TEMP_SIGNAL_0 = {CRC_error_in,clk_good,clk_present};
dtb_system b2v_inst(
.clkin_50(clk_sys),
.reset_n(res_n),
.epcs_data0(EPCS_DATA0),
.clk_clk(clk_daq),
.usb_usb_clk(SYNTHESIZED_WIRE_0),
.usb_usb_txe_n(USB_txe_n),
.usb_usb_rxf_n(USB_rxf_n),
.pg_clkena(clkena),
.pg_trigger(SYNTHESIZED_WIRE_1),
.sig_clk_sclk(sclk[0]),
.sig_clk_sig_in(SYNTHESIZED_WIRE_2),
.sig_sda_sclk(sclk[0]),
.sig_sda_sig_in(SYNTHESIZED_WIRE_3),
.sig_ctr_sclk(sclk[0]),
.sig_ctr_sig_in(SYNTHESIZED_WIRE_4),
.sig_tin_sclk(sclk[0]),
.sig_tin_sig_in(SYNTHESIZED_WIRE_5),
.mem_clk_to_and_from_the_sdram(RAM_clk),
.mem_clk_n_to_and_from_the_sdram(RAM_clk_n),
.i2c_pwr_sda(Power_sda),
.i2c_pwr_scl(Power_scl),
.i2c_hs_readdata(daq_readdata),
.in_port_to_the_button_pio(Switches),
.mem_dq_to_and_from_the_sdram(RAM_dq),
.mem_dqs_to_and_from_the_sdram(RAM_dqs),
.status_export(GDFX_TEMP_SIGNAL_0),
.usb_usb_data(USB_data),
.mem_odt_from_the_sdram(RAM_odt),
.mem_cs_n_from_the_sdram(RAM_cs_n),
.mem_cke_from_the_sdram(RAM_cke),
.mem_ras_n_from_the_sdram(RAM_ras_n),
.mem_cas_n_from_the_sdram(RAM_cas_n),
.mem_we_n_from_the_sdram(RAM_we_n),
.epcs_dclk(EPCS_DCLK),
.epcs_sce(EPCS_nCSO),
.epcs_sdo(EPCS_ASDO),
.usb_usb_siwu_n(USB_siwua),
.usb_usb_oe_n(USB_oe_n),
.usb_usb_wr_n(USB_wr_n),
.usb_usb_rd_n(USB_rd_n),
.lvds2lcds_reset_n(LVDS2LCDS_reset_n),
.lvds2lcds_scl(LVDS2LCDS_scl),
.lvds2lcds_sdi(LVDS2LCDS_sdi),
.lvds2lcds_sld(LVDS2LCDS_sld),
.adv3224_reset_n(CPS_reset_n),
.adv3224_ce_n(CPS_ce_n),
.adv3224_update_n(CPS_update_n),
.adv3224_clk(CPS_clk),
.adv3224_datain(CPS_datain),
.i2c_hs_read(daq_read),
.i2c_hs_write(daq_write),
.sig_clk_sig_out(LVDS2LCDS_clk),
.sig_sda_sig_out(LVDS2LCDS_sda),
.sig_ctr_sig_out(LVDS2LCDS_ctr),
.sig_tin_sig_out(LVDS2LCDS_tin),
.control_export(SYNTHESIZED_WIRE_11),
.i2c_hs_addr(daq_addr),
.i2c_hs_writedata(daq_writedata),
.mem_ba_from_the_sdram(RAM_ba),
.mem_dm_from_the_sdram(RAM_dm),
.out_port_from_the_led_pio(LEDs),
.pg_pgout(SYNTHESIZED_WIRE_7),
.roc_id_export(Chip_addr)
);
always@(posedge clk_daq)
begin
clkena <= clkena ^ SYNTHESIZED_WIRE_6;
end
FED b2v_inst3(
.clk(clk_daq),
.res(res),
.LVDS2LCDS_sdata_I(LVDS2LCDS_sdata_I),
.LVDS2LCDS_sdata_II(LVDS2LCDS_sdata_II),
.LVDS2LCDS_sdata_III(LVDS2LCDS_sdata_III),
.LVDS2LCDS_sdata_IV(LVDS2LCDS_sdata_IV),
.ADC_or(ADC_or),
.clkena(clkena),
.ADC_data(ADC_data),
.sclk(sclk),
.sel(LEDs_ALTERA_SYNTHESIZED),
.dout(Plug_IOs));
FEC b2v_inst5(
.res(res),
.TOUT(LVDS2LCDS_tout),
.trigger(UI_GPIO0),
.write(daq_write),
.read(daq_read),
.clkena(clkena),
.clk_sys(clk_sys),
.clk_daq(clk_daq),
.address(daq_addr),
.pg_data(SYNTHESIZED_WIRE_7),
.sclk(sclk),
.writedata(daq_writedata),
.TIN(SYNTHESIZED_WIRE_5),
.ROC_CLK(SYNTHESIZED_WIRE_2),
.ROC_CTR(SYNTHESIZED_WIRE_4),
.ROC_SDA(SYNTHESIZED_WIRE_3),
.pg_trigger(SYNTHESIZED_WIRE_1),
.readdata(daq_readdata));
global b2v_inst6(
.in(USB_clk),
.out(SYNTHESIZED_WIRE_0));
clocks_no_ethernet b2v_inst7(
.clock_int(clk40),
.clock_ext_select(clk_select_ext),
.clock_ext(UI_clk),
.sysclk(clk_sys),
.reset_n(res_n),
.clk(clk_daq),
.clock_ext_present(clk_present),
.clk_good(clk_good),
.reset(res),
.sclk(sclk));
assign clk_select_ext = SYNTHESIZED_WIRE_11[0];
endmodule
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* This source file was modified by Xiao Bo Zhao for the class 18-447 in
* order to meet the requirements of an ARM processor.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// arm_mem: A dual-ported virtual word-addressed memory with 5 segments.
// Performing any memory operation to a memory address while
// that memory address is being written produces an undefined
// result.
//
// This file is for simulation only and should not be included in synthesis
//
// The number on each interface signal indiactes the port associated with
// each signal. Within each port, the signals are as follows:
//
// addr (input) - The address of the memory access
// data_in (input) - The data for memory writes
// data_out (output) - The data from memory reads
// we (input) - Write enables for each byte within the word:
// we[3] - Write [31:24] of addressed word
// we[2] - Write [23:16] of addressed word
// we[1] - Write [15:8] of addressed word
// we[0] - Write [7:0] of addressed word
// excpt (output) - Access caused an exception
// allow_kernel (input) - Allow access to kernel segments
// kernel (output) - Access touched a kernel segment
//
// In addition, there is also the following signal:
//
// reset (input) - System reset
// clk (input) - System clock for write
//
//
module arm_mem(addr1,data_in1,data_out1,we1,excpt1,allow_kernel1,kernel1,
addr2,data_in2,data_out2,we2,excpt2,allow_kernel2,kernel2,
rst_b,clk);
// Boundaries and lengths of each segment
// Note that '_top' addresses off by one; the actual top is one less
// than the values below.
// '_w' values are word addresses
parameter
// Data segment
data_start = 32'h10000000,
data_words = 'h40000, /* 1 M */
data_length = data_words * 4,
data_top = data_start + data_length,
data_start_w = data_start >> 2,
data_top_w = data_start_w + data_words,
// Text segment
text_start = 32'h00400000,
text_words = 'h10000, /* 256 K */
text_length = text_words * 4,
text_top = text_start + text_length,
text_start_w = text_start >> 2,
text_top_w = text_start_w + text_words,
// Stack segment (grows down)
stack_top = 32'h80000000,
stack_words = 'h10000, /* 256 K */
stack_length = stack_words * 4,
stack_start = stack_top - stack_length,
stack_start_w = stack_start >> 2,
stack_top_w = stack_start_w + stack_words,
// Kernel data segment
kdata_start = 32'h90000000,
kdata_words = 'h40000, /* 1 M */
kdata_length = kdata_words * 4,
kdata_top = kdata_start + kdata_length,
kdata_start_w = kdata_start >> 2,
kdata_top_w = kdata_start_w + kdata_words,
// Kernel text segment
ktext_start = 32'h80000000,
ktext_words = 'h4000, /* 64 K */
ktext_length = ktext_words * 4,
ktext_top = ktext_start + ktext_length,
ktext_start_w = ktext_start >> 2,
ktext_top_w = ktext_start_w + ktext_words;
input rst_b;
input clk;
// Inputs and ouptuts: Port 1
input [29:0] addr1; // Memory address
input [31:0] data_in1; // Memory write data
output [31:0] data_out1; // Memory read data
reg [31:0] data_out1;
input [0:3] we1; // Write enable (active high; 1 bit per byte)
output excpt1; // Exception occurred (active high)
reg excpt1;
input allow_kernel1; // Is kernel access allowed? (active high)
output kernel1; // Current access is to kernel (active high)
reg kernel1;
// Inputs and outputs: Port 2
input [29:0] addr2; // Memory address
input [31:0] data_in2; // Memory write data
output [31:0] data_out2; // Memory read data
reg [31:0] data_out2;
input [0:3] we2; // Write enable (active high; 1 bit per byte)
output excpt2; // Exception occurred (active high)
reg excpt2;
input allow_kernel2; // Is kernel access allowed? (active high)
output kernel2; // Current access is to kernel (active high)
reg kernel2;
// Memory segments
reg [31:0] data_seg[0:data_words];
reg [31:0] text_seg[0:text_words];
reg [31:0] stack_seg[0:stack_words];
reg [31:0] kdata_seg[0:kdata_words];
reg [31:0] ktext_seg[0:ktext_words];
// Write events
// These events occur after the memory has been written in order
// to update the read ports, if they happen to be looking at the
// same location in memory.
event port_write1, port_write2;
// Verilog implementation stuff
integer i;
wire [31:0] write_mask1 = {we1[3], we1[3], we1[3], we1[3],
we1[3], we1[3], we1[3], we1[3],
we1[2], we1[2], we1[2], we1[2],
we1[2], we1[2], we1[2], we1[2],
we1[1], we1[1], we1[1], we1[1],
we1[1], we1[1], we1[1], we1[1],
we1[0], we1[0], we1[0], we1[0],
we1[0], we1[0], we1[0], we1[0]};
wire [31:0] write_mask2 = {we2[3], we2[3], we2[3], we2[3],
we2[3], we2[3], we2[3], we2[3],
we2[2], we2[2], we2[2], we2[2],
we2[2], we2[2], we2[2], we2[2],
we2[1], we2[1], we2[1], we2[1],
we2[1], we2[1], we2[1], we2[1],
we2[0], we2[0], we2[0], we2[0],
we2[0], we2[0], we2[0], we2[0]};
initial
begin
// Initialize Port 1
data_out1 = 32'hxxxxxxxx;
excpt1 = 1'b0;
kernel1 = 1'b0;
// Initialize Port 2
data_out2 = 32'hxxxxxxxx;
excpt2 = 1'b0;
kernel2 = 1'b0;
end
always@(rst_b)
if(rst_b == 1'b0)
begin
// Initialize Port 1
data_out1 = 32'hxxxxxxxx;
excpt1 = 1'b0;
kernel1 = 1'b0;
// Initialize Port 2
data_out2 = 32'hxxxxxxxx;
excpt2 = 1'b0;
kernel2 = 1'b0;
// Initialize memory (prevents x-pessimism problem)
for(i = 0; i < text_words; i = i + 1)
text_seg[i] = 32'hdeadbeef;
for(i = 0; i < data_words; i = i + 1)
data_seg[i] = 32'hdeadbeef;
for(i = 0; i < stack_words; i = i + 1)
stack_seg[i] = 32'hdeadbeef;
for(i = 0; i < ktext_words; i = i + 1)
ktext_seg[i] = 32'hdeadbeef;
for(i = 0; i < kdata_words; i = i + 1)
kdata_seg[i] = 32'hdeadbeef;
// Grab initial memory values
$readmemh("mem.text.dat", text_seg);
$readmemh("mem.data.dat", data_seg);
$readmemh("mem.stack.dat", stack_seg);
$readmemh("mem.ktext.dat", ktext_seg);
$readmemh("mem.kdata.dat", kdata_seg);
end
// Handle Port 1 Read
always @(rst_b or addr1 or data_in1 or write_mask1 or
port_write1 or port_write2)
begin
if((write_mask1 != 32'b0) && (rst_b == 1'b1))
// We need to write to memory
begin
data_out1 <= 32'hxxxxxxxx;
// Figure out which segment
if((addr1 >= text_start_w) && (addr1 < text_top_w))
begin
excpt1 <= 1'b0;
kernel1 <= 1'b0;
end
else if((addr1 >= data_start_w) && (addr1 < data_top_w))
begin
excpt1 <= 1'b0;
kernel1 <= 1'b0;
end
else if((addr1 >= stack_start_w) && (addr1 < stack_top_w))
begin
excpt1 <= 1'b0;
kernel1 <= 1'b0;
end
else if((addr1 >= ktext_start_w) && (addr1 < ktext_top_w))
begin
kernel1 <= 1'b1;
if(allow_kernel1 == 1'b1)
begin
excpt1 <= 1'b0;
end
else
begin
excpt1 <= 1'b1;
end
end
else if((addr1 >= kdata_start_w) && (addr1 < kdata_top_w))
begin
kernel1 <= 1'b1;
if(allow_kernel1 == 1'b1)
begin
excpt1 <= 1'b0;
end
else
begin
excpt1 <= 1'b1;
end
end
else
begin
// Not in any segment; raise an exception
kernel1 <= 1'b0;
excpt1 <= 1'b1;
end // else:
end
else
// We need to read from memory
begin
// Figure out which segment
if((addr1 >= text_start_w) && (addr1 < text_top_w))
begin
excpt1 <= 1'b0;
kernel1 <= 1'b0;
data_out1 <= text_seg[addr1 - text_start_w];
end
else if((addr1 >= data_start_w) && (addr1 < data_top_w))
begin
excpt1 <= 1'b0;
kernel1 <= 1'b0;
data_out1 <= data_seg[addr1 - data_start_w];
end
else if((addr1 >= stack_start_w) && (addr1 < stack_top_w))
begin
excpt1 <= 1'b0;
kernel1 <= 1'b0;
data_out1 <= stack_seg[addr1 - stack_start_w];
end
else if((addr1 >= ktext_start_w) && (addr1 < ktext_top_w))
begin
kernel1 <= 1'b1;
if(allow_kernel1 == 1'b1)
begin
excpt1 <= 1'b0;
data_out1 <= ktext_seg[addr1 - ktext_start_w];
end
else
begin
excpt1 <= 1'b1;
data_out1 <= 32'hxxxxxxxx;
end
end
else if((addr1 >= kdata_start_w) && (addr1 < kdata_top_w))
begin
kernel1 <= 1'b1;
if(allow_kernel1 == 1'b1)
begin
excpt1 <= 1'b0;
data_out1 <= kdata_seg[addr1 - kdata_start_w];
end
else
begin
excpt1 <= 1'b1;
data_out1 <= 32'hxxxxxxxx;
end
end
else
begin
// Not in any segment; raise an exception
kernel1 <= 1'b0;
excpt1 <= 1'b1;
end
end
end
// Handle Port 1 Write
always @(posedge clk)
begin
if((write_mask1 != 32'b0) && (rst_b == 1'b1))
// We need to write to memory
begin
data_out1 <= 32'hxxxxxxxx;
// Figure out which segment
if((addr1 >= text_start_w) && (addr1 < text_top_w))
begin
text_seg[addr1 - text_start_w]
<= ( write_mask1 & data_in1) |
(~write_mask1 & text_seg[addr1 - text_start_w]);
end
else if((addr1 >= data_start_w) && (addr1 < data_top_w))
begin
data_seg[addr1 - data_start_w]
<= ( write_mask1 & data_in1) |
(~write_mask1 & data_seg[addr1 - data_start_w]);
end
else if((addr1 >= stack_start_w) && (addr1 < stack_top_w))
begin
stack_seg[addr1 - stack_start_w]
<= ( write_mask1 & data_in1) |
(~write_mask1 & stack_seg[addr1 - stack_start_w]);
end
else if((addr1 >= ktext_start_w) && (addr1 < ktext_top_w))
begin
if(allow_kernel1 == 1'b1)
begin
ktext_seg[addr1 - ktext_start_w]
<= ( write_mask1 & data_in1) |
(~write_mask1 & ktext_seg[addr1 - ktext_start_w]);
end
end
else if((addr1 >= kdata_start_w) && (addr1 < kdata_top_w))
begin
if(allow_kernel1 == 1'b1)
begin
kdata_seg[addr1 - kdata_start_w]
<= ( write_mask1 & data_in1) |
(~write_mask1 & kdata_seg[addr1 - kdata_start_w]);
end
end
#0 ->port_write1;
// invoke the port_write1 event to make sure that
// the read ports are updated.
end // if ((write_mask1 != 32'b0) && (reset == 1'b0))
end // always @ (posedge clk)
// Handle Port 2 Read
always @(rst_b or addr2 or data_in2 or write_mask2 or
port_write1 or port_write2)
begin
if((write_mask2 != 32'b0) && (rst_b == 1'b1))
// We need to write to memory
begin
data_out2 <= 32'hxxxxxxxx;
// Figure out which segment
if((addr2 >= text_start_w) && (addr2 < text_top_w))
begin
excpt2 <= 1'b0;
kernel2 <= 1'b0;
end
else if((addr2 >= data_start_w) && (addr2 < data_top_w))
begin
excpt2 <= 1'b0;
kernel2 <= 1'b0;
end
else if((addr2 >= stack_start_w) && (addr2 < stack_top_w))
begin
excpt2 <= 1'b0;
kernel2 <= 1'b0;
end
else if((addr2 >= ktext_start_w) && (addr2 < ktext_top_w))
begin
kernel2 <= 1'b1;
if(allow_kernel2 == 1'b1)
begin
excpt2 <= 1'b0;
end
else
begin
excpt2 <= 1'b1;
end
end
else if((addr2 >= kdata_start_w) && (addr2 < kdata_top_w))
begin
kernel2 <= 1'b1;
if(allow_kernel2 == 1'b1)
begin
excpt2 <= 1'b0;
end
else
begin
excpt2 <= 1'b1;
end
end
else
begin
// Not in any segment; raise an exception
kernel2 <= 1'b0;
excpt2 <= 1'b1;
end // else: !if((addr2 >= kdata_start_w) && (addr2 < kdata_top_w))
end
else
// We need to read from memory
begin
// Figure out which segment
if((addr2 >= text_start_w) && (addr2 < text_top_w))
begin
excpt2 <= 1'b0;
kernel2 <= 1'b0;
data_out2 <= text_seg[addr2 - text_start_w];
end
else if((addr2 >= data_start_w) && (addr2 < data_top_w))
begin
excpt2 <= 1'b0;
kernel2 <= 1'b0;
data_out2 <= data_seg[addr2 - data_start_w];
end
else if((addr2 >= stack_start_w) && (addr2 < stack_top_w))
begin
excpt2 <= 1'b0;
kernel2 <= 1'b0;
data_out2 <= stack_seg[addr2 - stack_start_w];
end
else if((addr2 >= ktext_start_w) && (addr2 < ktext_top_w))
begin
kernel2 <= 1'b1;
if(allow_kernel2 == 1'b1)
begin
excpt2 <= 1'b0;
data_out2 <= ktext_seg[addr2 - ktext_start_w];
end
else
begin
excpt2 <= 1'b1;
data_out2 <= 32'hxxxxxxxx;
end
end
else if((addr2 >= kdata_start_w) && (addr2 < kdata_top_w))
begin
kernel2 <= 1'b1;
if(allow_kernel2 == 1'b1)
begin
excpt2 <= 1'b0;
data_out2 <= kdata_seg[addr2 - kdata_start_w];
end
else
begin
excpt2 <= 1'b1;
data_out2 <= 32'hxxxxxxxx;
end
end
else
begin
// Not in any segment; raise an exception
kernel2 <= 1'b0;
excpt2 <= 1'b1;
end
end
end
// Handle Port 2 Write
always @(posedge clk)
begin
if((write_mask2 != 32'b0) && (rst_b == 1'b1))
// We need to write to memory
begin
data_out2 <= 32'hxxxxxxxx;
// Figure out which segment
if((addr2 >= text_start_w) && (addr2 < text_top_w))
begin
text_seg[addr2 - text_start_w]
<= ( write_mask2 & data_in2) |
(~write_mask2 & text_seg[addr2 - text_start_w]);
end
else if((addr2 >= data_start_w) && (addr2 < data_top_w))
begin
data_seg[addr2 - data_start_w]
<= ( write_mask2 & data_in2) |
(~write_mask2 & data_seg[addr2 - data_start_w]);
end
else if((addr2 >= stack_start_w) && (addr2 < stack_top_w))
begin
stack_seg[addr2 - stack_start_w]
<= ( write_mask2 & data_in2) |
(~write_mask2 & stack_seg[addr2 - stack_start_w]);
end
else if((addr2 >= ktext_start_w) && (addr2 < ktext_top_w))
begin
if(allow_kernel2 == 1'b1)
begin
ktext_seg[addr2 - ktext_start_w]
<= ( write_mask2 & data_in2) |
(~write_mask2 & ktext_seg[addr2 - ktext_start_w]);
end
end
else if((addr2 >= kdata_start_w) && (addr2 < kdata_top_w))
begin
if(allow_kernel2 == 1'b1)
begin
kdata_seg[addr2 - kdata_start_w]
<= ( write_mask2 & data_in2) |
(~write_mask2 & kdata_seg[addr2 - kdata_start_w]);
end
end
#0 ->port_write2;
// invoke the port_write2 event to make sure that
// the read ports are updated.
end // if ((write_mask2 != 32'b0) && (reset == 1'b0))
end // always @ (posedge clk)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A22O_PP_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_PP_BLACKBOX_V
|
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.61
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
* - Duty Cycle Corrector is not modeled
* - Temperature Compensated Self Refresh is not modeled
* - DLL off mode is not modeled.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
* TDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* Improved checking of DQS during writes.
* Added true BL4 operation.
* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
* Added ODTS Readout.
* Replaced tZQCL with tZQinit and tZQoper
* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
* Added tRFC checking for Refresh to Power-Down Re-Entry.
* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
* Added Clock Frequency Change during Precharge Power-Down.
* Added -125x speed grades.
* Fixed tRCD checking during Write.
* 1.00 JMK 05/11/07 Initial release
* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
* Removed temp sensor readout from MPR
* Updated initialization sequence
* Updated timing parameters
* 1.20 JMK 09/05/07 Updated clock frequency change
* Added ddr3_dimm module
* 1.30 JMK 01/23/08 Updated timing parameters
* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
* Added multi-chip package model support in ddr3_mcp.v
* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW
*****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
// model flags
// `define MODEL_PASR
//Memory Details
`define x4Gb
`define sg125
`define x8
module ddr3_model (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "ddr3_model_parameters.vh"
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS#
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: mcb_flow_control.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:21 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex 6
//Design Name: DDR2/DDR3
//Purpose: This module is the main flow control between cmd_gen.v,
// write_data_path and read_data_path modules.
//Reference:
//Revision History: 7/29/10 Support V6 Back-to-back commands over user interface.
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_memc_flow_vcontrol #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter NUM_DQ_PINS = 32,
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 4,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3"
)
(
input clk_i,
input [9:0] rst_i,
input [3:0] data_mode_i,
input [5:0] cmds_gap_delay_value,
input mem_pattern_init_done_i,
// interface to cmd_gen, pipeline inserter
output reg cmd_rdy_o,
input cmd_valid_i,
input [2:0] cmd_i,
input [31:0] addr_i,
input [BL_WIDTH - 1:0] bl_i,
// interface to mcb_cmd port
input mcb_cmd_full,
input mcb_wr_full_i,
output reg [2:0] cmd_o,
output [31:0] addr_o,
output reg [BL_WIDTH-1:0] bl_o,
output cmd_en_o, // interface to write data path module
// *** interface to qdr ****
output reg qdr_rd_cmd_o,
// *************************
input mcb_wr_en_i,
input last_word_wr_i,
input wdp_rdy_i,
output reg wdp_valid_o,
output reg wdp_validB_o,
output reg wdp_validC_o,
output [31:0] wr_addr_o,
output [BL_WIDTH-1:0] wr_bl_o,
// interface to read data path module
input rdp_rdy_i,
output reg rdp_valid_o,
output [31:0] rd_addr_o,
output [BL_WIDTH-1:0] rd_bl_o
);
//FSM State Defination
localparam READY = 4'b0001,
READ = 4'b0010,
WRITE = 4'b0100,
CMD_WAIT = 4'b1000;
localparam RD = 3'b001;
localparam RDP = 3'b011;
localparam WR = 3'b000;
localparam WRP = 3'b010;
localparam REFRESH = 3'b100;
localparam NOP = 3'b101;
reg cmd_fifo_rdy;
reg push_cmd;
reg cmd_rdy;
reg [31:0] addr_r;
reg [2:0] cmd_reg;
reg [31:0] addr_reg;
reg [BL_WIDTH-1:0] bl_reg;
reg [BL_WIDTH:0] cmd_counts;
reg rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC;
reg [3:0] current_state;
reg [3:0] next_state;
reg push_cmd_r;
reg cmd_en_r1;
reg wr_in_progress;
reg wrcmd_in_progress;
reg rdcmd_in_progress;
reg [5:0] commands_delay_counters;
reg goahead;
reg cmd_en_r2;
reg cmd_wr_pending_r1;
reg [3:0] addr_INC;
reg COuta;
wire cmd_rd;
wire cmd_wr;
always @ (posedge clk_i) begin
if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6")
addr_INC <= #TCQ 0;
else
addr_INC <= #TCQ MEM_BURST_LEN[3:0];
end
// mcb_command bus outputs
always @(posedge clk_i) begin
if (rst_i[0]) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b1;
end
else if (cmds_gap_delay_value == 5'd0)
goahead <= 1'b1;
else if (wr_in_progress || wrcmd_in_progress ||
rdcmd_in_progress || cmd_rdy_o) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b0;
end
else if (commands_delay_counters == cmds_gap_delay_value) begin
commands_delay_counters <= commands_delay_counters;
goahead <= 1'b1;
end
else
commands_delay_counters <= commands_delay_counters + 1'b1;
end
assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ;
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ cmd_rdy;
always @ (posedge clk_i) begin
if (rst_i[8])
cmd_en_r1 <= #TCQ 1'b0;
else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i))
cmd_en_r1 <= #TCQ 1'b0;
else if ((rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR2PLUS") ||
(mcb_wr_en_i && MEM_TYPE == "QDR2PLUS"))
cmd_en_r1 <= #TCQ 1'b1;
else if (!mcb_cmd_full)
cmd_en_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
if (rst_i[8])
cmd_en_r2 <= #TCQ 1'b0;
else
cmd_en_r2 <= cmd_en_r1;
// QDR read command generation
always @ (posedge clk_i) begin
if (rst_i[8])
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (cmd_counts == 1 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1)
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (rdcmd_in_progress)
qdr_rd_cmd_o <= #TCQ 1'b1;
else if (!mcb_cmd_full)
qdr_rd_cmd_o <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[9])
cmd_fifo_rdy <= #TCQ 1'b1;
else if (cmd_en_r1 || mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b0;
else if (!mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[9]) begin
cmd_o <= #TCQ 'b0;
bl_o <= #TCQ 'b0;
end
else if (push_cmd_r && current_state == READ) begin
cmd_o <= #TCQ cmd_i;
bl_o <= #TCQ bl_i - 'b1;
end
else if (push_cmd_r && current_state == WRITE) begin
if (FAMILY == "SPARTAN6")
cmd_o <= #TCQ cmd_reg;
else
cmd_o <= #TCQ {2'b00,cmd_reg[0]};
bl_o <= #TCQ bl_reg;
end
end
always @ (posedge clk_i)
if ((push_cmd && mem_pattern_init_done_i) | rst_i)
addr_reg <= #TCQ addr_i;
else if (push_cmd && !mem_pattern_init_done_i)
addr_reg <= #TCQ addr_r;
always @ (posedge clk_i) begin
if (push_cmd && cmd_rd || rst_i[0])
addr_r <= #TCQ addr_i;
else if (push_cmd_r && current_state != READ)
addr_r <= #TCQ addr_reg;
else if ((wrcmd_in_progress || rdcmd_in_progress) &&
cmd_en_r1 && ~mcb_cmd_full) begin
if (MEM_TYPE == "QDR2PLUS")
{COuta,addr_r[31:0]} <= addr_o + 1;
else
{COuta,addr_r[31:0]} <= addr_o + addr_INC;
end
end
assign addr_o = addr_r;
assign wr_addr_o = addr_i;
assign rd_addr_o = addr_i;
assign rd_bl_o = bl_i;
assign wr_bl_o = bl_i;
always @ (posedge clk_i) begin
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
end
always @ (posedge clk_i)
rdp_valid_o <= rdp_valid;
always @(posedge clk_i)
push_cmd_r <= #TCQ push_cmd;
always @(posedge clk_i)
if (push_cmd) begin
cmd_reg <= #TCQ cmd_i;
bl_reg <= #TCQ bl_i - 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_counts <= #TCQ 'b0;
else if (push_cmd_r) begin
if (bl_i == 0) begin
if (MEM_BURST_LEN == 8) begin
if (nCK_PER_CLK == 4)
cmd_counts <= #TCQ {2'b01, {BL_WIDTH-1{1'b0}}};
else
cmd_counts <= #TCQ {3'b001, {BL_WIDTH-2{1'b0}}};
end
else
cmd_counts <= {1'b0,{BL_WIDTH{1'b1}}} ;//- 2;//63;
end
else begin
if (MEM_BURST_LEN == 8) begin
if (nCK_PER_CLK == 4)
cmd_counts <= {1'b0,bl_i};
else
cmd_counts <= {3'b000,bl_i[BL_WIDTH-2:1]};
end
else
cmd_counts <= {1'b0,bl_i};//- 1 ;// {1'b0,bl_i[5:1]} -2;
end
end
else if ((wrcmd_in_progress || rdcmd_in_progress) && cmd_en_r1 && ~mcb_cmd_full) begin
if (cmd_counts > 0) begin
if (FAMILY == "VIRTEX6")
cmd_counts <= cmd_counts - 1'b1;
else if (wrcmd_in_progress)
cmd_counts <= cmd_counts - 1'b1;
else
cmd_counts <= 0;
end
end
end
//--Command Decodes--
assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
always @ (posedge clk_i) begin
if (rst_i[0])
cmd_wr_pending_r1 <= #TCQ 1'b0;
else if (last_word_wr_i)
cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd & cmd_wr)
cmd_wr_pending_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[0])
wr_in_progress <= #TCQ 1'b0;
else if (last_word_wr_i)
wr_in_progress <= #TCQ 1'b0;
else if (push_cmd && cmd_wr)
wr_in_progress <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
wrcmd_in_progress <= #TCQ 1'b0;
else if (cmd_wr && push_cmd_r)
wrcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts == 0 || (cmd_counts == 1 && ~mcb_cmd_full))
wrcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[0])
rdcmd_in_progress <= #TCQ 1'b0;
else if (cmd_rd && push_cmd_r)
rdcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts <= 1)
rdcmd_in_progress <= #TCQ 1'b0;
end
// mcb_flow_control statemachine
always @ (posedge clk_i)
if (rst_i[0])
current_state <= #TCQ 5'b00001;
else
current_state <= #TCQ next_state;
always @ (*) begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
cmd_rdy = 1'b0;
next_state = current_state;
case(current_state) // next state logic
READY: begin // 5'h01
if (rdp_rdy_i && cmd_rd && ~mcb_cmd_full) begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
cmd_rdy = 1'b1;
end
else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full) begin
next_state = WRITE;
push_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
cmd_rdy = 1'b1;
end
else begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
end
end // READY
READ: begin // 5'h02
if (rdcmd_in_progress) begin
next_state = READ;
push_cmd = 1'b0;
rdp_valid = 1'b0;
wdp_valid = 1'b0;
end
else if (!rdp_rdy_i) begin
next_state = READ;
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead) begin
next_state = CMD_WAIT;
end
else if (goahead && ~push_cmd_r) begin
next_state = READY;
cmd_rdy = 1'b0;
end
else
next_state = READ;
end // READ
WRITE: begin // 5'h04
if (wr_in_progress || wrcmd_in_progress || push_cmd_r) begin
next_state = WRITE;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
push_cmd = 1'b0;
end
else if (!cmd_fifo_rdy && last_word_wr_i && goahead) begin
next_state = CMD_WAIT;
push_cmd = 1'b0;
end
else if (goahead) begin
next_state = READY;
end
else
next_state = WRITE;
cmd_rdy = 1'b0;
end // WRITE
CMD_WAIT: begin // 5'h08
if (!cmd_fifo_rdy || wr_in_progress) begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
end
else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd) begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
rdp_valid = 1'b0;
end
else if (cmd_fifo_rdy && cmd_wr && goahead &&
cmd_wr_pending_r1) begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
end
else begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
end
end // CMD_WAIT
default: begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
next_state = READY;
end
endcase
end
endmodule
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming encoder
*/
module ham_15_11_encoder (d,c);
// Output signals representing the 15-bit encoded vector
output reg [14:0] c;
// Input signals representing the 11-bit input
input [10:0] d;
// Declare "reg" signals...
// Parity bits for Hamming encoding
reg [3:0] p;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
// Determine for each parity bit, what data bits is it made of
//p[0]=((d[0]^d[1])^(d[3]^d[4]))^((d[6]^d[8])^d[10]);
p[0]=d[0]^d[1]^d[3]^d[4]^d[6]^d[8]^d[10];
// assign p[0]=d[0];
//p{0}=d{0};
//p(0)=d(0);
p[1]=((d[0]^d[2])^(d[3]^d[5]))^((d[6]^d[9])^d[10]);
p[2]=((d[1]^d[2])^(d[3]^d[7]))^((d[8]^d[9])^d[10]);
p[3]=((d[4]^d[5])^(d[6]^d[7]))^((d[8]^d[9])^d[10]);
// Assign the encoded signal bits to data bits...
c[2]=d[0];
c[4]=d[1];
c[5]=d[2];
c[6]=d[3];
c[8]=d[4];
c[9]=d[5];
c[10]=d[6];
c[11]=d[7];
c[12]=d[8];
c[13]=d[9];
c[14]=d[10];
// Introduce parity bits to encode signal values
c[0]=p[0];
c[1]=p[1];
c[3]=p[2];
c[7]=p[3];
end
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
//==================================================================================================
// Filename : musb_ifid_register.v
// Created On : 2014-09-27 20:34:54
// Last Modified : 2015-05-31 13:04:30
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : aterrones@usb.ve
//
// Description : Pipeline register: IF -> ID
//==================================================================================================
module musb_ifid_register(
input clk, // main clock
input rst, // main reset
input [31:0] if_instruction, // Instruction from IF
input [31:0] if_pc_add4, // PC + 1 from IF
input [31:0] if_pc, // PC from IF
input if_is_bds, // This instruction is a BDS.
input if_flush, // clean
input if_stall, // Stall IF
input id_stall, // Stall ID
output reg [31:0] id_instruction, // ID instruction
output reg [31:0] id_pc_add4, // PC + 1 to ID
output reg [31:0] id_exception_pc, // PC to ID
output reg id_is_bds, // Instruction is a BDS
output reg id_is_flushed // This instruction must be ignored
);
always @(posedge clk) begin
id_instruction <= (rst) ? 32'b0 : ((id_stall) ? id_instruction : ((if_stall | if_flush) ? 32'b0 : if_instruction));
id_pc_add4 <= (rst) ? 32'b0 : ((id_stall) ? id_pc_add4 : if_pc_add4); // check this for if_stall
id_exception_pc <= (rst) ? 32'b0 : ((id_stall) ? id_exception_pc : if_pc); // check this for if_stall
id_is_bds <= (rst) ? 1'b0 : ((id_stall) ? id_is_bds : if_is_bds);
id_is_flushed <= (rst) ? 1'b0 : ((id_stall) ? id_is_flushed : if_flush);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:14 04/19/2014
// Design Name:
// Module Name: Image_viewer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Image_viewer_top(ClkPort,
Hsync, Vsync, vgaRed, vgaGreen, vgaBlue,
MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE,
MemAdr, data,
An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp, Led,
btnC, btnR, btnL, btnU, btnD
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input ClkPort;
output MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE;
output [26:1] MemAdr;
inout [15:0] data;
//Button
input btnC, btnR, btnL, btnU, btnD;
//Light/Display
output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
output Vsync, Hsync;
output [2:0] vgaRed;
output [2:0] vgaGreen;
output [2:1] vgaBlue;
output [1:0] Led;
reg [2:0] _vgaRed;
reg [2:0] _vgaGreen;
reg [1:0] _vgaBlue;
wire inDisplayArea;
wire [9:0] CounterX;
wire [9:0] CounterY;
reg [5:0] bitCounter;
assign vgaRed = _vgaRed;
assign vgaGreen = _vgaGreen;
assign vgaBlue = _vgaBlue;
assign Led = readImage;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
//Global Stuff
wire ClkPort, sys_clk, Reset;
reg [26:0] DIV_CLK;
assign sys_clk = ClkPort;
assign MemClk = DIV_CLK[0];
//Memory Stuff
reg [22:0] address;
reg [15:0] dataRegister[0:127];
reg [22:0] imageRegister[0:3];
always@(posedge sys_clk)
begin
imageRegister[2'b00][22:0] <= 23'b00000000000000000000000;
imageRegister[2'b01][22:0] <= 23'b00000000000000010000000;
imageRegister[2'b10][22:0] <= 23'b00000000000000100000000;
imageRegister[2'b11][22:0] <= 23'b00000000000000110000000;
end
wire [7:0] uByte;
wire [7:0] lByte;
reg [1:0] readImage;
reg [6:0] readAddress;
reg [6:0] writePointer;
reg [6:0] readRow;
assign uByte = data[15:8];
assign lByte = data[7:0];
//Button Stuff
wire BtnR_Pulse, BtnL_Pulse, BtnU_Pulse, BtnD_Pulse;
assign Reset = btnC;
//-------------------------------------------------------------------//
always @ (posedge sys_clk, posedge Reset)
begin : CLOCK_DIVIDER
if (Reset)
DIV_CLK <= 0;
else
DIV_CLK <= DIV_CLK + 1;
end
//--------------------Debounce Controllers--------------------//
ee201_debouncer #(.N_dc(20)) ee201_debouncer_left
(.CLK(MemClk), .RESET(Reset), .PB(btnL), .DPB( ),
.SCEN(BtnL_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_right
(.CLK(MemClk), .RESET(Reset), .PB(btnR), .DPB( ),
.SCEN(BtnR_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_up
(.CLK(MemClk), .RESET(Reset), .PB(btnU), .DPB( ),
.SCEN(BtnU_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_down
(.CLK(MemClk), .RESET(Reset), .PB(btnD), .DPB( ),
.SCEN(BtnD_Pulse), .MCEN( ), .CCEN( ));
//--------------------Display Controller--------------------//
DisplayCtrl display (.Clk(DIV_CLK), .reset(Reset), .memoryData(dataRegister[readRow][15:0]),
.An0(An0), .An1(An1), .An2(An2), .An3(An3),
.Ca(Ca), .Cb(Cb), .Cc(Cc), .Cd(Cd), .Ce(Ce), .Cf(Cf), .Cg(Cg), .Dp(Dp)
);
//--------------------Memory Controller--------------------//
MemoryCtrl memory(.Clk(MemClk), .Reset(Reset), .MemAdr(MemAdr), .MemOE(MemOE), .MemWR(MemWR),
.RamCS(RamCS), .RamUB(RamUB), .RamLB(RamLB), .RamAdv(RamAdv), .RamCRE(RamCRE), .writeData(writeData),
.AddressIn(address), .BtnU_Pulse(BtnU_Pulse), .BtnD_Pulse(BtnD_Pulse)
);
//--------------------VGA Controller--------------------//
VGACtrl vga(.clk(DIV_CLK[1]), .reset(Reset), .vga_h_sync(Hsync),
.vga_v_sync(Vsync), .inDisplayArea(inDisplayArea),
.CounterX(CounterX), .CounterY(CounterY)
);
reg toggleByte;
always @(posedge DIV_CLK[1], posedge Reset)
begin
if(Reset)
begin
bitCounter <= 0;
toggleByte <= 0;
readAddress <= 0;
end
else if(CounterY > 192 && CounterY < 288)
begin
if(CounterX == 0)
begin
bitCounter <= 0;
toggleByte <= 1'b0;
end
else if(CounterX > 284 && bitCounter < 35)
begin
if(toggleByte == 1'b0)
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][7:0];
toggleByte <= 1'b1;
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][15:8];
toggleByte <= 1'b0;
bitCounter <= bitCounter + 1;
readAddress <= readAddress + 1;
end
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= 0;
end
end
else if (CounterY == 288)
readAddress <= 0;
end
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readImage <= 0;
else if(BtnU_Pulse)
readImage <= readImage + 1;
else if(BtnD_Pulse)
readImage <= readImage - 1;
else
address <= imageRegister[readImage][22:0];
end
//--------------------Process Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
begin
writePointer <= 0;
end
else
if(writeData == 1'b1)
begin
dataRegister[writePointer][15:0] <= {lByte, uByte};
writePointer <= writePointer + 1;
end
else
writePointer <= 0;
end
//--------------------SSD Display Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readRow <= 0;
else if(BtnR_Pulse)
readRow <= readRow + 1;
else if(BtnL_Pulse)
readRow <= readRow - 1;
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright (C) 2007 Onno Kortmann <onno@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA..
*
*/
/*
Bare simulavrxx AVR<->verilog interface 'testbench' without using any of
the gluecode in avr.v
*/
`timescale 1ns / 1ns
module test;
integer hd;
reg clk;
initial begin
// $display("%h",dfdf);
$dumpfile("baretest.vcd");
$dumpvars(0, test);
hd=8'h01;
#1 hd=8'h02;
#1 hd=8'h03;
hd=$avr_create("at90s4433", "toggle.elf");
$avr_reset(hd);
#100_000 $avr_destroy(hd);
$finish;
end
integer val;
// Pin state LOW is zero
wire pb0=val!=1'b0;
always @(posedge clk) begin
#10 $avr_tick(hd);
#10 val=$avr_get_pin(hd, "B0");
end
always begin
#125 clk<=0; //125000 -> 4MHz clock
#125 clk<=1;
end
endmodule // test
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module doHistStretch_fdiv_32ns_32ns_32_16
#(parameter
ID = 2,
NUM_STAGE = 16,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
doHistStretch_ap_fdiv_14_no_dsp_32 doHistStretch_ap_fdiv_14_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5) (
input clka,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
input clkb,
input reb,
input [(ADDRESS_WIDTH-1):0] addrb,
output reg [(DATA_WIDTH-1):0] doutb);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_prbs_rdlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// PRBS Read leveling calibration logic
// NOTES:
// 1. Window detection with PRBS pattern.
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_prbs_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter RANKS = 1, // # of DRAM ranks
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter PRBS_WIDTH = 8, // PRBS generator output width
parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE"
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON"
)
(
input clk,
input rst,
// Calibration status, control signals
input prbs_rdlvl_start,
(* max_fanout = 100 *) output reg prbs_rdlvl_done,
output reg prbs_last_byte_done,
output reg prbs_rdlvl_prech_req,
input complex_sample_cnt_inc,
input prech_done,
input phy_if_empty,
// Captured data in fabric clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
//Expected data from PRBS generator
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data,
// Decrement initial Phaser_IN Fine tap delay
input [5:0] pi_counter_read_val,
// Stage 1 calibration outputs
output reg pi_en_stg2_f,
output reg pi_stg2_f_incdec,
output [255:0] dbg_prbs_rdlvl,
output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt,
output reg [2:0] rd_victim_sel,
output reg complex_victim_inc,
output reg reset_rd_addr,
output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit
output reg fine_delay_sel, //fine delay selection - actual update of fine delay
output reg num_samples_done_r,
input complex_act_start, //read is done. ready for PI movement
output complex_init_pi_dec_done, //Initial PI incdec is done. ready for start
output reg complex_pi_incdec_done //PI incdec is done. ready for Read
);
localparam [5:0] PRBS_IDLE = 6'h00;
localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01;
localparam [5:0] PRBS_PAT_COMPARE = 6'h02;
localparam [5:0] PRBS_DEC_DQS = 6'h03;
localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04;
localparam [5:0] PRBS_INC_DQS = 6'h05;
localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06;
localparam [5:0] PRBS_CALC_TAPS = 6'h07;
localparam [5:0] PRBS_NEXT_DQS = 6'h08;
localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09;
localparam [5:0] PRBS_DONE = 6'h0A;
localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B;
localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C;
localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center
localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle
localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail
localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle
localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss
localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size
localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt
localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_INC = 6'h14; //wait for read is done before PI inc
localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_DEC = 6'h15; //wait for read is done before PI dec
localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd12 : 12'h001; //MG from 50
localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001;
localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001;
//minimum valid window for centering
localparam MIN_WIN = 8;
localparam [MIN_WIN-1:0] MATCH_ALL_ONE = {MIN_WIN{1'b1}};
localparam [MIN_WIN-1:0] MIN_PASS = {MIN_WIN{1'b0}}; //8'b00000000
localparam [MIN_WIN-1:0] MIN_LEFT = {1'b1,{{MIN_WIN-1}{1'b0}}}; //8'b10000000
wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing;
reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r;
reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r;
reg prbs_prech_req_r;
reg [5:0] prbs_state_r;
reg [5:0] prbs_state_r1;
reg wait_state_cnt_en_r;
reg [3:0] wait_state_cnt_r;
reg cnt_wait_state;
reg err_chk_invalid;
// reg found_edge_r;
reg prbs_found_1st_edge_r;
reg prbs_found_2nd_edge_r;
reg [5:0] prbs_1st_edge_taps_r;
// reg found_stable_eye_r;
reg [5:0] prbs_dqs_tap_cnt_r;
reg [5:0] prbs_dec_tap_calc_plus_3;
reg [5:0] prbs_dec_tap_calc_minus_3;
reg prbs_dqs_tap_limit_r;
reg [5:0] prbs_inc_tap_cnt;
reg [5:0] prbs_dec_tap_cnt;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4;
reg mux_rd_valid_r;
reg rd_valid_r1;
reg rd_valid_r2;
reg rd_valid_r3;
reg new_cnt_dqs_r;
reg prbs_tap_en_r;
reg prbs_tap_inc_r;
reg pi_en_stg2_f_timing;
reg pi_stg2_f_incdec_timing;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
wire [DQ_WIDTH-1:0] compare_data_r0;
wire [DQ_WIDTH-1:0] compare_data_f0;
wire [DQ_WIDTH-1:0] compare_data_r1;
wire [DQ_WIDTH-1:0] compare_data_f1;
wire [DQ_WIDTH-1:0] compare_data_r2;
wire [DQ_WIDTH-1:0] compare_data_f2;
wire [DQ_WIDTH-1:0] compare_data_r3;
wire [DQ_WIDTH-1:0] compare_data_f3;
reg [DRAM_WIDTH-1:0] compare_data_rise0_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall0_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise1_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall1_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise2_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall2_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise3_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall3_r1;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg [5:0] prbs_2nd_edge_taps_r;
// reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
reg [5:0] rdlvl_cpt_tap_cnt;
reg prbs_rdlvl_start_r;
reg compare_err;
reg compare_err_r0;
reg compare_err_f0;
reg compare_err_r1;
reg compare_err_f1;
reg compare_err_r2;
reg compare_err_f2;
reg compare_err_r3;
reg compare_err_f3;
reg compare_err_latch;
reg samples_cnt1_en_r;
reg samples_cnt2_en_r;
reg [11:0] samples_cnt_r;
reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync
reg [DQS_WIDTH-1:0] prbs_tap_mod;
//reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
//reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
//**************************************************************************
// signals for per-bit algorithm of fine_delay calculations
//**************************************************************************
reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit
reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit
reg [MIN_WIN*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit
reg [MIN_WIN-1:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail)
reg [MIN_WIN-1:0] match_flag_or; //5 consecute match flag of all bits (1: any bit fail)
reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation
reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update
reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update
reg right_edge_found; //smallest right_edge found
reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit
reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit
reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge)
reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit
reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge
reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits
reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte
reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte
reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center)
reg [6:0] center_calc; //used for calculate the dec tap for centering
reg [5:0] right_edge_ref; //ref_bit right edge
reg [5:0] left_edge_ref; //ref_bit left edge
reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit
reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge
reg compare_err_pb_and; //indicate all bit fail
reg compare_err_pb_or; //indicate any bit fail
reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit)
reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage)
wire fine_calib; //turn on/off fine delay calibration
reg [5:0] mem_out_dec;
reg [5:0] dec_cnt;
reg fine_dly_error; //indicate it has wrong left/right edge
reg edge_det_error; //indicate it has wrong left/right edge
wire center_comp;
wire pi_adj;
reg no_err_win_detected;
reg no_err_win_detected_latch;
reg [1:0] valid_window_cnt; //number of valid window in the scan
reg double_window_ind; //indication of double window
//if inital PI dec is not done, init SM should wait until it is done
reg complex_init_pi_dec_done_r; //if inital PI dec is not done, init SM should wait until it is done
wire complex_rdlvl_err;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
//fine delay turn on
assign fine_calib = (FINE_PER_BIT=="ON")? 1:0;
assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0;
assign pi_adj = (PI_VAL_ADJ == "ON")?1:0;
//Debug error flag
assign complex_rdlvl_err = fine_dly_error | edge_det_error;
//initial dec is only happening for per-bit
assign complex_init_pi_dec_done = fine_calib? complex_init_pi_dec_done_r : 1'b1;
assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6];
assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2];
assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6];
assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2];
assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ;
assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2];
assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ;
assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2];
assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6];
assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2];
assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6];
assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2];
assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6];
assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2];
assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6];
assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2];
assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6];
assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2];
assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ;
assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2];
assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6];
assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2];
assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6];
assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2];
assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6];
assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2];
assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6];
assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2];
assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6];
assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2];
assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6];
assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2];
assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val;
assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r;
assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r;
assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r;
assign dbg_prbs_rdlvl[142] = compare_err;
assign dbg_prbs_rdlvl[143] = phy_if_empty;
assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start;
assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done;
assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r;
assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ;
assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6];
assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]};
assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ;
assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0];
assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0];
assign dbg_prbs_rdlvl[184] = rd_valid_r2;
assign dbg_prbs_rdlvl[185] = compare_err_r0;
assign dbg_prbs_rdlvl[186] = compare_err_f0;
assign dbg_prbs_rdlvl[187] = compare_err_r1;
assign dbg_prbs_rdlvl[188] = compare_err_f1;
assign dbg_prbs_rdlvl[189] = compare_err_r2;
assign dbg_prbs_rdlvl[190] = compare_err_f2;
assign dbg_prbs_rdlvl[191] = compare_err_r3;
assign dbg_prbs_rdlvl[192] = compare_err_f3;
assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb;
assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb;
assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ;
assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ;
assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb;
assign dbg_prbs_rdlvl[229] = fine_delay_sel;
assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r;
assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt;
assign dbg_prbs_rdlvl[244+:5] = match_flag_and[4:0];
assign dbg_prbs_rdlvl[249+:2] = stage_cnt;
assign dbg_prbs_rdlvl[251] = fine_inc_stage;
assign dbg_prbs_rdlvl[252] = compare_err_pb_and;
assign dbg_prbs_rdlvl[253] = right_edge_found;
assign dbg_prbs_rdlvl[254] = complex_rdlvl_err;
assign dbg_prbs_rdlvl[255] = double_window_ind;
//**************************************************************************
// Record first and second edges found during calibration
//**************************************************************************
generate
always @(posedge clk)
if (rst) begin
dbg_prbs_first_edge_taps <= #TCQ 'b0;
dbg_prbs_second_edge_taps <= #TCQ 'b0;
end else if (prbs_state_r == PRBS_CALC_TAPS) begin
// Record tap counts of first and second edge edges during
// calibration for each DQS group. If neither edge has
// been found, then those taps will remain 0
if (prbs_found_1st_edge_r)
dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_1st_edge_taps_r;
if (prbs_found_2nd_edge_r)
dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_2nd_edge_taps_r;
end else if (prbs_state_r == FINE_CALC_TAPS) begin
if(stage_cnt == 'd2) begin
dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ largest_left_edge;
dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ smallest_right_edge;
end
end
endgenerate
//double window indication flag
always @ (posedge clk)
if (rst) double_window_ind <= #TCQ 1'd0;
else double_window_ind <= #TCQ double_window_ind? 1'b1: (valid_window_cnt > 1);
//padded calculation
always @ (smallest_right_edge or largest_left_edge)
center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge};
//***************************************************************************
//***************************************************************************
// Data mux to route appropriate bit to calibration logic - i.e. calibration
// is done sequentially, one bit (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else begin: rd_data_div2_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r2 = 'h0;
assign compare_data_f2 = 'h0;
assign compare_data_r3 = 'h0;
assign compare_data_f3 = 'h0;
end
endgenerate
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
//Compare data
compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
endgenerate
generate
genvar muxr2_i;
if (nCK_PER_CLK == 4) begin: gen_mux_div4
for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4
always @(posedge clk) begin
if (mux_rd_valid_r) begin
mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i];
mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i];
mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i];
mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i];
end
//pipeline stage
mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i];
mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i];
mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i];
mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i];
//pipeline stage
mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i];
mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i];
mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i];
mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_div2
for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2
always @(posedge clk) begin
if (mux_rd_valid_r) begin
mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
mux_rd_rise2_r2[muxr2_i] <= 'h0;
mux_rd_fall2_r2[muxr2_i] <= 'h0;
mux_rd_rise3_r2[muxr2_i] <= 'h0;
mux_rd_fall3_r2[muxr2_i] <= 'h0;
end
mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
mux_rd_rise2_r3[muxr2_i] <= 'h0;
mux_rd_fall2_r3[muxr2_i] <= 'h0;
mux_rd_rise3_r3[muxr2_i] <= 'h0;
mux_rd_fall3_r3[muxr2_i] <= 'h0;
//pipeline stage
mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
mux_rd_rise2_r4[muxr2_i] <= 'h0;
mux_rd_fall2_r4[muxr2_i] <= 'h0;
mux_rd_rise3_r4[muxr2_i] <= 'h0;
mux_rd_fall3_r4[muxr2_i] <= 'h0;
end
end
end
endgenerate
// Registered signal indicates when mux_rd_rise/fall_r is valid
always @(posedge clk) begin
mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start;
rd_valid_r1 <= #TCQ mux_rd_valid_r;
rd_valid_r2 <= #TCQ rd_valid_r1;
rd_valid_r3 <= #TCQ rd_valid_r2;
end
// Counter counts # of samples compared
// Reset sample counter when not "sampling"
// Otherwise, count # of samples compared
// Same counter is shared for three samples checked
always @(posedge clk)
if (rst)
samples_cnt_r <= #TCQ 'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
samples_cnt_r <= #TCQ 'b0;
end else if (complex_sample_cnt_inc) begin
samples_cnt_r <= #TCQ samples_cnt_r + 1;
/*if (!rd_valid_r1 ||
(prbs_state_r == PRBS_DEC_DQS_WAIT) ||
(prbs_state_r == PRBS_INC_DQS_WAIT) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(samples_cnt_r == NUM_SAMPLES_CNT) ||
(samples_cnt_r == NUM_SAMPLES_CNT1))
samples_cnt_r <= #TCQ 'b0;
else if (rd_valid_r1 &&
(((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) ||
((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) ||
((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r)))
samples_cnt_r <= #TCQ samples_cnt_r + 1;*/
end
// Count #2 enable generation
// Assert when correct number of samples compared
always @(posedge clk)
if (rst)
samples_cnt1_en_r <= #TCQ 1'b0;
else begin
if ((prbs_state_r == PRBS_IDLE) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
samples_cnt1_en_r <= #TCQ 1'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1)
samples_cnt1_en_r <= #TCQ 1'b1;
end
// Counter #3 enable generation
// Assert when correct number of samples compared
always @(posedge clk)
if (rst)
samples_cnt2_en_r <= #TCQ 1'b0;
else begin
if ((prbs_state_r == PRBS_IDLE) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
samples_cnt2_en_r <= #TCQ 1'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r)
samples_cnt2_en_r <= #TCQ 1'b1;
end
// Victim selection logic
always @(posedge clk)
if (rst)
rd_victim_sel <= #TCQ 'd0;
else if (num_samples_done_r)
rd_victim_sel <= #TCQ 'd0;
else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
if (rd_victim_sel < 'd7)
rd_victim_sel <= #TCQ rd_victim_sel + 1;
end
// Output row count increment pulse to phy_init
always @(posedge clk)
if (rst)
complex_victim_inc <= #TCQ 1'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT)
complex_victim_inc <= #TCQ 1'b1;
else
complex_victim_inc <= #TCQ 1'b0;
generate
if (FIXED_VICTIM == "TRUE") begin: victim_fixed
always @(posedge clk)
if (rst)
num_samples_done_r <= #TCQ 1'b0;
else if ((prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS)||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == FINE_PI_DEC))
num_samples_done_r <= #TCQ 'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT)
num_samples_done_r <= #TCQ 1'b1;
end else begin: victim_not_fixed
always @(posedge clk)
if (rst)
num_samples_done_r <= #TCQ 1'b0;
else if ((prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS)||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == FINE_PI_DEC))
num_samples_done_r <= #TCQ 'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7))
num_samples_done_r <= #TCQ 1'b1;
end
endgenerate
//***************************************************************************
// Compare Read Data for the byte being Leveled with Expected data from PRBS
// generator. Resulting compare_err signal used to determine read data valid
// edge.
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: cmp_err_4to1
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin
compare_err <= #TCQ 1'b0;
compare_err_r0 <= #TCQ 1'b0;
compare_err_f0 <= #TCQ 1'b0;
compare_err_r1 <= #TCQ 1'b0;
compare_err_f1 <= #TCQ 1'b0;
compare_err_r2 <= #TCQ 1'b0;
compare_err_f2 <= #TCQ 1'b0;
compare_err_r3 <= #TCQ 1'b0;
compare_err_f3 <= #TCQ 1'b0;
end else if (rd_valid_r2) begin
compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1);
compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1);
compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1);
compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1 |
compare_err_r2 | compare_err_f2 |
compare_err_r3 | compare_err_f3);
end
end
end else begin: cmp_err_2to1
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin
compare_err <= #TCQ 1'b0;
compare_err_r0 <= #TCQ 1'b0;
compare_err_f0 <= #TCQ 1'b0;
compare_err_r1 <= #TCQ 1'b0;
compare_err_f1 <= #TCQ 1'b0;
end else if (rd_valid_r2) begin
compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1);
end
end
end
endgenerate
//Sticky bit compare_err
always @ (posedge clk)
if (prbs_state_r == PRBS_PAT_COMPARE)
compare_err_latch <= #TCQ compare_err? 1'b1: compare_err_latch;
else
compare_err_latch <= #TCQ 1'b0;
//***************************************************************************
// Decrement initial Phaser_IN fine delay value before proceeding with
// read calibration
//***************************************************************************
//***************************************************************************
// Demultiplexor to control Phaser_IN delay values
//***************************************************************************
// Read DQS
always @(posedge clk) begin
if (rst) begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (prbs_tap_en_r) begin
// Change only specified DQS
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r;
end else begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;
pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
end
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
prbs_rdlvl_prech_req <= #TCQ 1'b0;
else
prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r;
//*****************************************************************
// keep track of edge tap counts found, and current capture clock
// tap count
//*****************************************************************
always @(posedge clk)
if (rst) begin
prbs_dqs_tap_cnt_r <= #TCQ 'b0;
rdlvl_cpt_tap_cnt <= #TCQ 'b0;
end else if (new_cnt_dqs_r) begin
prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val;
rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val;
end else if (prbs_tap_en_r) begin
if (prbs_tap_inc_r)
prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
else if (prbs_dqs_tap_cnt_r != 'd0)
prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
end
always @(posedge clk)
if (rst) begin
prbs_dec_tap_calc_plus_3 <= #TCQ 'b0;
prbs_dec_tap_calc_minus_3 <= #TCQ 'b0;
end else if (new_cnt_dqs_r) begin
prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011;
prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100;
end else begin
prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3);
prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3);
end
always @(posedge clk)
if (rst || new_cnt_dqs_r)
prbs_dqs_tap_limit_r <= #TCQ 1'b0;
else if (prbs_dqs_tap_cnt_r == 6'd63)
prbs_dqs_tap_limit_r <= #TCQ 1'b1;
else
prbs_dqs_tap_limit_r <= #TCQ 1'b0;
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*prbs_dqs_cnt_r.
// replacing this with two left shifts + one left shift to avoid
// DSP multiplier.
assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r};
always @(posedge clk)
prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing;
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
prbs_final_dqs_tap_cnt_r <= #TCQ 'b0;
end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin
prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_dqs_tap_cnt_r;
end
end
//*****************************************************************
always @(posedge clk) begin
prbs_state_r1 <= #TCQ prbs_state_r;
prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start;
end
// Wait counter for wait states
always @(posedge clk)
if ((prbs_state_r == PRBS_NEW_DQS_WAIT) ||
(prbs_state_r == PRBS_INC_DQS_WAIT) ||
(prbs_state_r == PRBS_DEC_DQS_WAIT) ||
(prbs_state_r == FINE_PI_DEC_WAIT) ||
(prbs_state_r == FINE_PI_INC_WAIT) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
wait_state_cnt_en_r <= #TCQ 1'b1;
else
wait_state_cnt_en_r <= #TCQ 1'b0;
always @(posedge clk)
if (!wait_state_cnt_en_r) begin
wait_state_cnt_r <= #TCQ 'b0;
cnt_wait_state <= #TCQ 1'b0;
end else begin
if (wait_state_cnt_r < 'd15) begin
wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1;
cnt_wait_state <= #TCQ 1'b0;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
wait_state_cnt_r <= #TCQ 'b0;
cnt_wait_state <= #TCQ 1'b1;
end
end
always @ (posedge clk)
err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14);
//*****************************************************************
// compare error checking per-bit
//****************************************************************
generate
genvar pb_i;
if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1
for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
always @ (posedge clk) begin
//prevent error check during PI inc/dec and wait
if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
(err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
compare_err_pb[pb_i] <= #TCQ 1'b0;
else if (rd_valid_r2)
compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
(mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
(mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
(mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) |
(mux_rd_rise2_r3[pb_i] != compare_data_rise2_r1[pb_i]) |
(mux_rd_fall2_r3[pb_i] != compare_data_fall2_r1[pb_i]) |
(mux_rd_rise3_r3[pb_i] != compare_data_rise3_r1[pb_i]) |
(mux_rd_fall3_r3[pb_i] != compare_data_fall3_r1[pb_i]) ;
end //always
end //for
end else begin: cmp_err_pb_2to1
for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
(err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
compare_err_pb[pb_i] <= #TCQ 1'b0;
else if (rd_valid_r2)
compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
(mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
(mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
(mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) ;
end //always
end //for
end //if
endgenerate
//generate stick error bit - left/right edge
generate
genvar pb_r;
for(pb_r=0; pb_r<DRAM_WIDTH; pb_r=pb_r+1) begin
always @ (posedge clk) begin
if((prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) |
(~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT))))
compare_err_pb_latch_r[pb_r] <= #TCQ 1'b0;
else
compare_err_pb_latch_r[pb_r] <= #TCQ compare_err_pb[pb_r]? 1'b1:compare_err_pb_latch_r[pb_r];
end
end
endgenerate
//checking all/any bit has error
always @ (posedge clk) begin
if(rst | (prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) |
(~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT)))) begin
compare_err_pb_and <= #TCQ 1'b0;
compare_err_pb_or <= #TCQ 1'b0;
end
else begin
compare_err_pb_and <= #TCQ &compare_err_pb? 1'b1: compare_err_pb_and;
compare_err_pb_or <= #TCQ |compare_err_pb? 1'b1: compare_err_pb_or;
end
end
//in stage 0, if left edge found, update ref_bit (one hot)
always @ (posedge clk) begin
if (rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
ref_bit_per_bit <= #TCQ 'd0;
end else if ((prbs_state_r == FINE_PI_INC) && (stage_cnt=='b0)) begin
if(|left_edge_updated) ref_bit_per_bit <= #TCQ left_edge_updated;
end
end
//ref bit with samllest right edge
//if bit 1 and 3 are set to ref_bit_per_bit but bit 1 has smaller right edge, bit is selected as ref_bit
always @ (posedge clk) begin
if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
bit_cnt <= #TCQ 'd0;
ref_right_edge <= #TCQ 6'h3f;
ref_bit <= #TCQ 'd0;
end else if ((prbs_state_r == FINE_CALC_TAPS_WAIT) && (stage_cnt == 'b0) && (bit_cnt < DRAM_WIDTH)) begin
bit_cnt <= #TCQ bit_cnt +'b1;
if ((ref_bit_per_bit[bit_cnt]==1'b1) && (right_edge_pb[bit_cnt*6+:6]<= ref_right_edge)) begin
ref_bit <= #TCQ bit_cnt;
ref_right_edge <= #TCQ right_edge_pb[bit_cnt*6+:6];
end
end
end
//pipe lining for reference bit left/right edge
always @ (posedge clk) begin
left_edge_ref <= #TCQ left_edge_pb[ref_bit*6+:6];
right_edge_ref <= #TCQ right_edge_pb[ref_bit*6+:6];
end
//left_edge/right_edge/left_loss/right_gain update
generate
genvar eg;
for(eg=0; eg<DRAM_WIDTH; eg = eg+1) begin
always @ (posedge clk) begin
if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE; //8'hff
left_edge_pb[eg*6+:6] <= #TCQ 'b0;
right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
left_edge_found_pb[eg] <= #TCQ 1'b0;
right_edge_found_pb[eg] <= #TCQ 1'b0;
left_loss_pb[eg*6+:6] <= #TCQ 'b0;
right_gain_pb[eg*6+:6] <= #TCQ 'b0;
left_edge_updated[eg] <= #TCQ 'b0;
end else begin
if((prbs_state_r == FINE_PAT_COMPARE_PER_BIT) && num_samples_done_r) begin
//left edge is updated when match flag becomes 10000000 (1 fail ,8 success)
if(match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_LEFT && compare_err_pb_latch_r[eg]==0) begin
left_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1);
left_edge_found_pb[eg] <= #TCQ 1'b1; //used for update largest_left_edge
left_edge_updated[eg] <= #TCQ 1'b1;
//check the loss of bit - update only for left edge found
if(~left_edge_found_pb[eg])
left_loss_pb[eg*6+:6] <= #TCQ (left_edge_ref > prbs_dqs_tap_cnt_r -(MIN_WIN-1))? 'd0
: prbs_dqs_tap_cnt_r-(MIN_WIN-1)-left_edge_ref;
//right edge is updated when match flag becomes 000000001 (8 success, 1 fail)
end else if (match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_PASS && compare_err_pb_latch_r[eg]) begin
right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1;
right_edge_found_pb[eg] <= #TCQ 1'b1;
//check the gain of bit - update only for right edge found
if(~right_edge_found_pb[eg])
right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)?
((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]):
((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]);
//no right edge found
end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin
right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
right_edge_found_pb[eg] <= #TCQ 1'b1;
//right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge)
right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])?
(right_edge_ref - right_edge_pb[eg*6+:6]) : 0;
end
//update match flag - shift and update
match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ {match_flag_pb[(eg*MIN_WIN)+:(MIN_WIN-1)],compare_err_pb_latch_r[eg]};
end else if (prbs_state_r == FINE_PI_DEC) begin
left_edge_found_pb[eg] <= #TCQ 1'b0;
right_edge_found_pb[eg] <= #TCQ 1'b0;
left_loss_pb[eg*6+:6] <= #TCQ 'b0;
right_gain_pb[eg*6+:6] <= #TCQ 'b0;
match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE ; //new fix
left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge
end else if (prbs_state_r == FINE_PI_INC) begin
left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge
end
end
end //always
end //for
endgenerate
//update fine_delay according to loss/gain value per bit
generate
genvar f_pb;
for(f_pb=0; f_pb<DRAM_WIDTH; f_pb=f_pb+1) begin
always @ (posedge clk) begin
if(rst | prbs_state_r == PRBS_NEW_DQS_WAIT ) begin
fine_delay_incdec_pb[f_pb] <= #TCQ 1'b0;
end else if((prbs_state_r == FINE_CALC_TAPS_WAIT) && (bit_cnt == DRAM_WIDTH)) begin
if(stage_cnt == 'd0) fine_delay_incdec_pb[f_pb] <= #TCQ (f_pb==ref_bit)? 1'b0:1'b1; //only for initial stage
else if(stage_cnt == 'd1) fine_delay_incdec_pb[f_pb] <= #TCQ (right_gain_pb[f_pb*6+:6]>left_loss_pb[f_pb*6+:6])?1'b1:1'b0;
end
end
end
endgenerate
//fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3)
always @ (posedge clk) begin
if (rst)
fine_inc_stage <= #TCQ 'b1;
else
fine_inc_stage <= #TCQ (stage_cnt!='d3);
end
//*****************************************************************
always @(posedge clk)
if (rst) begin
prbs_dqs_cnt_r <= #TCQ 'b0;
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
prbs_state_r <= #TCQ PRBS_IDLE;
prbs_found_1st_edge_r <= #TCQ 1'b0;
prbs_found_2nd_edge_r <= #TCQ 1'b0;
prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx;
prbs_inc_tap_cnt <= #TCQ 'b0;
prbs_dec_tap_cnt <= #TCQ 'b0;
new_cnt_dqs_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL")
prbs_rdlvl_done <= #TCQ 1'b1;
else
prbs_rdlvl_done <= #TCQ 1'b0;
prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_tap_mod <= #TCQ 'd0;
reset_rd_addr <= #TCQ 'b0;
fine_pi_dec_cnt <= #TCQ 'b0;
match_flag_and <= #TCQ MATCH_ALL_ONE;
match_flag_or <= #TCQ MATCH_ALL_ONE;
no_err_win_detected <= #TCQ 1'b0;
no_err_win_detected_latch <= #TCQ 1'b0;
valid_window_cnt <= 2'd0;
stage_cnt <= #TCQ 2'b00;
right_edge_found <= #TCQ 1'b0;
largest_left_edge <= #TCQ 6'b000000;
smallest_right_edge <= #TCQ 6'b111111;
num_samples_done_ind <= #TCQ 'b0;
fine_delay_sel <= #TCQ 'b0;
fine_dly_error <= #TCQ 'b0;
edge_det_error <= #TCQ 'b0;
complex_pi_incdec_done <= #TCQ 1'b0;
complex_init_pi_dec_done_r <= #TCQ 1'b0;
end else begin
case (prbs_state_r)
PRBS_IDLE: begin
prbs_last_byte_done <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin
if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin
prbs_state_r <= #TCQ PRBS_DONE;
reset_rd_addr <= #TCQ 1'b1;
end else begin
new_cnt_dqs_r <= #TCQ 1'b1;
prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
end
end
end
// Wait for the new DQS group to change
// also gives time for the read data IN_FIFO to
// output the updated data for the new DQS group
PRBS_NEW_DQS_WAIT: begin
reset_rd_addr <= #TCQ 'b0;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
stage_cnt <= #TCQ 2'b0;
match_flag_and <= #TCQ MATCH_ALL_ONE;
match_flag_or <= #TCQ MATCH_ALL_ONE;
no_err_win_detected <= #TCQ 1'b0;
no_err_win_detected_latch <= #TCQ 1'b0;
if (cnt_wait_state) begin
new_cnt_dqs_r <= #TCQ 1'b0;
prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE;
//For normal, it doesn't have initial pi incdec
complex_pi_incdec_done <= #TCQ fine_calib? complex_pi_incdec_done: 1'b1;
end
end
// Check for presence of data eye edge. During this state, we
// sample the read data multiple times, and look for changes
// in the read data, specifically:
// 1. A change in the read data compared with the value of
// read data from the previous delay tap. This indicates
// that the most recent tap delay increment has moved us
// into either a new window, or moved/kept us in the
// transition/jitter region between windows. Note that this
// condition only needs to be checked for once, and for
// logistical purposes, we check this soon after entering
// this state (see comment in PRBS_PAT_COMPARE below for
// why this is done)
// 2. A change in the read data while we are in this state
// (i.e. in the absence of a tap delay increment). This
// indicates that we're close enough to a window edge that
// jitter will cause the read data to change even in the
// absence of a tap delay change
PRBS_PAT_COMPARE: begin
// Continue to sample read data and look for edges until the
// appropriate time interval (shorter for simulation-only,
// much, much longer for actual h/w) has elapsed
//comparision started - wait for next PI movement after read
complex_pi_incdec_done <= #TCQ 1'b0; //need to be wait for new incdec done
if (num_samples_done_r) begin
if (prbs_dqs_tap_limit_r)
// Only one edge detected and ran out of taps since only one
// bit time worth of taps available for window detection. This
// can happen if at tap 0 DQS is in previous window which results
// in only left edge being detected. Or at tap 0 DQS is in the
// current window resulting in only right edge being detected.
// Depending on the frequency this case can also happen if at
// tap 0 DQS is in the left noise region resulting in only left
// edge being detected.
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
else if (compare_err_latch || (prbs_dqs_tap_cnt_r == 'd0)) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
prbs_found_1st_edge_r <= #TCQ 1'b1;
// Both edges of data valid window found:
// If we've found a second edge after a region of stability
// then we must have just passed the second ("right" edge of
// the window. Record this second_edge_taps = current tap-1,
// because we're one past the actual second edge tap, where
// the edge taps represent the extremes of the data valid
// window (i.e. smallest & largest taps where data still valid
if (prbs_found_1st_edge_r) begin
prbs_found_2nd_edge_r <= #TCQ 1'b1;
prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
end else begin
// Otherwise, an edge was found (just not the "second" edge)
// Assuming DQS is in the correct window at tap 0 of Phaser IN
// fine tap. The first edge found is the right edge of the valid
// window and is the beginning of the jitter region hence done!
if (compare_err_latch)
prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
else
prbs_1st_edge_taps_r <= #TCQ 'd0;
prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC;
end
end else begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
if (prbs_found_1st_edge_r)
//prbs_state_r <= #TCQ PRBS_INC_DQS;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC;
else
//prbs_state_r <= #TCQ PRBS_DEC_DQS;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end
end
end
// Increment Phaser_IN delay for DQS
PRBS_INC_DQS: begin
prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT;
if (prbs_inc_tap_cnt > 'd0)
prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1;
if (~prbs_dqs_tap_limit_r) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b1;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
// only all INC is done, incdec done is asserted
PRBS_INC_DQS_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
if (prbs_inc_tap_cnt > 'd0)
prbs_state_r <= #TCQ PRBS_INC_DQS; //centering
else begin
prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
complex_pi_incdec_done <= #TCQ 1'b1;
end
end
end
// Calculate final value of Phaser_IN taps. At this point, one or both
// edges of data eye have been found, and/or all taps have been
// exhausted looking for the edges
// NOTE: The amount to be decrement by is calculated, not the
// absolute setting for DQS.
// CENTER compensation with shift by 1
//wait finishing the read before PI dec to center
PRBS_CALC_TAPS: begin
if (center_comp) begin
prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj;
fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end else begin //No center compensation
if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin
// Both edges detected
prbs_dec_tap_cnt
<= #TCQ ((prbs_2nd_edge_taps_r -
prbs_1st_edge_taps_r)>>1) + 1 + pi_adj;
edge_det_error <= #TCQ edge_det_error? 1'b1:
(prbs_1st_edge_taps_r >= prbs_2nd_edge_taps_r);
end else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin
// Only left edge detected
prbs_dec_tap_cnt
<= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj;
end else begin
// No edges detected
edge_det_error <= #TCQ 1'b1;
prbs_dec_tap_cnt
<= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj;
end
// Now use the value we just calculated to decrement CPT taps
// to the desired calibration point
//wait finishing the read before PI dec to center
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end
end
// decrement capture clock for final adjustment - center
// capture clock in middle of data eye. This adjustment will occur
// only when both the edges are found usign CPT taps. Must do this
// incrementally to avoid clock glitching (since CPT drives clock
// divider within each ISERDES)
PRBS_DEC_DQS: begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b0;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
if (prbs_dec_tap_cnt > 'd0)
prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1;
if (prbs_dec_tap_cnt == 6'b000001) begin
prbs_state_r <= #TCQ PRBS_NEXT_DQS;
//only all DEC is done, incdec done is asserted
complex_pi_incdec_done <= #TCQ 1'b1;
end else
prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT;
end
PRBS_DEC_DQS_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
if (prbs_dec_tap_cnt > 'd0)
prbs_state_r <= #TCQ PRBS_DEC_DQS;
else begin
//PI movement is done, go to read and compare
complex_pi_incdec_done <= #TCQ 1'b1;
prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
end
end
end
// Determine whether we're done, or have more DQS's to calibrate
// Also request precharge after every byte, as appropriate
PRBS_NEXT_DQS: begin
//Need to do initial dec for per-bit algorithm
complex_init_pi_dec_done_r <= #TCQ 1'b0;
reset_rd_addr <= #TCQ 'b1;
prbs_prech_req_r <= #TCQ 1'b1;
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
// Prepare for another iteration with next DQS group
prbs_found_1st_edge_r <= #TCQ 1'b0;
prbs_found_2nd_edge_r <= #TCQ 1'b0;
prbs_1st_edge_taps_r <= #TCQ 'd0;
prbs_2nd_edge_taps_r <= #TCQ 'd0;
largest_left_edge <= #TCQ 6'b000000;
smallest_right_edge <= #TCQ 6'b111111;
if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
prbs_last_byte_done <= #TCQ 1'b1;
end
// Wait until precharge that occurs in between calibration of
// DQS groups is finished
if (prech_done) begin
prbs_prech_req_r <= #TCQ 1'b0;
if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
// All DQS groups done
prbs_state_r <= #TCQ PRBS_DONE;
end else begin
// Process next DQS group
new_cnt_dqs_r <= #TCQ 1'b1;
prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1;
prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT;
end
end
end
PRBS_NEW_DQS_PREWAIT: begin
if (cnt_wait_state) begin
prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
end
end
PRBS_CALC_TAPS_PRE:
begin
//Wait for new PI movement
complex_pi_incdec_done <= #TCQ 1'b0;
prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT;
if(center_comp && ~fine_calib) begin
if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r;
else largest_left_edge <= #TCQ 6'd0;
if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r;
else smallest_right_edge <= #TCQ 6'd63;
end
end
//wait for center compensation
PRBS_CALC_TAPS_WAIT:
begin
prbs_state_r <= #TCQ PRBS_CALC_TAPS;
end
//if it is fine_inc stage (first/second stage): dec to 0
//if it is fine_dec stage (third stage): dec to center
FINE_PI_DEC: begin
fine_delay_sel <= #TCQ 'b0;
if(fine_pi_dec_cnt > 0) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b0;
fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1;
end
prbs_state_r <= #TCQ FINE_PI_DEC_WAIT;
end
//wait for phaser_in tap decrement.
//if first/second stage is done, goes to FINE_PI_INC
//if last stage is done, goes to NEXT_DQS
//All PI DEC is done, incdec done is asserted
FINE_PI_DEC_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if(cnt_wait_state) begin
if(fine_pi_dec_cnt >0)
prbs_state_r <= #TCQ FINE_PI_DEC;
else begin
complex_pi_incdec_done <= #TCQ 1'b1;
if(fine_inc_stage)
prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0"
else
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS
end
end
end
//finish the read before PI increament
RD_DONE_WAIT_FOR_PI_INC_INC: begin
if(complex_act_start)
prbs_state_r <= #TCQ fine_calib? FINE_PI_INC: PRBS_INC_DQS;
end
FINE_PI_INC: begin
//prevent left edge update after valid window found
if(|left_edge_updated && ~no_err_win_detected_latch) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1);
if (no_err_win_detected) begin
//ignore previous right edge updated if valid window shown after
right_edge_found <= #TCQ 'b0;
end else if(|right_edge_found_pb && ~right_edge_found) begin
smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ;
right_edge_found <= #TCQ 'b1;
end
//until minimum window is detected, left edge can be updated
//once minimum window is detected, no further left edge update will be done
if(no_err_win_detected) no_err_win_detected_latch <= #TCQ 1'b1;
prbs_state_r <= #TCQ FINE_PI_INC_WAIT;
if(~prbs_dqs_tap_limit_r) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b1;
end
end
//wait for phase_in tap increment
//need to do pattern compare for every bit
FINE_PI_INC_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT;
//PI movement is done, go to read and compare
complex_pi_incdec_done <= #TCQ 1'b1;
end
end
//compare per bit data and update flags,left/right edge
FINE_PAT_COMPARE_PER_BIT: begin
//comparision started - initial pi dec is done, wait for another pi movement after read
complex_init_pi_dec_done_r <= #TCQ 1'b1;
complex_pi_incdec_done <= #TCQ 1'b0;
if(num_samples_done_r) begin //sampling boundary
//update and_flag - shift and add
match_flag_and <= #TCQ {match_flag_and[MIN_WIN-2:0],compare_err_pb_and};
match_flag_or <= #TCQ {match_flag_or[MIN_WIN-2:0],compare_err_pb_or};
//to solve false left/right edge detection
if({match_flag_or[MIN_WIN-2:0],compare_err_pb_or} == MIN_PASS) begin //if it detect minimum window
no_err_win_detected <= #TCQ 1'b1;
valid_window_cnt <= #TCQ valid_window_cnt + 'd1;
end else begin
no_err_win_detected <= #TCQ 1'b0;
end
//if it is consecutive 8 passing taps followed by fail or tap limit (finish the search)
//don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage
//Or if all right edge are found
if((match_flag_and == MIN_PASS && compare_err_pb_and && (prbs_dqs_tap_cnt_r > MIN_WIN )) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin
prbs_state_r <= #TCQ FINE_CALC_TAPS;
//if all right edge are alined (all right edge found at the same time), update smallest right edge in here
//doesnt need to set right_edge_found to 1 since it is not used after this stage
if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1;
end else begin
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; //keep increase until all fail
end
num_samples_done_ind <= num_samples_done_r;
end
end
//for fine_inc stage, inc all fine delay
//for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain)
// put phaser_in taps to the center
FINE_CALC_TAPS: begin
if(num_samples_done_ind || num_samples_done_r) begin
num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set
right_edge_found <= #TCQ 1'b0; //reset right edge found
match_flag_and <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits
match_flag_or <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits
no_err_win_detected <= #TCQ 1'b0;
no_err_win_detected_latch <= #TCQ 1'b0;
prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT;
valid_window_cnt <= #TCQ 2'd0; //reset valid window counter
end
end
FINE_CALC_TAPS_WAIT: begin //wait for ROM read out
if(stage_cnt == 'd2) begin //last stage : back to center
if(center_comp) begin
fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1
fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error;
end else begin
fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1
fine_dly_error <= #TCQ 1'b0;
end
end else begin
fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r;
end
if (bit_cnt == DRAM_WIDTH) begin
fine_delay_sel <= #TCQ 'b1;
stage_cnt <= #TCQ stage_cnt + 1;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end
end
//wait for finishing the read before PI movement
RD_DONE_WAIT_FOR_PI_INC_DEC: begin
if (complex_act_start & ~complex_rdlvl_err)
prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC: PRBS_DEC_DQS;
end
// Done with this stage of calibration
PRBS_DONE: begin
prbs_prech_req_r <= #TCQ 1'b0;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_rdlvl_done <= #TCQ ~complex_rdlvl_err;
reset_rd_addr <= #TCQ 1'b0;
end
endcase
end
//ROM generation for dec counter
always @ (largest_left_edge or smallest_right_edge) begin
case ({largest_left_edge, smallest_right_edge})
12'd0 : mem_out_dec = 6'b111111;
12'd1 : mem_out_dec = 6'b111111;
12'd2 : mem_out_dec = 6'b111111;
12'd3 : mem_out_dec = 6'b111111;
12'd4 : mem_out_dec = 6'b111111;
12'd5 : mem_out_dec = 6'b111111;
12'd6 : mem_out_dec = 6'b000100;
12'd7 : mem_out_dec = 6'b000101;
12'd8 : mem_out_dec = 6'b000101;
12'd9 : mem_out_dec = 6'b000110;
12'd10 : mem_out_dec = 6'b000110;
12'd11 : mem_out_dec = 6'b000111;
12'd12 : mem_out_dec = 6'b001000;
12'd13 : mem_out_dec = 6'b001000;
12'd14 : mem_out_dec = 6'b001001;
12'd15 : mem_out_dec = 6'b001010;
12'd16 : mem_out_dec = 6'b001010;
12'd17 : mem_out_dec = 6'b001011;
12'd18 : mem_out_dec = 6'b001011;
12'd19 : mem_out_dec = 6'b001100;
12'd20 : mem_out_dec = 6'b001100;
12'd21 : mem_out_dec = 6'b001100;
12'd22 : mem_out_dec = 6'b001100;
12'd23 : mem_out_dec = 6'b001101;
12'd24 : mem_out_dec = 6'b001100;
12'd25 : mem_out_dec = 6'b001100;
12'd26 : mem_out_dec = 6'b001101;
12'd27 : mem_out_dec = 6'b001110;
12'd28 : mem_out_dec = 6'b001110;
12'd29 : mem_out_dec = 6'b001111;
12'd30 : mem_out_dec = 6'b010000;
12'd31 : mem_out_dec = 6'b010001;
12'd32 : mem_out_dec = 6'b010001;
12'd33 : mem_out_dec = 6'b010010;
12'd34 : mem_out_dec = 6'b010010;
12'd35 : mem_out_dec = 6'b010010;
12'd36 : mem_out_dec = 6'b010011;
12'd37 : mem_out_dec = 6'b010100;
12'd38 : mem_out_dec = 6'b010100;
12'd39 : mem_out_dec = 6'b010101;
12'd40 : mem_out_dec = 6'b010101;
12'd41 : mem_out_dec = 6'b010110;
12'd42 : mem_out_dec = 6'b010110;
12'd43 : mem_out_dec = 6'b010111;
12'd44 : mem_out_dec = 6'b011000;
12'd45 : mem_out_dec = 6'b011001;
12'd46 : mem_out_dec = 6'b011001;
12'd47 : mem_out_dec = 6'b011010;
12'd48 : mem_out_dec = 6'b011010;
12'd49 : mem_out_dec = 6'b011011;
12'd50 : mem_out_dec = 6'b011011;
12'd51 : mem_out_dec = 6'b011100;
12'd52 : mem_out_dec = 6'b011100;
12'd53 : mem_out_dec = 6'b011100;
12'd54 : mem_out_dec = 6'b011100;
12'd55 : mem_out_dec = 6'b011100;
12'd56 : mem_out_dec = 6'b011100;
12'd57 : mem_out_dec = 6'b011100;
12'd58 : mem_out_dec = 6'b011100;
12'd59 : mem_out_dec = 6'b011101;
12'd60 : mem_out_dec = 6'b011110;
12'd61 : mem_out_dec = 6'b011111;
12'd62 : mem_out_dec = 6'b100000;
12'd63 : mem_out_dec = 6'b100000;
12'd64 : mem_out_dec = 6'b111111;
12'd65 : mem_out_dec = 6'b111111;
12'd66 : mem_out_dec = 6'b111111;
12'd67 : mem_out_dec = 6'b111111;
12'd68 : mem_out_dec = 6'b111111;
12'd69 : mem_out_dec = 6'b111111;
12'd70 : mem_out_dec = 6'b111111;
12'd71 : mem_out_dec = 6'b000100;
12'd72 : mem_out_dec = 6'b000100;
12'd73 : mem_out_dec = 6'b000101;
12'd74 : mem_out_dec = 6'b000110;
12'd75 : mem_out_dec = 6'b000111;
12'd76 : mem_out_dec = 6'b000111;
12'd77 : mem_out_dec = 6'b001000;
12'd78 : mem_out_dec = 6'b001001;
12'd79 : mem_out_dec = 6'b001001;
12'd80 : mem_out_dec = 6'b001010;
12'd81 : mem_out_dec = 6'b001010;
12'd82 : mem_out_dec = 6'b001011;
12'd83 : mem_out_dec = 6'b001011;
12'd84 : mem_out_dec = 6'b001011;
12'd85 : mem_out_dec = 6'b001011;
12'd86 : mem_out_dec = 6'b001011;
12'd87 : mem_out_dec = 6'b001100;
12'd88 : mem_out_dec = 6'b001011;
12'd89 : mem_out_dec = 6'b001100;
12'd90 : mem_out_dec = 6'b001100;
12'd91 : mem_out_dec = 6'b001101;
12'd92 : mem_out_dec = 6'b001110;
12'd93 : mem_out_dec = 6'b001111;
12'd94 : mem_out_dec = 6'b001111;
12'd95 : mem_out_dec = 6'b010000;
12'd96 : mem_out_dec = 6'b010001;
12'd97 : mem_out_dec = 6'b010001;
12'd98 : mem_out_dec = 6'b010010;
12'd99 : mem_out_dec = 6'b010010;
12'd100 : mem_out_dec = 6'b010011;
12'd101 : mem_out_dec = 6'b010011;
12'd102 : mem_out_dec = 6'b010100;
12'd103 : mem_out_dec = 6'b010100;
12'd104 : mem_out_dec = 6'b010100;
12'd105 : mem_out_dec = 6'b010101;
12'd106 : mem_out_dec = 6'b010110;
12'd107 : mem_out_dec = 6'b010111;
12'd108 : mem_out_dec = 6'b010111;
12'd109 : mem_out_dec = 6'b011000;
12'd110 : mem_out_dec = 6'b011001;
12'd111 : mem_out_dec = 6'b011001;
12'd112 : mem_out_dec = 6'b011010;
12'd113 : mem_out_dec = 6'b011010;
12'd114 : mem_out_dec = 6'b011011;
12'd115 : mem_out_dec = 6'b011011;
12'd116 : mem_out_dec = 6'b011011;
12'd117 : mem_out_dec = 6'b011011;
12'd118 : mem_out_dec = 6'b011011;
12'd119 : mem_out_dec = 6'b011011;
12'd120 : mem_out_dec = 6'b011011;
12'd121 : mem_out_dec = 6'b011011;
12'd122 : mem_out_dec = 6'b011100;
12'd123 : mem_out_dec = 6'b011101;
12'd124 : mem_out_dec = 6'b011110;
12'd125 : mem_out_dec = 6'b011110;
12'd126 : mem_out_dec = 6'b011111;
12'd127 : mem_out_dec = 6'b100000;
12'd128 : mem_out_dec = 6'b111111;
12'd129 : mem_out_dec = 6'b111111;
12'd130 : mem_out_dec = 6'b111111;
12'd131 : mem_out_dec = 6'b111111;
12'd132 : mem_out_dec = 6'b111111;
12'd133 : mem_out_dec = 6'b111111;
12'd134 : mem_out_dec = 6'b111111;
12'd135 : mem_out_dec = 6'b111111;
12'd136 : mem_out_dec = 6'b000100;
12'd137 : mem_out_dec = 6'b000101;
12'd138 : mem_out_dec = 6'b000101;
12'd139 : mem_out_dec = 6'b000110;
12'd140 : mem_out_dec = 6'b000110;
12'd141 : mem_out_dec = 6'b000111;
12'd142 : mem_out_dec = 6'b001000;
12'd143 : mem_out_dec = 6'b001001;
12'd144 : mem_out_dec = 6'b001001;
12'd145 : mem_out_dec = 6'b001010;
12'd146 : mem_out_dec = 6'b001010;
12'd147 : mem_out_dec = 6'b001010;
12'd148 : mem_out_dec = 6'b001010;
12'd149 : mem_out_dec = 6'b001010;
12'd150 : mem_out_dec = 6'b001010;
12'd151 : mem_out_dec = 6'b001011;
12'd152 : mem_out_dec = 6'b001010;
12'd153 : mem_out_dec = 6'b001011;
12'd154 : mem_out_dec = 6'b001100;
12'd155 : mem_out_dec = 6'b001101;
12'd156 : mem_out_dec = 6'b001101;
12'd157 : mem_out_dec = 6'b001110;
12'd158 : mem_out_dec = 6'b001111;
12'd159 : mem_out_dec = 6'b010000;
12'd160 : mem_out_dec = 6'b010000;
12'd161 : mem_out_dec = 6'b010001;
12'd162 : mem_out_dec = 6'b010001;
12'd163 : mem_out_dec = 6'b010010;
12'd164 : mem_out_dec = 6'b010010;
12'd165 : mem_out_dec = 6'b010011;
12'd166 : mem_out_dec = 6'b010011;
12'd167 : mem_out_dec = 6'b010100;
12'd168 : mem_out_dec = 6'b010100;
12'd169 : mem_out_dec = 6'b010101;
12'd170 : mem_out_dec = 6'b010101;
12'd171 : mem_out_dec = 6'b010110;
12'd172 : mem_out_dec = 6'b010111;
12'd173 : mem_out_dec = 6'b010111;
12'd174 : mem_out_dec = 6'b011000;
12'd175 : mem_out_dec = 6'b011001;
12'd176 : mem_out_dec = 6'b011001;
12'd177 : mem_out_dec = 6'b011010;
12'd178 : mem_out_dec = 6'b011010;
12'd179 : mem_out_dec = 6'b011010;
12'd180 : mem_out_dec = 6'b011010;
12'd181 : mem_out_dec = 6'b011010;
12'd182 : mem_out_dec = 6'b011010;
12'd183 : mem_out_dec = 6'b011010;
12'd184 : mem_out_dec = 6'b011010;
12'd185 : mem_out_dec = 6'b011011;
12'd186 : mem_out_dec = 6'b011100;
12'd187 : mem_out_dec = 6'b011100;
12'd188 : mem_out_dec = 6'b011101;
12'd189 : mem_out_dec = 6'b011110;
12'd190 : mem_out_dec = 6'b011111;
12'd191 : mem_out_dec = 6'b100000;
12'd192 : mem_out_dec = 6'b111111;
12'd193 : mem_out_dec = 6'b111111;
12'd194 : mem_out_dec = 6'b111111;
12'd195 : mem_out_dec = 6'b111111;
12'd196 : mem_out_dec = 6'b111111;
12'd197 : mem_out_dec = 6'b111111;
12'd198 : mem_out_dec = 6'b111111;
12'd199 : mem_out_dec = 6'b111111;
12'd200 : mem_out_dec = 6'b111111;
12'd201 : mem_out_dec = 6'b000100;
12'd202 : mem_out_dec = 6'b000100;
12'd203 : mem_out_dec = 6'b000101;
12'd204 : mem_out_dec = 6'b000110;
12'd205 : mem_out_dec = 6'b000111;
12'd206 : mem_out_dec = 6'b001000;
12'd207 : mem_out_dec = 6'b001000;
12'd208 : mem_out_dec = 6'b001001;
12'd209 : mem_out_dec = 6'b001001;
12'd210 : mem_out_dec = 6'b001001;
12'd211 : mem_out_dec = 6'b001001;
12'd212 : mem_out_dec = 6'b001001;
12'd213 : mem_out_dec = 6'b001001;
12'd214 : mem_out_dec = 6'b001001;
12'd215 : mem_out_dec = 6'b001010;
12'd216 : mem_out_dec = 6'b001010;
12'd217 : mem_out_dec = 6'b001011;
12'd218 : mem_out_dec = 6'b001011;
12'd219 : mem_out_dec = 6'b001100;
12'd220 : mem_out_dec = 6'b001101;
12'd221 : mem_out_dec = 6'b001110;
12'd222 : mem_out_dec = 6'b001111;
12'd223 : mem_out_dec = 6'b001111;
12'd224 : mem_out_dec = 6'b010000;
12'd225 : mem_out_dec = 6'b010000;
12'd226 : mem_out_dec = 6'b010001;
12'd227 : mem_out_dec = 6'b010001;
12'd228 : mem_out_dec = 6'b010010;
12'd229 : mem_out_dec = 6'b010010;
12'd230 : mem_out_dec = 6'b010011;
12'd231 : mem_out_dec = 6'b010011;
12'd232 : mem_out_dec = 6'b010011;
12'd233 : mem_out_dec = 6'b010100;
12'd234 : mem_out_dec = 6'b010100;
12'd235 : mem_out_dec = 6'b010101;
12'd236 : mem_out_dec = 6'b010110;
12'd237 : mem_out_dec = 6'b010111;
12'd238 : mem_out_dec = 6'b011000;
12'd239 : mem_out_dec = 6'b011000;
12'd240 : mem_out_dec = 6'b011001;
12'd241 : mem_out_dec = 6'b011001;
12'd242 : mem_out_dec = 6'b011001;
12'd243 : mem_out_dec = 6'b011001;
12'd244 : mem_out_dec = 6'b011001;
12'd245 : mem_out_dec = 6'b011001;
12'd246 : mem_out_dec = 6'b011001;
12'd247 : mem_out_dec = 6'b011001;
12'd248 : mem_out_dec = 6'b011010;
12'd249 : mem_out_dec = 6'b011010;
12'd250 : mem_out_dec = 6'b011011;
12'd251 : mem_out_dec = 6'b011100;
12'd252 : mem_out_dec = 6'b011101;
12'd253 : mem_out_dec = 6'b011110;
12'd254 : mem_out_dec = 6'b011110;
12'd255 : mem_out_dec = 6'b011111;
12'd256 : mem_out_dec = 6'b111111;
12'd257 : mem_out_dec = 6'b111111;
12'd258 : mem_out_dec = 6'b111111;
12'd259 : mem_out_dec = 6'b111111;
12'd260 : mem_out_dec = 6'b111111;
12'd261 : mem_out_dec = 6'b111111;
12'd262 : mem_out_dec = 6'b111111;
12'd263 : mem_out_dec = 6'b111111;
12'd264 : mem_out_dec = 6'b111111;
12'd265 : mem_out_dec = 6'b111111;
12'd266 : mem_out_dec = 6'b000100;
12'd267 : mem_out_dec = 6'b000101;
12'd268 : mem_out_dec = 6'b000110;
12'd269 : mem_out_dec = 6'b000110;
12'd270 : mem_out_dec = 6'b000111;
12'd271 : mem_out_dec = 6'b001000;
12'd272 : mem_out_dec = 6'b001000;
12'd273 : mem_out_dec = 6'b001000;
12'd274 : mem_out_dec = 6'b001000;
12'd275 : mem_out_dec = 6'b001000;
12'd276 : mem_out_dec = 6'b001000;
12'd277 : mem_out_dec = 6'b001000;
12'd278 : mem_out_dec = 6'b001000;
12'd279 : mem_out_dec = 6'b001001;
12'd280 : mem_out_dec = 6'b001001;
12'd281 : mem_out_dec = 6'b001010;
12'd282 : mem_out_dec = 6'b001011;
12'd283 : mem_out_dec = 6'b001100;
12'd284 : mem_out_dec = 6'b001101;
12'd285 : mem_out_dec = 6'b001101;
12'd286 : mem_out_dec = 6'b001110;
12'd287 : mem_out_dec = 6'b001111;
12'd288 : mem_out_dec = 6'b001111;
12'd289 : mem_out_dec = 6'b010000;
12'd290 : mem_out_dec = 6'b010000;
12'd291 : mem_out_dec = 6'b010001;
12'd292 : mem_out_dec = 6'b010001;
12'd293 : mem_out_dec = 6'b010010;
12'd294 : mem_out_dec = 6'b010010;
12'd295 : mem_out_dec = 6'b010011;
12'd296 : mem_out_dec = 6'b010010;
12'd297 : mem_out_dec = 6'b010011;
12'd298 : mem_out_dec = 6'b010100;
12'd299 : mem_out_dec = 6'b010101;
12'd300 : mem_out_dec = 6'b010110;
12'd301 : mem_out_dec = 6'b010110;
12'd302 : mem_out_dec = 6'b010111;
12'd303 : mem_out_dec = 6'b011000;
12'd304 : mem_out_dec = 6'b011000;
12'd305 : mem_out_dec = 6'b011000;
12'd306 : mem_out_dec = 6'b011000;
12'd307 : mem_out_dec = 6'b011000;
12'd308 : mem_out_dec = 6'b011000;
12'd309 : mem_out_dec = 6'b011000;
12'd310 : mem_out_dec = 6'b011000;
12'd311 : mem_out_dec = 6'b011001;
12'd312 : mem_out_dec = 6'b011001;
12'd313 : mem_out_dec = 6'b011010;
12'd314 : mem_out_dec = 6'b011011;
12'd315 : mem_out_dec = 6'b011100;
12'd316 : mem_out_dec = 6'b011100;
12'd317 : mem_out_dec = 6'b011101;
12'd318 : mem_out_dec = 6'b011110;
12'd319 : mem_out_dec = 6'b011111;
12'd320 : mem_out_dec = 6'b111111;
12'd321 : mem_out_dec = 6'b111111;
12'd322 : mem_out_dec = 6'b111111;
12'd323 : mem_out_dec = 6'b111111;
12'd324 : mem_out_dec = 6'b111111;
12'd325 : mem_out_dec = 6'b111111;
12'd326 : mem_out_dec = 6'b111111;
12'd327 : mem_out_dec = 6'b111111;
12'd328 : mem_out_dec = 6'b111111;
12'd329 : mem_out_dec = 6'b111111;
12'd330 : mem_out_dec = 6'b111111;
12'd331 : mem_out_dec = 6'b000100;
12'd332 : mem_out_dec = 6'b000101;
12'd333 : mem_out_dec = 6'b000110;
12'd334 : mem_out_dec = 6'b000111;
12'd335 : mem_out_dec = 6'b001000;
12'd336 : mem_out_dec = 6'b000111;
12'd337 : mem_out_dec = 6'b000111;
12'd338 : mem_out_dec = 6'b000111;
12'd339 : mem_out_dec = 6'b000111;
12'd340 : mem_out_dec = 6'b000111;
12'd341 : mem_out_dec = 6'b000111;
12'd342 : mem_out_dec = 6'b001000;
12'd343 : mem_out_dec = 6'b001001;
12'd344 : mem_out_dec = 6'b001001;
12'd345 : mem_out_dec = 6'b001010;
12'd346 : mem_out_dec = 6'b001011;
12'd347 : mem_out_dec = 6'b001011;
12'd348 : mem_out_dec = 6'b001100;
12'd349 : mem_out_dec = 6'b001101;
12'd350 : mem_out_dec = 6'b001110;
12'd351 : mem_out_dec = 6'b001110;
12'd352 : mem_out_dec = 6'b001111;
12'd353 : mem_out_dec = 6'b001111;
12'd354 : mem_out_dec = 6'b010000;
12'd355 : mem_out_dec = 6'b010000;
12'd356 : mem_out_dec = 6'b010001;
12'd357 : mem_out_dec = 6'b010001;
12'd358 : mem_out_dec = 6'b010001;
12'd359 : mem_out_dec = 6'b010010;
12'd360 : mem_out_dec = 6'b010010;
12'd361 : mem_out_dec = 6'b010011;
12'd362 : mem_out_dec = 6'b010100;
12'd363 : mem_out_dec = 6'b010100;
12'd364 : mem_out_dec = 6'b010101;
12'd365 : mem_out_dec = 6'b010110;
12'd366 : mem_out_dec = 6'b010111;
12'd367 : mem_out_dec = 6'b011000;
12'd368 : mem_out_dec = 6'b010111;
12'd369 : mem_out_dec = 6'b010111;
12'd370 : mem_out_dec = 6'b010111;
12'd371 : mem_out_dec = 6'b010111;
12'd372 : mem_out_dec = 6'b010111;
12'd373 : mem_out_dec = 6'b010111;
12'd374 : mem_out_dec = 6'b011000;
12'd375 : mem_out_dec = 6'b011001;
12'd376 : mem_out_dec = 6'b011001;
12'd377 : mem_out_dec = 6'b011010;
12'd378 : mem_out_dec = 6'b011010;
12'd379 : mem_out_dec = 6'b011011;
12'd380 : mem_out_dec = 6'b011100;
12'd381 : mem_out_dec = 6'b011101;
12'd382 : mem_out_dec = 6'b011101;
12'd383 : mem_out_dec = 6'b011110;
12'd384 : mem_out_dec = 6'b111111;
12'd385 : mem_out_dec = 6'b111111;
12'd386 : mem_out_dec = 6'b111111;
12'd387 : mem_out_dec = 6'b111111;
12'd388 : mem_out_dec = 6'b111111;
12'd389 : mem_out_dec = 6'b111111;
12'd390 : mem_out_dec = 6'b111111;
12'd391 : mem_out_dec = 6'b111111;
12'd392 : mem_out_dec = 6'b111111;
12'd393 : mem_out_dec = 6'b111111;
12'd394 : mem_out_dec = 6'b111111;
12'd395 : mem_out_dec = 6'b111111;
12'd396 : mem_out_dec = 6'b000101;
12'd397 : mem_out_dec = 6'b000110;
12'd398 : mem_out_dec = 6'b000110;
12'd399 : mem_out_dec = 6'b000111;
12'd400 : mem_out_dec = 6'b000110;
12'd401 : mem_out_dec = 6'b000110;
12'd402 : mem_out_dec = 6'b000110;
12'd403 : mem_out_dec = 6'b000110;
12'd404 : mem_out_dec = 6'b000110;
12'd405 : mem_out_dec = 6'b000111;
12'd406 : mem_out_dec = 6'b001000;
12'd407 : mem_out_dec = 6'b001000;
12'd408 : mem_out_dec = 6'b001001;
12'd409 : mem_out_dec = 6'b001001;
12'd410 : mem_out_dec = 6'b001010;
12'd411 : mem_out_dec = 6'b001011;
12'd412 : mem_out_dec = 6'b001100;
12'd413 : mem_out_dec = 6'b001100;
12'd414 : mem_out_dec = 6'b001101;
12'd415 : mem_out_dec = 6'b001110;
12'd416 : mem_out_dec = 6'b001110;
12'd417 : mem_out_dec = 6'b001111;
12'd418 : mem_out_dec = 6'b001111;
12'd419 : mem_out_dec = 6'b010000;
12'd420 : mem_out_dec = 6'b010000;
12'd421 : mem_out_dec = 6'b010000;
12'd422 : mem_out_dec = 6'b010001;
12'd423 : mem_out_dec = 6'b010001;
12'd424 : mem_out_dec = 6'b010010;
12'd425 : mem_out_dec = 6'b010011;
12'd426 : mem_out_dec = 6'b010011;
12'd427 : mem_out_dec = 6'b010100;
12'd428 : mem_out_dec = 6'b010101;
12'd429 : mem_out_dec = 6'b010110;
12'd430 : mem_out_dec = 6'b010111;
12'd431 : mem_out_dec = 6'b010111;
12'd432 : mem_out_dec = 6'b010110;
12'd433 : mem_out_dec = 6'b010110;
12'd434 : mem_out_dec = 6'b010110;
12'd435 : mem_out_dec = 6'b010110;
12'd436 : mem_out_dec = 6'b010110;
12'd437 : mem_out_dec = 6'b010111;
12'd438 : mem_out_dec = 6'b010111;
12'd439 : mem_out_dec = 6'b011000;
12'd440 : mem_out_dec = 6'b011001;
12'd441 : mem_out_dec = 6'b011001;
12'd442 : mem_out_dec = 6'b011010;
12'd443 : mem_out_dec = 6'b011011;
12'd444 : mem_out_dec = 6'b011011;
12'd445 : mem_out_dec = 6'b011100;
12'd446 : mem_out_dec = 6'b011101;
12'd447 : mem_out_dec = 6'b011110;
12'd448 : mem_out_dec = 6'b111111;
12'd449 : mem_out_dec = 6'b111111;
12'd450 : mem_out_dec = 6'b111111;
12'd451 : mem_out_dec = 6'b111111;
12'd452 : mem_out_dec = 6'b111111;
12'd453 : mem_out_dec = 6'b111111;
12'd454 : mem_out_dec = 6'b111111;
12'd455 : mem_out_dec = 6'b111111;
12'd456 : mem_out_dec = 6'b111111;
12'd457 : mem_out_dec = 6'b111111;
12'd458 : mem_out_dec = 6'b111111;
12'd459 : mem_out_dec = 6'b111111;
12'd460 : mem_out_dec = 6'b111111;
12'd461 : mem_out_dec = 6'b000101;
12'd462 : mem_out_dec = 6'b000110;
12'd463 : mem_out_dec = 6'b000110;
12'd464 : mem_out_dec = 6'b000110;
12'd465 : mem_out_dec = 6'b000110;
12'd466 : mem_out_dec = 6'b000110;
12'd467 : mem_out_dec = 6'b000110;
12'd468 : mem_out_dec = 6'b000110;
12'd469 : mem_out_dec = 6'b000111;
12'd470 : mem_out_dec = 6'b000111;
12'd471 : mem_out_dec = 6'b001000;
12'd472 : mem_out_dec = 6'b001000;
12'd473 : mem_out_dec = 6'b001001;
12'd474 : mem_out_dec = 6'b001010;
12'd475 : mem_out_dec = 6'b001011;
12'd476 : mem_out_dec = 6'b001011;
12'd477 : mem_out_dec = 6'b001100;
12'd478 : mem_out_dec = 6'b001101;
12'd479 : mem_out_dec = 6'b001110;
12'd480 : mem_out_dec = 6'b001110;
12'd481 : mem_out_dec = 6'b001110;
12'd482 : mem_out_dec = 6'b001111;
12'd483 : mem_out_dec = 6'b001111;
12'd484 : mem_out_dec = 6'b010000;
12'd485 : mem_out_dec = 6'b010000;
12'd486 : mem_out_dec = 6'b010000;
12'd487 : mem_out_dec = 6'b010001;
12'd488 : mem_out_dec = 6'b010001;
12'd489 : mem_out_dec = 6'b010010;
12'd490 : mem_out_dec = 6'b010011;
12'd491 : mem_out_dec = 6'b010100;
12'd492 : mem_out_dec = 6'b010101;
12'd493 : mem_out_dec = 6'b010101;
12'd494 : mem_out_dec = 6'b010110;
12'd495 : mem_out_dec = 6'b010110;
12'd496 : mem_out_dec = 6'b010110;
12'd497 : mem_out_dec = 6'b010110;
12'd498 : mem_out_dec = 6'b010101;
12'd499 : mem_out_dec = 6'b010101;
12'd500 : mem_out_dec = 6'b010110;
12'd501 : mem_out_dec = 6'b010111;
12'd502 : mem_out_dec = 6'b010111;
12'd503 : mem_out_dec = 6'b011000;
12'd504 : mem_out_dec = 6'b011000;
12'd505 : mem_out_dec = 6'b011001;
12'd506 : mem_out_dec = 6'b011010;
12'd507 : mem_out_dec = 6'b011010;
12'd508 : mem_out_dec = 6'b011011;
12'd509 : mem_out_dec = 6'b011100;
12'd510 : mem_out_dec = 6'b011101;
12'd511 : mem_out_dec = 6'b011101;
12'd512 : mem_out_dec = 6'b111111;
12'd513 : mem_out_dec = 6'b111111;
12'd514 : mem_out_dec = 6'b111111;
12'd515 : mem_out_dec = 6'b111111;
12'd516 : mem_out_dec = 6'b111111;
12'd517 : mem_out_dec = 6'b111111;
12'd518 : mem_out_dec = 6'b111111;
12'd519 : mem_out_dec = 6'b111111;
12'd520 : mem_out_dec = 6'b111111;
12'd521 : mem_out_dec = 6'b111111;
12'd522 : mem_out_dec = 6'b111111;
12'd523 : mem_out_dec = 6'b111111;
12'd524 : mem_out_dec = 6'b111111;
12'd525 : mem_out_dec = 6'b111111;
12'd526 : mem_out_dec = 6'b000100;
12'd527 : mem_out_dec = 6'b000101;
12'd528 : mem_out_dec = 6'b000100;
12'd529 : mem_out_dec = 6'b000100;
12'd530 : mem_out_dec = 6'b000100;
12'd531 : mem_out_dec = 6'b000101;
12'd532 : mem_out_dec = 6'b000101;
12'd533 : mem_out_dec = 6'b000110;
12'd534 : mem_out_dec = 6'b000111;
12'd535 : mem_out_dec = 6'b000111;
12'd536 : mem_out_dec = 6'b000111;
12'd537 : mem_out_dec = 6'b001000;
12'd538 : mem_out_dec = 6'b001001;
12'd539 : mem_out_dec = 6'b001010;
12'd540 : mem_out_dec = 6'b001011;
12'd541 : mem_out_dec = 6'b001011;
12'd542 : mem_out_dec = 6'b001100;
12'd543 : mem_out_dec = 6'b001101;
12'd544 : mem_out_dec = 6'b001101;
12'd545 : mem_out_dec = 6'b001101;
12'd546 : mem_out_dec = 6'b001110;
12'd547 : mem_out_dec = 6'b001110;
12'd548 : mem_out_dec = 6'b001110;
12'd549 : mem_out_dec = 6'b001111;
12'd550 : mem_out_dec = 6'b010000;
12'd551 : mem_out_dec = 6'b010000;
12'd552 : mem_out_dec = 6'b010001;
12'd553 : mem_out_dec = 6'b010001;
12'd554 : mem_out_dec = 6'b010010;
12'd555 : mem_out_dec = 6'b010010;
12'd556 : mem_out_dec = 6'b010011;
12'd557 : mem_out_dec = 6'b010100;
12'd558 : mem_out_dec = 6'b010100;
12'd559 : mem_out_dec = 6'b010100;
12'd560 : mem_out_dec = 6'b010100;
12'd561 : mem_out_dec = 6'b010100;
12'd562 : mem_out_dec = 6'b010100;
12'd563 : mem_out_dec = 6'b010101;
12'd564 : mem_out_dec = 6'b010101;
12'd565 : mem_out_dec = 6'b010110;
12'd566 : mem_out_dec = 6'b010111;
12'd567 : mem_out_dec = 6'b010111;
12'd568 : mem_out_dec = 6'b010111;
12'd569 : mem_out_dec = 6'b011000;
12'd570 : mem_out_dec = 6'b011001;
12'd571 : mem_out_dec = 6'b011010;
12'd572 : mem_out_dec = 6'b011010;
12'd573 : mem_out_dec = 6'b011011;
12'd574 : mem_out_dec = 6'b011100;
12'd575 : mem_out_dec = 6'b011101;
12'd576 : mem_out_dec = 6'b111111;
12'd577 : mem_out_dec = 6'b111111;
12'd578 : mem_out_dec = 6'b111111;
12'd579 : mem_out_dec = 6'b111111;
12'd580 : mem_out_dec = 6'b111111;
12'd581 : mem_out_dec = 6'b111111;
12'd582 : mem_out_dec = 6'b111111;
12'd583 : mem_out_dec = 6'b111111;
12'd584 : mem_out_dec = 6'b111111;
12'd585 : mem_out_dec = 6'b111111;
12'd586 : mem_out_dec = 6'b111111;
12'd587 : mem_out_dec = 6'b111111;
12'd588 : mem_out_dec = 6'b111111;
12'd589 : mem_out_dec = 6'b111111;
12'd590 : mem_out_dec = 6'b111111;
12'd591 : mem_out_dec = 6'b000100;
12'd592 : mem_out_dec = 6'b000011;
12'd593 : mem_out_dec = 6'b000011;
12'd594 : mem_out_dec = 6'b000100;
12'd595 : mem_out_dec = 6'b000101;
12'd596 : mem_out_dec = 6'b000101;
12'd597 : mem_out_dec = 6'b000110;
12'd598 : mem_out_dec = 6'b000110;
12'd599 : mem_out_dec = 6'b000111;
12'd600 : mem_out_dec = 6'b000111;
12'd601 : mem_out_dec = 6'b001000;
12'd602 : mem_out_dec = 6'b001001;
12'd603 : mem_out_dec = 6'b001010;
12'd604 : mem_out_dec = 6'b001010;
12'd605 : mem_out_dec = 6'b001011;
12'd606 : mem_out_dec = 6'b001100;
12'd607 : mem_out_dec = 6'b001101;
12'd608 : mem_out_dec = 6'b001101;
12'd609 : mem_out_dec = 6'b001101;
12'd610 : mem_out_dec = 6'b001110;
12'd611 : mem_out_dec = 6'b001110;
12'd612 : mem_out_dec = 6'b001110;
12'd613 : mem_out_dec = 6'b001111;
12'd614 : mem_out_dec = 6'b010000;
12'd615 : mem_out_dec = 6'b010000;
12'd616 : mem_out_dec = 6'b010000;
12'd617 : mem_out_dec = 6'b010001;
12'd618 : mem_out_dec = 6'b010001;
12'd619 : mem_out_dec = 6'b010010;
12'd620 : mem_out_dec = 6'b010010;
12'd621 : mem_out_dec = 6'b010011;
12'd622 : mem_out_dec = 6'b010011;
12'd623 : mem_out_dec = 6'b010100;
12'd624 : mem_out_dec = 6'b010011;
12'd625 : mem_out_dec = 6'b010011;
12'd626 : mem_out_dec = 6'b010100;
12'd627 : mem_out_dec = 6'b010100;
12'd628 : mem_out_dec = 6'b010101;
12'd629 : mem_out_dec = 6'b010110;
12'd630 : mem_out_dec = 6'b010110;
12'd631 : mem_out_dec = 6'b010111;
12'd632 : mem_out_dec = 6'b010111;
12'd633 : mem_out_dec = 6'b011000;
12'd634 : mem_out_dec = 6'b011001;
12'd635 : mem_out_dec = 6'b011001;
12'd636 : mem_out_dec = 6'b011010;
12'd637 : mem_out_dec = 6'b011011;
12'd638 : mem_out_dec = 6'b011100;
12'd639 : mem_out_dec = 6'b011100;
12'd640 : mem_out_dec = 6'b111111;
12'd641 : mem_out_dec = 6'b111111;
12'd642 : mem_out_dec = 6'b111111;
12'd643 : mem_out_dec = 6'b111111;
12'd644 : mem_out_dec = 6'b111111;
12'd645 : mem_out_dec = 6'b111111;
12'd646 : mem_out_dec = 6'b111111;
12'd647 : mem_out_dec = 6'b111111;
12'd648 : mem_out_dec = 6'b111111;
12'd649 : mem_out_dec = 6'b111111;
12'd650 : mem_out_dec = 6'b111111;
12'd651 : mem_out_dec = 6'b111111;
12'd652 : mem_out_dec = 6'b111111;
12'd653 : mem_out_dec = 6'b111111;
12'd654 : mem_out_dec = 6'b111111;
12'd655 : mem_out_dec = 6'b111111;
12'd656 : mem_out_dec = 6'b000011;
12'd657 : mem_out_dec = 6'b000011;
12'd658 : mem_out_dec = 6'b000100;
12'd659 : mem_out_dec = 6'b000100;
12'd660 : mem_out_dec = 6'b000101;
12'd661 : mem_out_dec = 6'b000110;
12'd662 : mem_out_dec = 6'b000110;
12'd663 : mem_out_dec = 6'b000111;
12'd664 : mem_out_dec = 6'b000111;
12'd665 : mem_out_dec = 6'b001000;
12'd666 : mem_out_dec = 6'b001001;
12'd667 : mem_out_dec = 6'b001001;
12'd668 : mem_out_dec = 6'b001010;
12'd669 : mem_out_dec = 6'b001011;
12'd670 : mem_out_dec = 6'b001100;
12'd671 : mem_out_dec = 6'b001100;
12'd672 : mem_out_dec = 6'b001100;
12'd673 : mem_out_dec = 6'b001101;
12'd674 : mem_out_dec = 6'b001101;
12'd675 : mem_out_dec = 6'b001101;
12'd676 : mem_out_dec = 6'b001110;
12'd677 : mem_out_dec = 6'b001111;
12'd678 : mem_out_dec = 6'b001111;
12'd679 : mem_out_dec = 6'b010000;
12'd680 : mem_out_dec = 6'b010000;
12'd681 : mem_out_dec = 6'b010000;
12'd682 : mem_out_dec = 6'b010001;
12'd683 : mem_out_dec = 6'b010001;
12'd684 : mem_out_dec = 6'b010010;
12'd685 : mem_out_dec = 6'b010010;
12'd686 : mem_out_dec = 6'b010011;
12'd687 : mem_out_dec = 6'b010011;
12'd688 : mem_out_dec = 6'b010011;
12'd689 : mem_out_dec = 6'b010011;
12'd690 : mem_out_dec = 6'b010100;
12'd691 : mem_out_dec = 6'b010100;
12'd692 : mem_out_dec = 6'b010101;
12'd693 : mem_out_dec = 6'b010101;
12'd694 : mem_out_dec = 6'b010110;
12'd695 : mem_out_dec = 6'b010111;
12'd696 : mem_out_dec = 6'b010111;
12'd697 : mem_out_dec = 6'b011000;
12'd698 : mem_out_dec = 6'b011000;
12'd699 : mem_out_dec = 6'b011001;
12'd700 : mem_out_dec = 6'b011010;
12'd701 : mem_out_dec = 6'b011011;
12'd702 : mem_out_dec = 6'b011011;
12'd703 : mem_out_dec = 6'b011100;
12'd704 : mem_out_dec = 6'b111111;
12'd705 : mem_out_dec = 6'b111111;
12'd706 : mem_out_dec = 6'b111111;
12'd707 : mem_out_dec = 6'b111111;
12'd708 : mem_out_dec = 6'b111111;
12'd709 : mem_out_dec = 6'b111111;
12'd710 : mem_out_dec = 6'b111111;
12'd711 : mem_out_dec = 6'b111111;
12'd712 : mem_out_dec = 6'b111111;
12'd713 : mem_out_dec = 6'b111111;
12'd714 : mem_out_dec = 6'b111111;
12'd715 : mem_out_dec = 6'b111111;
12'd716 : mem_out_dec = 6'b111111;
12'd717 : mem_out_dec = 6'b111111;
12'd718 : mem_out_dec = 6'b111111;
12'd719 : mem_out_dec = 6'b111111;
12'd720 : mem_out_dec = 6'b111111;
12'd721 : mem_out_dec = 6'b000011;
12'd722 : mem_out_dec = 6'b000100;
12'd723 : mem_out_dec = 6'b000100;
12'd724 : mem_out_dec = 6'b000101;
12'd725 : mem_out_dec = 6'b000101;
12'd726 : mem_out_dec = 6'b000110;
12'd727 : mem_out_dec = 6'b000111;
12'd728 : mem_out_dec = 6'b000111;
12'd729 : mem_out_dec = 6'b000111;
12'd730 : mem_out_dec = 6'b001000;
12'd731 : mem_out_dec = 6'b001001;
12'd732 : mem_out_dec = 6'b001010;
12'd733 : mem_out_dec = 6'b001011;
12'd734 : mem_out_dec = 6'b001011;
12'd735 : mem_out_dec = 6'b001100;
12'd736 : mem_out_dec = 6'b001100;
12'd737 : mem_out_dec = 6'b001101;
12'd738 : mem_out_dec = 6'b001101;
12'd739 : mem_out_dec = 6'b001101;
12'd740 : mem_out_dec = 6'b001110;
12'd741 : mem_out_dec = 6'b001110;
12'd742 : mem_out_dec = 6'b001111;
12'd743 : mem_out_dec = 6'b010000;
12'd744 : mem_out_dec = 6'b001111;
12'd745 : mem_out_dec = 6'b010000;
12'd746 : mem_out_dec = 6'b010000;
12'd747 : mem_out_dec = 6'b010001;
12'd748 : mem_out_dec = 6'b010001;
12'd749 : mem_out_dec = 6'b010010;
12'd750 : mem_out_dec = 6'b010010;
12'd751 : mem_out_dec = 6'b010011;
12'd752 : mem_out_dec = 6'b010010;
12'd753 : mem_out_dec = 6'b010011;
12'd754 : mem_out_dec = 6'b010011;
12'd755 : mem_out_dec = 6'b010100;
12'd756 : mem_out_dec = 6'b010101;
12'd757 : mem_out_dec = 6'b010101;
12'd758 : mem_out_dec = 6'b010110;
12'd759 : mem_out_dec = 6'b010110;
12'd760 : mem_out_dec = 6'b010111;
12'd761 : mem_out_dec = 6'b010111;
12'd762 : mem_out_dec = 6'b011000;
12'd763 : mem_out_dec = 6'b011001;
12'd764 : mem_out_dec = 6'b011010;
12'd765 : mem_out_dec = 6'b011010;
12'd766 : mem_out_dec = 6'b011011;
12'd767 : mem_out_dec = 6'b011100;
12'd768 : mem_out_dec = 6'b111111;
12'd769 : mem_out_dec = 6'b111111;
12'd770 : mem_out_dec = 6'b111111;
12'd771 : mem_out_dec = 6'b111111;
12'd772 : mem_out_dec = 6'b111111;
12'd773 : mem_out_dec = 6'b111111;
12'd774 : mem_out_dec = 6'b111111;
12'd775 : mem_out_dec = 6'b111111;
12'd776 : mem_out_dec = 6'b111111;
12'd777 : mem_out_dec = 6'b111111;
12'd778 : mem_out_dec = 6'b111111;
12'd779 : mem_out_dec = 6'b111111;
12'd780 : mem_out_dec = 6'b111111;
12'd781 : mem_out_dec = 6'b111111;
12'd782 : mem_out_dec = 6'b111111;
12'd783 : mem_out_dec = 6'b111111;
12'd784 : mem_out_dec = 6'b111111;
12'd785 : mem_out_dec = 6'b111111;
12'd786 : mem_out_dec = 6'b000011;
12'd787 : mem_out_dec = 6'b000100;
12'd788 : mem_out_dec = 6'b000101;
12'd789 : mem_out_dec = 6'b000101;
12'd790 : mem_out_dec = 6'b000110;
12'd791 : mem_out_dec = 6'b000110;
12'd792 : mem_out_dec = 6'b000110;
12'd793 : mem_out_dec = 6'b000111;
12'd794 : mem_out_dec = 6'b001000;
12'd795 : mem_out_dec = 6'b001001;
12'd796 : mem_out_dec = 6'b001010;
12'd797 : mem_out_dec = 6'b001010;
12'd798 : mem_out_dec = 6'b001011;
12'd799 : mem_out_dec = 6'b001100;
12'd800 : mem_out_dec = 6'b001100;
12'd801 : mem_out_dec = 6'b001100;
12'd802 : mem_out_dec = 6'b001101;
12'd803 : mem_out_dec = 6'b001101;
12'd804 : mem_out_dec = 6'b001110;
12'd805 : mem_out_dec = 6'b001110;
12'd806 : mem_out_dec = 6'b001111;
12'd807 : mem_out_dec = 6'b010000;
12'd808 : mem_out_dec = 6'b001111;
12'd809 : mem_out_dec = 6'b001111;
12'd810 : mem_out_dec = 6'b010000;
12'd811 : mem_out_dec = 6'b010000;
12'd812 : mem_out_dec = 6'b010001;
12'd813 : mem_out_dec = 6'b010001;
12'd814 : mem_out_dec = 6'b010010;
12'd815 : mem_out_dec = 6'b010010;
12'd816 : mem_out_dec = 6'b010010;
12'd817 : mem_out_dec = 6'b010011;
12'd818 : mem_out_dec = 6'b010011;
12'd819 : mem_out_dec = 6'b010100;
12'd820 : mem_out_dec = 6'b010100;
12'd821 : mem_out_dec = 6'b010101;
12'd822 : mem_out_dec = 6'b010110;
12'd823 : mem_out_dec = 6'b010110;
12'd824 : mem_out_dec = 6'b010110;
12'd825 : mem_out_dec = 6'b010111;
12'd826 : mem_out_dec = 6'b011000;
12'd827 : mem_out_dec = 6'b011001;
12'd828 : mem_out_dec = 6'b011001;
12'd829 : mem_out_dec = 6'b011010;
12'd830 : mem_out_dec = 6'b011011;
12'd831 : mem_out_dec = 6'b011100;
12'd832 : mem_out_dec = 6'b111111;
12'd833 : mem_out_dec = 6'b111111;
12'd834 : mem_out_dec = 6'b111111;
12'd835 : mem_out_dec = 6'b111111;
12'd836 : mem_out_dec = 6'b111111;
12'd837 : mem_out_dec = 6'b111111;
12'd838 : mem_out_dec = 6'b111111;
12'd839 : mem_out_dec = 6'b111111;
12'd840 : mem_out_dec = 6'b111111;
12'd841 : mem_out_dec = 6'b111111;
12'd842 : mem_out_dec = 6'b111111;
12'd843 : mem_out_dec = 6'b111111;
12'd844 : mem_out_dec = 6'b111111;
12'd845 : mem_out_dec = 6'b111111;
12'd846 : mem_out_dec = 6'b111111;
12'd847 : mem_out_dec = 6'b111111;
12'd848 : mem_out_dec = 6'b111111;
12'd849 : mem_out_dec = 6'b111111;
12'd850 : mem_out_dec = 6'b111111;
12'd851 : mem_out_dec = 6'b000100;
12'd852 : mem_out_dec = 6'b000100;
12'd853 : mem_out_dec = 6'b000101;
12'd854 : mem_out_dec = 6'b000101;
12'd855 : mem_out_dec = 6'b000110;
12'd856 : mem_out_dec = 6'b000110;
12'd857 : mem_out_dec = 6'b000111;
12'd858 : mem_out_dec = 6'b001000;
12'd859 : mem_out_dec = 6'b001001;
12'd860 : mem_out_dec = 6'b001001;
12'd861 : mem_out_dec = 6'b001010;
12'd862 : mem_out_dec = 6'b001011;
12'd863 : mem_out_dec = 6'b001100;
12'd864 : mem_out_dec = 6'b001100;
12'd865 : mem_out_dec = 6'b001100;
12'd866 : mem_out_dec = 6'b001100;
12'd867 : mem_out_dec = 6'b001101;
12'd868 : mem_out_dec = 6'b001101;
12'd869 : mem_out_dec = 6'b001110;
12'd870 : mem_out_dec = 6'b001111;
12'd871 : mem_out_dec = 6'b001111;
12'd872 : mem_out_dec = 6'b001110;
12'd873 : mem_out_dec = 6'b001111;
12'd874 : mem_out_dec = 6'b001111;
12'd875 : mem_out_dec = 6'b010000;
12'd876 : mem_out_dec = 6'b010000;
12'd877 : mem_out_dec = 6'b010001;
12'd878 : mem_out_dec = 6'b010001;
12'd879 : mem_out_dec = 6'b010010;
12'd880 : mem_out_dec = 6'b010010;
12'd881 : mem_out_dec = 6'b010010;
12'd882 : mem_out_dec = 6'b010011;
12'd883 : mem_out_dec = 6'b010100;
12'd884 : mem_out_dec = 6'b010100;
12'd885 : mem_out_dec = 6'b010101;
12'd886 : mem_out_dec = 6'b010101;
12'd887 : mem_out_dec = 6'b010110;
12'd888 : mem_out_dec = 6'b010110;
12'd889 : mem_out_dec = 6'b010111;
12'd890 : mem_out_dec = 6'b011000;
12'd891 : mem_out_dec = 6'b011000;
12'd892 : mem_out_dec = 6'b011001;
12'd893 : mem_out_dec = 6'b011010;
12'd894 : mem_out_dec = 6'b011011;
12'd895 : mem_out_dec = 6'b011011;
12'd896 : mem_out_dec = 6'b111111;
12'd897 : mem_out_dec = 6'b111111;
12'd898 : mem_out_dec = 6'b111111;
12'd899 : mem_out_dec = 6'b111111;
12'd900 : mem_out_dec = 6'b111111;
12'd901 : mem_out_dec = 6'b111111;
12'd902 : mem_out_dec = 6'b111111;
12'd903 : mem_out_dec = 6'b111111;
12'd904 : mem_out_dec = 6'b111111;
12'd905 : mem_out_dec = 6'b111111;
12'd906 : mem_out_dec = 6'b111111;
12'd907 : mem_out_dec = 6'b111111;
12'd908 : mem_out_dec = 6'b111111;
12'd909 : mem_out_dec = 6'b111111;
12'd910 : mem_out_dec = 6'b111111;
12'd911 : mem_out_dec = 6'b111111;
12'd912 : mem_out_dec = 6'b111111;
12'd913 : mem_out_dec = 6'b111111;
12'd914 : mem_out_dec = 6'b111111;
12'd915 : mem_out_dec = 6'b111111;
12'd916 : mem_out_dec = 6'b000100;
12'd917 : mem_out_dec = 6'b000101;
12'd918 : mem_out_dec = 6'b000101;
12'd919 : mem_out_dec = 6'b000110;
12'd920 : mem_out_dec = 6'b000110;
12'd921 : mem_out_dec = 6'b000111;
12'd922 : mem_out_dec = 6'b001000;
12'd923 : mem_out_dec = 6'b001000;
12'd924 : mem_out_dec = 6'b001001;
12'd925 : mem_out_dec = 6'b001010;
12'd926 : mem_out_dec = 6'b001011;
12'd927 : mem_out_dec = 6'b001011;
12'd928 : mem_out_dec = 6'b001011;
12'd929 : mem_out_dec = 6'b001100;
12'd930 : mem_out_dec = 6'b001100;
12'd931 : mem_out_dec = 6'b001101;
12'd932 : mem_out_dec = 6'b001101;
12'd933 : mem_out_dec = 6'b001110;
12'd934 : mem_out_dec = 6'b001110;
12'd935 : mem_out_dec = 6'b001111;
12'd936 : mem_out_dec = 6'b001110;
12'd937 : mem_out_dec = 6'b001110;
12'd938 : mem_out_dec = 6'b001111;
12'd939 : mem_out_dec = 6'b001111;
12'd940 : mem_out_dec = 6'b010000;
12'd941 : mem_out_dec = 6'b010000;
12'd942 : mem_out_dec = 6'b010001;
12'd943 : mem_out_dec = 6'b010001;
12'd944 : mem_out_dec = 6'b010010;
12'd945 : mem_out_dec = 6'b010010;
12'd946 : mem_out_dec = 6'b010011;
12'd947 : mem_out_dec = 6'b010011;
12'd948 : mem_out_dec = 6'b010100;
12'd949 : mem_out_dec = 6'b010100;
12'd950 : mem_out_dec = 6'b010101;
12'd951 : mem_out_dec = 6'b010110;
12'd952 : mem_out_dec = 6'b010110;
12'd953 : mem_out_dec = 6'b010111;
12'd954 : mem_out_dec = 6'b010111;
12'd955 : mem_out_dec = 6'b011000;
12'd956 : mem_out_dec = 6'b011001;
12'd957 : mem_out_dec = 6'b011010;
12'd958 : mem_out_dec = 6'b011010;
12'd959 : mem_out_dec = 6'b011011;
12'd960 : mem_out_dec = 6'b111111;
12'd961 : mem_out_dec = 6'b111111;
12'd962 : mem_out_dec = 6'b111111;
12'd963 : mem_out_dec = 6'b111111;
12'd964 : mem_out_dec = 6'b111111;
12'd965 : mem_out_dec = 6'b111111;
12'd966 : mem_out_dec = 6'b111111;
12'd967 : mem_out_dec = 6'b111111;
12'd968 : mem_out_dec = 6'b111111;
12'd969 : mem_out_dec = 6'b111111;
12'd970 : mem_out_dec = 6'b111111;
12'd971 : mem_out_dec = 6'b111111;
12'd972 : mem_out_dec = 6'b111111;
12'd973 : mem_out_dec = 6'b111111;
12'd974 : mem_out_dec = 6'b111111;
12'd975 : mem_out_dec = 6'b111111;
12'd976 : mem_out_dec = 6'b111111;
12'd977 : mem_out_dec = 6'b111111;
12'd978 : mem_out_dec = 6'b111111;
12'd979 : mem_out_dec = 6'b111111;
12'd980 : mem_out_dec = 6'b111111;
12'd981 : mem_out_dec = 6'b000100;
12'd982 : mem_out_dec = 6'b000101;
12'd983 : mem_out_dec = 6'b000110;
12'd984 : mem_out_dec = 6'b000110;
12'd985 : mem_out_dec = 6'b000111;
12'd986 : mem_out_dec = 6'b000111;
12'd987 : mem_out_dec = 6'b001000;
12'd988 : mem_out_dec = 6'b001001;
12'd989 : mem_out_dec = 6'b001010;
12'd990 : mem_out_dec = 6'b001010;
12'd991 : mem_out_dec = 6'b001011;
12'd992 : mem_out_dec = 6'b001011;
12'd993 : mem_out_dec = 6'b001011;
12'd994 : mem_out_dec = 6'b001100;
12'd995 : mem_out_dec = 6'b001100;
12'd996 : mem_out_dec = 6'b001101;
12'd997 : mem_out_dec = 6'b001110;
12'd998 : mem_out_dec = 6'b001110;
12'd999 : mem_out_dec = 6'b001110;
12'd1000 : mem_out_dec = 6'b001101;
12'd1001 : mem_out_dec = 6'b001110;
12'd1002 : mem_out_dec = 6'b001110;
12'd1003 : mem_out_dec = 6'b001111;
12'd1004 : mem_out_dec = 6'b001111;
12'd1005 : mem_out_dec = 6'b010000;
12'd1006 : mem_out_dec = 6'b010000;
12'd1007 : mem_out_dec = 6'b010001;
12'd1008 : mem_out_dec = 6'b010001;
12'd1009 : mem_out_dec = 6'b010010;
12'd1010 : mem_out_dec = 6'b010011;
12'd1011 : mem_out_dec = 6'b010011;
12'd1012 : mem_out_dec = 6'b010100;
12'd1013 : mem_out_dec = 6'b010100;
12'd1014 : mem_out_dec = 6'b010101;
12'd1015 : mem_out_dec = 6'b010110;
12'd1016 : mem_out_dec = 6'b010110;
12'd1017 : mem_out_dec = 6'b010110;
12'd1018 : mem_out_dec = 6'b010111;
12'd1019 : mem_out_dec = 6'b011000;
12'd1020 : mem_out_dec = 6'b011001;
12'd1021 : mem_out_dec = 6'b011001;
12'd1022 : mem_out_dec = 6'b011010;
12'd1023 : mem_out_dec = 6'b011011;
12'd1024 : mem_out_dec = 6'b111111;
12'd1025 : mem_out_dec = 6'b111111;
12'd1026 : mem_out_dec = 6'b111111;
12'd1027 : mem_out_dec = 6'b111111;
12'd1028 : mem_out_dec = 6'b111111;
12'd1029 : mem_out_dec = 6'b111111;
12'd1030 : mem_out_dec = 6'b111111;
12'd1031 : mem_out_dec = 6'b111111;
12'd1032 : mem_out_dec = 6'b111111;
12'd1033 : mem_out_dec = 6'b111111;
12'd1034 : mem_out_dec = 6'b111111;
12'd1035 : mem_out_dec = 6'b111111;
12'd1036 : mem_out_dec = 6'b111111;
12'd1037 : mem_out_dec = 6'b111111;
12'd1038 : mem_out_dec = 6'b111111;
12'd1039 : mem_out_dec = 6'b111111;
12'd1040 : mem_out_dec = 6'b111111;
12'd1041 : mem_out_dec = 6'b111111;
12'd1042 : mem_out_dec = 6'b111111;
12'd1043 : mem_out_dec = 6'b111111;
12'd1044 : mem_out_dec = 6'b111111;
12'd1045 : mem_out_dec = 6'b111111;
12'd1046 : mem_out_dec = 6'b000100;
12'd1047 : mem_out_dec = 6'b000101;
12'd1048 : mem_out_dec = 6'b000101;
12'd1049 : mem_out_dec = 6'b000110;
12'd1050 : mem_out_dec = 6'b000110;
12'd1051 : mem_out_dec = 6'b000111;
12'd1052 : mem_out_dec = 6'b001000;
12'd1053 : mem_out_dec = 6'b001001;
12'd1054 : mem_out_dec = 6'b001001;
12'd1055 : mem_out_dec = 6'b001010;
12'd1056 : mem_out_dec = 6'b001010;
12'd1057 : mem_out_dec = 6'b001011;
12'd1058 : mem_out_dec = 6'b001011;
12'd1059 : mem_out_dec = 6'b001100;
12'd1060 : mem_out_dec = 6'b001100;
12'd1061 : mem_out_dec = 6'b001100;
12'd1062 : mem_out_dec = 6'b001100;
12'd1063 : mem_out_dec = 6'b001100;
12'd1064 : mem_out_dec = 6'b001100;
12'd1065 : mem_out_dec = 6'b001100;
12'd1066 : mem_out_dec = 6'b001101;
12'd1067 : mem_out_dec = 6'b001101;
12'd1068 : mem_out_dec = 6'b001110;
12'd1069 : mem_out_dec = 6'b001111;
12'd1070 : mem_out_dec = 6'b010000;
12'd1071 : mem_out_dec = 6'b010000;
12'd1072 : mem_out_dec = 6'b010001;
12'd1073 : mem_out_dec = 6'b010001;
12'd1074 : mem_out_dec = 6'b010010;
12'd1075 : mem_out_dec = 6'b010010;
12'd1076 : mem_out_dec = 6'b010011;
12'd1077 : mem_out_dec = 6'b010011;
12'd1078 : mem_out_dec = 6'b010100;
12'd1079 : mem_out_dec = 6'b010101;
12'd1080 : mem_out_dec = 6'b010101;
12'd1081 : mem_out_dec = 6'b010110;
12'd1082 : mem_out_dec = 6'b010110;
12'd1083 : mem_out_dec = 6'b010111;
12'd1084 : mem_out_dec = 6'b011000;
12'd1085 : mem_out_dec = 6'b011000;
12'd1086 : mem_out_dec = 6'b011001;
12'd1087 : mem_out_dec = 6'b011010;
12'd1088 : mem_out_dec = 6'b111111;
12'd1089 : mem_out_dec = 6'b111111;
12'd1090 : mem_out_dec = 6'b111111;
12'd1091 : mem_out_dec = 6'b111111;
12'd1092 : mem_out_dec = 6'b111111;
12'd1093 : mem_out_dec = 6'b111111;
12'd1094 : mem_out_dec = 6'b111111;
12'd1095 : mem_out_dec = 6'b111111;
12'd1096 : mem_out_dec = 6'b111111;
12'd1097 : mem_out_dec = 6'b111111;
12'd1098 : mem_out_dec = 6'b111111;
12'd1099 : mem_out_dec = 6'b111111;
12'd1100 : mem_out_dec = 6'b111111;
12'd1101 : mem_out_dec = 6'b111111;
12'd1102 : mem_out_dec = 6'b111111;
12'd1103 : mem_out_dec = 6'b111111;
12'd1104 : mem_out_dec = 6'b111111;
12'd1105 : mem_out_dec = 6'b111111;
12'd1106 : mem_out_dec = 6'b111111;
12'd1107 : mem_out_dec = 6'b111111;
12'd1108 : mem_out_dec = 6'b111111;
12'd1109 : mem_out_dec = 6'b111111;
12'd1110 : mem_out_dec = 6'b111111;
12'd1111 : mem_out_dec = 6'b000100;
12'd1112 : mem_out_dec = 6'b000100;
12'd1113 : mem_out_dec = 6'b000101;
12'd1114 : mem_out_dec = 6'b000110;
12'd1115 : mem_out_dec = 6'b000111;
12'd1116 : mem_out_dec = 6'b000111;
12'd1117 : mem_out_dec = 6'b001000;
12'd1118 : mem_out_dec = 6'b001001;
12'd1119 : mem_out_dec = 6'b001001;
12'd1120 : mem_out_dec = 6'b001010;
12'd1121 : mem_out_dec = 6'b001010;
12'd1122 : mem_out_dec = 6'b001011;
12'd1123 : mem_out_dec = 6'b001011;
12'd1124 : mem_out_dec = 6'b001011;
12'd1125 : mem_out_dec = 6'b001011;
12'd1126 : mem_out_dec = 6'b001011;
12'd1127 : mem_out_dec = 6'b001011;
12'd1128 : mem_out_dec = 6'b001011;
12'd1129 : mem_out_dec = 6'b001011;
12'd1130 : mem_out_dec = 6'b001100;
12'd1131 : mem_out_dec = 6'b001101;
12'd1132 : mem_out_dec = 6'b001110;
12'd1133 : mem_out_dec = 6'b001110;
12'd1134 : mem_out_dec = 6'b001111;
12'd1135 : mem_out_dec = 6'b010000;
12'd1136 : mem_out_dec = 6'b010000;
12'd1137 : mem_out_dec = 6'b010001;
12'd1138 : mem_out_dec = 6'b010001;
12'd1139 : mem_out_dec = 6'b010010;
12'd1140 : mem_out_dec = 6'b010010;
12'd1141 : mem_out_dec = 6'b010011;
12'd1142 : mem_out_dec = 6'b010100;
12'd1143 : mem_out_dec = 6'b010100;
12'd1144 : mem_out_dec = 6'b010100;
12'd1145 : mem_out_dec = 6'b010101;
12'd1146 : mem_out_dec = 6'b010110;
12'd1147 : mem_out_dec = 6'b010110;
12'd1148 : mem_out_dec = 6'b010111;
12'd1149 : mem_out_dec = 6'b011000;
12'd1150 : mem_out_dec = 6'b011000;
12'd1151 : mem_out_dec = 6'b011001;
12'd1152 : mem_out_dec = 6'b111111;
12'd1153 : mem_out_dec = 6'b111111;
12'd1154 : mem_out_dec = 6'b111111;
12'd1155 : mem_out_dec = 6'b111111;
12'd1156 : mem_out_dec = 6'b111111;
12'd1157 : mem_out_dec = 6'b111111;
12'd1158 : mem_out_dec = 6'b111111;
12'd1159 : mem_out_dec = 6'b111111;
12'd1160 : mem_out_dec = 6'b111111;
12'd1161 : mem_out_dec = 6'b111111;
12'd1162 : mem_out_dec = 6'b111111;
12'd1163 : mem_out_dec = 6'b111111;
12'd1164 : mem_out_dec = 6'b111111;
12'd1165 : mem_out_dec = 6'b111111;
12'd1166 : mem_out_dec = 6'b111111;
12'd1167 : mem_out_dec = 6'b111111;
12'd1168 : mem_out_dec = 6'b111111;
12'd1169 : mem_out_dec = 6'b111111;
12'd1170 : mem_out_dec = 6'b111111;
12'd1171 : mem_out_dec = 6'b111111;
12'd1172 : mem_out_dec = 6'b111111;
12'd1173 : mem_out_dec = 6'b111111;
12'd1174 : mem_out_dec = 6'b111111;
12'd1175 : mem_out_dec = 6'b111111;
12'd1176 : mem_out_dec = 6'b000100;
12'd1177 : mem_out_dec = 6'b000101;
12'd1178 : mem_out_dec = 6'b000101;
12'd1179 : mem_out_dec = 6'b000110;
12'd1180 : mem_out_dec = 6'b000111;
12'd1181 : mem_out_dec = 6'b000111;
12'd1182 : mem_out_dec = 6'b001000;
12'd1183 : mem_out_dec = 6'b001001;
12'd1184 : mem_out_dec = 6'b001001;
12'd1185 : mem_out_dec = 6'b001010;
12'd1186 : mem_out_dec = 6'b001010;
12'd1187 : mem_out_dec = 6'b001010;
12'd1188 : mem_out_dec = 6'b001010;
12'd1189 : mem_out_dec = 6'b001010;
12'd1190 : mem_out_dec = 6'b001010;
12'd1191 : mem_out_dec = 6'b001010;
12'd1192 : mem_out_dec = 6'b001010;
12'd1193 : mem_out_dec = 6'b001011;
12'd1194 : mem_out_dec = 6'b001100;
12'd1195 : mem_out_dec = 6'b001100;
12'd1196 : mem_out_dec = 6'b001101;
12'd1197 : mem_out_dec = 6'b001110;
12'd1198 : mem_out_dec = 6'b001111;
12'd1199 : mem_out_dec = 6'b010000;
12'd1200 : mem_out_dec = 6'b010000;
12'd1201 : mem_out_dec = 6'b010000;
12'd1202 : mem_out_dec = 6'b010001;
12'd1203 : mem_out_dec = 6'b010001;
12'd1204 : mem_out_dec = 6'b010010;
12'd1205 : mem_out_dec = 6'b010011;
12'd1206 : mem_out_dec = 6'b010011;
12'd1207 : mem_out_dec = 6'b010100;
12'd1208 : mem_out_dec = 6'b010100;
12'd1209 : mem_out_dec = 6'b010100;
12'd1210 : mem_out_dec = 6'b010101;
12'd1211 : mem_out_dec = 6'b010110;
12'd1212 : mem_out_dec = 6'b010110;
12'd1213 : mem_out_dec = 6'b010111;
12'd1214 : mem_out_dec = 6'b011000;
12'd1215 : mem_out_dec = 6'b011001;
12'd1216 : mem_out_dec = 6'b111111;
12'd1217 : mem_out_dec = 6'b111111;
12'd1218 : mem_out_dec = 6'b111111;
12'd1219 : mem_out_dec = 6'b111111;
12'd1220 : mem_out_dec = 6'b111111;
12'd1221 : mem_out_dec = 6'b111111;
12'd1222 : mem_out_dec = 6'b111111;
12'd1223 : mem_out_dec = 6'b111111;
12'd1224 : mem_out_dec = 6'b111111;
12'd1225 : mem_out_dec = 6'b111111;
12'd1226 : mem_out_dec = 6'b111111;
12'd1227 : mem_out_dec = 6'b111111;
12'd1228 : mem_out_dec = 6'b111111;
12'd1229 : mem_out_dec = 6'b111111;
12'd1230 : mem_out_dec = 6'b111111;
12'd1231 : mem_out_dec = 6'b111111;
12'd1232 : mem_out_dec = 6'b111111;
12'd1233 : mem_out_dec = 6'b111111;
12'd1234 : mem_out_dec = 6'b111111;
12'd1235 : mem_out_dec = 6'b111111;
12'd1236 : mem_out_dec = 6'b111111;
12'd1237 : mem_out_dec = 6'b111111;
12'd1238 : mem_out_dec = 6'b111111;
12'd1239 : mem_out_dec = 6'b111111;
12'd1240 : mem_out_dec = 6'b111111;
12'd1241 : mem_out_dec = 6'b000100;
12'd1242 : mem_out_dec = 6'b000100;
12'd1243 : mem_out_dec = 6'b000101;
12'd1244 : mem_out_dec = 6'b000110;
12'd1245 : mem_out_dec = 6'b000111;
12'd1246 : mem_out_dec = 6'b001000;
12'd1247 : mem_out_dec = 6'b001000;
12'd1248 : mem_out_dec = 6'b001001;
12'd1249 : mem_out_dec = 6'b001001;
12'd1250 : mem_out_dec = 6'b001001;
12'd1251 : mem_out_dec = 6'b001001;
12'd1252 : mem_out_dec = 6'b001001;
12'd1253 : mem_out_dec = 6'b001001;
12'd1254 : mem_out_dec = 6'b001001;
12'd1255 : mem_out_dec = 6'b001001;
12'd1256 : mem_out_dec = 6'b001010;
12'd1257 : mem_out_dec = 6'b001010;
12'd1258 : mem_out_dec = 6'b001011;
12'd1259 : mem_out_dec = 6'b001100;
12'd1260 : mem_out_dec = 6'b001101;
12'd1261 : mem_out_dec = 6'b001110;
12'd1262 : mem_out_dec = 6'b001110;
12'd1263 : mem_out_dec = 6'b001111;
12'd1264 : mem_out_dec = 6'b001111;
12'd1265 : mem_out_dec = 6'b010000;
12'd1266 : mem_out_dec = 6'b010000;
12'd1267 : mem_out_dec = 6'b010001;
12'd1268 : mem_out_dec = 6'b010001;
12'd1269 : mem_out_dec = 6'b010010;
12'd1270 : mem_out_dec = 6'b010011;
12'd1271 : mem_out_dec = 6'b010011;
12'd1272 : mem_out_dec = 6'b010011;
12'd1273 : mem_out_dec = 6'b010100;
12'd1274 : mem_out_dec = 6'b010100;
12'd1275 : mem_out_dec = 6'b010101;
12'd1276 : mem_out_dec = 6'b010110;
12'd1277 : mem_out_dec = 6'b010111;
12'd1278 : mem_out_dec = 6'b011000;
12'd1279 : mem_out_dec = 6'b011000;
12'd1280 : mem_out_dec = 6'b111111;
12'd1281 : mem_out_dec = 6'b111111;
12'd1282 : mem_out_dec = 6'b111111;
12'd1283 : mem_out_dec = 6'b111111;
12'd1284 : mem_out_dec = 6'b111111;
12'd1285 : mem_out_dec = 6'b111111;
12'd1286 : mem_out_dec = 6'b111111;
12'd1287 : mem_out_dec = 6'b111111;
12'd1288 : mem_out_dec = 6'b111111;
12'd1289 : mem_out_dec = 6'b111111;
12'd1290 : mem_out_dec = 6'b111111;
12'd1291 : mem_out_dec = 6'b111111;
12'd1292 : mem_out_dec = 6'b111111;
12'd1293 : mem_out_dec = 6'b111111;
12'd1294 : mem_out_dec = 6'b111111;
12'd1295 : mem_out_dec = 6'b111111;
12'd1296 : mem_out_dec = 6'b111111;
12'd1297 : mem_out_dec = 6'b111111;
12'd1298 : mem_out_dec = 6'b111111;
12'd1299 : mem_out_dec = 6'b111111;
12'd1300 : mem_out_dec = 6'b111111;
12'd1301 : mem_out_dec = 6'b111111;
12'd1302 : mem_out_dec = 6'b111111;
12'd1303 : mem_out_dec = 6'b111111;
12'd1304 : mem_out_dec = 6'b111111;
12'd1305 : mem_out_dec = 6'b111111;
12'd1306 : mem_out_dec = 6'b000100;
12'd1307 : mem_out_dec = 6'b000101;
12'd1308 : mem_out_dec = 6'b000110;
12'd1309 : mem_out_dec = 6'b000110;
12'd1310 : mem_out_dec = 6'b000111;
12'd1311 : mem_out_dec = 6'b001000;
12'd1312 : mem_out_dec = 6'b001000;
12'd1313 : mem_out_dec = 6'b001000;
12'd1314 : mem_out_dec = 6'b001000;
12'd1315 : mem_out_dec = 6'b001000;
12'd1316 : mem_out_dec = 6'b001000;
12'd1317 : mem_out_dec = 6'b001000;
12'd1318 : mem_out_dec = 6'b001000;
12'd1319 : mem_out_dec = 6'b001001;
12'd1320 : mem_out_dec = 6'b001001;
12'd1321 : mem_out_dec = 6'b001010;
12'd1322 : mem_out_dec = 6'b001011;
12'd1323 : mem_out_dec = 6'b001100;
12'd1324 : mem_out_dec = 6'b001100;
12'd1325 : mem_out_dec = 6'b001101;
12'd1326 : mem_out_dec = 6'b001110;
12'd1327 : mem_out_dec = 6'b001111;
12'd1328 : mem_out_dec = 6'b001111;
12'd1329 : mem_out_dec = 6'b001111;
12'd1330 : mem_out_dec = 6'b010000;
12'd1331 : mem_out_dec = 6'b010000;
12'd1332 : mem_out_dec = 6'b010001;
12'd1333 : mem_out_dec = 6'b010001;
12'd1334 : mem_out_dec = 6'b010010;
12'd1335 : mem_out_dec = 6'b010011;
12'd1336 : mem_out_dec = 6'b010010;
12'd1337 : mem_out_dec = 6'b010011;
12'd1338 : mem_out_dec = 6'b010100;
12'd1339 : mem_out_dec = 6'b010101;
12'd1340 : mem_out_dec = 6'b010110;
12'd1341 : mem_out_dec = 6'b010110;
12'd1342 : mem_out_dec = 6'b010111;
12'd1343 : mem_out_dec = 6'b011000;
12'd1344 : mem_out_dec = 6'b111111;
12'd1345 : mem_out_dec = 6'b111111;
12'd1346 : mem_out_dec = 6'b111111;
12'd1347 : mem_out_dec = 6'b111111;
12'd1348 : mem_out_dec = 6'b111111;
12'd1349 : mem_out_dec = 6'b111111;
12'd1350 : mem_out_dec = 6'b111111;
12'd1351 : mem_out_dec = 6'b111111;
12'd1352 : mem_out_dec = 6'b111111;
12'd1353 : mem_out_dec = 6'b111111;
12'd1354 : mem_out_dec = 6'b111111;
12'd1355 : mem_out_dec = 6'b111111;
12'd1356 : mem_out_dec = 6'b111111;
12'd1357 : mem_out_dec = 6'b111111;
12'd1358 : mem_out_dec = 6'b111111;
12'd1359 : mem_out_dec = 6'b111111;
12'd1360 : mem_out_dec = 6'b111111;
12'd1361 : mem_out_dec = 6'b111111;
12'd1362 : mem_out_dec = 6'b111111;
12'd1363 : mem_out_dec = 6'b111111;
12'd1364 : mem_out_dec = 6'b111111;
12'd1365 : mem_out_dec = 6'b111111;
12'd1366 : mem_out_dec = 6'b111111;
12'd1367 : mem_out_dec = 6'b111111;
12'd1368 : mem_out_dec = 6'b111111;
12'd1369 : mem_out_dec = 6'b111111;
12'd1370 : mem_out_dec = 6'b111111;
12'd1371 : mem_out_dec = 6'b000101;
12'd1372 : mem_out_dec = 6'b000101;
12'd1373 : mem_out_dec = 6'b000110;
12'd1374 : mem_out_dec = 6'b000111;
12'd1375 : mem_out_dec = 6'b001000;
12'd1376 : mem_out_dec = 6'b000111;
12'd1377 : mem_out_dec = 6'b000111;
12'd1378 : mem_out_dec = 6'b000111;
12'd1379 : mem_out_dec = 6'b000111;
12'd1380 : mem_out_dec = 6'b000111;
12'd1381 : mem_out_dec = 6'b000111;
12'd1382 : mem_out_dec = 6'b001000;
12'd1383 : mem_out_dec = 6'b001001;
12'd1384 : mem_out_dec = 6'b001001;
12'd1385 : mem_out_dec = 6'b001010;
12'd1386 : mem_out_dec = 6'b001010;
12'd1387 : mem_out_dec = 6'b001011;
12'd1388 : mem_out_dec = 6'b001100;
12'd1389 : mem_out_dec = 6'b001101;
12'd1390 : mem_out_dec = 6'b001110;
12'd1391 : mem_out_dec = 6'b001110;
12'd1392 : mem_out_dec = 6'b001111;
12'd1393 : mem_out_dec = 6'b001111;
12'd1394 : mem_out_dec = 6'b010000;
12'd1395 : mem_out_dec = 6'b010000;
12'd1396 : mem_out_dec = 6'b010001;
12'd1397 : mem_out_dec = 6'b010001;
12'd1398 : mem_out_dec = 6'b010010;
12'd1399 : mem_out_dec = 6'b010010;
12'd1400 : mem_out_dec = 6'b010010;
12'd1401 : mem_out_dec = 6'b010011;
12'd1402 : mem_out_dec = 6'b010100;
12'd1403 : mem_out_dec = 6'b010100;
12'd1404 : mem_out_dec = 6'b010101;
12'd1405 : mem_out_dec = 6'b010110;
12'd1406 : mem_out_dec = 6'b010111;
12'd1407 : mem_out_dec = 6'b010111;
12'd1408 : mem_out_dec = 6'b111111;
12'd1409 : mem_out_dec = 6'b111111;
12'd1410 : mem_out_dec = 6'b111111;
12'd1411 : mem_out_dec = 6'b111111;
12'd1412 : mem_out_dec = 6'b111111;
12'd1413 : mem_out_dec = 6'b111111;
12'd1414 : mem_out_dec = 6'b111111;
12'd1415 : mem_out_dec = 6'b111111;
12'd1416 : mem_out_dec = 6'b111111;
12'd1417 : mem_out_dec = 6'b111111;
12'd1418 : mem_out_dec = 6'b111111;
12'd1419 : mem_out_dec = 6'b111111;
12'd1420 : mem_out_dec = 6'b111111;
12'd1421 : mem_out_dec = 6'b111111;
12'd1422 : mem_out_dec = 6'b111111;
12'd1423 : mem_out_dec = 6'b111111;
12'd1424 : mem_out_dec = 6'b111111;
12'd1425 : mem_out_dec = 6'b111111;
12'd1426 : mem_out_dec = 6'b111111;
12'd1427 : mem_out_dec = 6'b111111;
12'd1428 : mem_out_dec = 6'b111111;
12'd1429 : mem_out_dec = 6'b111111;
12'd1430 : mem_out_dec = 6'b111111;
12'd1431 : mem_out_dec = 6'b111111;
12'd1432 : mem_out_dec = 6'b111111;
12'd1433 : mem_out_dec = 6'b111111;
12'd1434 : mem_out_dec = 6'b111111;
12'd1435 : mem_out_dec = 6'b111111;
12'd1436 : mem_out_dec = 6'b000101;
12'd1437 : mem_out_dec = 6'b000110;
12'd1438 : mem_out_dec = 6'b000111;
12'd1439 : mem_out_dec = 6'b000111;
12'd1440 : mem_out_dec = 6'b000110;
12'd1441 : mem_out_dec = 6'b000110;
12'd1442 : mem_out_dec = 6'b000110;
12'd1443 : mem_out_dec = 6'b000110;
12'd1444 : mem_out_dec = 6'b000110;
12'd1445 : mem_out_dec = 6'b000111;
12'd1446 : mem_out_dec = 6'b000111;
12'd1447 : mem_out_dec = 6'b001000;
12'd1448 : mem_out_dec = 6'b001001;
12'd1449 : mem_out_dec = 6'b001001;
12'd1450 : mem_out_dec = 6'b001010;
12'd1451 : mem_out_dec = 6'b001011;
12'd1452 : mem_out_dec = 6'b001100;
12'd1453 : mem_out_dec = 6'b001100;
12'd1454 : mem_out_dec = 6'b001101;
12'd1455 : mem_out_dec = 6'b001110;
12'd1456 : mem_out_dec = 6'b001110;
12'd1457 : mem_out_dec = 6'b001111;
12'd1458 : mem_out_dec = 6'b001111;
12'd1459 : mem_out_dec = 6'b010000;
12'd1460 : mem_out_dec = 6'b010000;
12'd1461 : mem_out_dec = 6'b010001;
12'd1462 : mem_out_dec = 6'b010001;
12'd1463 : mem_out_dec = 6'b010010;
12'd1464 : mem_out_dec = 6'b010010;
12'd1465 : mem_out_dec = 6'b010011;
12'd1466 : mem_out_dec = 6'b010011;
12'd1467 : mem_out_dec = 6'b010100;
12'd1468 : mem_out_dec = 6'b010101;
12'd1469 : mem_out_dec = 6'b010110;
12'd1470 : mem_out_dec = 6'b010110;
12'd1471 : mem_out_dec = 6'b010111;
12'd1472 : mem_out_dec = 6'b111111;
12'd1473 : mem_out_dec = 6'b111111;
12'd1474 : mem_out_dec = 6'b111111;
12'd1475 : mem_out_dec = 6'b111111;
12'd1476 : mem_out_dec = 6'b111111;
12'd1477 : mem_out_dec = 6'b111111;
12'd1478 : mem_out_dec = 6'b111111;
12'd1479 : mem_out_dec = 6'b111111;
12'd1480 : mem_out_dec = 6'b111111;
12'd1481 : mem_out_dec = 6'b111111;
12'd1482 : mem_out_dec = 6'b111111;
12'd1483 : mem_out_dec = 6'b111111;
12'd1484 : mem_out_dec = 6'b111111;
12'd1485 : mem_out_dec = 6'b111111;
12'd1486 : mem_out_dec = 6'b111111;
12'd1487 : mem_out_dec = 6'b111111;
12'd1488 : mem_out_dec = 6'b111111;
12'd1489 : mem_out_dec = 6'b111111;
12'd1490 : mem_out_dec = 6'b111111;
12'd1491 : mem_out_dec = 6'b111111;
12'd1492 : mem_out_dec = 6'b111111;
12'd1493 : mem_out_dec = 6'b111111;
12'd1494 : mem_out_dec = 6'b111111;
12'd1495 : mem_out_dec = 6'b111111;
12'd1496 : mem_out_dec = 6'b111111;
12'd1497 : mem_out_dec = 6'b111111;
12'd1498 : mem_out_dec = 6'b111111;
12'd1499 : mem_out_dec = 6'b111111;
12'd1500 : mem_out_dec = 6'b111111;
12'd1501 : mem_out_dec = 6'b000101;
12'd1502 : mem_out_dec = 6'b000110;
12'd1503 : mem_out_dec = 6'b000110;
12'd1504 : mem_out_dec = 6'b000110;
12'd1505 : mem_out_dec = 6'b000110;
12'd1506 : mem_out_dec = 6'b000101;
12'd1507 : mem_out_dec = 6'b000101;
12'd1508 : mem_out_dec = 6'b000110;
12'd1509 : mem_out_dec = 6'b000111;
12'd1510 : mem_out_dec = 6'b000111;
12'd1511 : mem_out_dec = 6'b001000;
12'd1512 : mem_out_dec = 6'b001000;
12'd1513 : mem_out_dec = 6'b001001;
12'd1514 : mem_out_dec = 6'b001010;
12'd1515 : mem_out_dec = 6'b001011;
12'd1516 : mem_out_dec = 6'b001011;
12'd1517 : mem_out_dec = 6'b001100;
12'd1518 : mem_out_dec = 6'b001101;
12'd1519 : mem_out_dec = 6'b001110;
12'd1520 : mem_out_dec = 6'b001110;
12'd1521 : mem_out_dec = 6'b001110;
12'd1522 : mem_out_dec = 6'b001111;
12'd1523 : mem_out_dec = 6'b001111;
12'd1524 : mem_out_dec = 6'b010000;
12'd1525 : mem_out_dec = 6'b010000;
12'd1526 : mem_out_dec = 6'b010001;
12'd1527 : mem_out_dec = 6'b010001;
12'd1528 : mem_out_dec = 6'b010001;
12'd1529 : mem_out_dec = 6'b010010;
12'd1530 : mem_out_dec = 6'b010011;
12'd1531 : mem_out_dec = 6'b010100;
12'd1532 : mem_out_dec = 6'b010101;
12'd1533 : mem_out_dec = 6'b010101;
12'd1534 : mem_out_dec = 6'b010110;
12'd1535 : mem_out_dec = 6'b010110;
12'd1536 : mem_out_dec = 6'b111111;
12'd1537 : mem_out_dec = 6'b111111;
12'd1538 : mem_out_dec = 6'b111111;
12'd1539 : mem_out_dec = 6'b111111;
12'd1540 : mem_out_dec = 6'b111111;
12'd1541 : mem_out_dec = 6'b111111;
12'd1542 : mem_out_dec = 6'b111111;
12'd1543 : mem_out_dec = 6'b111111;
12'd1544 : mem_out_dec = 6'b111111;
12'd1545 : mem_out_dec = 6'b111111;
12'd1546 : mem_out_dec = 6'b111111;
12'd1547 : mem_out_dec = 6'b111111;
12'd1548 : mem_out_dec = 6'b111111;
12'd1549 : mem_out_dec = 6'b111111;
12'd1550 : mem_out_dec = 6'b111111;
12'd1551 : mem_out_dec = 6'b111111;
12'd1552 : mem_out_dec = 6'b111111;
12'd1553 : mem_out_dec = 6'b111111;
12'd1554 : mem_out_dec = 6'b111111;
12'd1555 : mem_out_dec = 6'b111111;
12'd1556 : mem_out_dec = 6'b111111;
12'd1557 : mem_out_dec = 6'b111111;
12'd1558 : mem_out_dec = 6'b111111;
12'd1559 : mem_out_dec = 6'b111111;
12'd1560 : mem_out_dec = 6'b111111;
12'd1561 : mem_out_dec = 6'b111111;
12'd1562 : mem_out_dec = 6'b111111;
12'd1563 : mem_out_dec = 6'b111111;
12'd1564 : mem_out_dec = 6'b111111;
12'd1565 : mem_out_dec = 6'b111111;
12'd1566 : mem_out_dec = 6'b000100;
12'd1567 : mem_out_dec = 6'b000100;
12'd1568 : mem_out_dec = 6'b000100;
12'd1569 : mem_out_dec = 6'b000100;
12'd1570 : mem_out_dec = 6'b000100;
12'd1571 : mem_out_dec = 6'b000101;
12'd1572 : mem_out_dec = 6'b000101;
12'd1573 : mem_out_dec = 6'b000110;
12'd1574 : mem_out_dec = 6'b000111;
12'd1575 : mem_out_dec = 6'b000111;
12'd1576 : mem_out_dec = 6'b000111;
12'd1577 : mem_out_dec = 6'b001000;
12'd1578 : mem_out_dec = 6'b001001;
12'd1579 : mem_out_dec = 6'b001010;
12'd1580 : mem_out_dec = 6'b001010;
12'd1581 : mem_out_dec = 6'b001011;
12'd1582 : mem_out_dec = 6'b001100;
12'd1583 : mem_out_dec = 6'b001101;
12'd1584 : mem_out_dec = 6'b001101;
12'd1585 : mem_out_dec = 6'b001101;
12'd1586 : mem_out_dec = 6'b001110;
12'd1587 : mem_out_dec = 6'b001110;
12'd1588 : mem_out_dec = 6'b001111;
12'd1589 : mem_out_dec = 6'b001111;
12'd1590 : mem_out_dec = 6'b010000;
12'd1591 : mem_out_dec = 6'b010001;
12'd1592 : mem_out_dec = 6'b010001;
12'd1593 : mem_out_dec = 6'b010001;
12'd1594 : mem_out_dec = 6'b010010;
12'd1595 : mem_out_dec = 6'b010010;
12'd1596 : mem_out_dec = 6'b010011;
12'd1597 : mem_out_dec = 6'b010011;
12'd1598 : mem_out_dec = 6'b010100;
12'd1599 : mem_out_dec = 6'b010100;
12'd1600 : mem_out_dec = 6'b111111;
12'd1601 : mem_out_dec = 6'b111111;
12'd1602 : mem_out_dec = 6'b111111;
12'd1603 : mem_out_dec = 6'b111111;
12'd1604 : mem_out_dec = 6'b111111;
12'd1605 : mem_out_dec = 6'b111111;
12'd1606 : mem_out_dec = 6'b111111;
12'd1607 : mem_out_dec = 6'b111111;
12'd1608 : mem_out_dec = 6'b111111;
12'd1609 : mem_out_dec = 6'b111111;
12'd1610 : mem_out_dec = 6'b111111;
12'd1611 : mem_out_dec = 6'b111111;
12'd1612 : mem_out_dec = 6'b111111;
12'd1613 : mem_out_dec = 6'b111111;
12'd1614 : mem_out_dec = 6'b111111;
12'd1615 : mem_out_dec = 6'b111111;
12'd1616 : mem_out_dec = 6'b111111;
12'd1617 : mem_out_dec = 6'b111111;
12'd1618 : mem_out_dec = 6'b111111;
12'd1619 : mem_out_dec = 6'b111111;
12'd1620 : mem_out_dec = 6'b111111;
12'd1621 : mem_out_dec = 6'b111111;
12'd1622 : mem_out_dec = 6'b111111;
12'd1623 : mem_out_dec = 6'b111111;
12'd1624 : mem_out_dec = 6'b111111;
12'd1625 : mem_out_dec = 6'b111111;
12'd1626 : mem_out_dec = 6'b111111;
12'd1627 : mem_out_dec = 6'b111111;
12'd1628 : mem_out_dec = 6'b111111;
12'd1629 : mem_out_dec = 6'b111111;
12'd1630 : mem_out_dec = 6'b111111;
12'd1631 : mem_out_dec = 6'b000100;
12'd1632 : mem_out_dec = 6'b000011;
12'd1633 : mem_out_dec = 6'b000011;
12'd1634 : mem_out_dec = 6'b000100;
12'd1635 : mem_out_dec = 6'b000100;
12'd1636 : mem_out_dec = 6'b000101;
12'd1637 : mem_out_dec = 6'b000110;
12'd1638 : mem_out_dec = 6'b000110;
12'd1639 : mem_out_dec = 6'b000111;
12'd1640 : mem_out_dec = 6'b000111;
12'd1641 : mem_out_dec = 6'b001000;
12'd1642 : mem_out_dec = 6'b001001;
12'd1643 : mem_out_dec = 6'b001001;
12'd1644 : mem_out_dec = 6'b001010;
12'd1645 : mem_out_dec = 6'b001011;
12'd1646 : mem_out_dec = 6'b001100;
12'd1647 : mem_out_dec = 6'b001101;
12'd1648 : mem_out_dec = 6'b001101;
12'd1649 : mem_out_dec = 6'b001101;
12'd1650 : mem_out_dec = 6'b001110;
12'd1651 : mem_out_dec = 6'b001110;
12'd1652 : mem_out_dec = 6'b001110;
12'd1653 : mem_out_dec = 6'b001111;
12'd1654 : mem_out_dec = 6'b010000;
12'd1655 : mem_out_dec = 6'b010000;
12'd1656 : mem_out_dec = 6'b010001;
12'd1657 : mem_out_dec = 6'b010001;
12'd1658 : mem_out_dec = 6'b010001;
12'd1659 : mem_out_dec = 6'b010010;
12'd1660 : mem_out_dec = 6'b010010;
12'd1661 : mem_out_dec = 6'b010011;
12'd1662 : mem_out_dec = 6'b010011;
12'd1663 : mem_out_dec = 6'b010100;
12'd1664 : mem_out_dec = 6'b111111;
12'd1665 : mem_out_dec = 6'b111111;
12'd1666 : mem_out_dec = 6'b111111;
12'd1667 : mem_out_dec = 6'b111111;
12'd1668 : mem_out_dec = 6'b111111;
12'd1669 : mem_out_dec = 6'b111111;
12'd1670 : mem_out_dec = 6'b111111;
12'd1671 : mem_out_dec = 6'b111111;
12'd1672 : mem_out_dec = 6'b111111;
12'd1673 : mem_out_dec = 6'b111111;
12'd1674 : mem_out_dec = 6'b111111;
12'd1675 : mem_out_dec = 6'b111111;
12'd1676 : mem_out_dec = 6'b111111;
12'd1677 : mem_out_dec = 6'b111111;
12'd1678 : mem_out_dec = 6'b111111;
12'd1679 : mem_out_dec = 6'b111111;
12'd1680 : mem_out_dec = 6'b111111;
12'd1681 : mem_out_dec = 6'b111111;
12'd1682 : mem_out_dec = 6'b111111;
12'd1683 : mem_out_dec = 6'b111111;
12'd1684 : mem_out_dec = 6'b111111;
12'd1685 : mem_out_dec = 6'b111111;
12'd1686 : mem_out_dec = 6'b111111;
12'd1687 : mem_out_dec = 6'b111111;
12'd1688 : mem_out_dec = 6'b111111;
12'd1689 : mem_out_dec = 6'b111111;
12'd1690 : mem_out_dec = 6'b111111;
12'd1691 : mem_out_dec = 6'b111111;
12'd1692 : mem_out_dec = 6'b111111;
12'd1693 : mem_out_dec = 6'b111111;
12'd1694 : mem_out_dec = 6'b111111;
12'd1695 : mem_out_dec = 6'b111111;
12'd1696 : mem_out_dec = 6'b000011;
12'd1697 : mem_out_dec = 6'b000011;
12'd1698 : mem_out_dec = 6'b000100;
12'd1699 : mem_out_dec = 6'b000100;
12'd1700 : mem_out_dec = 6'b000101;
12'd1701 : mem_out_dec = 6'b000101;
12'd1702 : mem_out_dec = 6'b000110;
12'd1703 : mem_out_dec = 6'b000111;
12'd1704 : mem_out_dec = 6'b000111;
12'd1705 : mem_out_dec = 6'b001000;
12'd1706 : mem_out_dec = 6'b001000;
12'd1707 : mem_out_dec = 6'b001001;
12'd1708 : mem_out_dec = 6'b001010;
12'd1709 : mem_out_dec = 6'b001011;
12'd1710 : mem_out_dec = 6'b001100;
12'd1711 : mem_out_dec = 6'b001100;
12'd1712 : mem_out_dec = 6'b001100;
12'd1713 : mem_out_dec = 6'b001101;
12'd1714 : mem_out_dec = 6'b001101;
12'd1715 : mem_out_dec = 6'b001110;
12'd1716 : mem_out_dec = 6'b001110;
12'd1717 : mem_out_dec = 6'b001111;
12'd1718 : mem_out_dec = 6'b001111;
12'd1719 : mem_out_dec = 6'b010000;
12'd1720 : mem_out_dec = 6'b010000;
12'd1721 : mem_out_dec = 6'b010000;
12'd1722 : mem_out_dec = 6'b010001;
12'd1723 : mem_out_dec = 6'b010001;
12'd1724 : mem_out_dec = 6'b010010;
12'd1725 : mem_out_dec = 6'b010010;
12'd1726 : mem_out_dec = 6'b010011;
12'd1727 : mem_out_dec = 6'b010011;
12'd1728 : mem_out_dec = 6'b111111;
12'd1729 : mem_out_dec = 6'b111111;
12'd1730 : mem_out_dec = 6'b111111;
12'd1731 : mem_out_dec = 6'b111111;
12'd1732 : mem_out_dec = 6'b111111;
12'd1733 : mem_out_dec = 6'b111111;
12'd1734 : mem_out_dec = 6'b111111;
12'd1735 : mem_out_dec = 6'b111111;
12'd1736 : mem_out_dec = 6'b111111;
12'd1737 : mem_out_dec = 6'b111111;
12'd1738 : mem_out_dec = 6'b111111;
12'd1739 : mem_out_dec = 6'b111111;
12'd1740 : mem_out_dec = 6'b111111;
12'd1741 : mem_out_dec = 6'b111111;
12'd1742 : mem_out_dec = 6'b111111;
12'd1743 : mem_out_dec = 6'b111111;
12'd1744 : mem_out_dec = 6'b111111;
12'd1745 : mem_out_dec = 6'b111111;
12'd1746 : mem_out_dec = 6'b111111;
12'd1747 : mem_out_dec = 6'b111111;
12'd1748 : mem_out_dec = 6'b111111;
12'd1749 : mem_out_dec = 6'b111111;
12'd1750 : mem_out_dec = 6'b111111;
12'd1751 : mem_out_dec = 6'b111111;
12'd1752 : mem_out_dec = 6'b111111;
12'd1753 : mem_out_dec = 6'b111111;
12'd1754 : mem_out_dec = 6'b111111;
12'd1755 : mem_out_dec = 6'b111111;
12'd1756 : mem_out_dec = 6'b111111;
12'd1757 : mem_out_dec = 6'b111111;
12'd1758 : mem_out_dec = 6'b111111;
12'd1759 : mem_out_dec = 6'b111111;
12'd1760 : mem_out_dec = 6'b111111;
12'd1761 : mem_out_dec = 6'b000011;
12'd1762 : mem_out_dec = 6'b000011;
12'd1763 : mem_out_dec = 6'b000100;
12'd1764 : mem_out_dec = 6'b000101;
12'd1765 : mem_out_dec = 6'b000101;
12'd1766 : mem_out_dec = 6'b000110;
12'd1767 : mem_out_dec = 6'b000111;
12'd1768 : mem_out_dec = 6'b000111;
12'd1769 : mem_out_dec = 6'b000111;
12'd1770 : mem_out_dec = 6'b001000;
12'd1771 : mem_out_dec = 6'b001001;
12'd1772 : mem_out_dec = 6'b001010;
12'd1773 : mem_out_dec = 6'b001011;
12'd1774 : mem_out_dec = 6'b001011;
12'd1775 : mem_out_dec = 6'b001100;
12'd1776 : mem_out_dec = 6'b001100;
12'd1777 : mem_out_dec = 6'b001101;
12'd1778 : mem_out_dec = 6'b001101;
12'd1779 : mem_out_dec = 6'b001101;
12'd1780 : mem_out_dec = 6'b001110;
12'd1781 : mem_out_dec = 6'b001111;
12'd1782 : mem_out_dec = 6'b001111;
12'd1783 : mem_out_dec = 6'b010000;
12'd1784 : mem_out_dec = 6'b010000;
12'd1785 : mem_out_dec = 6'b010000;
12'd1786 : mem_out_dec = 6'b010000;
12'd1787 : mem_out_dec = 6'b010001;
12'd1788 : mem_out_dec = 6'b010001;
12'd1789 : mem_out_dec = 6'b010010;
12'd1790 : mem_out_dec = 6'b010010;
12'd1791 : mem_out_dec = 6'b010011;
12'd1792 : mem_out_dec = 6'b111111;
12'd1793 : mem_out_dec = 6'b111111;
12'd1794 : mem_out_dec = 6'b111111;
12'd1795 : mem_out_dec = 6'b111111;
12'd1796 : mem_out_dec = 6'b111111;
12'd1797 : mem_out_dec = 6'b111111;
12'd1798 : mem_out_dec = 6'b111111;
12'd1799 : mem_out_dec = 6'b111111;
12'd1800 : mem_out_dec = 6'b111111;
12'd1801 : mem_out_dec = 6'b111111;
12'd1802 : mem_out_dec = 6'b111111;
12'd1803 : mem_out_dec = 6'b111111;
12'd1804 : mem_out_dec = 6'b111111;
12'd1805 : mem_out_dec = 6'b111111;
12'd1806 : mem_out_dec = 6'b111111;
12'd1807 : mem_out_dec = 6'b111111;
12'd1808 : mem_out_dec = 6'b111111;
12'd1809 : mem_out_dec = 6'b111111;
12'd1810 : mem_out_dec = 6'b111111;
12'd1811 : mem_out_dec = 6'b111111;
12'd1812 : mem_out_dec = 6'b111111;
12'd1813 : mem_out_dec = 6'b111111;
12'd1814 : mem_out_dec = 6'b111111;
12'd1815 : mem_out_dec = 6'b111111;
12'd1816 : mem_out_dec = 6'b111111;
12'd1817 : mem_out_dec = 6'b111111;
12'd1818 : mem_out_dec = 6'b111111;
12'd1819 : mem_out_dec = 6'b111111;
12'd1820 : mem_out_dec = 6'b111111;
12'd1821 : mem_out_dec = 6'b111111;
12'd1822 : mem_out_dec = 6'b111111;
12'd1823 : mem_out_dec = 6'b111111;
12'd1824 : mem_out_dec = 6'b111111;
12'd1825 : mem_out_dec = 6'b111111;
12'd1826 : mem_out_dec = 6'b000011;
12'd1827 : mem_out_dec = 6'b000100;
12'd1828 : mem_out_dec = 6'b000100;
12'd1829 : mem_out_dec = 6'b000101;
12'd1830 : mem_out_dec = 6'b000110;
12'd1831 : mem_out_dec = 6'b000110;
12'd1832 : mem_out_dec = 6'b000110;
12'd1833 : mem_out_dec = 6'b000111;
12'd1834 : mem_out_dec = 6'b001000;
12'd1835 : mem_out_dec = 6'b001001;
12'd1836 : mem_out_dec = 6'b001010;
12'd1837 : mem_out_dec = 6'b001010;
12'd1838 : mem_out_dec = 6'b001011;
12'd1839 : mem_out_dec = 6'b001100;
12'd1840 : mem_out_dec = 6'b001100;
12'd1841 : mem_out_dec = 6'b001100;
12'd1842 : mem_out_dec = 6'b001101;
12'd1843 : mem_out_dec = 6'b001101;
12'd1844 : mem_out_dec = 6'b001110;
12'd1845 : mem_out_dec = 6'b001110;
12'd1846 : mem_out_dec = 6'b001111;
12'd1847 : mem_out_dec = 6'b010000;
12'd1848 : mem_out_dec = 6'b001111;
12'd1849 : mem_out_dec = 6'b001111;
12'd1850 : mem_out_dec = 6'b010000;
12'd1851 : mem_out_dec = 6'b010000;
12'd1852 : mem_out_dec = 6'b010001;
12'd1853 : mem_out_dec = 6'b010001;
12'd1854 : mem_out_dec = 6'b010010;
12'd1855 : mem_out_dec = 6'b010010;
12'd1856 : mem_out_dec = 6'b111111;
12'd1857 : mem_out_dec = 6'b111111;
12'd1858 : mem_out_dec = 6'b111111;
12'd1859 : mem_out_dec = 6'b111111;
12'd1860 : mem_out_dec = 6'b111111;
12'd1861 : mem_out_dec = 6'b111111;
12'd1862 : mem_out_dec = 6'b111111;
12'd1863 : mem_out_dec = 6'b111111;
12'd1864 : mem_out_dec = 6'b111111;
12'd1865 : mem_out_dec = 6'b111111;
12'd1866 : mem_out_dec = 6'b111111;
12'd1867 : mem_out_dec = 6'b111111;
12'd1868 : mem_out_dec = 6'b111111;
12'd1869 : mem_out_dec = 6'b111111;
12'd1870 : mem_out_dec = 6'b111111;
12'd1871 : mem_out_dec = 6'b111111;
12'd1872 : mem_out_dec = 6'b111111;
12'd1873 : mem_out_dec = 6'b111111;
12'd1874 : mem_out_dec = 6'b111111;
12'd1875 : mem_out_dec = 6'b111111;
12'd1876 : mem_out_dec = 6'b111111;
12'd1877 : mem_out_dec = 6'b111111;
12'd1878 : mem_out_dec = 6'b111111;
12'd1879 : mem_out_dec = 6'b111111;
12'd1880 : mem_out_dec = 6'b111111;
12'd1881 : mem_out_dec = 6'b111111;
12'd1882 : mem_out_dec = 6'b111111;
12'd1883 : mem_out_dec = 6'b111111;
12'd1884 : mem_out_dec = 6'b111111;
12'd1885 : mem_out_dec = 6'b111111;
12'd1886 : mem_out_dec = 6'b111111;
12'd1887 : mem_out_dec = 6'b111111;
12'd1888 : mem_out_dec = 6'b111111;
12'd1889 : mem_out_dec = 6'b111111;
12'd1890 : mem_out_dec = 6'b111111;
12'd1891 : mem_out_dec = 6'b000100;
12'd1892 : mem_out_dec = 6'b000100;
12'd1893 : mem_out_dec = 6'b000101;
12'd1894 : mem_out_dec = 6'b000101;
12'd1895 : mem_out_dec = 6'b000110;
12'd1896 : mem_out_dec = 6'b000110;
12'd1897 : mem_out_dec = 6'b000111;
12'd1898 : mem_out_dec = 6'b001000;
12'd1899 : mem_out_dec = 6'b001001;
12'd1900 : mem_out_dec = 6'b001001;
12'd1901 : mem_out_dec = 6'b001010;
12'd1902 : mem_out_dec = 6'b001011;
12'd1903 : mem_out_dec = 6'b001100;
12'd1904 : mem_out_dec = 6'b001100;
12'd1905 : mem_out_dec = 6'b001100;
12'd1906 : mem_out_dec = 6'b001100;
12'd1907 : mem_out_dec = 6'b001101;
12'd1908 : mem_out_dec = 6'b001110;
12'd1909 : mem_out_dec = 6'b001110;
12'd1910 : mem_out_dec = 6'b001111;
12'd1911 : mem_out_dec = 6'b001111;
12'd1912 : mem_out_dec = 6'b001111;
12'd1913 : mem_out_dec = 6'b001111;
12'd1914 : mem_out_dec = 6'b001111;
12'd1915 : mem_out_dec = 6'b010000;
12'd1916 : mem_out_dec = 6'b010000;
12'd1917 : mem_out_dec = 6'b010001;
12'd1918 : mem_out_dec = 6'b010001;
12'd1919 : mem_out_dec = 6'b010010;
12'd1920 : mem_out_dec = 6'b111111;
12'd1921 : mem_out_dec = 6'b111111;
12'd1922 : mem_out_dec = 6'b111111;
12'd1923 : mem_out_dec = 6'b111111;
12'd1924 : mem_out_dec = 6'b111111;
12'd1925 : mem_out_dec = 6'b111111;
12'd1926 : mem_out_dec = 6'b111111;
12'd1927 : mem_out_dec = 6'b111111;
12'd1928 : mem_out_dec = 6'b111111;
12'd1929 : mem_out_dec = 6'b111111;
12'd1930 : mem_out_dec = 6'b111111;
12'd1931 : mem_out_dec = 6'b111111;
12'd1932 : mem_out_dec = 6'b111111;
12'd1933 : mem_out_dec = 6'b111111;
12'd1934 : mem_out_dec = 6'b111111;
12'd1935 : mem_out_dec = 6'b111111;
12'd1936 : mem_out_dec = 6'b111111;
12'd1937 : mem_out_dec = 6'b111111;
12'd1938 : mem_out_dec = 6'b111111;
12'd1939 : mem_out_dec = 6'b111111;
12'd1940 : mem_out_dec = 6'b111111;
12'd1941 : mem_out_dec = 6'b111111;
12'd1942 : mem_out_dec = 6'b111111;
12'd1943 : mem_out_dec = 6'b111111;
12'd1944 : mem_out_dec = 6'b111111;
12'd1945 : mem_out_dec = 6'b111111;
12'd1946 : mem_out_dec = 6'b111111;
12'd1947 : mem_out_dec = 6'b111111;
12'd1948 : mem_out_dec = 6'b111111;
12'd1949 : mem_out_dec = 6'b111111;
12'd1950 : mem_out_dec = 6'b111111;
12'd1951 : mem_out_dec = 6'b111111;
12'd1952 : mem_out_dec = 6'b111111;
12'd1953 : mem_out_dec = 6'b111111;
12'd1954 : mem_out_dec = 6'b111111;
12'd1955 : mem_out_dec = 6'b111111;
12'd1956 : mem_out_dec = 6'b000100;
12'd1957 : mem_out_dec = 6'b000101;
12'd1958 : mem_out_dec = 6'b000101;
12'd1959 : mem_out_dec = 6'b000110;
12'd1960 : mem_out_dec = 6'b000110;
12'd1961 : mem_out_dec = 6'b000111;
12'd1962 : mem_out_dec = 6'b001000;
12'd1963 : mem_out_dec = 6'b001000;
12'd1964 : mem_out_dec = 6'b001001;
12'd1965 : mem_out_dec = 6'b001010;
12'd1966 : mem_out_dec = 6'b001011;
12'd1967 : mem_out_dec = 6'b001011;
12'd1968 : mem_out_dec = 6'b001011;
12'd1969 : mem_out_dec = 6'b001100;
12'd1970 : mem_out_dec = 6'b001100;
12'd1971 : mem_out_dec = 6'b001101;
12'd1972 : mem_out_dec = 6'b001101;
12'd1973 : mem_out_dec = 6'b001110;
12'd1974 : mem_out_dec = 6'b001111;
12'd1975 : mem_out_dec = 6'b001111;
12'd1976 : mem_out_dec = 6'b001110;
12'd1977 : mem_out_dec = 6'b001110;
12'd1978 : mem_out_dec = 6'b001111;
12'd1979 : mem_out_dec = 6'b001111;
12'd1980 : mem_out_dec = 6'b010000;
12'd1981 : mem_out_dec = 6'b010000;
12'd1982 : mem_out_dec = 6'b010001;
12'd1983 : mem_out_dec = 6'b010001;
12'd1984 : mem_out_dec = 6'b111111;
12'd1985 : mem_out_dec = 6'b111111;
12'd1986 : mem_out_dec = 6'b111111;
12'd1987 : mem_out_dec = 6'b111111;
12'd1988 : mem_out_dec = 6'b111111;
12'd1989 : mem_out_dec = 6'b111111;
12'd1990 : mem_out_dec = 6'b111111;
12'd1991 : mem_out_dec = 6'b111111;
12'd1992 : mem_out_dec = 6'b111111;
12'd1993 : mem_out_dec = 6'b111111;
12'd1994 : mem_out_dec = 6'b111111;
12'd1995 : mem_out_dec = 6'b111111;
12'd1996 : mem_out_dec = 6'b111111;
12'd1997 : mem_out_dec = 6'b111111;
12'd1998 : mem_out_dec = 6'b111111;
12'd1999 : mem_out_dec = 6'b111111;
12'd2000 : mem_out_dec = 6'b111111;
12'd2001 : mem_out_dec = 6'b111111;
12'd2002 : mem_out_dec = 6'b111111;
12'd2003 : mem_out_dec = 6'b111111;
12'd2004 : mem_out_dec = 6'b111111;
12'd2005 : mem_out_dec = 6'b111111;
12'd2006 : mem_out_dec = 6'b111111;
12'd2007 : mem_out_dec = 6'b111111;
12'd2008 : mem_out_dec = 6'b111111;
12'd2009 : mem_out_dec = 6'b111111;
12'd2010 : mem_out_dec = 6'b111111;
12'd2011 : mem_out_dec = 6'b111111;
12'd2012 : mem_out_dec = 6'b111111;
12'd2013 : mem_out_dec = 6'b111111;
12'd2014 : mem_out_dec = 6'b111111;
12'd2015 : mem_out_dec = 6'b111111;
12'd2016 : mem_out_dec = 6'b111111;
12'd2017 : mem_out_dec = 6'b111111;
12'd2018 : mem_out_dec = 6'b111111;
12'd2019 : mem_out_dec = 6'b111111;
12'd2020 : mem_out_dec = 6'b111111;
12'd2021 : mem_out_dec = 6'b000100;
12'd2022 : mem_out_dec = 6'b000101;
12'd2023 : mem_out_dec = 6'b000110;
12'd2024 : mem_out_dec = 6'b000110;
12'd2025 : mem_out_dec = 6'b000111;
12'd2026 : mem_out_dec = 6'b000111;
12'd2027 : mem_out_dec = 6'b001000;
12'd2028 : mem_out_dec = 6'b001001;
12'd2029 : mem_out_dec = 6'b001010;
12'd2030 : mem_out_dec = 6'b001010;
12'd2031 : mem_out_dec = 6'b001011;
12'd2032 : mem_out_dec = 6'b001011;
12'd2033 : mem_out_dec = 6'b001011;
12'd2034 : mem_out_dec = 6'b001100;
12'd2035 : mem_out_dec = 6'b001101;
12'd2036 : mem_out_dec = 6'b001101;
12'd2037 : mem_out_dec = 6'b001110;
12'd2038 : mem_out_dec = 6'b001110;
12'd2039 : mem_out_dec = 6'b001110;
12'd2040 : mem_out_dec = 6'b001101;
12'd2041 : mem_out_dec = 6'b001110;
12'd2042 : mem_out_dec = 6'b001110;
12'd2043 : mem_out_dec = 6'b001111;
12'd2044 : mem_out_dec = 6'b001111;
12'd2045 : mem_out_dec = 6'b010000;
12'd2046 : mem_out_dec = 6'b010000;
12'd2047 : mem_out_dec = 6'b010001;
12'd2048 : mem_out_dec = 6'b111111;
12'd2049 : mem_out_dec = 6'b111111;
12'd2050 : mem_out_dec = 6'b111111;
12'd2051 : mem_out_dec = 6'b111111;
12'd2052 : mem_out_dec = 6'b111111;
12'd2053 : mem_out_dec = 6'b111111;
12'd2054 : mem_out_dec = 6'b111111;
12'd2055 : mem_out_dec = 6'b111111;
12'd2056 : mem_out_dec = 6'b111111;
12'd2057 : mem_out_dec = 6'b111111;
12'd2058 : mem_out_dec = 6'b111111;
12'd2059 : mem_out_dec = 6'b111111;
12'd2060 : mem_out_dec = 6'b111111;
12'd2061 : mem_out_dec = 6'b111111;
12'd2062 : mem_out_dec = 6'b111111;
12'd2063 : mem_out_dec = 6'b111111;
12'd2064 : mem_out_dec = 6'b111111;
12'd2065 : mem_out_dec = 6'b111111;
12'd2066 : mem_out_dec = 6'b111111;
12'd2067 : mem_out_dec = 6'b111111;
12'd2068 : mem_out_dec = 6'b111111;
12'd2069 : mem_out_dec = 6'b111111;
12'd2070 : mem_out_dec = 6'b111111;
12'd2071 : mem_out_dec = 6'b111111;
12'd2072 : mem_out_dec = 6'b111111;
12'd2073 : mem_out_dec = 6'b111111;
12'd2074 : mem_out_dec = 6'b111111;
12'd2075 : mem_out_dec = 6'b111111;
12'd2076 : mem_out_dec = 6'b111111;
12'd2077 : mem_out_dec = 6'b111111;
12'd2078 : mem_out_dec = 6'b111111;
12'd2079 : mem_out_dec = 6'b111111;
12'd2080 : mem_out_dec = 6'b111111;
12'd2081 : mem_out_dec = 6'b111111;
12'd2082 : mem_out_dec = 6'b111111;
12'd2083 : mem_out_dec = 6'b111111;
12'd2084 : mem_out_dec = 6'b111111;
12'd2085 : mem_out_dec = 6'b111111;
12'd2086 : mem_out_dec = 6'b000100;
12'd2087 : mem_out_dec = 6'b000101;
12'd2088 : mem_out_dec = 6'b000101;
12'd2089 : mem_out_dec = 6'b000110;
12'd2090 : mem_out_dec = 6'b000110;
12'd2091 : mem_out_dec = 6'b000111;
12'd2092 : mem_out_dec = 6'b001000;
12'd2093 : mem_out_dec = 6'b001001;
12'd2094 : mem_out_dec = 6'b001001;
12'd2095 : mem_out_dec = 6'b001010;
12'd2096 : mem_out_dec = 6'b001010;
12'd2097 : mem_out_dec = 6'b001011;
12'd2098 : mem_out_dec = 6'b001011;
12'd2099 : mem_out_dec = 6'b001100;
12'd2100 : mem_out_dec = 6'b001100;
12'd2101 : mem_out_dec = 6'b001100;
12'd2102 : mem_out_dec = 6'b001100;
12'd2103 : mem_out_dec = 6'b001101;
12'd2104 : mem_out_dec = 6'b001100;
12'd2105 : mem_out_dec = 6'b001100;
12'd2106 : mem_out_dec = 6'b001101;
12'd2107 : mem_out_dec = 6'b001101;
12'd2108 : mem_out_dec = 6'b001110;
12'd2109 : mem_out_dec = 6'b001111;
12'd2110 : mem_out_dec = 6'b010000;
12'd2111 : mem_out_dec = 6'b010000;
12'd2112 : mem_out_dec = 6'b111111;
12'd2113 : mem_out_dec = 6'b111111;
12'd2114 : mem_out_dec = 6'b111111;
12'd2115 : mem_out_dec = 6'b111111;
12'd2116 : mem_out_dec = 6'b111111;
12'd2117 : mem_out_dec = 6'b111111;
12'd2118 : mem_out_dec = 6'b111111;
12'd2119 : mem_out_dec = 6'b111111;
12'd2120 : mem_out_dec = 6'b111111;
12'd2121 : mem_out_dec = 6'b111111;
12'd2122 : mem_out_dec = 6'b111111;
12'd2123 : mem_out_dec = 6'b111111;
12'd2124 : mem_out_dec = 6'b111111;
12'd2125 : mem_out_dec = 6'b111111;
12'd2126 : mem_out_dec = 6'b111111;
12'd2127 : mem_out_dec = 6'b111111;
12'd2128 : mem_out_dec = 6'b111111;
12'd2129 : mem_out_dec = 6'b111111;
12'd2130 : mem_out_dec = 6'b111111;
12'd2131 : mem_out_dec = 6'b111111;
12'd2132 : mem_out_dec = 6'b111111;
12'd2133 : mem_out_dec = 6'b111111;
12'd2134 : mem_out_dec = 6'b111111;
12'd2135 : mem_out_dec = 6'b111111;
12'd2136 : mem_out_dec = 6'b111111;
12'd2137 : mem_out_dec = 6'b111111;
12'd2138 : mem_out_dec = 6'b111111;
12'd2139 : mem_out_dec = 6'b111111;
12'd2140 : mem_out_dec = 6'b111111;
12'd2141 : mem_out_dec = 6'b111111;
12'd2142 : mem_out_dec = 6'b111111;
12'd2143 : mem_out_dec = 6'b111111;
12'd2144 : mem_out_dec = 6'b111111;
12'd2145 : mem_out_dec = 6'b111111;
12'd2146 : mem_out_dec = 6'b111111;
12'd2147 : mem_out_dec = 6'b111111;
12'd2148 : mem_out_dec = 6'b111111;
12'd2149 : mem_out_dec = 6'b111111;
12'd2150 : mem_out_dec = 6'b111111;
12'd2151 : mem_out_dec = 6'b000100;
12'd2152 : mem_out_dec = 6'b000100;
12'd2153 : mem_out_dec = 6'b000101;
12'd2154 : mem_out_dec = 6'b000110;
12'd2155 : mem_out_dec = 6'b000111;
12'd2156 : mem_out_dec = 6'b000111;
12'd2157 : mem_out_dec = 6'b001000;
12'd2158 : mem_out_dec = 6'b001001;
12'd2159 : mem_out_dec = 6'b001001;
12'd2160 : mem_out_dec = 6'b001010;
12'd2161 : mem_out_dec = 6'b001010;
12'd2162 : mem_out_dec = 6'b001011;
12'd2163 : mem_out_dec = 6'b001011;
12'd2164 : mem_out_dec = 6'b001011;
12'd2165 : mem_out_dec = 6'b001011;
12'd2166 : mem_out_dec = 6'b001011;
12'd2167 : mem_out_dec = 6'b001100;
12'd2168 : mem_out_dec = 6'b001011;
12'd2169 : mem_out_dec = 6'b001011;
12'd2170 : mem_out_dec = 6'b001100;
12'd2171 : mem_out_dec = 6'b001101;
12'd2172 : mem_out_dec = 6'b001110;
12'd2173 : mem_out_dec = 6'b001110;
12'd2174 : mem_out_dec = 6'b001111;
12'd2175 : mem_out_dec = 6'b010000;
12'd2176 : mem_out_dec = 6'b111111;
12'd2177 : mem_out_dec = 6'b111111;
12'd2178 : mem_out_dec = 6'b111111;
12'd2179 : mem_out_dec = 6'b111111;
12'd2180 : mem_out_dec = 6'b111111;
12'd2181 : mem_out_dec = 6'b111111;
12'd2182 : mem_out_dec = 6'b111111;
12'd2183 : mem_out_dec = 6'b111111;
12'd2184 : mem_out_dec = 6'b111111;
12'd2185 : mem_out_dec = 6'b111111;
12'd2186 : mem_out_dec = 6'b111111;
12'd2187 : mem_out_dec = 6'b111111;
12'd2188 : mem_out_dec = 6'b111111;
12'd2189 : mem_out_dec = 6'b111111;
12'd2190 : mem_out_dec = 6'b111111;
12'd2191 : mem_out_dec = 6'b111111;
12'd2192 : mem_out_dec = 6'b111111;
12'd2193 : mem_out_dec = 6'b111111;
12'd2194 : mem_out_dec = 6'b111111;
12'd2195 : mem_out_dec = 6'b111111;
12'd2196 : mem_out_dec = 6'b111111;
12'd2197 : mem_out_dec = 6'b111111;
12'd2198 : mem_out_dec = 6'b111111;
12'd2199 : mem_out_dec = 6'b111111;
12'd2200 : mem_out_dec = 6'b111111;
12'd2201 : mem_out_dec = 6'b111111;
12'd2202 : mem_out_dec = 6'b111111;
12'd2203 : mem_out_dec = 6'b111111;
12'd2204 : mem_out_dec = 6'b111111;
12'd2205 : mem_out_dec = 6'b111111;
12'd2206 : mem_out_dec = 6'b111111;
12'd2207 : mem_out_dec = 6'b111111;
12'd2208 : mem_out_dec = 6'b111111;
12'd2209 : mem_out_dec = 6'b111111;
12'd2210 : mem_out_dec = 6'b111111;
12'd2211 : mem_out_dec = 6'b111111;
12'd2212 : mem_out_dec = 6'b111111;
12'd2213 : mem_out_dec = 6'b111111;
12'd2214 : mem_out_dec = 6'b111111;
12'd2215 : mem_out_dec = 6'b111111;
12'd2216 : mem_out_dec = 6'b000100;
12'd2217 : mem_out_dec = 6'b000101;
12'd2218 : mem_out_dec = 6'b000101;
12'd2219 : mem_out_dec = 6'b000110;
12'd2220 : mem_out_dec = 6'b000111;
12'd2221 : mem_out_dec = 6'b000111;
12'd2222 : mem_out_dec = 6'b001000;
12'd2223 : mem_out_dec = 6'b001001;
12'd2224 : mem_out_dec = 6'b001001;
12'd2225 : mem_out_dec = 6'b001010;
12'd2226 : mem_out_dec = 6'b001010;
12'd2227 : mem_out_dec = 6'b001010;
12'd2228 : mem_out_dec = 6'b001010;
12'd2229 : mem_out_dec = 6'b001010;
12'd2230 : mem_out_dec = 6'b001010;
12'd2231 : mem_out_dec = 6'b001010;
12'd2232 : mem_out_dec = 6'b001010;
12'd2233 : mem_out_dec = 6'b001011;
12'd2234 : mem_out_dec = 6'b001100;
12'd2235 : mem_out_dec = 6'b001100;
12'd2236 : mem_out_dec = 6'b001101;
12'd2237 : mem_out_dec = 6'b001110;
12'd2238 : mem_out_dec = 6'b001111;
12'd2239 : mem_out_dec = 6'b010000;
12'd2240 : mem_out_dec = 6'b111111;
12'd2241 : mem_out_dec = 6'b111111;
12'd2242 : mem_out_dec = 6'b111111;
12'd2243 : mem_out_dec = 6'b111111;
12'd2244 : mem_out_dec = 6'b111111;
12'd2245 : mem_out_dec = 6'b111111;
12'd2246 : mem_out_dec = 6'b111111;
12'd2247 : mem_out_dec = 6'b111111;
12'd2248 : mem_out_dec = 6'b111111;
12'd2249 : mem_out_dec = 6'b111111;
12'd2250 : mem_out_dec = 6'b111111;
12'd2251 : mem_out_dec = 6'b111111;
12'd2252 : mem_out_dec = 6'b111111;
12'd2253 : mem_out_dec = 6'b111111;
12'd2254 : mem_out_dec = 6'b111111;
12'd2255 : mem_out_dec = 6'b111111;
12'd2256 : mem_out_dec = 6'b111111;
12'd2257 : mem_out_dec = 6'b111111;
12'd2258 : mem_out_dec = 6'b111111;
12'd2259 : mem_out_dec = 6'b111111;
12'd2260 : mem_out_dec = 6'b111111;
12'd2261 : mem_out_dec = 6'b111111;
12'd2262 : mem_out_dec = 6'b111111;
12'd2263 : mem_out_dec = 6'b111111;
12'd2264 : mem_out_dec = 6'b111111;
12'd2265 : mem_out_dec = 6'b111111;
12'd2266 : mem_out_dec = 6'b111111;
12'd2267 : mem_out_dec = 6'b111111;
12'd2268 : mem_out_dec = 6'b111111;
12'd2269 : mem_out_dec = 6'b111111;
12'd2270 : mem_out_dec = 6'b111111;
12'd2271 : mem_out_dec = 6'b111111;
12'd2272 : mem_out_dec = 6'b111111;
12'd2273 : mem_out_dec = 6'b111111;
12'd2274 : mem_out_dec = 6'b111111;
12'd2275 : mem_out_dec = 6'b111111;
12'd2276 : mem_out_dec = 6'b111111;
12'd2277 : mem_out_dec = 6'b111111;
12'd2278 : mem_out_dec = 6'b111111;
12'd2279 : mem_out_dec = 6'b111111;
12'd2280 : mem_out_dec = 6'b111111;
12'd2281 : mem_out_dec = 6'b000100;
12'd2282 : mem_out_dec = 6'b000101;
12'd2283 : mem_out_dec = 6'b000101;
12'd2284 : mem_out_dec = 6'b000110;
12'd2285 : mem_out_dec = 6'b000111;
12'd2286 : mem_out_dec = 6'b001000;
12'd2287 : mem_out_dec = 6'b001001;
12'd2288 : mem_out_dec = 6'b001001;
12'd2289 : mem_out_dec = 6'b001001;
12'd2290 : mem_out_dec = 6'b001001;
12'd2291 : mem_out_dec = 6'b001001;
12'd2292 : mem_out_dec = 6'b001001;
12'd2293 : mem_out_dec = 6'b001001;
12'd2294 : mem_out_dec = 6'b001001;
12'd2295 : mem_out_dec = 6'b001001;
12'd2296 : mem_out_dec = 6'b001010;
12'd2297 : mem_out_dec = 6'b001010;
12'd2298 : mem_out_dec = 6'b001011;
12'd2299 : mem_out_dec = 6'b001100;
12'd2300 : mem_out_dec = 6'b001101;
12'd2301 : mem_out_dec = 6'b001110;
12'd2302 : mem_out_dec = 6'b001110;
12'd2303 : mem_out_dec = 6'b001111;
12'd2304 : mem_out_dec = 6'b111111;
12'd2305 : mem_out_dec = 6'b111111;
12'd2306 : mem_out_dec = 6'b111111;
12'd2307 : mem_out_dec = 6'b111111;
12'd2308 : mem_out_dec = 6'b111111;
12'd2309 : mem_out_dec = 6'b111111;
12'd2310 : mem_out_dec = 6'b111111;
12'd2311 : mem_out_dec = 6'b111111;
12'd2312 : mem_out_dec = 6'b111111;
12'd2313 : mem_out_dec = 6'b111111;
12'd2314 : mem_out_dec = 6'b111111;
12'd2315 : mem_out_dec = 6'b111111;
12'd2316 : mem_out_dec = 6'b111111;
12'd2317 : mem_out_dec = 6'b111111;
12'd2318 : mem_out_dec = 6'b111111;
12'd2319 : mem_out_dec = 6'b111111;
12'd2320 : mem_out_dec = 6'b111111;
12'd2321 : mem_out_dec = 6'b111111;
12'd2322 : mem_out_dec = 6'b111111;
12'd2323 : mem_out_dec = 6'b111111;
12'd2324 : mem_out_dec = 6'b111111;
12'd2325 : mem_out_dec = 6'b111111;
12'd2326 : mem_out_dec = 6'b111111;
12'd2327 : mem_out_dec = 6'b111111;
12'd2328 : mem_out_dec = 6'b111111;
12'd2329 : mem_out_dec = 6'b111111;
12'd2330 : mem_out_dec = 6'b111111;
12'd2331 : mem_out_dec = 6'b111111;
12'd2332 : mem_out_dec = 6'b111111;
12'd2333 : mem_out_dec = 6'b111111;
12'd2334 : mem_out_dec = 6'b111111;
12'd2335 : mem_out_dec = 6'b111111;
12'd2336 : mem_out_dec = 6'b111111;
12'd2337 : mem_out_dec = 6'b111111;
12'd2338 : mem_out_dec = 6'b111111;
12'd2339 : mem_out_dec = 6'b111111;
12'd2340 : mem_out_dec = 6'b111111;
12'd2341 : mem_out_dec = 6'b111111;
12'd2342 : mem_out_dec = 6'b111111;
12'd2343 : mem_out_dec = 6'b111111;
12'd2344 : mem_out_dec = 6'b111111;
12'd2345 : mem_out_dec = 6'b111111;
12'd2346 : mem_out_dec = 6'b000100;
12'd2347 : mem_out_dec = 6'b000101;
12'd2348 : mem_out_dec = 6'b000110;
12'd2349 : mem_out_dec = 6'b000111;
12'd2350 : mem_out_dec = 6'b000111;
12'd2351 : mem_out_dec = 6'b001000;
12'd2352 : mem_out_dec = 6'b001000;
12'd2353 : mem_out_dec = 6'b001000;
12'd2354 : mem_out_dec = 6'b001000;
12'd2355 : mem_out_dec = 6'b001000;
12'd2356 : mem_out_dec = 6'b001000;
12'd2357 : mem_out_dec = 6'b001000;
12'd2358 : mem_out_dec = 6'b001000;
12'd2359 : mem_out_dec = 6'b001001;
12'd2360 : mem_out_dec = 6'b001001;
12'd2361 : mem_out_dec = 6'b001010;
12'd2362 : mem_out_dec = 6'b001011;
12'd2363 : mem_out_dec = 6'b001100;
12'd2364 : mem_out_dec = 6'b001100;
12'd2365 : mem_out_dec = 6'b001101;
12'd2366 : mem_out_dec = 6'b001110;
12'd2367 : mem_out_dec = 6'b001111;
12'd2368 : mem_out_dec = 6'b111111;
12'd2369 : mem_out_dec = 6'b111111;
12'd2370 : mem_out_dec = 6'b111111;
12'd2371 : mem_out_dec = 6'b111111;
12'd2372 : mem_out_dec = 6'b111111;
12'd2373 : mem_out_dec = 6'b111111;
12'd2374 : mem_out_dec = 6'b111111;
12'd2375 : mem_out_dec = 6'b111111;
12'd2376 : mem_out_dec = 6'b111111;
12'd2377 : mem_out_dec = 6'b111111;
12'd2378 : mem_out_dec = 6'b111111;
12'd2379 : mem_out_dec = 6'b111111;
12'd2380 : mem_out_dec = 6'b111111;
12'd2381 : mem_out_dec = 6'b111111;
12'd2382 : mem_out_dec = 6'b111111;
12'd2383 : mem_out_dec = 6'b111111;
12'd2384 : mem_out_dec = 6'b111111;
12'd2385 : mem_out_dec = 6'b111111;
12'd2386 : mem_out_dec = 6'b111111;
12'd2387 : mem_out_dec = 6'b111111;
12'd2388 : mem_out_dec = 6'b111111;
12'd2389 : mem_out_dec = 6'b111111;
12'd2390 : mem_out_dec = 6'b111111;
12'd2391 : mem_out_dec = 6'b111111;
12'd2392 : mem_out_dec = 6'b111111;
12'd2393 : mem_out_dec = 6'b111111;
12'd2394 : mem_out_dec = 6'b111111;
12'd2395 : mem_out_dec = 6'b111111;
12'd2396 : mem_out_dec = 6'b111111;
12'd2397 : mem_out_dec = 6'b111111;
12'd2398 : mem_out_dec = 6'b111111;
12'd2399 : mem_out_dec = 6'b111111;
12'd2400 : mem_out_dec = 6'b111111;
12'd2401 : mem_out_dec = 6'b111111;
12'd2402 : mem_out_dec = 6'b111111;
12'd2403 : mem_out_dec = 6'b111111;
12'd2404 : mem_out_dec = 6'b111111;
12'd2405 : mem_out_dec = 6'b111111;
12'd2406 : mem_out_dec = 6'b111111;
12'd2407 : mem_out_dec = 6'b111111;
12'd2408 : mem_out_dec = 6'b111111;
12'd2409 : mem_out_dec = 6'b111111;
12'd2410 : mem_out_dec = 6'b111111;
12'd2411 : mem_out_dec = 6'b000101;
12'd2412 : mem_out_dec = 6'b000101;
12'd2413 : mem_out_dec = 6'b000110;
12'd2414 : mem_out_dec = 6'b000111;
12'd2415 : mem_out_dec = 6'b001000;
12'd2416 : mem_out_dec = 6'b000111;
12'd2417 : mem_out_dec = 6'b000111;
12'd2418 : mem_out_dec = 6'b000111;
12'd2419 : mem_out_dec = 6'b000111;
12'd2420 : mem_out_dec = 6'b000111;
12'd2421 : mem_out_dec = 6'b000111;
12'd2422 : mem_out_dec = 6'b001000;
12'd2423 : mem_out_dec = 6'b001001;
12'd2424 : mem_out_dec = 6'b001001;
12'd2425 : mem_out_dec = 6'b001010;
12'd2426 : mem_out_dec = 6'b001010;
12'd2427 : mem_out_dec = 6'b001011;
12'd2428 : mem_out_dec = 6'b001100;
12'd2429 : mem_out_dec = 6'b001101;
12'd2430 : mem_out_dec = 6'b001101;
12'd2431 : mem_out_dec = 6'b001110;
12'd2432 : mem_out_dec = 6'b111111;
12'd2433 : mem_out_dec = 6'b111111;
12'd2434 : mem_out_dec = 6'b111111;
12'd2435 : mem_out_dec = 6'b111111;
12'd2436 : mem_out_dec = 6'b111111;
12'd2437 : mem_out_dec = 6'b111111;
12'd2438 : mem_out_dec = 6'b111111;
12'd2439 : mem_out_dec = 6'b111111;
12'd2440 : mem_out_dec = 6'b111111;
12'd2441 : mem_out_dec = 6'b111111;
12'd2442 : mem_out_dec = 6'b111111;
12'd2443 : mem_out_dec = 6'b111111;
12'd2444 : mem_out_dec = 6'b111111;
12'd2445 : mem_out_dec = 6'b111111;
12'd2446 : mem_out_dec = 6'b111111;
12'd2447 : mem_out_dec = 6'b111111;
12'd2448 : mem_out_dec = 6'b111111;
12'd2449 : mem_out_dec = 6'b111111;
12'd2450 : mem_out_dec = 6'b111111;
12'd2451 : mem_out_dec = 6'b111111;
12'd2452 : mem_out_dec = 6'b111111;
12'd2453 : mem_out_dec = 6'b111111;
12'd2454 : mem_out_dec = 6'b111111;
12'd2455 : mem_out_dec = 6'b111111;
12'd2456 : mem_out_dec = 6'b111111;
12'd2457 : mem_out_dec = 6'b111111;
12'd2458 : mem_out_dec = 6'b111111;
12'd2459 : mem_out_dec = 6'b111111;
12'd2460 : mem_out_dec = 6'b111111;
12'd2461 : mem_out_dec = 6'b111111;
12'd2462 : mem_out_dec = 6'b111111;
12'd2463 : mem_out_dec = 6'b111111;
12'd2464 : mem_out_dec = 6'b111111;
12'd2465 : mem_out_dec = 6'b111111;
12'd2466 : mem_out_dec = 6'b111111;
12'd2467 : mem_out_dec = 6'b111111;
12'd2468 : mem_out_dec = 6'b111111;
12'd2469 : mem_out_dec = 6'b111111;
12'd2470 : mem_out_dec = 6'b111111;
12'd2471 : mem_out_dec = 6'b111111;
12'd2472 : mem_out_dec = 6'b111111;
12'd2473 : mem_out_dec = 6'b111111;
12'd2474 : mem_out_dec = 6'b111111;
12'd2475 : mem_out_dec = 6'b111111;
12'd2476 : mem_out_dec = 6'b000101;
12'd2477 : mem_out_dec = 6'b000110;
12'd2478 : mem_out_dec = 6'b000111;
12'd2479 : mem_out_dec = 6'b000111;
12'd2480 : mem_out_dec = 6'b000110;
12'd2481 : mem_out_dec = 6'b000110;
12'd2482 : mem_out_dec = 6'b000110;
12'd2483 : mem_out_dec = 6'b000110;
12'd2484 : mem_out_dec = 6'b000110;
12'd2485 : mem_out_dec = 6'b000111;
12'd2486 : mem_out_dec = 6'b000111;
12'd2487 : mem_out_dec = 6'b001000;
12'd2488 : mem_out_dec = 6'b001001;
12'd2489 : mem_out_dec = 6'b001001;
12'd2490 : mem_out_dec = 6'b001010;
12'd2491 : mem_out_dec = 6'b001011;
12'd2492 : mem_out_dec = 6'b001011;
12'd2493 : mem_out_dec = 6'b001100;
12'd2494 : mem_out_dec = 6'b001101;
12'd2495 : mem_out_dec = 6'b001110;
12'd2496 : mem_out_dec = 6'b111111;
12'd2497 : mem_out_dec = 6'b111111;
12'd2498 : mem_out_dec = 6'b111111;
12'd2499 : mem_out_dec = 6'b111111;
12'd2500 : mem_out_dec = 6'b111111;
12'd2501 : mem_out_dec = 6'b111111;
12'd2502 : mem_out_dec = 6'b111111;
12'd2503 : mem_out_dec = 6'b111111;
12'd2504 : mem_out_dec = 6'b111111;
12'd2505 : mem_out_dec = 6'b111111;
12'd2506 : mem_out_dec = 6'b111111;
12'd2507 : mem_out_dec = 6'b111111;
12'd2508 : mem_out_dec = 6'b111111;
12'd2509 : mem_out_dec = 6'b111111;
12'd2510 : mem_out_dec = 6'b111111;
12'd2511 : mem_out_dec = 6'b111111;
12'd2512 : mem_out_dec = 6'b111111;
12'd2513 : mem_out_dec = 6'b111111;
12'd2514 : mem_out_dec = 6'b111111;
12'd2515 : mem_out_dec = 6'b111111;
12'd2516 : mem_out_dec = 6'b111111;
12'd2517 : mem_out_dec = 6'b111111;
12'd2518 : mem_out_dec = 6'b111111;
12'd2519 : mem_out_dec = 6'b111111;
12'd2520 : mem_out_dec = 6'b111111;
12'd2521 : mem_out_dec = 6'b111111;
12'd2522 : mem_out_dec = 6'b111111;
12'd2523 : mem_out_dec = 6'b111111;
12'd2524 : mem_out_dec = 6'b111111;
12'd2525 : mem_out_dec = 6'b111111;
12'd2526 : mem_out_dec = 6'b111111;
12'd2527 : mem_out_dec = 6'b111111;
12'd2528 : mem_out_dec = 6'b111111;
12'd2529 : mem_out_dec = 6'b111111;
12'd2530 : mem_out_dec = 6'b111111;
12'd2531 : mem_out_dec = 6'b111111;
12'd2532 : mem_out_dec = 6'b111111;
12'd2533 : mem_out_dec = 6'b111111;
12'd2534 : mem_out_dec = 6'b111111;
12'd2535 : mem_out_dec = 6'b111111;
12'd2536 : mem_out_dec = 6'b111111;
12'd2537 : mem_out_dec = 6'b111111;
12'd2538 : mem_out_dec = 6'b111111;
12'd2539 : mem_out_dec = 6'b111111;
12'd2540 : mem_out_dec = 6'b111111;
12'd2541 : mem_out_dec = 6'b000101;
12'd2542 : mem_out_dec = 6'b000110;
12'd2543 : mem_out_dec = 6'b000110;
12'd2544 : mem_out_dec = 6'b000110;
12'd2545 : mem_out_dec = 6'b000110;
12'd2546 : mem_out_dec = 6'b000101;
12'd2547 : mem_out_dec = 6'b000101;
12'd2548 : mem_out_dec = 6'b000110;
12'd2549 : mem_out_dec = 6'b000111;
12'd2550 : mem_out_dec = 6'b000111;
12'd2551 : mem_out_dec = 6'b001000;
12'd2552 : mem_out_dec = 6'b001000;
12'd2553 : mem_out_dec = 6'b001001;
12'd2554 : mem_out_dec = 6'b001010;
12'd2555 : mem_out_dec = 6'b001010;
12'd2556 : mem_out_dec = 6'b001011;
12'd2557 : mem_out_dec = 6'b001100;
12'd2558 : mem_out_dec = 6'b001101;
12'd2559 : mem_out_dec = 6'b001101;
12'd2560 : mem_out_dec = 6'b111111;
12'd2561 : mem_out_dec = 6'b111111;
12'd2562 : mem_out_dec = 6'b111111;
12'd2563 : mem_out_dec = 6'b111111;
12'd2564 : mem_out_dec = 6'b111111;
12'd2565 : mem_out_dec = 6'b111111;
12'd2566 : mem_out_dec = 6'b111111;
12'd2567 : mem_out_dec = 6'b111111;
12'd2568 : mem_out_dec = 6'b111111;
12'd2569 : mem_out_dec = 6'b111111;
12'd2570 : mem_out_dec = 6'b111111;
12'd2571 : mem_out_dec = 6'b111111;
12'd2572 : mem_out_dec = 6'b111111;
12'd2573 : mem_out_dec = 6'b111111;
12'd2574 : mem_out_dec = 6'b111111;
12'd2575 : mem_out_dec = 6'b111111;
12'd2576 : mem_out_dec = 6'b111111;
12'd2577 : mem_out_dec = 6'b111111;
12'd2578 : mem_out_dec = 6'b111111;
12'd2579 : mem_out_dec = 6'b111111;
12'd2580 : mem_out_dec = 6'b111111;
12'd2581 : mem_out_dec = 6'b111111;
12'd2582 : mem_out_dec = 6'b111111;
12'd2583 : mem_out_dec = 6'b111111;
12'd2584 : mem_out_dec = 6'b111111;
12'd2585 : mem_out_dec = 6'b111111;
12'd2586 : mem_out_dec = 6'b111111;
12'd2587 : mem_out_dec = 6'b111111;
12'd2588 : mem_out_dec = 6'b111111;
12'd2589 : mem_out_dec = 6'b111111;
12'd2590 : mem_out_dec = 6'b111111;
12'd2591 : mem_out_dec = 6'b111111;
12'd2592 : mem_out_dec = 6'b111111;
12'd2593 : mem_out_dec = 6'b111111;
12'd2594 : mem_out_dec = 6'b111111;
12'd2595 : mem_out_dec = 6'b111111;
12'd2596 : mem_out_dec = 6'b111111;
12'd2597 : mem_out_dec = 6'b111111;
12'd2598 : mem_out_dec = 6'b111111;
12'd2599 : mem_out_dec = 6'b111111;
12'd2600 : mem_out_dec = 6'b111111;
12'd2601 : mem_out_dec = 6'b111111;
12'd2602 : mem_out_dec = 6'b111111;
12'd2603 : mem_out_dec = 6'b111111;
12'd2604 : mem_out_dec = 6'b111111;
12'd2605 : mem_out_dec = 6'b111111;
12'd2606 : mem_out_dec = 6'b000100;
12'd2607 : mem_out_dec = 6'b000101;
12'd2608 : mem_out_dec = 6'b000100;
12'd2609 : mem_out_dec = 6'b000100;
12'd2610 : mem_out_dec = 6'b000100;
12'd2611 : mem_out_dec = 6'b000101;
12'd2612 : mem_out_dec = 6'b000101;
12'd2613 : mem_out_dec = 6'b000110;
12'd2614 : mem_out_dec = 6'b000111;
12'd2615 : mem_out_dec = 6'b000111;
12'd2616 : mem_out_dec = 6'b000111;
12'd2617 : mem_out_dec = 6'b001000;
12'd2618 : mem_out_dec = 6'b001001;
12'd2619 : mem_out_dec = 6'b001010;
12'd2620 : mem_out_dec = 6'b001010;
12'd2621 : mem_out_dec = 6'b001011;
12'd2622 : mem_out_dec = 6'b001100;
12'd2623 : mem_out_dec = 6'b001101;
12'd2624 : mem_out_dec = 6'b111111;
12'd2625 : mem_out_dec = 6'b111111;
12'd2626 : mem_out_dec = 6'b111111;
12'd2627 : mem_out_dec = 6'b111111;
12'd2628 : mem_out_dec = 6'b111111;
12'd2629 : mem_out_dec = 6'b111111;
12'd2630 : mem_out_dec = 6'b111111;
12'd2631 : mem_out_dec = 6'b111111;
12'd2632 : mem_out_dec = 6'b111111;
12'd2633 : mem_out_dec = 6'b111111;
12'd2634 : mem_out_dec = 6'b111111;
12'd2635 : mem_out_dec = 6'b111111;
12'd2636 : mem_out_dec = 6'b111111;
12'd2637 : mem_out_dec = 6'b111111;
12'd2638 : mem_out_dec = 6'b111111;
12'd2639 : mem_out_dec = 6'b111111;
12'd2640 : mem_out_dec = 6'b111111;
12'd2641 : mem_out_dec = 6'b111111;
12'd2642 : mem_out_dec = 6'b111111;
12'd2643 : mem_out_dec = 6'b111111;
12'd2644 : mem_out_dec = 6'b111111;
12'd2645 : mem_out_dec = 6'b111111;
12'd2646 : mem_out_dec = 6'b111111;
12'd2647 : mem_out_dec = 6'b111111;
12'd2648 : mem_out_dec = 6'b111111;
12'd2649 : mem_out_dec = 6'b111111;
12'd2650 : mem_out_dec = 6'b111111;
12'd2651 : mem_out_dec = 6'b111111;
12'd2652 : mem_out_dec = 6'b111111;
12'd2653 : mem_out_dec = 6'b111111;
12'd2654 : mem_out_dec = 6'b111111;
12'd2655 : mem_out_dec = 6'b111111;
12'd2656 : mem_out_dec = 6'b111111;
12'd2657 : mem_out_dec = 6'b111111;
12'd2658 : mem_out_dec = 6'b111111;
12'd2659 : mem_out_dec = 6'b111111;
12'd2660 : mem_out_dec = 6'b111111;
12'd2661 : mem_out_dec = 6'b111111;
12'd2662 : mem_out_dec = 6'b111111;
12'd2663 : mem_out_dec = 6'b111111;
12'd2664 : mem_out_dec = 6'b111111;
12'd2665 : mem_out_dec = 6'b111111;
12'd2666 : mem_out_dec = 6'b111111;
12'd2667 : mem_out_dec = 6'b111111;
12'd2668 : mem_out_dec = 6'b111111;
12'd2669 : mem_out_dec = 6'b111111;
12'd2670 : mem_out_dec = 6'b111111;
12'd2671 : mem_out_dec = 6'b000100;
12'd2672 : mem_out_dec = 6'b000011;
12'd2673 : mem_out_dec = 6'b000011;
12'd2674 : mem_out_dec = 6'b000100;
12'd2675 : mem_out_dec = 6'b000100;
12'd2676 : mem_out_dec = 6'b000101;
12'd2677 : mem_out_dec = 6'b000110;
12'd2678 : mem_out_dec = 6'b000110;
12'd2679 : mem_out_dec = 6'b000111;
12'd2680 : mem_out_dec = 6'b000111;
12'd2681 : mem_out_dec = 6'b001000;
12'd2682 : mem_out_dec = 6'b001001;
12'd2683 : mem_out_dec = 6'b001001;
12'd2684 : mem_out_dec = 6'b001010;
12'd2685 : mem_out_dec = 6'b001011;
12'd2686 : mem_out_dec = 6'b001100;
12'd2687 : mem_out_dec = 6'b001100;
12'd2688 : mem_out_dec = 6'b111111;
12'd2689 : mem_out_dec = 6'b111111;
12'd2690 : mem_out_dec = 6'b111111;
12'd2691 : mem_out_dec = 6'b111111;
12'd2692 : mem_out_dec = 6'b111111;
12'd2693 : mem_out_dec = 6'b111111;
12'd2694 : mem_out_dec = 6'b111111;
12'd2695 : mem_out_dec = 6'b111111;
12'd2696 : mem_out_dec = 6'b111111;
12'd2697 : mem_out_dec = 6'b111111;
12'd2698 : mem_out_dec = 6'b111111;
12'd2699 : mem_out_dec = 6'b111111;
12'd2700 : mem_out_dec = 6'b111111;
12'd2701 : mem_out_dec = 6'b111111;
12'd2702 : mem_out_dec = 6'b111111;
12'd2703 : mem_out_dec = 6'b111111;
12'd2704 : mem_out_dec = 6'b111111;
12'd2705 : mem_out_dec = 6'b111111;
12'd2706 : mem_out_dec = 6'b111111;
12'd2707 : mem_out_dec = 6'b111111;
12'd2708 : mem_out_dec = 6'b111111;
12'd2709 : mem_out_dec = 6'b111111;
12'd2710 : mem_out_dec = 6'b111111;
12'd2711 : mem_out_dec = 6'b111111;
12'd2712 : mem_out_dec = 6'b111111;
12'd2713 : mem_out_dec = 6'b111111;
12'd2714 : mem_out_dec = 6'b111111;
12'd2715 : mem_out_dec = 6'b111111;
12'd2716 : mem_out_dec = 6'b111111;
12'd2717 : mem_out_dec = 6'b111111;
12'd2718 : mem_out_dec = 6'b111111;
12'd2719 : mem_out_dec = 6'b111111;
12'd2720 : mem_out_dec = 6'b111111;
12'd2721 : mem_out_dec = 6'b111111;
12'd2722 : mem_out_dec = 6'b111111;
12'd2723 : mem_out_dec = 6'b111111;
12'd2724 : mem_out_dec = 6'b111111;
12'd2725 : mem_out_dec = 6'b111111;
12'd2726 : mem_out_dec = 6'b111111;
12'd2727 : mem_out_dec = 6'b111111;
12'd2728 : mem_out_dec = 6'b111111;
12'd2729 : mem_out_dec = 6'b111111;
12'd2730 : mem_out_dec = 6'b111111;
12'd2731 : mem_out_dec = 6'b111111;
12'd2732 : mem_out_dec = 6'b111111;
12'd2733 : mem_out_dec = 6'b111111;
12'd2734 : mem_out_dec = 6'b111111;
12'd2735 : mem_out_dec = 6'b111111;
12'd2736 : mem_out_dec = 6'b000011;
12'd2737 : mem_out_dec = 6'b000011;
12'd2738 : mem_out_dec = 6'b000100;
12'd2739 : mem_out_dec = 6'b000100;
12'd2740 : mem_out_dec = 6'b000101;
12'd2741 : mem_out_dec = 6'b000101;
12'd2742 : mem_out_dec = 6'b000110;
12'd2743 : mem_out_dec = 6'b000111;
12'd2744 : mem_out_dec = 6'b000111;
12'd2745 : mem_out_dec = 6'b001000;
12'd2746 : mem_out_dec = 6'b001000;
12'd2747 : mem_out_dec = 6'b001001;
12'd2748 : mem_out_dec = 6'b001010;
12'd2749 : mem_out_dec = 6'b001011;
12'd2750 : mem_out_dec = 6'b001011;
12'd2751 : mem_out_dec = 6'b001100;
12'd2752 : mem_out_dec = 6'b111111;
12'd2753 : mem_out_dec = 6'b111111;
12'd2754 : mem_out_dec = 6'b111111;
12'd2755 : mem_out_dec = 6'b111111;
12'd2756 : mem_out_dec = 6'b111111;
12'd2757 : mem_out_dec = 6'b111111;
12'd2758 : mem_out_dec = 6'b111111;
12'd2759 : mem_out_dec = 6'b111111;
12'd2760 : mem_out_dec = 6'b111111;
12'd2761 : mem_out_dec = 6'b111111;
12'd2762 : mem_out_dec = 6'b111111;
12'd2763 : mem_out_dec = 6'b111111;
12'd2764 : mem_out_dec = 6'b111111;
12'd2765 : mem_out_dec = 6'b111111;
12'd2766 : mem_out_dec = 6'b111111;
12'd2767 : mem_out_dec = 6'b111111;
12'd2768 : mem_out_dec = 6'b111111;
12'd2769 : mem_out_dec = 6'b111111;
12'd2770 : mem_out_dec = 6'b111111;
12'd2771 : mem_out_dec = 6'b111111;
12'd2772 : mem_out_dec = 6'b111111;
12'd2773 : mem_out_dec = 6'b111111;
12'd2774 : mem_out_dec = 6'b111111;
12'd2775 : mem_out_dec = 6'b111111;
12'd2776 : mem_out_dec = 6'b111111;
12'd2777 : mem_out_dec = 6'b111111;
12'd2778 : mem_out_dec = 6'b111111;
12'd2779 : mem_out_dec = 6'b111111;
12'd2780 : mem_out_dec = 6'b111111;
12'd2781 : mem_out_dec = 6'b111111;
12'd2782 : mem_out_dec = 6'b111111;
12'd2783 : mem_out_dec = 6'b111111;
12'd2784 : mem_out_dec = 6'b111111;
12'd2785 : mem_out_dec = 6'b111111;
12'd2786 : mem_out_dec = 6'b111111;
12'd2787 : mem_out_dec = 6'b111111;
12'd2788 : mem_out_dec = 6'b111111;
12'd2789 : mem_out_dec = 6'b111111;
12'd2790 : mem_out_dec = 6'b111111;
12'd2791 : mem_out_dec = 6'b111111;
12'd2792 : mem_out_dec = 6'b111111;
12'd2793 : mem_out_dec = 6'b111111;
12'd2794 : mem_out_dec = 6'b111111;
12'd2795 : mem_out_dec = 6'b111111;
12'd2796 : mem_out_dec = 6'b111111;
12'd2797 : mem_out_dec = 6'b111111;
12'd2798 : mem_out_dec = 6'b111111;
12'd2799 : mem_out_dec = 6'b111111;
12'd2800 : mem_out_dec = 6'b111111;
12'd2801 : mem_out_dec = 6'b000011;
12'd2802 : mem_out_dec = 6'b000011;
12'd2803 : mem_out_dec = 6'b000100;
12'd2804 : mem_out_dec = 6'b000101;
12'd2805 : mem_out_dec = 6'b000101;
12'd2806 : mem_out_dec = 6'b000110;
12'd2807 : mem_out_dec = 6'b000111;
12'd2808 : mem_out_dec = 6'b000111;
12'd2809 : mem_out_dec = 6'b000111;
12'd2810 : mem_out_dec = 6'b001000;
12'd2811 : mem_out_dec = 6'b001001;
12'd2812 : mem_out_dec = 6'b001010;
12'd2813 : mem_out_dec = 6'b001010;
12'd2814 : mem_out_dec = 6'b001011;
12'd2815 : mem_out_dec = 6'b001100;
12'd2816 : mem_out_dec = 6'b111111;
12'd2817 : mem_out_dec = 6'b111111;
12'd2818 : mem_out_dec = 6'b111111;
12'd2819 : mem_out_dec = 6'b111111;
12'd2820 : mem_out_dec = 6'b111111;
12'd2821 : mem_out_dec = 6'b111111;
12'd2822 : mem_out_dec = 6'b111111;
12'd2823 : mem_out_dec = 6'b111111;
12'd2824 : mem_out_dec = 6'b111111;
12'd2825 : mem_out_dec = 6'b111111;
12'd2826 : mem_out_dec = 6'b111111;
12'd2827 : mem_out_dec = 6'b111111;
12'd2828 : mem_out_dec = 6'b111111;
12'd2829 : mem_out_dec = 6'b111111;
12'd2830 : mem_out_dec = 6'b111111;
12'd2831 : mem_out_dec = 6'b111111;
12'd2832 : mem_out_dec = 6'b111111;
12'd2833 : mem_out_dec = 6'b111111;
12'd2834 : mem_out_dec = 6'b111111;
12'd2835 : mem_out_dec = 6'b111111;
12'd2836 : mem_out_dec = 6'b111111;
12'd2837 : mem_out_dec = 6'b111111;
12'd2838 : mem_out_dec = 6'b111111;
12'd2839 : mem_out_dec = 6'b111111;
12'd2840 : mem_out_dec = 6'b111111;
12'd2841 : mem_out_dec = 6'b111111;
12'd2842 : mem_out_dec = 6'b111111;
12'd2843 : mem_out_dec = 6'b111111;
12'd2844 : mem_out_dec = 6'b111111;
12'd2845 : mem_out_dec = 6'b111111;
12'd2846 : mem_out_dec = 6'b111111;
12'd2847 : mem_out_dec = 6'b111111;
12'd2848 : mem_out_dec = 6'b111111;
12'd2849 : mem_out_dec = 6'b111111;
12'd2850 : mem_out_dec = 6'b111111;
12'd2851 : mem_out_dec = 6'b111111;
12'd2852 : mem_out_dec = 6'b111111;
12'd2853 : mem_out_dec = 6'b111111;
12'd2854 : mem_out_dec = 6'b111111;
12'd2855 : mem_out_dec = 6'b111111;
12'd2856 : mem_out_dec = 6'b111111;
12'd2857 : mem_out_dec = 6'b111111;
12'd2858 : mem_out_dec = 6'b111111;
12'd2859 : mem_out_dec = 6'b111111;
12'd2860 : mem_out_dec = 6'b111111;
12'd2861 : mem_out_dec = 6'b111111;
12'd2862 : mem_out_dec = 6'b111111;
12'd2863 : mem_out_dec = 6'b111111;
12'd2864 : mem_out_dec = 6'b111111;
12'd2865 : mem_out_dec = 6'b111111;
12'd2866 : mem_out_dec = 6'b000011;
12'd2867 : mem_out_dec = 6'b000100;
12'd2868 : mem_out_dec = 6'b000100;
12'd2869 : mem_out_dec = 6'b000101;
12'd2870 : mem_out_dec = 6'b000110;
12'd2871 : mem_out_dec = 6'b000110;
12'd2872 : mem_out_dec = 6'b000110;
12'd2873 : mem_out_dec = 6'b000111;
12'd2874 : mem_out_dec = 6'b001000;
12'd2875 : mem_out_dec = 6'b001001;
12'd2876 : mem_out_dec = 6'b001001;
12'd2877 : mem_out_dec = 6'b001010;
12'd2878 : mem_out_dec = 6'b001011;
12'd2879 : mem_out_dec = 6'b001100;
12'd2880 : mem_out_dec = 6'b111111;
12'd2881 : mem_out_dec = 6'b111111;
12'd2882 : mem_out_dec = 6'b111111;
12'd2883 : mem_out_dec = 6'b111111;
12'd2884 : mem_out_dec = 6'b111111;
12'd2885 : mem_out_dec = 6'b111111;
12'd2886 : mem_out_dec = 6'b111111;
12'd2887 : mem_out_dec = 6'b111111;
12'd2888 : mem_out_dec = 6'b111111;
12'd2889 : mem_out_dec = 6'b111111;
12'd2890 : mem_out_dec = 6'b111111;
12'd2891 : mem_out_dec = 6'b111111;
12'd2892 : mem_out_dec = 6'b111111;
12'd2893 : mem_out_dec = 6'b111111;
12'd2894 : mem_out_dec = 6'b111111;
12'd2895 : mem_out_dec = 6'b111111;
12'd2896 : mem_out_dec = 6'b111111;
12'd2897 : mem_out_dec = 6'b111111;
12'd2898 : mem_out_dec = 6'b111111;
12'd2899 : mem_out_dec = 6'b111111;
12'd2900 : mem_out_dec = 6'b111111;
12'd2901 : mem_out_dec = 6'b111111;
12'd2902 : mem_out_dec = 6'b111111;
12'd2903 : mem_out_dec = 6'b111111;
12'd2904 : mem_out_dec = 6'b111111;
12'd2905 : mem_out_dec = 6'b111111;
12'd2906 : mem_out_dec = 6'b111111;
12'd2907 : mem_out_dec = 6'b111111;
12'd2908 : mem_out_dec = 6'b111111;
12'd2909 : mem_out_dec = 6'b111111;
12'd2910 : mem_out_dec = 6'b111111;
12'd2911 : mem_out_dec = 6'b111111;
12'd2912 : mem_out_dec = 6'b111111;
12'd2913 : mem_out_dec = 6'b111111;
12'd2914 : mem_out_dec = 6'b111111;
12'd2915 : mem_out_dec = 6'b111111;
12'd2916 : mem_out_dec = 6'b111111;
12'd2917 : mem_out_dec = 6'b111111;
12'd2918 : mem_out_dec = 6'b111111;
12'd2919 : mem_out_dec = 6'b111111;
12'd2920 : mem_out_dec = 6'b111111;
12'd2921 : mem_out_dec = 6'b111111;
12'd2922 : mem_out_dec = 6'b111111;
12'd2923 : mem_out_dec = 6'b111111;
12'd2924 : mem_out_dec = 6'b111111;
12'd2925 : mem_out_dec = 6'b111111;
12'd2926 : mem_out_dec = 6'b111111;
12'd2927 : mem_out_dec = 6'b111111;
12'd2928 : mem_out_dec = 6'b111111;
12'd2929 : mem_out_dec = 6'b111111;
12'd2930 : mem_out_dec = 6'b111111;
12'd2931 : mem_out_dec = 6'b000100;
12'd2932 : mem_out_dec = 6'b000100;
12'd2933 : mem_out_dec = 6'b000101;
12'd2934 : mem_out_dec = 6'b000101;
12'd2935 : mem_out_dec = 6'b000110;
12'd2936 : mem_out_dec = 6'b000110;
12'd2937 : mem_out_dec = 6'b000111;
12'd2938 : mem_out_dec = 6'b001000;
12'd2939 : mem_out_dec = 6'b001000;
12'd2940 : mem_out_dec = 6'b001001;
12'd2941 : mem_out_dec = 6'b001010;
12'd2942 : mem_out_dec = 6'b001011;
12'd2943 : mem_out_dec = 6'b001011;
12'd2944 : mem_out_dec = 6'b111111;
12'd2945 : mem_out_dec = 6'b111111;
12'd2946 : mem_out_dec = 6'b111111;
12'd2947 : mem_out_dec = 6'b111111;
12'd2948 : mem_out_dec = 6'b111111;
12'd2949 : mem_out_dec = 6'b111111;
12'd2950 : mem_out_dec = 6'b111111;
12'd2951 : mem_out_dec = 6'b111111;
12'd2952 : mem_out_dec = 6'b111111;
12'd2953 : mem_out_dec = 6'b111111;
12'd2954 : mem_out_dec = 6'b111111;
12'd2955 : mem_out_dec = 6'b111111;
12'd2956 : mem_out_dec = 6'b111111;
12'd2957 : mem_out_dec = 6'b111111;
12'd2958 : mem_out_dec = 6'b111111;
12'd2959 : mem_out_dec = 6'b111111;
12'd2960 : mem_out_dec = 6'b111111;
12'd2961 : mem_out_dec = 6'b111111;
12'd2962 : mem_out_dec = 6'b111111;
12'd2963 : mem_out_dec = 6'b111111;
12'd2964 : mem_out_dec = 6'b111111;
12'd2965 : mem_out_dec = 6'b111111;
12'd2966 : mem_out_dec = 6'b111111;
12'd2967 : mem_out_dec = 6'b111111;
12'd2968 : mem_out_dec = 6'b111111;
12'd2969 : mem_out_dec = 6'b111111;
12'd2970 : mem_out_dec = 6'b111111;
12'd2971 : mem_out_dec = 6'b111111;
12'd2972 : mem_out_dec = 6'b111111;
12'd2973 : mem_out_dec = 6'b111111;
12'd2974 : mem_out_dec = 6'b111111;
12'd2975 : mem_out_dec = 6'b111111;
12'd2976 : mem_out_dec = 6'b111111;
12'd2977 : mem_out_dec = 6'b111111;
12'd2978 : mem_out_dec = 6'b111111;
12'd2979 : mem_out_dec = 6'b111111;
12'd2980 : mem_out_dec = 6'b111111;
12'd2981 : mem_out_dec = 6'b111111;
12'd2982 : mem_out_dec = 6'b111111;
12'd2983 : mem_out_dec = 6'b111111;
12'd2984 : mem_out_dec = 6'b111111;
12'd2985 : mem_out_dec = 6'b111111;
12'd2986 : mem_out_dec = 6'b111111;
12'd2987 : mem_out_dec = 6'b111111;
12'd2988 : mem_out_dec = 6'b111111;
12'd2989 : mem_out_dec = 6'b111111;
12'd2990 : mem_out_dec = 6'b111111;
12'd2991 : mem_out_dec = 6'b111111;
12'd2992 : mem_out_dec = 6'b111111;
12'd2993 : mem_out_dec = 6'b111111;
12'd2994 : mem_out_dec = 6'b111111;
12'd2995 : mem_out_dec = 6'b111111;
12'd2996 : mem_out_dec = 6'b000100;
12'd2997 : mem_out_dec = 6'b000101;
12'd2998 : mem_out_dec = 6'b000101;
12'd2999 : mem_out_dec = 6'b000110;
12'd3000 : mem_out_dec = 6'b000110;
12'd3001 : mem_out_dec = 6'b000111;
12'd3002 : mem_out_dec = 6'b000111;
12'd3003 : mem_out_dec = 6'b001000;
12'd3004 : mem_out_dec = 6'b001001;
12'd3005 : mem_out_dec = 6'b001010;
12'd3006 : mem_out_dec = 6'b001010;
12'd3007 : mem_out_dec = 6'b001011;
12'd3008 : mem_out_dec = 6'b111111;
12'd3009 : mem_out_dec = 6'b111111;
12'd3010 : mem_out_dec = 6'b111111;
12'd3011 : mem_out_dec = 6'b111111;
12'd3012 : mem_out_dec = 6'b111111;
12'd3013 : mem_out_dec = 6'b111111;
12'd3014 : mem_out_dec = 6'b111111;
12'd3015 : mem_out_dec = 6'b111111;
12'd3016 : mem_out_dec = 6'b111111;
12'd3017 : mem_out_dec = 6'b111111;
12'd3018 : mem_out_dec = 6'b111111;
12'd3019 : mem_out_dec = 6'b111111;
12'd3020 : mem_out_dec = 6'b111111;
12'd3021 : mem_out_dec = 6'b111111;
12'd3022 : mem_out_dec = 6'b111111;
12'd3023 : mem_out_dec = 6'b111111;
12'd3024 : mem_out_dec = 6'b111111;
12'd3025 : mem_out_dec = 6'b111111;
12'd3026 : mem_out_dec = 6'b111111;
12'd3027 : mem_out_dec = 6'b111111;
12'd3028 : mem_out_dec = 6'b111111;
12'd3029 : mem_out_dec = 6'b111111;
12'd3030 : mem_out_dec = 6'b111111;
12'd3031 : mem_out_dec = 6'b111111;
12'd3032 : mem_out_dec = 6'b111111;
12'd3033 : mem_out_dec = 6'b111111;
12'd3034 : mem_out_dec = 6'b111111;
12'd3035 : mem_out_dec = 6'b111111;
12'd3036 : mem_out_dec = 6'b111111;
12'd3037 : mem_out_dec = 6'b111111;
12'd3038 : mem_out_dec = 6'b111111;
12'd3039 : mem_out_dec = 6'b111111;
12'd3040 : mem_out_dec = 6'b111111;
12'd3041 : mem_out_dec = 6'b111111;
12'd3042 : mem_out_dec = 6'b111111;
12'd3043 : mem_out_dec = 6'b111111;
12'd3044 : mem_out_dec = 6'b111111;
12'd3045 : mem_out_dec = 6'b111111;
12'd3046 : mem_out_dec = 6'b111111;
12'd3047 : mem_out_dec = 6'b111111;
12'd3048 : mem_out_dec = 6'b111111;
12'd3049 : mem_out_dec = 6'b111111;
12'd3050 : mem_out_dec = 6'b111111;
12'd3051 : mem_out_dec = 6'b111111;
12'd3052 : mem_out_dec = 6'b111111;
12'd3053 : mem_out_dec = 6'b111111;
12'd3054 : mem_out_dec = 6'b111111;
12'd3055 : mem_out_dec = 6'b111111;
12'd3056 : mem_out_dec = 6'b111111;
12'd3057 : mem_out_dec = 6'b111111;
12'd3058 : mem_out_dec = 6'b111111;
12'd3059 : mem_out_dec = 6'b111111;
12'd3060 : mem_out_dec = 6'b111111;
12'd3061 : mem_out_dec = 6'b000100;
12'd3062 : mem_out_dec = 6'b000101;
12'd3063 : mem_out_dec = 6'b000110;
12'd3064 : mem_out_dec = 6'b000110;
12'd3065 : mem_out_dec = 6'b000111;
12'd3066 : mem_out_dec = 6'b000111;
12'd3067 : mem_out_dec = 6'b001000;
12'd3068 : mem_out_dec = 6'b001001;
12'd3069 : mem_out_dec = 6'b001001;
12'd3070 : mem_out_dec = 6'b001010;
12'd3071 : mem_out_dec = 6'b001011;
12'd3072 : mem_out_dec = 6'b111111;
12'd3073 : mem_out_dec = 6'b111111;
12'd3074 : mem_out_dec = 6'b111111;
12'd3075 : mem_out_dec = 6'b111111;
12'd3076 : mem_out_dec = 6'b111111;
12'd3077 : mem_out_dec = 6'b111111;
12'd3078 : mem_out_dec = 6'b111111;
12'd3079 : mem_out_dec = 6'b111111;
12'd3080 : mem_out_dec = 6'b111111;
12'd3081 : mem_out_dec = 6'b111111;
12'd3082 : mem_out_dec = 6'b111111;
12'd3083 : mem_out_dec = 6'b111111;
12'd3084 : mem_out_dec = 6'b111111;
12'd3085 : mem_out_dec = 6'b111111;
12'd3086 : mem_out_dec = 6'b111111;
12'd3087 : mem_out_dec = 6'b111111;
12'd3088 : mem_out_dec = 6'b111111;
12'd3089 : mem_out_dec = 6'b111111;
12'd3090 : mem_out_dec = 6'b111111;
12'd3091 : mem_out_dec = 6'b111111;
12'd3092 : mem_out_dec = 6'b111111;
12'd3093 : mem_out_dec = 6'b111111;
12'd3094 : mem_out_dec = 6'b111111;
12'd3095 : mem_out_dec = 6'b111111;
12'd3096 : mem_out_dec = 6'b111111;
12'd3097 : mem_out_dec = 6'b111111;
12'd3098 : mem_out_dec = 6'b111111;
12'd3099 : mem_out_dec = 6'b111111;
12'd3100 : mem_out_dec = 6'b111111;
12'd3101 : mem_out_dec = 6'b111111;
12'd3102 : mem_out_dec = 6'b111111;
12'd3103 : mem_out_dec = 6'b111111;
12'd3104 : mem_out_dec = 6'b111111;
12'd3105 : mem_out_dec = 6'b111111;
12'd3106 : mem_out_dec = 6'b111111;
12'd3107 : mem_out_dec = 6'b111111;
12'd3108 : mem_out_dec = 6'b111111;
12'd3109 : mem_out_dec = 6'b111111;
12'd3110 : mem_out_dec = 6'b111111;
12'd3111 : mem_out_dec = 6'b111111;
12'd3112 : mem_out_dec = 6'b111111;
12'd3113 : mem_out_dec = 6'b111111;
12'd3114 : mem_out_dec = 6'b111111;
12'd3115 : mem_out_dec = 6'b111111;
12'd3116 : mem_out_dec = 6'b111111;
12'd3117 : mem_out_dec = 6'b111111;
12'd3118 : mem_out_dec = 6'b111111;
12'd3119 : mem_out_dec = 6'b111111;
12'd3120 : mem_out_dec = 6'b111111;
12'd3121 : mem_out_dec = 6'b111111;
12'd3122 : mem_out_dec = 6'b111111;
12'd3123 : mem_out_dec = 6'b111111;
12'd3124 : mem_out_dec = 6'b111111;
12'd3125 : mem_out_dec = 6'b111111;
12'd3126 : mem_out_dec = 6'b000100;
12'd3127 : mem_out_dec = 6'b000101;
12'd3128 : mem_out_dec = 6'b000101;
12'd3129 : mem_out_dec = 6'b000110;
12'd3130 : mem_out_dec = 6'b000110;
12'd3131 : mem_out_dec = 6'b000111;
12'd3132 : mem_out_dec = 6'b001000;
12'd3133 : mem_out_dec = 6'b001000;
12'd3134 : mem_out_dec = 6'b001001;
12'd3135 : mem_out_dec = 6'b001010;
12'd3136 : mem_out_dec = 6'b111111;
12'd3137 : mem_out_dec = 6'b111111;
12'd3138 : mem_out_dec = 6'b111111;
12'd3139 : mem_out_dec = 6'b111111;
12'd3140 : mem_out_dec = 6'b111111;
12'd3141 : mem_out_dec = 6'b111111;
12'd3142 : mem_out_dec = 6'b111111;
12'd3143 : mem_out_dec = 6'b111111;
12'd3144 : mem_out_dec = 6'b111111;
12'd3145 : mem_out_dec = 6'b111111;
12'd3146 : mem_out_dec = 6'b111111;
12'd3147 : mem_out_dec = 6'b111111;
12'd3148 : mem_out_dec = 6'b111111;
12'd3149 : mem_out_dec = 6'b111111;
12'd3150 : mem_out_dec = 6'b111111;
12'd3151 : mem_out_dec = 6'b111111;
12'd3152 : mem_out_dec = 6'b111111;
12'd3153 : mem_out_dec = 6'b111111;
12'd3154 : mem_out_dec = 6'b111111;
12'd3155 : mem_out_dec = 6'b111111;
12'd3156 : mem_out_dec = 6'b111111;
12'd3157 : mem_out_dec = 6'b111111;
12'd3158 : mem_out_dec = 6'b111111;
12'd3159 : mem_out_dec = 6'b111111;
12'd3160 : mem_out_dec = 6'b111111;
12'd3161 : mem_out_dec = 6'b111111;
12'd3162 : mem_out_dec = 6'b111111;
12'd3163 : mem_out_dec = 6'b111111;
12'd3164 : mem_out_dec = 6'b111111;
12'd3165 : mem_out_dec = 6'b111111;
12'd3166 : mem_out_dec = 6'b111111;
12'd3167 : mem_out_dec = 6'b111111;
12'd3168 : mem_out_dec = 6'b111111;
12'd3169 : mem_out_dec = 6'b111111;
12'd3170 : mem_out_dec = 6'b111111;
12'd3171 : mem_out_dec = 6'b111111;
12'd3172 : mem_out_dec = 6'b111111;
12'd3173 : mem_out_dec = 6'b111111;
12'd3174 : mem_out_dec = 6'b111111;
12'd3175 : mem_out_dec = 6'b111111;
12'd3176 : mem_out_dec = 6'b111111;
12'd3177 : mem_out_dec = 6'b111111;
12'd3178 : mem_out_dec = 6'b111111;
12'd3179 : mem_out_dec = 6'b111111;
12'd3180 : mem_out_dec = 6'b111111;
12'd3181 : mem_out_dec = 6'b111111;
12'd3182 : mem_out_dec = 6'b111111;
12'd3183 : mem_out_dec = 6'b111111;
12'd3184 : mem_out_dec = 6'b111111;
12'd3185 : mem_out_dec = 6'b111111;
12'd3186 : mem_out_dec = 6'b111111;
12'd3187 : mem_out_dec = 6'b111111;
12'd3188 : mem_out_dec = 6'b111111;
12'd3189 : mem_out_dec = 6'b111111;
12'd3190 : mem_out_dec = 6'b111111;
12'd3191 : mem_out_dec = 6'b000100;
12'd3192 : mem_out_dec = 6'b000100;
12'd3193 : mem_out_dec = 6'b000101;
12'd3194 : mem_out_dec = 6'b000110;
12'd3195 : mem_out_dec = 6'b000110;
12'd3196 : mem_out_dec = 6'b000111;
12'd3197 : mem_out_dec = 6'b001000;
12'd3198 : mem_out_dec = 6'b001000;
12'd3199 : mem_out_dec = 6'b001001;
12'd3200 : mem_out_dec = 6'b111111;
12'd3201 : mem_out_dec = 6'b111111;
12'd3202 : mem_out_dec = 6'b111111;
12'd3203 : mem_out_dec = 6'b111111;
12'd3204 : mem_out_dec = 6'b111111;
12'd3205 : mem_out_dec = 6'b111111;
12'd3206 : mem_out_dec = 6'b111111;
12'd3207 : mem_out_dec = 6'b111111;
12'd3208 : mem_out_dec = 6'b111111;
12'd3209 : mem_out_dec = 6'b111111;
12'd3210 : mem_out_dec = 6'b111111;
12'd3211 : mem_out_dec = 6'b111111;
12'd3212 : mem_out_dec = 6'b111111;
12'd3213 : mem_out_dec = 6'b111111;
12'd3214 : mem_out_dec = 6'b111111;
12'd3215 : mem_out_dec = 6'b111111;
12'd3216 : mem_out_dec = 6'b111111;
12'd3217 : mem_out_dec = 6'b111111;
12'd3218 : mem_out_dec = 6'b111111;
12'd3219 : mem_out_dec = 6'b111111;
12'd3220 : mem_out_dec = 6'b111111;
12'd3221 : mem_out_dec = 6'b111111;
12'd3222 : mem_out_dec = 6'b111111;
12'd3223 : mem_out_dec = 6'b111111;
12'd3224 : mem_out_dec = 6'b111111;
12'd3225 : mem_out_dec = 6'b111111;
12'd3226 : mem_out_dec = 6'b111111;
12'd3227 : mem_out_dec = 6'b111111;
12'd3228 : mem_out_dec = 6'b111111;
12'd3229 : mem_out_dec = 6'b111111;
12'd3230 : mem_out_dec = 6'b111111;
12'd3231 : mem_out_dec = 6'b111111;
12'd3232 : mem_out_dec = 6'b111111;
12'd3233 : mem_out_dec = 6'b111111;
12'd3234 : mem_out_dec = 6'b111111;
12'd3235 : mem_out_dec = 6'b111111;
12'd3236 : mem_out_dec = 6'b111111;
12'd3237 : mem_out_dec = 6'b111111;
12'd3238 : mem_out_dec = 6'b111111;
12'd3239 : mem_out_dec = 6'b111111;
12'd3240 : mem_out_dec = 6'b111111;
12'd3241 : mem_out_dec = 6'b111111;
12'd3242 : mem_out_dec = 6'b111111;
12'd3243 : mem_out_dec = 6'b111111;
12'd3244 : mem_out_dec = 6'b111111;
12'd3245 : mem_out_dec = 6'b111111;
12'd3246 : mem_out_dec = 6'b111111;
12'd3247 : mem_out_dec = 6'b111111;
12'd3248 : mem_out_dec = 6'b111111;
12'd3249 : mem_out_dec = 6'b111111;
12'd3250 : mem_out_dec = 6'b111111;
12'd3251 : mem_out_dec = 6'b111111;
12'd3252 : mem_out_dec = 6'b111111;
12'd3253 : mem_out_dec = 6'b111111;
12'd3254 : mem_out_dec = 6'b111111;
12'd3255 : mem_out_dec = 6'b111111;
12'd3256 : mem_out_dec = 6'b000100;
12'd3257 : mem_out_dec = 6'b000100;
12'd3258 : mem_out_dec = 6'b000101;
12'd3259 : mem_out_dec = 6'b000110;
12'd3260 : mem_out_dec = 6'b000110;
12'd3261 : mem_out_dec = 6'b000111;
12'd3262 : mem_out_dec = 6'b001000;
12'd3263 : mem_out_dec = 6'b001001;
12'd3264 : mem_out_dec = 6'b111111;
12'd3265 : mem_out_dec = 6'b111111;
12'd3266 : mem_out_dec = 6'b111111;
12'd3267 : mem_out_dec = 6'b111111;
12'd3268 : mem_out_dec = 6'b111111;
12'd3269 : mem_out_dec = 6'b111111;
12'd3270 : mem_out_dec = 6'b111111;
12'd3271 : mem_out_dec = 6'b111111;
12'd3272 : mem_out_dec = 6'b111111;
12'd3273 : mem_out_dec = 6'b111111;
12'd3274 : mem_out_dec = 6'b111111;
12'd3275 : mem_out_dec = 6'b111111;
12'd3276 : mem_out_dec = 6'b111111;
12'd3277 : mem_out_dec = 6'b111111;
12'd3278 : mem_out_dec = 6'b111111;
12'd3279 : mem_out_dec = 6'b111111;
12'd3280 : mem_out_dec = 6'b111111;
12'd3281 : mem_out_dec = 6'b111111;
12'd3282 : mem_out_dec = 6'b111111;
12'd3283 : mem_out_dec = 6'b111111;
12'd3284 : mem_out_dec = 6'b111111;
12'd3285 : mem_out_dec = 6'b111111;
12'd3286 : mem_out_dec = 6'b111111;
12'd3287 : mem_out_dec = 6'b111111;
12'd3288 : mem_out_dec = 6'b111111;
12'd3289 : mem_out_dec = 6'b111111;
12'd3290 : mem_out_dec = 6'b111111;
12'd3291 : mem_out_dec = 6'b111111;
12'd3292 : mem_out_dec = 6'b111111;
12'd3293 : mem_out_dec = 6'b111111;
12'd3294 : mem_out_dec = 6'b111111;
12'd3295 : mem_out_dec = 6'b111111;
12'd3296 : mem_out_dec = 6'b111111;
12'd3297 : mem_out_dec = 6'b111111;
12'd3298 : mem_out_dec = 6'b111111;
12'd3299 : mem_out_dec = 6'b111111;
12'd3300 : mem_out_dec = 6'b111111;
12'd3301 : mem_out_dec = 6'b111111;
12'd3302 : mem_out_dec = 6'b111111;
12'd3303 : mem_out_dec = 6'b111111;
12'd3304 : mem_out_dec = 6'b111111;
12'd3305 : mem_out_dec = 6'b111111;
12'd3306 : mem_out_dec = 6'b111111;
12'd3307 : mem_out_dec = 6'b111111;
12'd3308 : mem_out_dec = 6'b111111;
12'd3309 : mem_out_dec = 6'b111111;
12'd3310 : mem_out_dec = 6'b111111;
12'd3311 : mem_out_dec = 6'b111111;
12'd3312 : mem_out_dec = 6'b111111;
12'd3313 : mem_out_dec = 6'b111111;
12'd3314 : mem_out_dec = 6'b111111;
12'd3315 : mem_out_dec = 6'b111111;
12'd3316 : mem_out_dec = 6'b111111;
12'd3317 : mem_out_dec = 6'b111111;
12'd3318 : mem_out_dec = 6'b111111;
12'd3319 : mem_out_dec = 6'b111111;
12'd3320 : mem_out_dec = 6'b111111;
12'd3321 : mem_out_dec = 6'b000100;
12'd3322 : mem_out_dec = 6'b000100;
12'd3323 : mem_out_dec = 6'b000101;
12'd3324 : mem_out_dec = 6'b000110;
12'd3325 : mem_out_dec = 6'b000111;
12'd3326 : mem_out_dec = 6'b001000;
12'd3327 : mem_out_dec = 6'b001000;
12'd3328 : mem_out_dec = 6'b111111;
12'd3329 : mem_out_dec = 6'b111111;
12'd3330 : mem_out_dec = 6'b111111;
12'd3331 : mem_out_dec = 6'b111111;
12'd3332 : mem_out_dec = 6'b111111;
12'd3333 : mem_out_dec = 6'b111111;
12'd3334 : mem_out_dec = 6'b111111;
12'd3335 : mem_out_dec = 6'b111111;
12'd3336 : mem_out_dec = 6'b111111;
12'd3337 : mem_out_dec = 6'b111111;
12'd3338 : mem_out_dec = 6'b111111;
12'd3339 : mem_out_dec = 6'b111111;
12'd3340 : mem_out_dec = 6'b111111;
12'd3341 : mem_out_dec = 6'b111111;
12'd3342 : mem_out_dec = 6'b111111;
12'd3343 : mem_out_dec = 6'b111111;
12'd3344 : mem_out_dec = 6'b111111;
12'd3345 : mem_out_dec = 6'b111111;
12'd3346 : mem_out_dec = 6'b111111;
12'd3347 : mem_out_dec = 6'b111111;
12'd3348 : mem_out_dec = 6'b111111;
12'd3349 : mem_out_dec = 6'b111111;
12'd3350 : mem_out_dec = 6'b111111;
12'd3351 : mem_out_dec = 6'b111111;
12'd3352 : mem_out_dec = 6'b111111;
12'd3353 : mem_out_dec = 6'b111111;
12'd3354 : mem_out_dec = 6'b111111;
12'd3355 : mem_out_dec = 6'b111111;
12'd3356 : mem_out_dec = 6'b111111;
12'd3357 : mem_out_dec = 6'b111111;
12'd3358 : mem_out_dec = 6'b111111;
12'd3359 : mem_out_dec = 6'b111111;
12'd3360 : mem_out_dec = 6'b111111;
12'd3361 : mem_out_dec = 6'b111111;
12'd3362 : mem_out_dec = 6'b111111;
12'd3363 : mem_out_dec = 6'b111111;
12'd3364 : mem_out_dec = 6'b111111;
12'd3365 : mem_out_dec = 6'b111111;
12'd3366 : mem_out_dec = 6'b111111;
12'd3367 : mem_out_dec = 6'b111111;
12'd3368 : mem_out_dec = 6'b111111;
12'd3369 : mem_out_dec = 6'b111111;
12'd3370 : mem_out_dec = 6'b111111;
12'd3371 : mem_out_dec = 6'b111111;
12'd3372 : mem_out_dec = 6'b111111;
12'd3373 : mem_out_dec = 6'b111111;
12'd3374 : mem_out_dec = 6'b111111;
12'd3375 : mem_out_dec = 6'b111111;
12'd3376 : mem_out_dec = 6'b111111;
12'd3377 : mem_out_dec = 6'b111111;
12'd3378 : mem_out_dec = 6'b111111;
12'd3379 : mem_out_dec = 6'b111111;
12'd3380 : mem_out_dec = 6'b111111;
12'd3381 : mem_out_dec = 6'b111111;
12'd3382 : mem_out_dec = 6'b111111;
12'd3383 : mem_out_dec = 6'b111111;
12'd3384 : mem_out_dec = 6'b111111;
12'd3385 : mem_out_dec = 6'b111111;
12'd3386 : mem_out_dec = 6'b000100;
12'd3387 : mem_out_dec = 6'b000101;
12'd3388 : mem_out_dec = 6'b000110;
12'd3389 : mem_out_dec = 6'b000110;
12'd3390 : mem_out_dec = 6'b000111;
12'd3391 : mem_out_dec = 6'b001000;
12'd3392 : mem_out_dec = 6'b111111;
12'd3393 : mem_out_dec = 6'b111111;
12'd3394 : mem_out_dec = 6'b111111;
12'd3395 : mem_out_dec = 6'b111111;
12'd3396 : mem_out_dec = 6'b111111;
12'd3397 : mem_out_dec = 6'b111111;
12'd3398 : mem_out_dec = 6'b111111;
12'd3399 : mem_out_dec = 6'b111111;
12'd3400 : mem_out_dec = 6'b111111;
12'd3401 : mem_out_dec = 6'b111111;
12'd3402 : mem_out_dec = 6'b111111;
12'd3403 : mem_out_dec = 6'b111111;
12'd3404 : mem_out_dec = 6'b111111;
12'd3405 : mem_out_dec = 6'b111111;
12'd3406 : mem_out_dec = 6'b111111;
12'd3407 : mem_out_dec = 6'b111111;
12'd3408 : mem_out_dec = 6'b111111;
12'd3409 : mem_out_dec = 6'b111111;
12'd3410 : mem_out_dec = 6'b111111;
12'd3411 : mem_out_dec = 6'b111111;
12'd3412 : mem_out_dec = 6'b111111;
12'd3413 : mem_out_dec = 6'b111111;
12'd3414 : mem_out_dec = 6'b111111;
12'd3415 : mem_out_dec = 6'b111111;
12'd3416 : mem_out_dec = 6'b111111;
12'd3417 : mem_out_dec = 6'b111111;
12'd3418 : mem_out_dec = 6'b111111;
12'd3419 : mem_out_dec = 6'b111111;
12'd3420 : mem_out_dec = 6'b111111;
12'd3421 : mem_out_dec = 6'b111111;
12'd3422 : mem_out_dec = 6'b111111;
12'd3423 : mem_out_dec = 6'b111111;
12'd3424 : mem_out_dec = 6'b111111;
12'd3425 : mem_out_dec = 6'b111111;
12'd3426 : mem_out_dec = 6'b111111;
12'd3427 : mem_out_dec = 6'b111111;
12'd3428 : mem_out_dec = 6'b111111;
12'd3429 : mem_out_dec = 6'b111111;
12'd3430 : mem_out_dec = 6'b111111;
12'd3431 : mem_out_dec = 6'b111111;
12'd3432 : mem_out_dec = 6'b111111;
12'd3433 : mem_out_dec = 6'b111111;
12'd3434 : mem_out_dec = 6'b111111;
12'd3435 : mem_out_dec = 6'b111111;
12'd3436 : mem_out_dec = 6'b111111;
12'd3437 : mem_out_dec = 6'b111111;
12'd3438 : mem_out_dec = 6'b111111;
12'd3439 : mem_out_dec = 6'b111111;
12'd3440 : mem_out_dec = 6'b111111;
12'd3441 : mem_out_dec = 6'b111111;
12'd3442 : mem_out_dec = 6'b111111;
12'd3443 : mem_out_dec = 6'b111111;
12'd3444 : mem_out_dec = 6'b111111;
12'd3445 : mem_out_dec = 6'b111111;
12'd3446 : mem_out_dec = 6'b111111;
12'd3447 : mem_out_dec = 6'b111111;
12'd3448 : mem_out_dec = 6'b111111;
12'd3449 : mem_out_dec = 6'b111111;
12'd3450 : mem_out_dec = 6'b111111;
12'd3451 : mem_out_dec = 6'b000100;
12'd3452 : mem_out_dec = 6'b000101;
12'd3453 : mem_out_dec = 6'b000110;
12'd3454 : mem_out_dec = 6'b000111;
12'd3455 : mem_out_dec = 6'b001000;
12'd3456 : mem_out_dec = 6'b111111;
12'd3457 : mem_out_dec = 6'b111111;
12'd3458 : mem_out_dec = 6'b111111;
12'd3459 : mem_out_dec = 6'b111111;
12'd3460 : mem_out_dec = 6'b111111;
12'd3461 : mem_out_dec = 6'b111111;
12'd3462 : mem_out_dec = 6'b111111;
12'd3463 : mem_out_dec = 6'b111111;
12'd3464 : mem_out_dec = 6'b111111;
12'd3465 : mem_out_dec = 6'b111111;
12'd3466 : mem_out_dec = 6'b111111;
12'd3467 : mem_out_dec = 6'b111111;
12'd3468 : mem_out_dec = 6'b111111;
12'd3469 : mem_out_dec = 6'b111111;
12'd3470 : mem_out_dec = 6'b111111;
12'd3471 : mem_out_dec = 6'b111111;
12'd3472 : mem_out_dec = 6'b111111;
12'd3473 : mem_out_dec = 6'b111111;
12'd3474 : mem_out_dec = 6'b111111;
12'd3475 : mem_out_dec = 6'b111111;
12'd3476 : mem_out_dec = 6'b111111;
12'd3477 : mem_out_dec = 6'b111111;
12'd3478 : mem_out_dec = 6'b111111;
12'd3479 : mem_out_dec = 6'b111111;
12'd3480 : mem_out_dec = 6'b111111;
12'd3481 : mem_out_dec = 6'b111111;
12'd3482 : mem_out_dec = 6'b111111;
12'd3483 : mem_out_dec = 6'b111111;
12'd3484 : mem_out_dec = 6'b111111;
12'd3485 : mem_out_dec = 6'b111111;
12'd3486 : mem_out_dec = 6'b111111;
12'd3487 : mem_out_dec = 6'b111111;
12'd3488 : mem_out_dec = 6'b111111;
12'd3489 : mem_out_dec = 6'b111111;
12'd3490 : mem_out_dec = 6'b111111;
12'd3491 : mem_out_dec = 6'b111111;
12'd3492 : mem_out_dec = 6'b111111;
12'd3493 : mem_out_dec = 6'b111111;
12'd3494 : mem_out_dec = 6'b111111;
12'd3495 : mem_out_dec = 6'b111111;
12'd3496 : mem_out_dec = 6'b111111;
12'd3497 : mem_out_dec = 6'b111111;
12'd3498 : mem_out_dec = 6'b111111;
12'd3499 : mem_out_dec = 6'b111111;
12'd3500 : mem_out_dec = 6'b111111;
12'd3501 : mem_out_dec = 6'b111111;
12'd3502 : mem_out_dec = 6'b111111;
12'd3503 : mem_out_dec = 6'b111111;
12'd3504 : mem_out_dec = 6'b111111;
12'd3505 : mem_out_dec = 6'b111111;
12'd3506 : mem_out_dec = 6'b111111;
12'd3507 : mem_out_dec = 6'b111111;
12'd3508 : mem_out_dec = 6'b111111;
12'd3509 : mem_out_dec = 6'b111111;
12'd3510 : mem_out_dec = 6'b111111;
12'd3511 : mem_out_dec = 6'b111111;
12'd3512 : mem_out_dec = 6'b111111;
12'd3513 : mem_out_dec = 6'b111111;
12'd3514 : mem_out_dec = 6'b111111;
12'd3515 : mem_out_dec = 6'b111111;
12'd3516 : mem_out_dec = 6'b000101;
12'd3517 : mem_out_dec = 6'b000110;
12'd3518 : mem_out_dec = 6'b000110;
12'd3519 : mem_out_dec = 6'b000111;
12'd3520 : mem_out_dec = 6'b111111;
12'd3521 : mem_out_dec = 6'b111111;
12'd3522 : mem_out_dec = 6'b111111;
12'd3523 : mem_out_dec = 6'b111111;
12'd3524 : mem_out_dec = 6'b111111;
12'd3525 : mem_out_dec = 6'b111111;
12'd3526 : mem_out_dec = 6'b111111;
12'd3527 : mem_out_dec = 6'b111111;
12'd3528 : mem_out_dec = 6'b111111;
12'd3529 : mem_out_dec = 6'b111111;
12'd3530 : mem_out_dec = 6'b111111;
12'd3531 : mem_out_dec = 6'b111111;
12'd3532 : mem_out_dec = 6'b111111;
12'd3533 : mem_out_dec = 6'b111111;
12'd3534 : mem_out_dec = 6'b111111;
12'd3535 : mem_out_dec = 6'b111111;
12'd3536 : mem_out_dec = 6'b111111;
12'd3537 : mem_out_dec = 6'b111111;
12'd3538 : mem_out_dec = 6'b111111;
12'd3539 : mem_out_dec = 6'b111111;
12'd3540 : mem_out_dec = 6'b111111;
12'd3541 : mem_out_dec = 6'b111111;
12'd3542 : mem_out_dec = 6'b111111;
12'd3543 : mem_out_dec = 6'b111111;
12'd3544 : mem_out_dec = 6'b111111;
12'd3545 : mem_out_dec = 6'b111111;
12'd3546 : mem_out_dec = 6'b111111;
12'd3547 : mem_out_dec = 6'b111111;
12'd3548 : mem_out_dec = 6'b111111;
12'd3549 : mem_out_dec = 6'b111111;
12'd3550 : mem_out_dec = 6'b111111;
12'd3551 : mem_out_dec = 6'b111111;
12'd3552 : mem_out_dec = 6'b111111;
12'd3553 : mem_out_dec = 6'b111111;
12'd3554 : mem_out_dec = 6'b111111;
12'd3555 : mem_out_dec = 6'b111111;
12'd3556 : mem_out_dec = 6'b111111;
12'd3557 : mem_out_dec = 6'b111111;
12'd3558 : mem_out_dec = 6'b111111;
12'd3559 : mem_out_dec = 6'b111111;
12'd3560 : mem_out_dec = 6'b111111;
12'd3561 : mem_out_dec = 6'b111111;
12'd3562 : mem_out_dec = 6'b111111;
12'd3563 : mem_out_dec = 6'b111111;
12'd3564 : mem_out_dec = 6'b111111;
12'd3565 : mem_out_dec = 6'b111111;
12'd3566 : mem_out_dec = 6'b111111;
12'd3567 : mem_out_dec = 6'b111111;
12'd3568 : mem_out_dec = 6'b111111;
12'd3569 : mem_out_dec = 6'b111111;
12'd3570 : mem_out_dec = 6'b111111;
12'd3571 : mem_out_dec = 6'b111111;
12'd3572 : mem_out_dec = 6'b111111;
12'd3573 : mem_out_dec = 6'b111111;
12'd3574 : mem_out_dec = 6'b111111;
12'd3575 : mem_out_dec = 6'b111111;
12'd3576 : mem_out_dec = 6'b111111;
12'd3577 : mem_out_dec = 6'b111111;
12'd3578 : mem_out_dec = 6'b111111;
12'd3579 : mem_out_dec = 6'b111111;
12'd3580 : mem_out_dec = 6'b111111;
12'd3581 : mem_out_dec = 6'b000101;
12'd3582 : mem_out_dec = 6'b000110;
12'd3583 : mem_out_dec = 6'b000110;
12'd3584 : mem_out_dec = 6'b111111;
12'd3585 : mem_out_dec = 6'b111111;
12'd3586 : mem_out_dec = 6'b111111;
12'd3587 : mem_out_dec = 6'b111111;
12'd3588 : mem_out_dec = 6'b111111;
12'd3589 : mem_out_dec = 6'b111111;
12'd3590 : mem_out_dec = 6'b111111;
12'd3591 : mem_out_dec = 6'b111111;
12'd3592 : mem_out_dec = 6'b111111;
12'd3593 : mem_out_dec = 6'b111111;
12'd3594 : mem_out_dec = 6'b111111;
12'd3595 : mem_out_dec = 6'b111111;
12'd3596 : mem_out_dec = 6'b111111;
12'd3597 : mem_out_dec = 6'b111111;
12'd3598 : mem_out_dec = 6'b111111;
12'd3599 : mem_out_dec = 6'b111111;
12'd3600 : mem_out_dec = 6'b111111;
12'd3601 : mem_out_dec = 6'b111111;
12'd3602 : mem_out_dec = 6'b111111;
12'd3603 : mem_out_dec = 6'b111111;
12'd3604 : mem_out_dec = 6'b111111;
12'd3605 : mem_out_dec = 6'b111111;
12'd3606 : mem_out_dec = 6'b111111;
12'd3607 : mem_out_dec = 6'b111111;
12'd3608 : mem_out_dec = 6'b111111;
12'd3609 : mem_out_dec = 6'b111111;
12'd3610 : mem_out_dec = 6'b111111;
12'd3611 : mem_out_dec = 6'b111111;
12'd3612 : mem_out_dec = 6'b111111;
12'd3613 : mem_out_dec = 6'b111111;
12'd3614 : mem_out_dec = 6'b111111;
12'd3615 : mem_out_dec = 6'b111111;
12'd3616 : mem_out_dec = 6'b111111;
12'd3617 : mem_out_dec = 6'b111111;
12'd3618 : mem_out_dec = 6'b111111;
12'd3619 : mem_out_dec = 6'b111111;
12'd3620 : mem_out_dec = 6'b111111;
12'd3621 : mem_out_dec = 6'b111111;
12'd3622 : mem_out_dec = 6'b111111;
12'd3623 : mem_out_dec = 6'b111111;
12'd3624 : mem_out_dec = 6'b111111;
12'd3625 : mem_out_dec = 6'b111111;
12'd3626 : mem_out_dec = 6'b111111;
12'd3627 : mem_out_dec = 6'b111111;
12'd3628 : mem_out_dec = 6'b111111;
12'd3629 : mem_out_dec = 6'b111111;
12'd3630 : mem_out_dec = 6'b111111;
12'd3631 : mem_out_dec = 6'b111111;
12'd3632 : mem_out_dec = 6'b111111;
12'd3633 : mem_out_dec = 6'b111111;
12'd3634 : mem_out_dec = 6'b111111;
12'd3635 : mem_out_dec = 6'b111111;
12'd3636 : mem_out_dec = 6'b111111;
12'd3637 : mem_out_dec = 6'b111111;
12'd3638 : mem_out_dec = 6'b111111;
12'd3639 : mem_out_dec = 6'b111111;
12'd3640 : mem_out_dec = 6'b111111;
12'd3641 : mem_out_dec = 6'b111111;
12'd3642 : mem_out_dec = 6'b111111;
12'd3643 : mem_out_dec = 6'b111111;
12'd3644 : mem_out_dec = 6'b111111;
12'd3645 : mem_out_dec = 6'b111111;
12'd3646 : mem_out_dec = 6'b000100;
12'd3647 : mem_out_dec = 6'b000101;
12'd3648 : mem_out_dec = 6'b111111;
12'd3649 : mem_out_dec = 6'b111111;
12'd3650 : mem_out_dec = 6'b111111;
12'd3651 : mem_out_dec = 6'b111111;
12'd3652 : mem_out_dec = 6'b111111;
12'd3653 : mem_out_dec = 6'b111111;
12'd3654 : mem_out_dec = 6'b111111;
12'd3655 : mem_out_dec = 6'b111111;
12'd3656 : mem_out_dec = 6'b111111;
12'd3657 : mem_out_dec = 6'b111111;
12'd3658 : mem_out_dec = 6'b111111;
12'd3659 : mem_out_dec = 6'b111111;
12'd3660 : mem_out_dec = 6'b111111;
12'd3661 : mem_out_dec = 6'b111111;
12'd3662 : mem_out_dec = 6'b111111;
12'd3663 : mem_out_dec = 6'b111111;
12'd3664 : mem_out_dec = 6'b111111;
12'd3665 : mem_out_dec = 6'b111111;
12'd3666 : mem_out_dec = 6'b111111;
12'd3667 : mem_out_dec = 6'b111111;
12'd3668 : mem_out_dec = 6'b111111;
12'd3669 : mem_out_dec = 6'b111111;
12'd3670 : mem_out_dec = 6'b111111;
12'd3671 : mem_out_dec = 6'b111111;
12'd3672 : mem_out_dec = 6'b111111;
12'd3673 : mem_out_dec = 6'b111111;
12'd3674 : mem_out_dec = 6'b111111;
12'd3675 : mem_out_dec = 6'b111111;
12'd3676 : mem_out_dec = 6'b111111;
12'd3677 : mem_out_dec = 6'b111111;
12'd3678 : mem_out_dec = 6'b111111;
12'd3679 : mem_out_dec = 6'b111111;
12'd3680 : mem_out_dec = 6'b111111;
12'd3681 : mem_out_dec = 6'b111111;
12'd3682 : mem_out_dec = 6'b111111;
12'd3683 : mem_out_dec = 6'b111111;
12'd3684 : mem_out_dec = 6'b111111;
12'd3685 : mem_out_dec = 6'b111111;
12'd3686 : mem_out_dec = 6'b111111;
12'd3687 : mem_out_dec = 6'b111111;
12'd3688 : mem_out_dec = 6'b111111;
12'd3689 : mem_out_dec = 6'b111111;
12'd3690 : mem_out_dec = 6'b111111;
12'd3691 : mem_out_dec = 6'b111111;
12'd3692 : mem_out_dec = 6'b111111;
12'd3693 : mem_out_dec = 6'b111111;
12'd3694 : mem_out_dec = 6'b111111;
12'd3695 : mem_out_dec = 6'b111111;
12'd3696 : mem_out_dec = 6'b111111;
12'd3697 : mem_out_dec = 6'b111111;
12'd3698 : mem_out_dec = 6'b111111;
12'd3699 : mem_out_dec = 6'b111111;
12'd3700 : mem_out_dec = 6'b111111;
12'd3701 : mem_out_dec = 6'b111111;
12'd3702 : mem_out_dec = 6'b111111;
12'd3703 : mem_out_dec = 6'b111111;
12'd3704 : mem_out_dec = 6'b111111;
12'd3705 : mem_out_dec = 6'b111111;
12'd3706 : mem_out_dec = 6'b111111;
12'd3707 : mem_out_dec = 6'b111111;
12'd3708 : mem_out_dec = 6'b111111;
12'd3709 : mem_out_dec = 6'b111111;
12'd3710 : mem_out_dec = 6'b111111;
12'd3711 : mem_out_dec = 6'b000100;
12'd3712 : mem_out_dec = 6'b111111;
12'd3713 : mem_out_dec = 6'b111111;
12'd3714 : mem_out_dec = 6'b111111;
12'd3715 : mem_out_dec = 6'b111111;
12'd3716 : mem_out_dec = 6'b111111;
12'd3717 : mem_out_dec = 6'b111111;
12'd3718 : mem_out_dec = 6'b111111;
12'd3719 : mem_out_dec = 6'b111111;
12'd3720 : mem_out_dec = 6'b111111;
12'd3721 : mem_out_dec = 6'b111111;
12'd3722 : mem_out_dec = 6'b111111;
12'd3723 : mem_out_dec = 6'b111111;
12'd3724 : mem_out_dec = 6'b111111;
12'd3725 : mem_out_dec = 6'b111111;
12'd3726 : mem_out_dec = 6'b111111;
12'd3727 : mem_out_dec = 6'b111111;
12'd3728 : mem_out_dec = 6'b111111;
12'd3729 : mem_out_dec = 6'b111111;
12'd3730 : mem_out_dec = 6'b111111;
12'd3731 : mem_out_dec = 6'b111111;
12'd3732 : mem_out_dec = 6'b111111;
12'd3733 : mem_out_dec = 6'b111111;
12'd3734 : mem_out_dec = 6'b111111;
12'd3735 : mem_out_dec = 6'b111111;
12'd3736 : mem_out_dec = 6'b111111;
12'd3737 : mem_out_dec = 6'b111111;
12'd3738 : mem_out_dec = 6'b111111;
12'd3739 : mem_out_dec = 6'b111111;
12'd3740 : mem_out_dec = 6'b111111;
12'd3741 : mem_out_dec = 6'b111111;
12'd3742 : mem_out_dec = 6'b111111;
12'd3743 : mem_out_dec = 6'b111111;
12'd3744 : mem_out_dec = 6'b111111;
12'd3745 : mem_out_dec = 6'b111111;
12'd3746 : mem_out_dec = 6'b111111;
12'd3747 : mem_out_dec = 6'b111111;
12'd3748 : mem_out_dec = 6'b111111;
12'd3749 : mem_out_dec = 6'b111111;
12'd3750 : mem_out_dec = 6'b111111;
12'd3751 : mem_out_dec = 6'b111111;
12'd3752 : mem_out_dec = 6'b111111;
12'd3753 : mem_out_dec = 6'b111111;
12'd3754 : mem_out_dec = 6'b111111;
12'd3755 : mem_out_dec = 6'b111111;
12'd3756 : mem_out_dec = 6'b111111;
12'd3757 : mem_out_dec = 6'b111111;
12'd3758 : mem_out_dec = 6'b111111;
12'd3759 : mem_out_dec = 6'b111111;
12'd3760 : mem_out_dec = 6'b111111;
12'd3761 : mem_out_dec = 6'b111111;
12'd3762 : mem_out_dec = 6'b111111;
12'd3763 : mem_out_dec = 6'b111111;
12'd3764 : mem_out_dec = 6'b111111;
12'd3765 : mem_out_dec = 6'b111111;
12'd3766 : mem_out_dec = 6'b111111;
12'd3767 : mem_out_dec = 6'b111111;
12'd3768 : mem_out_dec = 6'b111111;
12'd3769 : mem_out_dec = 6'b111111;
12'd3770 : mem_out_dec = 6'b111111;
12'd3771 : mem_out_dec = 6'b111111;
12'd3772 : mem_out_dec = 6'b111111;
12'd3773 : mem_out_dec = 6'b111111;
12'd3774 : mem_out_dec = 6'b111111;
12'd3775 : mem_out_dec = 6'b111111;
12'd3776 : mem_out_dec = 6'b111111;
12'd3777 : mem_out_dec = 6'b111111;
12'd3778 : mem_out_dec = 6'b111111;
12'd3779 : mem_out_dec = 6'b111111;
12'd3780 : mem_out_dec = 6'b111111;
12'd3781 : mem_out_dec = 6'b111111;
12'd3782 : mem_out_dec = 6'b111111;
12'd3783 : mem_out_dec = 6'b111111;
12'd3784 : mem_out_dec = 6'b111111;
12'd3785 : mem_out_dec = 6'b111111;
12'd3786 : mem_out_dec = 6'b111111;
12'd3787 : mem_out_dec = 6'b111111;
12'd3788 : mem_out_dec = 6'b111111;
12'd3789 : mem_out_dec = 6'b111111;
12'd3790 : mem_out_dec = 6'b111111;
12'd3791 : mem_out_dec = 6'b111111;
12'd3792 : mem_out_dec = 6'b111111;
12'd3793 : mem_out_dec = 6'b111111;
12'd3794 : mem_out_dec = 6'b111111;
12'd3795 : mem_out_dec = 6'b111111;
12'd3796 : mem_out_dec = 6'b111111;
12'd3797 : mem_out_dec = 6'b111111;
12'd3798 : mem_out_dec = 6'b111111;
12'd3799 : mem_out_dec = 6'b111111;
12'd3800 : mem_out_dec = 6'b111111;
12'd3801 : mem_out_dec = 6'b111111;
12'd3802 : mem_out_dec = 6'b111111;
12'd3803 : mem_out_dec = 6'b111111;
12'd3804 : mem_out_dec = 6'b111111;
12'd3805 : mem_out_dec = 6'b111111;
12'd3806 : mem_out_dec = 6'b111111;
12'd3807 : mem_out_dec = 6'b111111;
12'd3808 : mem_out_dec = 6'b111111;
12'd3809 : mem_out_dec = 6'b111111;
12'd3810 : mem_out_dec = 6'b111111;
12'd3811 : mem_out_dec = 6'b111111;
12'd3812 : mem_out_dec = 6'b111111;
12'd3813 : mem_out_dec = 6'b111111;
12'd3814 : mem_out_dec = 6'b111111;
12'd3815 : mem_out_dec = 6'b111111;
12'd3816 : mem_out_dec = 6'b111111;
12'd3817 : mem_out_dec = 6'b111111;
12'd3818 : mem_out_dec = 6'b111111;
12'd3819 : mem_out_dec = 6'b111111;
12'd3820 : mem_out_dec = 6'b111111;
12'd3821 : mem_out_dec = 6'b111111;
12'd3822 : mem_out_dec = 6'b111111;
12'd3823 : mem_out_dec = 6'b111111;
12'd3824 : mem_out_dec = 6'b111111;
12'd3825 : mem_out_dec = 6'b111111;
12'd3826 : mem_out_dec = 6'b111111;
12'd3827 : mem_out_dec = 6'b111111;
12'd3828 : mem_out_dec = 6'b111111;
12'd3829 : mem_out_dec = 6'b111111;
12'd3830 : mem_out_dec = 6'b111111;
12'd3831 : mem_out_dec = 6'b111111;
12'd3832 : mem_out_dec = 6'b111111;
12'd3833 : mem_out_dec = 6'b111111;
12'd3834 : mem_out_dec = 6'b111111;
12'd3835 : mem_out_dec = 6'b111111;
12'd3836 : mem_out_dec = 6'b111111;
12'd3837 : mem_out_dec = 6'b111111;
12'd3838 : mem_out_dec = 6'b111111;
12'd3839 : mem_out_dec = 6'b111111;
12'd3840 : mem_out_dec = 6'b111111;
12'd3841 : mem_out_dec = 6'b111111;
12'd3842 : mem_out_dec = 6'b111111;
12'd3843 : mem_out_dec = 6'b111111;
12'd3844 : mem_out_dec = 6'b111111;
12'd3845 : mem_out_dec = 6'b111111;
12'd3846 : mem_out_dec = 6'b111111;
12'd3847 : mem_out_dec = 6'b111111;
12'd3848 : mem_out_dec = 6'b111111;
12'd3849 : mem_out_dec = 6'b111111;
12'd3850 : mem_out_dec = 6'b111111;
12'd3851 : mem_out_dec = 6'b111111;
12'd3852 : mem_out_dec = 6'b111111;
12'd3853 : mem_out_dec = 6'b111111;
12'd3854 : mem_out_dec = 6'b111111;
12'd3855 : mem_out_dec = 6'b111111;
12'd3856 : mem_out_dec = 6'b111111;
12'd3857 : mem_out_dec = 6'b111111;
12'd3858 : mem_out_dec = 6'b111111;
12'd3859 : mem_out_dec = 6'b111111;
12'd3860 : mem_out_dec = 6'b111111;
12'd3861 : mem_out_dec = 6'b111111;
12'd3862 : mem_out_dec = 6'b111111;
12'd3863 : mem_out_dec = 6'b111111;
12'd3864 : mem_out_dec = 6'b111111;
12'd3865 : mem_out_dec = 6'b111111;
12'd3866 : mem_out_dec = 6'b111111;
12'd3867 : mem_out_dec = 6'b111111;
12'd3868 : mem_out_dec = 6'b111111;
12'd3869 : mem_out_dec = 6'b111111;
12'd3870 : mem_out_dec = 6'b111111;
12'd3871 : mem_out_dec = 6'b111111;
12'd3872 : mem_out_dec = 6'b111111;
12'd3873 : mem_out_dec = 6'b111111;
12'd3874 : mem_out_dec = 6'b111111;
12'd3875 : mem_out_dec = 6'b111111;
12'd3876 : mem_out_dec = 6'b111111;
12'd3877 : mem_out_dec = 6'b111111;
12'd3878 : mem_out_dec = 6'b111111;
12'd3879 : mem_out_dec = 6'b111111;
12'd3880 : mem_out_dec = 6'b111111;
12'd3881 : mem_out_dec = 6'b111111;
12'd3882 : mem_out_dec = 6'b111111;
12'd3883 : mem_out_dec = 6'b111111;
12'd3884 : mem_out_dec = 6'b111111;
12'd3885 : mem_out_dec = 6'b111111;
12'd3886 : mem_out_dec = 6'b111111;
12'd3887 : mem_out_dec = 6'b111111;
12'd3888 : mem_out_dec = 6'b111111;
12'd3889 : mem_out_dec = 6'b111111;
12'd3890 : mem_out_dec = 6'b111111;
12'd3891 : mem_out_dec = 6'b111111;
12'd3892 : mem_out_dec = 6'b111111;
12'd3893 : mem_out_dec = 6'b111111;
12'd3894 : mem_out_dec = 6'b111111;
12'd3895 : mem_out_dec = 6'b111111;
12'd3896 : mem_out_dec = 6'b111111;
12'd3897 : mem_out_dec = 6'b111111;
12'd3898 : mem_out_dec = 6'b111111;
12'd3899 : mem_out_dec = 6'b111111;
12'd3900 : mem_out_dec = 6'b111111;
12'd3901 : mem_out_dec = 6'b111111;
12'd3902 : mem_out_dec = 6'b111111;
12'd3903 : mem_out_dec = 6'b111111;
12'd3904 : mem_out_dec = 6'b111111;
12'd3905 : mem_out_dec = 6'b111111;
12'd3906 : mem_out_dec = 6'b111111;
12'd3907 : mem_out_dec = 6'b111111;
12'd3908 : mem_out_dec = 6'b111111;
12'd3909 : mem_out_dec = 6'b111111;
12'd3910 : mem_out_dec = 6'b111111;
12'd3911 : mem_out_dec = 6'b111111;
12'd3912 : mem_out_dec = 6'b111111;
12'd3913 : mem_out_dec = 6'b111111;
12'd3914 : mem_out_dec = 6'b111111;
12'd3915 : mem_out_dec = 6'b111111;
12'd3916 : mem_out_dec = 6'b111111;
12'd3917 : mem_out_dec = 6'b111111;
12'd3918 : mem_out_dec = 6'b111111;
12'd3919 : mem_out_dec = 6'b111111;
12'd3920 : mem_out_dec = 6'b111111;
12'd3921 : mem_out_dec = 6'b111111;
12'd3922 : mem_out_dec = 6'b111111;
12'd3923 : mem_out_dec = 6'b111111;
12'd3924 : mem_out_dec = 6'b111111;
12'd3925 : mem_out_dec = 6'b111111;
12'd3926 : mem_out_dec = 6'b111111;
12'd3927 : mem_out_dec = 6'b111111;
12'd3928 : mem_out_dec = 6'b111111;
12'd3929 : mem_out_dec = 6'b111111;
12'd3930 : mem_out_dec = 6'b111111;
12'd3931 : mem_out_dec = 6'b111111;
12'd3932 : mem_out_dec = 6'b111111;
12'd3933 : mem_out_dec = 6'b111111;
12'd3934 : mem_out_dec = 6'b111111;
12'd3935 : mem_out_dec = 6'b111111;
12'd3936 : mem_out_dec = 6'b111111;
12'd3937 : mem_out_dec = 6'b111111;
12'd3938 : mem_out_dec = 6'b111111;
12'd3939 : mem_out_dec = 6'b111111;
12'd3940 : mem_out_dec = 6'b111111;
12'd3941 : mem_out_dec = 6'b111111;
12'd3942 : mem_out_dec = 6'b111111;
12'd3943 : mem_out_dec = 6'b111111;
12'd3944 : mem_out_dec = 6'b111111;
12'd3945 : mem_out_dec = 6'b111111;
12'd3946 : mem_out_dec = 6'b111111;
12'd3947 : mem_out_dec = 6'b111111;
12'd3948 : mem_out_dec = 6'b111111;
12'd3949 : mem_out_dec = 6'b111111;
12'd3950 : mem_out_dec = 6'b111111;
12'd3951 : mem_out_dec = 6'b111111;
12'd3952 : mem_out_dec = 6'b111111;
12'd3953 : mem_out_dec = 6'b111111;
12'd3954 : mem_out_dec = 6'b111111;
12'd3955 : mem_out_dec = 6'b111111;
12'd3956 : mem_out_dec = 6'b111111;
12'd3957 : mem_out_dec = 6'b111111;
12'd3958 : mem_out_dec = 6'b111111;
12'd3959 : mem_out_dec = 6'b111111;
12'd3960 : mem_out_dec = 6'b111111;
12'd3961 : mem_out_dec = 6'b111111;
12'd3962 : mem_out_dec = 6'b111111;
12'd3963 : mem_out_dec = 6'b111111;
12'd3964 : mem_out_dec = 6'b111111;
12'd3965 : mem_out_dec = 6'b111111;
12'd3966 : mem_out_dec = 6'b111111;
12'd3967 : mem_out_dec = 6'b111111;
12'd3968 : mem_out_dec = 6'b111111;
12'd3969 : mem_out_dec = 6'b111111;
12'd3970 : mem_out_dec = 6'b111111;
12'd3971 : mem_out_dec = 6'b111111;
12'd3972 : mem_out_dec = 6'b111111;
12'd3973 : mem_out_dec = 6'b111111;
12'd3974 : mem_out_dec = 6'b111111;
12'd3975 : mem_out_dec = 6'b111111;
12'd3976 : mem_out_dec = 6'b111111;
12'd3977 : mem_out_dec = 6'b111111;
12'd3978 : mem_out_dec = 6'b111111;
12'd3979 : mem_out_dec = 6'b111111;
12'd3980 : mem_out_dec = 6'b111111;
12'd3981 : mem_out_dec = 6'b111111;
12'd3982 : mem_out_dec = 6'b111111;
12'd3983 : mem_out_dec = 6'b111111;
12'd3984 : mem_out_dec = 6'b111111;
12'd3985 : mem_out_dec = 6'b111111;
12'd3986 : mem_out_dec = 6'b111111;
12'd3987 : mem_out_dec = 6'b111111;
12'd3988 : mem_out_dec = 6'b111111;
12'd3989 : mem_out_dec = 6'b111111;
12'd3990 : mem_out_dec = 6'b111111;
12'd3991 : mem_out_dec = 6'b111111;
12'd3992 : mem_out_dec = 6'b111111;
12'd3993 : mem_out_dec = 6'b111111;
12'd3994 : mem_out_dec = 6'b111111;
12'd3995 : mem_out_dec = 6'b111111;
12'd3996 : mem_out_dec = 6'b111111;
12'd3997 : mem_out_dec = 6'b111111;
12'd3998 : mem_out_dec = 6'b111111;
12'd3999 : mem_out_dec = 6'b111111;
12'd4000 : mem_out_dec = 6'b111111;
12'd4001 : mem_out_dec = 6'b111111;
12'd4002 : mem_out_dec = 6'b111111;
12'd4003 : mem_out_dec = 6'b111111;
12'd4004 : mem_out_dec = 6'b111111;
12'd4005 : mem_out_dec = 6'b111111;
12'd4006 : mem_out_dec = 6'b111111;
12'd4007 : mem_out_dec = 6'b111111;
12'd4008 : mem_out_dec = 6'b111111;
12'd4009 : mem_out_dec = 6'b111111;
12'd4010 : mem_out_dec = 6'b111111;
12'd4011 : mem_out_dec = 6'b111111;
12'd4012 : mem_out_dec = 6'b111111;
12'd4013 : mem_out_dec = 6'b111111;
12'd4014 : mem_out_dec = 6'b111111;
12'd4015 : mem_out_dec = 6'b111111;
12'd4016 : mem_out_dec = 6'b111111;
12'd4017 : mem_out_dec = 6'b111111;
12'd4018 : mem_out_dec = 6'b111111;
12'd4019 : mem_out_dec = 6'b111111;
12'd4020 : mem_out_dec = 6'b111111;
12'd4021 : mem_out_dec = 6'b111111;
12'd4022 : mem_out_dec = 6'b111111;
12'd4023 : mem_out_dec = 6'b111111;
12'd4024 : mem_out_dec = 6'b111111;
12'd4025 : mem_out_dec = 6'b111111;
12'd4026 : mem_out_dec = 6'b111111;
12'd4027 : mem_out_dec = 6'b111111;
12'd4028 : mem_out_dec = 6'b111111;
12'd4029 : mem_out_dec = 6'b111111;
12'd4030 : mem_out_dec = 6'b111111;
12'd4031 : mem_out_dec = 6'b111111;
12'd4032 : mem_out_dec = 6'b111111;
12'd4033 : mem_out_dec = 6'b111111;
12'd4034 : mem_out_dec = 6'b111111;
12'd4035 : mem_out_dec = 6'b111111;
12'd4036 : mem_out_dec = 6'b111111;
12'd4037 : mem_out_dec = 6'b111111;
12'd4038 : mem_out_dec = 6'b111111;
12'd4039 : mem_out_dec = 6'b111111;
12'd4040 : mem_out_dec = 6'b111111;
12'd4041 : mem_out_dec = 6'b111111;
12'd4042 : mem_out_dec = 6'b111111;
12'd4043 : mem_out_dec = 6'b111111;
12'd4044 : mem_out_dec = 6'b111111;
12'd4045 : mem_out_dec = 6'b111111;
12'd4046 : mem_out_dec = 6'b111111;
12'd4047 : mem_out_dec = 6'b111111;
12'd4048 : mem_out_dec = 6'b111111;
12'd4049 : mem_out_dec = 6'b111111;
12'd4050 : mem_out_dec = 6'b111111;
12'd4051 : mem_out_dec = 6'b111111;
12'd4052 : mem_out_dec = 6'b111111;
12'd4053 : mem_out_dec = 6'b111111;
12'd4054 : mem_out_dec = 6'b111111;
12'd4055 : mem_out_dec = 6'b111111;
12'd4056 : mem_out_dec = 6'b111111;
12'd4057 : mem_out_dec = 6'b111111;
12'd4058 : mem_out_dec = 6'b111111;
12'd4059 : mem_out_dec = 6'b111111;
12'd4060 : mem_out_dec = 6'b111111;
12'd4061 : mem_out_dec = 6'b111111;
12'd4062 : mem_out_dec = 6'b111111;
12'd4063 : mem_out_dec = 6'b111111;
12'd4064 : mem_out_dec = 6'b111111;
12'd4065 : mem_out_dec = 6'b111111;
12'd4066 : mem_out_dec = 6'b111111;
12'd4067 : mem_out_dec = 6'b111111;
12'd4068 : mem_out_dec = 6'b111111;
12'd4069 : mem_out_dec = 6'b111111;
12'd4070 : mem_out_dec = 6'b111111;
12'd4071 : mem_out_dec = 6'b111111;
12'd4072 : mem_out_dec = 6'b111111;
12'd4073 : mem_out_dec = 6'b111111;
12'd4074 : mem_out_dec = 6'b111111;
12'd4075 : mem_out_dec = 6'b111111;
12'd4076 : mem_out_dec = 6'b111111;
12'd4077 : mem_out_dec = 6'b111111;
12'd4078 : mem_out_dec = 6'b111111;
12'd4079 : mem_out_dec = 6'b111111;
12'd4080 : mem_out_dec = 6'b111111;
12'd4081 : mem_out_dec = 6'b111111;
12'd4082 : mem_out_dec = 6'b111111;
12'd4083 : mem_out_dec = 6'b111111;
12'd4084 : mem_out_dec = 6'b111111;
12'd4085 : mem_out_dec = 6'b111111;
12'd4086 : mem_out_dec = 6'b111111;
12'd4087 : mem_out_dec = 6'b111111;
12'd4088 : mem_out_dec = 6'b111111;
12'd4089 : mem_out_dec = 6'b111111;
12'd4090 : mem_out_dec = 6'b111111;
12'd4091 : mem_out_dec = 6'b111111;
12'd4092 : mem_out_dec = 6'b111111;
12'd4093 : mem_out_dec = 6'b111111;
12'd4094 : mem_out_dec = 6'b111111;
12'd4095 : mem_out_dec = 6'b111111;
endcase
end
always @ (posedge clk) begin
dec_cnt <= #TCQ mem_out_dec;
end
endmodule
|
module pkt_recomb(
input clk,
input reset,
input pkt_metadata_cut_out_valid,
input [359:0] pkt_metadata_cut_out,
input [138:0] pkt_cut_data,
input pkt_cut_data_valid,
output [7:0] pkt_cut_data_usedw,
input buf_addr_wr,
input [3:0] buf_addr,
output reg [3:0] aging_recycle_addr,
output reg aging_recycle_addr_wr,
output reg [339:0] pkt_metadata_out, //[339:336]==pkt_addr,[335:0]
output reg pkt_metadata_out_valid,
input [10:0] ram_rd_addr,
input ram_rd,
output [138:0] ram_data_q
);
wire [3:0] buf_addr_q;
reg buf_addr_rd;
wire buf_addr_empty;
wire [138:0] pkt_cut_data_q;
reg pkt_cut_data_rdreq;
reg pkt_metadata_cut_out_rdreq;
wire [359:0] pkt_metadata_cut_out_q;
wire pkt_metadata_cut_out_empty;
reg [138:0] ram_data_in;
reg [10:0] ram_wr_addr;
reg ram_wr;
reg [359:0] pkt_metadata_cut_out_q_r;
reg [3:0] count;
reg [127:0] addr_3_0_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [127:0] addr_7_4_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [127:0] addr_11_8_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [127:0] addr_15_12_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [10:0] buf_addr_q_r;
reg [3:0] timing_count;
reg flag;
reg [63:0] count_timing;
reg [14:0] timing;
reg [2:0] current_state;
parameter idle_s = 3'd0,
initial_s = 3'd1,
parse_metadata_s = 3'd2,
trans_b_s = 3'd3,
delete_5clock = 3'd4,
discard_s = 3'd5,
check_aging_s = 3'd6;
always @ (posedge clk or negedge reset)
if(!reset) begin
pkt_metadata_cut_out_rdreq <= 1'b0;
pkt_cut_data_rdreq <= 1'b0;
//buf_addr <= 4'b0;
buf_addr_rd <= 1'b0;
//buf_addr_wr <= 1'b0;
flag <= 1'b0;
count <= 4'b0;
buf_addr_q_r <= 11'b0;
addr_3_0_pkt_a_timing <= 128'b0;
addr_7_4_pkt_a_timing <= 128'b0;
addr_11_8_pkt_a_timing <= 128'b0;
addr_15_12_pkt_a_timing <= 128'b0;
ram_data_in <= 139'b0;
ram_wr_addr <= 11'b0;
ram_wr <= 1'b0;
pkt_metadata_out <= 340'b0;
pkt_metadata_out_valid <= 1'b0;
aging_recycle_addr <= 4'b0;
aging_recycle_addr_wr <= 1'b0;
timing_count <= 4'b0;
current_state <= initial_s;
end
else begin
case(current_state)
initial_s: begin
if(count == 4'hf) begin
count <= 4'b0;
current_state <= idle_s;
end
else begin
count <= count + 1'b1;
current_state <= initial_s;
end
end
idle_s: begin
count <= 4'b0;
ram_data_in <= 139'b0;
ram_wr_addr <= 11'b0;
ram_wr <= 1'b0;
pkt_metadata_out_valid <= 1'b0;
aging_recycle_addr_wr <= 1'b0;
if((buf_addr_empty == 1'b0)&&(pkt_metadata_cut_out_empty == 1'b0)) begin
pkt_metadata_cut_out_rdreq <= 1'b1;
pkt_metadata_cut_out_q_r <= pkt_metadata_cut_out_q;
current_state <= parse_metadata_s;
end
else begin
current_state <= idle_s;
end
end
parse_metadata_s: begin
pkt_metadata_cut_out_rdreq <= 1'b0;
if(pkt_metadata_cut_out_q_r[354] == 1'b0) begin //part 0
pkt_cut_data_rdreq <= 1'b1;
count <= 4'b0;
buf_addr_q_r <= {buf_addr_q[3:0],7'b0};
buf_addr_rd <= 1'b1;
flag <= 1'b0;
current_state <= delete_5clock;
case(buf_addr_q)
4'b0000: addr_3_0_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0001: addr_3_0_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0010: addr_3_0_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0011: addr_3_0_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0100: addr_7_4_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0101: addr_7_4_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0110: addr_7_4_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0111: addr_7_4_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1000: addr_11_8_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1001: addr_11_8_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1010: addr_11_8_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1011: addr_11_8_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1100: addr_15_12_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1101: addr_15_12_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1110: addr_15_12_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
default: addr_15_12_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
endcase
end
else begin //part 1
flag <= 1'b1;
pkt_cut_data_rdreq <= 1'b1;
if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'h0,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'h1,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'h2,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'h3,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'h4,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'h5,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'h6,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'h7,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'h8,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'h9,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'ha,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'hb,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'hc,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'hd,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'he,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'hf,7'b0} +11'd64;
current_state <= delete_5clock;
end
else begin
current_state <= discard_s;
end
end
end
delete_5clock: begin
buf_addr_rd <= 1'b0;
if(count == 4'd4) begin
current_state <= trans_b_s;
end
else begin
count <= count + 1'b1;
current_state <= delete_5clock;
end
end
trans_b_s: begin
if(pkt_cut_data_q[138:136] == 3'b110) begin
pkt_cut_data_rdreq <= 1'b0;
if(flag == 1'b1) begin
pkt_metadata_out_valid <= 1'b1;
pkt_metadata_out <= {buf_addr_q_r[10:7],pkt_metadata_cut_out_q_r[335:0]};
ram_data_in <= {3'b110,pkt_cut_data_q[135:0]};
ram_wr_addr <= buf_addr_q_r;
ram_wr <= 1'b1;
current_state <= check_aging_s;
end
else begin
ram_data_in <= {3'b100,pkt_cut_data_q[135:0]};
ram_wr_addr <= buf_addr_q_r;
ram_wr <= 1'b1;
current_state <= idle_s;
end
end
else begin
buf_addr_q_r <= buf_addr_q_r + 1'b1;
ram_data_in <= {3'b100,pkt_cut_data_q[135:0]};
ram_wr_addr <= buf_addr_q_r;
ram_wr <= 1'b1;
current_state <= trans_b_s;
end
end
check_aging_s: begin
ram_data_in <= 139'b0;
ram_wr_addr <= 11'b0;
ram_wr <= 1'b0;
timing_count <= timing_count + 1'b1;
pkt_metadata_out_valid <= 1'b0;
case(timing_count)
4'b0000: begin
if(addr_3_0_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[30:16]) begin
if(timing > addr_3_0_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'h0;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'h0;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0001: begin
if(addr_3_0_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[62:48]) begin
if(timing > addr_3_0_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'h1;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'h1;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0010: begin
if(addr_3_0_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[94:80]) begin
if(timing > addr_3_0_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'h2;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'h2;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0011: begin
if(addr_3_0_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[126:112]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[126:112]) begin
if(timing > addr_3_0_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'h3;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'h3;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0100: begin
if(addr_7_4_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[30:16]) begin
if(timing > addr_7_4_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'h4;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'h4;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0101: begin
if(addr_7_4_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[62:48]) begin
if(timing > addr_7_4_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'h5;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'h5;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0110: begin
if(addr_7_4_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[94:80]) begin
if(timing > addr_7_4_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'h6;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'h6;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0111: begin
if(addr_7_4_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[126:112]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[126:112]) begin
if(timing > addr_7_4_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'h7;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'h7;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1000: begin
if(addr_11_8_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[30:16]) begin
if(timing > addr_11_8_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'h8;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'h8;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1001: begin
if(addr_11_8_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[62:48]) begin
if(timing > addr_11_8_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'h9;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'h9;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1010: begin
if(addr_11_8_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[94:80]) begin
if(timing > addr_11_8_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'ha;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'ha;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1011: begin
if(addr_11_8_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[126:112]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[126:112]) begin
if(timing > addr_11_8_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'hb;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'hb;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1100: begin
if(addr_15_12_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_15_12_pkt_a_timing[30:16]) begin
if(timing > addr_15_12_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'hc;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_15_12_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'hc;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1101: begin
if(addr_15_12_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_15_12_pkt_a_timing[62:48]) begin
if(timing > addr_15_12_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'hd;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_15_12_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'hd;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1110: begin
if(addr_3_0_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[94:80]) begin
if(timing > addr_3_0_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'he;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'he;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
default: begin
if(addr_15_12_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[126:112]) begin
current_state <= idle_s;
end
else
if(timing > addr_15_12_pkt_a_timing[126:112]) begin
if(timing > addr_15_12_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'hf;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= idle_s;
end
end
else begin
if(15'h7fff+ timing - addr_15_12_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'hf;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= idle_s;
end
end
end
else begin
current_state <= idle_s;
end
end
endcase
end
discard_s: begin
if(pkt_cut_data_q[138:136] == 3'b110) begin
pkt_cut_data_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
//////////////////////////////////aging timing
always @ (posedge clk or negedge reset)
if(!reset) begin
timing <= 15'b0;
count_timing <= 64'b0;
end
else begin
if(count_timing == 64'd125000000) begin
timing <= timing + 1'b1;
count_timing <= 64'b0;
end
else begin
count_timing <= count_timing + 1'b1;
end
end
fifo_4_16 fifo_4_16_addr (
.aclr (!reset),
.clock (clk),
.data (buf_addr),
.rdreq (buf_addr_rd),
.wrreq (buf_addr_wr),
.empty (buf_addr_empty),
.q (buf_addr_q));
ram_2048_139 ram_2048_139 (
.aclr (!reset),
.clock (clk),
.data (ram_data_in),
.rdaddress (ram_rd_addr),
.rden (ram_rd),
.wraddress (ram_wr_addr),
.wren (ram_wr),
.q (ram_data_q));
fifo_139_256 pkt_cut_data_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_cut_data),
.rdreq (pkt_cut_data_rdreq),
.wrreq (pkt_cut_data_valid),
.q (pkt_cut_data_q),
.usedw (pkt_cut_data_usedw));
fifo_360_64 pkt_metadata_cut_out_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_metadata_cut_out),
.rdreq (pkt_metadata_cut_out_rdreq),
.wrreq (pkt_metadata_cut_out_valid),
.empty (pkt_metadata_cut_out_empty),
.q (pkt_metadata_cut_out_q));
endmodule |
/**********************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
///////////////////////////////////////////////////////////
**********************************************************/
`timescale 1ps/1ps
`define PC_DATA_OFFSET_RANGE 22:17
module mig_7series_v2_3_ddr_phy_4lanes #(
parameter GENERATE_IDELAYCTRL = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter NUM_DDR_CK = 1,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter BITLANES = 48'hffff_ffff_ffff,
parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
parameter USE_PRE_POST_FIFO = "FALSE",
parameter RCLK_SELECT_LANE = "B",
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PO_FINE_DELAY = 0,
parameter PI_SEL_CLK_OFFSET = 0,
// phy_control paramter used in other paramsters
parameter PC_CLK_RATIO = 4,
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_CLKOUT_DIV = 2,
parameter A_PI_BURST_MODE = "TRUE",
parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter A_PI_FINE_DELAY = 60,
parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter C_PI_FINE_DELAY = 0,
parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter D_PI_FINE_DELAY = 0,
parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
//phaser_out parameters
parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,
parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_COARSE_DELAY = 0,
parameter A_PO_OCLK_DELAY = 0,
parameter A_PO_OCLKDELAY_INV = "FALSE",
parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,
parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,
parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,
parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter A_IDELAYE2_IDELAY_VALUE = 00,
parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "TRUE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
// io fifo parameters
parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
parameter A_OS_DATA_RATE = "DDR",
parameter A_OS_DATA_WIDTH = 4,
parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
// this is used locally, not for external pushdown
// NOTE: the 0+ is needed in each to coerce to integer for addition.
// otherwise 4x 1'b values are added producing a 1'b value.
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
// assume odt per rank + any declared cke's
parameter AUXOUT_WIDTH = 4,
parameter LP_DDR_CK_WIDTH = 2
,parameter CKE_ODT_AUX = "FALSE"
)
(
//`include "phy.vh"
input rst,
input phy_clk,
input phy_ctl_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input phy_ctl_mstr_empty,
input [31:0] phy_ctl_wd,
input [`PC_DATA_OFFSET_RANGE] data_offset,
input phy_ctl_wr,
input if_empty_def,
input phyGo,
input input_sink,
output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory
output rclk,
output if_a_empty,
output if_empty,
output byte_rd_en,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
output phy_ctl_empty,
output phy_ctl_a_full,
output phy_ctl_full,
output [HIGHEST_LANE*12-1:0]mem_dq_out,
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
input [HIGHEST_LANE*10-1:0]mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
input [1:0] byte_rd_en_oth_banks,
output [AUXOUT_WIDTH-1:0] aux_out,
output reg rst_out = 0,
output reg mcGo=0,
output phy_ctl_ready,
output ref_dll_lock,
input if_rst,
input phy_read_calib,
input phy_write_calib,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input [2:0] calib_sel,
input calib_zero_ctrl,
input [HIGHEST_LANE-1:0] calib_zero_lanes,
input calib_in_common,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
output reg pi_phase_locked,
output pi_phase_locked_all,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam IO_A_START = 41;
localparam IO_A_END = 40;
localparam IO_B_START = 43;
localparam IO_B_END = 42;
localparam IO_C_START = 45;
localparam IO_C_END = 44;
localparam IO_D_START = 47;
localparam IO_D_END = 46;
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
localparam IO_A_X_END = (IO_A_X_START-1);
localparam IO_B_X_START = (IO_A_X_START + 2);
localparam IO_B_X_END = (IO_B_X_START -1);
localparam IO_C_X_START = (IO_B_X_START + 2);
localparam IO_C_X_END = (IO_C_X_START -1);
localparam IO_D_X_START = (IO_C_X_START + 2);
localparam IO_D_X_END = (IO_D_X_START -1);
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
wire A_pi_dqs_found;
wire A_pi_dqs_out_of_range;
wire A_pi_phase_locked;
wire A_pi_iserdes_rst;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_pi_rst_dqs_find;
reg A_po_fine_enable;
reg A_po_coarse_enable;
reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_rclk;
reg A_idelay_ce;
reg A_idelay_ld;
reg [29:0] A_fine_delay;
reg A_fine_delay_sel;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
wire B_pi_phase_locked;
wire B_pi_iserdes_rst;
wire B_pi_dqs_found;
wire B_pi_dqs_out_of_range;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
reg B_pi_rst_dqs_find;
reg B_po_fine_enable;
reg B_po_coarse_enable;
reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
wire B_rclk;
reg B_idelay_ce;
reg B_idelay_ld;
reg [29:0] B_fine_delay;
reg B_fine_delay_sel;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_coarse_enable;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_dqs_found;
wire D_pi_dqs_found;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire C_pi_phase_locked;
wire C_pi_iserdes_rst;
wire D_pi_phase_locked;
wire D_pi_iserdes_rst;
wire C_pi_dqs_out_of_range;
wire D_pi_dqs_out_of_range;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_rclk;
wire D_rclk;
reg C_idelay_ce;
reg D_idelay_ce;
reg C_idelay_ld;
reg D_idelay_ld;
reg C_pi_rst_dqs_find;
reg D_pi_rst_dqs_find;
reg [29:0] C_fine_delay;
reg [29:0] D_fine_delay;
reg C_fine_delay_sel;
reg D_fine_delay_sel;
wire pi_iserdes_rst;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_byte_rd_en;
wire B_byte_rd_en;
wire C_byte_rd_en;
wire D_byte_rd_en;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
//wire A_if_full;
//wire B_if_full;
//wire C_if_full;
//wire D_if_full;
//wire A_of_empty;
//wire B_of_empty;
//wire C_of_empty;
//wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_pre_fifo_a_full;
wire B_pre_fifo_a_full;
wire C_pre_fifo_a_full;
wire D_pre_fifo_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
wire A_pre_data_a_full;
wire B_pre_data_a_full;
wire C_pre_data_a_full;
wire D_pre_data_a_full;
wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation
wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //
wire [3:0] dummy_data;
wire [31:0] _phy_ctl_wd;
wire [1:0] phy_encalib;
assign pi_dqs_found_all =
(! PRESENT_DATA_A | A_pi_dqs_found) &
(! PRESENT_DATA_B | B_pi_dqs_found) &
(! PRESENT_DATA_C | C_pi_dqs_found) &
(! PRESENT_DATA_D | D_pi_dqs_found) ;
assign pi_dqs_found_any =
( PRESENT_DATA_A & A_pi_dqs_found) |
( PRESENT_DATA_B & B_pi_dqs_found) |
( PRESENT_DATA_C & C_pi_dqs_found) |
( PRESENT_DATA_D & D_pi_dqs_found) ;
assign pi_phase_locked_all =
(! PRESENT_DATA_A | A_pi_phase_locked) &
(! PRESENT_DATA_B | B_pi_phase_locked) &
(! PRESENT_DATA_C | C_pi_phase_locked) &
(! PRESENT_DATA_D | D_pi_phase_locked);
wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal
// which is combined into another signals such that
// the other signal isn't changed. The purpose
// is to fake the tools into ignoring dangling inputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :
(A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);
assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;
assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
reg rst_out_trig = 1'b0;
reg [31:0] rclk_delay;
reg rst_edge1 = 1'b0;
reg rst_edge2 = 1'b0;
reg rst_edge3 = 1'b0;
reg rst_edge_detect = 1'b0;
wire rclk_;
reg rst_out_start = 1'b0 ;
reg rst_primitives=0;
reg A_rst_primitives=0;
reg B_rst_primitives=0;
reg C_rst_primitives=0;
reg D_rst_primitives=0;
`ifdef USE_PHY_CONTROL_TEST
wire [15:0] test_output;
wire [15:0] test_input;
wire [2:0] test_select=0;
wire scan_enable = 0;
`endif
generate
genvar i;
if (RCLK_SELECT_LANE == "A") begin
assign rclk_ = A_rclk;
assign pi_iserdes_rst = A_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "B") begin
assign rclk_ = B_rclk;
assign pi_iserdes_rst = B_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "C") begin
assign rclk_ = C_rclk;
assign pi_iserdes_rst = C_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "D") begin
assign rclk_ = D_rclk;
assign pi_iserdes_rst = D_pi_iserdes_rst;
end
else begin
assign rclk_ = B_rclk; // default
end
endgenerate
assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;
assign pi_phase_locked_lanes =
{(! PRESENT_DATA_A[0] | A_pi_phase_locked),
(! PRESENT_DATA_B[0] | B_pi_phase_locked) ,
(! PRESENT_DATA_C[0] | C_pi_phase_locked) ,
(! PRESENT_DATA_D[0] | D_pi_phase_locked)};
assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};
// this block scrubs X from rclk_delay[11]
reg rclk_delay_11;
always @(rclk_delay[11]) begin : rclk_delay_11_blk
if ( rclk_delay[11])
rclk_delay_11 = 1;
else
rclk_delay_11 = 0;
end
always @(posedge phy_clk or posedge rst ) begin
// scrub 4-state values from rclk_delay[11]
if ( rst) begin
rst_out <= #1 0;
end
else begin
if ( rclk_delay_11)
rst_out <= #1 1;
end
end
always @(posedge phy_clk ) begin
// phy_ctl_ready drives reset of the system
rst_primitives <= !phy_ctl_ready ;
A_rst_primitives <= rst_primitives ;
B_rst_primitives <= rst_primitives ;
C_rst_primitives <= rst_primitives ;
D_rst_primitives <= rst_primitives ;
rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);
mcGo <= #1 rst_out ;
end
generate
if (BYTE_LANES[0]) begin
assign dummy_data[0] = 0;
end
else begin
assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];
end
if (BYTE_LANES[1]) begin
assign dummy_data[1] = 0;
end
else begin
assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];
end
if (BYTE_LANES[2]) begin
assign dummy_data[2] = 0;
end
else begin
assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];
end
if (BYTE_LANES[3]) begin
assign dummy_data[3] = 0;
end
else begin
assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];
end
if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
assign A_pre_data_a_full = A_pre_fifo_a_full;
end
else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
assign A_pre_data_a_full = 0;
end
if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
assign B_pre_data_a_full = B_pre_fifo_a_full;
end
else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
assign B_pre_data_a_full = 0;
end
if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
assign C_pre_data_a_full = C_pre_fifo_a_full;
end
else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
assign C_pre_data_a_full = 0;
end
if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
assign D_pre_data_a_full = D_pre_fifo_a_full;
end
else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
assign D_pre_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (HIGHEST_LANE > 1)
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
if (HIGHEST_LANE == 1)
assign _phy_ctl_wd = phy_ctl_wd;
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("A"),
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[11:0]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (A_PI_BURST_MODE),
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
.PO_FINE_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (A_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_A(
.mem_dq_out (mem_dq_out[11:0]),
.mem_dq_ts (mem_dq_ts[11:0]),
.mem_dq_in (mem_dq_in[9:0]),
.mem_dqs_out (mem_dqs_out[0]),
.mem_dqs_ts (mem_dqs_ts[0]),
.mem_dqs_in (mem_dqs_in[0]),
.rst (A_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (A_ddr_clk),
.rclk (A_rclk),
.pi_dqs_found (A_pi_dqs_found),
.dqs_out_of_range (A_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*A_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*A_of_empty*/),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.pre_fifo_a_full (A_pre_fifo_a_full),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (A_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (A_idelay_ce),
.idelay_ld (A_idelay_ld),
.pi_rst_dqs_find (A_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.pi_iserdes_rst (A_pi_iserdes_rst),
.pi_phase_locked (A_pi_phase_locked),
.fine_delay (A_fine_delay),
.fine_delay_sel (A_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_pre_fifo_a_full = 1'b0;
assign A_if_empty = 1'b0;
assign A_byte_rd_en = 1'b1;
assign A_if_a_empty = 1'b0;
assign A_pi_phase_locked = 1;
assign A_pi_dqs_found = 1;
assign A_rclk = 0;
assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign A_pi_counter_read_val = 0;
assign A_po_counter_read_val = 0;
assign A_pi_fine_overflow = 0;
assign A_po_coarse_overflow = 0;
assign A_po_fine_overflow = 0;
end
if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("B"),
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[23:12]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (B_PI_BURST_MODE),
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
.PO_FINE_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_B(
.mem_dq_out (mem_dq_out[23:12]),
.mem_dq_ts (mem_dq_ts[23:12]),
.mem_dq_in (mem_dq_in[19:10]),
.mem_dqs_out (mem_dqs_out[1]),
.mem_dqs_ts (mem_dqs_ts[1]),
.mem_dqs_in (mem_dqs_in[1]),
.rst (B_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (B_ddr_clk),
.rclk (B_rclk),
.pi_dqs_found (B_pi_dqs_found),
.dqs_out_of_range (B_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*B_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*B_of_empty*/),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.pre_fifo_a_full (B_pre_fifo_a_full),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (B_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (B_idelay_ce),
.idelay_ld (B_idelay_ld),
.pi_rst_dqs_find (B_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.pi_iserdes_rst (B_pi_iserdes_rst),
.pi_phase_locked (B_pi_phase_locked),
.fine_delay (B_fine_delay),
.fine_delay_sel (B_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_pre_fifo_a_full = 1'b0;
assign B_if_empty = 1'b0;
assign B_if_a_empty = 1'b0;
assign B_byte_rd_en = 1'b1;
assign B_pi_phase_locked = 1;
assign B_pi_dqs_found = 1;
assign B_rclk = 0;
assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign B_pi_counter_read_val = 0;
assign B_po_counter_read_val = 0;
assign B_pi_fine_overflow = 0;
assign B_po_coarse_overflow = 0;
assign B_po_fine_overflow = 0;
end
if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("C"),
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[35:24]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (C_PI_BURST_MODE),
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
.PO_FINE_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_C(
.mem_dq_out (mem_dq_out[35:24]),
.mem_dq_ts (mem_dq_ts[35:24]),
.mem_dq_in (mem_dq_in[29:20]),
.mem_dqs_out (mem_dqs_out[2]),
.mem_dqs_ts (mem_dqs_ts[2]),
.mem_dqs_in (mem_dqs_in[2]),
.rst (C_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (C_ddr_clk),
.rclk (C_rclk),
.pi_dqs_found (C_pi_dqs_found),
.dqs_out_of_range (C_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*C_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*C_of_empty*/),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.pre_fifo_a_full (C_pre_fifo_a_full),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (C_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (C_idelay_ce),
.idelay_ld (C_idelay_ld),
.pi_rst_dqs_find (C_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.pi_iserdes_rst (C_pi_iserdes_rst),
.pi_phase_locked (C_pi_phase_locked),
.fine_delay (C_fine_delay),
.fine_delay_sel (C_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_pre_fifo_a_full = 1'b0;
assign C_if_empty = 1'b0;
assign C_byte_rd_en = 1'b1;
assign C_if_a_empty = 1'b0;
assign C_pi_phase_locked = 1;
assign C_pi_dqs_found = 1;
assign C_rclk = 0;
assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign C_pi_counter_read_val = 0;
assign C_po_counter_read_val = 0;
assign C_pi_fine_overflow = 0;
assign C_po_coarse_overflow = 0;
assign C_po_fine_overflow = 0;
end
if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("D"),
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[47:36]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (D_PI_BURST_MODE),
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
.PO_FINE_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_D(
.mem_dq_out (mem_dq_out[47:36]),
.mem_dq_ts (mem_dq_ts[47:36]),
.mem_dq_in (mem_dq_in[39:30]),
.mem_dqs_out (mem_dqs_out[3]),
.mem_dqs_ts (mem_dqs_ts[3]),
.mem_dqs_in (mem_dqs_in[3]),
.rst (D_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (D_ddr_clk),
.rclk (D_rclk),
.pi_dqs_found (D_pi_dqs_found),
.dqs_out_of_range (D_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*D_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*D_of_empty*/),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.pre_fifo_a_full (D_pre_fifo_a_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_inc (idelay_inc),
.idelay_ce (D_idelay_ce),
.idelay_ld (D_idelay_ld),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (D_byte_rd_en),
// calibration signals
.pi_rst_dqs_find (D_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.pi_iserdes_rst (D_pi_iserdes_rst),
.pi_phase_locked (D_pi_phase_locked),
.fine_delay (D_fine_delay),
.fine_delay_sel (D_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_pre_fifo_a_full = 1'b0;
assign D_if_empty = 1'b0;
assign D_byte_rd_en = 1'b1;
assign D_if_a_empty = 1'b0;
assign D_rclk = 0;
assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign D_pi_dqs_found = 1;
assign D_pi_phase_locked = 1;
assign D_pi_counter_read_val = 0;
assign D_po_counter_read_val = 0;
assign D_pi_fine_overflow = 0;
assign D_po_coarse_overflow = 0;
assign D_po_fine_overflow = 0;
end
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
.INRANKA (in_rank[1:0]),
.INRANKB (in_rank[3:2]),
.INRANKC (in_rank[5:4]),
.INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (_phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock), // is reset while !locked
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
`ifdef USE_PHY_CONTROL_TEST
, .TESTINPUT (16'b0),
.TESTOUTPUT (test_output),
.TESTSELECT (test_select),
.SCANENABLEN (scan_enable)
`endif
);
// register outputs to give extra slack in timing
always @(posedge phy_clk ) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val<= #1 A_pi_counter_read_val;
pi_phase_locked <= #1 A_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 A_pi_dqs_found;
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
pi_phase_locked <= #1 B_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 B_pi_dqs_found;
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
pi_phase_locked <= #1 C_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 C_pi_dqs_found;
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
pi_phase_locked <= #1 D_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 D_pi_dqs_found;
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
end
default: begin
po_coarse_overflow <= po_coarse_overflow;
end
endcase
end
wire B_mux_ctrl;
wire C_mux_ctrl;
wire D_mux_ctrl;
generate
if (HIGHEST_LANE > 1)
assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));
else
assign B_mux_ctrl = 0;
if (HIGHEST_LANE > 2)
assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));
else
assign C_mux_ctrl = 0;
if (HIGHEST_LANE > 3)
assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));
else
assign D_mux_ctrl = 0;
endgenerate
always @(*) begin
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
if ( calib_sel[2]) begin
// if this is asserted, all calib signals are deasserted
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
end else
if (calib_in_common) begin
// if this is asserted, each signal is broadcast to all phasers
// in common
if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
if ( B_mux_ctrl) begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
if ( C_mux_ctrl) begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
if ( D_mux_ctrl) begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_read_en = po_counter_read_en;
D_po_counter_load_val = po_counter_load_val;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
end
else begin
// otherwise, only a single phaser is selected
case (calib_sel[1:0])
0: begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
1: begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
2: begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
3: begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_load_val = po_counter_load_val;
D_po_counter_read_en = po_counter_read_en;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
endcase
end
end
//obligatory phaser-ref
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST ( ! pll_lock)
);
// optional idelay_ctrl
generate
if ( GENERATE_IDELAYCTRL == "TRUE")
IDELAYCTRL idelayctrl (
.RDY (/*idelayctrl_rdy*/),
.REFCLK (idelayctrl_refclk),
.RST (rst)
);
endgenerate
endmodule
|
module qsys (
clk_clk,
reset_reset_n,
sdram_clock_areset_conduit_export,
sdram_clock_c0_clk,
sdram_read_control_fixed_location,
sdram_read_control_read_base,
sdram_read_control_read_length,
sdram_read_control_go,
sdram_read_control_done,
sdram_read_control_early_done,
sdram_read_user_read_buffer,
sdram_read_user_buffer_output_data,
sdram_read_user_data_available,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n,
sdram_write_control_fixed_location,
sdram_write_control_write_base,
sdram_write_control_write_length,
sdram_write_control_go,
sdram_write_control_done,
sdram_write_user_write_buffer,
sdram_write_user_buffer_input_data,
sdram_write_user_buffer_full);
input clk_clk;
input reset_reset_n;
input sdram_clock_areset_conduit_export;
output sdram_clock_c0_clk;
input sdram_read_control_fixed_location;
input [31:0] sdram_read_control_read_base;
input [31:0] sdram_read_control_read_length;
input sdram_read_control_go;
output sdram_read_control_done;
output sdram_read_control_early_done;
input sdram_read_user_read_buffer;
output [63:0] sdram_read_user_buffer_output_data;
output sdram_read_user_data_available;
output [12:0] sdram_wire_addr;
output [1:0] sdram_wire_ba;
output sdram_wire_cas_n;
output sdram_wire_cke;
output sdram_wire_cs_n;
inout [15:0] sdram_wire_dq;
output [1:0] sdram_wire_dqm;
output sdram_wire_ras_n;
output sdram_wire_we_n;
input sdram_write_control_fixed_location;
input [31:0] sdram_write_control_write_base;
input [31:0] sdram_write_control_write_length;
input sdram_write_control_go;
output sdram_write_control_done;
input sdram_write_user_write_buffer;
input [63:0] sdram_write_user_buffer_input_data;
output sdram_write_user_buffer_full;
endmodule
|
// See Line 54
module hangcase (/*AUTOARG*/);
//
assign w_rdat_ena = ({16{foo[ 0]}} & bar ) |
({16{foo[ 1]}} & bar ) |
({16{foo[ 2]}} & bar ) |
({16{foo[ 3]}} & bar ) |
({16{foo[ 4]}} & bar ) |
({16{foo[ 5]}} & bar ) |
({16{foo[ 6]}} & bar ) |
({16{foo[ 7]}} & bar ) |
({16{foo[ 8]}} & bar ) |
({16{foo[ 9]}} & bar ) |
({16{foo[10]}} & bar ) |
({16{foo[11]}} & bar ) |
({16{foo[12]}} & bar ) |
({16{foo[13]}} & bar ) |
({16{foo[14]}} & bar ) |
({16{foo[15]}} & bar ) ;
//
assign w_rdat_mrk = ({16{foo[ 0]}} & bar & baz ) |
({16{foo[ 1]}} & bar & baz ) |
({16{foo[ 2]}} & bar & baz ) |
({16{foo[ 3]}} & bar & baz ) |
({16{foo[ 4]}} & bar & baz ) |
({16{foo[ 5]}} & bar & baz ) |
({16{foo[ 6]}} & bar & baz ) |
({16{foo[ 7]}} & bar & baz ) |
({16{foo[ 8]}} & bar & baz ) |
({16{foo[ 9]}} & bar & baz ) |
({16{foo[10]}} & bar & baz ) |
({16{foo[11]}} & bar & baz ) |
({16{foo[12]}} & bar & baz ) |
({16{foo[13]}} & bar & baz ) |
({16{foo[14]}} & bar & baz ) |
({16{foo[15]}} & bar & baz ) ;
//
assign w_wdat_ena_set = ({16{ena_set}} & col_dec );
assign w_wdat_ena_clr = ({16{ena_clr}} & col_dec );
assign w_wdat_mrk_set = ({16{mrk_set}} & w_rdat_ena );
assign w_wdat_mrk_clr = ({16{mrk_clr}} & col_dec );
assign w_wdat_ena = (w_rdat_ena & ~w_wdat_ena_clr) | w_wdat_ena_set;
assign w_wdat_mrk = (w_rdat_mrk & ~w_wdat_mrk_clr) | w_wdat_mrk_set;
//
assign w_dat15_ena = foo[15] ? w_wdat_ena : bar;
//
assign w_dat15_mrk = foo[15] ? w_wdat_mrk : baz;
//^^^^ FIX NEWLINE ABOVE HERE
//
assign w_timeout_mrk = row_check ? w_wdat_mrk : r_timeout_mrk;
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2014 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer FIFO ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implementation of store buffer FIFO. ////
//// ////
//// To Do: ////
//// - N/A ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb_fifo.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.3 2002/11/06 13:53:41 simons
// SB mem width fixed.
//
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb_fifo(
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
parameter dw = 68;
parameter fw = `OR1200_SB_LOG;
parameter fl = `OR1200_SB_ENTRIES;
//
// FIFO signals
//
input clk_i; // Clock
input rst_i; // Reset
input [dw-1:0] dat_i; // Input data bus
input wr_i; // Write request
input rd_i; // Read request
output [dw-1:0] dat_o; // Output data bus
output full_o; // FIFO full
output empty_o;// FIFO empty
//
// Internal regs
//
reg [dw-1:0] mem [fl-1:0];
reg [dw-1:0] dat_o;
reg [fw+1:0] cntr;
reg [fw-1:0] wr_pntr;
reg [fw-1:0] rd_pntr;
reg empty_o;
reg full_o;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
full_o <= #1 1'b0;
empty_o <= #1 1'b1;
wr_pntr <= #1 {fw{1'b0}};
rd_pntr <= #1 {fw{1'b0}};
cntr <= #1 {fw+2{1'b0}};
dat_o <= #1 {dw{1'b0}};
end
else if (wr_i && rd_i) begin // FIFO Read and Write
mem[wr_pntr] <= #1 dat_i;
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
if (empty_o) begin
dat_o <= #1 dat_i;
end
else begin
dat_o <= #1 mem[rd_pntr];
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
else if (wr_i && !full_o) begin // FIFO Write
mem[wr_pntr] <= #1 dat_i;
cntr <= #1 cntr + 1'b1;
empty_o <= #1 1'b0;
if (cntr >= (fl-1)) begin
full_o <= #1 1'b1;
cntr <= #1 fl;
end
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
end
else if (rd_i && !empty_o) begin // FIFO Read
dat_o <= #1 mem[rd_pntr];
cntr <= #1 cntr - 1'b1;
full_o <= #1 1'b0;
if (cntr <= 1) begin
empty_o <= #1 1'b1;
cntr <= #1 {fw+2{1'b0}};
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
endmodule
|
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Register Slice
// Register selected channels on the forward and/or reverse signal paths.
// 5-channel memory-mapped AXI4 interfaces.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_register_slice
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
// C_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
parameter integer C_REG_CONFIG_AW = 0,
parameter integer C_REG_CONFIG_W = 0,
parameter integer C_REG_CONFIG_B = 0,
parameter integer C_REG_CONFIG_AR = 0,
parameter integer C_REG_CONFIG_R = 0
)
(
// System Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
wire reset;
localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;
`include "axi_infrastructure_v1_1_header.vh"
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;
assign reset = ~aresetn;
axi_infrastructure_v1_1_axi2vector #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_axi2vector_0 (
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awuser ( s_axi_awuser ) ,
.s_axi_awregion ( s_axi_awregion ) ,
.s_axi_wid ( s_axi_wid ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( s_axi_wuser ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( s_axi_buser ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_aruser ( s_axi_aruser ) ,
.s_axi_arregion ( s_axi_arregion ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( s_axi_ruser ) ,
.s_awpayload ( s_awpayload ) ,
.s_wpayload ( s_wpayload ) ,
.s_bpayload ( s_bpayload ) ,
.s_arpayload ( s_arpayload ) ,
.s_rpayload ( s_rpayload )
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AW )
)
aw_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_awpayload),
.S_VALID(s_axi_awvalid),
.S_READY(s_axi_awready),
// Master side
.M_PAYLOAD_DATA(m_awpayload),
.M_VALID(m_axi_awvalid),
.M_READY(m_axi_awready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_W )
)
w_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_wpayload),
.S_VALID(s_axi_wvalid),
.S_READY(s_axi_wready),
// Master side
.M_PAYLOAD_DATA(m_wpayload),
.M_VALID(m_axi_wvalid),
.M_READY(m_axi_wready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_B )
)
b_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_bpayload),
.S_VALID(m_axi_bvalid),
.S_READY(m_axi_bready),
// Master side
.M_PAYLOAD_DATA(s_bpayload),
.M_VALID(s_axi_bvalid),
.M_READY(s_axi_bready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AR )
)
ar_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_arpayload),
.S_VALID(s_axi_arvalid),
.S_READY(s_axi_arready),
// Master side
.M_PAYLOAD_DATA(m_arpayload),
.M_VALID(m_axi_arvalid),
.M_READY(m_axi_arready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_R )
)
r_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_rpayload),
.S_VALID(m_axi_rvalid),
.S_READY(m_axi_rready),
// Master side
.M_PAYLOAD_DATA(s_rpayload),
.M_VALID(s_axi_rvalid),
.M_READY(s_axi_rready)
);
axi_infrastructure_v1_1_vector2axi #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_vector2axi_0 (
.m_awpayload ( m_awpayload ) ,
.m_wpayload ( m_wpayload ) ,
.m_bpayload ( m_bpayload ) ,
.m_arpayload ( m_arpayload ) ,
.m_rpayload ( m_rpayload ) ,
.m_axi_awid ( m_axi_awid ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awuser ( m_axi_awuser ) ,
.m_axi_awregion ( m_axi_awregion ) ,
.m_axi_wid ( m_axi_wid ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wuser ( m_axi_wuser ) ,
.m_axi_bid ( m_axi_bid ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( m_axi_buser ) ,
.m_axi_arid ( m_axi_arid ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_aruser ( m_axi_aruser ) ,
.m_axi_arregion ( m_axi_arregion ) ,
.m_axi_rid ( m_axi_rid ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_ruser ( m_axi_ruser )
);
endmodule // axi_register_slice
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_bb.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_TB_V
`define SKY130_FD_SC_HDLL__XNOR3_TB_V
/**
* xnor3: 3-input exclusive NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xnor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__xnor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_TB_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Memory with multiple read ports and one write (broadcast) port.
module acl_multireadport_mem
#(
parameter LOG2DEPTH=10,
parameter WIDTH=32,
parameter NUMPORTS=13, // Number of ports desired
parameter USE2XCLOCK=1,
parameter DEDICATED_BROADCAST_PORT=0
)
(
input clk,
input clk2x,
input resetn,
// Broadcast interface
input [LOG2DEPTH-1:0] broadcast_addr,
input [WIDTH-1:0] broadcast_writedata,
input broadcast_read,
input broadcast_write,
output broadcast_waitrequest,
output broadcast_readdatavalid,
output [WIDTH-1:0] broadcast_readdata,
// Read port interfaces
input [NUMPORTS*LOG2DEPTH-1:0] rdport_addr,
input [NUMPORTS-1:0] rdport_read,
output reg [NUMPORTS-1:0] rdport_waitrequest,
output reg [NUMPORTS-1:0] rdport_readdatavalid,
output reg [NUMPORTS*WIDTH-1:0] rdport_readdata
);
/******************
* LOCAL PARAMETERS
*******************/
localparam DEPTH=2**LOG2DEPTH;
localparam PORTSPERMEM = (USE2XCLOCK) ? 4 : 2; //Dual-port + double-pumped block RAMs
localparam KERNPORTSPERMEM=PORTSPERMEM-DEDICATED_BROADCAST_PORT;
// Do ceiling manually: CEIL(NUMPORTS/KERNPORTSPERMEM)
localparam NUMMEMORIES=(NUMPORTS/KERNPORTSPERMEM +
((NUMPORTS%KERNPORTSPERMEM==0) ? 0 : 1));
/******************
* SIGNALS
*******************/
// Ports interfaces - connect these to rdport_ interface
reg [NUMMEMORIES*PORTSPERMEM*LOG2DEPTH-1:0] port_addr;
reg [NUMMEMORIES*PORTSPERMEM-1:0] port_read;
wire [NUMMEMORIES*PORTSPERMEM-1:0] port_waitrequest;
wire [NUMMEMORIES*PORTSPERMEM-1:0] port_readdatavalid;
wire [NUMMEMORIES*PORTSPERMEM*WIDTH-1:0] port_readdata;
reg [NUMMEMORIES-1:0] done_write;
/******************
* ARCHITECTURE
*******************/
// Connect kernel interfaces to ports. Really these only exist to prevent
// compile errors on trailing ports. Eg. If you want only 1 port the code
// will still instatiate a 4-port memory but the last 3 interfaces get
// synthesized away
integer k;
integer j;
always@*
begin
j=0;
for (k=0; k<NUMPORTS; k=k+1)
begin
port_addr[j*LOG2DEPTH +: LOG2DEPTH]=rdport_addr[k*LOG2DEPTH +: LOG2DEPTH];
port_read[j]=rdport_read[k];
rdport_waitrequest[k]=port_waitrequest[j];
rdport_readdatavalid[k]=port_readdatavalid[j];
rdport_readdata[k*WIDTH +: WIDTH]=port_readdata[j*WIDTH +: WIDTH];
//If the 4th port is dedicated to the host, skip it
j=(j%PORTSPERMEM==KERNPORTSPERMEM-1) ? j+1+DEDICATED_BROADCAST_PORT : j+1 ;
end
end
// If the host and kernels share a port, sel arbitrates between them.
// 1 selects the kernel, 0 selects the host
// Note it will always take the kernel's request, so the host may starve
reg [NUMMEMORIES-1:0] sel;
integer i;
always@*
for (i=0; i<NUMMEMORIES; i=i+1)
sel[i]=(!DEDICATED_BROADCAST_PORT) & (port_read[i+PORTSPERMEM-1]);
// Replicate number of memories to achieve desired number of ports
genvar p;
generate
for (p=0; p<NUMMEMORIES*PORTSPERMEM; p=p+PORTSPERMEM)
begin : mem_gen
if ( USE2XCLOCK )
begin
memory_block2x #(.LOG2DEPTH(LOG2DEPTH), .WIDTH(WIDTH)) mem(
.clk(clk),
.clk2x(clk2x),
.addr_1(port_addr[p*LOG2DEPTH +: LOG2DEPTH]),
.read_1(port_read[p]),
.data_out_1(port_readdata[p*WIDTH +: WIDTH]),
.valid_1(port_readdatavalid[p]),
.addr_2(port_addr[(p+1)*LOG2DEPTH +: LOG2DEPTH]),
.read_2(port_read[p+1]),
.data_out_2(port_readdata[(p+1)*WIDTH +: WIDTH]),
.valid_2(port_readdatavalid[p+1]),
.addr_3(port_addr[(p+2)*LOG2DEPTH +: LOG2DEPTH]),
.read_3(port_read[p+2]),
.data_out_3(port_readdata[(p+2)*WIDTH +: WIDTH]),
.valid_3(port_readdatavalid[p+2]),
.addr_4((sel) ? port_addr[(p+3)*LOG2DEPTH +: LOG2DEPTH] : broadcast_addr),
.data_4( broadcast_writedata),
.read_4((sel) ? port_read[p+3] : broadcast_read),
.write_4((sel) ? 1'b0 : broadcast_write),
.data_out_4( port_readdata[(p+3)*WIDTH +: WIDTH]),
.valid_4( port_readdatavalid[p+3])
);
//Connect host read signals to 4th port
assign broadcast_readdata=port_readdata[3*WIDTH +: WIDTH];
assign broadcast_readdatavalid=port_readdatavalid[3];
end
else
begin
memory_block #(.LOG2DEPTH(LOG2DEPTH), .WIDTH(WIDTH)) mem(
.clk(clk),
.clk2x(clk2x),
.addr_1(port_addr[p*LOG2DEPTH +: LOG2DEPTH]),
.read_1(port_read[p]),
.data_out_1(port_readdata[p*WIDTH +: WIDTH]),
.valid_1(port_readdatavalid[p]),
.addr_2((sel) ? port_addr[(p+1)*LOG2DEPTH +: LOG2DEPTH] : broadcast_addr),
.data_2( broadcast_writedata),
.read_2((sel) ? port_read[p+1] : broadcast_read),
.write_2((sel) ? 1'b0 : broadcast_write),
.data_out_2( port_readdata[(p+1)*WIDTH +: WIDTH]),
.valid_2( port_readdatavalid[p+1])
);
//Connect host read signals to 4th port
assign broadcast_readdata=port_readdata[1*WIDTH +: WIDTH];
assign broadcast_readdatavalid=port_readdatavalid[1];
end
assign port_waitrequest[p +: PORTSPERMEM]={PORTSPERMEM{1'b0}};
end
endgenerate
// If broadcast port is shared, track and make sure all memories have written
always@(posedge clk or negedge resetn)
if (!resetn)
done_write<={NUMMEMORIES{1'b0}};
else if (&done_write)
done_write<={NUMMEMORIES{1'b0}};
else
done_write<=done_write | ~sel;
// Stall the host and write it again until all memories have written.
// FIXME: What about host read?
assign broadcast_waitrequest=(!DEDICATED_BROADCAST_PORT) & |(done_write | ~sel);
endmodule
module memory_block
#(
parameter LOG2DEPTH=14,
parameter WIDTH=32
)
(
input clk,
input clk2x,
input [WIDTH-1:0] data_1,
input [WIDTH-1:0] data_2,
input [LOG2DEPTH-1:0] addr_1,
input [LOG2DEPTH-1:0] addr_2,
input read_1,
input read_2,
input write_1,
input write_2,
output [WIDTH-1:0] data_out_1,
output [WIDTH-1:0] data_out_2,
output valid_1,
output valid_2
);
localparam DEPTH=2**LOG2DEPTH;
reg clk_90deg,sel2x;
shiftreg readatavalid_1(.D(read_1), .clock(clk), .enable(1'b1), .Q(valid_1));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 2;
shiftreg readatavalid_2(.D(read_2), .clock(clk), .enable(1'b1), .Q(valid_2));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 2;
altsyncram altsyncram_component (
.clock0 (clk),
.wren_a (write_1),
.wren_b (write_2),
.address_a (addr_1),
.address_b (addr_2),
.data_a (data_1),
.data_b (data_2),
.q_a (data_out_1),
.q_b (data_out_2),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.ram_block_type = "M9K",
//altsyncram_component.numwords_a = DEPTH*8/WIDTH,
//altsyncram_component.numwords_b = DEPTH*8/WIDTH,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = WIDTH,
altsyncram_component.width_b = WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
module memory_block2x
#(
parameter LOG2DEPTH=14,
parameter WIDTH=32
)
(
input clk,
input clk2x,
input [WIDTH-1:0] data_1,
input [WIDTH-1:0] data_2,
input [WIDTH-1:0] data_3,
input [WIDTH-1:0] data_4,
input [LOG2DEPTH-1:0] addr_1,
input [LOG2DEPTH-1:0] addr_2,
input [LOG2DEPTH-1:0] addr_3,
input [LOG2DEPTH-1:0] addr_4,
input read_1,
input read_2,
input read_3,
input read_4,
input write_1,
input write_2,
input write_3,
input write_4,
output reg [WIDTH-1:0] data_out_1,
output reg [WIDTH-1:0] data_out_2,
output reg [WIDTH-1:0] data_out_3,
output reg [WIDTH-1:0] data_out_4,
output valid_1,
output valid_2,
output valid_3,
output valid_4
);
localparam DEPTH=2**LOG2DEPTH;
reg [WIDTH-1:0] data_1_reg /* synthesis dont_merge */;
reg [WIDTH-1:0] data_2_reg /* synthesis dont_merge */;
reg [WIDTH-1:0] data_3_reg /* synthesis dont_merge */;
reg [WIDTH-1:0] data_4_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_1_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_3_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_4_reg /* synthesis dont_merge */;
reg write_1_reg, write_2_reg /* synthesis maxfan=32 */;
reg write_3_reg, write_4_reg /* sytnthesis maxfan=32 */;
wire [WIDTH-1:0] data_out_a_unreg;
wire [WIDTH-1:0] data_out_b_unreg;
reg [WIDTH-1:0] data_out_a_reg;
reg [WIDTH-1:0] data_out_b_reg;
reg [WIDTH-1:0] data_out_a_reg2;
reg [WIDTH-1:0] data_out_b_reg2;
reg [WIDTH-1:0] data_1_reg2x;
reg [WIDTH-1:0] data_2_reg2x;
reg [WIDTH-1:0] data_3_reg2x;
reg [WIDTH-1:0] data_4_reg2x;
reg [LOG2DEPTH-1:0] addr_1_reg2x;
reg [LOG2DEPTH-1:0] addr_2_reg2x;
reg [LOG2DEPTH-1:0] addr_3_reg2x;
reg [LOG2DEPTH-1:0] addr_4_reg2x;
reg write_1_reg2x, write_2_reg2x;
reg write_3_reg2x, write_4_reg2x;
reg clk_90deg,sel2x /* synthesis maxfan=32 */;
//Register before double pumping
always@(posedge clk)
begin
addr_1_reg <= addr_1;
addr_2_reg <= addr_2;
addr_3_reg <= addr_3;
addr_4_reg <= addr_4;
data_1_reg <= data_1;
data_2_reg <= data_2;
data_3_reg <= data_3;
data_4_reg <= data_4;
write_1_reg <= write_1;
write_2_reg <= write_2;
write_3_reg <= write_3;
write_4_reg <= write_4;
end
// Consider making only one port r/w and the rest read only
always@(posedge clk2x)
begin
addr_1_reg2x <= (!sel2x) ? addr_1_reg : addr_3_reg2x;
addr_2_reg2x <= (!sel2x) ? addr_2_reg : addr_4_reg2x;
addr_3_reg2x <= addr_3_reg;
addr_4_reg2x <= addr_4_reg;
data_1_reg2x <= (!sel2x) ? data_1_reg : data_3_reg2x;
data_2_reg2x <= (!sel2x) ? data_2_reg : data_4_reg2x;
data_3_reg2x <= data_3_reg;
data_4_reg2x <= data_4_reg;
write_1_reg2x <= (!sel2x) ? write_1_reg : write_3_reg2x;
write_2_reg2x <= (!sel2x) ? write_2_reg : write_4_reg2x;
write_3_reg2x <= write_3_reg;
write_4_reg2x <= write_4_reg;
end
shiftreg readatavalid_1(.D(read_1), .clock(clk), .enable(1'b1), .Q(valid_1));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 4;
shiftreg readatavalid_2(.D(read_2), .clock(clk), .enable(1'b1), .Q(valid_2));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 4;
shiftreg readatavalid_3(.D(read_3), .clock(clk), .enable(1'b1), .Q(valid_3));
defparam readatavalid_3.WIDTH = 1;
defparam readatavalid_3.DEPTH = 4;
shiftreg readatavalid_4(.D(read_4), .clock(clk), .enable(1'b1), .Q(valid_4));
defparam readatavalid_4.WIDTH = 1;
defparam readatavalid_4.DEPTH = 4;
//Convert clock to data signal
always@(negedge clk2x)
clk_90deg<=clk;
always@(posedge clk2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clk
altsyncram altsyncram_component (
.clock0 (clk2x),
.wren_a (write_1_reg2x),
.wren_b (write_2_reg2x),
.address_a (addr_1_reg2x),
.address_b (addr_2_reg2x),
.data_a (data_1_reg2x),
.data_b (data_2_reg2x),
.q_a (data_out_a_unreg),
.q_b (data_out_b_unreg),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.ram_block_type = "M9K",
//altsyncram_component.numwords_a = DEPTH*8/WIDTH,
//altsyncram_component.numwords_b = DEPTH*8/WIDTH,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = WIDTH,
altsyncram_component.width_b = WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
always@(posedge clk2x)
begin
data_out_a_reg<=data_out_a_unreg;
data_out_b_reg<=data_out_b_unreg;
data_out_a_reg2<=data_out_a_reg;
data_out_b_reg2<=data_out_b_reg;
end
always@(posedge clk)
begin
data_out_1 <= data_out_a_reg2;
data_out_2 <= data_out_b_reg2;
data_out_3 <= data_out_a_reg;
data_out_4 <= data_out_b_reg;
end
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module shiftreg(D, clock, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, enable;
output [WIDTH-1:0] Q;
reg [WIDTH-1:0] local_ffs [0:DEPTH-1];
genvar i;
generate
for(i = 0; i<=DEPTH-1; i = i+1)
begin : local_register
always @(posedge clock)
if (enable)
if (i==0)
local_ffs[0] <= D;
else
local_ffs[i] <= local_ffs[i-1];
end
endgenerate
assign Q = local_ffs[DEPTH-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx Inc.
// Engineer: Parimal Patel
// Create Date: 06/21/2016 09:22:41 AM
// Module Name: PdmDes
// Project Name: PYNQ
//////////////////////////////////////////////////////////////////////////////////
module PdmDes(
input clk,
input en,
output done,
output [15:0] dout,
output pdm_m_clk_o,
input pdm_m_data_i
);
parameter C_PDM_FREQ_HZ=2000000;
reg en_int=0;
reg done_int=0;
reg clk_int=0;
reg pdm_clk_rising;
reg [15:0] pdm_tmp, dout;
integer cnt_bits=0;
integer cnt_clk=0;
assign done = done_int;
assign pdm_m_clk_o = clk_int;
// register en input
always @(posedge clk)
en_int <= en;
// Sample input serial data process
always @(posedge clk)
if (en==0)
pdm_tmp <= 0;
else
if (pdm_clk_rising)
pdm_tmp <= {pdm_tmp[14:0],pdm_m_data_i};
// Count the number of sampled bits
always @(posedge clk)
begin
if (en_int==0)
cnt_bits <=0;
else
if (pdm_clk_rising)
begin
if (cnt_bits == 15)
cnt_bits <=0;
else
cnt_bits <= cnt_bits + 1;
end
end
// Generate the done signal
always @(posedge clk)
begin
if (pdm_clk_rising)
begin
if (cnt_bits==0)
begin
if (en_int)
begin
done_int<=1;
dout <= pdm_tmp;
end
end
end
else
done_int <= 0;
end
// Generate PDM Clock, that runs independent from the enable signal, therefore
// the onboard microphone will always send data
always @(posedge clk)
begin
// clk_int <= 0;
if (cnt_clk == 24) // (C_SYS_CLK_FREQ_MHZ*1000000)/(C_PDM_FREQ_HZ*2))-1 where C_SYS_CLK_FREQ_MHZ=100, C_PDM_FREQ_HZ=2MHz
begin
cnt_clk <= 0;
clk_int <= ~clk_int;
if (clk_int == 0)
pdm_clk_rising <= 1;
end
else
begin
cnt_clk <= cnt_clk + 1;
pdm_clk_rising <= 0;
end
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $
//
// $Date: 2009-01-20 10:25:29 $
// $Revision: 1.14 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: $
// Revision 1.14 2009/01/20 10:25:29 rherveille
// Added clock synchronization logic
// Fixed slave_wait signal
//
// Revision 1.13 2009/01/19 20:29:26 rherveille
// Fixed synopsys miss spell (synopsis)
// Fixed cr[0] register width
// Fixed ! usage instead of ~
// Fixed bit controller parameter width to 18bits
//
// Revision 1.12 2006/09/04 09:08:13 rherveille
// fixed short scl high pulse after clock stretch
// fixed slave model not returning correct '(n)ack' signal
//
// Revision 1.11 2004/05/07 11:02:26 rherveille
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
//
// Revision 1.10 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.9 2003/03/10 14:26:37 rherveille
// Fixed cmd_ack generation item (no bug).
//
// Revision 1.8 2003/02/05 00:06:10 rherveille
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
//
// Revision 1.7 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.6 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.5 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.4 2002/10/30 18:10:07 rherveille
// Fixed some reported minor start/stop generation timing issuess.
//
// Revision 1.3 2002/06/15 07:37:03 rherveille
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
//
// Revision 1.2 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
//
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start: SCL ~~~~~~~~~~\____
// SDA ~~~~~~~~\______
// x | A | B | C | D | i
//
// repstart SCL ____/~~~~\___
// SDA __/~~~\______
// x | A | B | C | D | i
//
// stop SCL ____/~~~~~~~~
// SDA ==\____/~~~~~
// x | A | B | C | D | i
//
//- write SCL ____/~~~~\____
// SDA ==X=========X=
// x | A | B | C | D | i
//
//- read SCL ____/~~~~\____
// SDA XXXX=====XXXX
// x | A | B | C | D | i
//
// Timing: Normal mode Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl 100KHz 400KHz
// Th_scl 4.0us 0.6us High period of SCL
// Tl_scl 4.7us 1.3us Low period of SCL
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
//
// synopsys translate_off
`include "i2c_timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_bit_ctrl (
input clk, // system clock
input rst, // synchronous active high reset
input nReset, // asynchronous active low reset
input ena, // core enable signal
input [15:0] clk_cnt, // clock prescale value
input [ 3:0] cmd, // command (from byte controller)
output reg cmd_ack, // command complete acknowledge
output reg busy, // i2c bus busy
output reg al, // i2c bus arbitration lost
input din,
output reg dout,
input scl_i, // i2c clock line input
output scl_o, // i2c clock line output
output reg scl_oen, // i2c clock line output enable (active low)
input sda_i, // i2c data line input
output sda_o, // i2c data line output
output reg sda_oen // i2c data line output enable (active low)
);
//
// variable declarations
//
reg [ 1:0] cSCL, cSDA; // capture SCL and SDA
reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs
reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs
reg dSCL, dSDA; // delayed versions of sSCL and sSDA
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
reg slave_wait; // slave inserts wait states
reg [15:0] cnt; // clock divider counter (synthesis)
reg [13:0] filter_cnt; // clock divider for filter
// state machine variable
reg [17:0] c_state; // synopsys enum_state
// SWM: register indicating enable points for signal tap:
// SWM: use the "noprune" directive to avoid the register being removed
(* noprune *) reg swm_i2c_signaltap_enable;
always @(posedge clk)
swm_i2c_signaltap_enable <= clk_en;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= #1 scl_oen;
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
// slave_wait remains asserted until the slave releases SCL
always @(posedge clk or negedge nReset)
if (!nReset) slave_wait <= 1'b0;
else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
// master drives SCL high, but another master pulls it low
// master start counting down its low cycle now (clock synchronization)
wire scl_sync = dSCL & ~sSCL & scl_oen;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if (~nReset)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if (rst || ~|cnt || !ena || scl_sync)
begin
cnt <= #1 clk_cnt;
clk_en <= #1 1'b1;
end
else if (slave_wait)
begin
cnt <= #1 cnt;
clk_en <= #1 1'b0;
end
else
begin
cnt <= #1 cnt - 16'h1;
clk_en <= #1 1'b0;
end
// generate bus status controller
// capture SDA and SCL
// reduce metastability risk
always @(posedge clk or negedge nReset)
if (!nReset)
begin
cSCL <= #1 2'b00;
cSDA <= #1 2'b00;
end
else if (rst)
begin
cSCL <= #1 2'b00;
cSDA <= #1 2'b00;
end
else
begin
cSCL <= {cSCL[0],scl_i};
cSDA <= {cSDA[0],sda_i};
end
// filter SCL and SDA signals; (attempt to) remove glitches
always @(posedge clk or negedge nReset)
if (!nReset ) filter_cnt <= 14'h0;
else if (rst || !ena ) filter_cnt <= 14'h0;
else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
else filter_cnt <= filter_cnt -1;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
fSCL <= 3'b111;
fSDA <= 3'b111;
end
else if (rst)
begin
fSCL <= 3'b111;
fSDA <= 3'b111;
end
else if (~|filter_cnt)
begin
fSCL <= {fSCL[1:0],cSCL[1]};
fSDA <= {fSDA[1:0],cSDA[1]};
end
// generate filtered SCL and SDA signals
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else if (rst)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else
begin
sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
reg sta_condition;
reg sto_condition;
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else if (rst)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else
begin
sta_condition <= #1 ~sSDA & dSDA & sSCL;
sto_condition <= #1 sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if (!nReset) busy <= #1 1'b0;
else if (rst ) busy <= #1 1'b0;
else busy <= #1 (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= #1 1'b0;
else if (rst)
cmd_stop <= #1 1'b0;
else if (clk_en)
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= #1 1'b0;
else if (rst)
al <= #1 1'b0;
else
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if (sSCL & ~dSCL) dout <= #1 sSDA;
// generate statemachine
// nxt_state decoder
parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
end
else if (rst | al)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
end
else
begin
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state) // synopsys full_case parallel_case
// idle state
idle:
begin
case (cmd) // synopsys full_case parallel_case
`I2C_CMD_START: c_state <= #1 start_a;
`I2C_CMD_STOP: c_state <= #1 stop_a;
`I2C_CMD_WRITE: c_state <= #1 wr_a;
`I2C_CMD_READ: c_state <= #1 rd_a;
default: c_state <= #1 idle;
endcase
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 sda_oen; // keep SDA in same state
sda_chk <= #1 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= #1 start_b;
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= #1 start_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= #1 start_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= #1 start_e;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= #1 stop_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= #1 stop_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= #1 stop_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= #1 rd_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b1; // tri-state SDA
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= #1 rd_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= #1 rd_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= #1 wr_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 din; // set SDA
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= #1 wr_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 din; // keep SDA
sda_chk <= #1 1'b0; // don't check SDA output yet
// allow some time for SDA and SCL to settle
end
wr_c:
begin
c_state <= #1 wr_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 din;
sda_chk <= #1 1'b1; // check SDA output
end
wr_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 din;
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
endcase
end
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_up_converter(clock, resetn, i_start,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 8;
parameter DATAOUT_WIDTH = 32;
input clock, resetn, i_start;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
// Specify state machine states.
parameter s_IDLE = 2'b00;
parameter s_RECEIVED_B1 = 2'b01;
parameter s_RECEIVED_B2 = 2'b10;
parameter s_RECEIVED_B3 = 2'b11;
// State and next_state variables
reg [1:0] present_state, next_state;
reg [DATAOUT_WIDTH-1:0] data_received;
// Simple state machine to store 1 byte per cycle, for 4 cycles,
// then output it downstream
always@(*)
begin
case (present_state)
s_IDLE: if (i_datain_valid)
next_state <= s_RECEIVED_B1;
else
next_state <= s_IDLE;
s_RECEIVED_B1: if (i_datain_valid)
next_state <= s_RECEIVED_B2;
else
next_state <= s_RECEIVED_B1;
s_RECEIVED_B2: if (i_datain_valid)
next_state <= s_RECEIVED_B3;
else
next_state <= s_RECEIVED_B2;
s_RECEIVED_B3: if (i_datain_valid)
next_state <= s_IDLE;
else
next_state <= s_RECEIVED_B3;
default: next_state <= 3'bxxx;
endcase
end
// Simple state machine to save 1 byte per cycle
always@(posedge clock or negedge resetn)
begin
if (~resetn)
data_received <= {DATAOUT_WIDTH{1'b0}};
else
begin
if ((present_state == s_IDLE) & i_datain_valid)
data_received <= {data_received[4*DATAIN_WIDTH-1:DATAIN_WIDTH], i_datain};
else if ((present_state == s_RECEIVED_B1) & i_datain_valid)
data_received <= {data_received[4*DATAIN_WIDTH-1:2*DATAIN_WIDTH], i_datain, data_received[DATAIN_WIDTH-1:0] };
else if ((present_state == s_RECEIVED_B2) & i_datain_valid)
data_received <= {data_received[4*DATAIN_WIDTH-1:3*DATAIN_WIDTH], i_datain, data_received[2*DATAIN_WIDTH-1:0] };
else if ((present_state == s_RECEIVED_B3) & i_datain_valid)
data_received <= {i_datain, data_received[3*DATAIN_WIDTH-1:0] };
else
data_received <= data_received;
end
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
o_dataout_valid <= 1'b0;
else
begin
o_dataout_valid <= (present_state == s_RECEIVED_B3) & i_datain_valid;
end
end
// State assignment
always@(posedge clock or negedge resetn)
begin
if (~resetn)
present_state <= s_IDLE;
else
present_state <= (i_start) ? next_state : s_IDLE;
end
assign o_dataout = data_received;
assign o_datain_stall = (i_start) ? i_dataout_stall : 1'b0;
endmodule
|
module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
);
parameter
N_IN = 7,
N_OUT = 90;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
// detect falling edge
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4) begin
req <= 1;
n <= 60;
end
else if(tri_sw5)
req <= 0;
end
fib
#(
.N_IN ( N_IN ) ,
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( RSTN ) ,
.clk ( clk ) ,
.req ( req ) ,
.n ( n ) ,
.ack ( ack ) ,
.result ( result )
);
/* 7SEG LED
+--------+--------+--------+--------+
| data0 | data1 | data2 | data3 |
+--------+--------+--------+--------+
| data4 | data5 | data6 | data7 |
+--------+--------+--------+--------+
| data8 | data9 | data10 | data11 |
+--------+--------+--------+--------+
| data12 | data13 | data14 | data15 |
+--------+--------+--------+--------+
*/
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ) ,
.data3 ( n ) ,
.data4 ( result[89:64] ) ,
.data5 ( result[63:48] ) ,
.data6 ( result[47:32] ) ,
.data7 ( result[31:16] ) ,
.data8 ( result[15: 0] ) ,
.data9 ( 0 ) ,
.data10 ( 0 ) ,
.data11 ( 0 ) ,
.data12 ( 0 ) ,
.data13 ( 0 ) ,
.data14 ( 0 ) ,
.data15 ( 0 ) ,
.SEG_A ( SEG_A ) ,
.SEG_B ( SEG_B ) ,
.SEG_C ( SEG_C ) ,
.SEG_D ( SEG_D ) ,
.SEG_E ( SEG_E ) ,
.SEG_F ( SEG_F ) ,
.SEG_G ( SEG_G ) ,
.SEG_H ( SEG_H ) ,
.SEG_SEL ( SEG_SEL_IK )
);
endmodule
|
module top;
reg pass;
reg signed [7:0] neg = -2;
reg signed [7:0] m1 = -1;
reg signed [7:0] zero = 0;
reg signed [7:0] one = 1;
reg signed [7:0] pos = 2;
reg signed [7:0] pose = 2;
reg signed [7:0] poso = 3;
reg signed [7:0] res;
initial begin
pass = 1'b1;
#1;
/* Positive exponent. */
res = neg**pose;
if (res !== 4) begin
$display("Failed neg**pos even, got %d", res);
pass = 1'b0;
end
res = neg**poso;
if (res !== -8) begin
$display("Failed neg**pos odd, got %d", res);
pass = 1'b0;
end
res = m1**pose;
if (res !== 1) begin
$display("Failed -1**pos even, got %d", res);
pass = 1'b0;
end
res = m1**poso;
if (res !== -1) begin
$display("Failed -1**pos odd, got %d", res);
pass = 1'b0;
end
res = zero**pos;
if (res !== 0) begin
$display("Failed 0**pos, got %d", res);
pass = 1'b0;
end
res = one**pos;
if (res !== 1) begin
$display("Failed 1**pos, got %d", res);
pass = 1'b0;
end
res = pos**pos;
if (res !== 4) begin
$display("Failed 1**pos, got %d", res);
pass = 1'b0;
end
/* Zero exponent. */
res = neg**zero;
if (res !== 1) begin
$display("Failed neg**0, got %d", res);
pass = 1'b0;
end
res = m1**zero;
if (res !== 1) begin
$display("Failed -1**0, got %d", res);
pass = 1'b0;
end
res = zero**zero;
if (res !== 1) begin
$display("Failed 0**0, got %d", res);
pass = 1'b0;
end
res = one**zero;
if (res !== 1) begin
$display("Failed 1**0, got %d", res);
pass = 1'b0;
end
res = pos**zero;
if (res !== 1) begin
$display("Failed pos**0, got %d", res);
pass = 1'b0;
end
/* Negative exponent. */
res = neg**m1;
if (res !== 0) begin
$display("Failed neg**neg got %d", res);
pass = 1'b0;
end
res = m1**neg;
if (res !== 1) begin
$display("Failed -1**neg (even) got %d", res);
pass = 1'b0;
end
res = m1**m1;
if (res !== -1) begin
$display("Failed -1**neg (odd) got %d", res);
pass = 1'b0;
end
res = zero**m1;
if (res !== 'sbx) begin
$display("Failed 0**neg got %d", res);
pass = 1'b0;
end
res = one**m1;
if (res !== 1) begin
$display("Failed 1**neg got %d", res);
pass = 1'b0;
end
res = pos**m1;
if (res !== 0) begin
$display("Failed pos**neg got %d", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_sitofp_32ns_32_6
#(parameter
ID = 3,
NUM_STAGE = 6,
din0_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
//------------------------Instantiation------------------
ANN_ap_sitofp_4_no_dsp_32 ANN_ap_sitofp_4_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
end
end
endmodule
|
//-------------------------------------------------------------------
//-- echowire2_tb.v
//-- Banco de pruebas para el eco cableado del puerto serie y las
//-- comprobaciones de las señales DTR y RTS
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
module echowire2_tb();
//-- Declaracion de los cables
reg dtr = 0;
reg rts = 0;
reg rx = 0;
wire tx, led1, led2;
wire tx2, rx2;
wire extwire;
//-- Instanciar el componente
echowire2
dut(
.dtr(dtr),
.rts(rts),
.D1(led1),
.D2(led2),
.tx2(tx2),
.rx2(rx2),
.tx(tx),
.rx(rx)
);
//-- Generar cambios en dtr. Los mismos deben reflejarse en el cable D1
always
#2 dtr <= ~dtr;
//-- Generar cambios en rts. Se deben reflejar en el cable D2
always
#3 rts = ~rts;
//-- Generar cambios en rs. Se reflejan en TX
always
#1 rx <= ~rx;
//-- Conectar el cable externo
assign tx2 = rx2;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("echowire2_tb.vcd");
$dumpvars(0, echowire2_tb);
# 200 $display("FIN de la simulacion");
$finish;
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pclk_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pclk_pll (
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
locked,
phasedone);
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire3;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire locked = sub_wire3;
wire phasedone = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.phasestep (phasestep),
.phaseupdown (phaseupdown),
.inclk (sub_wire6),
.phasecounterselect (phasecounterselect),
.scanclk (scanclk),
.clk (sub_wire0),
.locked (sub_wire3),
.phasedone (sub_wire4),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.charge_pump_current_bits = 1,
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.loop_filter_c_bits = 0,
altpll_component.loop_filter_r_bits = 27,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpcie_pclk_pll",
altpll_component.lpm_type = "altpll",
altpll_component.m = 12,
altpll_component.m_initial = 1,
altpll_component.m_ph = 0,
altpll_component.n = 1,
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.vco_post_scale = 1,
altpll_component.width_clock = 10,
altpll_component.c0_high = 6,
altpll_component.c0_initial = 1,
altpll_component.c0_low = 6,
altpll_component.c0_mode = "even",
altpll_component.c0_ph = 0,
altpll_component.c1_high = 6,
altpll_component.c1_initial = 1,
altpll_component.c1_low = 6,
altpll_component.c1_mode = "even",
altpll_component.c1_ph = 0,
altpll_component.clk0_counter = "c0",
altpll_component.clk1_counter = "c1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "305.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CHARGE_PUMP_CURRENT_BITS NUMERIC "1"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LOOP_FILTER_C_BITS NUMERIC "0"
// Retrieval info: CONSTANT: LOOP_FILTER_R_BITS NUMERIC "27"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: M NUMERIC "6"
// Retrieval info: CONSTANT: M_INITIAL NUMERIC "1"
// Retrieval info: CONSTANT: M_PH NUMERIC "0"
// Retrieval info: CONSTANT: N NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_POST_SCALE NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: CONSTANT: c0_high NUMERIC "3"
// Retrieval info: CONSTANT: c0_initial NUMERIC "1"
// Retrieval info: CONSTANT: c0_low NUMERIC "3"
// Retrieval info: CONSTANT: c0_mode STRING "even"
// Retrieval info: CONSTANT: c0_ph NUMERIC "0"
// Retrieval info: CONSTANT: c1_high NUMERIC "3"
// Retrieval info: CONSTANT: c1_initial NUMERIC "1"
// Retrieval info: CONSTANT: c1_low NUMERIC "3"
// Retrieval info: CONSTANT: c1_mode STRING "even"
// Retrieval info: CONSTANT: c1_ph NUMERIC "0"
// Retrieval info: CONSTANT: clk0_counter STRING "c0"
// Retrieval info: CONSTANT: clk1_counter STRING "c1"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:33:50 11/11/2015
// Design Name:
// Module Name: GameWithSound
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GameWithSound(input clk25, input Reset,
input [9:0] xpos,
input [9:0] ypos,
input rota,
input rotb,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output Speaker);
reg PlayAgain;
reg PlayAgain1;
reg [1:0] Choice, Choice1;
// paddle movement
reg [8:0] paddlePosition;
reg [2:0] quadAr, quadBr;
reg [3:0] score;
wire [3:0] scoreOnesDigit;
wire [3:0] scoreTensDigit;
assign scoreOnesDigit = score % 10;
assign scoreTensDigit = score / 10;
wire tensDigit;
wire onesDigit;
wire digitPixel;
assign digitPixel = tensDigit || onesDigit; // 76
VGA7SegDisplay VGA7SegDisplayTens(9'd100,9'd300,xpos,ypos,scoreTensDigit,tensDigit);
VGA7SegDisplay VGA7SegDisplayOnes(9'd130,9'd300,xpos,ypos,scoreOnesDigit,onesDigit);
always @(posedge clk25) quadAr <= {quadAr[1:0], rota};
always @(posedge clk25) quadBr <= {quadBr[1:0], rotb};
always @(posedge clk25)
if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1])
begin
if(quadAr[2] ^ quadBr[1]) begin
if(paddlePosition < 508) // make sure the value doesn't overflow
begin
paddlePosition <= paddlePosition + 3'd4;
Choice <= 2'b00;
PlayAgain <= 1;
end
else
PlayAgain <= 0;
end
else begin
if(paddlePosition > 2'd3) // make sure the value doesn't underflow
begin
paddlePosition <= paddlePosition - 3'd4;
Choice <= 2'b01;
PlayAgain <= 1;
end
else
PlayAgain <= 0;
end
end
// ball movement
reg [9:0] ballX;
reg [8:0] ballY;
reg ballXdir, ballYdir;
reg bounceX, bounceY;
wire endOfFrame = (xpos == 0 && ypos == 480);
always @(posedge clk25) begin
if (endOfFrame) begin // update ball position at end of each frame
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballX <= 480;
ballY <= 300;
end
else begin
if (ballXdir ^ bounceX)
ballX <= ballX + 2'd2;
else
ballX <= ballX - 2'd2;
if (ballYdir ^ bounceY)
ballY <= ballY + 2'd2;
else
ballY <= ballY - 2'd2;
end
end
end
// pixel color
reg [5:0] missTimer;
wire visible = (xpos < 640 && ypos < 480);
wire top = (visible && ypos <= 3);
wire bottom = (visible && ypos >= 476);
wire left = (visible && xpos <= 3);
wire right = (visible && xpos >= 636);
wire border = (visible && (left || right || top));
wire paddle = (xpos >= paddlePosition+4 && xpos <= paddlePosition+124 && ypos >= 440 && ypos <= 447);
wire ball = (xpos >= ballX && xpos <= ballX+7 && ypos >= ballY && ypos <= ballY+7);
wire background = (visible && !(border || paddle || ball));
wire checkerboard = (xpos[5] ^ ypos[5]);
wire missed = visible && missTimer != 0;
assign red = { missed || border || paddle, 2'b0 };
assign green = { !missed && (border || paddle || ball), digitPixel, digitPixel };
assign blue = { !missed && (border || ball) || digitPixel, background && checkerboard || digitPixel};
// ball collision
always @(posedge clk25) begin
if (!endOfFrame) begin
PlayAgain1 <= 0;
if (ball && (left || right))
bounceX <= 1;
if (ball && (top || bottom || (paddle && ballYdir)))
bounceY <= 1;
if (ball && bottom)
begin
missTimer <= 63;
score <= -1;
end
end
else begin
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballXdir <= 1;
ballYdir <= 1;
bounceX <= 0;
bounceY <= 0;
score <= -1;
PlayAgain1 <= 0;
end
else begin
if (bounceX)
ballXdir <= ~ballXdir;
if (bounceY)
if(ballYdir) begin
score <= score + 1;
//Choice1 <= 2'b10;
PlayAgain1 <= 1;
ballYdir <= ~ballYdir;
end
else
begin
ballYdir <= ~ballYdir;
PlayAgain1 <= 0;
end
bounceX <= 0;
bounceY <= 0;
if (missTimer != 0)
missTimer <= missTimer - 1'b1;
end
end
end
PlaySound PlayMusic(PlayAgain|PlayAgain1, Speaker, Reset, clk25, Choice);
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:33 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_processing_system7_0_2 -prefix
// design_1_processing_system7_0_2_ design_1_processing_system7_0_2_stub.v
// Design : design_1_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module design_1_processing_system7_0_2(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// hps_design_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
hps_design_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
`define MEMORY_CONTROLLER_TAGS 1
`define MEMORY_CONTROLLER_TAG_SIZE 1
`define TAG__str 1'b0
`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 32
module memory_controller
(
clk,
memory_controller_address,
memory_controller_write_enable,
memory_controller_in,
memory_controller_out
);
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
input memory_controller_write_enable;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [4:0] str_address;
reg str_write_enable;
reg [7:0] str_in;
wire [7:0] str_out;
single_port_ram _str (
.clk( clk ),
.addr( str_address ),
.we( str_write_enable ),
.data( str_in ),
.out( str_out )
);
wire tag;
//must use all wires inside module.....
assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
always @(posedge clk)
prevTag <= tag;
always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
begin
case(tag)
1'b0:
begin
str_address = memory_controller_address[5-1+0:0];
str_write_enable = memory_controller_write_enable;
str_in[8-1:0] = memory_controller_in[8-1:0];
end
endcase
case(prevTag)
1'b0:
memory_controller_out = str_out;
endcase
end
endmodule
module memset
(
clk,
reset,
start,
finish,
return_val,
m,
c,
n,
memory_controller_write_enable,
memory_controller_address,
memory_controller_in,
memory_controller_out
);
output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
input clk;
input reset;
input start;
output finish;
reg finish;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
input [31:0] c;
input [31:0] n;
output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output memory_controller_write_enable;
reg memory_controller_write_enable;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [3:0] cur_state;
/*
parameter Wait = 4'd0;
parameter entry = 4'd1;
parameter entry_1 = 4'd2;
parameter entry_2 = 4'd3;
parameter bb = 4'd4;
parameter bb_1 = 4'd5;
parameter bb1 = 4'd6;
parameter bb1_1 = 4'd7;
parameter bb_nph = 4'd8;
parameter bb2 = 4'd9;
parameter bb2_1 = 4'd10;
parameter bb2_2 = 4'd11;
parameter bb2_3 = 4'd12;
parameter bb2_4 = 4'd13;
parameter bb4 = 4'd14;
*/
memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out);
reg [31:0] indvar;
reg var1;
reg [31:0] tmp;
reg [31:0] tmp8;
reg var2;
reg [31:0] var0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
reg [31:0] indvar_next;
reg exitcond;
always @(posedge clk)
if (reset)
cur_state <= 4'b0000;
else
case(cur_state)
4'b0000:
begin
finish <= 1'b0;
if (start == 1'b1)
cur_state <= 4'b0001;
else
cur_state <= 4'b0000;
end
4'b0001:
begin
var0 <= n & 32'b00000000000000000000000000000011;
cur_state <= 4'b0010;
end
4'b0010:
begin
var1 <= 1'b0;
var0 <= 32'b00000000000000000000000000000000;
cur_state <= 4'b0011;
end
4'b0011:
begin
if (|var1) begin
cur_state <= 4'b0110;
end
else
begin
cur_state <= 4'b0100;
end
end
4'b0100:
begin
cur_state <= 4'b0101;
end
4'b0101:
begin
cur_state <= 4'b0110;
end
4'b0110:
begin
var2 <= | (n [31:4]);
cur_state <= 4'b0111;
end
4'b0111:
begin
if (|var2)
begin
cur_state <= 4'b1110;
end
else
begin
cur_state <= 4'b1000;
end
end
4'b1000:
begin
tmp <= n ;
indvar <= 32'b00000000000000000000000000000000;
cur_state <= 4'b1001;
end
4'b1001:
begin
cur_state <= 4'b1010;
end
4'b1010:
begin
tmp8 <= indvar;
indvar_next <= indvar;
cur_state <= 4'b1011;
end
4'b1011:
begin
scevgep <= (m & tmp8);
exitcond <= (indvar_next == tmp);
cur_state <= 4'b1100;
end
4'b1100:
begin
s_07 <= scevgep;
cur_state <= 4'b1101;
end
4'b1101:
begin
if (exitcond)
begin
cur_state <= 4'b1110;
end
else
begin
indvar <= indvar_next;
cur_state <= 4'b1001;
end
end
4'b1110:
begin
return_val <= m;
finish <= 1'b1;
cur_state <= 4'b0000;
end
endcase
always @(cur_state)
begin
case(cur_state)
4'b1101:
begin
memory_controller_address = s_07;
memory_controller_write_enable = 1'b1;
memory_controller_in = c;
end
endcase
end
endmodule
|
/*******************************************************************************
* Module: pll_base
* Date:2014-05-01
* Author: Andrey Filippov
* Description: PLLE2_BASE wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* pll_base.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pll_base.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module pll_base#(
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", // "OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT = 1, // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT0_DIVIDE = 1, // CLK0 outout divide, integer 1..128
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE" // Delays "DONE" signal until MMCM is locked
)
(
input clkin, // General clock input
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkfbout, // dedicate feedback output
output locked // PLL locked output
);
PLLE2_BASE #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_BASE_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst) // input
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FA_PP_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_PP_BLACKBOX_V
|
//rd0 - 128bit, aligned (also supports unaligned)
//rd1 - 64bit, aligned (also supports unaligned)
//rd2 - 64bit, aligned (also supports unaligned)
//wr0 - 128/64/32bit (4 bit enable), aligned
//wr1 - 64/32bit (2 bit enable), aligned
module reg_512x32b_3r_2w
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr1_addr, wr0_en,
wr1_en, wr0_data, wr1_data
`ifdef FPGA
, clk_double
`endif
);
input clk;
`ifdef FPGA
input clk_double;
`endif
output [127:0] rd0_data;
output [63:0] rd1_data;
output [63:0] rd2_data;
input [8:0] rd0_addr;
input [8:0] rd1_addr;
input [8:0] rd2_addr;
input [8:0] wr0_addr;
input [8:0] wr1_addr;
input [3:0] wr0_en;
input [1:0] wr1_en;
input [127:0] wr0_data;
input [63:0] wr1_data;
/////////////
wire [8:0] rd0_addr_last;
wire [8:0] rd1_addr_last;
wire [8:0] rd2_addr_last;
reg [127:0] rd0_data;
reg [63:0] rd1_data;
reg [63:0] rd2_data;
wire [8:0] rd0_addr_plus1;
wire [8:0] rd0_addr_plus2;
wire [8:0] rd0_addr_plus3;
assign rd0_addr_plus1 = rd0_addr + 1'b1;
assign rd0_addr_plus2 = rd0_addr + 2'b10;
assign rd0_addr_plus3 = rd0_addr + 2'b11;
wire [31:0] rd0_data_bank0;
wire [31:0] rd0_data_bank1;
wire [31:0] rd0_data_bank2;
wire [31:0] rd0_data_bank3;
reg [6:0] rd0_addr_bank0;
reg [6:0] rd0_addr_bank1;
reg [6:0] rd0_addr_bank2;
reg [6:0] rd0_addr_bank3;
//see mux at end of module
wire [8:0] rd1_addr_plus1;
assign rd1_addr_plus1 = rd1_addr + 1'b1;
wire [31:0] rd1_data_bank0;
wire [31:0] rd1_data_bank1;
wire [31:0] rd1_data_bank2;
wire [31:0] rd1_data_bank3;
reg [6:0] rd1_addr_bank0;
reg [6:0] rd1_addr_bank1;
reg [6:0] rd1_addr_bank2;
reg [6:0] rd1_addr_bank3;
//see mux at end of module
wire [8:0] rd2_addr_plus1;
assign rd2_addr_plus1 = rd2_addr + 1'b1;
wire [31:0] rd2_data_bank0;
wire [31:0] rd2_data_bank1;
wire [31:0] rd2_data_bank2;
wire [31:0] rd2_data_bank3;
reg [6:0] rd2_addr_bank0;
reg [6:0] rd2_addr_bank1;
reg [6:0] rd2_addr_bank2;
reg [6:0] rd2_addr_bank3;
//see mux at end of module
/////
reg wr0_en_bank0;
reg wr0_en_bank1;
reg wr0_en_bank2;
reg wr0_en_bank3;
reg [31:0] wr0_data_bank0;
reg [31:0] wr0_data_bank1;
reg [31:0] wr0_data_bank2;
reg [31:0] wr0_data_bank3;
//see mux at end of module
reg wr1_en_bank0;
reg wr1_en_bank1;
reg wr1_en_bank2;
reg wr1_en_bank3;
reg [31:0] wr1_data_bank0;
reg [31:0] wr1_data_bank1;
reg [31:0] wr1_data_bank2;
reg [31:0] wr1_data_bank3;
//see mux at end of module
`ifdef FPGA
reg_128x32b_3r_2w_fpga bank0(
.clk_double(clk_double),
`else
reg_128x32b_3r_2w bank0(
`endif
.rd0_addr(rd0_addr_bank0),
.rd0_data(rd0_data_bank0),
.rd1_addr(rd1_addr_bank0),
.rd1_data(rd1_data_bank0),
.rd2_addr(rd2_addr_bank0),
.rd2_data(rd2_data_bank0),
.wr0_addr(wr0_addr[8:2]),
.wr0_en(wr0_en_bank0),
.wr0_data(wr0_data_bank0),
.wr1_addr(wr1_addr[8:2]),
.wr1_en(wr1_en_bank0),
.wr1_data(wr1_data_bank0),
.clk(clk)
);
`ifdef FPGA
reg_128x32b_3r_2w_fpga bank1(
.clk_double(clk_double),
`else
reg_128x32b_3r_2w bank1(
`endif
.rd0_addr(rd0_addr_bank1),
.rd0_data(rd0_data_bank1),
.rd1_addr(rd1_addr_bank1),
.rd1_data(rd1_data_bank1),
.rd2_addr(rd2_addr_bank1),
.rd2_data(rd2_data_bank1),
.wr0_addr(wr0_addr[8:2]),
.wr0_en(wr0_en_bank1),
.wr0_data(wr0_data_bank1),
.wr1_addr(wr1_addr[8:2]),
.wr1_en(wr1_en_bank1),
.wr1_data(wr1_data_bank1),
.clk(clk)
);
`ifdef FPGA
reg_128x32b_3r_2w_fpga bank2(
.clk_double(clk_double),
`else
reg_128x32b_3r_2w bank2(
`endif
.rd0_addr(rd0_addr_bank2),
.rd0_data(rd0_data_bank2),
.rd1_addr(rd1_addr_bank2),
.rd1_data(rd1_data_bank2),
.rd2_addr(rd2_addr_bank2),
.rd2_data(rd2_data_bank2),
.wr0_addr(wr0_addr[8:2]),
.wr0_en(wr0_en_bank2),
.wr0_data(wr0_data_bank2),
.wr1_addr(wr1_addr[8:2]),
.wr1_en(wr1_en_bank2),
.wr1_data(wr1_data_bank2),
.clk(clk)
);
`ifdef FPGA
reg_128x32b_3r_2w_fpga bank3(
.clk_double(clk_double),
`else
reg_128x32b_3r_2w bank3(
`endif
.rd0_addr(rd0_addr_bank3),
.rd0_data(rd0_data_bank3),
.rd1_addr(rd1_addr_bank3),
.rd1_data(rd1_data_bank3),
.rd2_addr(rd2_addr_bank3),
.rd2_data(rd2_data_bank3),
.wr0_addr(wr0_addr[8:2]),
.wr0_en(wr0_en_bank3),
.wr0_data(wr0_data_bank3),
.wr1_addr(wr1_addr[8:2]),
.wr1_en(wr1_en_bank3),
.wr1_data(wr1_data_bank3),
.clk(clk)
);
//Bank distribution for 128/64/32 write bit port
always @(wr0_data or wr0_addr or wr0_en)
begin
casex({wr0_en,wr0_addr[1:0]})
6'b0001_00:
begin
wr0_en_bank0 <= 1'b1;
wr0_en_bank1 <= 1'b0;
wr0_en_bank2 <= 1'b0;
wr0_en_bank3 <= 1'b0;
wr0_data_bank0 <= wr0_data[31:0];
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= {32{1'bx}};
end
6'b0001_01:
begin
wr0_en_bank0 <= 1'b0;
wr0_en_bank1 <= 1'b1;
wr0_en_bank2 <= 1'b0;
wr0_en_bank3 <= 1'b0;
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= wr0_data[31:0];
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= {32{1'bx}};
end
6'b0001_10:
begin
wr0_en_bank0 <= 1'b0;
wr0_en_bank1 <= 1'b0;
wr0_en_bank2 <= 1'b1;
wr0_en_bank3 <= 1'b0;
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= wr0_data[31:0];
wr0_data_bank3 <= {32{1'bx}};
end
6'b0001_11:
begin
wr0_en_bank0 <= 1'b0;
wr0_en_bank1 <= 1'b0;
wr0_en_bank2 <= 1'b0;
wr0_en_bank3 <= 1'b1;
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= wr0_data[31:0];
end
6'b0011_00:
begin
wr0_en_bank0 <= 1'b1;
wr0_en_bank1 <= 1'b1;
wr0_en_bank2 <= 1'b0;
wr0_en_bank3 <= 1'b0;
wr0_data_bank0 <= wr0_data[31:0];
wr0_data_bank1 <= wr0_data[63:32];
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= {32{1'bx}};
end
6'b0011_10:
begin
wr0_en_bank0 <= 1'b0;
wr0_en_bank1 <= 1'b0;
wr0_en_bank2 <= 1'b1;
wr0_en_bank3 <= 1'b1;
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= wr0_data[31:0];
wr0_data_bank3 <= wr0_data[63:32];
end
6'b1111_00:
begin
wr0_en_bank0 <= 1'b1;
wr0_en_bank1 <= 1'b1;
wr0_en_bank2 <= 1'b1;
wr0_en_bank3 <= 1'b1;
wr0_data_bank0 <= wr0_data[31:0];
wr0_data_bank1 <= wr0_data[63:32];
wr0_data_bank2 <= wr0_data[95:64];
wr0_data_bank3 <= wr0_data[127:96];
end
6'b0000_??:
begin
wr0_en_bank0 <= 1'b0;
wr0_en_bank1 <= 1'b0;
wr0_en_bank2 <= 1'b0;
wr0_en_bank3 <= 1'b0;
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= {32{1'bx}};
end
default:
begin
wr0_en_bank0 <= 1'bx;
wr0_en_bank1 <= 1'bx;
wr0_en_bank2 <= 1'bx;
wr0_en_bank3 <= 1'bx;
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= {32{1'bx}};
end
endcase
end
//Bank distribution for 64/32 bit write port
always @(wr1_data or wr1_addr or wr1_en)
begin
casex({wr1_en,wr1_addr[1:0]})
4'b01_00:
begin
wr1_en_bank0 <= 1'b1;
wr1_en_bank1 <= 1'b0;
wr1_en_bank2 <= 1'b0;
wr1_en_bank3 <= 1'b0;
wr1_data_bank0 <= wr1_data[31:0];
wr1_data_bank1 <= {32{1'bx}};
wr1_data_bank2 <= {32{1'bx}};
wr1_data_bank3 <= {32{1'bx}};
end
4'b01_01:
begin
wr1_en_bank0 <= 1'b0;
wr1_en_bank1 <= 1'b1;
wr1_en_bank2 <= 1'b0;
wr1_en_bank3 <= 1'b0;
wr1_data_bank0 <= {32{1'bx}};
wr1_data_bank1 <= wr1_data[31:0];
wr1_data_bank2 <= {32{1'bx}};
wr1_data_bank3 <= {32{1'bx}};
end
4'b01_10:
begin
wr1_en_bank0 <= 1'b0;
wr1_en_bank1 <= 1'b0;
wr1_en_bank2 <= 1'b1;
wr1_en_bank3 <= 1'b0;
wr1_data_bank0 <= {32{1'bx}};
wr1_data_bank1 <= {32{1'bx}};
wr1_data_bank2 <= wr1_data[31:0];
wr1_data_bank3 <= {32{1'bx}};
end
4'b01_11:
begin
wr1_en_bank0 <= 1'b0;
wr1_en_bank1 <= 1'b0;
wr1_en_bank2 <= 1'b0;
wr1_en_bank3 <= 1'b1;
wr1_data_bank0 <= {32{1'bx}};
wr1_data_bank1 <= {32{1'bx}};
wr1_data_bank2 <= {32{1'bx}};
wr1_data_bank3 <= wr1_data[31:0];
end
4'b11_00:
begin
wr1_en_bank0 <= 1'b1;
wr1_en_bank1 <= 1'b1;
wr1_en_bank2 <= 1'b0;
wr1_en_bank3 <= 1'b0;
wr1_data_bank0 <= wr1_data[31:0];
wr1_data_bank1 <= wr1_data[63:32];
wr1_data_bank2 <= {32{1'bx}};
wr1_data_bank3 <= {32{1'bx}};
end
4'b11_10:
begin
wr1_en_bank0 <= 1'b0;
wr1_en_bank1 <= 1'b0;
wr1_en_bank2 <= 1'b1;
wr1_en_bank3 <= 1'b1;
wr1_data_bank0 <= {32{1'bx}};
wr1_data_bank1 <= {32{1'bx}};
wr1_data_bank2 <= wr1_data[31:0];
wr1_data_bank3 <= wr1_data[63:32];
end
4'b00_??:
begin
wr1_en_bank0 <= 1'b0;
wr1_en_bank1 <= 1'b0;
wr1_en_bank2 <= 1'b0;
wr1_en_bank3 <= 1'b0;
wr1_data_bank0 <= {32{1'bx}};
wr1_data_bank1 <= {32{1'bx}};
wr1_data_bank2 <= {32{1'bx}};
wr1_data_bank3 <= {32{1'bx}};
end
default:
begin
wr1_en_bank0 <= 1'bx;
wr1_en_bank1 <= 1'bx;
wr1_en_bank2 <= 1'bx;
wr1_en_bank3 <= 1'bx;
wr1_data_bank0 <= {32{1'bx}};
wr1_data_bank1 <= {32{1'bx}};
wr1_data_bank2 <= {32{1'bx}};
wr1_data_bank3 <= {32{1'bx}};
end
endcase
end
dff rd_addr_delay[9+9+9-1:0]
(.q({rd0_addr_last, rd1_addr_last, rd2_addr_last}),
.d({rd0_addr, rd1_addr, rd2_addr}),
.clk(clk),
.rst(1'b0));
//Bank distribution for 128/64/32 bit read port
always @(rd0_addr or rd0_addr_plus1 or rd0_addr_plus2 or rd0_addr_plus3)
begin
casex(rd0_addr[1:0])
2'b00:
begin
rd0_addr_bank0 <= rd0_addr[8:2];
rd0_addr_bank1 <= rd0_addr_plus1[8:2];
rd0_addr_bank2 <= rd0_addr_plus2[8:2];
rd0_addr_bank3 <= rd0_addr_plus3[8:2];
end
2'b01:
begin
rd0_addr_bank0 <= rd0_addr_plus3[8:2];
rd0_addr_bank1 <= rd0_addr[8:2];
rd0_addr_bank2 <= rd0_addr_plus1[8:2];
rd0_addr_bank3 <= rd0_addr_plus2[8:2];
end
2'b10:
begin
rd0_addr_bank0 <= rd0_addr_plus2[8:2];
rd0_addr_bank1 <= rd0_addr_plus3[8:2];
rd0_addr_bank2 <= rd0_addr[8:2];
rd0_addr_bank3 <= rd0_addr_plus1[8:2];
end
2'b11:
begin
rd0_addr_bank0 <= rd0_addr_plus1[8:2];
rd0_addr_bank1 <= rd0_addr_plus2[8:2];
rd0_addr_bank2 <= rd0_addr_plus3[8:2];
rd0_addr_bank3 <= rd0_addr[8:2];
end
default:
begin
rd0_addr_bank0 <= {7{1'bx}};
rd0_addr_bank1 <= {7{1'bx}};
rd0_addr_bank2 <= {7{1'bx}};
rd0_addr_bank3 <= {7{1'bx}};
end
endcase
end
always @(rd0_addr_last or rd0_data_bank0 or rd0_data_bank1 or
rd0_data_bank2 or rd0_data_bank3)
begin
casex(rd0_addr_last[1:0])
2'b00:
begin
rd0_data <= {rd0_data_bank3,rd0_data_bank2,
rd0_data_bank1,rd0_data_bank0};
end
2'b01:
begin
rd0_data <= {rd0_data_bank0,rd0_data_bank3,
rd0_data_bank2,rd0_data_bank1};
end
2'b10:
begin
rd0_data <= {rd0_data_bank1,rd0_data_bank0,
rd0_data_bank3,rd0_data_bank2};
end
2'b11:
begin
rd0_data <= {rd0_data_bank2,rd0_data_bank1,
rd0_data_bank0,rd0_data_bank3};
end
default:
begin
rd0_data <= {128{1'bx}};
end
endcase
end
//Bank distribution for 64/32 bit read port
always @(rd1_addr or rd1_addr_plus1)
begin
casex(rd1_addr[1:0])
2'b00:
begin
rd1_addr_bank0 <= rd1_addr[8:2];
rd1_addr_bank1 <= rd1_addr_plus1[8:2];
rd1_addr_bank2 <= {7{1'bx}};
rd1_addr_bank3 <= {7{1'bx}};
end
2'b01:
begin
rd1_addr_bank0 <= {7{1'bx}};
rd1_addr_bank1 <= rd1_addr[8:2];
rd1_addr_bank2 <= rd1_addr_plus1[8:2];
rd1_addr_bank3 <= {7{1'bx}};
end
2'b10:
begin
rd1_addr_bank0 <= {7{1'bx}};
rd1_addr_bank1 <= {7{1'bx}};
rd1_addr_bank2 <= rd1_addr[8:2];
rd1_addr_bank3 <= rd1_addr_plus1[8:2];
end
2'b11:
begin
rd1_addr_bank0 <= rd1_addr_plus1[8:2];
rd1_addr_bank1 <= {7{1'bx}};
rd1_addr_bank2 <= {7{1'bx}};
rd1_addr_bank3 <= rd1_addr[8:2];
end
default:
begin
rd1_addr_bank0 <= {7{1'bx}};
rd1_addr_bank1 <= {7{1'bx}};
rd1_addr_bank2 <= {7{1'bx}};
rd1_addr_bank3 <= {7{1'bx}};
end
endcase
end
always @(rd1_addr_last or rd1_data_bank0 or rd1_data_bank1 or
rd1_data_bank2 or rd1_data_bank3)
begin
casex(rd1_addr_last[1:0])
2'b00:
begin
rd1_data <= {rd1_data_bank1,rd1_data_bank0};
end
2'b01:
begin
rd1_data <= {rd1_data_bank2,rd1_data_bank1};
end
2'b10:
begin
rd1_data <= {rd1_data_bank3,rd1_data_bank2};
end
2'b11:
begin
rd1_data <= {rd1_data_bank0,rd1_data_bank3};
end
default:
begin
rd1_data <= {128{1'bx}};
end
endcase
end
//Bank distribution for 64/32 bit read port
always @(rd2_addr or rd2_addr_plus1)
begin
casex(rd2_addr[1:0])
2'b00:
begin
rd2_addr_bank0 <= rd2_addr[8:2];
rd2_addr_bank1 <= rd2_addr_plus1[8:2];
rd2_addr_bank2 <= {7{1'bx}};
rd2_addr_bank3 <= {7{1'bx}};
end
2'b01:
begin
rd2_addr_bank0 <= {7{1'bx}};
rd2_addr_bank1 <= rd2_addr[8:2];
rd2_addr_bank2 <= rd2_addr_plus1[8:2];
rd2_addr_bank3 <= {7{1'bx}};
end
2'b10:
begin
rd2_addr_bank0 <= {7{1'bx}};
rd2_addr_bank1 <= {7{1'bx}};
rd2_addr_bank2 <= rd2_addr[8:2];
rd2_addr_bank3 <= rd2_addr_plus1[8:2];
end
2'b11:
begin
rd2_addr_bank0 <= rd2_addr_plus1[8:2];
rd2_addr_bank1 <= {7{1'bx}};
rd2_addr_bank2 <= {7{1'bx}};
rd2_addr_bank3 <= rd2_addr[8:2];
end
default:
begin
rd2_addr_bank0 <= {7{1'bx}};
rd2_addr_bank1 <= {7{1'bx}};
rd2_addr_bank2 <= {7{1'bx}};
rd2_addr_bank3 <= {7{1'bx}};
end
endcase
end
always @(rd2_addr_last or rd2_data_bank0 or rd2_data_bank1 or
rd2_data_bank2 or rd2_data_bank3)
begin
casex(rd2_addr_last[1:0])
2'b00:
begin
rd2_data <= {rd2_data_bank1,rd2_data_bank0};
end
2'b01:
begin
rd2_data <= {rd2_data_bank2,rd2_data_bank1};
end
2'b10:
begin
rd2_data <= {rd2_data_bank3,rd2_data_bank2};
end
2'b11:
begin
rd2_data <= {rd2_data_bank0,rd2_data_bank3};
end
default:
begin
rd2_data <= {128{1'bx}};
end
endcase
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
module allocator
(/*AUTOARG*/
// Outputs
allocator_cu_valid, allocator_cu_rejected, allocator_wg_id_out,
allocator_cu_id_out, allocator_wf_count, allocator_vgpr_size_out,
allocator_sgpr_size_out, allocator_lds_size_out,
allocator_gds_size_out, allocator_vgpr_start_out,
allocator_sgpr_start_out, allocator_lds_start_out,
allocator_gds_start_out,
// Inputs
clk, rst, inflight_wg_buffer_alloc_wg_id,
inflight_wg_buffer_alloc_num_wf,
inflight_wg_buffer_alloc_vgpr_size,
inflight_wg_buffer_alloc_sgpr_size,
inflight_wg_buffer_alloc_lds_size,
inflight_wg_buffer_alloc_gds_size, dis_controller_cu_busy,
dis_controller_alloc_ack, dis_controller_start_alloc,
grt_cam_up_valid, grt_cam_up_cu_id, grt_cam_up_vgpr_strt,
grt_cam_up_vgpr_size, grt_cam_up_sgpr_strt, grt_cam_up_sgpr_size,
grt_cam_up_lds_strt, grt_cam_up_lds_size, grt_cam_up_gds_strt,
grt_cam_up_gds_size, grt_cam_up_wg_count
);
parameter WG_ID_WIDTH = 6;
parameter CU_ID_WIDTH = 6;
parameter NUMBER_CU = 64;
parameter VGPR_ID_WIDTH = 10;
parameter NUMBER_VGPR_SLOTS = 1024;
parameter SGPR_ID_WIDTH = 10;
parameter NUMBER_SGPR_SLOTS = 1024;
parameter LDS_ID_WIDTH = 10;
parameter NUMBER_LDS_SLOTS = 1024;
parameter WG_SLOT_ID_WIDTH = 10;
parameter NUMBER_WF_SLOTS = 40;
parameter GDS_ID_WIDTH = 10;
parameter GDS_SIZE = 1024;
parameter WF_COUNT_WIDTH = 4;
// Allocation input port
input clk,rst;
input [WG_ID_WIDTH-1:0] inflight_wg_buffer_alloc_wg_id;
input [WF_COUNT_WIDTH-1:0] inflight_wg_buffer_alloc_num_wf;
input [VGPR_ID_WIDTH :0] inflight_wg_buffer_alloc_vgpr_size;
input [SGPR_ID_WIDTH :0] inflight_wg_buffer_alloc_sgpr_size;
input [LDS_ID_WIDTH :0] inflight_wg_buffer_alloc_lds_size;
input [GDS_ID_WIDTH :0] inflight_wg_buffer_alloc_gds_size;
input [NUMBER_CU-1:0] dis_controller_cu_busy;
input dis_controller_alloc_ack;
input dis_controller_start_alloc;
// Allocation output port
output allocator_cu_valid;
output allocator_cu_rejected;
output [WG_ID_WIDTH-1:0] allocator_wg_id_out;
output [CU_ID_WIDTH-1 :0] allocator_cu_id_out;
output [WF_COUNT_WIDTH-1:0] allocator_wf_count;
output [VGPR_ID_WIDTH :0] allocator_vgpr_size_out;
output [SGPR_ID_WIDTH :0] allocator_sgpr_size_out;
output [LDS_ID_WIDTH :0] allocator_lds_size_out;
output [GDS_ID_WIDTH :0] allocator_gds_size_out;
output [VGPR_ID_WIDTH-1 :0] allocator_vgpr_start_out;
output [SGPR_ID_WIDTH-1 :0] allocator_sgpr_start_out;
output [LDS_ID_WIDTH-1 :0] allocator_lds_start_out;
output [GDS_ID_WIDTH-1 :0] allocator_gds_start_out;
// CAM update port
input grt_cam_up_valid;
input [CU_ID_WIDTH-1 :0] grt_cam_up_cu_id;
input [VGPR_ID_WIDTH-1 :0] grt_cam_up_vgpr_strt;
input [VGPR_ID_WIDTH :0] grt_cam_up_vgpr_size;
input [SGPR_ID_WIDTH-1 :0] grt_cam_up_sgpr_strt;
input [SGPR_ID_WIDTH :0] grt_cam_up_sgpr_size;
input [LDS_ID_WIDTH-1 :0] grt_cam_up_lds_strt;
input [LDS_ID_WIDTH :0] grt_cam_up_lds_size;
input [GDS_ID_WIDTH-1 :0] grt_cam_up_gds_strt;
input [GDS_ID_WIDTH :0] grt_cam_up_gds_size;
input [WG_SLOT_ID_WIDTH:0] grt_cam_up_wg_count;
// Flop inputs
reg alloc_valid_i;
reg [WG_ID_WIDTH-1:0] alloc_wg_id_i;
reg [WF_COUNT_WIDTH-1:0] alloc_num_wf_i;
reg [VGPR_ID_WIDTH :0] alloc_vgpr_size_i;
reg [SGPR_ID_WIDTH :0] alloc_sgpr_size_i;
reg [LDS_ID_WIDTH :0] alloc_lds_size_i;
reg [GDS_ID_WIDTH :0] alloc_gds_size_i;
reg [NUMBER_CU-1:0] dis_controller_cu_busy_i;
reg cam_up_valid_i;
reg [CU_ID_WIDTH-1 :0] cam_up_cu_id_i;
reg [VGPR_ID_WIDTH-1 :0] cam_up_vgpr_strt_i;
reg [VGPR_ID_WIDTH :0] cam_up_vgpr_size_i;
reg [SGPR_ID_WIDTH-1 :0] cam_up_sgpr_strt_i;
reg [SGPR_ID_WIDTH :0] cam_up_sgpr_size_i;
reg [LDS_ID_WIDTH-1 :0] cam_up_lds_strt_i;
reg [LDS_ID_WIDTH :0] cam_up_lds_size_i;
reg [GDS_ID_WIDTH-1 :0] cam_up_gds_strt_i;
reg [GDS_ID_WIDTH :0] cam_up_gds_size_i;
reg [WG_SLOT_ID_WIDTH:0] cam_up_wg_count_i;
// cam outputs
reg cam_out_valid;
wire [NUMBER_CU-1 :0] vgpr_search_out, sgpr_search_out, lds_search_out,
wg_search_out;
reg gds_valid;
// Signals that bypass the cam
reg cam_wait_valid;
reg [WG_ID_WIDTH-1 : 0] cam_wait_wg_id;
reg [WF_COUNT_WIDTH-1: 0] cam_wait_wf_count;
reg [VGPR_ID_WIDTH:0] cam_wait_vgpr_size;
reg [SGPR_ID_WIDTH:0] cam_wait_sgpr_size;
reg [LDS_ID_WIDTH:0] cam_wait_lds_size;
reg [GDS_ID_WIDTH:0] cam_wait_gds_size;
reg [GDS_ID_WIDTH-1:0] cam_wait_gds_strt;
reg [NUMBER_CU-1:0] cam_wait_dis_controller_cu_busy;
// And cam outputs to check if there is anything we can use, choose the right cu
reg anded_cam_out_valid;
reg [NUMBER_CU-1: 0] anded_cam_out;
reg [WG_ID_WIDTH-1 :0] anded_cam_wg_id;
reg [WF_COUNT_WIDTH-1: 0] anded_cam_wf_count;
reg [VGPR_ID_WIDTH :0] anded_cam_vgpr_size;
reg [SGPR_ID_WIDTH :0] anded_cam_sgpr_size;
reg [LDS_ID_WIDTH :0] anded_cam_lds_size;
reg [GDS_ID_WIDTH :0] anded_cam_gds_size;
reg [GDS_ID_WIDTH-1 :0] anded_cam_gds_strt;
// Output encoder and find if we can use any cu, also addr the res start ram
reg encoded_cu_out_valid,
encoded_cu_found_valid, encoded_cu_found_valid_comb;
reg [CU_ID_WIDTH-1:0] encoded_cu_id, encoded_cu_id_comb;
reg [WG_ID_WIDTH-1 :0] encoded_cu_wg_id;
reg [WF_COUNT_WIDTH-1: 0] encoded_wf_count;
reg [VGPR_ID_WIDTH :0] encoded_vgpr_size;
reg [SGPR_ID_WIDTH :0] encoded_sgpr_size;
reg [LDS_ID_WIDTH :0] encoded_lds_size;
reg [GDS_ID_WIDTH :0] encoded_gds_size;
reg [GDS_ID_WIDTH-1 :0] encoded_gds_strt;
// res size ram lookup
reg size_ram_valid, size_ram_cu_id_found;
reg [CU_ID_WIDTH-1:0] cu_id_out;
reg [VGPR_ID_WIDTH-1:0] vgpr_start_out;
reg [SGPR_ID_WIDTH-1:0] sgpr_start_out;
reg [LDS_ID_WIDTH-1:0] lds_start_out;
reg [GDS_ID_WIDTH-1:0] gds_start_out;
reg [WG_ID_WIDTH-1 :0] wg_id_out;
reg [VGPR_ID_WIDTH :0] vgpr_size_out;
reg [SGPR_ID_WIDTH :0] sgpr_size_out;
reg [LDS_ID_WIDTH :0] lds_size_out;
reg [GDS_ID_WIDTH :0] gds_size_out;
reg [WF_COUNT_WIDTH-1: 0] wf_count_out;
localparam RAM_SIZE_WIDTH
= VGPR_ID_WIDTH + SGPR_ID_WIDTH + LDS_ID_WIDTH +GDS_ID_WIDTH;
localparam RES_SIZE_VGPR_START = 0;
localparam RES_SIZE_VGPR_END = RES_SIZE_VGPR_START+ VGPR_ID_WIDTH-1;
localparam RES_SIZE_SGPR_START = RES_SIZE_VGPR_END + 1;
localparam RES_SIZE_SGPR_END = RES_SIZE_SGPR_START+ SGPR_ID_WIDTH-1;
localparam RES_SIZE_LDS_START = RES_SIZE_SGPR_END + 1;
localparam RES_SIZE_LDS_END = RES_SIZE_LDS_START+ LDS_ID_WIDTH-1;
localparam RES_SIZE_GDS_START = RES_SIZE_LDS_END + 1;
localparam RES_SIZE_GDS_END = RES_SIZE_GDS_START+ GDS_ID_WIDTH-1;
wire [RAM_SIZE_WIDTH-1 :0] res_size_rd_wire, res_size_wr_wire;
reg [GDS_ID_WIDTH:0] gds_free;
reg [GDS_ID_WIDTH-1:0] gds_strt;
reg [NUMBER_CU-1:0] cu_initialized;
reg pipeline_waiting;
// Instantiate cams
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(VGPR_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_VGPR_SLOTS))
vgpr_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_vgpr_size_i),
// Search port out
.res_search_out(vgpr_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_vgpr_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(SGPR_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_SGPR_SLOTS))
sgpr_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_sgpr_size_i),
// Search port out
.res_search_out(sgpr_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_sgpr_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(LDS_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_LDS_SLOTS))
lds_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size(alloc_lds_size_i),
// Search port out
.res_search_out(lds_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_lds_size_i));
cam_allocator
#(.CU_ID_WIDTH(CU_ID_WIDTH),
.NUMBER_CU(NUMBER_CU),
.RES_ID_WIDTH(WG_SLOT_ID_WIDTH),
.NUMBER_RES_SLOTS(NUMBER_WF_SLOTS))
wf_cam
(.clk(clk),
.rst(rst),
// Search port in
.res_search_en(alloc_valid_i),
.res_search_size({{(WG_SLOT_ID_WIDTH+1-(WF_COUNT_WIDTH)){1'b0}},
alloc_num_wf_i}),
// Search port out
.res_search_out(wg_search_out),
// Update port
.cam_wr_en(cam_up_valid_i),
.cam_wr_addr(cam_up_cu_id_i),
.cam_wr_data(cam_up_wg_count_i));
ram_2_port
#(.WORD_SIZE(RAM_SIZE_WIDTH),
.ADDR_SIZE(CU_ID_WIDTH),
.NUM_WORDS(NUMBER_CU))
res_start_cam
(// Outputs
.rd_word (res_size_rd_wire),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (cam_up_valid_i),
.wr_addr (cam_up_cu_id_i),
.wr_word (res_size_wr_wire),
.rd_en (encoded_cu_out_valid &&
encoded_cu_found_valid),
.rd_addr (encoded_cu_id));
assign res_size_wr_wire = { cam_up_lds_strt_i,
cam_up_sgpr_strt_i, cam_up_vgpr_strt_i };
always @(posedge clk or rst) begin
if(rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
alloc_gds_size_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
alloc_lds_size_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
alloc_num_wf_i <= {WF_COUNT_WIDTH{1'b0}};
alloc_sgpr_size_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
alloc_valid_i <= 1'h0;
alloc_vgpr_size_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
alloc_wg_id_i <= {WG_ID_WIDTH{1'b0}};
anded_cam_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
anded_cam_gds_strt <= {GDS_ID_WIDTH{1'b0}};
anded_cam_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
anded_cam_out <= {NUMBER_CU{1'b0}};
anded_cam_out_valid <= 1'h0;
anded_cam_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
anded_cam_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
anded_cam_wf_count <= {WF_COUNT_WIDTH{1'b0}};
anded_cam_wg_id <= {WG_ID_WIDTH{1'b0}};
cam_up_cu_id_i <= {CU_ID_WIDTH{1'b0}};
cam_up_gds_size_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
cam_up_gds_strt_i <= {GDS_ID_WIDTH{1'b0}};
cam_up_lds_size_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
cam_up_lds_strt_i <= {LDS_ID_WIDTH{1'b0}};
cam_up_sgpr_size_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
cam_up_sgpr_strt_i <= {SGPR_ID_WIDTH{1'b0}};
cam_up_valid_i <= 1'h0;
cam_up_vgpr_size_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
cam_up_vgpr_strt_i <= {VGPR_ID_WIDTH{1'b0}};
cam_up_wg_count_i <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
cam_wait_dis_controller_cu_busy <= {NUMBER_CU{1'b0}};
cam_wait_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
cam_wait_gds_strt <= {GDS_ID_WIDTH{1'b0}};
cam_wait_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
cam_wait_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
cam_wait_valid <= 1'h0;
cam_wait_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
cam_wait_wf_count <= {WF_COUNT_WIDTH{1'b0}};
cam_wait_wg_id <= {WG_ID_WIDTH{1'b0}};
cu_id_out <= {CU_ID_WIDTH{1'b0}};
cu_initialized <= {NUMBER_CU{1'b0}};
dis_controller_cu_busy_i <= {NUMBER_CU{1'b0}};
encoded_cu_found_valid <= 1'h0;
encoded_cu_id <= {CU_ID_WIDTH{1'b0}};
encoded_cu_out_valid <= 1'h0;
encoded_cu_wg_id <= {WG_ID_WIDTH{1'b0}};
encoded_gds_size <= {(1+(GDS_ID_WIDTH)){1'b0}};
encoded_gds_strt <= {GDS_ID_WIDTH{1'b0}};
encoded_lds_size <= {(1+(LDS_ID_WIDTH)){1'b0}};
encoded_sgpr_size <= {(1+(SGPR_ID_WIDTH)){1'b0}};
encoded_vgpr_size <= {(1+(VGPR_ID_WIDTH)){1'b0}};
encoded_wf_count <= {WF_COUNT_WIDTH{1'b0}};
gds_free <= {(1+(GDS_ID_WIDTH)){1'b0}};
gds_size_out <= {(1+(GDS_ID_WIDTH)){1'b0}};
gds_start_out <= {GDS_ID_WIDTH{1'b0}};
gds_strt <= {GDS_ID_WIDTH{1'b0}};
gds_valid <= 1'h0;
lds_size_out <= {(1+(LDS_ID_WIDTH)){1'b0}};
pipeline_waiting <= 1'h0;
sgpr_size_out <= {(1+(SGPR_ID_WIDTH)){1'b0}};
size_ram_cu_id_found <= 1'h0;
size_ram_valid <= 1'h0;
vgpr_size_out <= {(1+(VGPR_ID_WIDTH)){1'b0}};
wf_count_out <= {WF_COUNT_WIDTH{1'b0}};
wg_id_out <= {WG_ID_WIDTH{1'b0}};
// End of automatics
gds_free <= GDS_SIZE;
end
else begin // if (rst)
// Locks the pipeline until an ack arrive from the controller
if(encoded_cu_out_valid && !pipeline_waiting) begin
pipeline_waiting <= 1'b1;
end
if(dis_controller_alloc_ack) begin
pipeline_waiting <= 1'b0;
end
if(!pipeline_waiting) begin
//////////////////////////////////
// Cam search pipeline
//////////////////////////////////
alloc_valid_i <= dis_controller_start_alloc;
alloc_wg_id_i <= inflight_wg_buffer_alloc_wg_id;
alloc_num_wf_i <= inflight_wg_buffer_alloc_num_wf;
alloc_vgpr_size_i <= inflight_wg_buffer_alloc_vgpr_size;
alloc_sgpr_size_i <= inflight_wg_buffer_alloc_sgpr_size;
alloc_lds_size_i <= inflight_wg_buffer_alloc_lds_size;
alloc_gds_size_i <= inflight_wg_buffer_alloc_gds_size;
dis_controller_cu_busy_i <= dis_controller_cu_busy;
// Wait for cam search
cam_wait_valid <= alloc_valid_i;
cam_wait_wg_id <= alloc_wg_id_i;
cam_wait_wf_count <= alloc_num_wf_i;
cam_wait_vgpr_size <= alloc_vgpr_size_i;
cam_wait_sgpr_size <= alloc_sgpr_size_i;
cam_wait_lds_size <= alloc_lds_size_i;
cam_wait_gds_size <= alloc_gds_size_i;
cam_wait_gds_strt <= gds_strt;
cam_wait_dis_controller_cu_busy <= dis_controller_cu_busy_i;
if(gds_free >= alloc_gds_size_i)
gds_valid <= 1'b1;
else
gds_valid <= 1'b0;
// AND all cam outs
anded_cam_out_valid <= cam_wait_valid;
anded_cam_out <= vgpr_search_out & sgpr_search_out & lds_search_out &
wg_search_out & {NUMBER_CU{gds_valid}} &
(~cam_wait_dis_controller_cu_busy);
anded_cam_wg_id <= cam_wait_wg_id;
anded_cam_wf_count <= cam_wait_wf_count;
anded_cam_vgpr_size <= cam_wait_vgpr_size;
anded_cam_sgpr_size <= cam_wait_sgpr_size;
anded_cam_lds_size <= cam_wait_lds_size;
anded_cam_gds_size <= cam_wait_gds_size;
anded_cam_gds_strt <= cam_wait_gds_strt;
// Use the encoded output to find the start of the resources
encoded_cu_out_valid <= anded_cam_out_valid;
encoded_cu_found_valid <= encoded_cu_found_valid_comb;
encoded_cu_id <= encoded_cu_id_comb;
encoded_wf_count <= anded_cam_wf_count;
encoded_cu_wg_id <= anded_cam_wg_id;
encoded_vgpr_size <= anded_cam_vgpr_size;
encoded_sgpr_size <= anded_cam_sgpr_size;
encoded_lds_size <= anded_cam_lds_size;
encoded_gds_size <= anded_cam_gds_size;
encoded_gds_strt <= anded_cam_gds_strt;
// Output the starts and the cu id
size_ram_valid <= encoded_cu_out_valid;
size_ram_cu_id_found <= encoded_cu_found_valid;
cu_id_out <= encoded_cu_id;
wg_id_out <= encoded_cu_wg_id;
wf_count_out <= encoded_wf_count;
vgpr_size_out <= encoded_vgpr_size;
sgpr_size_out <= encoded_sgpr_size;
lds_size_out <= encoded_lds_size;
gds_size_out <= encoded_gds_size;
gds_start_out <= encoded_gds_strt;
end // if (pipeline_waiting)
//////////////////////////////////
// Cam write
//////////////////////////////////
cam_up_valid_i <= grt_cam_up_valid;
cam_up_cu_id_i <= grt_cam_up_cu_id;
cam_up_vgpr_strt_i <= grt_cam_up_vgpr_strt;
cam_up_sgpr_strt_i <= grt_cam_up_sgpr_strt;
cam_up_lds_strt_i <= grt_cam_up_lds_strt;
cam_up_gds_strt_i <= grt_cam_up_gds_strt;
cam_up_wg_count_i <= grt_cam_up_wg_count;
if(cam_up_valid_i) begin
cu_initialized[cam_up_cu_id_i] <= 1'b1;
end
//////////////////////////////////
// Size ram write
//////////////////////////////////
cam_up_vgpr_size_i <= grt_cam_up_vgpr_size;
cam_up_sgpr_size_i <= grt_cam_up_sgpr_size;
cam_up_lds_size_i <= grt_cam_up_lds_size;
cam_up_gds_size_i <= grt_cam_up_gds_size;
if(cam_up_valid_i) begin
gds_free <= cam_up_gds_size_i;
gds_strt <= cam_up_gds_strt_i;
end
else if(alloc_valid_i && (gds_free >= alloc_gds_size_i) && !pipeline_waiting) begin
gds_free <= gds_free - alloc_gds_size_i;
gds_strt <= gds_strt + alloc_gds_size_i;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
assign allocator_cu_valid = size_ram_valid;
assign allocator_cu_rejected = ~size_ram_cu_id_found;
assign allocator_wg_id_out = wg_id_out;
assign allocator_cu_id_out = cu_id_out;
assign allocator_vgpr_size_out = vgpr_size_out;
assign allocator_sgpr_size_out = sgpr_size_out;
assign allocator_lds_size_out = lds_size_out;
assign allocator_gds_size_out = gds_size_out;
assign allocator_vgpr_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_VGPR_END:RES_SIZE_VGPR_START];
assign allocator_sgpr_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_SGPR_END:RES_SIZE_SGPR_START];
assign allocator_lds_start_out = (!cu_initialized[cu_id_out])? 0 :
res_size_rd_wire[RES_SIZE_LDS_END:RES_SIZE_LDS_START];
assign allocator_gds_start_out = (!cu_initialized[cu_id_out])? 0 :
gds_start_out;
assign allocator_wf_count = wf_count_out;
always @ ( /*AUTOSENSE*/anded_cam_out) begin : PRI_ENCODER_CAM_OUT
integer i;
reg found_valid;
found_valid = 1'b0;
encoded_cu_id_comb = 0;
for (i=0; i<NUMBER_CU; i = i+1) begin
if(~found_valid && anded_cam_out[i]) begin
found_valid = 1'b1;
encoded_cu_id_comb = i;
end
end
encoded_cu_found_valid_comb = found_valid;
end
endmodule // allocator
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Set Implicit Arguments.
Require Export Notations.
Notation "A -> B" := (forall (_ : A), B) : type_scope.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
Arguments or_introl [A B] _, [A] B _.
Arguments or_intror [A B] _, A [B] _.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ assumption | ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ | assumption ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left; assumption| right]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left| right; assumption]);
[apply Hl | apply Hr]; assumption.
Qed.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
- intro H; split; [exact H | intro H1; elim H1].
- intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_l]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [apply Hl | ]; assumption.
+ apply HypR; split; [apply Hr | ]; assumption.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_r]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [ | apply Hl ]; assumption.
+ apply HypR; split; [ | apply Hr ]; assumption.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; split; intros [? ?]; split; assumption.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; split; [ intros [[? ?] ?]| intros [? [? ?]]]; repeat split; assumption.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_l]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ right | destruct Fl | ]; assumption. }
{ destruct Hr; [ right | destruct Fr | ]; assumption. }
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_r]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ left | | destruct Fl ]; assumption. }
{ destruct Hr; [ left | | destruct Fr ]; assumption. }
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; split; (intros [? | ?]; [ right | left ]; assumption).
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; split; [ intros [[?|?]|?]| intros [?|[?|?]]].
+ left; assumption.
+ right; left; assumption.
+ right; right; assumption.
+ left; left; assumption.
+ left; right; assumption.
+ right; assumption.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; split; intros [Hl Hr]; (split; intros; [ apply Hl | apply Hr]); assumption.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [Q] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x .. y , p" := (ex (fun x => .. (ex (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'exists' '/ ' x .. y , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : t , p & q" := (ex2 (fun x:t => p) (fun x:t => q))
(at level 200, x ident, t at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : t , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Arguments eq {A} x _.
Arguments eq_refl {A x} , [A] x.
Arguments eq_ind [A] x P _ y _.
Arguments eq_rec [A] x P _ y _.
Arguments eq_rect [A] x P _ y _.
Hint Resolve I conj or_introl or_intror : core.
Hint Resolve eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0. elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Module EqNotations.
Notation "'rew' H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' H in '/' H' ']'").
Notation "'rew' [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' <- H 'in' H'" := (eq_rect_r _ H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- H in '/' H' ']'").
Notation "'rew' <- [ P ] H 'in' H'" := (eq_rect_r P H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' -> H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10, only parsing).
Notation "'rew' -> [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10, only parsing).
End EqNotations.
Import EqNotations.
Lemma rew_opp_r : forall A (P:A->Type) (x y:A) (H:x=y) (a:P y), rew H in rew <- H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Lemma rew_opp_l : forall A (P:A->Type) (x y:A) (H:x=y) (a:P x), rew <- H in rew H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal_compose : forall A B C (a b:A) (f:A->B) (g:B->C) (e:a=b),
f_equal g (f_equal f e) = f_equal (fun a => g (f a)) e.
Proof.
destruct e. reflexivity.
Defined.
(** The goupoid structure of equality *)
Theorem eq_trans_refl_l : forall A (x y:A) (e:x=y), eq_trans eq_refl e = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_trans_refl_r : forall A (x y:A) (e:x=y), eq_trans e eq_refl = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_sym_involutive : forall A (x y:A) (e:x=y), eq_sym (eq_sym e) = e.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_l : forall A (x y:A) (e:x=y), eq_trans (eq_sym e) e = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_r : forall A (x y:A) (e:x=y), eq_trans e (eq_sym e) = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_assoc : forall A (x y z t:A) (e:x=y) (e':y=z) (e'':z=t),
eq_trans e (eq_trans e' e'') = eq_trans (eq_trans e e') e''.
Proof.
destruct e''; reflexivity.
Defined.
(** Extra properties of equality *)
Theorem eq_id_comm_l : forall A (f:A->A) (Hf:forall a, a = f a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf a)).
destruct (Hf a) at 1 2.
destruct (Hf a).
reflexivity.
Defined.
Theorem eq_id_comm_r : forall A (f:A->A) (Hf:forall a, f a = a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf (f (f a)))).
set (Hfsymf := fun a => eq_sym (Hf a)).
change (eq_sym (Hf (f (f a)))) with (Hfsymf (f (f a))).
pattern (Hfsymf (f (f a))).
destruct (eq_id_comm_l f Hfsymf (f a)).
destruct (eq_id_comm_l f Hfsymf a).
unfold Hfsymf.
destruct (Hf a). simpl.
rewrite eq_trans_refl_l.
reflexivity.
Defined.
Lemma eq_trans_map_distr : forall A B x y z (f:A->B) (e:x=y) (e':y=z), f_equal f (eq_trans e e') = eq_trans (f_equal f e) (f_equal f e').
Proof.
destruct e'.
reflexivity.
Defined.
Lemma eq_sym_map_distr : forall A B (x y:A) (f:A->B) (e:x=y), eq_sym (f_equal f e) = f_equal f (eq_sym e).
Proof.
destruct e.
reflexivity.
Defined.
Lemma eq_trans_sym_distr : forall A (x y z:A) (e:x=y) (e':y=z), eq_sym (eq_trans e e') = eq_trans (eq_sym e') (eq_sym e).
Proof.
destruct e, e'.
reflexivity.
Defined.
(* Aliases *)
Notation sym_eq := eq_sym (compat "8.3").
Notation trans_eq := eq_trans (compat "8.3").
Notation sym_not_eq := not_eq_sym (compat "8.3").
Notation refl_equal := eq_refl (compat "8.3").
Notation sym_equal := eq_sym (compat "8.3").
Notation trans_equal := eq_trans (compat "8.3").
Notation sym_not_equal := not_eq_sym (compat "8.3").
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x .. y , p" :=
(ex (unique (fun x => .. (ex (unique (fun y => p))) ..)))
(at level 200, x binder, right associativity,
format "'[' 'exists' ! '/ ' x .. y , '/ ' p ']'")
: type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
- intros ((x,Hx),Huni); exists x; red; auto.
- intros (x,(Hx,Huni)); split.
+ exists x; assumption.
+ intros x' x'' Hx' Hx''; transitivity x.
symmetry; auto.
auto.
Qed.
Lemma forall_exists_unique_domain_coincide :
forall A (P:A->Prop), (exists! x, P x) ->
forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x).
Proof.
intros A P (x & Hp & Huniq); split.
- intro; exists x; auto.
- intros (x0 & HPx0 & HQx0) x1 HPx1.
replace x1 with x0 by (transitivity x; [symmetry|]; auto).
assumption.
Qed.
Lemma forall_exists_coincide_unique_domain :
forall A (P:A->Prop),
(forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x))
-> (exists! x, P x).
Proof.
intros A P H.
destruct H with (Q:=P) as ((x & Hx & _),_); [trivial|].
exists x. split; [trivial|].
destruct H with (Q:=fun x'=>x=x') as (_,Huniq).
apply Huniq. exists x; auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros ? ? ? [? ?] [? ?]; split; intros; auto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 25.06.2017 19:20:37
// Design Name:
// Module Name: conversor_num_16b
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module conversor_num_16b(
input [19:0] numeros,
output [15:0] operador
);
localparam exp4= 16'd10000;
localparam exp3= 16'd1000;
localparam exp2= 16'd100;
localparam exp1= 16'd10;
localparam exp0= 16'd1;
wire [15:0] num_exp4,num_exp3,num_exp2,num_exp1,num_exp0;
assign num_exp4={12'b0,numeros[19:16]}*exp4;
assign num_exp3={12'b0,numeros[15:12]}*exp3;
assign num_exp2={12'b0,numeros[11:8]}*exp2;
assign num_exp1={12'b0,numeros[7:4]}*exp1;
assign num_exp0={12'b0,numeros[3:0]}*exp0;
assign operador=num_exp0+num_exp1+num_exp2+num_exp3+num_exp4;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module fifo_xlnx_2Kx36_2clk(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
rd_data_count,
wr_data_count);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
output [11 : 0] rd_data_count;
output [11 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V4_3 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(12),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("2kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(2047),
.C_PROG_FULL_THRESH_NEGATE_VAL(2046),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(12),
.C_RD_DEPTH(2048),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(11),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(12),
.C_WR_DEPTH(2048),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(11),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.UNDERFLOW(),
.WR_ACK(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box"
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user interface. The MC user interface has bidirectional
// data path and supports data width of 256/128/64/32 bits.
// The bridge is designed to allow AXI4 IP masters to communicate with
// the MC user interface.
//
//
// Specifications:
// AXI4 Slave Side:
// Configurable data width of 32, 64, 128, 256
// Read acceptance depth is:
// Write acceptance depth is:
//
// Structure:
// axi_protocol_converter_v2_1_b2s
// WRITE_BUNDLE
// aw_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// w_channel_0
// b_channel_0
// READ_BUNDLE
// ar_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// r_channel_0
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule
`default_nettype wire
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_2_V
`define SKY130_FD_SC_MS__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #(PAR) m1();
m3 #(PAR) m3();
mnooverride #(10) mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #(PAR1MINUS1) m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
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