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142,498 | data/full_repos/permissive/99182535/bjx1c32b/ModFbTxtW.v | 99,182,535 | ModFbTxtW.v | v | 299 | 66 | [] | [] | [] | [(25, 298)] | null | data/verilator_xmls/72b1fc26-5cbb-45aa-af11-8557a65ec8e3.xml | null | 314,670 | module | module ModFbTxtW(clock, reset,
pixPosX, pixPosY, pixCy, pixCu, pixCv,
pixCellIx, cellData,
fontGlyph, fontData);
input clock;
input reset;
input[9:0] pixPosX;
input[9:0] pixPosY;
output[7:0] pixCy;
output[7:0] pixCu;
output[7:0] pixCv;
output[13:0] pixCellIx;
input[127:0] cellData;
output[15:0] fontGlyph;
input[63:0] fontData;
reg[9:0] tPixPosX;
reg[9:0] tPixPosY;
reg[13:0] tPixCellX;
reg[13:0] tPixCellY;
reg[13:0] tPixCellIx;
reg[3:0] tPixCellFx;
reg[13:0] tPixCellNextIx;
reg[3:0] tPixCellNextFx;
reg[5:0] tPixCellNextGx;
reg[127:0] tCellData;
reg[15:0] tFontGlyph;
reg[63:0] tFontData;
reg[15:0] tFontGlyphU;
reg[15:0] tFontGlyphV;
reg[5:0] tClrA;
reg[5:0] tClrB;
reg[8:0] tClr9A;
reg[8:0] tClr9B;
reg[11:0] tClrRgbA;
reg[11:0] tClrRgbB;
reg[11:0] tClrYuvA;
reg[11:0] tClrYuvB;
reg[11:0] tClrYuvC;
reg[7:0] tPixCy;
reg[7:0] tPixCu;
reg[7:0] tPixCv;
reg[11:0] cbClrTab[63:0];
reg useCol80;
assign pixCellIx = tPixCellIx;
assign fontGlyph = tFontGlyph;
assign pixCy = tPixCy;
assign pixCu = tPixCu;
assign pixCv = tPixCv;
initial
begin
cbClrTab[ 0]=12'h088; cbClrTab[ 1]=12'h1A8;
cbClrTab[ 2]=12'h2D8; cbClrTab[ 3]=12'h3F8;
cbClrTab[ 4]=12'h255; cbClrTab[ 5]=12'h385;
cbClrTab[ 6]=12'h5A5; cbClrTab[ 7]=12'h6D5;
cbClrTab[ 8]=12'h522; cbClrTab[ 9]=12'h652;
cbClrTab[10]=12'h782; cbClrTab[11]=12'h9A2;
cbClrTab[12]=12'h700; cbClrTab[13]=12'h920;
cbClrTab[14]=12'hA50; cbClrTab[15]=12'hB80;
cbClrTab[16]=12'h18A; cbClrTab[17]=12'h2AA;
cbClrTab[18]=12'h3DA; cbClrTab[19]=12'h5FA;
cbClrTab[20]=12'h358; cbClrTab[21]=12'h588;
cbClrTab[22]=12'h6A8; cbClrTab[23]=12'h7D8;
cbClrTab[24]=12'h625; cbClrTab[25]=12'h755;
cbClrTab[26]=12'h985; cbClrTab[27]=12'hAA5;
cbClrTab[28]=12'h902; cbClrTab[29]=12'hA22;
cbClrTab[30]=12'hB52; cbClrTab[31]=12'hD82;
cbClrTab[32]=12'h28D; cbClrTab[33]=12'h3AD;
cbClrTab[34]=12'h5DD; cbClrTab[35]=12'h6FD;
cbClrTab[36]=12'h55A; cbClrTab[37]=12'h68A;
cbClrTab[38]=12'h7AA; cbClrTab[39]=12'h9DA;
cbClrTab[40]=12'h728; cbClrTab[41]=12'h958;
cbClrTab[42]=12'hA88; cbClrTab[43]=12'hBA8;
cbClrTab[44]=12'hA05; cbClrTab[45]=12'hB25;
cbClrTab[46]=12'hD55; cbClrTab[47]=12'hE85;
cbClrTab[48]=12'h38F; cbClrTab[49]=12'h5AF;
cbClrTab[50]=12'h6DF; cbClrTab[51]=12'h7FF;
cbClrTab[52]=12'h65D; cbClrTab[53]=12'h78D;
cbClrTab[54]=12'h9AD; cbClrTab[55]=12'hADD;
cbClrTab[56]=12'h92A; cbClrTab[57]=12'hA5A;
cbClrTab[58]=12'hB8A; cbClrTab[59]=12'hDAA;
cbClrTab[60]=12'hB08; cbClrTab[61]=12'hD28;
cbClrTab[62]=12'hE58; cbClrTab[63]=12'hF88;
end
always @*
begin
tPixCellX = 0;
tPixCellY = 0;
useCol80 = 0;
tClrYuvC = 0;
if(useCol80)
begin
tPixCellX[6:0] = tPixPosX[9:3];
tPixCellY[6:0] = tPixPosY[9:3];
tPixCellNextIx = tPixCellY*80 + tPixCellX - 160;
tPixCellNextFx[1:0] = 2'h2 - tPixPosX[2:1];
tPixCellNextFx[3:2] = 2'h2 - tPixPosY[2:1];
tPixCellNextGx[2:0] = 3'h7 - tPixPosX[2:0];
tPixCellNextGx[5:3] = 3'h7 - tPixPosY[2:0];
end
else
begin
tPixCellX[5:0] = tPixPosX[9:4];
tPixCellY[6:0] = tPixPosY[9:3];
tPixCellNextIx = tPixCellY*40 + tPixCellX - 80;
tPixCellNextFx[1:0] = 2'h3 - tPixPosX[3:2];
tPixCellNextFx[3:2] = 2'h3 - tPixPosY[2:1];
tPixCellNextGx[2:0] = 3'h7 - tPixPosX[3:1];
tPixCellNextGx[5:3] = 3'h7 - tPixPosY[2:0];
end
tCellData = cellData;
if(tPixCellIx >= 2000)
tCellData = 0;
if(!useCol80 && (tPixCellIx>=1000))
tCellData = 0;
tFontGlyph = tCellData[15:0];
tClrA = tCellData[21:16];
tClrB = tCellData[27:22];
tClr9A = tCellData[18:10];
tClr9B = tCellData[27:19];
tClrRgbA = 0;
tClrRgbB = 0;
case(tCellData[29:28])
2'b00: begin
tClrRgbA[11:10]=tClrA[5:4];
tClrRgbA[ 9: 8]=tClrA[5:4];
tClrRgbA[ 7: 6]=tClrA[3:2];
tClrRgbA[ 5: 4]=tClrA[3:2];
tClrRgbA[ 3: 2]=tClrA[1:0];
tClrRgbA[ 1: 0]=tClrA[1:0];
tClrRgbB[11:10]=tClrB[5:4];
tClrRgbB[ 9: 8]=tClrB[5:4];
tClrRgbB[ 7: 6]=tClrB[3:2];
tClrRgbB[ 5: 4]=tClrB[3:2];
tClrRgbB[ 3: 2]=tClrB[1:0];
tClrRgbB[ 1: 0]=tClrB[1:0];
end
2'b10: begin
tClrRgbA[11: 9]=tClr9A[8:6];
tClrRgbA[ 7: 5]=tClr9A[5:3];
tClrRgbA[ 3: 1]=tClr9A[2:0];
tClrRgbB[11: 9]=tClr9B[8:6];
tClrRgbB[ 7: 5]=tClr9B[5:3];
tClrRgbB[ 3: 1]=tClr9B[2:0];
end
default: begin end
endcase
tClrYuvA[11:8]=
{1'b0, tClrRgbA[ 7: 5]}+
{2'b0, tClrRgbA[11:10]}+
{2'b0, tClrRgbA[ 3: 2]};
tClrYuvB[11:8]=
{1'b0, tClrRgbB[ 7: 5]}+
{2'b0, tClrRgbB[11:10]}+
{2'b0, tClrRgbB[ 3: 2]};
tClrYuvA[7:4]=4'h8+(tClrRgbA[ 3: 1]-tClrRgbA[ 7: 5]);
tClrYuvB[7:4]=4'h8+(tClrRgbB[ 3: 1]-tClrRgbB[ 7: 5]);
tClrYuvA[3:0]=4'h8+(tClrRgbA[11: 9]-tClrRgbA[ 7: 5]);
tClrYuvB[3:0]=4'h8+(tClrRgbB[11: 9]-tClrRgbB[ 7: 5]);
tFontData = fontData;
if(tCellData[31:30]==2'b10)
begin
tFontData = tCellData[127:64];
tClrYuvB[11:8]=tCellData[27:24];
tClrYuvA[11:8]=tCellData[21:18];
tClrYuvB[ 7:4]=tCellData[15:12];
tClrYuvA[ 7:4]=tCellData[11: 8];
tClrYuvB[ 3:0]=tCellData[ 7: 4];
tClrYuvA[ 3:0]=tCellData[ 3: 0];
tFontGlyphU = tCellData[63:48];
tFontGlyphV = tCellData[47:32];
tClrYuvC[11:8] = (tFontData[tPixCellNextGx]) ?
tClrYuvA[11:8] : tClrYuvB[11:8];
tClrYuvC[7:4] = (tFontGlyphU[tPixCellNextFx]) ?
tClrYuvA[7:4] : tClrYuvB[7:4];
tClrYuvC[3:0] = (tFontGlyphV[tPixCellNextFx]) ?
tClrYuvA[3:0] : tClrYuvB[3:0];
end
else
begin
if(cellData[31:30]==2'b00)
tClrYuvC = (tFontData[tPixCellNextGx]) ? tClrYuvA : tClrYuvB;
else if(cellData[31:30]==2'b01)
tClrYuvC = (tFontGlyph[tPixCellNextFx]) ? tClrYuvA : tClrYuvB;
end
tPixCy[7:4] = tClrYuvC[11:8]; tPixCy[3:0] = tClrYuvC[11:8];
tPixCu[7:4] = tClrYuvC[7:4]; tPixCu[3:0] = tClrYuvC[7:4];
tPixCv[7:4] = tClrYuvC[3:0]; tPixCv[3:0] = tClrYuvC[3:0];
end
always @ (posedge clock)
begin
tPixPosX <= pixPosX;
tPixPosY <= pixPosY;
tPixCellIx <= tPixCellNextIx;
tPixCellFx <= tPixCellNextFx;
end
endmodule | module ModFbTxtW(clock, reset,
pixPosX, pixPosY, pixCy, pixCu, pixCv,
pixCellIx, cellData,
fontGlyph, fontData); |
input clock;
input reset;
input[9:0] pixPosX;
input[9:0] pixPosY;
output[7:0] pixCy;
output[7:0] pixCu;
output[7:0] pixCv;
output[13:0] pixCellIx;
input[127:0] cellData;
output[15:0] fontGlyph;
input[63:0] fontData;
reg[9:0] tPixPosX;
reg[9:0] tPixPosY;
reg[13:0] tPixCellX;
reg[13:0] tPixCellY;
reg[13:0] tPixCellIx;
reg[3:0] tPixCellFx;
reg[13:0] tPixCellNextIx;
reg[3:0] tPixCellNextFx;
reg[5:0] tPixCellNextGx;
reg[127:0] tCellData;
reg[15:0] tFontGlyph;
reg[63:0] tFontData;
reg[15:0] tFontGlyphU;
reg[15:0] tFontGlyphV;
reg[5:0] tClrA;
reg[5:0] tClrB;
reg[8:0] tClr9A;
reg[8:0] tClr9B;
reg[11:0] tClrRgbA;
reg[11:0] tClrRgbB;
reg[11:0] tClrYuvA;
reg[11:0] tClrYuvB;
reg[11:0] tClrYuvC;
reg[7:0] tPixCy;
reg[7:0] tPixCu;
reg[7:0] tPixCv;
reg[11:0] cbClrTab[63:0];
reg useCol80;
assign pixCellIx = tPixCellIx;
assign fontGlyph = tFontGlyph;
assign pixCy = tPixCy;
assign pixCu = tPixCu;
assign pixCv = tPixCv;
initial
begin
cbClrTab[ 0]=12'h088; cbClrTab[ 1]=12'h1A8;
cbClrTab[ 2]=12'h2D8; cbClrTab[ 3]=12'h3F8;
cbClrTab[ 4]=12'h255; cbClrTab[ 5]=12'h385;
cbClrTab[ 6]=12'h5A5; cbClrTab[ 7]=12'h6D5;
cbClrTab[ 8]=12'h522; cbClrTab[ 9]=12'h652;
cbClrTab[10]=12'h782; cbClrTab[11]=12'h9A2;
cbClrTab[12]=12'h700; cbClrTab[13]=12'h920;
cbClrTab[14]=12'hA50; cbClrTab[15]=12'hB80;
cbClrTab[16]=12'h18A; cbClrTab[17]=12'h2AA;
cbClrTab[18]=12'h3DA; cbClrTab[19]=12'h5FA;
cbClrTab[20]=12'h358; cbClrTab[21]=12'h588;
cbClrTab[22]=12'h6A8; cbClrTab[23]=12'h7D8;
cbClrTab[24]=12'h625; cbClrTab[25]=12'h755;
cbClrTab[26]=12'h985; cbClrTab[27]=12'hAA5;
cbClrTab[28]=12'h902; cbClrTab[29]=12'hA22;
cbClrTab[30]=12'hB52; cbClrTab[31]=12'hD82;
cbClrTab[32]=12'h28D; cbClrTab[33]=12'h3AD;
cbClrTab[34]=12'h5DD; cbClrTab[35]=12'h6FD;
cbClrTab[36]=12'h55A; cbClrTab[37]=12'h68A;
cbClrTab[38]=12'h7AA; cbClrTab[39]=12'h9DA;
cbClrTab[40]=12'h728; cbClrTab[41]=12'h958;
cbClrTab[42]=12'hA88; cbClrTab[43]=12'hBA8;
cbClrTab[44]=12'hA05; cbClrTab[45]=12'hB25;
cbClrTab[46]=12'hD55; cbClrTab[47]=12'hE85;
cbClrTab[48]=12'h38F; cbClrTab[49]=12'h5AF;
cbClrTab[50]=12'h6DF; cbClrTab[51]=12'h7FF;
cbClrTab[52]=12'h65D; cbClrTab[53]=12'h78D;
cbClrTab[54]=12'h9AD; cbClrTab[55]=12'hADD;
cbClrTab[56]=12'h92A; cbClrTab[57]=12'hA5A;
cbClrTab[58]=12'hB8A; cbClrTab[59]=12'hDAA;
cbClrTab[60]=12'hB08; cbClrTab[61]=12'hD28;
cbClrTab[62]=12'hE58; cbClrTab[63]=12'hF88;
end
always @*
begin
tPixCellX = 0;
tPixCellY = 0;
useCol80 = 0;
tClrYuvC = 0;
if(useCol80)
begin
tPixCellX[6:0] = tPixPosX[9:3];
tPixCellY[6:0] = tPixPosY[9:3];
tPixCellNextIx = tPixCellY*80 + tPixCellX - 160;
tPixCellNextFx[1:0] = 2'h2 - tPixPosX[2:1];
tPixCellNextFx[3:2] = 2'h2 - tPixPosY[2:1];
tPixCellNextGx[2:0] = 3'h7 - tPixPosX[2:0];
tPixCellNextGx[5:3] = 3'h7 - tPixPosY[2:0];
end
else
begin
tPixCellX[5:0] = tPixPosX[9:4];
tPixCellY[6:0] = tPixPosY[9:3];
tPixCellNextIx = tPixCellY*40 + tPixCellX - 80;
tPixCellNextFx[1:0] = 2'h3 - tPixPosX[3:2];
tPixCellNextFx[3:2] = 2'h3 - tPixPosY[2:1];
tPixCellNextGx[2:0] = 3'h7 - tPixPosX[3:1];
tPixCellNextGx[5:3] = 3'h7 - tPixPosY[2:0];
end
tCellData = cellData;
if(tPixCellIx >= 2000)
tCellData = 0;
if(!useCol80 && (tPixCellIx>=1000))
tCellData = 0;
tFontGlyph = tCellData[15:0];
tClrA = tCellData[21:16];
tClrB = tCellData[27:22];
tClr9A = tCellData[18:10];
tClr9B = tCellData[27:19];
tClrRgbA = 0;
tClrRgbB = 0;
case(tCellData[29:28])
2'b00: begin
tClrRgbA[11:10]=tClrA[5:4];
tClrRgbA[ 9: 8]=tClrA[5:4];
tClrRgbA[ 7: 6]=tClrA[3:2];
tClrRgbA[ 5: 4]=tClrA[3:2];
tClrRgbA[ 3: 2]=tClrA[1:0];
tClrRgbA[ 1: 0]=tClrA[1:0];
tClrRgbB[11:10]=tClrB[5:4];
tClrRgbB[ 9: 8]=tClrB[5:4];
tClrRgbB[ 7: 6]=tClrB[3:2];
tClrRgbB[ 5: 4]=tClrB[3:2];
tClrRgbB[ 3: 2]=tClrB[1:0];
tClrRgbB[ 1: 0]=tClrB[1:0];
end
2'b10: begin
tClrRgbA[11: 9]=tClr9A[8:6];
tClrRgbA[ 7: 5]=tClr9A[5:3];
tClrRgbA[ 3: 1]=tClr9A[2:0];
tClrRgbB[11: 9]=tClr9B[8:6];
tClrRgbB[ 7: 5]=tClr9B[5:3];
tClrRgbB[ 3: 1]=tClr9B[2:0];
end
default: begin end
endcase
tClrYuvA[11:8]=
{1'b0, tClrRgbA[ 7: 5]}+
{2'b0, tClrRgbA[11:10]}+
{2'b0, tClrRgbA[ 3: 2]};
tClrYuvB[11:8]=
{1'b0, tClrRgbB[ 7: 5]}+
{2'b0, tClrRgbB[11:10]}+
{2'b0, tClrRgbB[ 3: 2]};
tClrYuvA[7:4]=4'h8+(tClrRgbA[ 3: 1]-tClrRgbA[ 7: 5]);
tClrYuvB[7:4]=4'h8+(tClrRgbB[ 3: 1]-tClrRgbB[ 7: 5]);
tClrYuvA[3:0]=4'h8+(tClrRgbA[11: 9]-tClrRgbA[ 7: 5]);
tClrYuvB[3:0]=4'h8+(tClrRgbB[11: 9]-tClrRgbB[ 7: 5]);
tFontData = fontData;
if(tCellData[31:30]==2'b10)
begin
tFontData = tCellData[127:64];
tClrYuvB[11:8]=tCellData[27:24];
tClrYuvA[11:8]=tCellData[21:18];
tClrYuvB[ 7:4]=tCellData[15:12];
tClrYuvA[ 7:4]=tCellData[11: 8];
tClrYuvB[ 3:0]=tCellData[ 7: 4];
tClrYuvA[ 3:0]=tCellData[ 3: 0];
tFontGlyphU = tCellData[63:48];
tFontGlyphV = tCellData[47:32];
tClrYuvC[11:8] = (tFontData[tPixCellNextGx]) ?
tClrYuvA[11:8] : tClrYuvB[11:8];
tClrYuvC[7:4] = (tFontGlyphU[tPixCellNextFx]) ?
tClrYuvA[7:4] : tClrYuvB[7:4];
tClrYuvC[3:0] = (tFontGlyphV[tPixCellNextFx]) ?
tClrYuvA[3:0] : tClrYuvB[3:0];
end
else
begin
if(cellData[31:30]==2'b00)
tClrYuvC = (tFontData[tPixCellNextGx]) ? tClrYuvA : tClrYuvB;
else if(cellData[31:30]==2'b01)
tClrYuvC = (tFontGlyph[tPixCellNextFx]) ? tClrYuvA : tClrYuvB;
end
tPixCy[7:4] = tClrYuvC[11:8]; tPixCy[3:0] = tClrYuvC[11:8];
tPixCu[7:4] = tClrYuvC[7:4]; tPixCu[3:0] = tClrYuvC[7:4];
tPixCv[7:4] = tClrYuvC[3:0]; tPixCv[3:0] = tClrYuvC[3:0];
end
always @ (posedge clock)
begin
tPixPosX <= pixPosX;
tPixPosY <= pixPosY;
tPixCellIx <= tPixCellNextIx;
tPixCellFx <= tPixCellNextFx;
end
endmodule | 2 |
142,500 | data/full_repos/permissive/99182535/bjx1c32b/RegFPR.v | 99,182,535 | RegFPR.v | v | 286 | 66 | [] | [] | [] | null | line:36: before: "parameter" | null | 1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/RegFPR.v:9: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1c32b/RegFPR.v:11: Cannot find include file: FpuFp32To64.v\n`include "FpuFp32To64.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/RegFPR.v:12: Cannot find include file: FpuFp64To32.v\n`include "FpuFp64To32.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 314,673 | module | module RegFPR(
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRm, regValRm,
regIdRn, regValRn,
regMode, regCsFl,
regStMode,
ctlInFpul, ctlOutFpul
);
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRm;
input[6:0] regIdRn;
output[63:0] regValRs;
output[63:0] regValRt;
output[63:0] regValRm;
input[63:0] regValRn;
input[1:0] regMode;
input[15:0] regCsFl;
input[1:0] regStMode;
input[31:0] ctlInFpul;
output[31:0] ctlOutFpul;
reg[31:0] regFprH[15:0];
reg[31:0] regFprL[15:0];
reg[31:0] tRegValRsF;
reg[31:0] tRegValRtF;
reg[31:0] tRegValRmF;
wire[63:0] tRegValRsD;
wire[63:0] tRegValRtD;
wire[63:0] tRegValRmD;
wire[31:0] tRegValRnF;
reg[31:0] tRegValRnF2;
reg[63:0] tRegValRs;
reg[63:0] tRegValRt;
reg[63:0] tRegValRm;
reg[31:0] tFpul;
reg cvtF32To64;
reg accF32Raw;
reg cvtStF32To64;
reg accStF32Raw;
FpuFp32To64 fpCvtRs(clock, cvtF32To64, tRegValRsF, tRegValRsD);
FpuFp32To64 fpCvtRt(clock, cvtF32To64, tRegValRtF, tRegValRtD);
FpuFp32To64 fpCvtRm(clock, cvtF32To64, tRegValRmF, tRegValRmD);
FpuFp64To32 fpCvtRn(clock, cvtF32To64, regValRn, tRegValRnF);
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRm = tRegValRm;
assign ctlOutFpul = tFpul;
always @*
begin
tRegValRs=0;
tRegValRt=0;
tRegValRm=0;
tRegValRsF=0;
tRegValRtF=0;
tRegValRmF=0;
cvtF32To64=0;
accF32Raw=1;
cvtStF32To64=0;
accStF32Raw=1;
if(regIdRs[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRsF=regIdRs[0]?
regFprL[regIdRs[4:1]]:
regFprH[regIdRs[4:1]];
if(accF32Raw)
tRegValRs[31:0]=tRegValRsF;
else
tRegValRs=tRegValRsD;
end
else
begin
tRegValRs[31: 0]=regFprL[regIdRs[4:1]];
tRegValRs[63:32]=regFprH[regIdRs[4:1]];
end
end
else if(regIdRs==UREG_FPUL)
begin
tRegValRsF = ctlInFpul;
tRegValRs = tRegValRtD;
if(accF32Raw)
tRegValRs[31:0]=ctlInFpul[31:0];
end
if(regIdRt[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRtF=regIdRt[0]?
regFprL[regIdRt[4:1]]:
regFprH[regIdRt[4:1]];
if(accF32Raw)
tRegValRt[31:0]=tRegValRtF;
else
tRegValRt=tRegValRtD;
end
else
begin
tRegValRt[31: 0]=regFprL[regIdRt[4:1]];
tRegValRt[63:32]=regFprH[regIdRt[4:1]];
end
end
else if(regIdRt==UREG_FPUL)
begin
tRegValRtF = ctlInFpul;
tRegValRt = tRegValRtD;
if(accF32Raw)
tRegValRt[31:0]=ctlInFpul[31:0];
end
if(regIdRm[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRmF=regIdRs[0]?
regFprL[regIdRm[4:1]]:
regFprH[regIdRm[4:1]];
if(accF32Raw)
tRegValRm[31:0]=tRegValRmF;
else
tRegValRm=tRegValRmD;
end
else
begin
tRegValRm[31: 0]=regFprL[regIdRm[4:1]];
tRegValRm[63:32]=regFprH[regIdRm[4:1]];
end
end
if(cvtStF32To64 || accStF32Raw)
begin
tRegValRnF2 = accStF32Raw ?
regValRn[31:0] :
tRegValRnF;
end
end
always @ (posedge clock)
begin
if(regIdRn[6:5]==2'b10)
begin
if(cvtStF32To64 || accStF32Raw)
begin
if(regIdRn[0])
regFprL[regIdRn[4:1]] <= tRegValRnF2;
else
regFprH[regIdRn[4:1]] <= tRegValRnF2;
end
else
begin
regFprL[regIdRn[4:1]] <= regValRn[31: 0];
regFprH[regIdRn[4:1]] <= regValRn[63:32];
end
end
if(regIdRn==UREG_FPUL)
begin
case(regStMode)
2'b00: tFpul <= tRegValRnF2;
2'b01: tFpul <= tRegValRnF2;
2'b10: tFpul <= regValRn[31:0];
2'b11: tFpul <= regValRn[31:0];
endcase
end
else
tFpul <= ctlInFpul;
end
endmodule | module RegFPR(
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRm, regValRm,
regIdRn, regValRn,
regMode, regCsFl,
regStMode,
ctlInFpul, ctlOutFpul
); |
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRm;
input[6:0] regIdRn;
output[63:0] regValRs;
output[63:0] regValRt;
output[63:0] regValRm;
input[63:0] regValRn;
input[1:0] regMode;
input[15:0] regCsFl;
input[1:0] regStMode;
input[31:0] ctlInFpul;
output[31:0] ctlOutFpul;
reg[31:0] regFprH[15:0];
reg[31:0] regFprL[15:0];
reg[31:0] tRegValRsF;
reg[31:0] tRegValRtF;
reg[31:0] tRegValRmF;
wire[63:0] tRegValRsD;
wire[63:0] tRegValRtD;
wire[63:0] tRegValRmD;
wire[31:0] tRegValRnF;
reg[31:0] tRegValRnF2;
reg[63:0] tRegValRs;
reg[63:0] tRegValRt;
reg[63:0] tRegValRm;
reg[31:0] tFpul;
reg cvtF32To64;
reg accF32Raw;
reg cvtStF32To64;
reg accStF32Raw;
FpuFp32To64 fpCvtRs(clock, cvtF32To64, tRegValRsF, tRegValRsD);
FpuFp32To64 fpCvtRt(clock, cvtF32To64, tRegValRtF, tRegValRtD);
FpuFp32To64 fpCvtRm(clock, cvtF32To64, tRegValRmF, tRegValRmD);
FpuFp64To32 fpCvtRn(clock, cvtF32To64, regValRn, tRegValRnF);
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRm = tRegValRm;
assign ctlOutFpul = tFpul;
always @*
begin
tRegValRs=0;
tRegValRt=0;
tRegValRm=0;
tRegValRsF=0;
tRegValRtF=0;
tRegValRmF=0;
cvtF32To64=0;
accF32Raw=1;
cvtStF32To64=0;
accStF32Raw=1;
if(regIdRs[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRsF=regIdRs[0]?
regFprL[regIdRs[4:1]]:
regFprH[regIdRs[4:1]];
if(accF32Raw)
tRegValRs[31:0]=tRegValRsF;
else
tRegValRs=tRegValRsD;
end
else
begin
tRegValRs[31: 0]=regFprL[regIdRs[4:1]];
tRegValRs[63:32]=regFprH[regIdRs[4:1]];
end
end
else if(regIdRs==UREG_FPUL)
begin
tRegValRsF = ctlInFpul;
tRegValRs = tRegValRtD;
if(accF32Raw)
tRegValRs[31:0]=ctlInFpul[31:0];
end
if(regIdRt[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRtF=regIdRt[0]?
regFprL[regIdRt[4:1]]:
regFprH[regIdRt[4:1]];
if(accF32Raw)
tRegValRt[31:0]=tRegValRtF;
else
tRegValRt=tRegValRtD;
end
else
begin
tRegValRt[31: 0]=regFprL[regIdRt[4:1]];
tRegValRt[63:32]=regFprH[regIdRt[4:1]];
end
end
else if(regIdRt==UREG_FPUL)
begin
tRegValRtF = ctlInFpul;
tRegValRt = tRegValRtD;
if(accF32Raw)
tRegValRt[31:0]=ctlInFpul[31:0];
end
if(regIdRm[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRmF=regIdRs[0]?
regFprL[regIdRm[4:1]]:
regFprH[regIdRm[4:1]];
if(accF32Raw)
tRegValRm[31:0]=tRegValRmF;
else
tRegValRm=tRegValRmD;
end
else
begin
tRegValRm[31: 0]=regFprL[regIdRm[4:1]];
tRegValRm[63:32]=regFprH[regIdRm[4:1]];
end
end
if(cvtStF32To64 || accStF32Raw)
begin
tRegValRnF2 = accStF32Raw ?
regValRn[31:0] :
tRegValRnF;
end
end
always @ (posedge clock)
begin
if(regIdRn[6:5]==2'b10)
begin
if(cvtStF32To64 || accStF32Raw)
begin
if(regIdRn[0])
regFprL[regIdRn[4:1]] <= tRegValRnF2;
else
regFprH[regIdRn[4:1]] <= tRegValRnF2;
end
else
begin
regFprL[regIdRn[4:1]] <= regValRn[31: 0];
regFprH[regIdRn[4:1]] <= regValRn[63:32];
end
end
if(regIdRn==UREG_FPUL)
begin
case(regStMode)
2'b00: tFpul <= tRegValRnF2;
2'b01: tFpul <= tRegValRnF2;
2'b10: tFpul <= regValRn[31:0];
2'b11: tFpul <= regValRn[31:0];
endcase
end
else
tFpul <= ctlInFpul;
end
endmodule | 2 |
142,501 | data/full_repos/permissive/99182535/bjx1c32b/RegFPR2.v | 99,182,535 | RegFPR2.v | v | 461 | 58 | [] | [] | [] | null | line:36: before: "parameter" | null | 1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/RegFPR2.v:9: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 314,674 | module | module RegFPR2(
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
regIdRo, regValRo,
regMode, regCsFl,
regStMode,
ctlInFpul, ctlOutFpul
);
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
input[6:0] regIdRo;
output[63:0] regValRs;
output[63:0] regValRt;
output[63:0] regValRn;
input[63:0] regValRo;
input[1:0] regMode;
input[15:0] regCsFl;
input[1:0] regStMode;
input[31:0] ctlInFpul;
output[31:0] ctlOutFpul;
reg[31:0] regFprFR00;
reg[31:0] regFprFR01;
reg[31:0] regFprFR02;
reg[31:0] regFprFR03;
reg[31:0] regFprFR04;
reg[31:0] regFprFR05;
reg[31:0] regFprFR06;
reg[31:0] regFprFR07;
reg[31:0] regFprFR08;
reg[31:0] regFprFR09;
reg[31:0] regFprFR10;
reg[31:0] regFprFR11;
reg[31:0] regFprFR12;
reg[31:0] regFprFR13;
reg[31:0] regFprFR14;
reg[31:0] regFprFR15;
reg[31:0] regFprXF00;
reg[31:0] regFprXF01;
reg[31:0] regFprXF02;
reg[31:0] regFprXF03;
reg[31:0] regFprXF04;
reg[31:0] regFprXF05;
reg[31:0] regFprXF06;
reg[31:0] regFprXF07;
reg[31:0] regFprXF08;
reg[31:0] regFprXF09;
reg[31:0] regFprXF10;
reg[31:0] regFprXF11;
reg[31:0] regFprXF12;
reg[31:0] regFprXF13;
reg[31:0] regFprXF14;
reg[31:0] regFprXF15;
reg[31:0] nxtRegFprFR00;
reg[31:0] nxtRegFprFR01;
reg[31:0] nxtRegFprFR02;
reg[31:0] nxtRegFprFR03;
reg[31:0] nxtRegFprFR04;
reg[31:0] nxtRegFprFR05;
reg[31:0] nxtRegFprFR06;
reg[31:0] nxtRegFprFR07;
reg[31:0] nxtRegFprFR08;
reg[31:0] nxtRegFprFR09;
reg[31:0] nxtRegFprFR10;
reg[31:0] nxtRegFprFR11;
reg[31:0] nxtRegFprFR12;
reg[31:0] nxtRegFprFR13;
reg[31:0] nxtRegFprFR14;
reg[31:0] nxtRegFprFR15;
reg[31:0] nxtRegFprXF00;
reg[31:0] nxtRegFprXF01;
reg[31:0] nxtRegFprXF02;
reg[31:0] nxtRegFprXF03;
reg[31:0] nxtRegFprXF04;
reg[31:0] nxtRegFprXF05;
reg[31:0] nxtRegFprXF06;
reg[31:0] nxtRegFprXF07;
reg[31:0] nxtRegFprXF08;
reg[31:0] nxtRegFprXF09;
reg[31:0] nxtRegFprXF10;
reg[31:0] nxtRegFprXF11;
reg[31:0] nxtRegFprXF12;
reg[31:0] nxtRegFprXF13;
reg[31:0] nxtRegFprXF14;
reg[31:0] nxtRegFprXF15;
reg[63:0] tRegValRs;
reg[63:0] tRegValRt;
reg[63:0] tRegValRn;
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRn = tRegValRn;
reg[31:0] tFpul;
assign ctlOutFpul = tFpul;
reg regGet64;
reg regSet64;
always @*
begin
nxtRegFprFR00 = regFprFR00; nxtRegFprFR01 = regFprFR01;
nxtRegFprFR02 = regFprFR02; nxtRegFprFR03 = regFprFR03;
nxtRegFprFR04 = regFprFR04; nxtRegFprFR05 = regFprFR05;
nxtRegFprFR06 = regFprFR06; nxtRegFprFR07 = regFprFR07;
nxtRegFprFR08 = regFprFR08; nxtRegFprFR09 = regFprFR09;
nxtRegFprFR10 = regFprFR10; nxtRegFprFR11 = regFprFR11;
nxtRegFprFR12 = regFprFR12; nxtRegFprFR13 = regFprFR13;
nxtRegFprFR14 = regFprFR14; nxtRegFprFR15 = regFprFR15;
nxtRegFprXF00 = regFprXF00; nxtRegFprXF01 = regFprXF01;
nxtRegFprXF02 = regFprXF02; nxtRegFprXF03 = regFprXF03;
nxtRegFprXF04 = regFprXF04; nxtRegFprXF05 = regFprXF05;
nxtRegFprXF06 = regFprXF06; nxtRegFprXF07 = regFprXF07;
nxtRegFprXF08 = regFprXF08; nxtRegFprXF09 = regFprXF09;
nxtRegFprXF10 = regFprXF10; nxtRegFprXF11 = regFprXF11;
nxtRegFprXF12 = regFprXF12; nxtRegFprXF13 = regFprXF13;
nxtRegFprXF14 = regFprXF14; nxtRegFprXF15 = regFprXF15;
tRegValRs=0;
tRegValRt=0;
tRegValRn=0;
regGet64 = regMode[0];
regSet64 = regStMode[0];
tFpul = ctlInFpul;
if(regGet64)
begin
case(regIdRs)
UREG_FR0: tRegValRs = {regFprFR00, regFprFR01};
UREG_FR1: tRegValRs = {regFprXF00, regFprXF01};
UREG_FR2: tRegValRs = {regFprFR02, regFprFR03};
UREG_FR3: tRegValRs = {regFprXF02, regFprXF03};
UREG_FR4: tRegValRs = {regFprFR04, regFprFR05};
UREG_FR5: tRegValRs = {regFprXF04, regFprXF05};
UREG_FR6: tRegValRs = {regFprFR06, regFprFR07};
UREG_FR7: tRegValRs = {regFprXF06, regFprXF07};
UREG_FR8: tRegValRs = {regFprFR08, regFprFR09};
UREG_FR9: tRegValRs = {regFprXF08, regFprXF09};
UREG_FR10: tRegValRs = {regFprFR10, regFprFR11};
UREG_FR11: tRegValRs = {regFprXF10, regFprXF11};
UREG_FR12: tRegValRs = {regFprFR12, regFprFR13};
UREG_FR13: tRegValRs = {regFprXF12, regFprXF13};
UREG_FR14: tRegValRs = {regFprFR14, regFprFR15};
UREG_FR15: tRegValRs = {regFprXF14, regFprXF15};
UREG_FPUL: tRegValRs = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRt)
UREG_FR0: tRegValRt = {regFprFR00, regFprFR01};
UREG_FR1: tRegValRt = {regFprXF00, regFprXF01};
UREG_FR2: tRegValRt = {regFprFR02, regFprFR03};
UREG_FR3: tRegValRt = {regFprXF02, regFprXF03};
UREG_FR4: tRegValRt = {regFprFR04, regFprFR05};
UREG_FR5: tRegValRt = {regFprXF04, regFprXF05};
UREG_FR6: tRegValRt = {regFprFR06, regFprFR07};
UREG_FR7: tRegValRt = {regFprXF06, regFprXF07};
UREG_FR8: tRegValRt = {regFprFR08, regFprFR09};
UREG_FR9: tRegValRt = {regFprXF08, regFprXF09};
UREG_FR10: tRegValRt = {regFprFR10, regFprFR11};
UREG_FR11: tRegValRt = {regFprXF10, regFprXF11};
UREG_FR12: tRegValRt = {regFprFR12, regFprFR13};
UREG_FR13: tRegValRt = {regFprXF12, regFprXF13};
UREG_FR14: tRegValRt = {regFprFR14, regFprFR15};
UREG_FR15: tRegValRt = {regFprXF14, regFprXF15};
UREG_FPUL: tRegValRt = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRn)
UREG_FR0: tRegValRn = {regFprFR00, regFprFR01};
UREG_FR1: tRegValRn = {regFprXF00, regFprXF01};
UREG_FR2: tRegValRn = {regFprFR02, regFprFR03};
UREG_FR3: tRegValRn = {regFprXF02, regFprXF03};
UREG_FR4: tRegValRn = {regFprFR04, regFprFR05};
UREG_FR5: tRegValRn = {regFprXF04, regFprXF05};
UREG_FR6: tRegValRn = {regFprFR06, regFprFR07};
UREG_FR7: tRegValRn = {regFprXF06, regFprXF07};
UREG_FR8: tRegValRn = {regFprFR08, regFprFR09};
UREG_FR9: tRegValRn = {regFprXF08, regFprXF09};
UREG_FR10: tRegValRn = {regFprFR10, regFprFR11};
UREG_FR11: tRegValRn = {regFprXF10, regFprXF11};
UREG_FR12: tRegValRn = {regFprFR12, regFprFR13};
UREG_FR13: tRegValRn = {regFprXF12, regFprXF13};
UREG_FR14: tRegValRn = {regFprFR14, regFprFR15};
UREG_FR15: tRegValRn = {regFprXF14, regFprXF15};
UREG_FPUL: tRegValRn = {UV32_XX, ctlInFpul};
default: begin end
endcase
end else begin
case(regIdRs)
UREG_FR0: tRegValRs = {UV32_XX, regFprFR00};
UREG_FR1: tRegValRs = {UV32_XX, regFprFR01};
UREG_FR2: tRegValRs = {UV32_XX, regFprFR02};
UREG_FR3: tRegValRs = {UV32_XX, regFprFR03};
UREG_FR4: tRegValRs = {UV32_XX, regFprFR04};
UREG_FR5: tRegValRs = {UV32_XX, regFprFR05};
UREG_FR6: tRegValRs = {UV32_XX, regFprFR06};
UREG_FR7: tRegValRs = {UV32_XX, regFprFR07};
UREG_FR8: tRegValRs = {UV32_XX, regFprFR08};
UREG_FR9: tRegValRs = {UV32_XX, regFprFR09};
UREG_FR10: tRegValRs = {UV32_XX, regFprFR10};
UREG_FR11: tRegValRs = {UV32_XX, regFprFR11};
UREG_FR12: tRegValRs = {UV32_XX, regFprFR12};
UREG_FR13: tRegValRs = {UV32_XX, regFprFR13};
UREG_FR14: tRegValRs = {UV32_XX, regFprFR14};
UREG_FR15: tRegValRs = {UV32_XX, regFprFR15};
UREG_XF0: tRegValRs = {UV32_XX, regFprXF00};
UREG_XF1: tRegValRs = {UV32_XX, regFprXF01};
UREG_XF2: tRegValRs = {UV32_XX, regFprXF02};
UREG_XF3: tRegValRs = {UV32_XX, regFprXF03};
UREG_XF4: tRegValRs = {UV32_XX, regFprXF04};
UREG_XF5: tRegValRs = {UV32_XX, regFprXF05};
UREG_XF6: tRegValRs = {UV32_XX, regFprXF06};
UREG_XF7: tRegValRs = {UV32_XX, regFprXF07};
UREG_XF8: tRegValRs = {UV32_XX, regFprXF08};
UREG_XF9: tRegValRs = {UV32_XX, regFprXF09};
UREG_XF10: tRegValRs = {UV32_XX, regFprXF10};
UREG_XF11: tRegValRs = {UV32_XX, regFprXF11};
UREG_XF12: tRegValRs = {UV32_XX, regFprXF12};
UREG_XF13: tRegValRs = {UV32_XX, regFprXF13};
UREG_XF14: tRegValRs = {UV32_XX, regFprXF14};
UREG_XF15: tRegValRs = {UV32_XX, regFprXF15};
UREG_FPUL: tRegValRs = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRt)
UREG_FR0: tRegValRt = {UV32_XX, regFprFR00};
UREG_FR1: tRegValRt = {UV32_XX, regFprFR01};
UREG_FR2: tRegValRt = {UV32_XX, regFprFR02};
UREG_FR3: tRegValRt = {UV32_XX, regFprFR03};
UREG_FR4: tRegValRt = {UV32_XX, regFprFR04};
UREG_FR5: tRegValRt = {UV32_XX, regFprFR05};
UREG_FR6: tRegValRt = {UV32_XX, regFprFR06};
UREG_FR7: tRegValRt = {UV32_XX, regFprFR07};
UREG_FR8: tRegValRt = {UV32_XX, regFprFR08};
UREG_FR9: tRegValRt = {UV32_XX, regFprFR09};
UREG_FR10: tRegValRt = {UV32_XX, regFprFR10};
UREG_FR11: tRegValRt = {UV32_XX, regFprFR11};
UREG_FR12: tRegValRt = {UV32_XX, regFprFR12};
UREG_FR13: tRegValRt = {UV32_XX, regFprFR13};
UREG_FR14: tRegValRt = {UV32_XX, regFprFR14};
UREG_FR15: tRegValRt = {UV32_XX, regFprFR15};
UREG_XF0: tRegValRt = {UV32_XX, regFprXF00};
UREG_XF1: tRegValRt = {UV32_XX, regFprXF01};
UREG_XF2: tRegValRt = {UV32_XX, regFprXF02};
UREG_XF3: tRegValRt = {UV32_XX, regFprXF03};
UREG_XF4: tRegValRt = {UV32_XX, regFprXF04};
UREG_XF5: tRegValRt = {UV32_XX, regFprXF05};
UREG_XF6: tRegValRt = {UV32_XX, regFprXF06};
UREG_XF7: tRegValRt = {UV32_XX, regFprXF07};
UREG_XF8: tRegValRt = {UV32_XX, regFprXF08};
UREG_XF9: tRegValRt = {UV32_XX, regFprXF09};
UREG_XF10: tRegValRt = {UV32_XX, regFprXF10};
UREG_XF11: tRegValRt = {UV32_XX, regFprXF11};
UREG_XF12: tRegValRt = {UV32_XX, regFprXF12};
UREG_XF13: tRegValRt = {UV32_XX, regFprXF13};
UREG_XF14: tRegValRt = {UV32_XX, regFprXF14};
UREG_XF15: tRegValRt = {UV32_XX, regFprXF15};
UREG_FPUL: tRegValRt = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRn)
UREG_FR0: tRegValRn = {UV32_XX, regFprFR00};
UREG_FR1: tRegValRn = {UV32_XX, regFprFR01};
UREG_FR2: tRegValRn = {UV32_XX, regFprFR02};
UREG_FR3: tRegValRn = {UV32_XX, regFprFR03};
UREG_FR4: tRegValRn = {UV32_XX, regFprFR04};
UREG_FR5: tRegValRn = {UV32_XX, regFprFR05};
UREG_FR6: tRegValRn = {UV32_XX, regFprFR06};
UREG_FR7: tRegValRn = {UV32_XX, regFprFR07};
UREG_FR8: tRegValRn = {UV32_XX, regFprFR08};
UREG_FR9: tRegValRn = {UV32_XX, regFprFR09};
UREG_FR10: tRegValRn = {UV32_XX, regFprFR10};
UREG_FR11: tRegValRn = {UV32_XX, regFprFR11};
UREG_FR12: tRegValRn = {UV32_XX, regFprFR12};
UREG_FR13: tRegValRn = {UV32_XX, regFprFR13};
UREG_FR14: tRegValRn = {UV32_XX, regFprFR14};
UREG_FR15: tRegValRn = {UV32_XX, regFprFR15};
UREG_XF0: tRegValRn = {UV32_XX, regFprXF00};
UREG_XF1: tRegValRn = {UV32_XX, regFprXF01};
UREG_XF2: tRegValRn = {UV32_XX, regFprXF02};
UREG_XF3: tRegValRn = {UV32_XX, regFprXF03};
UREG_XF4: tRegValRn = {UV32_XX, regFprXF04};
UREG_XF5: tRegValRn = {UV32_XX, regFprXF05};
UREG_XF6: tRegValRn = {UV32_XX, regFprXF06};
UREG_XF7: tRegValRn = {UV32_XX, regFprXF07};
UREG_XF8: tRegValRn = {UV32_XX, regFprXF08};
UREG_XF9: tRegValRn = {UV32_XX, regFprXF09};
UREG_XF10: tRegValRn = {UV32_XX, regFprXF10};
UREG_XF11: tRegValRn = {UV32_XX, regFprXF11};
UREG_XF12: tRegValRn = {UV32_XX, regFprXF12};
UREG_XF13: tRegValRn = {UV32_XX, regFprXF13};
UREG_XF14: tRegValRn = {UV32_XX, regFprXF14};
UREG_XF15: tRegValRn = {UV32_XX, regFprXF15};
UREG_FPUL: tRegValRn = {UV32_XX, ctlInFpul};
default: begin end
endcase
end
if(regSet64)
begin
case(regIdRo)
UREG_FR0: {nxtRegFprFR00, nxtRegFprFR01} = regValRo;
UREG_FR1: {nxtRegFprXF00, nxtRegFprXF01} = regValRo;
UREG_FR2: {nxtRegFprFR02, nxtRegFprFR03} = regValRo;
UREG_FR3: {nxtRegFprXF02, nxtRegFprXF03} = regValRo;
UREG_FR4: {nxtRegFprFR04, nxtRegFprFR05} = regValRo;
UREG_FR5: {nxtRegFprXF04, nxtRegFprXF05} = regValRo;
UREG_FR6: {nxtRegFprFR06, nxtRegFprFR07} = regValRo;
UREG_FR7: {nxtRegFprXF06, nxtRegFprXF07} = regValRo;
UREG_FR8: {nxtRegFprFR08, nxtRegFprFR09} = regValRo;
UREG_FR9: {nxtRegFprXF08, nxtRegFprXF09} = regValRo;
UREG_FR10: {nxtRegFprFR10, nxtRegFprFR11} = regValRo;
UREG_FR11: {nxtRegFprXF10, nxtRegFprXF11} = regValRo;
UREG_FR12: {nxtRegFprFR12, nxtRegFprFR13} = regValRo;
UREG_FR13: {nxtRegFprXF12, nxtRegFprXF13} = regValRo;
UREG_FR14: {nxtRegFprFR14, nxtRegFprFR15} = regValRo;
UREG_FR15: {nxtRegFprXF14, nxtRegFprXF15} = regValRo;
UREG_FPUL: tFpul = regValRo[31:0];
default: begin end
endcase
end
else
begin
case(regIdRo)
UREG_FR0: nxtRegFprFR00 = regValRo[31:0];
UREG_FR1: nxtRegFprFR01 = regValRo[31:0];
UREG_FR2: nxtRegFprFR02 = regValRo[31:0];
UREG_FR3: nxtRegFprFR03 = regValRo[31:0];
UREG_FR4: nxtRegFprFR04 = regValRo[31:0];
UREG_FR5: nxtRegFprFR05 = regValRo[31:0];
UREG_FR6: nxtRegFprFR06 = regValRo[31:0];
UREG_FR7: nxtRegFprFR07 = regValRo[31:0];
UREG_FR8: nxtRegFprFR08 = regValRo[31:0];
UREG_FR9: nxtRegFprFR09 = regValRo[31:0];
UREG_FR10: nxtRegFprFR10 = regValRo[31:0];
UREG_FR11: nxtRegFprFR11 = regValRo[31:0];
UREG_FR12: nxtRegFprFR12 = regValRo[31:0];
UREG_FR13: nxtRegFprFR13 = regValRo[31:0];
UREG_FR14: nxtRegFprFR14 = regValRo[31:0];
UREG_FR15: nxtRegFprFR15 = regValRo[31:0];
UREG_XF0: nxtRegFprXF00 = regValRo[31:0];
UREG_XF1: nxtRegFprXF01 = regValRo[31:0];
UREG_XF2: nxtRegFprXF02 = regValRo[31:0];
UREG_XF3: nxtRegFprXF03 = regValRo[31:0];
UREG_XF4: nxtRegFprXF04 = regValRo[31:0];
UREG_XF5: nxtRegFprXF05 = regValRo[31:0];
UREG_XF6: nxtRegFprXF06 = regValRo[31:0];
UREG_XF7: nxtRegFprXF07 = regValRo[31:0];
UREG_XF8: nxtRegFprXF08 = regValRo[31:0];
UREG_XF9: nxtRegFprXF09 = regValRo[31:0];
UREG_XF10: nxtRegFprXF10 = regValRo[31:0];
UREG_XF11: nxtRegFprXF11 = regValRo[31:0];
UREG_XF12: nxtRegFprXF12 = regValRo[31:0];
UREG_XF13: nxtRegFprXF13 = regValRo[31:0];
UREG_XF14: nxtRegFprXF14 = regValRo[31:0];
UREG_XF15: nxtRegFprXF15 = regValRo[31:0];
UREG_FPUL: tFpul = regValRo[31:0];
default: begin end
endcase
end
end
always @ (posedge clock)
begin
regFprFR00 <= nxtRegFprFR00;
regFprFR01 <= nxtRegFprFR01;
regFprFR02 <= nxtRegFprFR02;
regFprFR03 <= nxtRegFprFR03;
regFprFR04 <= nxtRegFprFR04;
regFprFR05 <= nxtRegFprFR05;
regFprFR06 <= nxtRegFprFR06;
regFprFR07 <= nxtRegFprFR07;
regFprFR08 <= nxtRegFprFR08;
regFprFR09 <= nxtRegFprFR09;
regFprFR10 <= nxtRegFprFR10;
regFprFR11 <= nxtRegFprFR11;
regFprFR12 <= nxtRegFprFR12;
regFprFR13 <= nxtRegFprFR13;
regFprFR14 <= nxtRegFprFR14;
regFprFR15 <= nxtRegFprFR15;
regFprXF00 <= nxtRegFprXF00;
regFprXF01 <= nxtRegFprXF01;
regFprXF02 <= nxtRegFprXF02;
regFprXF03 <= nxtRegFprXF03;
regFprXF04 <= nxtRegFprXF04;
regFprXF05 <= nxtRegFprXF05;
regFprXF06 <= nxtRegFprXF06;
regFprXF07 <= nxtRegFprXF07;
regFprXF08 <= nxtRegFprXF08;
regFprXF09 <= nxtRegFprXF09;
regFprXF10 <= nxtRegFprXF10;
regFprXF11 <= nxtRegFprXF11;
regFprXF12 <= nxtRegFprXF12;
regFprXF13 <= nxtRegFprXF13;
regFprXF14 <= nxtRegFprXF14;
regFprXF15 <= nxtRegFprXF15;
end
endmodule | module RegFPR2(
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
regIdRo, regValRo,
regMode, regCsFl,
regStMode,
ctlInFpul, ctlOutFpul
); |
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
input[6:0] regIdRo;
output[63:0] regValRs;
output[63:0] regValRt;
output[63:0] regValRn;
input[63:0] regValRo;
input[1:0] regMode;
input[15:0] regCsFl;
input[1:0] regStMode;
input[31:0] ctlInFpul;
output[31:0] ctlOutFpul;
reg[31:0] regFprFR00;
reg[31:0] regFprFR01;
reg[31:0] regFprFR02;
reg[31:0] regFprFR03;
reg[31:0] regFprFR04;
reg[31:0] regFprFR05;
reg[31:0] regFprFR06;
reg[31:0] regFprFR07;
reg[31:0] regFprFR08;
reg[31:0] regFprFR09;
reg[31:0] regFprFR10;
reg[31:0] regFprFR11;
reg[31:0] regFprFR12;
reg[31:0] regFprFR13;
reg[31:0] regFprFR14;
reg[31:0] regFprFR15;
reg[31:0] regFprXF00;
reg[31:0] regFprXF01;
reg[31:0] regFprXF02;
reg[31:0] regFprXF03;
reg[31:0] regFprXF04;
reg[31:0] regFprXF05;
reg[31:0] regFprXF06;
reg[31:0] regFprXF07;
reg[31:0] regFprXF08;
reg[31:0] regFprXF09;
reg[31:0] regFprXF10;
reg[31:0] regFprXF11;
reg[31:0] regFprXF12;
reg[31:0] regFprXF13;
reg[31:0] regFprXF14;
reg[31:0] regFprXF15;
reg[31:0] nxtRegFprFR00;
reg[31:0] nxtRegFprFR01;
reg[31:0] nxtRegFprFR02;
reg[31:0] nxtRegFprFR03;
reg[31:0] nxtRegFprFR04;
reg[31:0] nxtRegFprFR05;
reg[31:0] nxtRegFprFR06;
reg[31:0] nxtRegFprFR07;
reg[31:0] nxtRegFprFR08;
reg[31:0] nxtRegFprFR09;
reg[31:0] nxtRegFprFR10;
reg[31:0] nxtRegFprFR11;
reg[31:0] nxtRegFprFR12;
reg[31:0] nxtRegFprFR13;
reg[31:0] nxtRegFprFR14;
reg[31:0] nxtRegFprFR15;
reg[31:0] nxtRegFprXF00;
reg[31:0] nxtRegFprXF01;
reg[31:0] nxtRegFprXF02;
reg[31:0] nxtRegFprXF03;
reg[31:0] nxtRegFprXF04;
reg[31:0] nxtRegFprXF05;
reg[31:0] nxtRegFprXF06;
reg[31:0] nxtRegFprXF07;
reg[31:0] nxtRegFprXF08;
reg[31:0] nxtRegFprXF09;
reg[31:0] nxtRegFprXF10;
reg[31:0] nxtRegFprXF11;
reg[31:0] nxtRegFprXF12;
reg[31:0] nxtRegFprXF13;
reg[31:0] nxtRegFprXF14;
reg[31:0] nxtRegFprXF15;
reg[63:0] tRegValRs;
reg[63:0] tRegValRt;
reg[63:0] tRegValRn;
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRn = tRegValRn;
reg[31:0] tFpul;
assign ctlOutFpul = tFpul;
reg regGet64;
reg regSet64;
always @*
begin
nxtRegFprFR00 = regFprFR00; nxtRegFprFR01 = regFprFR01;
nxtRegFprFR02 = regFprFR02; nxtRegFprFR03 = regFprFR03;
nxtRegFprFR04 = regFprFR04; nxtRegFprFR05 = regFprFR05;
nxtRegFprFR06 = regFprFR06; nxtRegFprFR07 = regFprFR07;
nxtRegFprFR08 = regFprFR08; nxtRegFprFR09 = regFprFR09;
nxtRegFprFR10 = regFprFR10; nxtRegFprFR11 = regFprFR11;
nxtRegFprFR12 = regFprFR12; nxtRegFprFR13 = regFprFR13;
nxtRegFprFR14 = regFprFR14; nxtRegFprFR15 = regFprFR15;
nxtRegFprXF00 = regFprXF00; nxtRegFprXF01 = regFprXF01;
nxtRegFprXF02 = regFprXF02; nxtRegFprXF03 = regFprXF03;
nxtRegFprXF04 = regFprXF04; nxtRegFprXF05 = regFprXF05;
nxtRegFprXF06 = regFprXF06; nxtRegFprXF07 = regFprXF07;
nxtRegFprXF08 = regFprXF08; nxtRegFprXF09 = regFprXF09;
nxtRegFprXF10 = regFprXF10; nxtRegFprXF11 = regFprXF11;
nxtRegFprXF12 = regFprXF12; nxtRegFprXF13 = regFprXF13;
nxtRegFprXF14 = regFprXF14; nxtRegFprXF15 = regFprXF15;
tRegValRs=0;
tRegValRt=0;
tRegValRn=0;
regGet64 = regMode[0];
regSet64 = regStMode[0];
tFpul = ctlInFpul;
if(regGet64)
begin
case(regIdRs)
UREG_FR0: tRegValRs = {regFprFR00, regFprFR01};
UREG_FR1: tRegValRs = {regFprXF00, regFprXF01};
UREG_FR2: tRegValRs = {regFprFR02, regFprFR03};
UREG_FR3: tRegValRs = {regFprXF02, regFprXF03};
UREG_FR4: tRegValRs = {regFprFR04, regFprFR05};
UREG_FR5: tRegValRs = {regFprXF04, regFprXF05};
UREG_FR6: tRegValRs = {regFprFR06, regFprFR07};
UREG_FR7: tRegValRs = {regFprXF06, regFprXF07};
UREG_FR8: tRegValRs = {regFprFR08, regFprFR09};
UREG_FR9: tRegValRs = {regFprXF08, regFprXF09};
UREG_FR10: tRegValRs = {regFprFR10, regFprFR11};
UREG_FR11: tRegValRs = {regFprXF10, regFprXF11};
UREG_FR12: tRegValRs = {regFprFR12, regFprFR13};
UREG_FR13: tRegValRs = {regFprXF12, regFprXF13};
UREG_FR14: tRegValRs = {regFprFR14, regFprFR15};
UREG_FR15: tRegValRs = {regFprXF14, regFprXF15};
UREG_FPUL: tRegValRs = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRt)
UREG_FR0: tRegValRt = {regFprFR00, regFprFR01};
UREG_FR1: tRegValRt = {regFprXF00, regFprXF01};
UREG_FR2: tRegValRt = {regFprFR02, regFprFR03};
UREG_FR3: tRegValRt = {regFprXF02, regFprXF03};
UREG_FR4: tRegValRt = {regFprFR04, regFprFR05};
UREG_FR5: tRegValRt = {regFprXF04, regFprXF05};
UREG_FR6: tRegValRt = {regFprFR06, regFprFR07};
UREG_FR7: tRegValRt = {regFprXF06, regFprXF07};
UREG_FR8: tRegValRt = {regFprFR08, regFprFR09};
UREG_FR9: tRegValRt = {regFprXF08, regFprXF09};
UREG_FR10: tRegValRt = {regFprFR10, regFprFR11};
UREG_FR11: tRegValRt = {regFprXF10, regFprXF11};
UREG_FR12: tRegValRt = {regFprFR12, regFprFR13};
UREG_FR13: tRegValRt = {regFprXF12, regFprXF13};
UREG_FR14: tRegValRt = {regFprFR14, regFprFR15};
UREG_FR15: tRegValRt = {regFprXF14, regFprXF15};
UREG_FPUL: tRegValRt = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRn)
UREG_FR0: tRegValRn = {regFprFR00, regFprFR01};
UREG_FR1: tRegValRn = {regFprXF00, regFprXF01};
UREG_FR2: tRegValRn = {regFprFR02, regFprFR03};
UREG_FR3: tRegValRn = {regFprXF02, regFprXF03};
UREG_FR4: tRegValRn = {regFprFR04, regFprFR05};
UREG_FR5: tRegValRn = {regFprXF04, regFprXF05};
UREG_FR6: tRegValRn = {regFprFR06, regFprFR07};
UREG_FR7: tRegValRn = {regFprXF06, regFprXF07};
UREG_FR8: tRegValRn = {regFprFR08, regFprFR09};
UREG_FR9: tRegValRn = {regFprXF08, regFprXF09};
UREG_FR10: tRegValRn = {regFprFR10, regFprFR11};
UREG_FR11: tRegValRn = {regFprXF10, regFprXF11};
UREG_FR12: tRegValRn = {regFprFR12, regFprFR13};
UREG_FR13: tRegValRn = {regFprXF12, regFprXF13};
UREG_FR14: tRegValRn = {regFprFR14, regFprFR15};
UREG_FR15: tRegValRn = {regFprXF14, regFprXF15};
UREG_FPUL: tRegValRn = {UV32_XX, ctlInFpul};
default: begin end
endcase
end else begin
case(regIdRs)
UREG_FR0: tRegValRs = {UV32_XX, regFprFR00};
UREG_FR1: tRegValRs = {UV32_XX, regFprFR01};
UREG_FR2: tRegValRs = {UV32_XX, regFprFR02};
UREG_FR3: tRegValRs = {UV32_XX, regFprFR03};
UREG_FR4: tRegValRs = {UV32_XX, regFprFR04};
UREG_FR5: tRegValRs = {UV32_XX, regFprFR05};
UREG_FR6: tRegValRs = {UV32_XX, regFprFR06};
UREG_FR7: tRegValRs = {UV32_XX, regFprFR07};
UREG_FR8: tRegValRs = {UV32_XX, regFprFR08};
UREG_FR9: tRegValRs = {UV32_XX, regFprFR09};
UREG_FR10: tRegValRs = {UV32_XX, regFprFR10};
UREG_FR11: tRegValRs = {UV32_XX, regFprFR11};
UREG_FR12: tRegValRs = {UV32_XX, regFprFR12};
UREG_FR13: tRegValRs = {UV32_XX, regFprFR13};
UREG_FR14: tRegValRs = {UV32_XX, regFprFR14};
UREG_FR15: tRegValRs = {UV32_XX, regFprFR15};
UREG_XF0: tRegValRs = {UV32_XX, regFprXF00};
UREG_XF1: tRegValRs = {UV32_XX, regFprXF01};
UREG_XF2: tRegValRs = {UV32_XX, regFprXF02};
UREG_XF3: tRegValRs = {UV32_XX, regFprXF03};
UREG_XF4: tRegValRs = {UV32_XX, regFprXF04};
UREG_XF5: tRegValRs = {UV32_XX, regFprXF05};
UREG_XF6: tRegValRs = {UV32_XX, regFprXF06};
UREG_XF7: tRegValRs = {UV32_XX, regFprXF07};
UREG_XF8: tRegValRs = {UV32_XX, regFprXF08};
UREG_XF9: tRegValRs = {UV32_XX, regFprXF09};
UREG_XF10: tRegValRs = {UV32_XX, regFprXF10};
UREG_XF11: tRegValRs = {UV32_XX, regFprXF11};
UREG_XF12: tRegValRs = {UV32_XX, regFprXF12};
UREG_XF13: tRegValRs = {UV32_XX, regFprXF13};
UREG_XF14: tRegValRs = {UV32_XX, regFprXF14};
UREG_XF15: tRegValRs = {UV32_XX, regFprXF15};
UREG_FPUL: tRegValRs = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRt)
UREG_FR0: tRegValRt = {UV32_XX, regFprFR00};
UREG_FR1: tRegValRt = {UV32_XX, regFprFR01};
UREG_FR2: tRegValRt = {UV32_XX, regFprFR02};
UREG_FR3: tRegValRt = {UV32_XX, regFprFR03};
UREG_FR4: tRegValRt = {UV32_XX, regFprFR04};
UREG_FR5: tRegValRt = {UV32_XX, regFprFR05};
UREG_FR6: tRegValRt = {UV32_XX, regFprFR06};
UREG_FR7: tRegValRt = {UV32_XX, regFprFR07};
UREG_FR8: tRegValRt = {UV32_XX, regFprFR08};
UREG_FR9: tRegValRt = {UV32_XX, regFprFR09};
UREG_FR10: tRegValRt = {UV32_XX, regFprFR10};
UREG_FR11: tRegValRt = {UV32_XX, regFprFR11};
UREG_FR12: tRegValRt = {UV32_XX, regFprFR12};
UREG_FR13: tRegValRt = {UV32_XX, regFprFR13};
UREG_FR14: tRegValRt = {UV32_XX, regFprFR14};
UREG_FR15: tRegValRt = {UV32_XX, regFprFR15};
UREG_XF0: tRegValRt = {UV32_XX, regFprXF00};
UREG_XF1: tRegValRt = {UV32_XX, regFprXF01};
UREG_XF2: tRegValRt = {UV32_XX, regFprXF02};
UREG_XF3: tRegValRt = {UV32_XX, regFprXF03};
UREG_XF4: tRegValRt = {UV32_XX, regFprXF04};
UREG_XF5: tRegValRt = {UV32_XX, regFprXF05};
UREG_XF6: tRegValRt = {UV32_XX, regFprXF06};
UREG_XF7: tRegValRt = {UV32_XX, regFprXF07};
UREG_XF8: tRegValRt = {UV32_XX, regFprXF08};
UREG_XF9: tRegValRt = {UV32_XX, regFprXF09};
UREG_XF10: tRegValRt = {UV32_XX, regFprXF10};
UREG_XF11: tRegValRt = {UV32_XX, regFprXF11};
UREG_XF12: tRegValRt = {UV32_XX, regFprXF12};
UREG_XF13: tRegValRt = {UV32_XX, regFprXF13};
UREG_XF14: tRegValRt = {UV32_XX, regFprXF14};
UREG_XF15: tRegValRt = {UV32_XX, regFprXF15};
UREG_FPUL: tRegValRt = {UV32_XX, ctlInFpul};
default: begin end
endcase
case(regIdRn)
UREG_FR0: tRegValRn = {UV32_XX, regFprFR00};
UREG_FR1: tRegValRn = {UV32_XX, regFprFR01};
UREG_FR2: tRegValRn = {UV32_XX, regFprFR02};
UREG_FR3: tRegValRn = {UV32_XX, regFprFR03};
UREG_FR4: tRegValRn = {UV32_XX, regFprFR04};
UREG_FR5: tRegValRn = {UV32_XX, regFprFR05};
UREG_FR6: tRegValRn = {UV32_XX, regFprFR06};
UREG_FR7: tRegValRn = {UV32_XX, regFprFR07};
UREG_FR8: tRegValRn = {UV32_XX, regFprFR08};
UREG_FR9: tRegValRn = {UV32_XX, regFprFR09};
UREG_FR10: tRegValRn = {UV32_XX, regFprFR10};
UREG_FR11: tRegValRn = {UV32_XX, regFprFR11};
UREG_FR12: tRegValRn = {UV32_XX, regFprFR12};
UREG_FR13: tRegValRn = {UV32_XX, regFprFR13};
UREG_FR14: tRegValRn = {UV32_XX, regFprFR14};
UREG_FR15: tRegValRn = {UV32_XX, regFprFR15};
UREG_XF0: tRegValRn = {UV32_XX, regFprXF00};
UREG_XF1: tRegValRn = {UV32_XX, regFprXF01};
UREG_XF2: tRegValRn = {UV32_XX, regFprXF02};
UREG_XF3: tRegValRn = {UV32_XX, regFprXF03};
UREG_XF4: tRegValRn = {UV32_XX, regFprXF04};
UREG_XF5: tRegValRn = {UV32_XX, regFprXF05};
UREG_XF6: tRegValRn = {UV32_XX, regFprXF06};
UREG_XF7: tRegValRn = {UV32_XX, regFprXF07};
UREG_XF8: tRegValRn = {UV32_XX, regFprXF08};
UREG_XF9: tRegValRn = {UV32_XX, regFprXF09};
UREG_XF10: tRegValRn = {UV32_XX, regFprXF10};
UREG_XF11: tRegValRn = {UV32_XX, regFprXF11};
UREG_XF12: tRegValRn = {UV32_XX, regFprXF12};
UREG_XF13: tRegValRn = {UV32_XX, regFprXF13};
UREG_XF14: tRegValRn = {UV32_XX, regFprXF14};
UREG_XF15: tRegValRn = {UV32_XX, regFprXF15};
UREG_FPUL: tRegValRn = {UV32_XX, ctlInFpul};
default: begin end
endcase
end
if(regSet64)
begin
case(regIdRo)
UREG_FR0: {nxtRegFprFR00, nxtRegFprFR01} = regValRo;
UREG_FR1: {nxtRegFprXF00, nxtRegFprXF01} = regValRo;
UREG_FR2: {nxtRegFprFR02, nxtRegFprFR03} = regValRo;
UREG_FR3: {nxtRegFprXF02, nxtRegFprXF03} = regValRo;
UREG_FR4: {nxtRegFprFR04, nxtRegFprFR05} = regValRo;
UREG_FR5: {nxtRegFprXF04, nxtRegFprXF05} = regValRo;
UREG_FR6: {nxtRegFprFR06, nxtRegFprFR07} = regValRo;
UREG_FR7: {nxtRegFprXF06, nxtRegFprXF07} = regValRo;
UREG_FR8: {nxtRegFprFR08, nxtRegFprFR09} = regValRo;
UREG_FR9: {nxtRegFprXF08, nxtRegFprXF09} = regValRo;
UREG_FR10: {nxtRegFprFR10, nxtRegFprFR11} = regValRo;
UREG_FR11: {nxtRegFprXF10, nxtRegFprXF11} = regValRo;
UREG_FR12: {nxtRegFprFR12, nxtRegFprFR13} = regValRo;
UREG_FR13: {nxtRegFprXF12, nxtRegFprXF13} = regValRo;
UREG_FR14: {nxtRegFprFR14, nxtRegFprFR15} = regValRo;
UREG_FR15: {nxtRegFprXF14, nxtRegFprXF15} = regValRo;
UREG_FPUL: tFpul = regValRo[31:0];
default: begin end
endcase
end
else
begin
case(regIdRo)
UREG_FR0: nxtRegFprFR00 = regValRo[31:0];
UREG_FR1: nxtRegFprFR01 = regValRo[31:0];
UREG_FR2: nxtRegFprFR02 = regValRo[31:0];
UREG_FR3: nxtRegFprFR03 = regValRo[31:0];
UREG_FR4: nxtRegFprFR04 = regValRo[31:0];
UREG_FR5: nxtRegFprFR05 = regValRo[31:0];
UREG_FR6: nxtRegFprFR06 = regValRo[31:0];
UREG_FR7: nxtRegFprFR07 = regValRo[31:0];
UREG_FR8: nxtRegFprFR08 = regValRo[31:0];
UREG_FR9: nxtRegFprFR09 = regValRo[31:0];
UREG_FR10: nxtRegFprFR10 = regValRo[31:0];
UREG_FR11: nxtRegFprFR11 = regValRo[31:0];
UREG_FR12: nxtRegFprFR12 = regValRo[31:0];
UREG_FR13: nxtRegFprFR13 = regValRo[31:0];
UREG_FR14: nxtRegFprFR14 = regValRo[31:0];
UREG_FR15: nxtRegFprFR15 = regValRo[31:0];
UREG_XF0: nxtRegFprXF00 = regValRo[31:0];
UREG_XF1: nxtRegFprXF01 = regValRo[31:0];
UREG_XF2: nxtRegFprXF02 = regValRo[31:0];
UREG_XF3: nxtRegFprXF03 = regValRo[31:0];
UREG_XF4: nxtRegFprXF04 = regValRo[31:0];
UREG_XF5: nxtRegFprXF05 = regValRo[31:0];
UREG_XF6: nxtRegFprXF06 = regValRo[31:0];
UREG_XF7: nxtRegFprXF07 = regValRo[31:0];
UREG_XF8: nxtRegFprXF08 = regValRo[31:0];
UREG_XF9: nxtRegFprXF09 = regValRo[31:0];
UREG_XF10: nxtRegFprXF10 = regValRo[31:0];
UREG_XF11: nxtRegFprXF11 = regValRo[31:0];
UREG_XF12: nxtRegFprXF12 = regValRo[31:0];
UREG_XF13: nxtRegFprXF13 = regValRo[31:0];
UREG_XF14: nxtRegFprXF14 = regValRo[31:0];
UREG_XF15: nxtRegFprXF15 = regValRo[31:0];
UREG_FPUL: tFpul = regValRo[31:0];
default: begin end
endcase
end
end
always @ (posedge clock)
begin
regFprFR00 <= nxtRegFprFR00;
regFprFR01 <= nxtRegFprFR01;
regFprFR02 <= nxtRegFprFR02;
regFprFR03 <= nxtRegFprFR03;
regFprFR04 <= nxtRegFprFR04;
regFprFR05 <= nxtRegFprFR05;
regFprFR06 <= nxtRegFprFR06;
regFprFR07 <= nxtRegFprFR07;
regFprFR08 <= nxtRegFprFR08;
regFprFR09 <= nxtRegFprFR09;
regFprFR10 <= nxtRegFprFR10;
regFprFR11 <= nxtRegFprFR11;
regFprFR12 <= nxtRegFprFR12;
regFprFR13 <= nxtRegFprFR13;
regFprFR14 <= nxtRegFprFR14;
regFprFR15 <= nxtRegFprFR15;
regFprXF00 <= nxtRegFprXF00;
regFprXF01 <= nxtRegFprXF01;
regFprXF02 <= nxtRegFprXF02;
regFprXF03 <= nxtRegFprXF03;
regFprXF04 <= nxtRegFprXF04;
regFprXF05 <= nxtRegFprXF05;
regFprXF06 <= nxtRegFprXF06;
regFprXF07 <= nxtRegFprXF07;
regFprXF08 <= nxtRegFprXF08;
regFprXF09 <= nxtRegFprXF09;
regFprXF10 <= nxtRegFprXF10;
regFprXF11 <= nxtRegFprXF11;
regFprXF12 <= nxtRegFprXF12;
regFprXF13 <= nxtRegFprXF13;
regFprXF14 <= nxtRegFprXF14;
regFprXF15 <= nxtRegFprXF15;
end
endmodule | 2 |
142,503 | data/full_repos/permissive/99182535/bjx1c32b/RegGPR2.v | 99,182,535 | RegGPR2.v | v | 528 | 72 | [] | [] | [] | null | line:35: before: "parameter" | null | 1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/RegGPR2.v:8: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 314,676 | module | module RegGPR2(
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
regIdRo, regValRo,
regSrVal, regExHold,
idImm,
oregSr, exNextSr2,
oregPr, exNextPr2,
oregPc, exNextPc2,
oregMac, exNextMac2,
oregSp, exNextSp2,
oregGbr, exNextGbr2,
oregVbr, exNextVbr2,
oregSSr, exNextSSr2,
oregSPc, exNextSPc2,
oregSGr, exNextSGr2,
oregFpul, exNextFpul2,
oregFpScr, exNextFpScr2
);
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
output[31:0] regValRs;
output[31:0] regValRt;
output[31:0] regValRn;
input[6:0] regIdRo;
input[31:0] regValRo;
input[31:0] regSrVal;
input regExHold;
input[31:0] idImm;
input[31:0] exNextSr2;
input[31:0] exNextPr2;
input[31:0] exNextPc2;
input[63:0] exNextMac2;
input[31:0] exNextGbr2;
input[31:0] exNextVbr2;
input[31:0] exNextSSr2;
input[31:0] exNextSPc2;
input[31:0] exNextSGr2;
input[31:0] exNextFpul2;
input[31:0] exNextFpScr2;
input[31:0] exNextSp2;
output[63:0] oregMac;
output[31:0] oregPr;
output[31:0] oregSGr;
output[31:0] oregFpul;
output[31:0] oregFpScr;
output[31:0] oregSr;
output[31:0] oregGbr;
output[31:0] oregVbr;
output[31:0] oregSSr;
output[31:0] oregSPc;
output[31:0] oregPc;
output[31:0] oregSp;
reg[63:0] regMac;
reg[31:0] regPr;
reg[31:0] regSGr;
reg[31:0] regFpul;
reg[31:0] regFpScr;
reg[31:0] regSr;
reg[31:0] regGbr;
reg[31:0] regVbr;
reg[31:0] regSSr;
reg[31:0] regSPc;
reg[31:0] regPc;
reg[31:0] regSp;
assign oregMac = regMac;
assign oregPr = regPr;
assign oregSGr = regSGr;
assign oregFpul = regFpul;
assign oregFpScr = regFpScr;
assign oregSr = regSr;
assign oregGbr = regGbr;
assign oregVbr = regVbr;
assign oregSSr = regSSr;
assign oregSPc = regSPc;
assign oregPc = regPc;
assign oregSp = regSp;
reg regSrRB;
reg nxtRegSrRB;
reg[31:0] tRegValRs;
reg[31:0] tRegValRt;
reg[31:0] tRegValRn;
reg[31:0] regGprR0A;
reg[31:0] regGprR1A;
reg[31:0] regGprR2A;
reg[31:0] regGprR3A;
reg[31:0] regGprR4A;
reg[31:0] regGprR5A;
reg[31:0] regGprR6A;
reg[31:0] regGprR7A;
reg[31:0] regGprR0B;
reg[31:0] regGprR1B;
reg[31:0] regGprR2B;
reg[31:0] regGprR3B;
reg[31:0] regGprR4B;
reg[31:0] regGprR5B;
reg[31:0] regGprR6B;
reg[31:0] regGprR7B;
reg[31:0] regGprR8;
reg[31:0] regGprR9;
reg[31:0] regGprR10;
reg[31:0] regGprR11;
reg[31:0] regGprR12;
reg[31:0] regGprR13;
reg[31:0] regGprR14;
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRn = tRegValRn;
always @*
begin
tRegValRs=UV32_XX;
tRegValRt=UV32_XX;
tRegValRn=UV32_XX;
nxtRegSrRB=regSrVal[29];
case(regIdRs)
UREG_R8: tRegValRs=regGprR8;
UREG_R9: tRegValRs=regGprR9;
UREG_R10: tRegValRs=regGprR10;
UREG_R11: tRegValRs=regGprR11;
UREG_R12: tRegValRs=regGprR12;
UREG_R13: tRegValRs=regGprR13;
UREG_R14: tRegValRs=regGprR14;
UREG_R15: tRegValRs=regSp;
UREG_MR_IMM: tRegValRs = idImm;
UREG_ZZR: tRegValRs = 0;
UREG_MACH: tRegValRs = regMac[63:32];
UREG_MACL: tRegValRs = regMac[31: 0];
UREG_PR: tRegValRs = regPr;
UREG_SGR: tRegValRs = regSGr;
UREG_FPUL: tRegValRs = regFpul;
UREG_FPSCR: tRegValRs = regFpScr;
UREG_SR: tRegValRs = regSr;
UREG_GBR: tRegValRs = regGbr;
UREG_VBR: tRegValRs = regVbr;
UREG_SSR: tRegValRs = regSSr;
UREG_SPC: tRegValRs = regSPc;
UREG_PC: tRegValRs = regPc;
default: tRegValRs=UV32_XX;
endcase
case(regIdRt)
UREG_R0: tRegValRt=regGprR0A;
UREG_R1: tRegValRt=regGprR1A;
UREG_R2: tRegValRt=regGprR2A;
UREG_R3: tRegValRt=regGprR3A;
UREG_R4: tRegValRt=regGprR4A;
UREG_R5: tRegValRt=regGprR5A;
UREG_R6: tRegValRt=regGprR6A;
UREG_R7: tRegValRt=regGprR7A;
UREG_R8: tRegValRt=regGprR8;
UREG_R9: tRegValRt=regGprR9;
UREG_R10: tRegValRt=regGprR10;
UREG_R11: tRegValRt=regGprR11;
UREG_R12: tRegValRt=regGprR12;
UREG_R13: tRegValRt=regGprR13;
UREG_R14: tRegValRt=regGprR14;
UREG_R15: tRegValRt=regSp;
UREG_MR_IMM: tRegValRt = idImm;
UREG_ZZR: tRegValRt = 0;
default: tRegValRt=UV32_XX;
endcase
case(regIdRn)
UREG_R0: tRegValRn=regGprR0A;
UREG_R1: tRegValRn=regGprR1A;
UREG_R2: tRegValRn=regGprR2A;
UREG_R3: tRegValRn=regGprR3A;
UREG_R4: tRegValRn=regGprR4A;
UREG_R5: tRegValRn=regGprR5A;
UREG_R6: tRegValRn=regGprR6A;
UREG_R7: tRegValRn=regGprR7A;
UREG_R8: tRegValRn=regGprR8;
UREG_R9: tRegValRn=regGprR9;
UREG_R10: tRegValRn=regGprR10;
UREG_R11: tRegValRn=regGprR11;
UREG_R12: tRegValRn=regGprR12;
UREG_R13: tRegValRn=regGprR13;
UREG_R14: tRegValRn=regGprR14;
UREG_R15: tRegValRn=regSp;
UREG_GBR: tRegValRn = regGbr;
default: tRegValRn=UV32_XX;
endcase
end
always @ (posedge clock)
begin
regSrRB <= nxtRegSrRB;
if(regSrRB^nxtRegSrRB)
begin
regGprR0A <= regGprR0B;
regGprR1A <= regGprR1B;
regGprR2A <= regGprR2B;
regGprR3A <= regGprR3B;
regGprR4A <= regGprR4B;
regGprR5A <= regGprR5B;
regGprR6A <= regGprR6B;
regGprR7A <= regGprR7B;
regGprR0B <= regGprR0A;
regGprR1B <= regGprR1A;
regGprR2B <= regGprR2A;
regGprR3B <= regGprR3A;
regGprR4B <= regGprR4A;
regGprR5B <= regGprR5A;
regGprR6B <= regGprR6A;
regGprR7B <= regGprR7A;
end
else
begin
regGprR0A <= (regIdRo==UREG_R0) ? regValRo : regGprR0A;
regGprR1A <= (regIdRo==UREG_R1) ? regValRo : regGprR1A;
regGprR2A <= (regIdRo==UREG_R2) ? regValRo : regGprR2A;
regGprR3A <= (regIdRo==UREG_R3) ? regValRo : regGprR3A;
regGprR4A <= (regIdRo==UREG_R4) ? regValRo : regGprR4A;
regGprR5A <= (regIdRo==UREG_R5) ? regValRo : regGprR5A;
regGprR6A <= (regIdRo==UREG_R6) ? regValRo : regGprR6A;
regGprR7A <= (regIdRo==UREG_R7) ? regValRo : regGprR7A;
regGprR0B <= (regIdRo==UREG_R0B) ? regValRo : regGprR0B;
regGprR1B <= (regIdRo==UREG_R1B) ? regValRo : regGprR1B;
regGprR2B <= (regIdRo==UREG_R2B) ? regValRo : regGprR2B;
regGprR3B <= (regIdRo==UREG_R3B) ? regValRo : regGprR3B;
regGprR4B <= (regIdRo==UREG_R4B) ? regValRo : regGprR4B;
regGprR5B <= (regIdRo==UREG_R5B) ? regValRo : regGprR5B;
regGprR6B <= (regIdRo==UREG_R6B) ? regValRo : regGprR6B;
regGprR7B <= (regIdRo==UREG_R7B) ? regValRo : regGprR7B;
end
regGprR8 <= (regIdRo==UREG_R8 ) ? regValRo : regGprR8 ;
regGprR9 <= (regIdRo==UREG_R9 ) ? regValRo : regGprR9 ;
regGprR10 <= (regIdRo==UREG_R10) ? regValRo : regGprR10;
regGprR11 <= (regIdRo==UREG_R11) ? regValRo : regGprR11;
regGprR12 <= (regIdRo==UREG_R12) ? regValRo : regGprR12;
regGprR13 <= (regIdRo==UREG_R13) ? regValRo : regGprR13;
regGprR14 <= (regIdRo==UREG_R14) ? regValRo : regGprR14;
if(reset)
begin
regSr <= 0;
regPr <= 0;
regPc <= 32'hA000_0000;
regMac <= 0;
regSp <= 0;
regGbr <= 0;
regVbr <= 0;
regSSr <= 0;
regSPc <= 0;
regSGr <= 0;
regFpul <= 0;
regFpScr <= 0;
end
else
if(!regExHold)
begin
end
end
endmodule | module RegGPR2(
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
regIdRo, regValRo,
regSrVal, regExHold,
idImm,
oregSr, exNextSr2,
oregPr, exNextPr2,
oregPc, exNextPc2,
oregMac, exNextMac2,
oregSp, exNextSp2,
oregGbr, exNextGbr2,
oregVbr, exNextVbr2,
oregSSr, exNextSSr2,
oregSPc, exNextSPc2,
oregSGr, exNextSGr2,
oregFpul, exNextFpul2,
oregFpScr, exNextFpScr2
); |
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
output[31:0] regValRs;
output[31:0] regValRt;
output[31:0] regValRn;
input[6:0] regIdRo;
input[31:0] regValRo;
input[31:0] regSrVal;
input regExHold;
input[31:0] idImm;
input[31:0] exNextSr2;
input[31:0] exNextPr2;
input[31:0] exNextPc2;
input[63:0] exNextMac2;
input[31:0] exNextGbr2;
input[31:0] exNextVbr2;
input[31:0] exNextSSr2;
input[31:0] exNextSPc2;
input[31:0] exNextSGr2;
input[31:0] exNextFpul2;
input[31:0] exNextFpScr2;
input[31:0] exNextSp2;
output[63:0] oregMac;
output[31:0] oregPr;
output[31:0] oregSGr;
output[31:0] oregFpul;
output[31:0] oregFpScr;
output[31:0] oregSr;
output[31:0] oregGbr;
output[31:0] oregVbr;
output[31:0] oregSSr;
output[31:0] oregSPc;
output[31:0] oregPc;
output[31:0] oregSp;
reg[63:0] regMac;
reg[31:0] regPr;
reg[31:0] regSGr;
reg[31:0] regFpul;
reg[31:0] regFpScr;
reg[31:0] regSr;
reg[31:0] regGbr;
reg[31:0] regVbr;
reg[31:0] regSSr;
reg[31:0] regSPc;
reg[31:0] regPc;
reg[31:0] regSp;
assign oregMac = regMac;
assign oregPr = regPr;
assign oregSGr = regSGr;
assign oregFpul = regFpul;
assign oregFpScr = regFpScr;
assign oregSr = regSr;
assign oregGbr = regGbr;
assign oregVbr = regVbr;
assign oregSSr = regSSr;
assign oregSPc = regSPc;
assign oregPc = regPc;
assign oregSp = regSp;
reg regSrRB;
reg nxtRegSrRB;
reg[31:0] tRegValRs;
reg[31:0] tRegValRt;
reg[31:0] tRegValRn;
reg[31:0] regGprR0A;
reg[31:0] regGprR1A;
reg[31:0] regGprR2A;
reg[31:0] regGprR3A;
reg[31:0] regGprR4A;
reg[31:0] regGprR5A;
reg[31:0] regGprR6A;
reg[31:0] regGprR7A;
reg[31:0] regGprR0B;
reg[31:0] regGprR1B;
reg[31:0] regGprR2B;
reg[31:0] regGprR3B;
reg[31:0] regGprR4B;
reg[31:0] regGprR5B;
reg[31:0] regGprR6B;
reg[31:0] regGprR7B;
reg[31:0] regGprR8;
reg[31:0] regGprR9;
reg[31:0] regGprR10;
reg[31:0] regGprR11;
reg[31:0] regGprR12;
reg[31:0] regGprR13;
reg[31:0] regGprR14;
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRn = tRegValRn;
always @*
begin
tRegValRs=UV32_XX;
tRegValRt=UV32_XX;
tRegValRn=UV32_XX;
nxtRegSrRB=regSrVal[29];
case(regIdRs)
UREG_R8: tRegValRs=regGprR8;
UREG_R9: tRegValRs=regGprR9;
UREG_R10: tRegValRs=regGprR10;
UREG_R11: tRegValRs=regGprR11;
UREG_R12: tRegValRs=regGprR12;
UREG_R13: tRegValRs=regGprR13;
UREG_R14: tRegValRs=regGprR14;
UREG_R15: tRegValRs=regSp;
UREG_MR_IMM: tRegValRs = idImm;
UREG_ZZR: tRegValRs = 0;
UREG_MACH: tRegValRs = regMac[63:32];
UREG_MACL: tRegValRs = regMac[31: 0];
UREG_PR: tRegValRs = regPr;
UREG_SGR: tRegValRs = regSGr;
UREG_FPUL: tRegValRs = regFpul;
UREG_FPSCR: tRegValRs = regFpScr;
UREG_SR: tRegValRs = regSr;
UREG_GBR: tRegValRs = regGbr;
UREG_VBR: tRegValRs = regVbr;
UREG_SSR: tRegValRs = regSSr;
UREG_SPC: tRegValRs = regSPc;
UREG_PC: tRegValRs = regPc;
default: tRegValRs=UV32_XX;
endcase
case(regIdRt)
UREG_R0: tRegValRt=regGprR0A;
UREG_R1: tRegValRt=regGprR1A;
UREG_R2: tRegValRt=regGprR2A;
UREG_R3: tRegValRt=regGprR3A;
UREG_R4: tRegValRt=regGprR4A;
UREG_R5: tRegValRt=regGprR5A;
UREG_R6: tRegValRt=regGprR6A;
UREG_R7: tRegValRt=regGprR7A;
UREG_R8: tRegValRt=regGprR8;
UREG_R9: tRegValRt=regGprR9;
UREG_R10: tRegValRt=regGprR10;
UREG_R11: tRegValRt=regGprR11;
UREG_R12: tRegValRt=regGprR12;
UREG_R13: tRegValRt=regGprR13;
UREG_R14: tRegValRt=regGprR14;
UREG_R15: tRegValRt=regSp;
UREG_MR_IMM: tRegValRt = idImm;
UREG_ZZR: tRegValRt = 0;
default: tRegValRt=UV32_XX;
endcase
case(regIdRn)
UREG_R0: tRegValRn=regGprR0A;
UREG_R1: tRegValRn=regGprR1A;
UREG_R2: tRegValRn=regGprR2A;
UREG_R3: tRegValRn=regGprR3A;
UREG_R4: tRegValRn=regGprR4A;
UREG_R5: tRegValRn=regGprR5A;
UREG_R6: tRegValRn=regGprR6A;
UREG_R7: tRegValRn=regGprR7A;
UREG_R8: tRegValRn=regGprR8;
UREG_R9: tRegValRn=regGprR9;
UREG_R10: tRegValRn=regGprR10;
UREG_R11: tRegValRn=regGprR11;
UREG_R12: tRegValRn=regGprR12;
UREG_R13: tRegValRn=regGprR13;
UREG_R14: tRegValRn=regGprR14;
UREG_R15: tRegValRn=regSp;
UREG_GBR: tRegValRn = regGbr;
default: tRegValRn=UV32_XX;
endcase
end
always @ (posedge clock)
begin
regSrRB <= nxtRegSrRB;
if(regSrRB^nxtRegSrRB)
begin
regGprR0A <= regGprR0B;
regGprR1A <= regGprR1B;
regGprR2A <= regGprR2B;
regGprR3A <= regGprR3B;
regGprR4A <= regGprR4B;
regGprR5A <= regGprR5B;
regGprR6A <= regGprR6B;
regGprR7A <= regGprR7B;
regGprR0B <= regGprR0A;
regGprR1B <= regGprR1A;
regGprR2B <= regGprR2A;
regGprR3B <= regGprR3A;
regGprR4B <= regGprR4A;
regGprR5B <= regGprR5A;
regGprR6B <= regGprR6A;
regGprR7B <= regGprR7A;
end
else
begin
regGprR0A <= (regIdRo==UREG_R0) ? regValRo : regGprR0A;
regGprR1A <= (regIdRo==UREG_R1) ? regValRo : regGprR1A;
regGprR2A <= (regIdRo==UREG_R2) ? regValRo : regGprR2A;
regGprR3A <= (regIdRo==UREG_R3) ? regValRo : regGprR3A;
regGprR4A <= (regIdRo==UREG_R4) ? regValRo : regGprR4A;
regGprR5A <= (regIdRo==UREG_R5) ? regValRo : regGprR5A;
regGprR6A <= (regIdRo==UREG_R6) ? regValRo : regGprR6A;
regGprR7A <= (regIdRo==UREG_R7) ? regValRo : regGprR7A;
regGprR0B <= (regIdRo==UREG_R0B) ? regValRo : regGprR0B;
regGprR1B <= (regIdRo==UREG_R1B) ? regValRo : regGprR1B;
regGprR2B <= (regIdRo==UREG_R2B) ? regValRo : regGprR2B;
regGprR3B <= (regIdRo==UREG_R3B) ? regValRo : regGprR3B;
regGprR4B <= (regIdRo==UREG_R4B) ? regValRo : regGprR4B;
regGprR5B <= (regIdRo==UREG_R5B) ? regValRo : regGprR5B;
regGprR6B <= (regIdRo==UREG_R6B) ? regValRo : regGprR6B;
regGprR7B <= (regIdRo==UREG_R7B) ? regValRo : regGprR7B;
end
regGprR8 <= (regIdRo==UREG_R8 ) ? regValRo : regGprR8 ;
regGprR9 <= (regIdRo==UREG_R9 ) ? regValRo : regGprR9 ;
regGprR10 <= (regIdRo==UREG_R10) ? regValRo : regGprR10;
regGprR11 <= (regIdRo==UREG_R11) ? regValRo : regGprR11;
regGprR12 <= (regIdRo==UREG_R12) ? regValRo : regGprR12;
regGprR13 <= (regIdRo==UREG_R13) ? regValRo : regGprR13;
regGprR14 <= (regIdRo==UREG_R14) ? regValRo : regGprR14;
if(reset)
begin
regSr <= 0;
regPr <= 0;
regPc <= 32'hA000_0000;
regMac <= 0;
regSp <= 0;
regGbr <= 0;
regVbr <= 0;
regSSr <= 0;
regSPc <= 0;
regSGr <= 0;
regFpul <= 0;
regFpScr <= 0;
end
else
if(!regExHold)
begin
end
end
endmodule | 2 |
142,505 | data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v | 99,182,535 | ExUnit.v | v | 650 | 73 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:5: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b1,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b1,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b1,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:6: Cannot find include file: Dc2Tile.v\n`include "Dc2Tile.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:7: Cannot find include file: DcTile3.v\n`include "DcTile3.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:8: Cannot find include file: IcTile2.v\n`include "IcTile2.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:10: Cannot find include file: RegGPR3.v\n`include "RegGPR3.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:12: Cannot find include file: DecOp4.v\n`include "DecOp4.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b1/ExUnit.v:14: Cannot find include file: ExOp2.v\n`include "ExOp2.v" \n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 314,694 | module | module ExUnit(
clock, reset,
extAddr, extData,
extOE, extWR,
extOK,
mmioAddr, mmioData,
mmioOE, mmioWR,
mmioOK
);
input clock;
input reset;
output[31:0] extAddr;
inout[127:0] extData;
output extOE;
output extWR;
input extOK;
output[31:0] mmioAddr;
inout[31:0] mmioData;
output mmioOE;
output mmioWR;
input[1:0] mmioOK;
assign extAddr = 32'hZ;
assign extData = 128'hZ;
assign extOE = 0;
assign extWR = 0;
assign mmioAddr = dc2MmioAddr;
assign mmioData = dc2MmioWR ? dc2MmioOutData : 32'hZ;
assign mmioOE = dc2MmioOE;
assign mmioWR = dc2MmioWR;
assign dc2MmioOK = mmioOK;
wire[31:0] regMach;
wire[31:0] regMacl;
wire[31:0] regPr;
wire[31:0] regSGr;
wire[31:0] regFpul;
wire[31:0] regFpScr;
wire[31:0] regSr;
wire[31:0] regGbr;
wire[31:0] regVbr;
wire[31:0] regSSr;
wire[31:0] regSPc;
wire[31:0] regPc;
wire[31:0] regSp;
reg[7:0] regRstTok;
reg[7:0] regNextRstTok;
reg[31:0] dc2RegInAddr;
reg[127:0] dc2RegInData;
wire[127:0] dc2RegOutData;
wire[1:0] dc2RegOutOK;
reg dc2RegInOE;
reg dc2RegInWR;
reg[4:0] dc2RegInOp;
reg[127:0] dc2MemInData;
wire[127:0] dc2MemOutData;
wire[31:0] dc2MemAddr;
wire dc2MemOE;
wire dc2MemWR;
reg[1:0] dc2MemOK;
reg[31:0] dc2MmioInData;
wire[31:0] dc2MmioOutData;
wire[31:0] dc2MmioAddr;
wire dc2MmioOE;
wire dc2MmioWR;
wire[1:0] dc2MmioOK;
Dc2Tile dcl2(
clock, reset,
dc2RegInAddr, dc2RegInData,
dc2RegOutData, dc2RegOutOK,
dc2RegInOE, dc2RegInWR,
dc2RegInOp,
dc2MemInData, dc2MemOutData, dc2MemAddr,
dc2MemOE, dc2MemWR, dc2MemOK,
dc2MmioInData, dc2MmioOutData, dc2MmioAddr,
dc2MmioOE, dc2MmioWR, dc2MmioOK
);
reg[31:0] dcfRegInAddr;
reg[63:0] dcfRegInData;
wire[63:0] dcfRegOutData;
wire[1:0] dcfRegOutOK;
reg dcfRegInOE;
reg dcfRegInWR;
reg[4:0] dcfRegInOp;
reg[127:0] dcfMemInData;
wire[127:0] dcfMemOutData;
wire[31:0] dcfMemPcAddr;
wire dcfMemPcOE;
wire dcfMemPcWR;
reg[1:0] dcfMemPcOK;
wire[4:0] dcfMemOp;
DcTile3 dcf(
clock, reset,
dcfRegInData, dcfRegOutData,
dcfRegInAddr, dcfRegOutOK,
dcfRegInOE, dcfRegInWR,
dcfRegInOp,
dcfMemInData, dcfMemOutData,
dcfMemPcAddr, dcfMemPcOK,
dcfMemPcOE, dcfMemPcWR,
dcfMemOp
);
reg[31:0] ifValPc;
reg[31:0] ifValSr;
wire[47:0] regIfPcVal;
wire[1:0] regIfPcOK;
reg[127:0] memIfPcData;
wire[31:0] memIfPcAddr;
wire memIfPcOE;
reg[1:0] memIfPcOK;
IcTile2 icf(clock, reset,
ifValPc,
regIfPcVal, regIfPcOK,
memIfPcData,
memIfPcAddr, memIfPcOE, memIfPcOK);
reg[47:0] regIfPcVal2;
reg[47:0] regIdPcVal;
reg[15:0] regIdCsFl;
reg[31:0] idValPc;
reg[31:0] idValSr;
wire[6:0] idRegN;
wire[6:0] idRegS;
wire[6:0] idRegT;
wire[31:0] idImm;
wire[3:0] idStepPc;
wire[3:0] idStepPc2;
wire[7:0] idUCmd;
reg[6:0] idWbRegO;
reg[63:0] idWbRegValO;
reg[6:0] wbRegO;
reg[63:0] wbRegValO;
DecOp4 dec(
clock, regIdPcVal[47:0], regIdCsFl,
idRegN, idRegS, idRegT, idImm,
idStepPc, idStepPc2, idUCmd);
reg[31:0] id2ValPc;
reg[31:0] id2ValSr;
wire[31:0] id2ValPrPc;
assign id2ValPrPc = id2ValPc + {28'h0, id2StepPc} + 2;
reg[47:0] regId2PcVal;
reg[15:0] regId2CsFl;
reg[6:0] id2RegN;
reg[6:0] id2RegS;
reg[6:0] id2RegT;
reg[31:0] id2Imm;
reg[3:0] id2StepPc;
reg[3:0] id2StepPc2;
reg[7:0] id2UCmd;
wire[63:0] id2RegValN;
wire[63:0] id2RegValS;
wire[63:0] id2RegValT;
reg[1:0] id2RegFpLdMode;
reg[1:0] idWbRegFpStMode;
RegGPR3 gpr(
clock, reset || (regRstTok != 8'h55),
id2RegS, id2RegValS,
id2RegT, id2RegValT,
id2RegN, id2RegValN,
idWbRegO, idWbRegValO,
id2ValSr, tRegExHold,
id2Imm, id2ValPrPc,
id2RegFpLdMode,
idWbRegFpStMode,
regSr, exNextSr2,
regPr, exNextPr2,
regPc, exNextPc2,
regMach, exNextMach2,
regMacl, exNextMacl2,
regSp, exNextSp2,
regGbr, exNextGbr2,
regVbr, exNextVbr2,
regSSr, exNextSSr2,
regSPc, exNextSPc2,
regSGr, exNextSGr2,
regFpul, exNextFpul2,
regFpScr, exNextFpScr2
);
reg[7:0] id2UCmd2;
reg[63:0] id2RegValN2;
reg[63:0] id2RegValS2;
reg[63:0] id2RegValT2;
reg[47:0] regExPcVal;
reg[15:0] regExCsFl;
reg[31:0] regExPc;
reg[31:0] regExSr;
reg[6:0] exRegN;
reg[6:0] exRegS;
reg[6:0] exRegT;
reg[31:0] exImm;
reg[3:0] exStepPc;
reg[3:0] exStepPc2;
reg[7:0] exUCmd;
reg[63:0] exRegValN;
reg[63:0] exRegValS;
reg[63:0] exRegValT;
wire[6:0] exRegO;
wire[63:0] exRegValO;
wire[1:0] exRegOutOK;
wire[1:0] exRegOutStMode;
wire[31:0] exMemAddr;
wire[63:0] exMemData;
wire exMemLoad;
wire exMemStore;
wire[4:0] exMemOpMode;
wire[7:0] exMemOpCmd2;
wire[31:0] exNextSr;
wire[31:0] exNextPr;
wire[31:0] exNextPc;
wire[31:0] exNextMach;
wire[31:0] exNextMacl;
wire[31:0] exNextGbr;
wire[31:0] exNextVbr;
wire[31:0] exNextSSr;
wire[31:0] exNextSPc;
wire[31:0] exNextSGr;
wire[31:0] exNextSp;
wire[31:0] exNextFpul;
wire[31:0] exNextFpScr;
ExOp2 exOp(clock, reset,
exUCmd, exStepPc,
exRegS, exRegValS,
exRegT, exRegValT,
exRegN, exRegValN,
exImm, tRegGenIdPc,
exRegO, exRegValO,
exRegOutOK, exRegOutStMode,
exMemAddr, exMemData,
exMemLoad, exMemStore,
exMemOpMode, exMemOpCmd2,
regSr, exNextSr,
regPr, exNextPr,
regExPc, exNextPc,
regMach, exNextMach,
regMacl, exNextMacl,
regSp, exNextSp,
regFpul, exNextFpul,
regFpScr, exNextFpScr,
regGbr, exNextGbr,
regVbr, exNextVbr,
regSSr, exNextSSr,
regSPc, exNextSPc,
regSGr, exNextSGr
);
reg[31:0] exNextSr2;
reg[31:0] exNextPr2;
reg[31:0] exNextPc2;
reg[31:0] exNextMach2;
reg[31:0] exNextMacl2;
reg[31:0] exNextGbr2;
reg[31:0] exNextVbr2;
reg[31:0] exNextSSr2;
reg[31:0] exNextSPc2;
reg[31:0] exNextSGr2;
reg[31:0] exNextFpul2;
reg[31:0] exNextFpScr2;
reg[31:0] exNextSp2;
reg[31:0] tRegGenIdPc;
reg[31:0] tRegGenIdPr;
reg[15:0] tRegGenIdOpw;
reg[3:0] tRegGenIdStepPc;
reg tRegExHold;
always @*
begin
regIdCsFl=0;
regIdCsFl[0]=1;
regIdCsFl[1]=regFpScr[19];
regIdCsFl[2]=regFpScr[20];
regIdCsFl[3]=regFpScr[21];
regIdCsFl[4]=regFpScr[24];
regIdCsFl[5]=regSr[31];
regIdCsFl[6]=regSr[12];
regNextRstTok=8'h55;
if(reset)
regNextRstTok=8'h00;
tRegGenIdStepPc=exStepPc2;
tRegExHold = 0;
if(regIfPcOK!=UMEM_OK_OK)
tRegExHold = 1;
if(exMemLoad||exMemStore)
begin
if(dcfRegOutOK!=UMEM_OK_OK)
tRegExHold = 1;
end
if(exRegOutOK==UMEM_OK_HOLD)
tRegExHold = 1;
dc2MemInData = 0;
dc2MemOK = UMEM_OK_READY;
dc2MmioInData = 0;
id2RegFpLdMode = 0;
idWbRegFpStMode = exRegOutStMode;
if(regFpScr[19])
id2RegFpLdMode = 1;
if(regFpScr[20])
id2RegFpLdMode = 1;
id2UCmd2 = id2UCmd;
case(exUCmd)
UCMD_BRAN: id2UCmd2 = UCMD_NONE;
UCMD_BSRN: id2UCmd2 = UCMD_NONE;
UCMD_BT: id2UCmd2 = UCMD_NONE;
UCMD_BF: id2UCmd2 = UCMD_NONE;
UCMD_RTSN: id2UCmd2 = UCMD_NONE;
UCMD_RTEN: id2UCmd2 = UCMD_NONE;
default: begin end
endcase
tRegGenIdPc = ifValPc + {28'h0, tRegGenIdStepPc};
tRegGenIdPr = ifValPc + 32'h4;
id2RegValN2 = id2RegValN;
id2RegValS2 = id2RegValS;
id2RegValT2 = id2RegValT;
wbRegO = exRegO;
wbRegValO = exRegValO;
if(id2RegS == wbRegO)
id2RegValS2 = wbRegValO;
if(id2RegT == wbRegO)
id2RegValT2 = wbRegValO;
if(id2RegN == wbRegO)
id2RegValN2 = wbRegValO;
exNextSr2 = exNextSr;
exNextPr2 = exNextPr;
exNextPc2 = exNextPc;
exNextMach2 = exNextMach;
exNextMacl2 = exNextMacl;
exNextGbr2 = exNextGbr;
exNextVbr2 = exNextVbr;
exNextSSr2 = exNextSSr;
exNextSPc2 = exNextSPc;
exNextSGr2 = exNextSGr;
regIfPcVal2 = regIfPcVal;
if(exNextPc != tRegGenIdPc)
begin
regIfPcVal2 = 48'h0F09_0F09_0E09;
end
exNextFpul2 = exNextFpul;
exNextFpScr2 = exNextFpScr;
exNextSp2 = exNextSp;
if(regRstTok != 8'h55)
begin
$display("Reset");
exNextPc2 = 32'hA000_0000;
tRegExHold = 1;
end
$display("IF: %X %X", ifValPc, regIfPcVal);
$display("ID: %X %X", idValPc, regIdPcVal);
end
always @ (posedge clock)
begin
regRstTok <= regNextRstTok;
dcfRegInAddr <= exMemAddr;
dcfRegInData <= exMemData;
dcfRegInOE <= exMemLoad;
dcfRegInWR <= exMemStore;
dcfRegInOp <= exMemOpMode;
idWbRegO <= wbRegO;
idWbRegValO <= wbRegValO;
if((exMemLoad||exMemStore) &&
(dcfRegOutOK==UMEM_OK_OK))
begin
idWbRegO <= id2RegN;
idWbRegValO <= dcfRegOutData[63:0];
end
else
begin
idWbRegO <= wbRegO;
idWbRegValO <= wbRegValO;
end
if(memIfPcOE)
begin
$display("ExUnit: memIfPcOE");
dc2RegInAddr <= memIfPcAddr;
dc2RegInData <= 0;
dc2RegInOE <= memIfPcOE;
dc2RegInWR <= 0;
dc2RegInOp <= 1;
memIfPcData <= dc2RegOutData;
memIfPcOK <= dc2RegOutOK;
dcfMemInData <= 128'hX;
if(dcfMemPcOE || dcfMemPcWR)
dcfMemPcOK <= UMEM_OK_HOLD;
else
dcfMemPcOK <= UMEM_OK_READY;
end
else
if(dcfMemPcOE || dcfMemPcWR)
begin
dc2RegInAddr <= dcfMemPcAddr;
dc2RegInData <= dcfMemOutData;
dc2RegInOE <= dcfMemPcOE;
dc2RegInWR <= dcfMemPcWR;
dc2RegInOp <= dcfMemOp;
dcfMemInData <= dc2RegOutData;
dcfMemPcOK <= dc2RegOutOK;
memIfPcData <= 128'hX;
if(memIfPcOE)
memIfPcOK <= UMEM_OK_HOLD;
else
memIfPcOK <= UMEM_OK_READY;
end
else
begin
dc2RegInAddr <= 0;
dc2RegInData <= 0;
dc2RegInOE <= 0;
dc2RegInWR <= 0;
dc2RegInOp <= 1;
end
if(regRstTok != 8'h55)
begin
ifValPc <= 32'hA000_0000;
ifValSr <= 0;
idValPc <= 32'hA000_0000;
idValSr <= 0;
regIdPcVal <= 0;
regExPcVal <= 0;
regExCsFl <= 0;
regExPc <= 32'hA000_0000;
regExSr <= 0;
exStepPc <= 0;
exStepPc2 <= 0;
end
else
if(!tRegExHold)
begin
$display("Step");
ifValPc <= exNextPc2;
ifValSr <= exNextSr2;
idValPc <= ifValPc;
idValSr <= ifValSr;
regIdPcVal <= regIfPcVal2;
id2ValPc <= idValPc;
id2ValSr <= idValSr;
regId2PcVal <= regIdPcVal;
regId2CsFl <= regIdCsFl;
id2RegN <= idRegN;
id2RegS <= idRegS;
id2RegT <= idRegT;
id2Imm <= idImm;
id2StepPc <= idStepPc;
id2StepPc2 <= idStepPc2;
id2UCmd <= idUCmd;
regExPcVal <= regId2PcVal;
regExCsFl <= regId2CsFl;
regExPc <= id2ValPc;
regExSr <= id2ValSr;
exRegN <= id2RegN;
exRegS <= id2RegS;
exRegT <= id2RegT;
exImm <= id2Imm;
exStepPc <= id2StepPc;
exStepPc2 <= id2StepPc2;
exUCmd <= id2UCmd2;
exRegValN <= id2RegValN2;
exRegValS <= id2RegValS2;
exRegValT <= id2RegValT2;
end
else
begin
$display("Hold");
end
end
endmodule | module ExUnit(
clock, reset,
extAddr, extData,
extOE, extWR,
extOK,
mmioAddr, mmioData,
mmioOE, mmioWR,
mmioOK
); |
input clock;
input reset;
output[31:0] extAddr;
inout[127:0] extData;
output extOE;
output extWR;
input extOK;
output[31:0] mmioAddr;
inout[31:0] mmioData;
output mmioOE;
output mmioWR;
input[1:0] mmioOK;
assign extAddr = 32'hZ;
assign extData = 128'hZ;
assign extOE = 0;
assign extWR = 0;
assign mmioAddr = dc2MmioAddr;
assign mmioData = dc2MmioWR ? dc2MmioOutData : 32'hZ;
assign mmioOE = dc2MmioOE;
assign mmioWR = dc2MmioWR;
assign dc2MmioOK = mmioOK;
wire[31:0] regMach;
wire[31:0] regMacl;
wire[31:0] regPr;
wire[31:0] regSGr;
wire[31:0] regFpul;
wire[31:0] regFpScr;
wire[31:0] regSr;
wire[31:0] regGbr;
wire[31:0] regVbr;
wire[31:0] regSSr;
wire[31:0] regSPc;
wire[31:0] regPc;
wire[31:0] regSp;
reg[7:0] regRstTok;
reg[7:0] regNextRstTok;
reg[31:0] dc2RegInAddr;
reg[127:0] dc2RegInData;
wire[127:0] dc2RegOutData;
wire[1:0] dc2RegOutOK;
reg dc2RegInOE;
reg dc2RegInWR;
reg[4:0] dc2RegInOp;
reg[127:0] dc2MemInData;
wire[127:0] dc2MemOutData;
wire[31:0] dc2MemAddr;
wire dc2MemOE;
wire dc2MemWR;
reg[1:0] dc2MemOK;
reg[31:0] dc2MmioInData;
wire[31:0] dc2MmioOutData;
wire[31:0] dc2MmioAddr;
wire dc2MmioOE;
wire dc2MmioWR;
wire[1:0] dc2MmioOK;
Dc2Tile dcl2(
clock, reset,
dc2RegInAddr, dc2RegInData,
dc2RegOutData, dc2RegOutOK,
dc2RegInOE, dc2RegInWR,
dc2RegInOp,
dc2MemInData, dc2MemOutData, dc2MemAddr,
dc2MemOE, dc2MemWR, dc2MemOK,
dc2MmioInData, dc2MmioOutData, dc2MmioAddr,
dc2MmioOE, dc2MmioWR, dc2MmioOK
);
reg[31:0] dcfRegInAddr;
reg[63:0] dcfRegInData;
wire[63:0] dcfRegOutData;
wire[1:0] dcfRegOutOK;
reg dcfRegInOE;
reg dcfRegInWR;
reg[4:0] dcfRegInOp;
reg[127:0] dcfMemInData;
wire[127:0] dcfMemOutData;
wire[31:0] dcfMemPcAddr;
wire dcfMemPcOE;
wire dcfMemPcWR;
reg[1:0] dcfMemPcOK;
wire[4:0] dcfMemOp;
DcTile3 dcf(
clock, reset,
dcfRegInData, dcfRegOutData,
dcfRegInAddr, dcfRegOutOK,
dcfRegInOE, dcfRegInWR,
dcfRegInOp,
dcfMemInData, dcfMemOutData,
dcfMemPcAddr, dcfMemPcOK,
dcfMemPcOE, dcfMemPcWR,
dcfMemOp
);
reg[31:0] ifValPc;
reg[31:0] ifValSr;
wire[47:0] regIfPcVal;
wire[1:0] regIfPcOK;
reg[127:0] memIfPcData;
wire[31:0] memIfPcAddr;
wire memIfPcOE;
reg[1:0] memIfPcOK;
IcTile2 icf(clock, reset,
ifValPc,
regIfPcVal, regIfPcOK,
memIfPcData,
memIfPcAddr, memIfPcOE, memIfPcOK);
reg[47:0] regIfPcVal2;
reg[47:0] regIdPcVal;
reg[15:0] regIdCsFl;
reg[31:0] idValPc;
reg[31:0] idValSr;
wire[6:0] idRegN;
wire[6:0] idRegS;
wire[6:0] idRegT;
wire[31:0] idImm;
wire[3:0] idStepPc;
wire[3:0] idStepPc2;
wire[7:0] idUCmd;
reg[6:0] idWbRegO;
reg[63:0] idWbRegValO;
reg[6:0] wbRegO;
reg[63:0] wbRegValO;
DecOp4 dec(
clock, regIdPcVal[47:0], regIdCsFl,
idRegN, idRegS, idRegT, idImm,
idStepPc, idStepPc2, idUCmd);
reg[31:0] id2ValPc;
reg[31:0] id2ValSr;
wire[31:0] id2ValPrPc;
assign id2ValPrPc = id2ValPc + {28'h0, id2StepPc} + 2;
reg[47:0] regId2PcVal;
reg[15:0] regId2CsFl;
reg[6:0] id2RegN;
reg[6:0] id2RegS;
reg[6:0] id2RegT;
reg[31:0] id2Imm;
reg[3:0] id2StepPc;
reg[3:0] id2StepPc2;
reg[7:0] id2UCmd;
wire[63:0] id2RegValN;
wire[63:0] id2RegValS;
wire[63:0] id2RegValT;
reg[1:0] id2RegFpLdMode;
reg[1:0] idWbRegFpStMode;
RegGPR3 gpr(
clock, reset || (regRstTok != 8'h55),
id2RegS, id2RegValS,
id2RegT, id2RegValT,
id2RegN, id2RegValN,
idWbRegO, idWbRegValO,
id2ValSr, tRegExHold,
id2Imm, id2ValPrPc,
id2RegFpLdMode,
idWbRegFpStMode,
regSr, exNextSr2,
regPr, exNextPr2,
regPc, exNextPc2,
regMach, exNextMach2,
regMacl, exNextMacl2,
regSp, exNextSp2,
regGbr, exNextGbr2,
regVbr, exNextVbr2,
regSSr, exNextSSr2,
regSPc, exNextSPc2,
regSGr, exNextSGr2,
regFpul, exNextFpul2,
regFpScr, exNextFpScr2
);
reg[7:0] id2UCmd2;
reg[63:0] id2RegValN2;
reg[63:0] id2RegValS2;
reg[63:0] id2RegValT2;
reg[47:0] regExPcVal;
reg[15:0] regExCsFl;
reg[31:0] regExPc;
reg[31:0] regExSr;
reg[6:0] exRegN;
reg[6:0] exRegS;
reg[6:0] exRegT;
reg[31:0] exImm;
reg[3:0] exStepPc;
reg[3:0] exStepPc2;
reg[7:0] exUCmd;
reg[63:0] exRegValN;
reg[63:0] exRegValS;
reg[63:0] exRegValT;
wire[6:0] exRegO;
wire[63:0] exRegValO;
wire[1:0] exRegOutOK;
wire[1:0] exRegOutStMode;
wire[31:0] exMemAddr;
wire[63:0] exMemData;
wire exMemLoad;
wire exMemStore;
wire[4:0] exMemOpMode;
wire[7:0] exMemOpCmd2;
wire[31:0] exNextSr;
wire[31:0] exNextPr;
wire[31:0] exNextPc;
wire[31:0] exNextMach;
wire[31:0] exNextMacl;
wire[31:0] exNextGbr;
wire[31:0] exNextVbr;
wire[31:0] exNextSSr;
wire[31:0] exNextSPc;
wire[31:0] exNextSGr;
wire[31:0] exNextSp;
wire[31:0] exNextFpul;
wire[31:0] exNextFpScr;
ExOp2 exOp(clock, reset,
exUCmd, exStepPc,
exRegS, exRegValS,
exRegT, exRegValT,
exRegN, exRegValN,
exImm, tRegGenIdPc,
exRegO, exRegValO,
exRegOutOK, exRegOutStMode,
exMemAddr, exMemData,
exMemLoad, exMemStore,
exMemOpMode, exMemOpCmd2,
regSr, exNextSr,
regPr, exNextPr,
regExPc, exNextPc,
regMach, exNextMach,
regMacl, exNextMacl,
regSp, exNextSp,
regFpul, exNextFpul,
regFpScr, exNextFpScr,
regGbr, exNextGbr,
regVbr, exNextVbr,
regSSr, exNextSSr,
regSPc, exNextSPc,
regSGr, exNextSGr
);
reg[31:0] exNextSr2;
reg[31:0] exNextPr2;
reg[31:0] exNextPc2;
reg[31:0] exNextMach2;
reg[31:0] exNextMacl2;
reg[31:0] exNextGbr2;
reg[31:0] exNextVbr2;
reg[31:0] exNextSSr2;
reg[31:0] exNextSPc2;
reg[31:0] exNextSGr2;
reg[31:0] exNextFpul2;
reg[31:0] exNextFpScr2;
reg[31:0] exNextSp2;
reg[31:0] tRegGenIdPc;
reg[31:0] tRegGenIdPr;
reg[15:0] tRegGenIdOpw;
reg[3:0] tRegGenIdStepPc;
reg tRegExHold;
always @*
begin
regIdCsFl=0;
regIdCsFl[0]=1;
regIdCsFl[1]=regFpScr[19];
regIdCsFl[2]=regFpScr[20];
regIdCsFl[3]=regFpScr[21];
regIdCsFl[4]=regFpScr[24];
regIdCsFl[5]=regSr[31];
regIdCsFl[6]=regSr[12];
regNextRstTok=8'h55;
if(reset)
regNextRstTok=8'h00;
tRegGenIdStepPc=exStepPc2;
tRegExHold = 0;
if(regIfPcOK!=UMEM_OK_OK)
tRegExHold = 1;
if(exMemLoad||exMemStore)
begin
if(dcfRegOutOK!=UMEM_OK_OK)
tRegExHold = 1;
end
if(exRegOutOK==UMEM_OK_HOLD)
tRegExHold = 1;
dc2MemInData = 0;
dc2MemOK = UMEM_OK_READY;
dc2MmioInData = 0;
id2RegFpLdMode = 0;
idWbRegFpStMode = exRegOutStMode;
if(regFpScr[19])
id2RegFpLdMode = 1;
if(regFpScr[20])
id2RegFpLdMode = 1;
id2UCmd2 = id2UCmd;
case(exUCmd)
UCMD_BRAN: id2UCmd2 = UCMD_NONE;
UCMD_BSRN: id2UCmd2 = UCMD_NONE;
UCMD_BT: id2UCmd2 = UCMD_NONE;
UCMD_BF: id2UCmd2 = UCMD_NONE;
UCMD_RTSN: id2UCmd2 = UCMD_NONE;
UCMD_RTEN: id2UCmd2 = UCMD_NONE;
default: begin end
endcase
tRegGenIdPc = ifValPc + {28'h0, tRegGenIdStepPc};
tRegGenIdPr = ifValPc + 32'h4;
id2RegValN2 = id2RegValN;
id2RegValS2 = id2RegValS;
id2RegValT2 = id2RegValT;
wbRegO = exRegO;
wbRegValO = exRegValO;
if(id2RegS == wbRegO)
id2RegValS2 = wbRegValO;
if(id2RegT == wbRegO)
id2RegValT2 = wbRegValO;
if(id2RegN == wbRegO)
id2RegValN2 = wbRegValO;
exNextSr2 = exNextSr;
exNextPr2 = exNextPr;
exNextPc2 = exNextPc;
exNextMach2 = exNextMach;
exNextMacl2 = exNextMacl;
exNextGbr2 = exNextGbr;
exNextVbr2 = exNextVbr;
exNextSSr2 = exNextSSr;
exNextSPc2 = exNextSPc;
exNextSGr2 = exNextSGr;
regIfPcVal2 = regIfPcVal;
if(exNextPc != tRegGenIdPc)
begin
regIfPcVal2 = 48'h0F09_0F09_0E09;
end
exNextFpul2 = exNextFpul;
exNextFpScr2 = exNextFpScr;
exNextSp2 = exNextSp;
if(regRstTok != 8'h55)
begin
$display("Reset");
exNextPc2 = 32'hA000_0000;
tRegExHold = 1;
end
$display("IF: %X %X", ifValPc, regIfPcVal);
$display("ID: %X %X", idValPc, regIdPcVal);
end
always @ (posedge clock)
begin
regRstTok <= regNextRstTok;
dcfRegInAddr <= exMemAddr;
dcfRegInData <= exMemData;
dcfRegInOE <= exMemLoad;
dcfRegInWR <= exMemStore;
dcfRegInOp <= exMemOpMode;
idWbRegO <= wbRegO;
idWbRegValO <= wbRegValO;
if((exMemLoad||exMemStore) &&
(dcfRegOutOK==UMEM_OK_OK))
begin
idWbRegO <= id2RegN;
idWbRegValO <= dcfRegOutData[63:0];
end
else
begin
idWbRegO <= wbRegO;
idWbRegValO <= wbRegValO;
end
if(memIfPcOE)
begin
$display("ExUnit: memIfPcOE");
dc2RegInAddr <= memIfPcAddr;
dc2RegInData <= 0;
dc2RegInOE <= memIfPcOE;
dc2RegInWR <= 0;
dc2RegInOp <= 1;
memIfPcData <= dc2RegOutData;
memIfPcOK <= dc2RegOutOK;
dcfMemInData <= 128'hX;
if(dcfMemPcOE || dcfMemPcWR)
dcfMemPcOK <= UMEM_OK_HOLD;
else
dcfMemPcOK <= UMEM_OK_READY;
end
else
if(dcfMemPcOE || dcfMemPcWR)
begin
dc2RegInAddr <= dcfMemPcAddr;
dc2RegInData <= dcfMemOutData;
dc2RegInOE <= dcfMemPcOE;
dc2RegInWR <= dcfMemPcWR;
dc2RegInOp <= dcfMemOp;
dcfMemInData <= dc2RegOutData;
dcfMemPcOK <= dc2RegOutOK;
memIfPcData <= 128'hX;
if(memIfPcOE)
memIfPcOK <= UMEM_OK_HOLD;
else
memIfPcOK <= UMEM_OK_READY;
end
else
begin
dc2RegInAddr <= 0;
dc2RegInData <= 0;
dc2RegInOE <= 0;
dc2RegInWR <= 0;
dc2RegInOp <= 1;
end
if(regRstTok != 8'h55)
begin
ifValPc <= 32'hA000_0000;
ifValSr <= 0;
idValPc <= 32'hA000_0000;
idValSr <= 0;
regIdPcVal <= 0;
regExPcVal <= 0;
regExCsFl <= 0;
regExPc <= 32'hA000_0000;
regExSr <= 0;
exStepPc <= 0;
exStepPc2 <= 0;
end
else
if(!tRegExHold)
begin
$display("Step");
ifValPc <= exNextPc2;
ifValSr <= exNextSr2;
idValPc <= ifValPc;
idValSr <= ifValSr;
regIdPcVal <= regIfPcVal2;
id2ValPc <= idValPc;
id2ValSr <= idValSr;
regId2PcVal <= regIdPcVal;
regId2CsFl <= regIdCsFl;
id2RegN <= idRegN;
id2RegS <= idRegS;
id2RegT <= idRegT;
id2Imm <= idImm;
id2StepPc <= idStepPc;
id2StepPc2 <= idStepPc2;
id2UCmd <= idUCmd;
regExPcVal <= regId2PcVal;
regExCsFl <= regId2CsFl;
regExPc <= id2ValPc;
regExSr <= id2ValSr;
exRegN <= id2RegN;
exRegS <= id2RegS;
exRegT <= id2RegT;
exImm <= id2Imm;
exStepPc <= id2StepPc;
exStepPc2 <= id2StepPc2;
exUCmd <= id2UCmd2;
exRegValN <= id2RegValN2;
exRegValS <= id2RegValS2;
exRegValT <= id2RegValT2;
end
else
begin
$display("Hold");
end
end
endmodule | 2 |
142,506 | data/full_repos/permissive/99182535/bjx1c32b1/FpuFpF_Add.v | 99,182,535 | FpuFpF_Add.v | v | 193 | 33 | [] | [] | [] | [(1, 192)] | null | data/verilator_xmls/80172bf0-06ac-4d92-9bb0-0c7d7a486953.xml | null | 314,702 | module | module FpuFpF_Add(
clk,
isen,
doSub,
srca,
srcb,
dst
);
input clk;
input isen;
input doSub;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[9:0] exa;
reg[9:0] exb;
reg[9:0] exc;
reg[9:0] exm;
reg[31:0] tFracA;
reg[31:0] tFracB;
reg[31:0] tFracC;
reg[31:0] tFracA1;
reg[31:0] tFracB1;
reg[31:0] tFracC1;
reg[31:0] tFracC2;
reg[31:0] tFracC2_A;
reg[31:0] tFracC2_B;
reg[31:0] tFracC2_C;
reg[31:0] tFracC2_D;
reg[9:0] tExc_A;
reg[9:0] tExc_B;
reg[9:0] tExc_C;
reg[9:0] tExc_D;
always @ (clk) begin
sgna=srca[31];
sgnb=srcb[31];
exa[7:0]=srca[30:23];
exb[7:0]=srcb[30:23];
exa[9:8]=0;
exb[9:8]=0;
exm=(exa>=exb)?exa:exb;
if(sgna)
begin
tFracA[31:23]=~(9'h1);
tFracA[22:0]=~(srca[22:0]);
end
else
begin
tFracA[31:23]=9'h1;
tFracA[22:0]=srca[22:0];
end
if(sgnb^doSub)
begin
tFracB[31:23]=~(9'h1);
tFracB[22:0]=~(srcb[22:0]);
end
else
begin
tFracB[31:23]=9'h1;
tFracB[22:0]=srcb[22:0];
end
tFracA1=tFracA>>>(exm-exa);
tFracB1=tFracB>>>(exm-exb);
tFracC1=tFracA1+tFracB1;
if(tFracC1[31])
begin
sgnc=1;
tFracC2=~tFracC1;
end
else
begin
sgnc=0;
tFracC2=tFracC1;
end
if(tFracC2[23:0]==0)
begin
sgnc=0;
tFracC=0;
exc=0;
end
else
if(tFracC2[24:23]==0)
begin
if(tFracC2[23:8]==0)
begin
tFracC2_A=tFracC2<<16;
tExc_A=exm-16;
end
else
begin
tFracC2_A=tFracC2;
tExc_A=exm;
end
if(tFracC2_A[23:16]==0)
begin
tFracC2_B=tFracC2_A<<8;
tExc_B=tExc_A-8;
end
else
begin
tFracC2_B=tFracC2_A;
tExc_B=tExc_A;
end
if(tFracC2_B[23:20]==0)
begin
tFracC2_C=tFracC2_B<<4;
tExc_C=tExc_B-4;
end
else
begin
tFracC2_C=tFracC2_B;
tExc_C=tExc_B;
end
if(tFracC2_C[23:22]==0)
begin
tFracC2_D=tFracC2_C<<2;
tExc_D=tExc_C-2;
end
else
begin
tFracC2_D=tFracC2_C;
tExc_D=tExc_C;
end
if(tFracC2_D[23]==0)
begin
tFracC=tFracC2_D<<1;
exc=tExc_D-1;
end
else
begin
tFracC=tFracC2_D;
exc=tExc_D;
end
end
else
begin
if(tFracC2[24])
begin
tFracC=tFracC2>>1;
exc=exm+1;
end
else
begin
tFracC=tFracC2;
exc=exm;
end
end
if(exc[9])
begin
dst[31:0]=32'h0;
end
else if(exc[8])
begin
dst[31]=sgnc;
dst[30:0]=31'h7F80_0000;
end
else
begin
dst[31]=sgnc;
dst[30:23]=exc[7:0];
dst[22:0]=tFracC[22:0];
end
end
endmodule | module FpuFpF_Add(
clk,
isen,
doSub,
srca,
srcb,
dst
); |
input clk;
input isen;
input doSub;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[9:0] exa;
reg[9:0] exb;
reg[9:0] exc;
reg[9:0] exm;
reg[31:0] tFracA;
reg[31:0] tFracB;
reg[31:0] tFracC;
reg[31:0] tFracA1;
reg[31:0] tFracB1;
reg[31:0] tFracC1;
reg[31:0] tFracC2;
reg[31:0] tFracC2_A;
reg[31:0] tFracC2_B;
reg[31:0] tFracC2_C;
reg[31:0] tFracC2_D;
reg[9:0] tExc_A;
reg[9:0] tExc_B;
reg[9:0] tExc_C;
reg[9:0] tExc_D;
always @ (clk) begin
sgna=srca[31];
sgnb=srcb[31];
exa[7:0]=srca[30:23];
exb[7:0]=srcb[30:23];
exa[9:8]=0;
exb[9:8]=0;
exm=(exa>=exb)?exa:exb;
if(sgna)
begin
tFracA[31:23]=~(9'h1);
tFracA[22:0]=~(srca[22:0]);
end
else
begin
tFracA[31:23]=9'h1;
tFracA[22:0]=srca[22:0];
end
if(sgnb^doSub)
begin
tFracB[31:23]=~(9'h1);
tFracB[22:0]=~(srcb[22:0]);
end
else
begin
tFracB[31:23]=9'h1;
tFracB[22:0]=srcb[22:0];
end
tFracA1=tFracA>>>(exm-exa);
tFracB1=tFracB>>>(exm-exb);
tFracC1=tFracA1+tFracB1;
if(tFracC1[31])
begin
sgnc=1;
tFracC2=~tFracC1;
end
else
begin
sgnc=0;
tFracC2=tFracC1;
end
if(tFracC2[23:0]==0)
begin
sgnc=0;
tFracC=0;
exc=0;
end
else
if(tFracC2[24:23]==0)
begin
if(tFracC2[23:8]==0)
begin
tFracC2_A=tFracC2<<16;
tExc_A=exm-16;
end
else
begin
tFracC2_A=tFracC2;
tExc_A=exm;
end
if(tFracC2_A[23:16]==0)
begin
tFracC2_B=tFracC2_A<<8;
tExc_B=tExc_A-8;
end
else
begin
tFracC2_B=tFracC2_A;
tExc_B=tExc_A;
end
if(tFracC2_B[23:20]==0)
begin
tFracC2_C=tFracC2_B<<4;
tExc_C=tExc_B-4;
end
else
begin
tFracC2_C=tFracC2_B;
tExc_C=tExc_B;
end
if(tFracC2_C[23:22]==0)
begin
tFracC2_D=tFracC2_C<<2;
tExc_D=tExc_C-2;
end
else
begin
tFracC2_D=tFracC2_C;
tExc_D=tExc_C;
end
if(tFracC2_D[23]==0)
begin
tFracC=tFracC2_D<<1;
exc=tExc_D-1;
end
else
begin
tFracC=tFracC2_D;
exc=tExc_D;
end
end
else
begin
if(tFracC2[24])
begin
tFracC=tFracC2>>1;
exc=exm+1;
end
else
begin
tFracC=tFracC2;
exc=exm;
end
end
if(exc[9])
begin
dst[31:0]=32'h0;
end
else if(exc[8])
begin
dst[31]=sgnc;
dst[30:0]=31'h7F80_0000;
end
else
begin
dst[31]=sgnc;
dst[30:23]=exc[7:0];
dst[22:0]=tFracC[22:0];
end
end
endmodule | 2 |
142,507 | data/full_repos/permissive/99182535/bjx1c32b1/FpuFpL_Mul.v | 99,182,535 | FpuFpL_Mul.v | v | 82 | 70 | [] | [] | [] | [(7, 81)] | null | data/verilator_xmls/2cca06fb-e4ef-4b5a-a1db-d03ca7fadf87.xml | null | 314,704 | module | module FpuFpL_Mul(
clk,
enable,
srca,
srcb,
dst
);
input clk;
input enable;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[9:0] exa;
reg[9:0] exb;
reg[9:0] exc;
reg[35:0] tFracC;
reg[22:0] tFracC2;
reg[31:0] tDst;
assign dst = tDst;
always @*
begin
sgna = srca[31];
sgnb = srcb[31];
exa = { 2'b00, srca[30:23] };
exb = { 2'b00, srcb[30:23] };
sgnc = sgna^sgnb;
tFracC =
{20'h1, srca[22:7]} *
{20'h1, srcb[22:7]};
if(tFracC[35])
begin
tFracC2[22:0]=tFracC[34:12];
exc=exa+exb-126;
end
else
begin
tFracC2[22:0]=tFracC[33:11];
exc=exa+exb-127;
end
if(exc[9])
begin
tDst=0;
end
else
if(exc[8])
begin
tDst[31]=sgnc;
tDst[30:0]=31'h7F80_0000;
end
else
begin
tDst[31]=sgnc;
tDst[30:23]=exc[7:0];
tDst[22: 0]=tFracC2[22:0];
end
end
endmodule | module FpuFpL_Mul(
clk,
enable,
srca,
srcb,
dst
); |
input clk;
input enable;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[9:0] exa;
reg[9:0] exb;
reg[9:0] exc;
reg[35:0] tFracC;
reg[22:0] tFracC2;
reg[31:0] tDst;
assign dst = tDst;
always @*
begin
sgna = srca[31];
sgnb = srcb[31];
exa = { 2'b00, srca[30:23] };
exb = { 2'b00, srcb[30:23] };
sgnc = sgna^sgnb;
tFracC =
{20'h1, srca[22:7]} *
{20'h1, srcb[22:7]};
if(tFracC[35])
begin
tFracC2[22:0]=tFracC[34:12];
exc=exa+exb-126;
end
else
begin
tFracC2[22:0]=tFracC[33:11];
exc=exa+exb-127;
end
if(exc[9])
begin
tDst=0;
end
else
if(exc[8])
begin
tDst[31]=sgnc;
tDst[30:0]=31'h7F80_0000;
end
else
begin
tDst[31]=sgnc;
tDst[30:23]=exc[7:0];
tDst[22: 0]=tFracC2[22:0];
end
end
endmodule | 2 |
142,511 | data/full_repos/permissive/99182535/bjx1core32/DecOp.v | 99,182,535 | DecOp.v | v | 617 | 74 | [] | [] | [] | null | line:33: before: "]" | null | 1: b"%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:114: Can't find definition of variable: 'UOP_FWOP'\n idUopWord[31:24]=UOP_FWOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:128: Can't find definition of variable: 'REG_CC0'\n tIdRegS=REG_CC0;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:131: Can't find definition of variable: 'REG_ZZR'\n tIdRegT=REG_ZZR;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:132: Can't find definition of variable: 'UOP_MOVI'\n idUopWord[31:24]=UOP_MOVI;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:154: Can't find definition of variable: 'REG_CS0'\n : ... Suggested alternative: 'REG_CC0'\n tIdRegS=REG_CS0;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:175: Can't find definition of variable: 'REG_R0'\n : ... Suggested alternative: 'REG_CC0'\n tIdRegT=REG_R0;\n ^~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:176: Can't find definition of variable: 'UOP_MOVLDB'\n : ... Suggested alternative: 'UOP_MOVI'\n idUopWord[31:24]=UOP_MOVLDB;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:184: Can't find definition of variable: 'UOP_MOVLDW'\n : ... Suggested alternative: 'UOP_MOVLDB'\n idUopWord[31:24]=UOP_MOVLDW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:192: Can't find definition of variable: 'UOP_MOVLDI'\n : ... Suggested alternative: 'UOP_MOVLDB'\n idUopWord[31:24]=UOP_MOVLDI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:207: Can't find definition of variable: 'UOP_MOVSTI'\n : ... Suggested alternative: 'UOP_MOVI'\n idUopWord[31:24]=UOP_MOVSTI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:217: Can't find definition of variable: 'UOP_MOVSTB'\n : ... Suggested alternative: 'UOP_MOVSTI'\n 4'h0: idUopWord[31:24]=UOP_MOVSTB;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:218: Can't find definition of variable: 'UOP_MOVSTW'\n : ... Suggested alternative: 'UOP_MOVSTB'\n 4'h1: idUopWord[31:24]=UOP_MOVSTW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:221: Can't find definition of variable: 'UOP_TESTI'\n : ... Suggested alternative: 'UOP_MOVSTI'\n 4'h8: idUopWord[31:24]=UOP_TESTI;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:222: Can't find definition of variable: 'UOP_ANDI'\n : ... Suggested alternative: 'UOP_MOVLDI'\n 4'h9: idUopWord[31:24]=UOP_ANDI;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:223: Can't find definition of variable: 'UOP_XORI'\n : ... Suggested alternative: 'UOP_MOVI'\n 4'hA: idUopWord[31:24]=UOP_XORI;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:224: Can't find definition of variable: 'UOP_ORI'\n : ... Suggested alternative: 'UOP_XORI'\n 4'hB: idUopWord[31:24]=UOP_ORI;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:239: Can't find definition of variable: 'UOP_CMPEQI'\n : ... Suggested alternative: 'UOP_MOVI'\n 4'h0: idUopWord[31:24]=UOP_CMPEQI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:241: Can't find definition of variable: 'UOP_CMPHSI'\n : ... Suggested alternative: 'UOP_CMPEQI'\n 4'h2: idUopWord[31:24]=UOP_CMPHSI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:242: Can't find definition of variable: 'UOP_CMPGEI'\n : ... Suggested alternative: 'UOP_CMPEQI'\n 4'h3: idUopWord[31:24]=UOP_CMPGEI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:245: Can't find definition of variable: 'UOP_CMPHII'\n : ... Suggested alternative: 'UOP_CMPHSI'\n 4'h6: idUopWord[31:24]=UOP_CMPHII;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:246: Can't find definition of variable: 'UOP_CMPGTI'\n : ... Suggested alternative: 'UOP_CMPGEI'\n 4'h7: idUopWord[31:24]=UOP_CMPGTI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:247: Can't find definition of variable: 'UOP_SUBI'\n 4'h8: idUopWord[31:24]=UOP_SUBI;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:249: Can't find definition of variable: 'UOP_SUBCI'\n : ... Suggested alternative: 'UOP_SUBI'\n 4'hA: idUopWord[31:24]=UOP_SUBCI;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:250: Can't find definition of variable: 'UOP_SUBVI'\n : ... Suggested alternative: 'UOP_SUBCI'\n 4'hB: idUopWord[31:24]=UOP_SUBVI;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:251: Can't find definition of variable: 'UOP_ADDI'\n : ... Suggested alternative: 'UOP_ANDI'\n 4'hC: idUopWord[31:24]=UOP_ADDI;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:253: Can't find definition of variable: 'UOP_ADDCI'\n : ... Suggested alternative: 'UOP_ADDI'\n 4'hE: idUopWord[31:24]=UOP_ADDCI;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:254: Can't find definition of variable: 'UOP_ADDVI'\n : ... Suggested alternative: 'UOP_ADDCI'\n 4'hF: idUopWord[31:24]=UOP_ADDVI;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:323: Can't find definition of variable: 'REG_IMM'\n tIdRegT[3:0]=REG_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:325: Can't find definition of variable: 'UOP_XOR'\n : ... Suggested alternative: 'UOP_XORI'\n idUopWord[31:24]=UOP_XOR;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:349: Can't find definition of variable: 'UOP_AND'\n : ... Suggested alternative: 'UOP_ANDI'\n idUopWord[31:24]=UOP_AND;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:406: Can't find definition of variable: 'UOP_BRTF'\n idUopWord[31:24]=UOP_BRTF;\n ^~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:499: Can't find definition of variable: 'REG_PC4A2'\n tIdRegS=REG_PC4A2;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:510: Can't find definition of variable: 'UOP_JMP'\n : ... Suggested alternative: 'UOP_CMPEQI'\n idUopWord[31:24]=UOP_JMP;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:530: Can't find definition of variable: 'UOP_JSR'\n : ... Suggested alternative: 'UOP_JMP'\n idUopWord[31:24]=UOP_JSR;\n ^~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/DecOp.v:557: Can't find definition of variable: 'REG_PC4A4'\n : ... Suggested alternative: 'REG_PC4A2'\n tIdRegS=REG_PC4A4;\n ^~~~~~~~~\n%Error: Exiting due to 35 error(s)\n" | 314,713 | module | module DecOp(
clk,
istrWord,
regCurSr,
idRegD,
idRegS,
idRegT,
idImm,
idStepPc,
idUopPc,
idUopWord
);
input clk;
input[31:0] istrWord;
input[31:0] regCurSr;
output[6:0] idRegD;
output[6:0] idRegS;
output[6:0] idRegT;
output[31:0] idImm;
output[3:0] idStepPc;
output[11:0] idUopPc;
output[31:0] idUopWord;
reg[11:0] uopPcIdx[256];
reg[31:0] uopPgm[4096];
reg[7:0] uopUseIdx;
reg srIsDq;
initial begin
$readmemh("uopidx.txt", uopPcIdx);
$readmemh("uoppgm.txt", uopPgm);
end
reg opIs32p;
reg op2Is32p;
reg[6:0] tIdRegD;
reg[6:0] tIdRegS;
reg[6:0] tIdRegT;
reg[31:0] tIdImm;
reg[3:0] tIdStepPc;
assign idStepPc = tIdStepPc;
reg[15:0] tInstWord1;
reg[15:0] tInstWord2;
reg[7:0] tInstPfxOp;
reg opIs8Ep;
always @ (clk)
begin
opIs32p =
((istrWord[15:12]==0) && (istrWord[3:1]==0)) ||
((istrWord[15:12]==3) && ((istrWord[3:0]==1) || (istrWord[3:0]==9))) ||
((istrWord[15:12]==15) && (istrWord[3:0]==15)) ||
((istrWord[15:12]==8)&& ((istrWord[3:0]==10) ||
(istrWord[3:0]==12) || (istrWord[3:0]==14))) ;
if(istrWord[15:8]==8'h8E)
begin
tInstWord1=istrWord[31:16];
tInstPfxOp=istrWord[ 7: 0];
opIs8Ep=1;
end
else
begin
tInstWord1=istrWord[15:0];
tInstPfxOp=0;
opIs8Ep=0;
end
if(opIs32p)
tInstWord2=istrWord[47:32];
else
tInstWord2=istrWord[31:16];
op2Is32p =
((tInstWord2[15:12]==0) && (tInstWord2[3:1]==0)) ||
((tInstWord2[15:12]==3) && ((tInstWord2[3:0]==1) ||
(tInstWord2[3:0]==9))) ||
((tInstWord2[15:12]==15) && (tInstWord2[3:0]==15)) ||
((tInstWord2[15:12]==8)&& ((tInstWord2[3:0]==10) ||
(tInstWord2[3:0]==12) || (tInstWord2[3:0]==14))) ;
uopUseIdx=0;
tIdRegD[6:0]=0;
tIdRegS[6:0]=0;
tIdRegT[6:0]=0;
tIdImm[31:0]=32'h0;
tIdStepPc[1:0]=opIs32p ? 2'h2 : 2'h1;
tIdStepPc[3:2]=op2Is32p ? 2'h2 : 2'h1;
idUopPc[11:0]=12'h0;
idUopWord[31:0]=32'h0;
idUopWord[23]=0;
idUopWord[31:24]=UOP_FWOP;
srIsDq = regCurSr[12];
case(tInstWord1[15:12])
4'h0:
begin
case(tInstWord1[3:0])
4'h2:
begin
tIdRegS=REG_CC0;
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'h8:
begin
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'h9:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[11:8];
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'hA:
begin
tIdRegS=REG_CS0;
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'hB:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[11:8];
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'hC:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDB;
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDW;
end
4'hE:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDI;
end
default:
begin
end
endcase
end
4'h1:
begin
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
tIdImm[3:0]=tInstWord1[3:0];
idUopWord[31:24]=UOP_MOVSTI;
end
4'h2:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_MOVSTB;
4'h1: idUopWord[31:24]=UOP_MOVSTW;
4'h2: idUopWord[31:24]=UOP_MOVSTI;
4'h8: idUopWord[31:24]=UOP_TESTI;
4'h9: idUopWord[31:24]=UOP_ANDI;
4'hA: idUopWord[31:24]=UOP_XORI;
4'hB: idUopWord[31:24]=UOP_ORI;
default:
begin
end
endcase
end
4'h3:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_CMPEQI;
4'h2: idUopWord[31:24]=UOP_CMPHSI;
4'h3: idUopWord[31:24]=UOP_CMPGEI;
4'h6: idUopWord[31:24]=UOP_CMPHII;
4'h7: idUopWord[31:24]=UOP_CMPGTI;
4'h8: idUopWord[31:24]=UOP_SUBI;
4'hA: idUopWord[31:24]=UOP_SUBCI;
4'hB: idUopWord[31:24]=UOP_SUBVI;
4'hC: idUopWord[31:24]=UOP_ADDI;
4'hE: idUopWord[31:24]=UOP_ADDCI;
4'hF: idUopWord[31:24]=UOP_ADDVI;
default:
begin
end
endcase
end
4'h4:
begin
case(istrWord[3:0])
4'hA:
begin
tIdRegD=REG_CS0;
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'hE:
begin
tIdRegD=REG_CC0;
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
default:
begin
end
endcase
end
4'h5:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
tIdImm[3:0]=tInstWord1[3:0];
idUopWord[31:24]=UOP_MOVLDI;
end
4'h6:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_MOVLDB;
4'h1: idUopWord[31:24]=UOP_MOVLDW;
4'h2: idUopWord[31:24]=UOP_MOVLDI;
4'h3:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'h7:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'hFFFF_FFFF;
idUopWord[31:24]=UOP_XOR;
end
4'hA:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=REG_ZZR;
tIdRegT[3:0]=tInstWord1[ 7:4];
idUopWord[31:24]=UOP_SUBI;
end
4'hB:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=REG_ZZR;
tIdRegT[3:0]=tInstWord1[ 7:4];
idUopWord[31:24]=UOP_SUBCI;
end
4'hC:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'h0000_00FF;
idUopWord[31:24]=UOP_AND;
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'h0000_FFFF;
idUopWord[31:24]=UOP_AND;
end
default:
begin
end
endcase
end
4'h7:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[6:0]=REG_IMM;
idUopWord[31:24]=UOP_ADDI;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'h8:
begin
case(istrWord[11:8])
4'h9:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=1;
idUopWord[17]=1;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hB:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=0;
idUopWord[17]=1;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hD:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=1;
idUopWord[17]=0;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hF:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=0;
idUopWord[17]=0;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
default:
begin
end
endcase
end
4'h9:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_PC4A2;
tIdRegT=REG_ZZR;
tIdImm[7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_MOVLDW;
end
4'hA:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_JMP;
if(opIs8Ep)
begin
tIdImm[31:20]=tInstPfxOp[7] ? 12'hFFF : 12'h000 ;
tIdImm[19:12]=tInstPfxOp[7:0];
tIdImm[11: 0]=tInstWord1[11:0];
end
else
begin
tIdImm[31:12]=tInstWord1[7] ? 20'hFFFFF : 20'h00000 ;
tIdImm[11:0]=tInstWord1[11:0];
end
end
4'hB:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_JSR;
if(opIs8Ep)
begin
tIdImm[31:20]=tInstPfxOp[7] ? 12'hFFF : 12'h000 ;
tIdImm[19:12]=tInstPfxOp[7:0];
tIdImm[11: 0]=tInstWord1[11:0];
end
else
begin
tIdImm[31:12]=tInstWord1[7] ? 20'hFFFFF : 20'h00000 ;
tIdImm[11:0]=tInstWord1[11:0];
end
end
4'hC:
begin
case(tInstWord1[11:8])
default:
begin
end
endcase
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_PC4A4;
tIdRegT=REG_ZZR;
tIdImm[7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_MOVLDI;
end
4'hE:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_ADDI;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
default:
begin
tIdRegD[6:0]=7'h7F;
tIdRegS[6:0]=7'h7F;
tIdRegT[6:0]=7'h7F;
tIdImm[31:0]=32'h0;
idStepPc=2'h1;
end
endcase
if(uopUseIdx!=0)
begin
idUopPc=uopPcIdx[uopUseIdx];
idUopWord=uopPgm[idUopPc];
end
idRegD=tIdRegD ^
((regCurSr[29] && (tIdRegD[6:3]==4'h0)) ? 7'h40 : 7'h00);
idRegS=tIdRegS ^
((regCurSr[29] && (tIdRegS[6:3]==4'h0)) ? 7'h40 : 7'h00);
idRegT=tIdRegT ^
((regCurSr[29] && (tIdRegT[6:3]==4'h0)) ? 7'h40 : 7'h00);
idImm=tIdImm;
end
endmodule | module DecOp(
clk,
istrWord,
regCurSr,
idRegD,
idRegS,
idRegT,
idImm,
idStepPc,
idUopPc,
idUopWord
); |
input clk;
input[31:0] istrWord;
input[31:0] regCurSr;
output[6:0] idRegD;
output[6:0] idRegS;
output[6:0] idRegT;
output[31:0] idImm;
output[3:0] idStepPc;
output[11:0] idUopPc;
output[31:0] idUopWord;
reg[11:0] uopPcIdx[256];
reg[31:0] uopPgm[4096];
reg[7:0] uopUseIdx;
reg srIsDq;
initial begin
$readmemh("uopidx.txt", uopPcIdx);
$readmemh("uoppgm.txt", uopPgm);
end
reg opIs32p;
reg op2Is32p;
reg[6:0] tIdRegD;
reg[6:0] tIdRegS;
reg[6:0] tIdRegT;
reg[31:0] tIdImm;
reg[3:0] tIdStepPc;
assign idStepPc = tIdStepPc;
reg[15:0] tInstWord1;
reg[15:0] tInstWord2;
reg[7:0] tInstPfxOp;
reg opIs8Ep;
always @ (clk)
begin
opIs32p =
((istrWord[15:12]==0) && (istrWord[3:1]==0)) ||
((istrWord[15:12]==3) && ((istrWord[3:0]==1) || (istrWord[3:0]==9))) ||
((istrWord[15:12]==15) && (istrWord[3:0]==15)) ||
((istrWord[15:12]==8)&& ((istrWord[3:0]==10) ||
(istrWord[3:0]==12) || (istrWord[3:0]==14))) ;
if(istrWord[15:8]==8'h8E)
begin
tInstWord1=istrWord[31:16];
tInstPfxOp=istrWord[ 7: 0];
opIs8Ep=1;
end
else
begin
tInstWord1=istrWord[15:0];
tInstPfxOp=0;
opIs8Ep=0;
end
if(opIs32p)
tInstWord2=istrWord[47:32];
else
tInstWord2=istrWord[31:16];
op2Is32p =
((tInstWord2[15:12]==0) && (tInstWord2[3:1]==0)) ||
((tInstWord2[15:12]==3) && ((tInstWord2[3:0]==1) ||
(tInstWord2[3:0]==9))) ||
((tInstWord2[15:12]==15) && (tInstWord2[3:0]==15)) ||
((tInstWord2[15:12]==8)&& ((tInstWord2[3:0]==10) ||
(tInstWord2[3:0]==12) || (tInstWord2[3:0]==14))) ;
uopUseIdx=0;
tIdRegD[6:0]=0;
tIdRegS[6:0]=0;
tIdRegT[6:0]=0;
tIdImm[31:0]=32'h0;
tIdStepPc[1:0]=opIs32p ? 2'h2 : 2'h1;
tIdStepPc[3:2]=op2Is32p ? 2'h2 : 2'h1;
idUopPc[11:0]=12'h0;
idUopWord[31:0]=32'h0;
idUopWord[23]=0;
idUopWord[31:24]=UOP_FWOP;
srIsDq = regCurSr[12];
case(tInstWord1[15:12])
4'h0:
begin
case(tInstWord1[3:0])
4'h2:
begin
tIdRegS=REG_CC0;
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'h8:
begin
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'h9:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[11:8];
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'hA:
begin
tIdRegS=REG_CS0;
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'hB:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[11:8];
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'hC:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDB;
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDW;
end
4'hE:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDI;
end
default:
begin
end
endcase
end
4'h1:
begin
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
tIdImm[3:0]=tInstWord1[3:0];
idUopWord[31:24]=UOP_MOVSTI;
end
4'h2:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_MOVSTB;
4'h1: idUopWord[31:24]=UOP_MOVSTW;
4'h2: idUopWord[31:24]=UOP_MOVSTI;
4'h8: idUopWord[31:24]=UOP_TESTI;
4'h9: idUopWord[31:24]=UOP_ANDI;
4'hA: idUopWord[31:24]=UOP_XORI;
4'hB: idUopWord[31:24]=UOP_ORI;
default:
begin
end
endcase
end
4'h3:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_CMPEQI;
4'h2: idUopWord[31:24]=UOP_CMPHSI;
4'h3: idUopWord[31:24]=UOP_CMPGEI;
4'h6: idUopWord[31:24]=UOP_CMPHII;
4'h7: idUopWord[31:24]=UOP_CMPGTI;
4'h8: idUopWord[31:24]=UOP_SUBI;
4'hA: idUopWord[31:24]=UOP_SUBCI;
4'hB: idUopWord[31:24]=UOP_SUBVI;
4'hC: idUopWord[31:24]=UOP_ADDI;
4'hE: idUopWord[31:24]=UOP_ADDCI;
4'hF: idUopWord[31:24]=UOP_ADDVI;
default:
begin
end
endcase
end
4'h4:
begin
case(istrWord[3:0])
4'hA:
begin
tIdRegD=REG_CS0;
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'hE:
begin
tIdRegD=REG_CC0;
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
default:
begin
end
endcase
end
4'h5:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
tIdImm[3:0]=tInstWord1[3:0];
idUopWord[31:24]=UOP_MOVLDI;
end
4'h6:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_MOVLDB;
4'h1: idUopWord[31:24]=UOP_MOVLDW;
4'h2: idUopWord[31:24]=UOP_MOVLDI;
4'h3:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'h7:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'hFFFF_FFFF;
idUopWord[31:24]=UOP_XOR;
end
4'hA:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=REG_ZZR;
tIdRegT[3:0]=tInstWord1[ 7:4];
idUopWord[31:24]=UOP_SUBI;
end
4'hB:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=REG_ZZR;
tIdRegT[3:0]=tInstWord1[ 7:4];
idUopWord[31:24]=UOP_SUBCI;
end
4'hC:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'h0000_00FF;
idUopWord[31:24]=UOP_AND;
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'h0000_FFFF;
idUopWord[31:24]=UOP_AND;
end
default:
begin
end
endcase
end
4'h7:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[6:0]=REG_IMM;
idUopWord[31:24]=UOP_ADDI;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'h8:
begin
case(istrWord[11:8])
4'h9:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=1;
idUopWord[17]=1;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hB:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=0;
idUopWord[17]=1;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hD:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=1;
idUopWord[17]=0;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hF:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=0;
idUopWord[17]=0;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
default:
begin
end
endcase
end
4'h9:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_PC4A2;
tIdRegT=REG_ZZR;
tIdImm[7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_MOVLDW;
end
4'hA:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_JMP;
if(opIs8Ep)
begin
tIdImm[31:20]=tInstPfxOp[7] ? 12'hFFF : 12'h000 ;
tIdImm[19:12]=tInstPfxOp[7:0];
tIdImm[11: 0]=tInstWord1[11:0];
end
else
begin
tIdImm[31:12]=tInstWord1[7] ? 20'hFFFFF : 20'h00000 ;
tIdImm[11:0]=tInstWord1[11:0];
end
end
4'hB:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_JSR;
if(opIs8Ep)
begin
tIdImm[31:20]=tInstPfxOp[7] ? 12'hFFF : 12'h000 ;
tIdImm[19:12]=tInstPfxOp[7:0];
tIdImm[11: 0]=tInstWord1[11:0];
end
else
begin
tIdImm[31:12]=tInstWord1[7] ? 20'hFFFFF : 20'h00000 ;
tIdImm[11:0]=tInstWord1[11:0];
end
end
4'hC:
begin
case(tInstWord1[11:8])
default:
begin
end
endcase
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_PC4A4;
tIdRegT=REG_ZZR;
tIdImm[7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_MOVLDI;
end
4'hE:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_ADDI;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
default:
begin
tIdRegD[6:0]=7'h7F;
tIdRegS[6:0]=7'h7F;
tIdRegT[6:0]=7'h7F;
tIdImm[31:0]=32'h0;
idStepPc=2'h1;
end
endcase
if(uopUseIdx!=0)
begin
idUopPc=uopPcIdx[uopUseIdx];
idUopWord=uopPgm[idUopPc];
end
idRegD=tIdRegD ^
((regCurSr[29] && (tIdRegD[6:3]==4'h0)) ? 7'h40 : 7'h00);
idRegS=tIdRegS ^
((regCurSr[29] && (tIdRegS[6:3]==4'h0)) ? 7'h40 : 7'h00);
idRegT=tIdRegT ^
((regCurSr[29] && (tIdRegT[6:3]==4'h0)) ? 7'h40 : 7'h00);
idImm=tIdImm;
end
endmodule | 2 |
142,513 | data/full_repos/permissive/99182535/bjx1core32/ExUop.v | 99,182,535 | ExUop.v | v | 915 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:131: Cannot find include file: ArithAlu.v\n`include "ArithAlu.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1core32,data/full_repos/permissive/99182535/ArithAlu.v\n data/full_repos/permissive/99182535/bjx1core32,data/full_repos/permissive/99182535/ArithAlu.v.v\n data/full_repos/permissive/99182535/bjx1core32,data/full_repos/permissive/99182535/ArithAlu.v.sv\n ArithAlu.v\n ArithAlu.v.v\n ArithAlu.v.sv\n obj_dir/ArithAlu.v\n obj_dir/ArithAlu.v.v\n obj_dir/ArithAlu.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:132: Cannot find include file: MemAlu.v\n`include "MemAlu.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:133: Cannot find include file: FpuFp64B.v\n`include "FpuFp64B.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:134: Cannot find include file: GpReg.v\n`include "GpReg.v" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:135: Cannot find include file: MemTile2.v\n`include "MemTile2.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:136: Cannot find include file: DecOp.v\n`include "DecOp.v" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:550: syntax error, unexpected \'=\', expecting \',\' or \':\'\n tData2D={32\'h0, tDataAluD};\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:565: syntax error, unexpected \':\'\n 4\'h2:\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:594: syntax error, unexpected INTEGER NUMBER\n 4\'h3:\n ^~~~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:622: syntax error, unexpected \'=\', expecting IDENTIFIER\n memRd=1\'b0;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:627: syntax error, unexpected \'=\', expecting IDENTIFIER\n memRd=1\'b1;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:632: syntax error, unexpected \'=\', expecting IDENTIFIER\n tNextPipeHold=1;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:640: syntax error, unexpected \'=\', expecting IDENTIFIER\n tNextPipeHold=2;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:645: syntax error, unexpected \'=\', expecting IDENTIFIER\n tIsWr2D=1\'b1;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:651: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h1: tData2D=aguDataHeldS-1;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:652: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h2: tData2D=aguDataHeldS-2;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:653: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h3: tData2D=aguDataHeldS-4;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:654: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h4: tData2D=aguDataHeldS-8;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:660: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h1: tData2D=aguDataHeldS+1;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:661: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h2: tData2D=aguDataHeldS+2;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:662: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h3: tData2D=aguDataHeldS+4;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:663: syntax error, unexpected \'=\', expecting IDENTIFIER\n 3\'h4: tData2D=aguDataHeldS+8;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:670: syntax error, unexpected \'=\', expecting IDENTIFIER\n aguDataNextHeldS = iDataS;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:689: syntax error, unexpected \'=\', expecting IDENTIFIER\n tIsWr2D=0;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:717: syntax error, unexpected \'=\', expecting IDENTIFIER\n tIsWr2D=0;\n ^\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:843: syntax error, unexpected <=, expecting IDENTIFIER\n tResetMagic <= 12345;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:845: syntax error, unexpected <=, expecting IDENTIFIER\n tResetMagic <= 0;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:849: syntax error, unexpected <=, expecting IDENTIFIER\n regs.reg_sr <= 0;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:850: syntax error, unexpected <=, expecting IDENTIFIER\n regs.reg_pc <= 0;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:851: syntax error, unexpected <=, expecting IDENTIFIER\n regs.reg_pr <= 0;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:864: syntax error, unexpected <=, expecting IDENTIFIER\n regs.reg_sr <= regNextSr;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:865: syntax error, unexpected <=, expecting IDENTIFIER\n regs.reg_pc <= regNextPc;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:866: syntax error, unexpected <=, expecting IDENTIFIER\n regs.reg_pr <= regNextPr;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:882: syntax error, unexpected <=, expecting IDENTIFIER\n idInstWord <= 32\'h0F090F09;\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:888: syntax error, unexpected <=, expecting IDENTIFIER\n idInstWord <= imemRdValue[31:0];\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:893: syntax error, unexpected <=, expecting IDENTIFIER\n idInstWord <= imemRdValue[31:0];\n ^~\n%Error: data/full_repos/permissive/99182535/bjx1core32/ExUop.v:899: syntax error, unexpected <=, expecting IDENTIFIER\n ixRegD <= idRegD;\n ^~\n%Error: Cannot continue\n' | 314,715 | module | module ExUop(clk, reset,
extAddr, extData,
extOE, extWR,
extNotReady);
input clk;
input reset;
output[31:0] extAddr;
inout[31:0] extData;
output extOE;
output extWR;
input extNotReady;
reg[31:0] ifRegPc;
reg[31:0] idNextInstWord;
reg[31:0] idInstWord;
reg[6:0] idRegD;
reg[6:0] idRegS;
reg[6:0] idRegT;
reg[31:0] idImm;
reg[11:0] idUopPc;
reg[31:0] idUopWord;
reg[31:0] idRegPc;
reg[31:0] idRegNextPc;
reg[31:0] uopWord;
reg[31:0] uopNextWord;
reg[7:0] uopCmd;
reg[6:0] ixRegD;
reg[6:0] ixRegS;
reg[6:0] ixRegT;
reg[31:0] ixImm;
reg[31:0] ixRegPc;
reg[31:0] ixRegNextPc;
reg[6:0] iRegD;
reg[6:0] iRegS;
reg[6:0] iRegT;
reg[31:0] iImm;
reg[63:0] iDataD;
reg[63:0] iDataS;
reg[63:0] iDataT;
reg[63:0] tData2D;
reg[6:0] tIdReg2D;
reg tIsWr2D;
reg tIsQw2D;
reg[63:0] oData2D;
reg[6:0] oIdReg2D;
reg oIsWr2D;
reg oIsQw2D;
GpReg regs(clk,
oIsWr2D, oIsQw2D, oIdReg2D, oData2D,
iRegD, iDataD, iRegS, iDataS, iRegT, iDataT);
reg[31:0] iDataAluS;
reg[31:0] iDataAluT;
reg[31:0] tDataAluD;
reg[31:0] regSr;
reg[31:0] regNextSr;
reg[31:0] regPc;
reg[31:0] regNextPc;
reg[31:0] regPrNextPc;
reg[31:0] regPrPc;
reg[31:0] regPr;
reg[31:0] regNextPr;
reg[4:0] aluCmd;
reg[3:0] tAluSr;
ArithAlu alu1(clk, aluCmd,
iDataAluS, iDataAluT, tDataAluD, regSr[3:0], tAluSr);
reg[31:0] aguDataHeldS;
reg[31:0] aguDataNextHeldS;
reg aguHasIndex;
reg[31:0] tDataAguD;
reg[2:0] aguCmd;
reg[31:0] aguDataS;
reg[31:0] aguDataT;
MemAlu agu1(clk, aguCmd,
aguDataS, aguDataT, iImm, tDataAguD);
assign aguDataT = aguHasIndex ? iDataT[31:0] : 0;
assign aguDataS = tPostIncr ? aguDataHeldS[31:0] : iDataS[31:0];
reg fpuOpFp32;
reg[3:0] fpuCmd;
reg[3:0] tFpuSr;
reg[63:0] iDataFpuD;
reg[63:0] iDataFpuS;
reg[63:0] iDataFpuT;
reg[63:0] fpuDataD;
FpuFp64B fpu1(clk, fpuOpFp32, fpuCmd, iDataFpuS, iDataFpuT, iDataFpuD, fpuDataD,
regSr[3:0], tFpuSr);
reg memRd;
reg memWr;
reg[2:0] memCmd;
reg[31:0] memAddr;
reg[63:0] memRdValue;
reg[63:0] memWrValue;
reg imemRd;
reg[31:0] imemAddr;
wire[63:0] imemRdValue;
wire memHold;
MemTile2 mem1(clk, reset,
memRd, memWr, memCmd,
memAddr, memRdValue, memWrValue,
imemRd, imemAddr, imemRdValue,
extAddr, extData, extOE, extWR,
memHold, extNotReady);
reg[1:0] idStepPc;
DecOp dec1(clk, idInstWord, regSr[31:0],
idRegD, idRegS, idRegT, idImm, idStepPc, idUopPc, idUopWord);
reg[31:0] tRegStepPc;
reg[11:0] uopPc;
reg[11:0] uopNextPc;
reg uopPcLive;
reg uopNextPcLive;
reg[15:0] tResetMagic;
reg tResetOK;
reg tHold;
reg[2:0] tPipeFlush;
reg[2:0] tNextPipeFlush;
reg tPipeDsFlush;
reg tNextPipeDsFlush;
reg[2:0] tPipeHold;
reg[2:0] tNextPipeHold;
reg tPostIncr;
reg tNextPostIncr;
reg tPostIncrDn;
reg tNextPostIncrDn;
reg tPostIncrDir;
reg tNextPostIncrDir;
assign tResetOK = !reset && (tResetMagic==12345);
assign tHold = !tResetOK && !memHold;
assign regPc = regs.reg_pc;
assign regPr = regs.reg_pr;
assign regSr = regs.reg_sr;
always @ (clk)
begin
if(!tResetOK)
begin
$display("Reset");
end
else if(tHold)
begin
$display("Hold");
end
else
if((memHold==0) && tResetOK)
begin
if(!uopPcLive)
begin
idNextInstWord=imemRdValue[31:0];
$display("1F: PC=%X Op=%X", ifRegPc, idNextInstWord);
if(imemRdValue==0)
idNextInstWord=32'hFFFF_FFFF;
idRegNextPc=ifRegPc;
end
else
begin
idNextInstWord=idInstWord;
end
tRegStepPc[31:3]=29'h0;
tRegStepPc[2:1]=idStepPc[1:0];
tRegStepPc[0]=1'b0;
if(tPipeFlush>1)
begin
$display("2D-0/F: PC=%X Op=%X St=%X", idRegPc, idInstWord, idStepPc);
$display("2D-1/F: uPC=%X uOp=%X", idUopPc, idUopWord);
regNextPc=regPc;
regPrNextPc=regPc+4;
uopNextPc=idUopPc;
uopNextWord=idUopWord;
ixRegNextPc=idRegPc;
end
else
if(!uopPcLive)
begin
$display("2D-0: PC=%X Op=%X St=%X", idRegPc, idInstWord, idStepPc);
$display("2D-1: uPC=%X uOp=%X", idUopPc, idUopWord);
if(idInstWord==32'hFFFF_FFFF)
$finish(0);
uopNextPc=idUopPc;
uopNextWord=idUopWord;
regNextPc=ifRegPc+tRegStepPc;
regPrNextPc=ifRegPc+tRegStepPc;
ixRegNextPc=idRegPc;
end
else
begin
if(!memHold)
begin
$display("2D-2 uPC=%X uOp=%X", idUopPc, idUopWord);
end
regNextPc=regPc;
regPrNextPc=regPc+4;
end
uopCmd=uopWord[31:24];
if(tPipeFlush!=0)
begin
tNextPipeFlush=tPipeFlush-1;
tNextPipeDsFlush=tPipeDsFlush;
end
else
begin
tNextPipeFlush=0;
tNextPipeDsFlush=0;
end
if(tPipeHold!=0)
tNextPipeHold=tPipeHold-1;
else
tNextPipeHold=0;
$display("3E-0: PC=%X", ixRegPc);
$display("3E-1 uPC=%X uOp=%X", uopPc, uopWord);
if(uopWord[23]==0)
begin
uopNextPcLive=0;
end
else
begin
uopNextPc=uopPc+1;
uopNextWord=dec1.uopPgm[uopNextPc];
uopNextPcLive=1;
end
if(tPipeFlush!=0)
uopNextPcLive=0;
case(uopWord[22:21])
2'b00:
begin
iRegD = ixRegD;
iRegS = ixRegS;
iRegT = ixRegT;
iImm = ixImm;
end
2'b10:
begin
iRegD = uopWord[20:14];
iRegS = uopWord[13: 7];
iRegT = uopWord[ 6: 0];
iImm = ixImm;
end
2'b01:
begin
if(uopWord[20])
begin
iRegS = ixRegS;
iRegT = ixRegT;
iRegD[6:4] = 0;
iRegD[3:0] = uopWord[19:16];
iImm[31:16] = uopWord[15] ? 16'hFFFF : 16'h0000 ;
iImm[15:0] = uopWord[15:0];
end
else
begin
iRegD = ixRegD;
iRegS = ixRegS;
iRegT = ixRegT;
iImm[31:20] = uopWord[19] ? 12'hFFF : 12'h000 ;
iImm[19:0] = uopWord[19:0];
end
end
2'b11:
begin
iRegD[6:4] = 0;
iRegD[3:0] = uopWord[19:16];
iRegS[6:4] = 0;
iRegS[3:0] = uopWord[15:12];
iRegT[6:4] = 0;
iRegT[3:0] = uopWord[11: 8];
iImm[31:8] = (uopWord[20] && uopWord[7]) ?
24'hFFFFFF : 24'h000000 ;
iImm[ 7:0] = uopWord[7:0];
end
endcase
iDataAluS=iDataS[31:0];
iDataAluT=iDataT[31:0];
iDataFpuD=iDataD[63:0];
iDataFpuS=iDataS[63:0];
iDataFpuT=iDataT[63:0];
if(iRegS==regs.REG_ZZR)
begin
iDataAluS[31: 0] = 0;
end
if(iRegT==regs.REG_IMM)
begin
iDataAluT[31: 0] = iImm;
end
tData2D=iDataD;
tIsWr2D=1'b0;
tIsQw2D=1'b0;
regNextSr=regSr;
regNextPr=regPr;
tIdReg2D=iRegD;
aguHasIndex = (iRegT[3:0]!=15);
aguDataNextHeldS = aguDataHeldS;
aluCmd=0;
aguCmd=0;
memCmd=0;
fpuCmd=0;
fpuOpFp32=0;
tNextPostIncr=0;
tNextPostIncrDn=0;
$display("Uop Cmd %X", uopCmd);
case(uopCmd[7:4])
4'h0:
begin
if(uopCmd[3:0]==4'h0)
begin
uopNextPcLive = 0;
end
else
begin
aluCmd=uopCmd[4:0];
tData2D={32'h0, tDataAluD};
tIsWr2D=1'b1;
$display("EX ALU.L Op=%X D=%X(%X) S=%X(%X) T=%X(%X) -> %X",
aluCmd,
iRegD, iDataD,
iRegS, iDataAluS,
iRegT, iDataAluT,
tDataAluD);
end
end
4'h1:
aluCmd=uopCmd[4:0];
tData2D={32'h0, tDataAluD};
tIsWr2D=aluCmd<alu1.UOP_TEST;
regNextSr[31:1]=regSr[31:1];
regNextSr[0]=tAluSr[0];
$display("EX ALU.L Op=%X D=%X(%X) S=%X(%X) T=%X(%X) -> %X",
aluCmd,
iRegD, iDataD,
iRegS, iDataAluS,
iRegT, iDataAluT,
tDataAluD);
begin
end
4'h2:
begin
if(uopCmd[3:0]==4'h0)
begin
regNextPc = regPrPc + (iDataAluT*2);
tNextPipeFlush = 2;
$display("3E BRA PC=%X -> %X (Disp=%X)",
regPrPc, regNextPc, iDataAluT);
end
else
begin
if(iRegT==regs.REG_R0)
aguCmd=agu1.MD_BYTE;
else
aguCmd=uopCmd[2:0];
if(uopCmd[3])
begin
tIdReg2D=iRegS;
aguHasIndex = 0;
end
tData2D={32'h0, tDataAguD};
tIsWr2D=1'b1;
end
end
4'h3:
begin
if(uopCmd[3:0]==4'h0)
begin
regNextPr = regPrNextPc;
regNextPc = regPrNextPc + (iDataAluT*2);
tNextPipeFlush = 2;
$display("3E BSR PC=%X -> %X (Disp=%X)",
regPrPc, regNextPc, iDataAluT);
end
else
begin
if(iRegT==regs.REG_R0)
aguCmd=agu1.MD_BYTE;
else
aguCmd=uopCmd[2:0];
memCmd=uopCmd[2:0];
memAddr=tDataAguD[31:0];
tIsWr2D=uopCmd[3];
memWrValue=iDataD;
tData2D=memRdValue;
if(uopCmd[3])
begin
memRd=1'b0;
memWr=1'b1;
end
else
begin
memRd=1'b1;
memWr=1'b0;
end
if(tPipeHold==0)
tNextPipeHold=1;
tPostNextIncr=uopWord[17];
tPostNextIncrDir=uopWord[16];
if(tPostIncr)
begin
if(tPipeHold==0)
tNextPipeHold=2;
tNextPostIncrDn=1;
if(!tPostIncrDn)
begin
tIsWr2D=1'b1;
tIsQw2D=1'b0;
tIdReg2D=iRegS;
if(tPostNextIncrDir)
begin
case(memCmd)
3'h1: tData2D=aguDataHeldS-1;
3'h2: tData2D=aguDataHeldS-2;
3'h3: tData2D=aguDataHeldS-4;
3'h4: tData2D=aguDataHeldS-8;
endcase
end
else
begin
case(memCmd)
3'h1: tData2D=aguDataHeldS+1;
3'h2: tData2D=aguDataHeldS+2;
3'h3: tData2D=aguDataHeldS+4;
3'h4: tData2D=aguDataHeldS+8;
endcase
end
end
end
else
begin
aguDataNextHeldS = iDataS;
end
end
end
4'h4:
begin
if(uopCmd[3:0]==4'h0)
begin
end
else
begin
fpuCmd=uopCmd[3:0];
tData2D=fpuDataD;
tIsWr2D=1;
if((fpuCmd!=fpu1.OP_CMPEQ) || (fpuCmd!=fpu1.OP_CMPGT))
begin
tIsWr2D=0;
regNextSr[31:1]=regSr[31:1];
regNextSr[0]=tFpuSr[0];
end
end
end
4'h5:
begin
if(uopCmd[3:0]==4'h0)
begin
if((regSr[0]^uopWord[16])==0)
begin
regNextPc = regPrPc + (iDataAluT*2);
tNextPipeFlush = 2;
tNextPipeDsFlush = uopWord[17];
$display("3E BRTF PC=%X -> %X (Disp=%X)",
regPrPc, regNextPc, iDataAluT);
end
end
else
begin
fpuCmd=uopCmd[3:0];
tData2D=fpuDataD;
tIsWr2D=1;
if((fpuCmd!=fpu1.OP_CMPEQ) || (fpuCmd!=fpu1.OP_CMPGT))
begin
tIsWr2D=0;
regNextSr[31:1]=regSr[31:1];
regNextSr[0]=tFpuSr[0];
end
end
end
default: begin
end
endcase
if(uopCmd==8'h40)
begin
case(uopWord[15:12])
4'h0:
case(uopWord[3:0])
4'h0:
begin
end
4'h8:
case(uopWord[7:4])
4'h0:
regNextSr[0]=0;
4'h1:
regNextSr[0]=1;
4'h4:
case(uopWord[11:8])
4'h0: regNextSr[1]=0;
4'h1: regNextSr[12]=0;
4'h2: regNextSr[31]=0;
4'h3: begin regNextSr[31]=0; regNextSr[12]=0; end
default: regNextSr[1]=0;
endcase
4'h5:
case(uopWord[11:8])
4'h0: regNextSr[1]=1;
4'h1: regNextSr[12]=1;
4'h2: regNextSr[31]=1;
4'h3: begin regNextSr[31]=1; regNextSr[12]=1; end
default: regNextSr[1]=1;
endcase
4'h6:
regNextSr[0]=!regSr[0];
default: begin end
endcase
4'h9:
case(uopWord[7:4])
4'h0:
begin end
4'h1:
begin
regNextSr[0]=0;
regNextSr[8]=0;
regNextSr[9]=0;
end
4'h2:
begin
tData2D[63:0]=0;
tData2D[0]=regSr[0];
end
4'h3:
begin
regNextSr[0]=iDataT[0];
end
default: begin end
endcase
4'hB:
case(uopWord[7:4])
4'h0:
regNextPc=regPr;
4'h1:
begin end
4'h2:
begin
end
4'h3:
begin end
default: begin end
endcase
default: begin end
endcase
default: begin
end
endcase
end
end
end
always @ (negedge clk)
begin
oData2D <= tData2D;
oIsWr2D <= tIsWr2D;
oIsQw2D <= tIsQw2D;
oIdReg2D <= tIdReg2D;
end
always @ (posedge clk)
begin
tPostIncr <= tNextPostIncr;
tPostIncrDn <= tNextPostIncrDn;
tPostIncrDir <= tNextPostIncrDir;
aguDataHeldS <= aguDataNextHeldS;
tPipeHold <= tNextPipeHold;
if(memHold || (tPipeHold || tNextPipeHold) || !tResetOK)
begin
if(!reset)
tResetMagic <= 12345;
else
tResetMagic <= 0;
if(!tResetOK)
begin
regs.reg_sr <= 0;
regs.reg_pc <= 0;
regs.reg_pr <= 0;
imemAddr[31:0] <= 0;
imemRd <= 1'b1;
end
end
else
begin
regs.reg_sr <= regNextSr;
regs.reg_pc <= regNextPc;
regs.reg_pr <= regNextPr;
tPipeFlush <= tNextPipeFlush;
tPipeDsFlush <= tNextPipeDsFlush;
imemAddr[31:0] <= regNextPc[31:0];
imemRd <= 1'b1;
ifRegPc <= regNextPc;
if((tPipeFlush>1) || (tPipeDsFlush!=0))
begin
idInstWord <= 32'h0F090F09;
idRegPc <= ifRegPc;
end
else
if(tPipeFlush!=0)
begin
idInstWord <= imemRdValue[31:0];
idRegPc <= ifRegPc;
end
else
begin
idInstWord <= imemRdValue[31:0];
idRegPc <= idRegNextPc;
end
ixRegD <= idRegD;
ixRegS <= idRegS;
ixRegT <= idRegT;
ixImm <= idImm;
ixRegPc <= ixRegNextPc;
regPrPc <= regPrNextPc;
uopPc <= uopNextPc;
uopWord <= uopNextWord;
uopPcLive <= uopNextPcLive;
end
end
endmodule | module ExUop(clk, reset,
extAddr, extData,
extOE, extWR,
extNotReady); |
input clk;
input reset;
output[31:0] extAddr;
inout[31:0] extData;
output extOE;
output extWR;
input extNotReady;
reg[31:0] ifRegPc;
reg[31:0] idNextInstWord;
reg[31:0] idInstWord;
reg[6:0] idRegD;
reg[6:0] idRegS;
reg[6:0] idRegT;
reg[31:0] idImm;
reg[11:0] idUopPc;
reg[31:0] idUopWord;
reg[31:0] idRegPc;
reg[31:0] idRegNextPc;
reg[31:0] uopWord;
reg[31:0] uopNextWord;
reg[7:0] uopCmd;
reg[6:0] ixRegD;
reg[6:0] ixRegS;
reg[6:0] ixRegT;
reg[31:0] ixImm;
reg[31:0] ixRegPc;
reg[31:0] ixRegNextPc;
reg[6:0] iRegD;
reg[6:0] iRegS;
reg[6:0] iRegT;
reg[31:0] iImm;
reg[63:0] iDataD;
reg[63:0] iDataS;
reg[63:0] iDataT;
reg[63:0] tData2D;
reg[6:0] tIdReg2D;
reg tIsWr2D;
reg tIsQw2D;
reg[63:0] oData2D;
reg[6:0] oIdReg2D;
reg oIsWr2D;
reg oIsQw2D;
GpReg regs(clk,
oIsWr2D, oIsQw2D, oIdReg2D, oData2D,
iRegD, iDataD, iRegS, iDataS, iRegT, iDataT);
reg[31:0] iDataAluS;
reg[31:0] iDataAluT;
reg[31:0] tDataAluD;
reg[31:0] regSr;
reg[31:0] regNextSr;
reg[31:0] regPc;
reg[31:0] regNextPc;
reg[31:0] regPrNextPc;
reg[31:0] regPrPc;
reg[31:0] regPr;
reg[31:0] regNextPr;
reg[4:0] aluCmd;
reg[3:0] tAluSr;
ArithAlu alu1(clk, aluCmd,
iDataAluS, iDataAluT, tDataAluD, regSr[3:0], tAluSr);
reg[31:0] aguDataHeldS;
reg[31:0] aguDataNextHeldS;
reg aguHasIndex;
reg[31:0] tDataAguD;
reg[2:0] aguCmd;
reg[31:0] aguDataS;
reg[31:0] aguDataT;
MemAlu agu1(clk, aguCmd,
aguDataS, aguDataT, iImm, tDataAguD);
assign aguDataT = aguHasIndex ? iDataT[31:0] : 0;
assign aguDataS = tPostIncr ? aguDataHeldS[31:0] : iDataS[31:0];
reg fpuOpFp32;
reg[3:0] fpuCmd;
reg[3:0] tFpuSr;
reg[63:0] iDataFpuD;
reg[63:0] iDataFpuS;
reg[63:0] iDataFpuT;
reg[63:0] fpuDataD;
FpuFp64B fpu1(clk, fpuOpFp32, fpuCmd, iDataFpuS, iDataFpuT, iDataFpuD, fpuDataD,
regSr[3:0], tFpuSr);
reg memRd;
reg memWr;
reg[2:0] memCmd;
reg[31:0] memAddr;
reg[63:0] memRdValue;
reg[63:0] memWrValue;
reg imemRd;
reg[31:0] imemAddr;
wire[63:0] imemRdValue;
wire memHold;
MemTile2 mem1(clk, reset,
memRd, memWr, memCmd,
memAddr, memRdValue, memWrValue,
imemRd, imemAddr, imemRdValue,
extAddr, extData, extOE, extWR,
memHold, extNotReady);
reg[1:0] idStepPc;
DecOp dec1(clk, idInstWord, regSr[31:0],
idRegD, idRegS, idRegT, idImm, idStepPc, idUopPc, idUopWord);
reg[31:0] tRegStepPc;
reg[11:0] uopPc;
reg[11:0] uopNextPc;
reg uopPcLive;
reg uopNextPcLive;
reg[15:0] tResetMagic;
reg tResetOK;
reg tHold;
reg[2:0] tPipeFlush;
reg[2:0] tNextPipeFlush;
reg tPipeDsFlush;
reg tNextPipeDsFlush;
reg[2:0] tPipeHold;
reg[2:0] tNextPipeHold;
reg tPostIncr;
reg tNextPostIncr;
reg tPostIncrDn;
reg tNextPostIncrDn;
reg tPostIncrDir;
reg tNextPostIncrDir;
assign tResetOK = !reset && (tResetMagic==12345);
assign tHold = !tResetOK && !memHold;
assign regPc = regs.reg_pc;
assign regPr = regs.reg_pr;
assign regSr = regs.reg_sr;
always @ (clk)
begin
if(!tResetOK)
begin
$display("Reset");
end
else if(tHold)
begin
$display("Hold");
end
else
if((memHold==0) && tResetOK)
begin
if(!uopPcLive)
begin
idNextInstWord=imemRdValue[31:0];
$display("1F: PC=%X Op=%X", ifRegPc, idNextInstWord);
if(imemRdValue==0)
idNextInstWord=32'hFFFF_FFFF;
idRegNextPc=ifRegPc;
end
else
begin
idNextInstWord=idInstWord;
end
tRegStepPc[31:3]=29'h0;
tRegStepPc[2:1]=idStepPc[1:0];
tRegStepPc[0]=1'b0;
if(tPipeFlush>1)
begin
$display("2D-0/F: PC=%X Op=%X St=%X", idRegPc, idInstWord, idStepPc);
$display("2D-1/F: uPC=%X uOp=%X", idUopPc, idUopWord);
regNextPc=regPc;
regPrNextPc=regPc+4;
uopNextPc=idUopPc;
uopNextWord=idUopWord;
ixRegNextPc=idRegPc;
end
else
if(!uopPcLive)
begin
$display("2D-0: PC=%X Op=%X St=%X", idRegPc, idInstWord, idStepPc);
$display("2D-1: uPC=%X uOp=%X", idUopPc, idUopWord);
if(idInstWord==32'hFFFF_FFFF)
$finish(0);
uopNextPc=idUopPc;
uopNextWord=idUopWord;
regNextPc=ifRegPc+tRegStepPc;
regPrNextPc=ifRegPc+tRegStepPc;
ixRegNextPc=idRegPc;
end
else
begin
if(!memHold)
begin
$display("2D-2 uPC=%X uOp=%X", idUopPc, idUopWord);
end
regNextPc=regPc;
regPrNextPc=regPc+4;
end
uopCmd=uopWord[31:24];
if(tPipeFlush!=0)
begin
tNextPipeFlush=tPipeFlush-1;
tNextPipeDsFlush=tPipeDsFlush;
end
else
begin
tNextPipeFlush=0;
tNextPipeDsFlush=0;
end
if(tPipeHold!=0)
tNextPipeHold=tPipeHold-1;
else
tNextPipeHold=0;
$display("3E-0: PC=%X", ixRegPc);
$display("3E-1 uPC=%X uOp=%X", uopPc, uopWord);
if(uopWord[23]==0)
begin
uopNextPcLive=0;
end
else
begin
uopNextPc=uopPc+1;
uopNextWord=dec1.uopPgm[uopNextPc];
uopNextPcLive=1;
end
if(tPipeFlush!=0)
uopNextPcLive=0;
case(uopWord[22:21])
2'b00:
begin
iRegD = ixRegD;
iRegS = ixRegS;
iRegT = ixRegT;
iImm = ixImm;
end
2'b10:
begin
iRegD = uopWord[20:14];
iRegS = uopWord[13: 7];
iRegT = uopWord[ 6: 0];
iImm = ixImm;
end
2'b01:
begin
if(uopWord[20])
begin
iRegS = ixRegS;
iRegT = ixRegT;
iRegD[6:4] = 0;
iRegD[3:0] = uopWord[19:16];
iImm[31:16] = uopWord[15] ? 16'hFFFF : 16'h0000 ;
iImm[15:0] = uopWord[15:0];
end
else
begin
iRegD = ixRegD;
iRegS = ixRegS;
iRegT = ixRegT;
iImm[31:20] = uopWord[19] ? 12'hFFF : 12'h000 ;
iImm[19:0] = uopWord[19:0];
end
end
2'b11:
begin
iRegD[6:4] = 0;
iRegD[3:0] = uopWord[19:16];
iRegS[6:4] = 0;
iRegS[3:0] = uopWord[15:12];
iRegT[6:4] = 0;
iRegT[3:0] = uopWord[11: 8];
iImm[31:8] = (uopWord[20] && uopWord[7]) ?
24'hFFFFFF : 24'h000000 ;
iImm[ 7:0] = uopWord[7:0];
end
endcase
iDataAluS=iDataS[31:0];
iDataAluT=iDataT[31:0];
iDataFpuD=iDataD[63:0];
iDataFpuS=iDataS[63:0];
iDataFpuT=iDataT[63:0];
if(iRegS==regs.REG_ZZR)
begin
iDataAluS[31: 0] = 0;
end
if(iRegT==regs.REG_IMM)
begin
iDataAluT[31: 0] = iImm;
end
tData2D=iDataD;
tIsWr2D=1'b0;
tIsQw2D=1'b0;
regNextSr=regSr;
regNextPr=regPr;
tIdReg2D=iRegD;
aguHasIndex = (iRegT[3:0]!=15);
aguDataNextHeldS = aguDataHeldS;
aluCmd=0;
aguCmd=0;
memCmd=0;
fpuCmd=0;
fpuOpFp32=0;
tNextPostIncr=0;
tNextPostIncrDn=0;
$display("Uop Cmd %X", uopCmd);
case(uopCmd[7:4])
4'h0:
begin
if(uopCmd[3:0]==4'h0)
begin
uopNextPcLive = 0;
end
else
begin
aluCmd=uopCmd[4:0];
tData2D={32'h0, tDataAluD};
tIsWr2D=1'b1;
$display("EX ALU.L Op=%X D=%X(%X) S=%X(%X) T=%X(%X) -> %X",
aluCmd,
iRegD, iDataD,
iRegS, iDataAluS,
iRegT, iDataAluT,
tDataAluD);
end
end
4'h1:
aluCmd=uopCmd[4:0];
tData2D={32'h0, tDataAluD};
tIsWr2D=aluCmd<alu1.UOP_TEST;
regNextSr[31:1]=regSr[31:1];
regNextSr[0]=tAluSr[0];
$display("EX ALU.L Op=%X D=%X(%X) S=%X(%X) T=%X(%X) -> %X",
aluCmd,
iRegD, iDataD,
iRegS, iDataAluS,
iRegT, iDataAluT,
tDataAluD);
begin
end
4'h2:
begin
if(uopCmd[3:0]==4'h0)
begin
regNextPc = regPrPc + (iDataAluT*2);
tNextPipeFlush = 2;
$display("3E BRA PC=%X -> %X (Disp=%X)",
regPrPc, regNextPc, iDataAluT);
end
else
begin
if(iRegT==regs.REG_R0)
aguCmd=agu1.MD_BYTE;
else
aguCmd=uopCmd[2:0];
if(uopCmd[3])
begin
tIdReg2D=iRegS;
aguHasIndex = 0;
end
tData2D={32'h0, tDataAguD};
tIsWr2D=1'b1;
end
end
4'h3:
begin
if(uopCmd[3:0]==4'h0)
begin
regNextPr = regPrNextPc;
regNextPc = regPrNextPc + (iDataAluT*2);
tNextPipeFlush = 2;
$display("3E BSR PC=%X -> %X (Disp=%X)",
regPrPc, regNextPc, iDataAluT);
end
else
begin
if(iRegT==regs.REG_R0)
aguCmd=agu1.MD_BYTE;
else
aguCmd=uopCmd[2:0];
memCmd=uopCmd[2:0];
memAddr=tDataAguD[31:0];
tIsWr2D=uopCmd[3];
memWrValue=iDataD;
tData2D=memRdValue;
if(uopCmd[3])
begin
memRd=1'b0;
memWr=1'b1;
end
else
begin
memRd=1'b1;
memWr=1'b0;
end
if(tPipeHold==0)
tNextPipeHold=1;
tPostNextIncr=uopWord[17];
tPostNextIncrDir=uopWord[16];
if(tPostIncr)
begin
if(tPipeHold==0)
tNextPipeHold=2;
tNextPostIncrDn=1;
if(!tPostIncrDn)
begin
tIsWr2D=1'b1;
tIsQw2D=1'b0;
tIdReg2D=iRegS;
if(tPostNextIncrDir)
begin
case(memCmd)
3'h1: tData2D=aguDataHeldS-1;
3'h2: tData2D=aguDataHeldS-2;
3'h3: tData2D=aguDataHeldS-4;
3'h4: tData2D=aguDataHeldS-8;
endcase
end
else
begin
case(memCmd)
3'h1: tData2D=aguDataHeldS+1;
3'h2: tData2D=aguDataHeldS+2;
3'h3: tData2D=aguDataHeldS+4;
3'h4: tData2D=aguDataHeldS+8;
endcase
end
end
end
else
begin
aguDataNextHeldS = iDataS;
end
end
end
4'h4:
begin
if(uopCmd[3:0]==4'h0)
begin
end
else
begin
fpuCmd=uopCmd[3:0];
tData2D=fpuDataD;
tIsWr2D=1;
if((fpuCmd!=fpu1.OP_CMPEQ) || (fpuCmd!=fpu1.OP_CMPGT))
begin
tIsWr2D=0;
regNextSr[31:1]=regSr[31:1];
regNextSr[0]=tFpuSr[0];
end
end
end
4'h5:
begin
if(uopCmd[3:0]==4'h0)
begin
if((regSr[0]^uopWord[16])==0)
begin
regNextPc = regPrPc + (iDataAluT*2);
tNextPipeFlush = 2;
tNextPipeDsFlush = uopWord[17];
$display("3E BRTF PC=%X -> %X (Disp=%X)",
regPrPc, regNextPc, iDataAluT);
end
end
else
begin
fpuCmd=uopCmd[3:0];
tData2D=fpuDataD;
tIsWr2D=1;
if((fpuCmd!=fpu1.OP_CMPEQ) || (fpuCmd!=fpu1.OP_CMPGT))
begin
tIsWr2D=0;
regNextSr[31:1]=regSr[31:1];
regNextSr[0]=tFpuSr[0];
end
end
end
default: begin
end
endcase
if(uopCmd==8'h40)
begin
case(uopWord[15:12])
4'h0:
case(uopWord[3:0])
4'h0:
begin
end
4'h8:
case(uopWord[7:4])
4'h0:
regNextSr[0]=0;
4'h1:
regNextSr[0]=1;
4'h4:
case(uopWord[11:8])
4'h0: regNextSr[1]=0;
4'h1: regNextSr[12]=0;
4'h2: regNextSr[31]=0;
4'h3: begin regNextSr[31]=0; regNextSr[12]=0; end
default: regNextSr[1]=0;
endcase
4'h5:
case(uopWord[11:8])
4'h0: regNextSr[1]=1;
4'h1: regNextSr[12]=1;
4'h2: regNextSr[31]=1;
4'h3: begin regNextSr[31]=1; regNextSr[12]=1; end
default: regNextSr[1]=1;
endcase
4'h6:
regNextSr[0]=!regSr[0];
default: begin end
endcase
4'h9:
case(uopWord[7:4])
4'h0:
begin end
4'h1:
begin
regNextSr[0]=0;
regNextSr[8]=0;
regNextSr[9]=0;
end
4'h2:
begin
tData2D[63:0]=0;
tData2D[0]=regSr[0];
end
4'h3:
begin
regNextSr[0]=iDataT[0];
end
default: begin end
endcase
4'hB:
case(uopWord[7:4])
4'h0:
regNextPc=regPr;
4'h1:
begin end
4'h2:
begin
end
4'h3:
begin end
default: begin end
endcase
default: begin end
endcase
default: begin
end
endcase
end
end
end
always @ (negedge clk)
begin
oData2D <= tData2D;
oIsWr2D <= tIsWr2D;
oIsQw2D <= tIsQw2D;
oIdReg2D <= tIdReg2D;
end
always @ (posedge clk)
begin
tPostIncr <= tNextPostIncr;
tPostIncrDn <= tNextPostIncrDn;
tPostIncrDir <= tNextPostIncrDir;
aguDataHeldS <= aguDataNextHeldS;
tPipeHold <= tNextPipeHold;
if(memHold || (tPipeHold || tNextPipeHold) || !tResetOK)
begin
if(!reset)
tResetMagic <= 12345;
else
tResetMagic <= 0;
if(!tResetOK)
begin
regs.reg_sr <= 0;
regs.reg_pc <= 0;
regs.reg_pr <= 0;
imemAddr[31:0] <= 0;
imemRd <= 1'b1;
end
end
else
begin
regs.reg_sr <= regNextSr;
regs.reg_pc <= regNextPc;
regs.reg_pr <= regNextPr;
tPipeFlush <= tNextPipeFlush;
tPipeDsFlush <= tNextPipeDsFlush;
imemAddr[31:0] <= regNextPc[31:0];
imemRd <= 1'b1;
ifRegPc <= regNextPc;
if((tPipeFlush>1) || (tPipeDsFlush!=0))
begin
idInstWord <= 32'h0F090F09;
idRegPc <= ifRegPc;
end
else
if(tPipeFlush!=0)
begin
idInstWord <= imemRdValue[31:0];
idRegPc <= ifRegPc;
end
else
begin
idInstWord <= imemRdValue[31:0];
idRegPc <= idRegNextPc;
end
ixRegD <= idRegD;
ixRegS <= idRegS;
ixRegT <= idRegT;
ixImm <= idImm;
ixRegPc <= ixRegNextPc;
regPrPc <= regPrNextPc;
uopPc <= uopNextPc;
uopWord <= uopNextWord;
uopPcLive <= uopNextPcLive;
end
end
endmodule | 2 |
142,515 | data/full_repos/permissive/99182535/bjx1core32/FpuFp32_Mul.v | 99,182,535 | FpuFp32_Mul.v | v | 76 | 33 | [] | [] | [] | [(1, 75)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/99182535/bjx1core32/FpuFp32_Mul.v:72: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dst'\n : ... In instance FpuFp32_Mul\n dst=tDst;\n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 314,719 | module | module FpuFp32_Mul(
clk,
srca,
srcb,
dst
);
input clk;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[9:0] exa;
reg[9:0] exb;
reg[9:0] exc;
reg[47:0] tFracA;
reg[47:0] tFracB;
reg[47:0] tFracC;
reg[22:0] tFracC2;
reg[31:0] tDst;
always @ (clk) begin
sgna=srca[31];
sgnb=srcb[31];
exa[7:0]=srca[30:23];
exb[7:0]=srcb[30:23];
exa[9:8]=0;
exb[9:8]=0;
sgnc=sgna^sgnb;
tFracA[47:23]=25'h1;
tFracB[47:23]=25'h1;
tFracA[22:0]=srca[22:0];
tFracB[22:0]=srcb[22:0];
tFracC=tFracA*tFracB;
if(tFracC[47])
begin
tFracC2[22:0]=tFracC[46:24];
exc=exa+exb-126;
end
begin
tFracC2[22:0]=tFracC[45:23];
exc=exa+exb-127;
end
if(exc[9])
begin
tDst=0;
end
else
if(exc[8])
begin
tDst[31]=sgnc;
tDst[30:0]=31'h7F80_0000;
end
else
begin
tDst[31]=sgnc;
tDst[30:23]=exc[7:0];
tDst[22: 0]=tFracC2[22:0];
end
dst=tDst;
end
endmodule | module FpuFp32_Mul(
clk,
srca,
srcb,
dst
); |
input clk;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[9:0] exa;
reg[9:0] exb;
reg[9:0] exc;
reg[47:0] tFracA;
reg[47:0] tFracB;
reg[47:0] tFracC;
reg[22:0] tFracC2;
reg[31:0] tDst;
always @ (clk) begin
sgna=srca[31];
sgnb=srcb[31];
exa[7:0]=srca[30:23];
exb[7:0]=srcb[30:23];
exa[9:8]=0;
exb[9:8]=0;
sgnc=sgna^sgnb;
tFracA[47:23]=25'h1;
tFracB[47:23]=25'h1;
tFracA[22:0]=srca[22:0];
tFracB[22:0]=srcb[22:0];
tFracC=tFracA*tFracB;
if(tFracC[47])
begin
tFracC2[22:0]=tFracC[46:24];
exc=exa+exb-126;
end
begin
tFracC2[22:0]=tFracC[45:23];
exc=exa+exb-127;
end
if(exc[9])
begin
tDst=0;
end
else
if(exc[8])
begin
tDst[31]=sgnc;
tDst[30:0]=31'h7F80_0000;
end
else
begin
tDst[31]=sgnc;
tDst[30:23]=exc[7:0];
tDst[22: 0]=tFracC2[22:0];
end
dst=tDst;
end
endmodule | 2 |
142,518 | data/full_repos/permissive/99182535/bjx1core32/FpuFp64To32.v | 99,182,535 | FpuFp64To32.v | v | 51 | 26 | [] | [] | [] | null | line:21: before: "&&" | data/verilator_xmls/c411df0e-165b-48f7-aa23-607f3a969786.xml | null | 314,724 | module | module FpuFp64To32(
clk,
enable,
src,
dst
);
input clk;
input enable;
input[63:0] src;
output[31:0] dst;
reg[11:0] exa;
reg[11:0] exb;
reg[31:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
exa[11]=0;
exa[10:0]=src[62:52];
exb=exa-(1023-127);
if(exb[11:8]==0)
begin
tDst[31]=src[63];
tDst[30:23]=exb[7:0];
tDst[22:0]=src[51:29];
end
else
if(exb[11])
begin
tDst[31:0]=0;
end
else
begin
tDst[31]=src[63];
tDst[30:23]=8'hFF;
tDst[22:0]=23'h80_0000;
end
end
endmodule | module FpuFp64To32(
clk,
enable,
src,
dst
); |
input clk;
input enable;
input[63:0] src;
output[31:0] dst;
reg[11:0] exa;
reg[11:0] exb;
reg[31:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
exa[11]=0;
exa[10:0]=src[62:52];
exb=exa-(1023-127);
if(exb[11:8]==0)
begin
tDst[31]=src[63];
tDst[30:23]=exb[7:0];
tDst[22:0]=src[51:29];
end
else
if(exb[11])
begin
tDst[31:0]=0;
end
else
begin
tDst[31]=src[63];
tDst[30:23]=8'hFF;
tDst[22:0]=23'h80_0000;
end
end
endmodule | 2 |
142,520 | data/full_repos/permissive/99182535/bjx1core32/FpuFp64_Mul.v | 99,182,535 | FpuFp64_Mul.v | v | 107 | 38 | [] | [] | [] | null | line:46: before: "&&" | data/verilator_xmls/5095956b-acdb-4e93-8682-a9e24428c1d4.xml | null | 314,727 | module | module FpuFp64_Mul(
clk,
enable,
srca,
srcb,
dst
);
input clk;
input enable;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[12:0] exa;
reg[12:0] exb;
reg[12:0] exc;
`ifdef PRECISE_FMUL
reg[105:0] tFracA;
reg[105:0] tFracB;
reg[105:0] tFracC1;
reg[63:0] tFracC;
`else
reg[63:0] tFracA;
reg[63:0] tFracB;
reg[63:0] tFracC;
`endif
reg[51:0] tFracC2;
reg[63:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
sgna=srca[63];
sgnb=srcb[63];
exa[10:0]=srca[62:52];
exb[10:0]=srcb[62:52];
exa[12:11]=0;
exb[12:11]=0;
sgnc=sgna^sgnb;
`ifdef PRECISE_FMUL
tFracA[105:52]=1;
tFracB[105:52]=1;
`else
tFracA[63:52]=1;
tFracB[63:52]=1;
`endif
tFracA[51:0]=srca[51:0];
tFracB[51:0]=srcb[51:0];
`ifdef PRECISE_FMUL
tFracC1=tFracA*tFracB;
tFracC=tFracC1[105:42]+64'h3FF;
`else
tFracC=(tFracA>>21)*(tFracB>>21);
`endif
if(tFracC[63])
begin
tFracC2[51:0]=tFracC[62:11];
exc=exa+exb-1022;
end
else
begin
tFracC2[51:0]=tFracC[61:10];
exc=exa+exb-1023;
end
if(exc[12])
begin
tDst=0;
end
else
if(exc[11])
begin
tDst[63]=sgnc;
tDst[62:0]=63'h7FF0_0000_0000_0000;
end
else
begin
tDst[63]=sgnc;
tDst[62:52]=exc[10:0];
tDst[51: 0]=tFracC2[51:0];
end
end
endmodule | module FpuFp64_Mul(
clk,
enable,
srca,
srcb,
dst
); |
input clk;
input enable;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[12:0] exa;
reg[12:0] exb;
reg[12:0] exc;
`ifdef PRECISE_FMUL
reg[105:0] tFracA;
reg[105:0] tFracB;
reg[105:0] tFracC1;
reg[63:0] tFracC;
`else
reg[63:0] tFracA;
reg[63:0] tFracB;
reg[63:0] tFracC;
`endif
reg[51:0] tFracC2;
reg[63:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
sgna=srca[63];
sgnb=srcb[63];
exa[10:0]=srca[62:52];
exb[10:0]=srcb[62:52];
exa[12:11]=0;
exb[12:11]=0;
sgnc=sgna^sgnb;
`ifdef PRECISE_FMUL
tFracA[105:52]=1;
tFracB[105:52]=1;
`else
tFracA[63:52]=1;
tFracB[63:52]=1;
`endif
tFracA[51:0]=srca[51:0];
tFracB[51:0]=srcb[51:0];
`ifdef PRECISE_FMUL
tFracC1=tFracA*tFracB;
tFracC=tFracC1[105:42]+64'h3FF;
`else
tFracC=(tFracA>>21)*(tFracB>>21);
`endif
if(tFracC[63])
begin
tFracC2[51:0]=tFracC[62:11];
exc=exa+exb-1022;
end
else
begin
tFracC2[51:0]=tFracC[61:10];
exc=exa+exb-1023;
end
if(exc[12])
begin
tDst=0;
end
else
if(exc[11])
begin
tDst[63]=sgnc;
tDst[62:0]=63'h7FF0_0000_0000_0000;
end
else
begin
tDst[63]=sgnc;
tDst[62:52]=exc[10:0];
tDst[51: 0]=tFracC2[51:0];
end
end
endmodule | 2 |
142,524 | data/full_repos/permissive/99182535/bjx1core32/MemTile.v | 99,182,535 | MemTile.v | v | 169 | 46 | [] | [] | [] | null | line:21: before: "]" | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/99182535/bjx1core32/MemTile.v:91: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rdValue'\n : ... In instance MemTile\n rdValue=rdtValue;\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/99182535/bjx1core32/MemTile.v:108: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rdValue'\n : ... In instance MemTile\n rdValue=rdtValue;\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 314,732 | module | module MemTile(
clk,
opRd,
opWr,
opMode,
memAddr,
rdValue,
wrValue
);
input clk;
input opRd;
input opWr;
input[2:0] opMode;
input[47:0] memAddr;
input[63:0] wrValue;
output[63:0] rdValue;
reg[11:0] tileIdx;
reg[31:0] tile[4096];
reg[63:0] rdtTBlock;
reg[63:0] rdtValue;
reg[63:0] rdtValue2;
reg[63:0] rdtTBlock2;
reg[63:0] rdtMask;
reg[63:0] rdtMask2;
reg[4:0] rdtShl;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_UBYTE = 3'b110;
parameter[2:0] MD_UWORD = 3'b111;
always @ (opRd or opWr)
begin
tileIdx = memAddr[13:2];
rdtShl[4:3]=memAddr[1:0];
rdtShl[2:0]=3'b000;
end
always @ (opRd)
begin
if(opRd)
begin
rdtTBlock[31: 0]=tile[tileIdx ];
rdtTBlock[63:32]=tile[tileIdx+1];
rdtValue=rdtTBlock>>rdtShl;
case(opMode)
MD_BYTE:
begin
rdValue[7:0]=rdtValue[7:0];
rdValue[63:8]=rdtValue[7]?
56'hFFFF_FFFF_FFFF_FF :
56'h0000_0000_0000_00 ;
end
MD_WORD:
begin
rdValue[15:0]=rdtValue[15:0];
rdValue[63:16]=rdtValue[15]?
48'hFFFF_FFFF_FFFF :
48'h0000_0000_0000 ;
end
MD_DWORD:
begin
rdValue[31:0]=rdtValue[31:0];
rdValue[63:32]=rdtValue[31]?
32'hFFFF_FFFF :
32'h0000_0000 ;
end
MD_QWORD:
begin
rdValue=rdtValue;
end
MD_UBYTE:
begin
rdValue[7:0]=rdtValue[7:0];
rdValue[63:8]=56'h0000_0000_0000_00 ;
end
MD_UWORD:
begin
rdValue[15:0]=rdtValue[15:0];
rdValue[63:16]=48'h0000_0000_0000 ;
end
default:
begin
rdValue=rdtValue;
end
endcase
end
end
always @ (opWr)
begin
if(opWr)
begin
case(opMode)
MD_BYTE:
begin
rdtValue2[7:0]=wrValue[7:0];
rdtValue2[63:8]=56'h0000_0000_0000_00 ;
rdtMask2=64'h0000_0000_0000_00FF ;
end
MD_WORD:
begin
rdtValue2[15:0]=wrValue[15:0];
rdtValue2[63:16]=48'h0000_0000_0000 ;
rdtMask2=64'h0000_0000_0000_FFFF ;
end
MD_DWORD:
begin
rdtValue2[31:0]=wrValue[31:0];
rdtValue2[63:32]=32'h0000_0000 ;
rdtMask2=64'h0000_0000_FFFF_FFFF ;
end
MD_QWORD:
begin
rdtValue2[63:0]=wrValue[63:0];
rdtMask2=64'hFFFF_FFFF_FFFF_FFFF ;
end
default:
begin
rdtValue2=64'h0000_0000_0000_0000 ;
rdtMask2=64'h0000_0000_0000_0000 ;
end
endcase
rdtValue=rdtValue2<<rdtShl;
rdtMask=rdtMask2<<rdtShl;
rdtTBlock[31: 0]=tile[tileIdx ];
rdtTBlock[63:32]=tile[tileIdx+1];
rdtTBlock2=(rdtTBlock&(~rdtMask))|rdtValue;
tile[tileIdx ]=rdtTBlock[31: 0];
tile[tileIdx+1]=rdtTBlock[63:32];
end
end
always @ (posedge clk)
begin
end
endmodule | module MemTile(
clk,
opRd,
opWr,
opMode,
memAddr,
rdValue,
wrValue
); |
input clk;
input opRd;
input opWr;
input[2:0] opMode;
input[47:0] memAddr;
input[63:0] wrValue;
output[63:0] rdValue;
reg[11:0] tileIdx;
reg[31:0] tile[4096];
reg[63:0] rdtTBlock;
reg[63:0] rdtValue;
reg[63:0] rdtValue2;
reg[63:0] rdtTBlock2;
reg[63:0] rdtMask;
reg[63:0] rdtMask2;
reg[4:0] rdtShl;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_UBYTE = 3'b110;
parameter[2:0] MD_UWORD = 3'b111;
always @ (opRd or opWr)
begin
tileIdx = memAddr[13:2];
rdtShl[4:3]=memAddr[1:0];
rdtShl[2:0]=3'b000;
end
always @ (opRd)
begin
if(opRd)
begin
rdtTBlock[31: 0]=tile[tileIdx ];
rdtTBlock[63:32]=tile[tileIdx+1];
rdtValue=rdtTBlock>>rdtShl;
case(opMode)
MD_BYTE:
begin
rdValue[7:0]=rdtValue[7:0];
rdValue[63:8]=rdtValue[7]?
56'hFFFF_FFFF_FFFF_FF :
56'h0000_0000_0000_00 ;
end
MD_WORD:
begin
rdValue[15:0]=rdtValue[15:0];
rdValue[63:16]=rdtValue[15]?
48'hFFFF_FFFF_FFFF :
48'h0000_0000_0000 ;
end
MD_DWORD:
begin
rdValue[31:0]=rdtValue[31:0];
rdValue[63:32]=rdtValue[31]?
32'hFFFF_FFFF :
32'h0000_0000 ;
end
MD_QWORD:
begin
rdValue=rdtValue;
end
MD_UBYTE:
begin
rdValue[7:0]=rdtValue[7:0];
rdValue[63:8]=56'h0000_0000_0000_00 ;
end
MD_UWORD:
begin
rdValue[15:0]=rdtValue[15:0];
rdValue[63:16]=48'h0000_0000_0000 ;
end
default:
begin
rdValue=rdtValue;
end
endcase
end
end
always @ (opWr)
begin
if(opWr)
begin
case(opMode)
MD_BYTE:
begin
rdtValue2[7:0]=wrValue[7:0];
rdtValue2[63:8]=56'h0000_0000_0000_00 ;
rdtMask2=64'h0000_0000_0000_00FF ;
end
MD_WORD:
begin
rdtValue2[15:0]=wrValue[15:0];
rdtValue2[63:16]=48'h0000_0000_0000 ;
rdtMask2=64'h0000_0000_0000_FFFF ;
end
MD_DWORD:
begin
rdtValue2[31:0]=wrValue[31:0];
rdtValue2[63:32]=32'h0000_0000 ;
rdtMask2=64'h0000_0000_FFFF_FFFF ;
end
MD_QWORD:
begin
rdtValue2[63:0]=wrValue[63:0];
rdtMask2=64'hFFFF_FFFF_FFFF_FFFF ;
end
default:
begin
rdtValue2=64'h0000_0000_0000_0000 ;
rdtMask2=64'h0000_0000_0000_0000 ;
end
endcase
rdtValue=rdtValue2<<rdtShl;
rdtMask=rdtMask2<<rdtShl;
rdtTBlock[31: 0]=tile[tileIdx ];
rdtTBlock[63:32]=tile[tileIdx+1];
rdtTBlock2=(rdtTBlock&(~rdtMask))|rdtValue;
tile[tileIdx ]=rdtTBlock[31: 0];
tile[tileIdx+1]=rdtTBlock[63:32];
end
end
always @ (posedge clk)
begin
end
endmodule | 2 |
142,526 | data/full_repos/permissive/99182535/bjx1core32/MemTLB.v | 99,182,535 | MemTLB.v | v | 320 | 68 | [] | [] | [] | null | line:13: before: "parameter" | data/verilator_xmls/fbc74d7c-dde2-4342-9073-890846f66c07.xml | null | 314,735 | module | module MemTLB(
clk,
reset,
opMode,
opReg,
inAddr,
outAddr,
outTlbSr
);
input clk;
input reset;
input[2:0] opMode;
input[2:0] opReg;
input[63:0] inAddr;
output[63:0] outAddr;
output[7:0] outTlbSr;
reg[63:0] tOutAddr;
reg[7:0] tHashIdx0;
reg[5:0] tHashIdx;
reg[35:0] tlbPageSrcA[63:0];
reg[35:0] tlbPageSrcB[63:0];
reg[35:0] tlbPageSrcC[63:0];
reg[35:0] tlbPageSrcD[63:0];
reg[27:0] tlbPageDstA[63:0];
reg[27:0] tlbPageDstB[63:0];
reg[27:0] tlbPageDstC[63:0];
reg[27:0] tlbPageDstD[63:0];
reg[63:0] regPTEH;
reg[63:0] regPTEL;
reg[63:0] regTTB;
reg[63:0] regTEA;
reg[63:0] regMMUCR;
reg[63:0] regNextPTEH;
reg[63:0] regNextPTEL;
reg[63:0] regNextTTB;
reg[63:0] regNextTEA;
reg[63:0] regNextMMUCR;
reg[7:0] tTlbSr;
reg tlbMiss;
reg[2:0] tlbSwap;
reg[35:0] tlbSwapSrcA;
reg[35:0] tlbSwapSrcB;
reg[35:0] tlbSwapSrcC;
reg[35:0] tlbSwapSrcD;
reg[27:0] tlbSwapDstA;
reg[27:0] tlbSwapDstB;
reg[27:0] tlbSwapDstC;
reg[27:0] tlbSwapDstD;
reg[35:0] tlbSwapSrcE;
reg[27:0] tlbSwapDstE;
assign outAddr = tOutAddr;
assign outTlbSr = tTlbSr;
always @ (opMode)
begin
tlbMiss = 0;
tlbSwap = 0;
tTlbSr = 0;
regNextPTEH = regPTEH;
regNextPTEL = regPTEL;
regNextTTB = regTTB;
regNextTEA = regTEA;
regNextMMUCR = regMMUCR;
if(opMode==TLB_OPMODE_NONE)
begin
tlbMiss = 0;
end
else
if(opMode==TLB_OPMODE_LOOKUP)
begin
tHashIdx0=
inAddr[19:12]+inAddr[26:19]+
inAddr[33:26]+inAddr[40:33]+
inAddr[47:40]+3;
tHashIdx=tHashIdx0[7:2];
tlbMiss = 1;
tlbSwapSrcA=tlbPageSrcA[tHashIdx];
tlbSwapDstA=tlbPageDstA[tHashIdx];
tlbSwapSrcB=tlbPageSrcB[tHashIdx];
tlbSwapDstB=tlbPageDstB[tHashIdx];
tlbSwapSrcC=tlbPageSrcC[tHashIdx];
tlbSwapDstC=tlbPageDstC[tHashIdx];
tlbSwapSrcD=tlbPageSrcD[tHashIdx];
tlbSwapDstD=tlbPageDstD[tHashIdx];
if((inAddr[47:40]==8'h80) ||
(regMMUCR[0]==0) ||
(inAddr[61]!=inAddr[63]))
begin
tOutAddr[63:40] = 0;
tOutAddr[39: 0] = inAddr[39:0];
tlbMiss = 0;
end
else
begin
if(inAddr[47:12]==tlbSwapSrcA[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstA[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 0;
end
else if(inAddr[47:12]==tlbSwapSrcB[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstB[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 1;
end
else if(inAddr[47:12]==tlbSwapSrcC[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstC[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 2;
end
else if(inAddr[47:12]==tlbSwapSrcD[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstD[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 3;
end
end
end
else
if(opMode==TLB_OPMODE_GETREG)
begin
case(opReg)
3'h0:
begin
tOutAddr = 0;
tlbMiss = 0;
end
3'h1:
begin
tOutAddr = regPTEH;
tlbMiss = 0;
end
3'h2:
begin
tOutAddr = regPTEL;
tlbMiss = 0;
end
3'h3:
begin
tOutAddr = regTTB;
tlbMiss = 0;
end
3'h4:
begin
tOutAddr = regTEA;
tlbMiss = 0;
end
3'h5:
begin
tOutAddr = regMMUCR;
tlbMiss = 0;
end
default:
begin
tOutAddr = 0;
tlbMiss = 1;
end
endcase
end
else
if(opMode==TLB_OPMODE_SETREG)
begin
case(opReg)
3'h0:
begin
tOutAddr = 0;
tlbMiss = 0;
end
3'h1:
begin
regNextPTEH = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h2:
begin
regNextPTEL = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h3:
begin
regNextTTB = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h4:
begin
regNextTEA = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h5:
begin
regNextMMUCR = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
default:
begin
tOutAddr = 0;
tlbMiss = 1;
end
endcase
end
else
if(opMode==TLB_OPMODE_LDTLB)
begin
tHashIdx0=
regPTEH[19:12]+regPTEH[26:19]+
regPTEH[33:26]+regPTEH[40:33]+
regPTEH[47:40]+3;
tHashIdx=tHashIdx0[7:2];
tlbSwapSrcE[35:0] = regPTEH[47:12];
tlbSwapDstE[27:0] = regPTEL[39:12];
tlbSwap = 4;
end
tTlbSr[0] = tlbMiss;
end
always @ (posedge clk)
begin
regPTEH <= regNextPTEH;
regPTEL <= regNextPTEL;
regTTB <= regNextTTB;
regTEA <= regNextTEA;
regMMUCR <= regNextMMUCR;
case(tlbSwap)
0: begin end
1: begin
tlbPageSrcA[tHashIdx] <= tlbSwapSrcB;
tlbPageDstA[tHashIdx] <= tlbSwapDstB;
tlbPageSrcB[tHashIdx] <= tlbSwapSrcA;
tlbPageDstB[tHashIdx] <= tlbSwapDstA;
end
2: begin
tlbPageSrcB[tHashIdx] <= tlbSwapSrcC;
tlbPageDstB[tHashIdx] <= tlbSwapDstC;
tlbPageSrcC[tHashIdx] <= tlbSwapSrcB;
tlbPageDstC[tHashIdx] <= tlbSwapDstB;
end
3: begin
tlbPageSrcC[tHashIdx] <= tlbSwapSrcD;
tlbPageDstC[tHashIdx] <= tlbSwapDstD;
tlbPageSrcD[tHashIdx] <= tlbSwapSrcC;
tlbPageDstD[tHashIdx] <= tlbSwapDstC;
end
4: begin
tlbPageSrcD[tHashIdx] <= tlbSwapSrcE;
tlbPageDstD[tHashIdx] <= tlbSwapDstE;
end
default: begin end
endcase
end
endmodule | module MemTLB(
clk,
reset,
opMode,
opReg,
inAddr,
outAddr,
outTlbSr
); |
input clk;
input reset;
input[2:0] opMode;
input[2:0] opReg;
input[63:0] inAddr;
output[63:0] outAddr;
output[7:0] outTlbSr;
reg[63:0] tOutAddr;
reg[7:0] tHashIdx0;
reg[5:0] tHashIdx;
reg[35:0] tlbPageSrcA[63:0];
reg[35:0] tlbPageSrcB[63:0];
reg[35:0] tlbPageSrcC[63:0];
reg[35:0] tlbPageSrcD[63:0];
reg[27:0] tlbPageDstA[63:0];
reg[27:0] tlbPageDstB[63:0];
reg[27:0] tlbPageDstC[63:0];
reg[27:0] tlbPageDstD[63:0];
reg[63:0] regPTEH;
reg[63:0] regPTEL;
reg[63:0] regTTB;
reg[63:0] regTEA;
reg[63:0] regMMUCR;
reg[63:0] regNextPTEH;
reg[63:0] regNextPTEL;
reg[63:0] regNextTTB;
reg[63:0] regNextTEA;
reg[63:0] regNextMMUCR;
reg[7:0] tTlbSr;
reg tlbMiss;
reg[2:0] tlbSwap;
reg[35:0] tlbSwapSrcA;
reg[35:0] tlbSwapSrcB;
reg[35:0] tlbSwapSrcC;
reg[35:0] tlbSwapSrcD;
reg[27:0] tlbSwapDstA;
reg[27:0] tlbSwapDstB;
reg[27:0] tlbSwapDstC;
reg[27:0] tlbSwapDstD;
reg[35:0] tlbSwapSrcE;
reg[27:0] tlbSwapDstE;
assign outAddr = tOutAddr;
assign outTlbSr = tTlbSr;
always @ (opMode)
begin
tlbMiss = 0;
tlbSwap = 0;
tTlbSr = 0;
regNextPTEH = regPTEH;
regNextPTEL = regPTEL;
regNextTTB = regTTB;
regNextTEA = regTEA;
regNextMMUCR = regMMUCR;
if(opMode==TLB_OPMODE_NONE)
begin
tlbMiss = 0;
end
else
if(opMode==TLB_OPMODE_LOOKUP)
begin
tHashIdx0=
inAddr[19:12]+inAddr[26:19]+
inAddr[33:26]+inAddr[40:33]+
inAddr[47:40]+3;
tHashIdx=tHashIdx0[7:2];
tlbMiss = 1;
tlbSwapSrcA=tlbPageSrcA[tHashIdx];
tlbSwapDstA=tlbPageDstA[tHashIdx];
tlbSwapSrcB=tlbPageSrcB[tHashIdx];
tlbSwapDstB=tlbPageDstB[tHashIdx];
tlbSwapSrcC=tlbPageSrcC[tHashIdx];
tlbSwapDstC=tlbPageDstC[tHashIdx];
tlbSwapSrcD=tlbPageSrcD[tHashIdx];
tlbSwapDstD=tlbPageDstD[tHashIdx];
if((inAddr[47:40]==8'h80) ||
(regMMUCR[0]==0) ||
(inAddr[61]!=inAddr[63]))
begin
tOutAddr[63:40] = 0;
tOutAddr[39: 0] = inAddr[39:0];
tlbMiss = 0;
end
else
begin
if(inAddr[47:12]==tlbSwapSrcA[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstA[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 0;
end
else if(inAddr[47:12]==tlbSwapSrcB[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstB[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 1;
end
else if(inAddr[47:12]==tlbSwapSrcC[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstC[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 2;
end
else if(inAddr[47:12]==tlbSwapSrcD[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstD[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 3;
end
end
end
else
if(opMode==TLB_OPMODE_GETREG)
begin
case(opReg)
3'h0:
begin
tOutAddr = 0;
tlbMiss = 0;
end
3'h1:
begin
tOutAddr = regPTEH;
tlbMiss = 0;
end
3'h2:
begin
tOutAddr = regPTEL;
tlbMiss = 0;
end
3'h3:
begin
tOutAddr = regTTB;
tlbMiss = 0;
end
3'h4:
begin
tOutAddr = regTEA;
tlbMiss = 0;
end
3'h5:
begin
tOutAddr = regMMUCR;
tlbMiss = 0;
end
default:
begin
tOutAddr = 0;
tlbMiss = 1;
end
endcase
end
else
if(opMode==TLB_OPMODE_SETREG)
begin
case(opReg)
3'h0:
begin
tOutAddr = 0;
tlbMiss = 0;
end
3'h1:
begin
regNextPTEH = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h2:
begin
regNextPTEL = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h3:
begin
regNextTTB = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h4:
begin
regNextTEA = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h5:
begin
regNextMMUCR = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
default:
begin
tOutAddr = 0;
tlbMiss = 1;
end
endcase
end
else
if(opMode==TLB_OPMODE_LDTLB)
begin
tHashIdx0=
regPTEH[19:12]+regPTEH[26:19]+
regPTEH[33:26]+regPTEH[40:33]+
regPTEH[47:40]+3;
tHashIdx=tHashIdx0[7:2];
tlbSwapSrcE[35:0] = regPTEH[47:12];
tlbSwapDstE[27:0] = regPTEL[39:12];
tlbSwap = 4;
end
tTlbSr[0] = tlbMiss;
end
always @ (posedge clk)
begin
regPTEH <= regNextPTEH;
regPTEL <= regNextPTEL;
regTTB <= regNextTTB;
regTEA <= regNextTEA;
regMMUCR <= regNextMMUCR;
case(tlbSwap)
0: begin end
1: begin
tlbPageSrcA[tHashIdx] <= tlbSwapSrcB;
tlbPageDstA[tHashIdx] <= tlbSwapDstB;
tlbPageSrcB[tHashIdx] <= tlbSwapSrcA;
tlbPageDstB[tHashIdx] <= tlbSwapDstA;
end
2: begin
tlbPageSrcB[tHashIdx] <= tlbSwapSrcC;
tlbPageDstB[tHashIdx] <= tlbSwapDstC;
tlbPageSrcC[tHashIdx] <= tlbSwapSrcB;
tlbPageDstC[tHashIdx] <= tlbSwapDstB;
end
3: begin
tlbPageSrcC[tHashIdx] <= tlbSwapSrcD;
tlbPageDstC[tHashIdx] <= tlbSwapDstD;
tlbPageSrcD[tHashIdx] <= tlbSwapSrcC;
tlbPageDstD[tHashIdx] <= tlbSwapDstC;
end
4: begin
tlbPageSrcD[tHashIdx] <= tlbSwapSrcE;
tlbPageDstD[tHashIdx] <= tlbSwapDstE;
end
default: begin end
endcase
end
endmodule | 2 |
142,532 | data/full_repos/permissive/99182535/bwjx1c64a/ExShad64.v | 99,182,535 | ExShad64.v | v | 208 | 56 | [] | [] | [] | [(5, 207)] | null | data/verilator_xmls/7fc2b6a1-9ecc-4091-a440-4c4977c9a0d2.xml | null | 314,744 | module | module ExShad64(
clock, reset,
valRs, valRt,
valRn, shOp
);
input clock;
input reset;
input[63:0] valRs;
input[ 7:0] valRt;
input[ 2:0] shOp;
output[63:0] valRn;
reg[63:0] tValRn;
assign valRn = tValRn;
reg[63:0] tValRol;
reg[63:0] tValRor;
reg[ 7:0] tValSh;
always @*
begin
tValRol=0;
tValRor=0;
tValRn = 0;
tValSh = 0;
case(shOp)
3'h0: begin
end
3'h1: begin
tValRol=0;
tValRor=0;
tValSh = valRt;
end
3'h2: begin
tValRol=0;
tValRor=valRs[63] ? 64'hFFFFFFFF : 64'h00000000;
tValSh = valRt;
end
3'h3: begin
tValRol=0;
tValRor=0;
tValSh = -valRt;
end
3'h4: begin
tValRol=0;
tValRor=valRs[63] ? 64'hFFFFFFFF : 64'h00000000;
tValSh = -valRt;
end
default:
begin
end
endcase
casez(tValSh)
8'b0z000000: tValRn = valRs;
8'b0z000001: tValRn = { valRs[62:0], tValRol[63 ] };
8'b0z000010: tValRn = { valRs[61:0], tValRol[63:62] };
8'b0z000011: tValRn = { valRs[60:0], tValRol[63:61] };
8'b0z000100: tValRn = { valRs[59:0], tValRol[63:60] };
8'b0z000101: tValRn = { valRs[58:0], tValRol[63:59] };
8'b0z000110: tValRn = { valRs[57:0], tValRol[63:58] };
8'b0z000111: tValRn = { valRs[56:0], tValRol[63:57] };
8'b0z001000: tValRn = { valRs[55:0], tValRol[63:56] };
8'b0z001001: tValRn = { valRs[54:0], tValRol[63:55] };
8'b0z001010: tValRn = { valRs[53:0], tValRol[63:54] };
8'b0z001011: tValRn = { valRs[52:0], tValRol[63:53] };
8'b0z001100: tValRn = { valRs[51:0], tValRol[63:52] };
8'b0z001101: tValRn = { valRs[50:0], tValRol[63:51] };
8'b0z001110: tValRn = { valRs[49:0], tValRol[63:50] };
8'b0z001111: tValRn = { valRs[48:0], tValRol[63:49] };
8'b0z010000: tValRn = { valRs[47:0], tValRol[63:48] };
8'b0z010001: tValRn = { valRs[46:0], tValRol[63:47] };
8'b0z010010: tValRn = { valRs[45:0], tValRol[63:46] };
8'b0z010011: tValRn = { valRs[44:0], tValRol[63:45] };
8'b0z010100: tValRn = { valRs[43:0], tValRol[63:44] };
8'b0z010101: tValRn = { valRs[42:0], tValRol[63:43] };
8'b0z010110: tValRn = { valRs[41:0], tValRol[63:42] };
8'b0z010111: tValRn = { valRs[40:0], tValRol[63:41] };
8'b0z011000: tValRn = { valRs[39:0], tValRol[63:40] };
8'b0z011001: tValRn = { valRs[38:0], tValRol[63:39] };
8'b0z011010: tValRn = { valRs[37:0], tValRol[63:38] };
8'b0z011011: tValRn = { valRs[36:0], tValRol[63:37] };
8'b0z011100: tValRn = { valRs[35:0], tValRol[63:36] };
8'b0z011101: tValRn = { valRs[34:0], tValRol[63:35] };
8'b0z011110: tValRn = { valRs[33:0], tValRol[63:34] };
8'b0z011111: tValRn = { valRs[32:0], tValRol[63:33] };
8'b0z100000: tValRn = { valRs[31:0], tValRol[63:32] };
8'b0z100001: tValRn = { valRs[30:0], tValRol[63:31] };
8'b0z100010: tValRn = { valRs[29:0], tValRol[63:30] };
8'b0z100011: tValRn = { valRs[28:0], tValRol[63:29] };
8'b0z100100: tValRn = { valRs[27:0], tValRol[63:28] };
8'b0z100101: tValRn = { valRs[26:0], tValRol[63:27] };
8'b0z100110: tValRn = { valRs[25:0], tValRol[63:26] };
8'b0z100111: tValRn = { valRs[24:0], tValRol[63:25] };
8'b0z101000: tValRn = { valRs[23:0], tValRol[63:24] };
8'b0z101001: tValRn = { valRs[22:0], tValRol[63:23] };
8'b0z101010: tValRn = { valRs[21:0], tValRol[63:22] };
8'b0z101011: tValRn = { valRs[20:0], tValRol[63:21] };
8'b0z101100: tValRn = { valRs[19:0], tValRol[63:20] };
8'b0z101101: tValRn = { valRs[18:0], tValRol[63:19] };
8'b0z101110: tValRn = { valRs[17:0], tValRol[63:18] };
8'b0z101111: tValRn = { valRs[16:0], tValRol[63:17] };
8'b0z110000: tValRn = { valRs[15:0], tValRol[63:16] };
8'b0z110001: tValRn = { valRs[14:0], tValRol[63:15] };
8'b0z110010: tValRn = { valRs[13:0], tValRol[63:14] };
8'b0z110011: tValRn = { valRs[12:0], tValRol[63:13] };
8'b0z110100: tValRn = { valRs[11:0], tValRol[63:12] };
8'b0z110101: tValRn = { valRs[10:0], tValRol[63:11] };
8'b0z110110: tValRn = { valRs[ 9:0], tValRol[63:10] };
8'b0z110111: tValRn = { valRs[ 8:0], tValRol[63: 9] };
8'b0z111000: tValRn = { valRs[ 7:0], tValRol[63: 8] };
8'b0z111001: tValRn = { valRs[ 6:0], tValRol[63: 7] };
8'b0z111010: tValRn = { valRs[ 5:0], tValRol[63: 6] };
8'b0z111011: tValRn = { valRs[ 4:0], tValRol[63: 5] };
8'b0z111100: tValRn = { valRs[ 3:0], tValRol[63: 4] };
8'b0z111101: tValRn = { valRs[ 2:0], tValRol[63: 3] };
8'b0z111110: tValRn = { valRs[ 1:0], tValRol[63: 2] };
8'b0z111111: tValRn = { valRs[ 0], tValRol[63: 1] };
8'b1z111111: tValRn = { tValRor[ 0 ], valRs[63: 1] };
8'b1z111110: tValRn = { tValRor[ 1:0], valRs[63: 2] };
8'b1z111101: tValRn = { tValRor[ 2:0], valRs[63: 3] };
8'b1z111100: tValRn = { tValRor[ 3:0], valRs[63: 4] };
8'b1z111011: tValRn = { tValRor[ 4:0], valRs[63: 5] };
8'b1z111010: tValRn = { tValRor[ 5:0], valRs[63: 6] };
8'b1z111001: tValRn = { tValRor[ 6:0], valRs[63: 7] };
8'b1z111000: tValRn = { tValRor[ 7:0], valRs[63: 8] };
8'b1z110111: tValRn = { tValRor[ 8:0], valRs[63: 9] };
8'b1z110110: tValRn = { tValRor[ 9:0], valRs[63:10] };
8'b1z110101: tValRn = { tValRor[10:0], valRs[63:11] };
8'b1z110100: tValRn = { tValRor[11:0], valRs[63:12] };
8'b1z110011: tValRn = { tValRor[12:0], valRs[63:13] };
8'b1z110010: tValRn = { tValRor[13:0], valRs[63:14] };
8'b1z110001: tValRn = { tValRor[14:0], valRs[63:15] };
8'b1z110000: tValRn = { tValRor[15:0], valRs[63:16] };
8'b1z101111: tValRn = { tValRor[16:0], valRs[63:17] };
8'b1z101110: tValRn = { tValRor[17:0], valRs[63:18] };
8'b1z101101: tValRn = { tValRor[18:0], valRs[63:19] };
8'b1z101100: tValRn = { tValRor[19:0], valRs[63:20] };
8'b1z101011: tValRn = { tValRor[20:0], valRs[63:21] };
8'b1z101010: tValRn = { tValRor[21:0], valRs[63:22] };
8'b1z101001: tValRn = { tValRor[22:0], valRs[63:23] };
8'b1z101000: tValRn = { tValRor[23:0], valRs[63:24] };
8'b1z100111: tValRn = { tValRor[24:0], valRs[63:25] };
8'b1z100110: tValRn = { tValRor[25:0], valRs[63:26] };
8'b1z100101: tValRn = { tValRor[26:0], valRs[63:27] };
8'b1z100100: tValRn = { tValRor[27:0], valRs[63:28] };
8'b1z100011: tValRn = { tValRor[28:0], valRs[63:29] };
8'b1z100010: tValRn = { tValRor[29:0], valRs[63:30] };
8'b1z100001: tValRn = { tValRor[30:0], valRs[63:31] };
8'b1z100000: tValRn = { tValRor[31:0], valRs[63:32] };
8'b1z011111: tValRn = { tValRor[32:0], valRs[63:33] };
8'b1z011110: tValRn = { tValRor[33:0], valRs[63:34] };
8'b1z011101: tValRn = { tValRor[34:0], valRs[63:35] };
8'b1z011100: tValRn = { tValRor[35:0], valRs[63:36] };
8'b1z011011: tValRn = { tValRor[36:0], valRs[63:37] };
8'b1z011010: tValRn = { tValRor[37:0], valRs[63:38] };
8'b1z011001: tValRn = { tValRor[38:0], valRs[63:39] };
8'b1z011000: tValRn = { tValRor[39:0], valRs[63:40] };
8'b1z010111: tValRn = { tValRor[40:0], valRs[63:41] };
8'b1z010110: tValRn = { tValRor[41:0], valRs[63:42] };
8'b1z010101: tValRn = { tValRor[42:0], valRs[63:43] };
8'b1z010100: tValRn = { tValRor[43:0], valRs[63:44] };
8'b1z010011: tValRn = { tValRor[44:0], valRs[63:45] };
8'b1z010010: tValRn = { tValRor[45:0], valRs[63:46] };
8'b1z010001: tValRn = { tValRor[46:0], valRs[63:47] };
8'b1z010000: tValRn = { tValRor[47:0], valRs[63:48] };
8'b1z001111: tValRn = { tValRor[48:0], valRs[63:49] };
8'b1z001110: tValRn = { tValRor[49:0], valRs[63:50] };
8'b1z001101: tValRn = { tValRor[50:0], valRs[63:51] };
8'b1z001100: tValRn = { tValRor[51:0], valRs[63:52] };
8'b1z001011: tValRn = { tValRor[52:0], valRs[63:53] };
8'b1z001010: tValRn = { tValRor[53:0], valRs[63:54] };
8'b1z001001: tValRn = { tValRor[54:0], valRs[63:55] };
8'b1z001000: tValRn = { tValRor[55:0], valRs[63:56] };
8'b1z000111: tValRn = { tValRor[56:0], valRs[63:57] };
8'b1z000110: tValRn = { tValRor[57:0], valRs[63:58] };
8'b1z000101: tValRn = { tValRor[58:0], valRs[63:59] };
8'b1z000100: tValRn = { tValRor[59:0], valRs[63:60] };
8'b1z000011: tValRn = { tValRor[60:0], valRs[63:61] };
8'b1z000010: tValRn = { tValRor[61:0], valRs[63:62] };
8'b1z000001: tValRn = { tValRor[62:0], valRs[63 ] };
8'b1z000000: tValRn = tValRor;
endcase
end
endmodule | module ExShad64(
clock, reset,
valRs, valRt,
valRn, shOp
); |
input clock;
input reset;
input[63:0] valRs;
input[ 7:0] valRt;
input[ 2:0] shOp;
output[63:0] valRn;
reg[63:0] tValRn;
assign valRn = tValRn;
reg[63:0] tValRol;
reg[63:0] tValRor;
reg[ 7:0] tValSh;
always @*
begin
tValRol=0;
tValRor=0;
tValRn = 0;
tValSh = 0;
case(shOp)
3'h0: begin
end
3'h1: begin
tValRol=0;
tValRor=0;
tValSh = valRt;
end
3'h2: begin
tValRol=0;
tValRor=valRs[63] ? 64'hFFFFFFFF : 64'h00000000;
tValSh = valRt;
end
3'h3: begin
tValRol=0;
tValRor=0;
tValSh = -valRt;
end
3'h4: begin
tValRol=0;
tValRor=valRs[63] ? 64'hFFFFFFFF : 64'h00000000;
tValSh = -valRt;
end
default:
begin
end
endcase
casez(tValSh)
8'b0z000000: tValRn = valRs;
8'b0z000001: tValRn = { valRs[62:0], tValRol[63 ] };
8'b0z000010: tValRn = { valRs[61:0], tValRol[63:62] };
8'b0z000011: tValRn = { valRs[60:0], tValRol[63:61] };
8'b0z000100: tValRn = { valRs[59:0], tValRol[63:60] };
8'b0z000101: tValRn = { valRs[58:0], tValRol[63:59] };
8'b0z000110: tValRn = { valRs[57:0], tValRol[63:58] };
8'b0z000111: tValRn = { valRs[56:0], tValRol[63:57] };
8'b0z001000: tValRn = { valRs[55:0], tValRol[63:56] };
8'b0z001001: tValRn = { valRs[54:0], tValRol[63:55] };
8'b0z001010: tValRn = { valRs[53:0], tValRol[63:54] };
8'b0z001011: tValRn = { valRs[52:0], tValRol[63:53] };
8'b0z001100: tValRn = { valRs[51:0], tValRol[63:52] };
8'b0z001101: tValRn = { valRs[50:0], tValRol[63:51] };
8'b0z001110: tValRn = { valRs[49:0], tValRol[63:50] };
8'b0z001111: tValRn = { valRs[48:0], tValRol[63:49] };
8'b0z010000: tValRn = { valRs[47:0], tValRol[63:48] };
8'b0z010001: tValRn = { valRs[46:0], tValRol[63:47] };
8'b0z010010: tValRn = { valRs[45:0], tValRol[63:46] };
8'b0z010011: tValRn = { valRs[44:0], tValRol[63:45] };
8'b0z010100: tValRn = { valRs[43:0], tValRol[63:44] };
8'b0z010101: tValRn = { valRs[42:0], tValRol[63:43] };
8'b0z010110: tValRn = { valRs[41:0], tValRol[63:42] };
8'b0z010111: tValRn = { valRs[40:0], tValRol[63:41] };
8'b0z011000: tValRn = { valRs[39:0], tValRol[63:40] };
8'b0z011001: tValRn = { valRs[38:0], tValRol[63:39] };
8'b0z011010: tValRn = { valRs[37:0], tValRol[63:38] };
8'b0z011011: tValRn = { valRs[36:0], tValRol[63:37] };
8'b0z011100: tValRn = { valRs[35:0], tValRol[63:36] };
8'b0z011101: tValRn = { valRs[34:0], tValRol[63:35] };
8'b0z011110: tValRn = { valRs[33:0], tValRol[63:34] };
8'b0z011111: tValRn = { valRs[32:0], tValRol[63:33] };
8'b0z100000: tValRn = { valRs[31:0], tValRol[63:32] };
8'b0z100001: tValRn = { valRs[30:0], tValRol[63:31] };
8'b0z100010: tValRn = { valRs[29:0], tValRol[63:30] };
8'b0z100011: tValRn = { valRs[28:0], tValRol[63:29] };
8'b0z100100: tValRn = { valRs[27:0], tValRol[63:28] };
8'b0z100101: tValRn = { valRs[26:0], tValRol[63:27] };
8'b0z100110: tValRn = { valRs[25:0], tValRol[63:26] };
8'b0z100111: tValRn = { valRs[24:0], tValRol[63:25] };
8'b0z101000: tValRn = { valRs[23:0], tValRol[63:24] };
8'b0z101001: tValRn = { valRs[22:0], tValRol[63:23] };
8'b0z101010: tValRn = { valRs[21:0], tValRol[63:22] };
8'b0z101011: tValRn = { valRs[20:0], tValRol[63:21] };
8'b0z101100: tValRn = { valRs[19:0], tValRol[63:20] };
8'b0z101101: tValRn = { valRs[18:0], tValRol[63:19] };
8'b0z101110: tValRn = { valRs[17:0], tValRol[63:18] };
8'b0z101111: tValRn = { valRs[16:0], tValRol[63:17] };
8'b0z110000: tValRn = { valRs[15:0], tValRol[63:16] };
8'b0z110001: tValRn = { valRs[14:0], tValRol[63:15] };
8'b0z110010: tValRn = { valRs[13:0], tValRol[63:14] };
8'b0z110011: tValRn = { valRs[12:0], tValRol[63:13] };
8'b0z110100: tValRn = { valRs[11:0], tValRol[63:12] };
8'b0z110101: tValRn = { valRs[10:0], tValRol[63:11] };
8'b0z110110: tValRn = { valRs[ 9:0], tValRol[63:10] };
8'b0z110111: tValRn = { valRs[ 8:0], tValRol[63: 9] };
8'b0z111000: tValRn = { valRs[ 7:0], tValRol[63: 8] };
8'b0z111001: tValRn = { valRs[ 6:0], tValRol[63: 7] };
8'b0z111010: tValRn = { valRs[ 5:0], tValRol[63: 6] };
8'b0z111011: tValRn = { valRs[ 4:0], tValRol[63: 5] };
8'b0z111100: tValRn = { valRs[ 3:0], tValRol[63: 4] };
8'b0z111101: tValRn = { valRs[ 2:0], tValRol[63: 3] };
8'b0z111110: tValRn = { valRs[ 1:0], tValRol[63: 2] };
8'b0z111111: tValRn = { valRs[ 0], tValRol[63: 1] };
8'b1z111111: tValRn = { tValRor[ 0 ], valRs[63: 1] };
8'b1z111110: tValRn = { tValRor[ 1:0], valRs[63: 2] };
8'b1z111101: tValRn = { tValRor[ 2:0], valRs[63: 3] };
8'b1z111100: tValRn = { tValRor[ 3:0], valRs[63: 4] };
8'b1z111011: tValRn = { tValRor[ 4:0], valRs[63: 5] };
8'b1z111010: tValRn = { tValRor[ 5:0], valRs[63: 6] };
8'b1z111001: tValRn = { tValRor[ 6:0], valRs[63: 7] };
8'b1z111000: tValRn = { tValRor[ 7:0], valRs[63: 8] };
8'b1z110111: tValRn = { tValRor[ 8:0], valRs[63: 9] };
8'b1z110110: tValRn = { tValRor[ 9:0], valRs[63:10] };
8'b1z110101: tValRn = { tValRor[10:0], valRs[63:11] };
8'b1z110100: tValRn = { tValRor[11:0], valRs[63:12] };
8'b1z110011: tValRn = { tValRor[12:0], valRs[63:13] };
8'b1z110010: tValRn = { tValRor[13:0], valRs[63:14] };
8'b1z110001: tValRn = { tValRor[14:0], valRs[63:15] };
8'b1z110000: tValRn = { tValRor[15:0], valRs[63:16] };
8'b1z101111: tValRn = { tValRor[16:0], valRs[63:17] };
8'b1z101110: tValRn = { tValRor[17:0], valRs[63:18] };
8'b1z101101: tValRn = { tValRor[18:0], valRs[63:19] };
8'b1z101100: tValRn = { tValRor[19:0], valRs[63:20] };
8'b1z101011: tValRn = { tValRor[20:0], valRs[63:21] };
8'b1z101010: tValRn = { tValRor[21:0], valRs[63:22] };
8'b1z101001: tValRn = { tValRor[22:0], valRs[63:23] };
8'b1z101000: tValRn = { tValRor[23:0], valRs[63:24] };
8'b1z100111: tValRn = { tValRor[24:0], valRs[63:25] };
8'b1z100110: tValRn = { tValRor[25:0], valRs[63:26] };
8'b1z100101: tValRn = { tValRor[26:0], valRs[63:27] };
8'b1z100100: tValRn = { tValRor[27:0], valRs[63:28] };
8'b1z100011: tValRn = { tValRor[28:0], valRs[63:29] };
8'b1z100010: tValRn = { tValRor[29:0], valRs[63:30] };
8'b1z100001: tValRn = { tValRor[30:0], valRs[63:31] };
8'b1z100000: tValRn = { tValRor[31:0], valRs[63:32] };
8'b1z011111: tValRn = { tValRor[32:0], valRs[63:33] };
8'b1z011110: tValRn = { tValRor[33:0], valRs[63:34] };
8'b1z011101: tValRn = { tValRor[34:0], valRs[63:35] };
8'b1z011100: tValRn = { tValRor[35:0], valRs[63:36] };
8'b1z011011: tValRn = { tValRor[36:0], valRs[63:37] };
8'b1z011010: tValRn = { tValRor[37:0], valRs[63:38] };
8'b1z011001: tValRn = { tValRor[38:0], valRs[63:39] };
8'b1z011000: tValRn = { tValRor[39:0], valRs[63:40] };
8'b1z010111: tValRn = { tValRor[40:0], valRs[63:41] };
8'b1z010110: tValRn = { tValRor[41:0], valRs[63:42] };
8'b1z010101: tValRn = { tValRor[42:0], valRs[63:43] };
8'b1z010100: tValRn = { tValRor[43:0], valRs[63:44] };
8'b1z010011: tValRn = { tValRor[44:0], valRs[63:45] };
8'b1z010010: tValRn = { tValRor[45:0], valRs[63:46] };
8'b1z010001: tValRn = { tValRor[46:0], valRs[63:47] };
8'b1z010000: tValRn = { tValRor[47:0], valRs[63:48] };
8'b1z001111: tValRn = { tValRor[48:0], valRs[63:49] };
8'b1z001110: tValRn = { tValRor[49:0], valRs[63:50] };
8'b1z001101: tValRn = { tValRor[50:0], valRs[63:51] };
8'b1z001100: tValRn = { tValRor[51:0], valRs[63:52] };
8'b1z001011: tValRn = { tValRor[52:0], valRs[63:53] };
8'b1z001010: tValRn = { tValRor[53:0], valRs[63:54] };
8'b1z001001: tValRn = { tValRor[54:0], valRs[63:55] };
8'b1z001000: tValRn = { tValRor[55:0], valRs[63:56] };
8'b1z000111: tValRn = { tValRor[56:0], valRs[63:57] };
8'b1z000110: tValRn = { tValRor[57:0], valRs[63:58] };
8'b1z000101: tValRn = { tValRor[58:0], valRs[63:59] };
8'b1z000100: tValRn = { tValRor[59:0], valRs[63:60] };
8'b1z000011: tValRn = { tValRor[60:0], valRs[63:61] };
8'b1z000010: tValRn = { tValRor[61:0], valRs[63:62] };
8'b1z000001: tValRn = { tValRor[62:0], valRs[63 ] };
8'b1z000000: tValRn = tValRor;
endcase
end
endmodule | 2 |
142,535 | data/full_repos/permissive/99182535/bwjx1c64a/RegWGPR.v | 99,182,535 | RegWGPR.v | v | 1,242 | 66 | [] | [] | [] | null | line:28: before: "parameter" | null | 1: b'%Error: data/full_repos/permissive/99182535/bwjx1c64a/RegWGPR.v:1: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bwjx1c64a,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bwjx1c64a,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bwjx1c64a,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 314,747 | module | module RegWGPR(
clock, idNextPc,
idRegN1, idRegS1, idRegT1, idRegW1,
idRegN2, idRegS2, idRegT2, idRegW2,
idRegN3, idRegS3, idRegT3, idRegW3,
idRegN4, idRegS4, idRegT4, idRegW4,
idRegN5, idRegS5, idRegT5, idRegW5,
odValN1, odValS1, odValT1, idValW1, idImm1,
odValN2, odValS2, odValT2, idValW2, idImm2,
odValN3, odValS3, odValT3, idValW3, idImm3,
odValN4, odValS4, odValT4, idValW4, idImm4,
odValN5, odValS5, odValT5, idValW5, idImm5,
oregSr, exNextSr2,
oregPr, exNextPr2,
oregPc, exNextPc2,
oregMach, exNextMach2,
oregMacl, exNextMacl2,
oregSp, exNextSp2,
oregGbr, exNextGbr2,
oregVbr, exNextVbr2,
oregSSr, exNextSSr2,
oregSPc, exNextSPc2,
oregSGr, exNextSGr2,
oregFpul, exNextFpul2,
oregFpScr, exNextFpScr2
);
parameter wgprEnableLane4 = 0;
parameter wgprEnableLane5 = 0;
input clock;
input[63:0] idNextPc;
input[6:0] idRegN1;
input[6:0] idRegS1;
input[6:0] idRegT1;
input[6:0] idRegN2;
input[6:0] idRegS2;
input[6:0] idRegT2;
input[6:0] idRegN3;
input[6:0] idRegS3;
input[6:0] idRegT3;
input[6:0] idRegN4;
input[6:0] idRegS4;
input[6:0] idRegT4;
input[6:0] idRegN5;
input[6:0] idRegS5;
input[6:0] idRegT5;
input[6:0] idRegW1;
input[6:0] idRegW2;
input[6:0] idRegW3;
input[6:0] idRegW4;
input[6:0] idRegW5;
output[63:0] odValN1;
output[63:0] odValS1;
output[63:0] odValT1;
output[63:0] odValN2;
output[63:0] odValS2;
output[63:0] odValT2;
output[63:0] odValN3;
output[63:0] odValS3;
output[63:0] odValT3;
output[63:0] odValN4;
output[63:0] odValS4;
output[63:0] odValT4;
output[63:0] odValN5;
output[63:0] odValS5;
output[63:0] odValT5;
input[63:0] idValW1;
input[63:0] idValW2;
input[63:0] idValW3;
input[63:0] idValW4;
input[63:0] idValW5;
input[63:0] idImm1;
input[63:0] idImm2;
input[63:0] idImm3;
input[63:0] idImm4;
input[63:0] idImm5;
input[63:0] exNextSr2;
input[63:0] exNextPr2;
input[63:0] exNextPc2;
input[63:0] exNextMach2;
input[63:0] exNextMacl2;
input[63:0] exNextGbr2;
input[63:0] exNextVbr2;
input[63:0] exNextSSr2;
input[63:0] exNextSPc2;
input[63:0] exNextSGr2;
input[63:0] exNextFpul2;
input[63:0] exNextFpScr2;
input[63:0] exNextSp2;
output[63:0] oregMach;
output[63:0] oregMacl;
output[63:0] oregPr;
output[63:0] oregSGr;
output[63:0] oregFpul;
output[63:0] oregFpScr;
output[63:0] oregSr;
output[63:0] oregGbr;
output[63:0] oregVbr;
output[63:0] oregSSr;
output[63:0] oregSPc;
output[63:0] oregPc;
output[63:0] oregSp;
reg[63:0] regMach;
reg[63:0] regMacl;
reg[63:0] regPr;
reg[63:0] regSGr;
reg[63:0] regFpul;
reg[63:0] regFpScr;
reg[63:0] regSr;
reg[63:0] regGbr;
reg[63:0] regVbr;
reg[63:0] regSSr;
reg[63:0] regSPc;
reg[63:0] regPc;
reg[63:0] regSp;
assign oregMach = regMach;
assign oregMacl = regMacl;
assign oregPr = regPr;
assign oregSGr = regSGr;
assign oregFpul = regFpul;
assign oregFpScr = regFpScr;
assign oregSr = regSr;
assign oregGbr = regGbr;
assign oregVbr = regVbr;
assign oregSSr = regSSr;
assign oregSPc = regSPc;
assign oregPc = regPc;
assign oregSp = regSp;
reg[63:0] tValN1;
reg[63:0] tValS1;
reg[63:0] tValT1;
reg[63:0] tValN2;
reg[63:0] tValS2;
reg[63:0] tValT2;
reg[63:0] tValN3;
reg[63:0] tValS3;
reg[63:0] tValT3;
reg[63:0] tValN4;
reg[63:0] tValS4;
reg[63:0] tValT4;
reg[63:0] tValN5;
reg[63:0] tValS5;
reg[63:0] tValT5;
assign odValN1 = tValN1;
assign odValS1 = tValS1;
assign odValT1 = tValT1;
assign odValN2 = tValN2;
assign odValS2 = tValS2;
assign odValT2 = tValT2;
assign odValN3 = tValN3;
assign odValS3 = tValS3;
assign odValT3 = tValT3;
assign odValN4 = tValN4;
assign odValS4 = tValS4;
assign odValT4 = tValT4;
assign odValN5 = tValN5;
assign odValS5 = tValS5;
assign odValT5 = tValT5;
reg regSrRB;
reg nxtRegSrRB;
reg regFprRB;
reg nxtRegFprRB;
reg fprIsLd64;
reg fprIsSt64;
reg[63:0] regGprR0;
reg[63:0] regGprR1;
reg[63:0] regGprR2;
reg[63:0] regGprR3;
reg[63:0] regGprR4;
reg[63:0] regGprR5;
reg[63:0] regGprR6;
reg[63:0] regGprR7;
reg[63:0] regGprR8;
reg[63:0] regGprR9;
reg[63:0] regGprR10;
reg[63:0] regGprR11;
reg[63:0] regGprR12;
reg[63:0] regGprR13;
reg[63:0] regGprR14;
reg[63:0] regGprR15;
reg[63:0] regGprR16;
reg[63:0] regGprR17;
reg[63:0] regGprR18;
reg[63:0] regGprR19;
reg[63:0] regGprR20;
reg[63:0] regGprR21;
reg[63:0] regGprR22;
reg[63:0] regGprR23;
reg[63:0] regGprR24;
reg[63:0] regGprR25;
reg[63:0] regGprR26;
reg[63:0] regGprR27;
reg[63:0] regGprR28;
reg[63:0] regGprR29;
reg[63:0] regGprR30;
reg[63:0] regGprR31;
reg[63:0] regGprR0B;
reg[63:0] regGprR1B;
reg[63:0] regGprR2B;
reg[63:0] regGprR3B;
reg[63:0] regGprR4B;
reg[63:0] regGprR5B;
reg[63:0] regGprR6B;
reg[63:0] regGprR7B;
reg[63:0] regGprR16B;
reg[63:0] regGprR17B;
reg[63:0] regGprR18B;
reg[63:0] regGprR19B;
reg[63:0] regGprR20B;
reg[63:0] regGprR21B;
reg[63:0] regGprR22B;
reg[63:0] regGprR23B;
reg[31:0] regFprFR00;
reg[31:0] regFprFR01;
reg[31:0] regFprFR02;
reg[31:0] regFprFR03;
reg[31:0] regFprFR04;
reg[31:0] regFprFR05;
reg[31:0] regFprFR06;
reg[31:0] regFprFR07;
reg[31:0] regFprFR08;
reg[31:0] regFprFR09;
reg[31:0] regFprFR10;
reg[31:0] regFprFR11;
reg[31:0] regFprFR12;
reg[31:0] regFprFR13;
reg[31:0] regFprFR14;
reg[31:0] regFprFR15;
reg[31:0] regFprXF00;
reg[31:0] regFprXF01;
reg[31:0] regFprXF02;
reg[31:0] regFprXF03;
reg[31:0] regFprXF04;
reg[31:0] regFprXF05;
reg[31:0] regFprXF06;
reg[31:0] regFprXF07;
reg[31:0] regFprXF08;
reg[31:0] regFprXF09;
reg[31:0] regFprXF10;
reg[31:0] regFprXF11;
reg[31:0] regFprXF12;
reg[31:0] regFprXF13;
reg[31:0] regFprXF14;
reg[31:0] regFprXF15;
reg[31:0] nxtRegFprFR00;
reg[31:0] nxtRegFprFR01;
reg[31:0] nxtRegFprFR02;
reg[31:0] nxtRegFprFR03;
reg[31:0] nxtRegFprFR04;
reg[31:0] nxtRegFprFR05;
reg[31:0] nxtRegFprFR06;
reg[31:0] nxtRegFprFR07;
reg[31:0] nxtRegFprFR08;
reg[31:0] nxtRegFprFR09;
reg[31:0] nxtRegFprFR10;
reg[31:0] nxtRegFprFR11;
reg[31:0] nxtRegFprFR12;
reg[31:0] nxtRegFprFR13;
reg[31:0] nxtRegFprFR14;
reg[31:0] nxtRegFprFR15;
reg[31:0] nxtRegFprXF00;
reg[31:0] nxtRegFprXF01;
reg[31:0] nxtRegFprXF02;
reg[31:0] nxtRegFprXF03;
reg[31:0] nxtRegFprXF04;
reg[31:0] nxtRegFprXF05;
reg[31:0] nxtRegFprXF06;
reg[31:0] nxtRegFprXF07;
reg[31:0] nxtRegFprXF08;
reg[31:0] nxtRegFprXF09;
reg[31:0] nxtRegFprXF10;
reg[31:0] nxtRegFprXF11;
reg[31:0] nxtRegFprXF12;
reg[31:0] nxtRegFprXF13;
reg[31:0] nxtRegFprXF14;
reg[31:0] nxtRegFprXF15;
always @*
begin
fprIsLd64 = 0;
fprIsSt64 = 0;
nxtRegSrRB = 0;
nxtRegFprRB = 0;
tValN2 = UV64_XX;
tValN3 = UV64_XX;
tValN4 = UV64_XX;
tValN5 = UV64_XX;
tValS4 = UV64_XX;
tValS5 = UV64_XX;
tValT4 = UV64_XX;
tValT5 = UV64_XX;
case(idRegN1)
UREG_R0: tValN1 = regGprR0; UREG_R1: tValN1 = regGprR1;
UREG_R2: tValN1 = regGprR2; UREG_R3: tValN1 = regGprR3;
UREG_R4: tValN1 = regGprR4; UREG_R5: tValN1 = regGprR5;
UREG_R6: tValN1 = regGprR6; UREG_R7: tValN1 = regGprR7;
UREG_R8: tValN1 = regGprR8; UREG_R9: tValN1 = regGprR9;
UREG_R10: tValN1 = regGprR10; UREG_R11: tValN1 = regGprR11;
UREG_R12: tValN1 = regGprR12; UREG_R13: tValN1 = regGprR13;
UREG_R14: tValN1 = regGprR14; UREG_R15: tValN1 = regGprR15;
UREG_R16: tValN1 = regGprR16; UREG_R17: tValN1 = regGprR17;
UREG_R18: tValN1 = regGprR18; UREG_R19: tValN1 = regGprR19;
UREG_R20: tValN1 = regGprR20; UREG_R21: tValN1 = regGprR21;
UREG_R22: tValN1 = regGprR22; UREG_R23: tValN1 = regGprR23;
UREG_R24: tValN1 = regGprR24; UREG_R25: tValN1 = regGprR25;
UREG_R26: tValN1 = regGprR26; UREG_R27: tValN1 = regGprR27;
UREG_R28: tValN1 = regGprR28; UREG_R29: tValN1 = regGprR29;
UREG_R30: tValN1 = regGprR30; UREG_R31: tValN1 = regGprR31;
default: tValN1 = UV64_XX;
endcase
case(idRegS1)
UREG_R0: tValS1 = regGprR0; UREG_R1: tValS1 = regGprR1;
UREG_R2: tValS1 = regGprR2; UREG_R3: tValS1 = regGprR3;
UREG_R4: tValS1 = regGprR4; UREG_R5: tValS1 = regGprR5;
UREG_R6: tValS1 = regGprR6; UREG_R7: tValS1 = regGprR7;
UREG_R8: tValS1 = regGprR8; UREG_R9: tValS1 = regGprR9;
UREG_R10: tValS1 = regGprR10; UREG_R11: tValS1 = regGprR11;
UREG_R12: tValS1 = regGprR12; UREG_R13: tValS1 = regGprR13;
UREG_R14: tValS1 = regGprR14; UREG_R15: tValS1 = regGprR15;
UREG_R16: tValS1 = regGprR16; UREG_R17: tValS1 = regGprR17;
UREG_R18: tValS1 = regGprR18; UREG_R19: tValS1 = regGprR19;
UREG_R20: tValS1 = regGprR20; UREG_R21: tValS1 = regGprR21;
UREG_R22: tValS1 = regGprR22; UREG_R23: tValS1 = regGprR23;
UREG_R24: tValS1 = regGprR24; UREG_R25: tValS1 = regGprR25;
UREG_R26: tValS1 = regGprR26; UREG_R27: tValS1 = regGprR27;
UREG_R28: tValS1 = regGprR28; UREG_R29: tValS1 = regGprR29;
UREG_R30: tValS1 = regGprR30; UREG_R31: tValS1 = regGprR31;
UREG_R0B: tValS1 = regGprR0B; UREG_R1B: tValS1 = regGprR1B;
UREG_R2B: tValS1 = regGprR2B; UREG_R3B: tValS1 = regGprR3B;
UREG_R4B: tValS1 = regGprR4B; UREG_R5B: tValS1 = regGprR5B;
UREG_R6B: tValS1 = regGprR6B; UREG_R7B: tValS1 = regGprR7B;
UREG_R16B: tValS1 = regGprR16B; UREG_R17B: tValS1 = regGprR17B;
UREG_R18B: tValS1 = regGprR18B; UREG_R19B: tValS1 = regGprR19B;
UREG_R20B: tValS1 = regGprR20B; UREG_R21B: tValS1 = regGprR21B;
UREG_R22B: tValS1 = regGprR22B; UREG_R23B: tValS1 = regGprR23B;
UREG_FR0: tValS1 = fprIsLd64 ?
{regFprFR00, regFprFR01} : {UV32_XX, regFprFR00};
UREG_FR1: tValS1 = fprIsLd64 ?
{regFprXF00, regFprXF01} : {UV32_XX, regFprFR01};
UREG_FR2: tValS1 = fprIsLd64 ?
{regFprFR02, regFprFR03} : {UV32_XX, regFprFR02};
UREG_FR3: tValS1 = fprIsLd64 ?
{regFprXF02, regFprXF03} : {UV32_XX, regFprFR03};
UREG_FR4: tValS1 = fprIsLd64 ?
{regFprFR04, regFprFR05} : {UV32_XX, regFprFR04};
UREG_FR5: tValS1 = fprIsLd64 ?
{regFprXF04, regFprXF05} : {UV32_XX, regFprFR05};
UREG_FR6: tValS1 = fprIsLd64 ?
{regFprFR06, regFprFR07} : {UV32_XX, regFprFR06};
UREG_FR7: tValS1 = fprIsLd64 ?
{regFprXF06, regFprXF07} : {UV32_XX, regFprFR07};
UREG_FR8: tValS1 = fprIsLd64 ?
{regFprFR08, regFprFR09} : {UV32_XX, regFprFR08};
UREG_FR9: tValS1 = fprIsLd64 ?
{regFprXF08, regFprXF09} : {UV32_XX, regFprFR09};
UREG_FR10: tValS1 = fprIsLd64 ?
{regFprFR10, regFprFR11} : {UV32_XX, regFprFR10};
UREG_FR11: tValS1 = fprIsLd64 ?
{regFprXF10, regFprXF11} : {UV32_XX, regFprFR11};
UREG_FR12: tValS1 = fprIsLd64 ?
{regFprFR12, regFprFR13} : {UV32_XX, regFprFR12};
UREG_FR13: tValS1 = fprIsLd64 ?
{regFprXF12, regFprXF13} : {UV32_XX, regFprFR13};
UREG_FR14: tValS1 = fprIsLd64 ?
{regFprFR14, regFprFR15} : {UV32_XX, regFprFR14};
UREG_FR15: tValS1 = fprIsLd64 ?
{regFprXF14, regFprXF15} : {UV32_XX, regFprFR15};
UREG_SR: tValS1 = regSr; UREG_GBR: tValS1 = regGbr;
UREG_VBR: tValS1 = regVbr; UREG_SSR: tValS1 = regSSr;
UREG_SPC: tValS1 = regSPc;
UREG_MACH: tValS1 = regMach; UREG_MACL: tValS1 = regMacl;
UREG_PR: tValS1 = regPr; UREG_SGR: tValS1 = regSGr;
UREG_FPUL: tValS1 = regFpul; UREG_FPSCR: tValS1 = regFpScr;
UREG_PCW: tValS1 = idNextPc; UREG_PCL: tValS1 = idNextPc;
UREG_MR_IMM: tValS1 = idImm1; UREG_ZZR: tValS1 = 0;
default: tValS1 = UV64_XX;
endcase
case(idRegT1)
UREG_R0: tValT1 = regGprR0; UREG_R1: tValT1 = regGprR1;
UREG_R2: tValT1 = regGprR2; UREG_R3: tValT1 = regGprR3;
UREG_R4: tValT1 = regGprR4; UREG_R5: tValT1 = regGprR5;
UREG_R6: tValT1 = regGprR6; UREG_R7: tValT1 = regGprR7;
UREG_R8: tValT1 = regGprR8; UREG_R9: tValT1 = regGprR9;
UREG_R10: tValT1 = regGprR10; UREG_R11: tValT1 = regGprR11;
UREG_R12: tValT1 = regGprR12; UREG_R13: tValT1 = regGprR13;
UREG_R14: tValT1 = regGprR14; UREG_R15: tValT1 = regGprR15;
UREG_R16: tValT1 = regGprR16; UREG_R17: tValT1 = regGprR17;
UREG_R18: tValT1 = regGprR18; UREG_R19: tValT1 = regGprR19;
UREG_R20: tValT1 = regGprR20; UREG_R21: tValT1 = regGprR21;
UREG_R22: tValT1 = regGprR22; UREG_R23: tValT1 = regGprR23;
UREG_R24: tValT1 = regGprR24; UREG_R25: tValT1 = regGprR25;
UREG_R26: tValT1 = regGprR26; UREG_R27: tValT1 = regGprR27;
UREG_R28: tValT1 = regGprR28; UREG_R29: tValT1 = regGprR29;
UREG_R30: tValT1 = regGprR30; UREG_R31: tValT1 = regGprR31;
UREG_R0B: tValT1 = regGprR0B; UREG_R1B: tValT1 = regGprR1B;
UREG_R2B: tValT1 = regGprR2B; UREG_R3B: tValT1 = regGprR3B;
UREG_R4B: tValT1 = regGprR4B; UREG_R5B: tValT1 = regGprR5B;
UREG_R6B: tValT1 = regGprR6B; UREG_R7B: tValT1 = regGprR7B;
UREG_R16B: tValT1 = regGprR16B; UREG_R17B: tValT1 = regGprR17B;
UREG_R18B: tValT1 = regGprR18B; UREG_R19B: tValT1 = regGprR19B;
UREG_R20B: tValT1 = regGprR20B; UREG_R21B: tValT1 = regGprR21B;
UREG_R22B: tValT1 = regGprR22B; UREG_R23B: tValT1 = regGprR23B;
UREG_FR0: tValT1 = fprIsLd64 ?
{regFprFR00, regFprFR01} : {UV32_XX, regFprFR00};
UREG_FR1: tValT1 = fprIsLd64 ?
{regFprXF00, regFprXF01} : {UV32_XX, regFprFR01};
UREG_FR2: tValT1 = fprIsLd64 ?
{regFprFR02, regFprFR03} : {UV32_XX, regFprFR02};
UREG_FR3: tValT1 = fprIsLd64 ?
{regFprXF02, regFprXF03} : {UV32_XX, regFprFR03};
UREG_FR4: tValT1 = fprIsLd64 ?
{regFprFR04, regFprFR05} : {UV32_XX, regFprFR04};
UREG_FR5: tValT1 = fprIsLd64 ?
{regFprXF04, regFprXF05} : {UV32_XX, regFprFR05};
UREG_FR6: tValT1 = fprIsLd64 ?
{regFprFR06, regFprFR07} : {UV32_XX, regFprFR06};
UREG_FR7: tValT1 = fprIsLd64 ?
{regFprXF06, regFprXF07} : {UV32_XX, regFprFR07};
UREG_FR8: tValT1 = fprIsLd64 ?
{regFprFR08, regFprFR09} : {UV32_XX, regFprFR08};
UREG_FR9: tValT1 = fprIsLd64 ?
{regFprXF08, regFprXF09} : {UV32_XX, regFprFR09};
UREG_FR10: tValT1 = fprIsLd64 ?
{regFprFR10, regFprFR11} : {UV32_XX, regFprFR10};
UREG_FR11: tValT1 = fprIsLd64 ?
{regFprXF10, regFprXF11} : {UV32_XX, regFprFR11};
UREG_FR12: tValT1 = fprIsLd64 ?
{regFprFR12, regFprFR13} : {UV32_XX, regFprFR12};
UREG_FR13: tValT1 = fprIsLd64 ?
{regFprXF12, regFprXF13} : {UV32_XX, regFprFR13};
UREG_FR14: tValT1 = fprIsLd64 ?
{regFprFR14, regFprFR15} : {UV32_XX, regFprFR14};
UREG_FR15: tValT1 = fprIsLd64 ?
{regFprXF14, regFprXF15} : {UV32_XX, regFprFR15};
UREG_SR: tValT1 = regSr; UREG_GBR: tValT1 = regGbr;
UREG_VBR: tValT1 = regVbr; UREG_SSR: tValT1 = regSSr;
UREG_SPC: tValT1 = regSPc;
UREG_MACH: tValT1 = regMach; UREG_MACL: tValT1 = regMacl;
UREG_PR: tValT1 = regPr; UREG_SGR: tValT1 = regSGr;
UREG_FPUL: tValT1 = regFpul; UREG_FPSCR: tValT1 = regFpScr;
UREG_PCW: tValT1 = idNextPc; UREG_PCL: tValT1 = idNextPc;
UREG_MR_IMM: tValT1 = idImm1; UREG_ZZR: tValT1 = 0;
default: tValT1 = UV64_XX;
endcase
case(idRegS2)
UREG_R0: tValS2 = regGprR0; UREG_R1: tValS2 = regGprR1;
UREG_R2: tValS2 = regGprR2; UREG_R3: tValS2 = regGprR3;
UREG_R4: tValS2 = regGprR4; UREG_R5: tValS2 = regGprR5;
UREG_R6: tValS2 = regGprR6; UREG_R7: tValS2 = regGprR7;
UREG_R8: tValS2 = regGprR8; UREG_R9: tValS2 = regGprR9;
UREG_R10: tValS2 = regGprR10; UREG_R11: tValS2 = regGprR11;
UREG_R12: tValS2 = regGprR12; UREG_R13: tValS2 = regGprR13;
UREG_R14: tValS2 = regGprR14; UREG_R15: tValS2 = regGprR15;
UREG_R16: tValS2 = regGprR16; UREG_R17: tValS2 = regGprR17;
UREG_R18: tValS2 = regGprR18; UREG_R19: tValS2 = regGprR19;
UREG_R20: tValS2 = regGprR20; UREG_R21: tValS2 = regGprR21;
UREG_R22: tValS2 = regGprR22; UREG_R23: tValS2 = regGprR23;
UREG_R24: tValS2 = regGprR24; UREG_R25: tValS2 = regGprR25;
UREG_R26: tValS2 = regGprR26; UREG_R27: tValS2 = regGprR27;
UREG_R28: tValS2 = regGprR28; UREG_R29: tValS2 = regGprR29;
UREG_R30: tValS2 = regGprR30; UREG_R31: tValS2 = regGprR31;
UREG_PCW: tValS2 = idNextPc; UREG_PCL: tValS2 = idNextPc;
UREG_MR_IMM: tValS2 = idImm2; UREG_ZZR: tValS2 = 0;
default: tValS2 = UV64_XX;
endcase
case(idRegT2)
UREG_R0: tValT2 = regGprR0; UREG_R1: tValT2 = regGprR1;
UREG_R2: tValT2 = regGprR2; UREG_R3: tValT2 = regGprR3;
UREG_R4: tValT2 = regGprR4; UREG_R5: tValT2 = regGprR5;
UREG_R6: tValT2 = regGprR6; UREG_R7: tValT2 = regGprR7;
UREG_R8: tValT2 = regGprR8; UREG_R9: tValT2 = regGprR9;
UREG_R10: tValT2 = regGprR10; UREG_R11: tValT2 = regGprR11;
UREG_R12: tValT2 = regGprR12; UREG_R13: tValT2 = regGprR13;
UREG_R14: tValT2 = regGprR14; UREG_R15: tValT2 = regGprR15;
UREG_R16: tValT2 = regGprR16; UREG_R17: tValT2 = regGprR17;
UREG_R18: tValT2 = regGprR18; UREG_R19: tValT2 = regGprR19;
UREG_R20: tValT2 = regGprR20; UREG_R21: tValT2 = regGprR21;
UREG_R22: tValT2 = regGprR22; UREG_R23: tValT2 = regGprR23;
UREG_R24: tValT2 = regGprR24; UREG_R25: tValT2 = regGprR25;
UREG_R26: tValT2 = regGprR26; UREG_R27: tValT2 = regGprR27;
UREG_R28: tValT2 = regGprR28; UREG_R29: tValT2 = regGprR29;
UREG_R30: tValT2 = regGprR30; UREG_R31: tValT2 = regGprR31;
UREG_PCW: tValT2 = idNextPc; UREG_PCL: tValT2 = idNextPc;
UREG_MR_IMM: tValT2 = idImm2; UREG_ZZR: tValT2 = 0;
default: tValT2 = UV64_XX;
endcase
case(idRegS3)
UREG_R0: tValS3 = regGprR0; UREG_R1: tValS3 = regGprR1;
UREG_R2: tValS3 = regGprR2; UREG_R3: tValS3 = regGprR3;
UREG_R4: tValS3 = regGprR4; UREG_R5: tValS3 = regGprR5;
UREG_R6: tValS3 = regGprR6; UREG_R7: tValS3 = regGprR7;
UREG_R8: tValS3 = regGprR8; UREG_R9: tValS3 = regGprR9;
UREG_R10: tValS3 = regGprR10; UREG_R11: tValS3 = regGprR11;
UREG_R12: tValS3 = regGprR12; UREG_R13: tValS3 = regGprR13;
UREG_R14: tValS3 = regGprR14; UREG_R15: tValS3 = regGprR15;
UREG_R16: tValS3 = regGprR16; UREG_R17: tValS3 = regGprR17;
UREG_R18: tValS3 = regGprR18; UREG_R19: tValS3 = regGprR19;
UREG_R20: tValS3 = regGprR20; UREG_R21: tValS3 = regGprR21;
UREG_R22: tValS3 = regGprR22; UREG_R23: tValS3 = regGprR23;
UREG_R24: tValS3 = regGprR24; UREG_R25: tValS3 = regGprR25;
UREG_R26: tValS3 = regGprR26; UREG_R27: tValS3 = regGprR27;
UREG_R28: tValS3 = regGprR28; UREG_R29: tValS3 = regGprR29;
UREG_R30: tValS3 = regGprR30; UREG_R31: tValS3 = regGprR31;
UREG_PCW: tValS3 = idNextPc; UREG_PCL: tValS3 = idNextPc;
UREG_MR_IMM: tValS3 = idImm3; UREG_ZZR: tValS3 = 0;
default: tValS3 = UV64_XX;
endcase
case(idRegT3)
UREG_R0: tValT3 = regGprR0; UREG_R1: tValT3 = regGprR1;
UREG_R2: tValT3 = regGprR2; UREG_R3: tValT3 = regGprR3;
UREG_R4: tValT3 = regGprR4; UREG_R5: tValT3 = regGprR5;
UREG_R6: tValT3 = regGprR6; UREG_R7: tValT3 = regGprR7;
UREG_R8: tValT3 = regGprR8; UREG_R9: tValT3 = regGprR9;
UREG_R10: tValT3 = regGprR10; UREG_R11: tValT3 = regGprR11;
UREG_R12: tValT3 = regGprR12; UREG_R13: tValT3 = regGprR13;
UREG_R14: tValT3 = regGprR14; UREG_R15: tValT3 = regGprR15;
UREG_R16: tValT3 = regGprR16; UREG_R17: tValT3 = regGprR17;
UREG_R18: tValT3 = regGprR18; UREG_R19: tValT3 = regGprR19;
UREG_R20: tValT3 = regGprR20; UREG_R21: tValT3 = regGprR21;
UREG_R22: tValT3 = regGprR22; UREG_R23: tValT3 = regGprR23;
UREG_R24: tValT3 = regGprR24; UREG_R25: tValT3 = regGprR25;
UREG_R26: tValT3 = regGprR26; UREG_R27: tValT3 = regGprR27;
UREG_R28: tValT3 = regGprR28; UREG_R29: tValT3 = regGprR29;
UREG_R30: tValT3 = regGprR30; UREG_R31: tValT3 = regGprR31;
UREG_PCW: tValT3 = idNextPc; UREG_PCL: tValT3 = idNextPc;
UREG_MR_IMM: tValT3 = idImm3; UREG_ZZR: tValT3 = 0;
default: tValT3 = UV64_XX;
endcase
if(wgprEnableLane4)
begin
case(idRegS4)
UREG_R0: tValS4 = regGprR0; UREG_R1: tValS4 = regGprR1;
UREG_R2: tValS4 = regGprR2; UREG_R3: tValS4 = regGprR3;
UREG_R4: tValS4 = regGprR4; UREG_R5: tValS4 = regGprR5;
UREG_R6: tValS4 = regGprR6; UREG_R7: tValS4 = regGprR7;
UREG_R8: tValS4 = regGprR8; UREG_R9: tValS4 = regGprR9;
UREG_R10: tValS4 = regGprR10; UREG_R11: tValS4 = regGprR11;
UREG_R12: tValS4 = regGprR12; UREG_R13: tValS4 = regGprR13;
UREG_R14: tValS4 = regGprR14; UREG_R15: tValS4 = regGprR15;
UREG_R16: tValS4 = regGprR16; UREG_R17: tValS4 = regGprR17;
UREG_R18: tValS4 = regGprR18; UREG_R19: tValS4 = regGprR19;
UREG_R20: tValS4 = regGprR20; UREG_R21: tValS4 = regGprR21;
UREG_R22: tValS4 = regGprR22; UREG_R23: tValS4 = regGprR23;
UREG_R24: tValS4 = regGprR24; UREG_R25: tValS4 = regGprR25;
UREG_R26: tValS4 = regGprR26; UREG_R27: tValS4 = regGprR27;
UREG_R28: tValS4 = regGprR28; UREG_R29: tValS4 = regGprR29;
UREG_R30: tValS4 = regGprR30; UREG_R31: tValS4 = regGprR31;
UREG_PCW: tValS4 = idNextPc; UREG_PCL: tValS4 = idNextPc;
UREG_MR_IMM: tValS4 = idImm4; UREG_ZZR: tValS4 = 0;
default: tValS4 = UV64_XX;
endcase
case(idRegT4)
UREG_R0: tValT4 = regGprR0; UREG_R1: tValT4 = regGprR1;
UREG_R2: tValT4 = regGprR2; UREG_R3: tValT4 = regGprR3;
UREG_R4: tValT4 = regGprR4; UREG_R5: tValT4 = regGprR5;
UREG_R6: tValT4 = regGprR6; UREG_R7: tValT4 = regGprR7;
UREG_R8: tValT4 = regGprR8; UREG_R9: tValT4 = regGprR9;
UREG_R10: tValT4 = regGprR10; UREG_R11: tValT4 = regGprR11;
UREG_R12: tValT4 = regGprR12; UREG_R13: tValT4 = regGprR13;
UREG_R14: tValT4 = regGprR14; UREG_R15: tValT4 = regGprR15;
UREG_R16: tValT4 = regGprR16; UREG_R17: tValT4 = regGprR17;
UREG_R18: tValT4 = regGprR18; UREG_R19: tValT4 = regGprR19;
UREG_R20: tValT4 = regGprR20; UREG_R21: tValT4 = regGprR21;
UREG_R22: tValT4 = regGprR22; UREG_R23: tValT4 = regGprR23;
UREG_R24: tValT4 = regGprR24; UREG_R25: tValT4 = regGprR25;
UREG_R26: tValT4 = regGprR26; UREG_R27: tValT4 = regGprR27;
UREG_R28: tValT4 = regGprR28; UREG_R29: tValT4 = regGprR29;
UREG_R30: tValT4 = regGprR30; UREG_R31: tValT4 = regGprR31;
UREG_PCW: tValT4 = idNextPc; UREG_PCL: tValT4 = idNextPc;
UREG_MR_IMM: tValT4 = idImm4; UREG_ZZR: tValT4 = 0;
default: tValT4 = UV64_XX;
endcase
end
if(wgprEnableLane5)
begin
case(idRegS5)
UREG_R0: tValS5 = regGprR0; UREG_R1: tValS5 = regGprR1;
UREG_R2: tValS5 = regGprR2; UREG_R3: tValS5 = regGprR3;
UREG_R4: tValS5 = regGprR4; UREG_R5: tValS5 = regGprR5;
UREG_R6: tValS5 = regGprR6; UREG_R7: tValS5 = regGprR7;
UREG_R8: tValS5 = regGprR8; UREG_R9: tValS5 = regGprR9;
UREG_R10: tValS5 = regGprR10; UREG_R11: tValS5 = regGprR11;
UREG_R12: tValS5 = regGprR12; UREG_R13: tValS5 = regGprR13;
UREG_R14: tValS5 = regGprR14; UREG_R15: tValS5 = regGprR15;
UREG_R16: tValS5 = regGprR16; UREG_R17: tValS5 = regGprR17;
UREG_R18: tValS5 = regGprR18; UREG_R19: tValS5 = regGprR19;
UREG_R20: tValS5 = regGprR20; UREG_R21: tValS5 = regGprR21;
UREG_R22: tValS5 = regGprR22; UREG_R23: tValS5 = regGprR23;
UREG_R24: tValS5 = regGprR24; UREG_R25: tValS5 = regGprR25;
UREG_R26: tValS5 = regGprR26; UREG_R27: tValS5 = regGprR27;
UREG_R28: tValS5 = regGprR28; UREG_R29: tValS5 = regGprR29;
UREG_R30: tValS5 = regGprR30; UREG_R31: tValS5 = regGprR31;
UREG_PCW: tValS5 = idNextPc; UREG_PCL: tValS5 = idNextPc;
UREG_MR_IMM: tValS5 = idImm5; UREG_ZZR: tValS5 = 0;
default: tValS5 = UV64_XX;
endcase
case(idRegT5)
UREG_R0: tValT5 = regGprR0; UREG_R1: tValT5 = regGprR1;
UREG_R2: tValT5 = regGprR2; UREG_R3: tValT5 = regGprR3;
UREG_R4: tValT5 = regGprR4; UREG_R5: tValT5 = regGprR5;
UREG_R6: tValT5 = regGprR6; UREG_R7: tValT5 = regGprR7;
UREG_R8: tValT5 = regGprR8; UREG_R9: tValT5 = regGprR9;
UREG_R10: tValT5 = regGprR10; UREG_R11: tValT5 = regGprR11;
UREG_R12: tValT5 = regGprR12; UREG_R13: tValT5 = regGprR13;
UREG_R14: tValT5 = regGprR14; UREG_R15: tValT5 = regGprR15;
UREG_R16: tValT5 = regGprR16; UREG_R17: tValT5 = regGprR17;
UREG_R18: tValT5 = regGprR18; UREG_R19: tValT5 = regGprR19;
UREG_R20: tValT5 = regGprR20; UREG_R21: tValT5 = regGprR21;
UREG_R22: tValT5 = regGprR22; UREG_R23: tValT5 = regGprR23;
UREG_R24: tValT5 = regGprR24; UREG_R25: tValT5 = regGprR25;
UREG_R26: tValT5 = regGprR26; UREG_R27: tValT5 = regGprR27;
UREG_R28: tValT5 = regGprR28; UREG_R29: tValT5 = regGprR29;
UREG_R30: tValT5 = regGprR30; UREG_R31: tValT5 = regGprR31;
UREG_PCW: tValT5 = idNextPc; UREG_PCL: tValT5 = idNextPc;
UREG_MR_IMM: tValT5 = idImm1; UREG_ZZR: tValT5 = 0;
default: tValT5 = UV64_XX;
endcase
end
nxtRegFprFR00 = regFprFR00; nxtRegFprFR01 = regFprFR01;
nxtRegFprFR02 = regFprFR02; nxtRegFprFR03 = regFprFR03;
nxtRegFprFR04 = regFprFR04; nxtRegFprFR05 = regFprFR05;
nxtRegFprFR06 = regFprFR06; nxtRegFprFR07 = regFprFR07;
nxtRegFprFR08 = regFprFR08; nxtRegFprFR09 = regFprFR09;
nxtRegFprFR10 = regFprFR10; nxtRegFprFR11 = regFprFR11;
nxtRegFprFR12 = regFprFR12; nxtRegFprFR13 = regFprFR13;
nxtRegFprFR14 = regFprFR14; nxtRegFprFR15 = regFprFR15;
nxtRegFprXF00 = regFprXF00; nxtRegFprXF01 = regFprXF01;
nxtRegFprXF02 = regFprXF02; nxtRegFprXF03 = regFprXF03;
nxtRegFprXF04 = regFprXF04; nxtRegFprXF05 = regFprXF05;
nxtRegFprXF06 = regFprXF06; nxtRegFprXF07 = regFprXF07;
nxtRegFprXF08 = regFprXF08; nxtRegFprXF09 = regFprXF09;
nxtRegFprXF10 = regFprXF10; nxtRegFprXF11 = regFprXF11;
nxtRegFprXF12 = regFprXF12; nxtRegFprXF13 = regFprXF13;
nxtRegFprXF14 = regFprXF14; nxtRegFprXF15 = regFprXF15;
if(fprIsSt64)
begin
case(idRegW1)
UREG_FR0: {nxtRegFprFR00, nxtRegFprFR01} = idValW1;
UREG_FR1: {nxtRegFprXF00, nxtRegFprXF01} = idValW1;
UREG_FR2: {nxtRegFprFR02, nxtRegFprFR03} = idValW1;
UREG_FR3: {nxtRegFprXF02, nxtRegFprXF03} = idValW1;
UREG_FR4: {nxtRegFprFR04, nxtRegFprFR05} = idValW1;
UREG_FR5: {nxtRegFprXF04, nxtRegFprXF05} = idValW1;
UREG_FR6: {nxtRegFprFR06, nxtRegFprFR07} = idValW1;
UREG_FR7: {nxtRegFprXF06, nxtRegFprXF07} = idValW1;
UREG_FR8: {nxtRegFprFR08, nxtRegFprFR09} = idValW1;
UREG_FR9: {nxtRegFprXF08, nxtRegFprXF09} = idValW1;
UREG_FR10: {nxtRegFprFR10, nxtRegFprFR11} = idValW1;
UREG_FR11: {nxtRegFprXF10, nxtRegFprXF11} = idValW1;
UREG_FR12: {nxtRegFprFR12, nxtRegFprFR13} = idValW1;
UREG_FR13: {nxtRegFprXF12, nxtRegFprXF13} = idValW1;
UREG_FR14: {nxtRegFprFR14, nxtRegFprFR15} = idValW1;
UREG_FR15: {nxtRegFprXF14, nxtRegFprXF15} = idValW1;
default: begin end
endcase
end
else
begin
case(idRegW1)
UREG_FR0: nxtRegFprFR00 = idValW1[31:0];
UREG_FR1: nxtRegFprFR01 = idValW1[31:0];
UREG_FR2: nxtRegFprFR02 = idValW1[31:0];
UREG_FR3: nxtRegFprFR03 = idValW1[31:0];
UREG_FR4: nxtRegFprFR04 = idValW1[31:0];
UREG_FR5: nxtRegFprFR05 = idValW1[31:0];
UREG_FR6: nxtRegFprFR06 = idValW1[31:0];
UREG_FR7: nxtRegFprFR07 = idValW1[31:0];
UREG_FR8: nxtRegFprFR08 = idValW1[31:0];
UREG_FR9: nxtRegFprFR09 = idValW1[31:0];
UREG_FR10: nxtRegFprFR10 = idValW1[31:0];
UREG_FR11: nxtRegFprFR11 = idValW1[31:0];
UREG_FR12: nxtRegFprFR12 = idValW1[31:0];
UREG_FR13: nxtRegFprFR13 = idValW1[31:0];
UREG_FR14: nxtRegFprFR14 = idValW1[31:0];
UREG_FR15: nxtRegFprFR15 = idValW1[31:0];
UREG_XF0: nxtRegFprXF00 = idValW1[31:0];
UREG_XF1: nxtRegFprXF01 = idValW1[31:0];
UREG_XF2: nxtRegFprXF02 = idValW1[31:0];
UREG_XF3: nxtRegFprXF03 = idValW1[31:0];
UREG_XF4: nxtRegFprXF04 = idValW1[31:0];
UREG_XF5: nxtRegFprXF05 = idValW1[31:0];
UREG_XF6: nxtRegFprXF06 = idValW1[31:0];
UREG_XF7: nxtRegFprXF07 = idValW1[31:0];
UREG_XF8: nxtRegFprXF08 = idValW1[31:0];
UREG_XF9: nxtRegFprXF09 = idValW1[31:0];
UREG_XF10: nxtRegFprXF10 = idValW1[31:0];
UREG_XF11: nxtRegFprXF11 = idValW1[31:0];
UREG_XF12: nxtRegFprXF12 = idValW1[31:0];
UREG_XF13: nxtRegFprXF13 = idValW1[31:0];
UREG_XF14: nxtRegFprXF14 = idValW1[31:0];
UREG_XF15: nxtRegFprXF15 = idValW1[31:0];
default: begin end
endcase
end
end
always @(posedge clock)
begin
regSrRB <= nxtRegSrRB;
regFprRB <= nxtRegFprRB;
if(regSrRB ^ nxtRegSrRB)
begin
regGprR0 <= regGprR0B; regGprR1 <= regGprR1B;
regGprR2 <= regGprR2B; regGprR3 <= regGprR3B;
regGprR4 <= regGprR4B; regGprR5 <= regGprR5B;
regGprR6 <= regGprR6B; regGprR7 <= regGprR7B;
regGprR16 <= regGprR16B; regGprR17 <= regGprR17B;
regGprR18 <= regGprR18B; regGprR19 <= regGprR19B;
regGprR20 <= regGprR20B; regGprR21 <= regGprR21B;
regGprR22 <= regGprR22B; regGprR23 <= regGprR23B;
regGprR0B <= regGprR0; regGprR1B <= regGprR1;
regGprR2B <= regGprR2; regGprR3B <= regGprR3;
regGprR4B <= regGprR4; regGprR5B <= regGprR5;
regGprR6B <= regGprR6; regGprR7B <= regGprR7;
regGprR16B <= regGprR16; regGprR17B <= regGprR17;
regGprR18B <= regGprR18; regGprR19B <= regGprR19;
regGprR20B <= regGprR20; regGprR21B <= regGprR21;
regGprR22B <= regGprR22; regGprR23B <= regGprR23;
end
else
begin
if(wgprEnableLane5)
begin
regGprR0 <=
(idRegW1==UREG_R0) ? idValW1: (idRegW2==UREG_R0) ? idValW2:
(idRegW3==UREG_R0) ? idValW3: (idRegW4==UREG_R0) ? idValW4:
(idRegW5==UREG_R0) ? idValW5: regGprR0;
regGprR1 <=
(idRegW1==UREG_R1) ? idValW1: (idRegW2==UREG_R1) ? idValW2:
(idRegW3==UREG_R1) ? idValW3: (idRegW4==UREG_R1) ? idValW4:
(idRegW5==UREG_R1) ? idValW5: regGprR1;
regGprR2 <=
(idRegW1==UREG_R2) ? idValW1: (idRegW2==UREG_R2) ? idValW2:
(idRegW3==UREG_R2) ? idValW3: (idRegW4==UREG_R2) ? idValW4:
(idRegW5==UREG_R2) ? idValW5: regGprR2;
regGprR3 <=
(idRegW1==UREG_R3) ? idValW1: (idRegW2==UREG_R3) ? idValW2:
(idRegW3==UREG_R3) ? idValW3: (idRegW4==UREG_R3) ? idValW4:
(idRegW5==UREG_R3) ? idValW5: regGprR3;
regGprR4 <=
(idRegW1==UREG_R4) ? idValW1: (idRegW2==UREG_R4) ? idValW2:
(idRegW3==UREG_R4) ? idValW3: (idRegW4==UREG_R4) ? idValW4:
(idRegW5==UREG_R4) ? idValW5: regGprR4;
regGprR5 <=
(idRegW1==UREG_R5) ? idValW1: (idRegW2==UREG_R5) ? idValW2:
(idRegW3==UREG_R5) ? idValW3: (idRegW4==UREG_R5) ? idValW4:
(idRegW5==UREG_R5) ? idValW5: regGprR5;
regGprR6 <=
(idRegW1==UREG_R6) ? idValW1: (idRegW2==UREG_R6) ? idValW2:
(idRegW3==UREG_R6) ? idValW3: (idRegW4==UREG_R6) ? idValW4:
(idRegW5==UREG_R6) ? idValW5: regGprR6;
regGprR7 <=
(idRegW1==UREG_R7) ? idValW1: (idRegW2==UREG_R7) ? idValW2:
(idRegW3==UREG_R7) ? idValW3: (idRegW4==UREG_R7) ? idValW4:
(idRegW5==UREG_R7) ? idValW5: regGprR7;
regGprR8 <=
(idRegW1==UREG_R8) ? idValW1: (idRegW2==UREG_R8) ? idValW2:
(idRegW3==UREG_R8) ? idValW3: (idRegW4==UREG_R8) ? idValW4:
(idRegW5==UREG_R8) ? idValW5: regGprR8;
regGprR9 <=
(idRegW1==UREG_R9) ? idValW1: (idRegW2==UREG_R9) ? idValW2:
(idRegW3==UREG_R9) ? idValW3: (idRegW4==UREG_R9) ? idValW4:
(idRegW5==UREG_R9) ? idValW5: regGprR9;
regGprR10 <=
(idRegW1==UREG_R10) ? idValW1: (idRegW2==UREG_R10) ? idValW2:
(idRegW3==UREG_R10) ? idValW3: (idRegW4==UREG_R10) ? idValW4:
(idRegW5==UREG_R10) ? idValW5: regGprR10;
regGprR11 <=
(idRegW1==UREG_R11) ? idValW1: (idRegW2==UREG_R11) ? idValW2:
(idRegW3==UREG_R11) ? idValW3: (idRegW4==UREG_R11) ? idValW4:
(idRegW5==UREG_R11) ? idValW5: regGprR11;
regGprR12 <=
(idRegW1==UREG_R12) ? idValW1: (idRegW2==UREG_R12) ? idValW2:
(idRegW3==UREG_R12) ? idValW3: (idRegW4==UREG_R12) ? idValW4:
(idRegW5==UREG_R12) ? idValW5: regGprR12;
regGprR13 <=
(idRegW1==UREG_R13) ? idValW1: (idRegW2==UREG_R13) ? idValW2:
(idRegW3==UREG_R13) ? idValW3: (idRegW4==UREG_R13) ? idValW4:
(idRegW5==UREG_R13) ? idValW5: regGprR13;
regGprR14 <=
(idRegW1==UREG_R14) ? idValW1: (idRegW2==UREG_R14) ? idValW2:
(idRegW3==UREG_R14) ? idValW3: (idRegW4==UREG_R14) ? idValW4:
(idRegW5==UREG_R14) ? idValW5: regGprR14;
regGprR15 <=
(idRegW1==UREG_R15) ? idValW1: (idRegW2==UREG_R15) ? idValW2:
(idRegW3==UREG_R15) ? idValW3: (idRegW4==UREG_R15) ? idValW4:
(idRegW5==UREG_R15) ? idValW5: regGprR15;
regGprR16 <=
(idRegW1==UREG_R16) ? idValW1: (idRegW2==UREG_R16) ? idValW2:
(idRegW3==UREG_R16) ? idValW3: (idRegW4==UREG_R16) ? idValW4:
(idRegW5==UREG_R16) ? idValW5: regGprR16;
regGprR17 <=
(idRegW1==UREG_R17) ? idValW1: (idRegW2==UREG_R17) ? idValW2:
(idRegW3==UREG_R17) ? idValW3: (idRegW4==UREG_R17) ? idValW4:
(idRegW5==UREG_R17) ? idValW5: regGprR17;
regGprR18 <=
(idRegW1==UREG_R18) ? idValW1: (idRegW2==UREG_R18) ? idValW2:
(idRegW3==UREG_R18) ? idValW3: (idRegW4==UREG_R18) ? idValW4:
(idRegW5==UREG_R18) ? idValW5: regGprR18;
regGprR19 <=
(idRegW1==UREG_R19) ? idValW1: (idRegW2==UREG_R19) ? idValW2:
(idRegW3==UREG_R19) ? idValW3: (idRegW4==UREG_R19) ? idValW4:
(idRegW5==UREG_R19) ? idValW5: regGprR19;
regGprR20 <=
(idRegW1==UREG_R20) ? idValW1: (idRegW2==UREG_R20) ? idValW2:
(idRegW3==UREG_R20) ? idValW3: (idRegW4==UREG_R20) ? idValW4:
(idRegW5==UREG_R20) ? idValW5: regGprR20;
regGprR21 <=
(idRegW1==UREG_R21) ? idValW1: (idRegW2==UREG_R21) ? idValW2:
(idRegW3==UREG_R21) ? idValW3: (idRegW4==UREG_R21) ? idValW4:
(idRegW5==UREG_R21) ? idValW5: regGprR21;
regGprR22 <=
(idRegW1==UREG_R22) ? idValW1: (idRegW2==UREG_R22) ? idValW2:
(idRegW3==UREG_R22) ? idValW3: (idRegW4==UREG_R22) ? idValW4:
(idRegW5==UREG_R22) ? idValW5: regGprR22;
regGprR23 <=
(idRegW1==UREG_R23) ? idValW1: (idRegW2==UREG_R23) ? idValW2:
(idRegW3==UREG_R23) ? idValW3: (idRegW4==UREG_R23) ? idValW4:
(idRegW5==UREG_R23) ? idValW5: regGprR23;
regGprR24 <=
(idRegW1==UREG_R24) ? idValW1: (idRegW2==UREG_R24) ? idValW2:
(idRegW3==UREG_R24) ? idValW3: (idRegW4==UREG_R24) ? idValW4:
(idRegW5==UREG_R24) ? idValW5: regGprR24;
regGprR25 <=
(idRegW1==UREG_R25) ? idValW1: (idRegW2==UREG_R25) ? idValW2:
(idRegW3==UREG_R25) ? idValW3: (idRegW4==UREG_R25) ? idValW4:
(idRegW5==UREG_R25) ? idValW5: regGprR25;
regGprR26 <=
(idRegW1==UREG_R26) ? idValW1: (idRegW2==UREG_R26) ? idValW2:
(idRegW3==UREG_R26) ? idValW3: (idRegW4==UREG_R26) ? idValW4:
(idRegW5==UREG_R26) ? idValW5: regGprR26;
regGprR27 <=
(idRegW1==UREG_R27) ? idValW1: (idRegW2==UREG_R27) ? idValW2:
(idRegW3==UREG_R27) ? idValW3: (idRegW4==UREG_R27) ? idValW4:
(idRegW5==UREG_R27) ? idValW5: regGprR27;
regGprR28 <=
(idRegW1==UREG_R28) ? idValW1: (idRegW2==UREG_R28) ? idValW2:
(idRegW3==UREG_R28) ? idValW3: (idRegW4==UREG_R28) ? idValW4:
(idRegW5==UREG_R28) ? idValW5: regGprR28;
regGprR29 <=
(idRegW1==UREG_R29) ? idValW1: (idRegW2==UREG_R29) ? idValW2:
(idRegW3==UREG_R29) ? idValW3: (idRegW4==UREG_R29) ? idValW4:
(idRegW5==UREG_R29) ? idValW5: regGprR29;
regGprR30 <=
(idRegW1==UREG_R30) ? idValW1: (idRegW2==UREG_R30) ? idValW2:
(idRegW3==UREG_R30) ? idValW3: (idRegW4==UREG_R30) ? idValW4:
(idRegW5==UREG_R30) ? idValW5: regGprR30;
regGprR31 <=
(idRegW1==UREG_R31) ? idValW1: (idRegW2==UREG_R31) ? idValW2:
(idRegW3==UREG_R31) ? idValW3: (idRegW4==UREG_R31) ? idValW4:
(idRegW5==UREG_R31) ? idValW5: regGprR31;
end
else
begin
regGprR0 <=
(idRegW1==UREG_R0) ? idValW1: (idRegW2==UREG_R0) ? idValW2:
(idRegW3==UREG_R0) ? idValW3: regGprR0;
regGprR1 <=
(idRegW1==UREG_R1) ? idValW1: (idRegW2==UREG_R1) ? idValW2:
(idRegW3==UREG_R1) ? idValW3: regGprR1;
regGprR2 <=
(idRegW1==UREG_R2) ? idValW1: (idRegW2==UREG_R2) ? idValW2:
(idRegW3==UREG_R2) ? idValW3: regGprR2;
regGprR3 <=
(idRegW1==UREG_R3) ? idValW1: (idRegW2==UREG_R3) ? idValW2:
(idRegW3==UREG_R3) ? idValW3: regGprR3;
regGprR4 <=
(idRegW1==UREG_R4) ? idValW1: (idRegW2==UREG_R4) ? idValW2:
(idRegW3==UREG_R4) ? idValW3: regGprR4;
regGprR5 <=
(idRegW1==UREG_R5) ? idValW1: (idRegW2==UREG_R5) ? idValW2:
(idRegW3==UREG_R5) ? idValW3: regGprR5;
regGprR6 <=
(idRegW1==UREG_R6) ? idValW1: (idRegW2==UREG_R6) ? idValW2:
(idRegW3==UREG_R6) ? idValW3: regGprR6;
regGprR7 <=
(idRegW1==UREG_R7) ? idValW1: (idRegW2==UREG_R7) ? idValW2:
(idRegW3==UREG_R7) ? idValW3: regGprR7;
regGprR8 <=
(idRegW1==UREG_R8) ? idValW1: (idRegW2==UREG_R8) ? idValW2:
(idRegW3==UREG_R8) ? idValW3: regGprR8;
regGprR9 <=
(idRegW1==UREG_R9) ? idValW1: (idRegW2==UREG_R9) ? idValW2:
(idRegW3==UREG_R9) ? idValW3: regGprR9;
regGprR10 <=
(idRegW1==UREG_R10) ? idValW1: (idRegW2==UREG_R10) ? idValW2:
(idRegW3==UREG_R10) ? idValW3: regGprR10;
regGprR11 <=
(idRegW1==UREG_R11) ? idValW1: (idRegW2==UREG_R11) ? idValW2:
(idRegW3==UREG_R11) ? idValW3: regGprR11;
regGprR12 <=
(idRegW1==UREG_R12) ? idValW1: (idRegW2==UREG_R12) ? idValW2:
(idRegW3==UREG_R12) ? idValW3: regGprR12;
regGprR13 <=
(idRegW1==UREG_R13) ? idValW1: (idRegW2==UREG_R13) ? idValW2:
(idRegW3==UREG_R13) ? idValW3: regGprR13;
regGprR14 <=
(idRegW1==UREG_R14) ? idValW1: (idRegW2==UREG_R14) ? idValW2:
(idRegW3==UREG_R14) ? idValW3: regGprR14;
regGprR15 <=
(idRegW1==UREG_R15) ? idValW1: (idRegW2==UREG_R15) ? idValW2:
(idRegW3==UREG_R15) ? idValW3: regGprR15;
regGprR16 <=
(idRegW1==UREG_R16) ? idValW1: (idRegW2==UREG_R16) ? idValW2:
(idRegW3==UREG_R16) ? idValW3: regGprR16;
regGprR17 <=
(idRegW1==UREG_R17) ? idValW1: (idRegW2==UREG_R17) ? idValW2:
(idRegW3==UREG_R17) ? idValW3: regGprR17;
regGprR18 <=
(idRegW1==UREG_R18) ? idValW1: (idRegW2==UREG_R18) ? idValW2:
(idRegW3==UREG_R18) ? idValW3: regGprR18;
regGprR19 <=
(idRegW1==UREG_R19) ? idValW1: (idRegW2==UREG_R19) ? idValW2:
(idRegW3==UREG_R19) ? idValW3: regGprR19;
regGprR20 <=
(idRegW1==UREG_R20) ? idValW1: (idRegW2==UREG_R20) ? idValW2:
(idRegW3==UREG_R20) ? idValW3: regGprR20;
regGprR21 <=
(idRegW1==UREG_R21) ? idValW1: (idRegW2==UREG_R21) ? idValW2:
(idRegW3==UREG_R21) ? idValW3: regGprR21;
regGprR22 <=
(idRegW1==UREG_R22) ? idValW1: (idRegW2==UREG_R22) ? idValW2:
(idRegW3==UREG_R22) ? idValW3: regGprR22;
regGprR23 <=
(idRegW1==UREG_R23) ? idValW1: (idRegW2==UREG_R23) ? idValW2:
(idRegW3==UREG_R23) ? idValW3: regGprR23;
regGprR24 <=
(idRegW1==UREG_R24) ? idValW1: (idRegW2==UREG_R24) ? idValW2:
(idRegW3==UREG_R24) ? idValW3: regGprR24;
regGprR25 <=
(idRegW1==UREG_R25) ? idValW1: (idRegW2==UREG_R25) ? idValW2:
(idRegW3==UREG_R25) ? idValW3: regGprR25;
regGprR26 <=
(idRegW1==UREG_R26) ? idValW1: (idRegW2==UREG_R26) ? idValW2:
(idRegW3==UREG_R26) ? idValW3: regGprR26;
regGprR27 <=
(idRegW1==UREG_R27) ? idValW1: (idRegW2==UREG_R27) ? idValW2:
(idRegW3==UREG_R27) ? idValW3: regGprR27;
regGprR28 <=
(idRegW1==UREG_R28) ? idValW1: (idRegW2==UREG_R28) ? idValW2:
(idRegW3==UREG_R28) ? idValW3: regGprR28;
regGprR29 <=
(idRegW1==UREG_R29) ? idValW1: (idRegW2==UREG_R29) ? idValW2:
(idRegW3==UREG_R29) ? idValW3: regGprR29;
regGprR30 <=
(idRegW1==UREG_R30) ? idValW1: (idRegW2==UREG_R30) ? idValW2:
(idRegW3==UREG_R30) ? idValW3: regGprR30;
regGprR31 <=
(idRegW1==UREG_R31) ? idValW1: (idRegW2==UREG_R31) ? idValW2:
(idRegW3==UREG_R31) ? idValW3: regGprR31;
end
regGprR0B <= (idRegW1==UREG_R0B) ? idValW1: regGprR0B;
regGprR1B <= (idRegW1==UREG_R1B) ? idValW1: regGprR1B;
regGprR2B <= (idRegW1==UREG_R2B) ? idValW1: regGprR2B;
regGprR3B <= (idRegW1==UREG_R3B) ? idValW1: regGprR3B;
regGprR4B <= (idRegW1==UREG_R4B) ? idValW1: regGprR4B;
regGprR5B <= (idRegW1==UREG_R5B) ? idValW1: regGprR5B;
regGprR6B <= (idRegW1==UREG_R6B) ? idValW1: regGprR6B;
regGprR7B <= (idRegW1==UREG_R7B) ? idValW1: regGprR7B;
regGprR16B <= (idRegW1==UREG_R16B) ? idValW1: regGprR16B;
regGprR17B <= (idRegW1==UREG_R17B) ? idValW1: regGprR17B;
regGprR18B <= (idRegW1==UREG_R18B) ? idValW1: regGprR18B;
regGprR19B <= (idRegW1==UREG_R19B) ? idValW1: regGprR19B;
regGprR20B <= (idRegW1==UREG_R20B) ? idValW1: regGprR20B;
regGprR21B <= (idRegW1==UREG_R21B) ? idValW1: regGprR21B;
regGprR22B <= (idRegW1==UREG_R22B) ? idValW1: regGprR22B;
regGprR23B <= (idRegW1==UREG_R23B) ? idValW1: regGprR23B;
end
if(regFprRB^nxtRegFprRB)
begin
regFprFR00 <= nxtRegFprXF00; regFprFR01 <= nxtRegFprXF01;
regFprFR02 <= nxtRegFprXF02; regFprFR03 <= nxtRegFprXF03;
regFprFR04 <= nxtRegFprXF04; regFprFR05 <= nxtRegFprXF05;
regFprFR06 <= nxtRegFprXF06; regFprFR07 <= nxtRegFprXF07;
regFprFR08 <= nxtRegFprXF08; regFprFR09 <= nxtRegFprXF09;
regFprFR10 <= nxtRegFprXF10; regFprFR11 <= nxtRegFprXF11;
regFprFR12 <= nxtRegFprXF12; regFprFR13 <= nxtRegFprXF13;
regFprFR14 <= nxtRegFprXF14; regFprFR15 <= nxtRegFprXF15;
regFprXF00 <= nxtRegFprFR00; regFprXF01 <= nxtRegFprFR01;
regFprXF02 <= nxtRegFprFR02; regFprXF03 <= nxtRegFprFR03;
regFprXF04 <= nxtRegFprFR04; regFprXF05 <= nxtRegFprFR05;
regFprXF06 <= nxtRegFprFR06; regFprXF07 <= nxtRegFprFR07;
regFprXF08 <= nxtRegFprFR08; regFprXF09 <= nxtRegFprFR09;
regFprXF10 <= nxtRegFprFR10; regFprXF11 <= nxtRegFprFR11;
regFprXF12 <= nxtRegFprFR12; regFprXF13 <= nxtRegFprFR13;
regFprXF14 <= nxtRegFprFR14; regFprXF15 <= nxtRegFprFR15;
end
else
begin
regFprFR00 <= nxtRegFprFR00; regFprFR01 <= nxtRegFprFR01;
regFprFR02 <= nxtRegFprFR02; regFprFR03 <= nxtRegFprFR03;
regFprFR04 <= nxtRegFprFR04; regFprFR05 <= nxtRegFprFR05;
regFprFR06 <= nxtRegFprFR06; regFprFR07 <= nxtRegFprFR07;
regFprFR08 <= nxtRegFprFR08; regFprFR09 <= nxtRegFprFR09;
regFprFR10 <= nxtRegFprFR10; regFprFR11 <= nxtRegFprFR11;
regFprFR12 <= nxtRegFprFR12; regFprFR13 <= nxtRegFprFR13;
regFprFR14 <= nxtRegFprFR14; regFprFR15 <= nxtRegFprFR15;
regFprXF00 <= nxtRegFprXF00; regFprXF01 <= nxtRegFprXF01;
regFprXF02 <= nxtRegFprXF02; regFprXF03 <= nxtRegFprXF03;
regFprXF04 <= nxtRegFprXF04; regFprXF05 <= nxtRegFprXF05;
regFprXF06 <= nxtRegFprXF06; regFprXF07 <= nxtRegFprXF07;
regFprXF08 <= nxtRegFprXF08; regFprXF09 <= nxtRegFprXF09;
regFprXF10 <= nxtRegFprXF10; regFprXF11 <= nxtRegFprXF11;
regFprXF12 <= nxtRegFprXF12; regFprXF13 <= nxtRegFprXF13;
regFprXF14 <= nxtRegFprXF14; regFprXF15 <= nxtRegFprXF15;
end
regSr <= (idRegW1==UREG_SR ) ? idValW1 : exNextSr2;
regPr <= (idRegW1==UREG_PR ) ? idValW1 : exNextPr2;
regPc <= (idRegW1==UREG_PC ) ? idValW1 : exNextPc2;
regMach <= (idRegW1==UREG_MACL ) ? idValW1 : exNextMach2;
regMacl <= (idRegW1==UREG_MACH ) ? idValW1 : exNextMacl2;
regSp <= (idRegW1==UREG_R15 ) ? idValW1 : exNextSp2;
regGbr <= (idRegW1==UREG_GBR ) ? idValW1 : exNextGbr2;
regVbr <= (idRegW1==UREG_VBR ) ? idValW1 : exNextVbr2;
regSSr <= (idRegW1==UREG_SSR ) ? idValW1 : exNextSSr2;
regSPc <= (idRegW1==UREG_SPC ) ? idValW1 : exNextSPc2;
regSGr <= (idRegW1==UREG_SGR ) ? idValW1 : exNextSGr2;
regFpul <= (idRegW1==UREG_FPUL ) ? idValW1 : exNextFpul2;
regFpScr <= (idRegW1==UREG_FPSCR ) ? idValW1 : exNextFpScr2;
end
endmodule | module RegWGPR(
clock, idNextPc,
idRegN1, idRegS1, idRegT1, idRegW1,
idRegN2, idRegS2, idRegT2, idRegW2,
idRegN3, idRegS3, idRegT3, idRegW3,
idRegN4, idRegS4, idRegT4, idRegW4,
idRegN5, idRegS5, idRegT5, idRegW5,
odValN1, odValS1, odValT1, idValW1, idImm1,
odValN2, odValS2, odValT2, idValW2, idImm2,
odValN3, odValS3, odValT3, idValW3, idImm3,
odValN4, odValS4, odValT4, idValW4, idImm4,
odValN5, odValS5, odValT5, idValW5, idImm5,
oregSr, exNextSr2,
oregPr, exNextPr2,
oregPc, exNextPc2,
oregMach, exNextMach2,
oregMacl, exNextMacl2,
oregSp, exNextSp2,
oregGbr, exNextGbr2,
oregVbr, exNextVbr2,
oregSSr, exNextSSr2,
oregSPc, exNextSPc2,
oregSGr, exNextSGr2,
oregFpul, exNextFpul2,
oregFpScr, exNextFpScr2
); |
parameter wgprEnableLane4 = 0;
parameter wgprEnableLane5 = 0;
input clock;
input[63:0] idNextPc;
input[6:0] idRegN1;
input[6:0] idRegS1;
input[6:0] idRegT1;
input[6:0] idRegN2;
input[6:0] idRegS2;
input[6:0] idRegT2;
input[6:0] idRegN3;
input[6:0] idRegS3;
input[6:0] idRegT3;
input[6:0] idRegN4;
input[6:0] idRegS4;
input[6:0] idRegT4;
input[6:0] idRegN5;
input[6:0] idRegS5;
input[6:0] idRegT5;
input[6:0] idRegW1;
input[6:0] idRegW2;
input[6:0] idRegW3;
input[6:0] idRegW4;
input[6:0] idRegW5;
output[63:0] odValN1;
output[63:0] odValS1;
output[63:0] odValT1;
output[63:0] odValN2;
output[63:0] odValS2;
output[63:0] odValT2;
output[63:0] odValN3;
output[63:0] odValS3;
output[63:0] odValT3;
output[63:0] odValN4;
output[63:0] odValS4;
output[63:0] odValT4;
output[63:0] odValN5;
output[63:0] odValS5;
output[63:0] odValT5;
input[63:0] idValW1;
input[63:0] idValW2;
input[63:0] idValW3;
input[63:0] idValW4;
input[63:0] idValW5;
input[63:0] idImm1;
input[63:0] idImm2;
input[63:0] idImm3;
input[63:0] idImm4;
input[63:0] idImm5;
input[63:0] exNextSr2;
input[63:0] exNextPr2;
input[63:0] exNextPc2;
input[63:0] exNextMach2;
input[63:0] exNextMacl2;
input[63:0] exNextGbr2;
input[63:0] exNextVbr2;
input[63:0] exNextSSr2;
input[63:0] exNextSPc2;
input[63:0] exNextSGr2;
input[63:0] exNextFpul2;
input[63:0] exNextFpScr2;
input[63:0] exNextSp2;
output[63:0] oregMach;
output[63:0] oregMacl;
output[63:0] oregPr;
output[63:0] oregSGr;
output[63:0] oregFpul;
output[63:0] oregFpScr;
output[63:0] oregSr;
output[63:0] oregGbr;
output[63:0] oregVbr;
output[63:0] oregSSr;
output[63:0] oregSPc;
output[63:0] oregPc;
output[63:0] oregSp;
reg[63:0] regMach;
reg[63:0] regMacl;
reg[63:0] regPr;
reg[63:0] regSGr;
reg[63:0] regFpul;
reg[63:0] regFpScr;
reg[63:0] regSr;
reg[63:0] regGbr;
reg[63:0] regVbr;
reg[63:0] regSSr;
reg[63:0] regSPc;
reg[63:0] regPc;
reg[63:0] regSp;
assign oregMach = regMach;
assign oregMacl = regMacl;
assign oregPr = regPr;
assign oregSGr = regSGr;
assign oregFpul = regFpul;
assign oregFpScr = regFpScr;
assign oregSr = regSr;
assign oregGbr = regGbr;
assign oregVbr = regVbr;
assign oregSSr = regSSr;
assign oregSPc = regSPc;
assign oregPc = regPc;
assign oregSp = regSp;
reg[63:0] tValN1;
reg[63:0] tValS1;
reg[63:0] tValT1;
reg[63:0] tValN2;
reg[63:0] tValS2;
reg[63:0] tValT2;
reg[63:0] tValN3;
reg[63:0] tValS3;
reg[63:0] tValT3;
reg[63:0] tValN4;
reg[63:0] tValS4;
reg[63:0] tValT4;
reg[63:0] tValN5;
reg[63:0] tValS5;
reg[63:0] tValT5;
assign odValN1 = tValN1;
assign odValS1 = tValS1;
assign odValT1 = tValT1;
assign odValN2 = tValN2;
assign odValS2 = tValS2;
assign odValT2 = tValT2;
assign odValN3 = tValN3;
assign odValS3 = tValS3;
assign odValT3 = tValT3;
assign odValN4 = tValN4;
assign odValS4 = tValS4;
assign odValT4 = tValT4;
assign odValN5 = tValN5;
assign odValS5 = tValS5;
assign odValT5 = tValT5;
reg regSrRB;
reg nxtRegSrRB;
reg regFprRB;
reg nxtRegFprRB;
reg fprIsLd64;
reg fprIsSt64;
reg[63:0] regGprR0;
reg[63:0] regGprR1;
reg[63:0] regGprR2;
reg[63:0] regGprR3;
reg[63:0] regGprR4;
reg[63:0] regGprR5;
reg[63:0] regGprR6;
reg[63:0] regGprR7;
reg[63:0] regGprR8;
reg[63:0] regGprR9;
reg[63:0] regGprR10;
reg[63:0] regGprR11;
reg[63:0] regGprR12;
reg[63:0] regGprR13;
reg[63:0] regGprR14;
reg[63:0] regGprR15;
reg[63:0] regGprR16;
reg[63:0] regGprR17;
reg[63:0] regGprR18;
reg[63:0] regGprR19;
reg[63:0] regGprR20;
reg[63:0] regGprR21;
reg[63:0] regGprR22;
reg[63:0] regGprR23;
reg[63:0] regGprR24;
reg[63:0] regGprR25;
reg[63:0] regGprR26;
reg[63:0] regGprR27;
reg[63:0] regGprR28;
reg[63:0] regGprR29;
reg[63:0] regGprR30;
reg[63:0] regGprR31;
reg[63:0] regGprR0B;
reg[63:0] regGprR1B;
reg[63:0] regGprR2B;
reg[63:0] regGprR3B;
reg[63:0] regGprR4B;
reg[63:0] regGprR5B;
reg[63:0] regGprR6B;
reg[63:0] regGprR7B;
reg[63:0] regGprR16B;
reg[63:0] regGprR17B;
reg[63:0] regGprR18B;
reg[63:0] regGprR19B;
reg[63:0] regGprR20B;
reg[63:0] regGprR21B;
reg[63:0] regGprR22B;
reg[63:0] regGprR23B;
reg[31:0] regFprFR00;
reg[31:0] regFprFR01;
reg[31:0] regFprFR02;
reg[31:0] regFprFR03;
reg[31:0] regFprFR04;
reg[31:0] regFprFR05;
reg[31:0] regFprFR06;
reg[31:0] regFprFR07;
reg[31:0] regFprFR08;
reg[31:0] regFprFR09;
reg[31:0] regFprFR10;
reg[31:0] regFprFR11;
reg[31:0] regFprFR12;
reg[31:0] regFprFR13;
reg[31:0] regFprFR14;
reg[31:0] regFprFR15;
reg[31:0] regFprXF00;
reg[31:0] regFprXF01;
reg[31:0] regFprXF02;
reg[31:0] regFprXF03;
reg[31:0] regFprXF04;
reg[31:0] regFprXF05;
reg[31:0] regFprXF06;
reg[31:0] regFprXF07;
reg[31:0] regFprXF08;
reg[31:0] regFprXF09;
reg[31:0] regFprXF10;
reg[31:0] regFprXF11;
reg[31:0] regFprXF12;
reg[31:0] regFprXF13;
reg[31:0] regFprXF14;
reg[31:0] regFprXF15;
reg[31:0] nxtRegFprFR00;
reg[31:0] nxtRegFprFR01;
reg[31:0] nxtRegFprFR02;
reg[31:0] nxtRegFprFR03;
reg[31:0] nxtRegFprFR04;
reg[31:0] nxtRegFprFR05;
reg[31:0] nxtRegFprFR06;
reg[31:0] nxtRegFprFR07;
reg[31:0] nxtRegFprFR08;
reg[31:0] nxtRegFprFR09;
reg[31:0] nxtRegFprFR10;
reg[31:0] nxtRegFprFR11;
reg[31:0] nxtRegFprFR12;
reg[31:0] nxtRegFprFR13;
reg[31:0] nxtRegFprFR14;
reg[31:0] nxtRegFprFR15;
reg[31:0] nxtRegFprXF00;
reg[31:0] nxtRegFprXF01;
reg[31:0] nxtRegFprXF02;
reg[31:0] nxtRegFprXF03;
reg[31:0] nxtRegFprXF04;
reg[31:0] nxtRegFprXF05;
reg[31:0] nxtRegFprXF06;
reg[31:0] nxtRegFprXF07;
reg[31:0] nxtRegFprXF08;
reg[31:0] nxtRegFprXF09;
reg[31:0] nxtRegFprXF10;
reg[31:0] nxtRegFprXF11;
reg[31:0] nxtRegFprXF12;
reg[31:0] nxtRegFprXF13;
reg[31:0] nxtRegFprXF14;
reg[31:0] nxtRegFprXF15;
always @*
begin
fprIsLd64 = 0;
fprIsSt64 = 0;
nxtRegSrRB = 0;
nxtRegFprRB = 0;
tValN2 = UV64_XX;
tValN3 = UV64_XX;
tValN4 = UV64_XX;
tValN5 = UV64_XX;
tValS4 = UV64_XX;
tValS5 = UV64_XX;
tValT4 = UV64_XX;
tValT5 = UV64_XX;
case(idRegN1)
UREG_R0: tValN1 = regGprR0; UREG_R1: tValN1 = regGprR1;
UREG_R2: tValN1 = regGprR2; UREG_R3: tValN1 = regGprR3;
UREG_R4: tValN1 = regGprR4; UREG_R5: tValN1 = regGprR5;
UREG_R6: tValN1 = regGprR6; UREG_R7: tValN1 = regGprR7;
UREG_R8: tValN1 = regGprR8; UREG_R9: tValN1 = regGprR9;
UREG_R10: tValN1 = regGprR10; UREG_R11: tValN1 = regGprR11;
UREG_R12: tValN1 = regGprR12; UREG_R13: tValN1 = regGprR13;
UREG_R14: tValN1 = regGprR14; UREG_R15: tValN1 = regGprR15;
UREG_R16: tValN1 = regGprR16; UREG_R17: tValN1 = regGprR17;
UREG_R18: tValN1 = regGprR18; UREG_R19: tValN1 = regGprR19;
UREG_R20: tValN1 = regGprR20; UREG_R21: tValN1 = regGprR21;
UREG_R22: tValN1 = regGprR22; UREG_R23: tValN1 = regGprR23;
UREG_R24: tValN1 = regGprR24; UREG_R25: tValN1 = regGprR25;
UREG_R26: tValN1 = regGprR26; UREG_R27: tValN1 = regGprR27;
UREG_R28: tValN1 = regGprR28; UREG_R29: tValN1 = regGprR29;
UREG_R30: tValN1 = regGprR30; UREG_R31: tValN1 = regGprR31;
default: tValN1 = UV64_XX;
endcase
case(idRegS1)
UREG_R0: tValS1 = regGprR0; UREG_R1: tValS1 = regGprR1;
UREG_R2: tValS1 = regGprR2; UREG_R3: tValS1 = regGprR3;
UREG_R4: tValS1 = regGprR4; UREG_R5: tValS1 = regGprR5;
UREG_R6: tValS1 = regGprR6; UREG_R7: tValS1 = regGprR7;
UREG_R8: tValS1 = regGprR8; UREG_R9: tValS1 = regGprR9;
UREG_R10: tValS1 = regGprR10; UREG_R11: tValS1 = regGprR11;
UREG_R12: tValS1 = regGprR12; UREG_R13: tValS1 = regGprR13;
UREG_R14: tValS1 = regGprR14; UREG_R15: tValS1 = regGprR15;
UREG_R16: tValS1 = regGprR16; UREG_R17: tValS1 = regGprR17;
UREG_R18: tValS1 = regGprR18; UREG_R19: tValS1 = regGprR19;
UREG_R20: tValS1 = regGprR20; UREG_R21: tValS1 = regGprR21;
UREG_R22: tValS1 = regGprR22; UREG_R23: tValS1 = regGprR23;
UREG_R24: tValS1 = regGprR24; UREG_R25: tValS1 = regGprR25;
UREG_R26: tValS1 = regGprR26; UREG_R27: tValS1 = regGprR27;
UREG_R28: tValS1 = regGprR28; UREG_R29: tValS1 = regGprR29;
UREG_R30: tValS1 = regGprR30; UREG_R31: tValS1 = regGprR31;
UREG_R0B: tValS1 = regGprR0B; UREG_R1B: tValS1 = regGprR1B;
UREG_R2B: tValS1 = regGprR2B; UREG_R3B: tValS1 = regGprR3B;
UREG_R4B: tValS1 = regGprR4B; UREG_R5B: tValS1 = regGprR5B;
UREG_R6B: tValS1 = regGprR6B; UREG_R7B: tValS1 = regGprR7B;
UREG_R16B: tValS1 = regGprR16B; UREG_R17B: tValS1 = regGprR17B;
UREG_R18B: tValS1 = regGprR18B; UREG_R19B: tValS1 = regGprR19B;
UREG_R20B: tValS1 = regGprR20B; UREG_R21B: tValS1 = regGprR21B;
UREG_R22B: tValS1 = regGprR22B; UREG_R23B: tValS1 = regGprR23B;
UREG_FR0: tValS1 = fprIsLd64 ?
{regFprFR00, regFprFR01} : {UV32_XX, regFprFR00};
UREG_FR1: tValS1 = fprIsLd64 ?
{regFprXF00, regFprXF01} : {UV32_XX, regFprFR01};
UREG_FR2: tValS1 = fprIsLd64 ?
{regFprFR02, regFprFR03} : {UV32_XX, regFprFR02};
UREG_FR3: tValS1 = fprIsLd64 ?
{regFprXF02, regFprXF03} : {UV32_XX, regFprFR03};
UREG_FR4: tValS1 = fprIsLd64 ?
{regFprFR04, regFprFR05} : {UV32_XX, regFprFR04};
UREG_FR5: tValS1 = fprIsLd64 ?
{regFprXF04, regFprXF05} : {UV32_XX, regFprFR05};
UREG_FR6: tValS1 = fprIsLd64 ?
{regFprFR06, regFprFR07} : {UV32_XX, regFprFR06};
UREG_FR7: tValS1 = fprIsLd64 ?
{regFprXF06, regFprXF07} : {UV32_XX, regFprFR07};
UREG_FR8: tValS1 = fprIsLd64 ?
{regFprFR08, regFprFR09} : {UV32_XX, regFprFR08};
UREG_FR9: tValS1 = fprIsLd64 ?
{regFprXF08, regFprXF09} : {UV32_XX, regFprFR09};
UREG_FR10: tValS1 = fprIsLd64 ?
{regFprFR10, regFprFR11} : {UV32_XX, regFprFR10};
UREG_FR11: tValS1 = fprIsLd64 ?
{regFprXF10, regFprXF11} : {UV32_XX, regFprFR11};
UREG_FR12: tValS1 = fprIsLd64 ?
{regFprFR12, regFprFR13} : {UV32_XX, regFprFR12};
UREG_FR13: tValS1 = fprIsLd64 ?
{regFprXF12, regFprXF13} : {UV32_XX, regFprFR13};
UREG_FR14: tValS1 = fprIsLd64 ?
{regFprFR14, regFprFR15} : {UV32_XX, regFprFR14};
UREG_FR15: tValS1 = fprIsLd64 ?
{regFprXF14, regFprXF15} : {UV32_XX, regFprFR15};
UREG_SR: tValS1 = regSr; UREG_GBR: tValS1 = regGbr;
UREG_VBR: tValS1 = regVbr; UREG_SSR: tValS1 = regSSr;
UREG_SPC: tValS1 = regSPc;
UREG_MACH: tValS1 = regMach; UREG_MACL: tValS1 = regMacl;
UREG_PR: tValS1 = regPr; UREG_SGR: tValS1 = regSGr;
UREG_FPUL: tValS1 = regFpul; UREG_FPSCR: tValS1 = regFpScr;
UREG_PCW: tValS1 = idNextPc; UREG_PCL: tValS1 = idNextPc;
UREG_MR_IMM: tValS1 = idImm1; UREG_ZZR: tValS1 = 0;
default: tValS1 = UV64_XX;
endcase
case(idRegT1)
UREG_R0: tValT1 = regGprR0; UREG_R1: tValT1 = regGprR1;
UREG_R2: tValT1 = regGprR2; UREG_R3: tValT1 = regGprR3;
UREG_R4: tValT1 = regGprR4; UREG_R5: tValT1 = regGprR5;
UREG_R6: tValT1 = regGprR6; UREG_R7: tValT1 = regGprR7;
UREG_R8: tValT1 = regGprR8; UREG_R9: tValT1 = regGprR9;
UREG_R10: tValT1 = regGprR10; UREG_R11: tValT1 = regGprR11;
UREG_R12: tValT1 = regGprR12; UREG_R13: tValT1 = regGprR13;
UREG_R14: tValT1 = regGprR14; UREG_R15: tValT1 = regGprR15;
UREG_R16: tValT1 = regGprR16; UREG_R17: tValT1 = regGprR17;
UREG_R18: tValT1 = regGprR18; UREG_R19: tValT1 = regGprR19;
UREG_R20: tValT1 = regGprR20; UREG_R21: tValT1 = regGprR21;
UREG_R22: tValT1 = regGprR22; UREG_R23: tValT1 = regGprR23;
UREG_R24: tValT1 = regGprR24; UREG_R25: tValT1 = regGprR25;
UREG_R26: tValT1 = regGprR26; UREG_R27: tValT1 = regGprR27;
UREG_R28: tValT1 = regGprR28; UREG_R29: tValT1 = regGprR29;
UREG_R30: tValT1 = regGprR30; UREG_R31: tValT1 = regGprR31;
UREG_R0B: tValT1 = regGprR0B; UREG_R1B: tValT1 = regGprR1B;
UREG_R2B: tValT1 = regGprR2B; UREG_R3B: tValT1 = regGprR3B;
UREG_R4B: tValT1 = regGprR4B; UREG_R5B: tValT1 = regGprR5B;
UREG_R6B: tValT1 = regGprR6B; UREG_R7B: tValT1 = regGprR7B;
UREG_R16B: tValT1 = regGprR16B; UREG_R17B: tValT1 = regGprR17B;
UREG_R18B: tValT1 = regGprR18B; UREG_R19B: tValT1 = regGprR19B;
UREG_R20B: tValT1 = regGprR20B; UREG_R21B: tValT1 = regGprR21B;
UREG_R22B: tValT1 = regGprR22B; UREG_R23B: tValT1 = regGprR23B;
UREG_FR0: tValT1 = fprIsLd64 ?
{regFprFR00, regFprFR01} : {UV32_XX, regFprFR00};
UREG_FR1: tValT1 = fprIsLd64 ?
{regFprXF00, regFprXF01} : {UV32_XX, regFprFR01};
UREG_FR2: tValT1 = fprIsLd64 ?
{regFprFR02, regFprFR03} : {UV32_XX, regFprFR02};
UREG_FR3: tValT1 = fprIsLd64 ?
{regFprXF02, regFprXF03} : {UV32_XX, regFprFR03};
UREG_FR4: tValT1 = fprIsLd64 ?
{regFprFR04, regFprFR05} : {UV32_XX, regFprFR04};
UREG_FR5: tValT1 = fprIsLd64 ?
{regFprXF04, regFprXF05} : {UV32_XX, regFprFR05};
UREG_FR6: tValT1 = fprIsLd64 ?
{regFprFR06, regFprFR07} : {UV32_XX, regFprFR06};
UREG_FR7: tValT1 = fprIsLd64 ?
{regFprXF06, regFprXF07} : {UV32_XX, regFprFR07};
UREG_FR8: tValT1 = fprIsLd64 ?
{regFprFR08, regFprFR09} : {UV32_XX, regFprFR08};
UREG_FR9: tValT1 = fprIsLd64 ?
{regFprXF08, regFprXF09} : {UV32_XX, regFprFR09};
UREG_FR10: tValT1 = fprIsLd64 ?
{regFprFR10, regFprFR11} : {UV32_XX, regFprFR10};
UREG_FR11: tValT1 = fprIsLd64 ?
{regFprXF10, regFprXF11} : {UV32_XX, regFprFR11};
UREG_FR12: tValT1 = fprIsLd64 ?
{regFprFR12, regFprFR13} : {UV32_XX, regFprFR12};
UREG_FR13: tValT1 = fprIsLd64 ?
{regFprXF12, regFprXF13} : {UV32_XX, regFprFR13};
UREG_FR14: tValT1 = fprIsLd64 ?
{regFprFR14, regFprFR15} : {UV32_XX, regFprFR14};
UREG_FR15: tValT1 = fprIsLd64 ?
{regFprXF14, regFprXF15} : {UV32_XX, regFprFR15};
UREG_SR: tValT1 = regSr; UREG_GBR: tValT1 = regGbr;
UREG_VBR: tValT1 = regVbr; UREG_SSR: tValT1 = regSSr;
UREG_SPC: tValT1 = regSPc;
UREG_MACH: tValT1 = regMach; UREG_MACL: tValT1 = regMacl;
UREG_PR: tValT1 = regPr; UREG_SGR: tValT1 = regSGr;
UREG_FPUL: tValT1 = regFpul; UREG_FPSCR: tValT1 = regFpScr;
UREG_PCW: tValT1 = idNextPc; UREG_PCL: tValT1 = idNextPc;
UREG_MR_IMM: tValT1 = idImm1; UREG_ZZR: tValT1 = 0;
default: tValT1 = UV64_XX;
endcase
case(idRegS2)
UREG_R0: tValS2 = regGprR0; UREG_R1: tValS2 = regGprR1;
UREG_R2: tValS2 = regGprR2; UREG_R3: tValS2 = regGprR3;
UREG_R4: tValS2 = regGprR4; UREG_R5: tValS2 = regGprR5;
UREG_R6: tValS2 = regGprR6; UREG_R7: tValS2 = regGprR7;
UREG_R8: tValS2 = regGprR8; UREG_R9: tValS2 = regGprR9;
UREG_R10: tValS2 = regGprR10; UREG_R11: tValS2 = regGprR11;
UREG_R12: tValS2 = regGprR12; UREG_R13: tValS2 = regGprR13;
UREG_R14: tValS2 = regGprR14; UREG_R15: tValS2 = regGprR15;
UREG_R16: tValS2 = regGprR16; UREG_R17: tValS2 = regGprR17;
UREG_R18: tValS2 = regGprR18; UREG_R19: tValS2 = regGprR19;
UREG_R20: tValS2 = regGprR20; UREG_R21: tValS2 = regGprR21;
UREG_R22: tValS2 = regGprR22; UREG_R23: tValS2 = regGprR23;
UREG_R24: tValS2 = regGprR24; UREG_R25: tValS2 = regGprR25;
UREG_R26: tValS2 = regGprR26; UREG_R27: tValS2 = regGprR27;
UREG_R28: tValS2 = regGprR28; UREG_R29: tValS2 = regGprR29;
UREG_R30: tValS2 = regGprR30; UREG_R31: tValS2 = regGprR31;
UREG_PCW: tValS2 = idNextPc; UREG_PCL: tValS2 = idNextPc;
UREG_MR_IMM: tValS2 = idImm2; UREG_ZZR: tValS2 = 0;
default: tValS2 = UV64_XX;
endcase
case(idRegT2)
UREG_R0: tValT2 = regGprR0; UREG_R1: tValT2 = regGprR1;
UREG_R2: tValT2 = regGprR2; UREG_R3: tValT2 = regGprR3;
UREG_R4: tValT2 = regGprR4; UREG_R5: tValT2 = regGprR5;
UREG_R6: tValT2 = regGprR6; UREG_R7: tValT2 = regGprR7;
UREG_R8: tValT2 = regGprR8; UREG_R9: tValT2 = regGprR9;
UREG_R10: tValT2 = regGprR10; UREG_R11: tValT2 = regGprR11;
UREG_R12: tValT2 = regGprR12; UREG_R13: tValT2 = regGprR13;
UREG_R14: tValT2 = regGprR14; UREG_R15: tValT2 = regGprR15;
UREG_R16: tValT2 = regGprR16; UREG_R17: tValT2 = regGprR17;
UREG_R18: tValT2 = regGprR18; UREG_R19: tValT2 = regGprR19;
UREG_R20: tValT2 = regGprR20; UREG_R21: tValT2 = regGprR21;
UREG_R22: tValT2 = regGprR22; UREG_R23: tValT2 = regGprR23;
UREG_R24: tValT2 = regGprR24; UREG_R25: tValT2 = regGprR25;
UREG_R26: tValT2 = regGprR26; UREG_R27: tValT2 = regGprR27;
UREG_R28: tValT2 = regGprR28; UREG_R29: tValT2 = regGprR29;
UREG_R30: tValT2 = regGprR30; UREG_R31: tValT2 = regGprR31;
UREG_PCW: tValT2 = idNextPc; UREG_PCL: tValT2 = idNextPc;
UREG_MR_IMM: tValT2 = idImm2; UREG_ZZR: tValT2 = 0;
default: tValT2 = UV64_XX;
endcase
case(idRegS3)
UREG_R0: tValS3 = regGprR0; UREG_R1: tValS3 = regGprR1;
UREG_R2: tValS3 = regGprR2; UREG_R3: tValS3 = regGprR3;
UREG_R4: tValS3 = regGprR4; UREG_R5: tValS3 = regGprR5;
UREG_R6: tValS3 = regGprR6; UREG_R7: tValS3 = regGprR7;
UREG_R8: tValS3 = regGprR8; UREG_R9: tValS3 = regGprR9;
UREG_R10: tValS3 = regGprR10; UREG_R11: tValS3 = regGprR11;
UREG_R12: tValS3 = regGprR12; UREG_R13: tValS3 = regGprR13;
UREG_R14: tValS3 = regGprR14; UREG_R15: tValS3 = regGprR15;
UREG_R16: tValS3 = regGprR16; UREG_R17: tValS3 = regGprR17;
UREG_R18: tValS3 = regGprR18; UREG_R19: tValS3 = regGprR19;
UREG_R20: tValS3 = regGprR20; UREG_R21: tValS3 = regGprR21;
UREG_R22: tValS3 = regGprR22; UREG_R23: tValS3 = regGprR23;
UREG_R24: tValS3 = regGprR24; UREG_R25: tValS3 = regGprR25;
UREG_R26: tValS3 = regGprR26; UREG_R27: tValS3 = regGprR27;
UREG_R28: tValS3 = regGprR28; UREG_R29: tValS3 = regGprR29;
UREG_R30: tValS3 = regGprR30; UREG_R31: tValS3 = regGprR31;
UREG_PCW: tValS3 = idNextPc; UREG_PCL: tValS3 = idNextPc;
UREG_MR_IMM: tValS3 = idImm3; UREG_ZZR: tValS3 = 0;
default: tValS3 = UV64_XX;
endcase
case(idRegT3)
UREG_R0: tValT3 = regGprR0; UREG_R1: tValT3 = regGprR1;
UREG_R2: tValT3 = regGprR2; UREG_R3: tValT3 = regGprR3;
UREG_R4: tValT3 = regGprR4; UREG_R5: tValT3 = regGprR5;
UREG_R6: tValT3 = regGprR6; UREG_R7: tValT3 = regGprR7;
UREG_R8: tValT3 = regGprR8; UREG_R9: tValT3 = regGprR9;
UREG_R10: tValT3 = regGprR10; UREG_R11: tValT3 = regGprR11;
UREG_R12: tValT3 = regGprR12; UREG_R13: tValT3 = regGprR13;
UREG_R14: tValT3 = regGprR14; UREG_R15: tValT3 = regGprR15;
UREG_R16: tValT3 = regGprR16; UREG_R17: tValT3 = regGprR17;
UREG_R18: tValT3 = regGprR18; UREG_R19: tValT3 = regGprR19;
UREG_R20: tValT3 = regGprR20; UREG_R21: tValT3 = regGprR21;
UREG_R22: tValT3 = regGprR22; UREG_R23: tValT3 = regGprR23;
UREG_R24: tValT3 = regGprR24; UREG_R25: tValT3 = regGprR25;
UREG_R26: tValT3 = regGprR26; UREG_R27: tValT3 = regGprR27;
UREG_R28: tValT3 = regGprR28; UREG_R29: tValT3 = regGprR29;
UREG_R30: tValT3 = regGprR30; UREG_R31: tValT3 = regGprR31;
UREG_PCW: tValT3 = idNextPc; UREG_PCL: tValT3 = idNextPc;
UREG_MR_IMM: tValT3 = idImm3; UREG_ZZR: tValT3 = 0;
default: tValT3 = UV64_XX;
endcase
if(wgprEnableLane4)
begin
case(idRegS4)
UREG_R0: tValS4 = regGprR0; UREG_R1: tValS4 = regGprR1;
UREG_R2: tValS4 = regGprR2; UREG_R3: tValS4 = regGprR3;
UREG_R4: tValS4 = regGprR4; UREG_R5: tValS4 = regGprR5;
UREG_R6: tValS4 = regGprR6; UREG_R7: tValS4 = regGprR7;
UREG_R8: tValS4 = regGprR8; UREG_R9: tValS4 = regGprR9;
UREG_R10: tValS4 = regGprR10; UREG_R11: tValS4 = regGprR11;
UREG_R12: tValS4 = regGprR12; UREG_R13: tValS4 = regGprR13;
UREG_R14: tValS4 = regGprR14; UREG_R15: tValS4 = regGprR15;
UREG_R16: tValS4 = regGprR16; UREG_R17: tValS4 = regGprR17;
UREG_R18: tValS4 = regGprR18; UREG_R19: tValS4 = regGprR19;
UREG_R20: tValS4 = regGprR20; UREG_R21: tValS4 = regGprR21;
UREG_R22: tValS4 = regGprR22; UREG_R23: tValS4 = regGprR23;
UREG_R24: tValS4 = regGprR24; UREG_R25: tValS4 = regGprR25;
UREG_R26: tValS4 = regGprR26; UREG_R27: tValS4 = regGprR27;
UREG_R28: tValS4 = regGprR28; UREG_R29: tValS4 = regGprR29;
UREG_R30: tValS4 = regGprR30; UREG_R31: tValS4 = regGprR31;
UREG_PCW: tValS4 = idNextPc; UREG_PCL: tValS4 = idNextPc;
UREG_MR_IMM: tValS4 = idImm4; UREG_ZZR: tValS4 = 0;
default: tValS4 = UV64_XX;
endcase
case(idRegT4)
UREG_R0: tValT4 = regGprR0; UREG_R1: tValT4 = regGprR1;
UREG_R2: tValT4 = regGprR2; UREG_R3: tValT4 = regGprR3;
UREG_R4: tValT4 = regGprR4; UREG_R5: tValT4 = regGprR5;
UREG_R6: tValT4 = regGprR6; UREG_R7: tValT4 = regGprR7;
UREG_R8: tValT4 = regGprR8; UREG_R9: tValT4 = regGprR9;
UREG_R10: tValT4 = regGprR10; UREG_R11: tValT4 = regGprR11;
UREG_R12: tValT4 = regGprR12; UREG_R13: tValT4 = regGprR13;
UREG_R14: tValT4 = regGprR14; UREG_R15: tValT4 = regGprR15;
UREG_R16: tValT4 = regGprR16; UREG_R17: tValT4 = regGprR17;
UREG_R18: tValT4 = regGprR18; UREG_R19: tValT4 = regGprR19;
UREG_R20: tValT4 = regGprR20; UREG_R21: tValT4 = regGprR21;
UREG_R22: tValT4 = regGprR22; UREG_R23: tValT4 = regGprR23;
UREG_R24: tValT4 = regGprR24; UREG_R25: tValT4 = regGprR25;
UREG_R26: tValT4 = regGprR26; UREG_R27: tValT4 = regGprR27;
UREG_R28: tValT4 = regGprR28; UREG_R29: tValT4 = regGprR29;
UREG_R30: tValT4 = regGprR30; UREG_R31: tValT4 = regGprR31;
UREG_PCW: tValT4 = idNextPc; UREG_PCL: tValT4 = idNextPc;
UREG_MR_IMM: tValT4 = idImm4; UREG_ZZR: tValT4 = 0;
default: tValT4 = UV64_XX;
endcase
end
if(wgprEnableLane5)
begin
case(idRegS5)
UREG_R0: tValS5 = regGprR0; UREG_R1: tValS5 = regGprR1;
UREG_R2: tValS5 = regGprR2; UREG_R3: tValS5 = regGprR3;
UREG_R4: tValS5 = regGprR4; UREG_R5: tValS5 = regGprR5;
UREG_R6: tValS5 = regGprR6; UREG_R7: tValS5 = regGprR7;
UREG_R8: tValS5 = regGprR8; UREG_R9: tValS5 = regGprR9;
UREG_R10: tValS5 = regGprR10; UREG_R11: tValS5 = regGprR11;
UREG_R12: tValS5 = regGprR12; UREG_R13: tValS5 = regGprR13;
UREG_R14: tValS5 = regGprR14; UREG_R15: tValS5 = regGprR15;
UREG_R16: tValS5 = regGprR16; UREG_R17: tValS5 = regGprR17;
UREG_R18: tValS5 = regGprR18; UREG_R19: tValS5 = regGprR19;
UREG_R20: tValS5 = regGprR20; UREG_R21: tValS5 = regGprR21;
UREG_R22: tValS5 = regGprR22; UREG_R23: tValS5 = regGprR23;
UREG_R24: tValS5 = regGprR24; UREG_R25: tValS5 = regGprR25;
UREG_R26: tValS5 = regGprR26; UREG_R27: tValS5 = regGprR27;
UREG_R28: tValS5 = regGprR28; UREG_R29: tValS5 = regGprR29;
UREG_R30: tValS5 = regGprR30; UREG_R31: tValS5 = regGprR31;
UREG_PCW: tValS5 = idNextPc; UREG_PCL: tValS5 = idNextPc;
UREG_MR_IMM: tValS5 = idImm5; UREG_ZZR: tValS5 = 0;
default: tValS5 = UV64_XX;
endcase
case(idRegT5)
UREG_R0: tValT5 = regGprR0; UREG_R1: tValT5 = regGprR1;
UREG_R2: tValT5 = regGprR2; UREG_R3: tValT5 = regGprR3;
UREG_R4: tValT5 = regGprR4; UREG_R5: tValT5 = regGprR5;
UREG_R6: tValT5 = regGprR6; UREG_R7: tValT5 = regGprR7;
UREG_R8: tValT5 = regGprR8; UREG_R9: tValT5 = regGprR9;
UREG_R10: tValT5 = regGprR10; UREG_R11: tValT5 = regGprR11;
UREG_R12: tValT5 = regGprR12; UREG_R13: tValT5 = regGprR13;
UREG_R14: tValT5 = regGprR14; UREG_R15: tValT5 = regGprR15;
UREG_R16: tValT5 = regGprR16; UREG_R17: tValT5 = regGprR17;
UREG_R18: tValT5 = regGprR18; UREG_R19: tValT5 = regGprR19;
UREG_R20: tValT5 = regGprR20; UREG_R21: tValT5 = regGprR21;
UREG_R22: tValT5 = regGprR22; UREG_R23: tValT5 = regGprR23;
UREG_R24: tValT5 = regGprR24; UREG_R25: tValT5 = regGprR25;
UREG_R26: tValT5 = regGprR26; UREG_R27: tValT5 = regGprR27;
UREG_R28: tValT5 = regGprR28; UREG_R29: tValT5 = regGprR29;
UREG_R30: tValT5 = regGprR30; UREG_R31: tValT5 = regGprR31;
UREG_PCW: tValT5 = idNextPc; UREG_PCL: tValT5 = idNextPc;
UREG_MR_IMM: tValT5 = idImm1; UREG_ZZR: tValT5 = 0;
default: tValT5 = UV64_XX;
endcase
end
nxtRegFprFR00 = regFprFR00; nxtRegFprFR01 = regFprFR01;
nxtRegFprFR02 = regFprFR02; nxtRegFprFR03 = regFprFR03;
nxtRegFprFR04 = regFprFR04; nxtRegFprFR05 = regFprFR05;
nxtRegFprFR06 = regFprFR06; nxtRegFprFR07 = regFprFR07;
nxtRegFprFR08 = regFprFR08; nxtRegFprFR09 = regFprFR09;
nxtRegFprFR10 = regFprFR10; nxtRegFprFR11 = regFprFR11;
nxtRegFprFR12 = regFprFR12; nxtRegFprFR13 = regFprFR13;
nxtRegFprFR14 = regFprFR14; nxtRegFprFR15 = regFprFR15;
nxtRegFprXF00 = regFprXF00; nxtRegFprXF01 = regFprXF01;
nxtRegFprXF02 = regFprXF02; nxtRegFprXF03 = regFprXF03;
nxtRegFprXF04 = regFprXF04; nxtRegFprXF05 = regFprXF05;
nxtRegFprXF06 = regFprXF06; nxtRegFprXF07 = regFprXF07;
nxtRegFprXF08 = regFprXF08; nxtRegFprXF09 = regFprXF09;
nxtRegFprXF10 = regFprXF10; nxtRegFprXF11 = regFprXF11;
nxtRegFprXF12 = regFprXF12; nxtRegFprXF13 = regFprXF13;
nxtRegFprXF14 = regFprXF14; nxtRegFprXF15 = regFprXF15;
if(fprIsSt64)
begin
case(idRegW1)
UREG_FR0: {nxtRegFprFR00, nxtRegFprFR01} = idValW1;
UREG_FR1: {nxtRegFprXF00, nxtRegFprXF01} = idValW1;
UREG_FR2: {nxtRegFprFR02, nxtRegFprFR03} = idValW1;
UREG_FR3: {nxtRegFprXF02, nxtRegFprXF03} = idValW1;
UREG_FR4: {nxtRegFprFR04, nxtRegFprFR05} = idValW1;
UREG_FR5: {nxtRegFprXF04, nxtRegFprXF05} = idValW1;
UREG_FR6: {nxtRegFprFR06, nxtRegFprFR07} = idValW1;
UREG_FR7: {nxtRegFprXF06, nxtRegFprXF07} = idValW1;
UREG_FR8: {nxtRegFprFR08, nxtRegFprFR09} = idValW1;
UREG_FR9: {nxtRegFprXF08, nxtRegFprXF09} = idValW1;
UREG_FR10: {nxtRegFprFR10, nxtRegFprFR11} = idValW1;
UREG_FR11: {nxtRegFprXF10, nxtRegFprXF11} = idValW1;
UREG_FR12: {nxtRegFprFR12, nxtRegFprFR13} = idValW1;
UREG_FR13: {nxtRegFprXF12, nxtRegFprXF13} = idValW1;
UREG_FR14: {nxtRegFprFR14, nxtRegFprFR15} = idValW1;
UREG_FR15: {nxtRegFprXF14, nxtRegFprXF15} = idValW1;
default: begin end
endcase
end
else
begin
case(idRegW1)
UREG_FR0: nxtRegFprFR00 = idValW1[31:0];
UREG_FR1: nxtRegFprFR01 = idValW1[31:0];
UREG_FR2: nxtRegFprFR02 = idValW1[31:0];
UREG_FR3: nxtRegFprFR03 = idValW1[31:0];
UREG_FR4: nxtRegFprFR04 = idValW1[31:0];
UREG_FR5: nxtRegFprFR05 = idValW1[31:0];
UREG_FR6: nxtRegFprFR06 = idValW1[31:0];
UREG_FR7: nxtRegFprFR07 = idValW1[31:0];
UREG_FR8: nxtRegFprFR08 = idValW1[31:0];
UREG_FR9: nxtRegFprFR09 = idValW1[31:0];
UREG_FR10: nxtRegFprFR10 = idValW1[31:0];
UREG_FR11: nxtRegFprFR11 = idValW1[31:0];
UREG_FR12: nxtRegFprFR12 = idValW1[31:0];
UREG_FR13: nxtRegFprFR13 = idValW1[31:0];
UREG_FR14: nxtRegFprFR14 = idValW1[31:0];
UREG_FR15: nxtRegFprFR15 = idValW1[31:0];
UREG_XF0: nxtRegFprXF00 = idValW1[31:0];
UREG_XF1: nxtRegFprXF01 = idValW1[31:0];
UREG_XF2: nxtRegFprXF02 = idValW1[31:0];
UREG_XF3: nxtRegFprXF03 = idValW1[31:0];
UREG_XF4: nxtRegFprXF04 = idValW1[31:0];
UREG_XF5: nxtRegFprXF05 = idValW1[31:0];
UREG_XF6: nxtRegFprXF06 = idValW1[31:0];
UREG_XF7: nxtRegFprXF07 = idValW1[31:0];
UREG_XF8: nxtRegFprXF08 = idValW1[31:0];
UREG_XF9: nxtRegFprXF09 = idValW1[31:0];
UREG_XF10: nxtRegFprXF10 = idValW1[31:0];
UREG_XF11: nxtRegFprXF11 = idValW1[31:0];
UREG_XF12: nxtRegFprXF12 = idValW1[31:0];
UREG_XF13: nxtRegFprXF13 = idValW1[31:0];
UREG_XF14: nxtRegFprXF14 = idValW1[31:0];
UREG_XF15: nxtRegFprXF15 = idValW1[31:0];
default: begin end
endcase
end
end
always @(posedge clock)
begin
regSrRB <= nxtRegSrRB;
regFprRB <= nxtRegFprRB;
if(regSrRB ^ nxtRegSrRB)
begin
regGprR0 <= regGprR0B; regGprR1 <= regGprR1B;
regGprR2 <= regGprR2B; regGprR3 <= regGprR3B;
regGprR4 <= regGprR4B; regGprR5 <= regGprR5B;
regGprR6 <= regGprR6B; regGprR7 <= regGprR7B;
regGprR16 <= regGprR16B; regGprR17 <= regGprR17B;
regGprR18 <= regGprR18B; regGprR19 <= regGprR19B;
regGprR20 <= regGprR20B; regGprR21 <= regGprR21B;
regGprR22 <= regGprR22B; regGprR23 <= regGprR23B;
regGprR0B <= regGprR0; regGprR1B <= regGprR1;
regGprR2B <= regGprR2; regGprR3B <= regGprR3;
regGprR4B <= regGprR4; regGprR5B <= regGprR5;
regGprR6B <= regGprR6; regGprR7B <= regGprR7;
regGprR16B <= regGprR16; regGprR17B <= regGprR17;
regGprR18B <= regGprR18; regGprR19B <= regGprR19;
regGprR20B <= regGprR20; regGprR21B <= regGprR21;
regGprR22B <= regGprR22; regGprR23B <= regGprR23;
end
else
begin
if(wgprEnableLane5)
begin
regGprR0 <=
(idRegW1==UREG_R0) ? idValW1: (idRegW2==UREG_R0) ? idValW2:
(idRegW3==UREG_R0) ? idValW3: (idRegW4==UREG_R0) ? idValW4:
(idRegW5==UREG_R0) ? idValW5: regGprR0;
regGprR1 <=
(idRegW1==UREG_R1) ? idValW1: (idRegW2==UREG_R1) ? idValW2:
(idRegW3==UREG_R1) ? idValW3: (idRegW4==UREG_R1) ? idValW4:
(idRegW5==UREG_R1) ? idValW5: regGprR1;
regGprR2 <=
(idRegW1==UREG_R2) ? idValW1: (idRegW2==UREG_R2) ? idValW2:
(idRegW3==UREG_R2) ? idValW3: (idRegW4==UREG_R2) ? idValW4:
(idRegW5==UREG_R2) ? idValW5: regGprR2;
regGprR3 <=
(idRegW1==UREG_R3) ? idValW1: (idRegW2==UREG_R3) ? idValW2:
(idRegW3==UREG_R3) ? idValW3: (idRegW4==UREG_R3) ? idValW4:
(idRegW5==UREG_R3) ? idValW5: regGprR3;
regGprR4 <=
(idRegW1==UREG_R4) ? idValW1: (idRegW2==UREG_R4) ? idValW2:
(idRegW3==UREG_R4) ? idValW3: (idRegW4==UREG_R4) ? idValW4:
(idRegW5==UREG_R4) ? idValW5: regGprR4;
regGprR5 <=
(idRegW1==UREG_R5) ? idValW1: (idRegW2==UREG_R5) ? idValW2:
(idRegW3==UREG_R5) ? idValW3: (idRegW4==UREG_R5) ? idValW4:
(idRegW5==UREG_R5) ? idValW5: regGprR5;
regGprR6 <=
(idRegW1==UREG_R6) ? idValW1: (idRegW2==UREG_R6) ? idValW2:
(idRegW3==UREG_R6) ? idValW3: (idRegW4==UREG_R6) ? idValW4:
(idRegW5==UREG_R6) ? idValW5: regGprR6;
regGprR7 <=
(idRegW1==UREG_R7) ? idValW1: (idRegW2==UREG_R7) ? idValW2:
(idRegW3==UREG_R7) ? idValW3: (idRegW4==UREG_R7) ? idValW4:
(idRegW5==UREG_R7) ? idValW5: regGprR7;
regGprR8 <=
(idRegW1==UREG_R8) ? idValW1: (idRegW2==UREG_R8) ? idValW2:
(idRegW3==UREG_R8) ? idValW3: (idRegW4==UREG_R8) ? idValW4:
(idRegW5==UREG_R8) ? idValW5: regGprR8;
regGprR9 <=
(idRegW1==UREG_R9) ? idValW1: (idRegW2==UREG_R9) ? idValW2:
(idRegW3==UREG_R9) ? idValW3: (idRegW4==UREG_R9) ? idValW4:
(idRegW5==UREG_R9) ? idValW5: regGprR9;
regGprR10 <=
(idRegW1==UREG_R10) ? idValW1: (idRegW2==UREG_R10) ? idValW2:
(idRegW3==UREG_R10) ? idValW3: (idRegW4==UREG_R10) ? idValW4:
(idRegW5==UREG_R10) ? idValW5: regGprR10;
regGprR11 <=
(idRegW1==UREG_R11) ? idValW1: (idRegW2==UREG_R11) ? idValW2:
(idRegW3==UREG_R11) ? idValW3: (idRegW4==UREG_R11) ? idValW4:
(idRegW5==UREG_R11) ? idValW5: regGprR11;
regGprR12 <=
(idRegW1==UREG_R12) ? idValW1: (idRegW2==UREG_R12) ? idValW2:
(idRegW3==UREG_R12) ? idValW3: (idRegW4==UREG_R12) ? idValW4:
(idRegW5==UREG_R12) ? idValW5: regGprR12;
regGprR13 <=
(idRegW1==UREG_R13) ? idValW1: (idRegW2==UREG_R13) ? idValW2:
(idRegW3==UREG_R13) ? idValW3: (idRegW4==UREG_R13) ? idValW4:
(idRegW5==UREG_R13) ? idValW5: regGprR13;
regGprR14 <=
(idRegW1==UREG_R14) ? idValW1: (idRegW2==UREG_R14) ? idValW2:
(idRegW3==UREG_R14) ? idValW3: (idRegW4==UREG_R14) ? idValW4:
(idRegW5==UREG_R14) ? idValW5: regGprR14;
regGprR15 <=
(idRegW1==UREG_R15) ? idValW1: (idRegW2==UREG_R15) ? idValW2:
(idRegW3==UREG_R15) ? idValW3: (idRegW4==UREG_R15) ? idValW4:
(idRegW5==UREG_R15) ? idValW5: regGprR15;
regGprR16 <=
(idRegW1==UREG_R16) ? idValW1: (idRegW2==UREG_R16) ? idValW2:
(idRegW3==UREG_R16) ? idValW3: (idRegW4==UREG_R16) ? idValW4:
(idRegW5==UREG_R16) ? idValW5: regGprR16;
regGprR17 <=
(idRegW1==UREG_R17) ? idValW1: (idRegW2==UREG_R17) ? idValW2:
(idRegW3==UREG_R17) ? idValW3: (idRegW4==UREG_R17) ? idValW4:
(idRegW5==UREG_R17) ? idValW5: regGprR17;
regGprR18 <=
(idRegW1==UREG_R18) ? idValW1: (idRegW2==UREG_R18) ? idValW2:
(idRegW3==UREG_R18) ? idValW3: (idRegW4==UREG_R18) ? idValW4:
(idRegW5==UREG_R18) ? idValW5: regGprR18;
regGprR19 <=
(idRegW1==UREG_R19) ? idValW1: (idRegW2==UREG_R19) ? idValW2:
(idRegW3==UREG_R19) ? idValW3: (idRegW4==UREG_R19) ? idValW4:
(idRegW5==UREG_R19) ? idValW5: regGprR19;
regGprR20 <=
(idRegW1==UREG_R20) ? idValW1: (idRegW2==UREG_R20) ? idValW2:
(idRegW3==UREG_R20) ? idValW3: (idRegW4==UREG_R20) ? idValW4:
(idRegW5==UREG_R20) ? idValW5: regGprR20;
regGprR21 <=
(idRegW1==UREG_R21) ? idValW1: (idRegW2==UREG_R21) ? idValW2:
(idRegW3==UREG_R21) ? idValW3: (idRegW4==UREG_R21) ? idValW4:
(idRegW5==UREG_R21) ? idValW5: regGprR21;
regGprR22 <=
(idRegW1==UREG_R22) ? idValW1: (idRegW2==UREG_R22) ? idValW2:
(idRegW3==UREG_R22) ? idValW3: (idRegW4==UREG_R22) ? idValW4:
(idRegW5==UREG_R22) ? idValW5: regGprR22;
regGprR23 <=
(idRegW1==UREG_R23) ? idValW1: (idRegW2==UREG_R23) ? idValW2:
(idRegW3==UREG_R23) ? idValW3: (idRegW4==UREG_R23) ? idValW4:
(idRegW5==UREG_R23) ? idValW5: regGprR23;
regGprR24 <=
(idRegW1==UREG_R24) ? idValW1: (idRegW2==UREG_R24) ? idValW2:
(idRegW3==UREG_R24) ? idValW3: (idRegW4==UREG_R24) ? idValW4:
(idRegW5==UREG_R24) ? idValW5: regGprR24;
regGprR25 <=
(idRegW1==UREG_R25) ? idValW1: (idRegW2==UREG_R25) ? idValW2:
(idRegW3==UREG_R25) ? idValW3: (idRegW4==UREG_R25) ? idValW4:
(idRegW5==UREG_R25) ? idValW5: regGprR25;
regGprR26 <=
(idRegW1==UREG_R26) ? idValW1: (idRegW2==UREG_R26) ? idValW2:
(idRegW3==UREG_R26) ? idValW3: (idRegW4==UREG_R26) ? idValW4:
(idRegW5==UREG_R26) ? idValW5: regGprR26;
regGprR27 <=
(idRegW1==UREG_R27) ? idValW1: (idRegW2==UREG_R27) ? idValW2:
(idRegW3==UREG_R27) ? idValW3: (idRegW4==UREG_R27) ? idValW4:
(idRegW5==UREG_R27) ? idValW5: regGprR27;
regGprR28 <=
(idRegW1==UREG_R28) ? idValW1: (idRegW2==UREG_R28) ? idValW2:
(idRegW3==UREG_R28) ? idValW3: (idRegW4==UREG_R28) ? idValW4:
(idRegW5==UREG_R28) ? idValW5: regGprR28;
regGprR29 <=
(idRegW1==UREG_R29) ? idValW1: (idRegW2==UREG_R29) ? idValW2:
(idRegW3==UREG_R29) ? idValW3: (idRegW4==UREG_R29) ? idValW4:
(idRegW5==UREG_R29) ? idValW5: regGprR29;
regGprR30 <=
(idRegW1==UREG_R30) ? idValW1: (idRegW2==UREG_R30) ? idValW2:
(idRegW3==UREG_R30) ? idValW3: (idRegW4==UREG_R30) ? idValW4:
(idRegW5==UREG_R30) ? idValW5: regGprR30;
regGprR31 <=
(idRegW1==UREG_R31) ? idValW1: (idRegW2==UREG_R31) ? idValW2:
(idRegW3==UREG_R31) ? idValW3: (idRegW4==UREG_R31) ? idValW4:
(idRegW5==UREG_R31) ? idValW5: regGprR31;
end
else
begin
regGprR0 <=
(idRegW1==UREG_R0) ? idValW1: (idRegW2==UREG_R0) ? idValW2:
(idRegW3==UREG_R0) ? idValW3: regGprR0;
regGprR1 <=
(idRegW1==UREG_R1) ? idValW1: (idRegW2==UREG_R1) ? idValW2:
(idRegW3==UREG_R1) ? idValW3: regGprR1;
regGprR2 <=
(idRegW1==UREG_R2) ? idValW1: (idRegW2==UREG_R2) ? idValW2:
(idRegW3==UREG_R2) ? idValW3: regGprR2;
regGprR3 <=
(idRegW1==UREG_R3) ? idValW1: (idRegW2==UREG_R3) ? idValW2:
(idRegW3==UREG_R3) ? idValW3: regGprR3;
regGprR4 <=
(idRegW1==UREG_R4) ? idValW1: (idRegW2==UREG_R4) ? idValW2:
(idRegW3==UREG_R4) ? idValW3: regGprR4;
regGprR5 <=
(idRegW1==UREG_R5) ? idValW1: (idRegW2==UREG_R5) ? idValW2:
(idRegW3==UREG_R5) ? idValW3: regGprR5;
regGprR6 <=
(idRegW1==UREG_R6) ? idValW1: (idRegW2==UREG_R6) ? idValW2:
(idRegW3==UREG_R6) ? idValW3: regGprR6;
regGprR7 <=
(idRegW1==UREG_R7) ? idValW1: (idRegW2==UREG_R7) ? idValW2:
(idRegW3==UREG_R7) ? idValW3: regGprR7;
regGprR8 <=
(idRegW1==UREG_R8) ? idValW1: (idRegW2==UREG_R8) ? idValW2:
(idRegW3==UREG_R8) ? idValW3: regGprR8;
regGprR9 <=
(idRegW1==UREG_R9) ? idValW1: (idRegW2==UREG_R9) ? idValW2:
(idRegW3==UREG_R9) ? idValW3: regGprR9;
regGprR10 <=
(idRegW1==UREG_R10) ? idValW1: (idRegW2==UREG_R10) ? idValW2:
(idRegW3==UREG_R10) ? idValW3: regGprR10;
regGprR11 <=
(idRegW1==UREG_R11) ? idValW1: (idRegW2==UREG_R11) ? idValW2:
(idRegW3==UREG_R11) ? idValW3: regGprR11;
regGprR12 <=
(idRegW1==UREG_R12) ? idValW1: (idRegW2==UREG_R12) ? idValW2:
(idRegW3==UREG_R12) ? idValW3: regGprR12;
regGprR13 <=
(idRegW1==UREG_R13) ? idValW1: (idRegW2==UREG_R13) ? idValW2:
(idRegW3==UREG_R13) ? idValW3: regGprR13;
regGprR14 <=
(idRegW1==UREG_R14) ? idValW1: (idRegW2==UREG_R14) ? idValW2:
(idRegW3==UREG_R14) ? idValW3: regGprR14;
regGprR15 <=
(idRegW1==UREG_R15) ? idValW1: (idRegW2==UREG_R15) ? idValW2:
(idRegW3==UREG_R15) ? idValW3: regGprR15;
regGprR16 <=
(idRegW1==UREG_R16) ? idValW1: (idRegW2==UREG_R16) ? idValW2:
(idRegW3==UREG_R16) ? idValW3: regGprR16;
regGprR17 <=
(idRegW1==UREG_R17) ? idValW1: (idRegW2==UREG_R17) ? idValW2:
(idRegW3==UREG_R17) ? idValW3: regGprR17;
regGprR18 <=
(idRegW1==UREG_R18) ? idValW1: (idRegW2==UREG_R18) ? idValW2:
(idRegW3==UREG_R18) ? idValW3: regGprR18;
regGprR19 <=
(idRegW1==UREG_R19) ? idValW1: (idRegW2==UREG_R19) ? idValW2:
(idRegW3==UREG_R19) ? idValW3: regGprR19;
regGprR20 <=
(idRegW1==UREG_R20) ? idValW1: (idRegW2==UREG_R20) ? idValW2:
(idRegW3==UREG_R20) ? idValW3: regGprR20;
regGprR21 <=
(idRegW1==UREG_R21) ? idValW1: (idRegW2==UREG_R21) ? idValW2:
(idRegW3==UREG_R21) ? idValW3: regGprR21;
regGprR22 <=
(idRegW1==UREG_R22) ? idValW1: (idRegW2==UREG_R22) ? idValW2:
(idRegW3==UREG_R22) ? idValW3: regGprR22;
regGprR23 <=
(idRegW1==UREG_R23) ? idValW1: (idRegW2==UREG_R23) ? idValW2:
(idRegW3==UREG_R23) ? idValW3: regGprR23;
regGprR24 <=
(idRegW1==UREG_R24) ? idValW1: (idRegW2==UREG_R24) ? idValW2:
(idRegW3==UREG_R24) ? idValW3: regGprR24;
regGprR25 <=
(idRegW1==UREG_R25) ? idValW1: (idRegW2==UREG_R25) ? idValW2:
(idRegW3==UREG_R25) ? idValW3: regGprR25;
regGprR26 <=
(idRegW1==UREG_R26) ? idValW1: (idRegW2==UREG_R26) ? idValW2:
(idRegW3==UREG_R26) ? idValW3: regGprR26;
regGprR27 <=
(idRegW1==UREG_R27) ? idValW1: (idRegW2==UREG_R27) ? idValW2:
(idRegW3==UREG_R27) ? idValW3: regGprR27;
regGprR28 <=
(idRegW1==UREG_R28) ? idValW1: (idRegW2==UREG_R28) ? idValW2:
(idRegW3==UREG_R28) ? idValW3: regGprR28;
regGprR29 <=
(idRegW1==UREG_R29) ? idValW1: (idRegW2==UREG_R29) ? idValW2:
(idRegW3==UREG_R29) ? idValW3: regGprR29;
regGprR30 <=
(idRegW1==UREG_R30) ? idValW1: (idRegW2==UREG_R30) ? idValW2:
(idRegW3==UREG_R30) ? idValW3: regGprR30;
regGprR31 <=
(idRegW1==UREG_R31) ? idValW1: (idRegW2==UREG_R31) ? idValW2:
(idRegW3==UREG_R31) ? idValW3: regGprR31;
end
regGprR0B <= (idRegW1==UREG_R0B) ? idValW1: regGprR0B;
regGprR1B <= (idRegW1==UREG_R1B) ? idValW1: regGprR1B;
regGprR2B <= (idRegW1==UREG_R2B) ? idValW1: regGprR2B;
regGprR3B <= (idRegW1==UREG_R3B) ? idValW1: regGprR3B;
regGprR4B <= (idRegW1==UREG_R4B) ? idValW1: regGprR4B;
regGprR5B <= (idRegW1==UREG_R5B) ? idValW1: regGprR5B;
regGprR6B <= (idRegW1==UREG_R6B) ? idValW1: regGprR6B;
regGprR7B <= (idRegW1==UREG_R7B) ? idValW1: regGprR7B;
regGprR16B <= (idRegW1==UREG_R16B) ? idValW1: regGprR16B;
regGprR17B <= (idRegW1==UREG_R17B) ? idValW1: regGprR17B;
regGprR18B <= (idRegW1==UREG_R18B) ? idValW1: regGprR18B;
regGprR19B <= (idRegW1==UREG_R19B) ? idValW1: regGprR19B;
regGprR20B <= (idRegW1==UREG_R20B) ? idValW1: regGprR20B;
regGprR21B <= (idRegW1==UREG_R21B) ? idValW1: regGprR21B;
regGprR22B <= (idRegW1==UREG_R22B) ? idValW1: regGprR22B;
regGprR23B <= (idRegW1==UREG_R23B) ? idValW1: regGprR23B;
end
if(regFprRB^nxtRegFprRB)
begin
regFprFR00 <= nxtRegFprXF00; regFprFR01 <= nxtRegFprXF01;
regFprFR02 <= nxtRegFprXF02; regFprFR03 <= nxtRegFprXF03;
regFprFR04 <= nxtRegFprXF04; regFprFR05 <= nxtRegFprXF05;
regFprFR06 <= nxtRegFprXF06; regFprFR07 <= nxtRegFprXF07;
regFprFR08 <= nxtRegFprXF08; regFprFR09 <= nxtRegFprXF09;
regFprFR10 <= nxtRegFprXF10; regFprFR11 <= nxtRegFprXF11;
regFprFR12 <= nxtRegFprXF12; regFprFR13 <= nxtRegFprXF13;
regFprFR14 <= nxtRegFprXF14; regFprFR15 <= nxtRegFprXF15;
regFprXF00 <= nxtRegFprFR00; regFprXF01 <= nxtRegFprFR01;
regFprXF02 <= nxtRegFprFR02; regFprXF03 <= nxtRegFprFR03;
regFprXF04 <= nxtRegFprFR04; regFprXF05 <= nxtRegFprFR05;
regFprXF06 <= nxtRegFprFR06; regFprXF07 <= nxtRegFprFR07;
regFprXF08 <= nxtRegFprFR08; regFprXF09 <= nxtRegFprFR09;
regFprXF10 <= nxtRegFprFR10; regFprXF11 <= nxtRegFprFR11;
regFprXF12 <= nxtRegFprFR12; regFprXF13 <= nxtRegFprFR13;
regFprXF14 <= nxtRegFprFR14; regFprXF15 <= nxtRegFprFR15;
end
else
begin
regFprFR00 <= nxtRegFprFR00; regFprFR01 <= nxtRegFprFR01;
regFprFR02 <= nxtRegFprFR02; regFprFR03 <= nxtRegFprFR03;
regFprFR04 <= nxtRegFprFR04; regFprFR05 <= nxtRegFprFR05;
regFprFR06 <= nxtRegFprFR06; regFprFR07 <= nxtRegFprFR07;
regFprFR08 <= nxtRegFprFR08; regFprFR09 <= nxtRegFprFR09;
regFprFR10 <= nxtRegFprFR10; regFprFR11 <= nxtRegFprFR11;
regFprFR12 <= nxtRegFprFR12; regFprFR13 <= nxtRegFprFR13;
regFprFR14 <= nxtRegFprFR14; regFprFR15 <= nxtRegFprFR15;
regFprXF00 <= nxtRegFprXF00; regFprXF01 <= nxtRegFprXF01;
regFprXF02 <= nxtRegFprXF02; regFprXF03 <= nxtRegFprXF03;
regFprXF04 <= nxtRegFprXF04; regFprXF05 <= nxtRegFprXF05;
regFprXF06 <= nxtRegFprXF06; regFprXF07 <= nxtRegFprXF07;
regFprXF08 <= nxtRegFprXF08; regFprXF09 <= nxtRegFprXF09;
regFprXF10 <= nxtRegFprXF10; regFprXF11 <= nxtRegFprXF11;
regFprXF12 <= nxtRegFprXF12; regFprXF13 <= nxtRegFprXF13;
regFprXF14 <= nxtRegFprXF14; regFprXF15 <= nxtRegFprXF15;
end
regSr <= (idRegW1==UREG_SR ) ? idValW1 : exNextSr2;
regPr <= (idRegW1==UREG_PR ) ? idValW1 : exNextPr2;
regPc <= (idRegW1==UREG_PC ) ? idValW1 : exNextPc2;
regMach <= (idRegW1==UREG_MACL ) ? idValW1 : exNextMach2;
regMacl <= (idRegW1==UREG_MACH ) ? idValW1 : exNextMacl2;
regSp <= (idRegW1==UREG_R15 ) ? idValW1 : exNextSp2;
regGbr <= (idRegW1==UREG_GBR ) ? idValW1 : exNextGbr2;
regVbr <= (idRegW1==UREG_VBR ) ? idValW1 : exNextVbr2;
regSSr <= (idRegW1==UREG_SSR ) ? idValW1 : exNextSSr2;
regSPc <= (idRegW1==UREG_SPC ) ? idValW1 : exNextSPc2;
regSGr <= (idRegW1==UREG_SGR ) ? idValW1 : exNextSGr2;
regFpul <= (idRegW1==UREG_FPUL ) ? idValW1 : exNextFpul2;
regFpScr <= (idRegW1==UREG_FPSCR ) ? idValW1 : exNextFpScr2;
end
endmodule | 2 |
142,537 | data/full_repos/permissive/99182535/smalltst/compdec/FbNtMod.v | 99,182,535 | FbNtMod.v | v | 47 | 43 | [] | [] | [] | [(5, 277), (283, 423), (456, 889), (892, 932)] | null | null | 1: b'%Error: data/full_repos/permissive/99182535/smalltst/compdec/FbNtMod.v:1: Cannot find include file: ModNtsc.v\n`include "ModNtsc.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/smalltst/compdec,data/full_repos/permissive/99182535/ModNtsc.v\n data/full_repos/permissive/99182535/smalltst/compdec,data/full_repos/permissive/99182535/ModNtsc.v.v\n data/full_repos/permissive/99182535/smalltst/compdec,data/full_repos/permissive/99182535/ModNtsc.v.sv\n ModNtsc.v\n ModNtsc.v.v\n ModNtsc.v.sv\n obj_dir/ModNtsc.v\n obj_dir/ModNtsc.v.v\n obj_dir/ModNtsc.v.sv\n%Error: data/full_repos/permissive/99182535/smalltst/compdec/FbNtMod.v:2: Cannot find include file: ModFbMem.v\n`include "ModFbMem.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/smalltst/compdec/FbNtMod.v:3: Cannot find include file: ModFbCc.v\n`include "ModFbCc.v" \n ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 314,749 | module | module FbNtMod(clock, reset, pwmOut,
busAddr, busData, busOE, busWR, busHold);
input clock;
input reset;
output[3:0] pwmOut;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
wire[7:0] pixCy;
wire[7:0] pixCu;
wire[7:0] pixCv;
wire[9:0] pixPosX;
wire[9:0] pixPosY;
wire[13:0] pixCellIx;
wire[31:0] cellData1;
wire[31:0] cellData2;
ModNtsc ntsc(clock, reset,
pixCy, pixCu, pixCv,
pwmOut, pixPosX, pixPosY);
ModFbMem fbmem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold);
ModFbCc fbcc(clock, reset,
pixPosX, pixPosY,
pixCy, pixCu, pixCv,
pixCellIx, cellData1, cellData2);
endmodule | module FbNtMod(clock, reset, pwmOut,
busAddr, busData, busOE, busWR, busHold); |
input clock;
input reset;
output[3:0] pwmOut;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
wire[7:0] pixCy;
wire[7:0] pixCu;
wire[7:0] pixCv;
wire[9:0] pixPosX;
wire[9:0] pixPosY;
wire[13:0] pixCellIx;
wire[31:0] cellData1;
wire[31:0] cellData2;
ModNtsc ntsc(clock, reset,
pixCy, pixCu, pixCv,
pwmOut, pixPosX, pixPosY);
ModFbMem fbmem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold);
ModFbCc fbcc(clock, reset,
pixPosX, pixPosY,
pixCy, pixCu, pixCv,
pixCellIx, cellData1, cellData2);
endmodule | 2 |
142,540 | data/full_repos/permissive/99182535/smalltst/compdec/ModFbMem.v | 99,182,535 | ModFbMem.v | v | 147 | 83 | [] | [] | [] | [(6, 146)] | null | data/verilator_xmls/35db3167-e91b-49df-adfa-6a6f4c8273f3.xml | null | 314,752 | module | module ModFbMem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold);
input clock;
input reset;
input[13:0] pixCellIx;
output[31:0] cellData1;
output[31:0] cellData2;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
reg tBusHold;
reg[31:0] tBusData;
wire tBusCSel;
assign busHold = (busOE && tBusCSel) ? tBusHold : 1'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[39:16]==24'hA0_A000) ||
(busAddr[39:16]==24'h00_ACA0) ||
(busAddr[39:16]==24'h00_ACA1);
reg[13:0] tPixCellIx;
(* ram_style="block" *) reg[31:0] scrCell1A[0:511];
(* ram_style="block" *) reg[31:0] scrCell1B[0:511];
reg[31:0] scrRegCtrl[7:0];
reg scrIs320;
reg scrCellNoRead;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
assign cellData1 = tCell1;
assign cellData2 = tCell2;
always @ (clock)
begin
tBusHold = 1;
tBusData = 0;
if(busOE && tBusCSel)
begin
if(busAddr[15:8]==255)
begin
tBusHold=0;
case(busAddr[6:2])
0: tBusData = scrRegCtrl[0];
1: tBusData = scrRegCtrl[1];
2: tBusData = scrRegCtrl[2];
3: tBusData = scrRegCtrl[3];
8: tBusData = {18'h0, pixCellIx};
endcase
end
else
begin
tBusHold = tPixCellIx != busAddr[15:2];
tBusData = busAddr[2] ? tCell2 : tCell1;
end
end
end
always @ (posedge clock)
begin
tCell1 <= tNextCell1;
tCell2 <= tNextCell2;
tPixCellIx <= pixCellIx;
if(tBusCSel && busWR && !busOE)
begin
scrCellNoRead <= 0;
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else
begin
if(busAddr[2])
scrCell1B[busAddr[11:3]] <= busData;
else
scrCell1A[busAddr[11:3]] <= busData;
end
end
end
always @ (posedge clock)
begin
tNextCell1 <= scrCell1A[pixCellIx[9:1]];
tNextCell2 <= scrCell1B[pixCellIx[9:1]];
end
endmodule | module ModFbMem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold); |
input clock;
input reset;
input[13:0] pixCellIx;
output[31:0] cellData1;
output[31:0] cellData2;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
reg tBusHold;
reg[31:0] tBusData;
wire tBusCSel;
assign busHold = (busOE && tBusCSel) ? tBusHold : 1'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[39:16]==24'hA0_A000) ||
(busAddr[39:16]==24'h00_ACA0) ||
(busAddr[39:16]==24'h00_ACA1);
reg[13:0] tPixCellIx;
(* ram_style="block" *) reg[31:0] scrCell1A[0:511];
(* ram_style="block" *) reg[31:0] scrCell1B[0:511];
reg[31:0] scrRegCtrl[7:0];
reg scrIs320;
reg scrCellNoRead;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
assign cellData1 = tCell1;
assign cellData2 = tCell2;
always @ (clock)
begin
tBusHold = 1;
tBusData = 0;
if(busOE && tBusCSel)
begin
if(busAddr[15:8]==255)
begin
tBusHold=0;
case(busAddr[6:2])
0: tBusData = scrRegCtrl[0];
1: tBusData = scrRegCtrl[1];
2: tBusData = scrRegCtrl[2];
3: tBusData = scrRegCtrl[3];
8: tBusData = {18'h0, pixCellIx};
endcase
end
else
begin
tBusHold = tPixCellIx != busAddr[15:2];
tBusData = busAddr[2] ? tCell2 : tCell1;
end
end
end
always @ (posedge clock)
begin
tCell1 <= tNextCell1;
tCell2 <= tNextCell2;
tPixCellIx <= pixCellIx;
if(tBusCSel && busWR && !busOE)
begin
scrCellNoRead <= 0;
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else
begin
if(busAddr[2])
scrCell1B[busAddr[11:3]] <= busData;
else
scrCell1A[busAddr[11:3]] <= busData;
end
end
end
always @ (posedge clock)
begin
tNextCell1 <= scrCell1A[pixCellIx[9:1]];
tNextCell2 <= scrCell1B[pixCellIx[9:1]];
end
endmodule | 2 |
142,541 | data/full_repos/permissive/99182535/smalltst/compdec/ModFbMem_0.v | 99,182,535 | ModFbMem_0.v | v | 219 | 80 | [] | [] | [] | [(1, 219)] | null | data/verilator_xmls/fded504a-9da4-4952-a2c1-899616066026.xml | null | 314,753 | module | module ModFbMem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold);
input clock;
input reset;
input[13:0] pixCellIx;
output[31:0] cellData1;
output[31:0] cellData2;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
reg tBusHold;
reg[31:0] tBusData;
wire tBusCSel;
assign busHold = (busOE && tBusCSel) ? tBusHold : 1'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[39:16]==24'hA0_A000);
wire[13:0] tReadAddr;
assign tReadAddr = (busOE && tBusCSel) ? busAddr[15:2] : pixCellIx;
reg[13:0] tPixCellIx;
(* ram_style="block" *) reg[31:0] scrCell1A[0:2047];
(* ram_style="block" *) reg[31:0] scrCell1B[0:2047];
(* ram_style="block" *) reg[31:0] scrCell2A[0:511];
(* ram_style="block" *) reg[31:0] scrCell2B[0:511];
reg[31:0] scrRegCtrl[7:0];
reg scrIs320;
reg scrCellNoRead;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
assign cellData1 = tCell1;
assign cellData2 = tCell2;
always @ (clock)
begin
tBusHold = 1;
tBusData = 0;
if(busOE && tBusCSel)
begin
tBusHold = tPixCellIx != busAddr[15:2];
tBusData = busAddr[2] ? tCell2 : tCell1;
end
end
always @ (posedge clock)
begin
tCell1 <= tNextCell1;
tCell2 <= tNextCell2;
if(tBusCSel && busOE && !busWR)
begin
tPixCellIx <= busAddr[15:2];
end
else
begin
tPixCellIx <= pixCellIx;
end
if(tBusCSel && busWR && !busOE)
begin
scrCellNoRead <= 1;
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else if(busAddr[14])
begin
if(busAddr[2])
begin
scrCell2B[busAddr[11:3]] <= busData;
end
else
begin
scrCell2A[busAddr[11:3]] <= busData;
end
end
else
begin
if(busAddr[2])
begin
scrCell1B[busAddr[13:3]] <= busData;
end
else
begin
scrCell1A[busAddr[13:3]] <= busData;
end
end
end
end
always @ (posedge clock)
begin
if(!busWR)
begin
scrCellNoRead <= 0;
if(tReadAddr[12])
begin
tNextCell1 <= scrCell2A[tReadAddr[9:1]];
tNextCell2 <= scrCell2B[tReadAddr[9:1]];
end
else
begin
tNextCell1 <= scrCell1A[tReadAddr[11:1]];
tNextCell2 <= scrCell1B[tReadAddr[11:1]];
end
end
end
endmodule | module ModFbMem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold); |
input clock;
input reset;
input[13:0] pixCellIx;
output[31:0] cellData1;
output[31:0] cellData2;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
reg tBusHold;
reg[31:0] tBusData;
wire tBusCSel;
assign busHold = (busOE && tBusCSel) ? tBusHold : 1'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[39:16]==24'hA0_A000);
wire[13:0] tReadAddr;
assign tReadAddr = (busOE && tBusCSel) ? busAddr[15:2] : pixCellIx;
reg[13:0] tPixCellIx;
(* ram_style="block" *) reg[31:0] scrCell1A[0:2047];
(* ram_style="block" *) reg[31:0] scrCell1B[0:2047];
(* ram_style="block" *) reg[31:0] scrCell2A[0:511];
(* ram_style="block" *) reg[31:0] scrCell2B[0:511];
reg[31:0] scrRegCtrl[7:0];
reg scrIs320;
reg scrCellNoRead;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
assign cellData1 = tCell1;
assign cellData2 = tCell2;
always @ (clock)
begin
tBusHold = 1;
tBusData = 0;
if(busOE && tBusCSel)
begin
tBusHold = tPixCellIx != busAddr[15:2];
tBusData = busAddr[2] ? tCell2 : tCell1;
end
end
always @ (posedge clock)
begin
tCell1 <= tNextCell1;
tCell2 <= tNextCell2;
if(tBusCSel && busOE && !busWR)
begin
tPixCellIx <= busAddr[15:2];
end
else
begin
tPixCellIx <= pixCellIx;
end
if(tBusCSel && busWR && !busOE)
begin
scrCellNoRead <= 1;
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else if(busAddr[14])
begin
if(busAddr[2])
begin
scrCell2B[busAddr[11:3]] <= busData;
end
else
begin
scrCell2A[busAddr[11:3]] <= busData;
end
end
else
begin
if(busAddr[2])
begin
scrCell1B[busAddr[13:3]] <= busData;
end
else
begin
scrCell1A[busAddr[13:3]] <= busData;
end
end
end
end
always @ (posedge clock)
begin
if(!busWR)
begin
scrCellNoRead <= 0;
if(tReadAddr[12])
begin
tNextCell1 <= scrCell2A[tReadAddr[9:1]];
tNextCell2 <= scrCell2B[tReadAddr[9:1]];
end
else
begin
tNextCell1 <= scrCell1A[tReadAddr[11:1]];
tNextCell2 <= scrCell1B[tReadAddr[11:1]];
end
end
end
endmodule | 2 |
142,544 | data/full_repos/permissive/99182535/smalltst/compdec/TxtNtTop.v | 99,182,535 | TxtNtTop.v | v | 34 | 46 | [] | [] | [] | [(5, 277), (286, 444), (469, 742), (745, 790), (792, 821)] | null | null | 1: b'%Error: data/full_repos/permissive/99182535/smalltst/compdec/TxtNtTop.v:1: Cannot find include file: TxtNtModW.v\n`include "TxtNtModW.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/smalltst/compdec,data/full_repos/permissive/99182535/TxtNtModW.v\n data/full_repos/permissive/99182535/smalltst/compdec,data/full_repos/permissive/99182535/TxtNtModW.v.v\n data/full_repos/permissive/99182535/smalltst/compdec,data/full_repos/permissive/99182535/TxtNtModW.v.sv\n TxtNtModW.v\n TxtNtModW.v.v\n TxtNtModW.v.sv\n obj_dir/TxtNtModW.v\n obj_dir/TxtNtModW.v.v\n obj_dir/TxtNtModW.v.sv\n%Error: Exiting due to 1 error(s)\n' | 314,761 | module | module TxtNtTop(clock, reset, pwmOut);
input clock;
input reset;
output pwmOut;
TxtNtModW txtntmod(clock, reset, tPwmOut,
tBusAddr, tBusData, tBusOE, tBusWR, tBusOK);
wire[3:0] tPwmOut;
wire tBusOK;
wire[31:0] tBusData;
reg[31:0] tBusAddr;
reg tBusOE;
reg tBusWR;
assign pwmOut = tPwmOut[3];
always @ (clock)
begin
tBusAddr = 0;
tBusOE = 0;
tBusWR = 0;
end
endmodule | module TxtNtTop(clock, reset, pwmOut); |
input clock;
input reset;
output pwmOut;
TxtNtModW txtntmod(clock, reset, tPwmOut,
tBusAddr, tBusData, tBusOE, tBusWR, tBusOK);
wire[3:0] tPwmOut;
wire tBusOK;
wire[31:0] tBusData;
reg[31:0] tBusAddr;
reg tBusOE;
reg tBusWR;
assign pwmOut = tPwmOut[3];
always @ (clock)
begin
tBusAddr = 0;
tBusOE = 0;
tBusWR = 0;
end
endmodule | 2 |
142,548 | data/full_repos/permissive/99182535/srvcore/GpReg_0.v | 99,182,535 | GpReg_0.v | v | 160 | 34 | [] | [] | [] | [(5, 159)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/GpReg_0.v:89: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dataLo1'\n : ... In instance GpReg\n dataLo1 = regs[tIdReg1Lo];\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/GpReg_0.v:91: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dataHi1'\n : ... In instance GpReg\n dataHi1 = regs[tIdReg1Hi];\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/GpReg_0.v:110: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dataLo2'\n : ... In instance GpReg\n dataLo2 = regs[tIdReg2Lo];\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/GpReg_0.v:112: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dataHi2'\n : ... In instance GpReg\n dataHi2 = regs[tIdReg2Hi];\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/GpReg_0.v:127: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dataLo3'\n : ... In instance GpReg\n dataLo3 = regs[tIdReg3Lo];\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/GpReg_0.v:129: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dataHi3'\n : ... In instance GpReg\n dataHi3 = regs[tIdReg3Hi];\n ^~~~~~~\n%Error: Exiting due to 6 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 314,782 | module | module GpReg(
clk,
isRd1,
isWr1,
isQw1,
idReg1,
dataLo1,
dataHi1,
isRd2,
isWr2,
isQw2,
idReg2,
dataLo2,
dataHi2,
isRd3,
isWr3,
isQw3,
idReg3,
dataLo3,
dataHi3
);
input clk;
input isRd1;
input isRd2;
input isRd3;
input isWr1;
input isWr2;
input isWr3;
input isQw1;
input isQw2;
input isQw3;
input[6:0] idReg1;
input[6:0] idReg2;
input[6:0] idReg3;
inout[31:0] dataLo1;
inout[31:0] dataHi1;
inout[31:0] dataLo2;
inout[31:0] dataHi2;
inout[31:0] dataLo3;
inout[31:0] dataHi3;
reg[31:0] regs[0:127];
reg[6:0] tIdReg1Lo;
reg[6:0] tIdReg1Hi;
reg[6:0] tIdReg2Lo;
reg[6:0] tIdReg2Hi;
reg[6:0] tIdReg3Lo;
reg[6:0] tIdReg3Hi;
always @ (isRd1 or isWr1) begin
tIdReg1Lo = idReg1;
tIdReg1Hi = idReg1 | (7'h40);
if(isRd1==1'b1)
begin
dataLo1 = regs[tIdReg1Lo];
if(isQw1==1'b1)
dataHi1 = regs[tIdReg1Hi];
end
end
always @ (isRd2 or isWr2) begin
tIdReg2Lo = idReg2;
tIdReg2Hi = idReg2 | (7'h40);
if(isRd2==1'b1)
begin
dataLo2 = regs[tIdReg2Lo];
if(isQw2==1'b1)
dataHi2 = regs[tIdReg2Hi];
end
end
always @ (isRd3 or isWr3) begin
tIdReg3Lo = idReg3;
tIdReg3Hi = idReg3 | (7'h40);
if(isRd3==1'b1)
begin
dataLo3 = regs[tIdReg3Lo];
if(isQw3==1'b1)
dataHi3 = regs[tIdReg3Hi];
end
end
always @ (negedge clk) begin
if(isWr1==1'b1)
begin
regs[tIdReg1Lo] <= dataLo1;
if(isQw1==1'b1)
regs[tIdReg1Hi] <= dataHi1;
end
if(isWr2==1'b1)
begin
regs[tIdReg2Lo] <= dataLo2;
if(isQw2==1'b1)
regs[tIdReg2Hi] <= dataHi2;
end
if(isWr3==1'b1)
begin
regs[tIdReg3Lo] <= dataLo3;
if(isQw3==1'b1)
regs[tIdReg3Hi] <= dataHi3;
end
end
endmodule | module GpReg(
clk,
isRd1,
isWr1,
isQw1,
idReg1,
dataLo1,
dataHi1,
isRd2,
isWr2,
isQw2,
idReg2,
dataLo2,
dataHi2,
isRd3,
isWr3,
isQw3,
idReg3,
dataLo3,
dataHi3
); |
input clk;
input isRd1;
input isRd2;
input isRd3;
input isWr1;
input isWr2;
input isWr3;
input isQw1;
input isQw2;
input isQw3;
input[6:0] idReg1;
input[6:0] idReg2;
input[6:0] idReg3;
inout[31:0] dataLo1;
inout[31:0] dataHi1;
inout[31:0] dataLo2;
inout[31:0] dataHi2;
inout[31:0] dataLo3;
inout[31:0] dataHi3;
reg[31:0] regs[0:127];
reg[6:0] tIdReg1Lo;
reg[6:0] tIdReg1Hi;
reg[6:0] tIdReg2Lo;
reg[6:0] tIdReg2Hi;
reg[6:0] tIdReg3Lo;
reg[6:0] tIdReg3Hi;
always @ (isRd1 or isWr1) begin
tIdReg1Lo = idReg1;
tIdReg1Hi = idReg1 | (7'h40);
if(isRd1==1'b1)
begin
dataLo1 = regs[tIdReg1Lo];
if(isQw1==1'b1)
dataHi1 = regs[tIdReg1Hi];
end
end
always @ (isRd2 or isWr2) begin
tIdReg2Lo = idReg2;
tIdReg2Hi = idReg2 | (7'h40);
if(isRd2==1'b1)
begin
dataLo2 = regs[tIdReg2Lo];
if(isQw2==1'b1)
dataHi2 = regs[tIdReg2Hi];
end
end
always @ (isRd3 or isWr3) begin
tIdReg3Lo = idReg3;
tIdReg3Hi = idReg3 | (7'h40);
if(isRd3==1'b1)
begin
dataLo3 = regs[tIdReg3Lo];
if(isQw3==1'b1)
dataHi3 = regs[tIdReg3Hi];
end
end
always @ (negedge clk) begin
if(isWr1==1'b1)
begin
regs[tIdReg1Lo] <= dataLo1;
if(isQw1==1'b1)
regs[tIdReg1Hi] <= dataHi1;
end
if(isWr2==1'b1)
begin
regs[tIdReg2Lo] <= dataLo2;
if(isQw2==1'b1)
regs[tIdReg2Hi] <= dataHi2;
end
if(isWr3==1'b1)
begin
regs[tIdReg3Lo] <= dataLo3;
if(isQw3==1'b1)
regs[tIdReg3Hi] <= dataHi3;
end
end
endmodule | 2 |
142,549 | data/full_repos/permissive/99182535/srvcore/MemAlu.v | 99,182,535 | MemAlu.v | v | 78 | 53 | [] | [] | [] | [(1, 77)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/99182535/srvcore/MemAlu.v:70: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'outAddr'\n : ... In instance MemAlu\n outAddr = tOutAddr;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 314,783 | module | module MemAlu(
clk,
mode,
baseAddr,
idxAddr,
idxDisp,
outAddr
);
input clk;
input[2:0] mode;
input[63:0] baseAddr;
input[31:0] idxAddr;
input[31:0] idxDisp;
output[63:0] outAddr;
reg[31:0] tIdxAddr;
reg[63:0] tIdxAddr2;
reg[63:0] tOutAddr;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_MOV = 3'b111;
parameter[63:0] NULL_ADDR = 64'h0000_0000_0000_0000;
parameter[63:0] NEG_ADDR = 64'hFFFF_FFFF_0000_0000;
always @ (mode) begin
tIdxAddr = idxAddr+idxDisp;
tIdxAddr2[31:0] = tIdxAddr;
tIdxAddr2[63:32] = tIdxAddr[31] ?
32'hFFFF_FFFF :
32'h0000_0000 ;
case(mode)
MD_BYTE: begin
tOutAddr = baseAddr+tIdxAddr2;
end
MD_WORD: begin
tOutAddr = baseAddr+tIdxAddr2*2;
end
MD_DWORD: begin
tOutAddr = baseAddr+tIdxAddr2*4;
end
MD_QWORD: begin
tOutAddr = baseAddr+tIdxAddr2*8;
end
MD_OWORD: begin
tOutAddr = baseAddr+tIdxAddr2*16;
end
MD_MOV: begin
tOutAddr = baseAddr;
end
default: begin
tOutAddr = NULL_ADDR;
end
endcase
outAddr = tOutAddr;
end
endmodule | module MemAlu(
clk,
mode,
baseAddr,
idxAddr,
idxDisp,
outAddr
); |
input clk;
input[2:0] mode;
input[63:0] baseAddr;
input[31:0] idxAddr;
input[31:0] idxDisp;
output[63:0] outAddr;
reg[31:0] tIdxAddr;
reg[63:0] tIdxAddr2;
reg[63:0] tOutAddr;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_MOV = 3'b111;
parameter[63:0] NULL_ADDR = 64'h0000_0000_0000_0000;
parameter[63:0] NEG_ADDR = 64'hFFFF_FFFF_0000_0000;
always @ (mode) begin
tIdxAddr = idxAddr+idxDisp;
tIdxAddr2[31:0] = tIdxAddr;
tIdxAddr2[63:32] = tIdxAddr[31] ?
32'hFFFF_FFFF :
32'h0000_0000 ;
case(mode)
MD_BYTE: begin
tOutAddr = baseAddr+tIdxAddr2;
end
MD_WORD: begin
tOutAddr = baseAddr+tIdxAddr2*2;
end
MD_DWORD: begin
tOutAddr = baseAddr+tIdxAddr2*4;
end
MD_QWORD: begin
tOutAddr = baseAddr+tIdxAddr2*8;
end
MD_OWORD: begin
tOutAddr = baseAddr+tIdxAddr2*16;
end
MD_MOV: begin
tOutAddr = baseAddr;
end
default: begin
tOutAddr = NULL_ADDR;
end
endcase
outAddr = tOutAddr;
end
endmodule | 2 |
142,552 | data/full_repos/permissive/99186799/Clock.v | 99,186,799 | Clock.v | v | 75 | 87 | [] | [] | [] | [(6, 75)] | null | null | 1: b"%Error: data/full_repos/permissive/99186799/Clock.v:26: Cannot find file containing module: 'SecondTick'\n SecondTick T1( .CLK(CLK),\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99186799,data/full_repos/permissive/99186799/SecondTick\n data/full_repos/permissive/99186799,data/full_repos/permissive/99186799/SecondTick.v\n data/full_repos/permissive/99186799,data/full_repos/permissive/99186799/SecondTick.sv\n SecondTick\n SecondTick.v\n SecondTick.sv\n obj_dir/SecondTick\n obj_dir/SecondTick.v\n obj_dir/SecondTick.sv\n%Error: data/full_repos/permissive/99186799/Clock.v:30: Cannot find file containing module: 'Adjust'\n Adjust A1( .CLK(CLK),\n ^~~~~~\n%Error: data/full_repos/permissive/99186799/Clock.v:39: Cannot find file containing module: 'SecondsMinutesDigits'\n SecondsMinutesDigits S1( .CLK(CLK),\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99186799/Clock.v:48: Cannot find file containing module: 'SecondsMinutesDigits'\n SecondsMinutesDigits S2( .CLK(CLK),\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99186799/Clock.v:57: Cannot find file containing module: 'HoursDigits'\n HoursDigits H1( .CLK(CLK),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99186799/Clock.v:65: Cannot find file containing module: 'SevenSegmentDriver'\n SevenSegmentDriver S3( .CLK(CLK),\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 314,789 | module | module Clock(CLK, RST, ButtonMode, ButtonDigit, ButtonValue, DigitEnable, DigitValue);
input CLK;
input RST;
input ButtonMode, ButtonDigit, ButtonValue;
output[5:0] DigitEnable;
output[6:0] DigitValue;
wire SecondTick;
wire MinuteTick;
wire HourTick;
wire[3:0] SecMSD, SecLSD, MinMSD, MinLSD, HourMSD, HourLSD;
wire[2:0] ActiveDigit;
wire IncrementDigit;
wire GlobalPause;
wire[2:0] EnableEdit;
SecondTick T1( .CLK(CLK),
.RST(RST),
.Tick(SecondTick));
Adjust A1( .CLK(CLK),
.RST(RST),
.ButtonMode(ButtonMode),
.ButtonDigit(ButtonDigit),
.ButtonValue(ButtonValue),
.Editing(GlobalPause),
.Digit(ActiveDigit),
.IncrementDigit(IncrementDigit));
SecondsMinutesDigits S1( .CLK(CLK),
.RST(RST),
.InTick(SecondTick & ~GlobalPause),
.EditEnable(ActiveDigit[0] & GlobalPause),
.Increment(IncrementDigit),
.OutTick(MinuteTick),
.MSD(SecMSD),
.LSD(SecLSD));
SecondsMinutesDigits S2( .CLK(CLK),
.RST(RST),
.InTick(MinuteTick & ~GlobalPause),
.EditEnable(ActiveDigit[1] & GlobalPause),
.Increment(IncrementDigit),
.OutTick(HourTick),
.MSD(MinMSD),
.LSD(MinLSD));
HoursDigits H1( .CLK(CLK),
.RST(RST),
.InTick(HourTick & ~GlobalPause),
.EditEnable(ActiveDigit[2] & GlobalPause),
.Increment(IncrementDigit),
.MSD(HourMSD),
.LSD(HourLSD));
SevenSegmentDriver S3( .CLK(CLK),
.RST(RST),
.HourMSD(HourMSD),
.HourLSD(HourLSD),
.MinMSD(MinMSD),
.MinLSD(MinLSD),
.SecMSD(SecMSD),
.SecLSD(SecLSD),
.DigitEnable(DigitEnable),
.DigitValue(DigitValue));
endmodule | module Clock(CLK, RST, ButtonMode, ButtonDigit, ButtonValue, DigitEnable, DigitValue); |
input CLK;
input RST;
input ButtonMode, ButtonDigit, ButtonValue;
output[5:0] DigitEnable;
output[6:0] DigitValue;
wire SecondTick;
wire MinuteTick;
wire HourTick;
wire[3:0] SecMSD, SecLSD, MinMSD, MinLSD, HourMSD, HourLSD;
wire[2:0] ActiveDigit;
wire IncrementDigit;
wire GlobalPause;
wire[2:0] EnableEdit;
SecondTick T1( .CLK(CLK),
.RST(RST),
.Tick(SecondTick));
Adjust A1( .CLK(CLK),
.RST(RST),
.ButtonMode(ButtonMode),
.ButtonDigit(ButtonDigit),
.ButtonValue(ButtonValue),
.Editing(GlobalPause),
.Digit(ActiveDigit),
.IncrementDigit(IncrementDigit));
SecondsMinutesDigits S1( .CLK(CLK),
.RST(RST),
.InTick(SecondTick & ~GlobalPause),
.EditEnable(ActiveDigit[0] & GlobalPause),
.Increment(IncrementDigit),
.OutTick(MinuteTick),
.MSD(SecMSD),
.LSD(SecLSD));
SecondsMinutesDigits S2( .CLK(CLK),
.RST(RST),
.InTick(MinuteTick & ~GlobalPause),
.EditEnable(ActiveDigit[1] & GlobalPause),
.Increment(IncrementDigit),
.OutTick(HourTick),
.MSD(MinMSD),
.LSD(MinLSD));
HoursDigits H1( .CLK(CLK),
.RST(RST),
.InTick(HourTick & ~GlobalPause),
.EditEnable(ActiveDigit[2] & GlobalPause),
.Increment(IncrementDigit),
.MSD(HourMSD),
.LSD(HourLSD));
SevenSegmentDriver S3( .CLK(CLK),
.RST(RST),
.HourMSD(HourMSD),
.HourLSD(HourLSD),
.MinMSD(MinMSD),
.MinLSD(MinLSD),
.SecMSD(SecMSD),
.SecLSD(SecLSD),
.DigitEnable(DigitEnable),
.DigitValue(DigitValue));
endmodule | 1 |
142,554 | data/full_repos/permissive/99186799/SecondTick.v | 99,186,799 | SecondTick.v | v | 31 | 45 | [] | [] | [] | [(6, 31)] | null | data/verilator_xmls/a42dc95c-3c25-4310-ae00-b9834a058737.xml | null | 314,792 | module | module SecondTick(CLK, RST, Tick);
input CLK;
input RST;
output reg Tick;
parameter CLOCKSPEED = 100000000;
reg[26:0] Counter;
always @ (posedge CLK or posedge RST) begin
if(RST) begin
Tick <= 1'b0;
Counter <= 27'd0;
end else begin
Counter <= Counter + 1;
if(Counter == CLOCKSPEED) begin
Tick <= 1'b1;
Counter <= 27'd0;
end else begin
Tick <= 1'b0;
end
end
end
endmodule | module SecondTick(CLK, RST, Tick); |
input CLK;
input RST;
output reg Tick;
parameter CLOCKSPEED = 100000000;
reg[26:0] Counter;
always @ (posedge CLK or posedge RST) begin
if(RST) begin
Tick <= 1'b0;
Counter <= 27'd0;
end else begin
Counter <= Counter + 1;
if(Counter == CLOCKSPEED) begin
Tick <= 1'b1;
Counter <= 27'd0;
end else begin
Tick <= 1'b0;
end
end
end
endmodule | 1 |
142,562 | data/full_repos/permissive/99191002/synchronizer/reset_synch/reset_removal_tb.v | 99,191,002 | reset_removal_tb.v | v | 28 | 65 | [] | [] | [] | null | line:13: before: "/" | null | 1: b"%Error: data/full_repos/permissive/99191002/synchronizer/reset_synch/reset_removal_tb.v:13: Define or directive not defined: '`CYCLE'\n forever #(`CYCLE/2) clk <= ~clk; \n ^~~~~~\n%Error: data/full_repos/permissive/99191002/synchronizer/reset_synch/reset_removal_tb.v:13: syntax error, unexpected '/', expecting TYPE-IDENTIFIER\n forever #(`CYCLE/2) clk <= ~clk; \n ^\n%Error: data/full_repos/permissive/99191002/synchronizer/reset_synch/reset_removal_tb.v:18: syntax error, unexpected '@'\n @(posedge clk); \n ^\n%Error: Exiting due to 3 error(s)\n" | 314,799 | module | module tb();
initial begin
clk <= 0;
forever #(`CYCLE/2) clk <= ~clk;
end
initial begin
rst_n <= 0;
@(posedge clk);
@(negedge clk) rst_n = 1;
end
endmodule | module tb(); |
initial begin
clk <= 0;
forever #(`CYCLE/2) clk <= ~clk;
end
initial begin
rst_n <= 0;
@(posedge clk);
@(negedge clk) rst_n = 1;
end
endmodule | 2 |
142,564 | data/full_repos/permissive/99191002/synchronizer/single_bit_cdc_synchronizer/single_bit_cdc_synchronizer.v | 99,191,002 | single_bit_cdc_synchronizer.v | v | 69 | 70 | [] | [] | [] | null | line:54: before: ";" | null | 1: b"%Error: data/full_repos/permissive/99191002/synchronizer/single_bit_cdc_synchronizer/single_bit_cdc_synchronizer.v:54: syntax error, unexpected ';', expecting ')' or ','\n output q_out;\n ^\n%Error: data/full_repos/permissive/99191002/synchronizer/single_bit_cdc_synchronizer/single_bit_cdc_synchronizer.v:58: syntax error, unexpected assign\nassign q_out=r[NUM_STAGES-1];\n^~~~~~\n%Error: data/full_repos/permissive/99191002/synchronizer/single_bit_cdc_synchronizer/single_bit_cdc_synchronizer.v:61: syntax error, unexpected always\nalways@(posedge latch_clk)\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 314,802 | module | module single_bit_cdc_synchronizer #(
parameter NUM_STAGES = 3
) (
input clk,
input d_in,
output q_out;
);
reg[NUM_STAGES-1:0] r;
assign q_out=r[NUM_STAGES-1];
integer i;
always@(posedge latch_clk)
begin
for(i=1; i<NUM_STAGES; i=i+1) begin
r[i] <= r[i-1];
end
end
endmodule | module single_bit_cdc_synchronizer #(
parameter NUM_STAGES = 3
) (
input clk,
input d_in,
output q_out; |
);
reg[NUM_STAGES-1:0] r;
assign q_out=r[NUM_STAGES-1];
integer i;
always@(posedge latch_clk)
begin
for(i=1; i<NUM_STAGES; i=i+1) begin
r[i] <= r[i-1];
end
end
endmodule | 2 |
142,565 | data/full_repos/permissive/99191002/translation/grey_to_binary.v | 99,191,002 | grey_to_binary.v | v | 24 | 50 | [] | [] | [] | null | line:19: before: "output" | null | 1: b"%Error: data/full_repos/permissive/99191002/translation/grey_to_binary.v:19: syntax error, unexpected output, expecting ')' or ','\n output [WIDTH-1:0] binary\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 314,805 | module | module grey_to_binary #(
parameter WIDTH=3
) (
input [WIDTH-1:0] grey
output [WIDTH-1:0] binary
);
endmodule | module grey_to_binary #(
parameter WIDTH=3
) (
input [WIDTH-1:0] grey
output [WIDTH-1:0] binary
); |
endmodule | 2 |
142,568 | data/full_repos/permissive/9931590/Cpu.v | 9,931,590 | Cpu.v | v | 90 | 464 | [] | [] | [] | null | line:5: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9931590/Cpu.v:42: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n : ... In instance Cpu\n (addrPrev == 8\'he1) ? btn[0] :\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9931590/Cpu.v:43: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n : ... In instance Cpu\n (addrPrev == 8\'he2) ? btn[1] :\n ^\n%Warning-WIDTH: data/full_repos/permissive/9931590/Cpu.v:44: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n : ... In instance Cpu\n (addrPrev == 8\'he3) ? btn[2] :\n ^\n%Warning-WIDTH: data/full_repos/permissive/9931590/Cpu.v:45: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n : ... In instance Cpu\n (addrPrev == 8\'he4) ? btn[3] :\n ^\n%Error: data/full_repos/permissive/9931590/Cpu.v:48: Cannot find file containing module: \'Operate\'\n Operate operate(.clk(clk), .reset(reset), .start(start), .ack(ack), .instruc(instruc), .rdData(rdData),\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/9931590,data/full_repos/permissive/9931590/Operate\n data/full_repos/permissive/9931590,data/full_repos/permissive/9931590/Operate.v\n data/full_repos/permissive/9931590,data/full_repos/permissive/9931590/Operate.sv\n Operate\n Operate.v\n Operate.sv\n obj_dir/Operate\n obj_dir/Operate.v\n obj_dir/Operate.sv\n%Error: data/full_repos/permissive/9931590/Cpu.v:51: Cannot find file containing module: \'DataMemory\'\n DataMemory dataMemory(.Clk(clk), .rdEn(rdEn), .wrEn(wrEn), .addr(addr), .wrData(wrData),\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n' | 314,808 | module | module Cpu
(clk, reset, start, ack, instruc, btn, sw,
pc, done, ld, ssd0, ssd1, ssd2, ssd3);
localparam INSTRUC_SIZE = 32, ARG_SIZE = 8, DATA_SIZE = 8;
input clk, reset, start, ack;
input [(INSTRUC_SIZE - 1) : 0] instruc;
input [3:0] btn;
input [7:0] sw;
output [(ARG_SIZE - 1) : 0] pc;
output done;
output reg [7:0] ld;
output reg [3:0] ssd0;
output reg [3:0] ssd1;
output reg [3:0] ssd2;
output reg [3:0] ssd3;
wire [(DATA_SIZE - 1) : 0] rdData;
wire rdEn;
wire wrEn;
wire [(ARG_SIZE - 1) : 0] addr;
wire [(DATA_SIZE - 1) : 0] wrData;
wire [(DATA_SIZE - 1) : 0] rdDataMem;
reg [(ARG_SIZE - 1) : 0] addrPrev;
assign rdData = ((addrPrev == 8'he0) ? sw[7:0] :
(addrPrev == 8'he1) ? btn[0] :
(addrPrev == 8'he2) ? btn[1] :
(addrPrev == 8'he3) ? btn[2] :
(addrPrev == 8'he4) ? btn[3] :
rdDataMem);
Operate operate(.clk(clk), .reset(reset), .start(start), .ack(ack), .instruc(instruc), .rdData(rdData),
.rdEn(rdEn), .wrEn(wrEn), .addr(addr), .wrData(wrData), .pc(pc), .done(done));
DataMemory dataMemory(.Clk(clk), .rdEn(rdEn), .wrEn(wrEn), .addr(addr), .wrData(wrData),
.Data(rdDataMem));
always @(posedge clk, posedge reset)
begin
if (reset)
begin
ld <= 8'b0;
ssd0 <= 4'h0;
ssd1 <= 4'h0;
ssd2 <= 4'h0;
ssd3 <= 4'h0;
end
else
begin
addrPrev <= addr;
if (wrEn)
begin
case (addr)
8'hf0: ld[0] <= wrData[0];
8'hf1: ld[1] <= wrData[0];
8'hf2: ld[2] <= wrData[0];
8'hf3: ld[3] <= wrData[0];
8'hf4: ld[4] <= wrData[0];
8'hf5: ld[5] <= wrData[0];
8'hf6: ld[6] <= wrData[0];
8'hf7: ld[7] <= wrData[0];
8'hfa: ssd0 <= wrData[3:0];
8'hfb: ssd1 <= wrData[3:0];
8'hfc: ssd2 <= wrData[3:0];
8'hfd: ssd3 <= wrData[3:0];
endcase
end
end
end
endmodule | module Cpu
(clk, reset, start, ack, instruc, btn, sw,
pc, done, ld, ssd0, ssd1, ssd2, ssd3); |
localparam INSTRUC_SIZE = 32, ARG_SIZE = 8, DATA_SIZE = 8;
input clk, reset, start, ack;
input [(INSTRUC_SIZE - 1) : 0] instruc;
input [3:0] btn;
input [7:0] sw;
output [(ARG_SIZE - 1) : 0] pc;
output done;
output reg [7:0] ld;
output reg [3:0] ssd0;
output reg [3:0] ssd1;
output reg [3:0] ssd2;
output reg [3:0] ssd3;
wire [(DATA_SIZE - 1) : 0] rdData;
wire rdEn;
wire wrEn;
wire [(ARG_SIZE - 1) : 0] addr;
wire [(DATA_SIZE - 1) : 0] wrData;
wire [(DATA_SIZE - 1) : 0] rdDataMem;
reg [(ARG_SIZE - 1) : 0] addrPrev;
assign rdData = ((addrPrev == 8'he0) ? sw[7:0] :
(addrPrev == 8'he1) ? btn[0] :
(addrPrev == 8'he2) ? btn[1] :
(addrPrev == 8'he3) ? btn[2] :
(addrPrev == 8'he4) ? btn[3] :
rdDataMem);
Operate operate(.clk(clk), .reset(reset), .start(start), .ack(ack), .instruc(instruc), .rdData(rdData),
.rdEn(rdEn), .wrEn(wrEn), .addr(addr), .wrData(wrData), .pc(pc), .done(done));
DataMemory dataMemory(.Clk(clk), .rdEn(rdEn), .wrEn(wrEn), .addr(addr), .wrData(wrData),
.Data(rdDataMem));
always @(posedge clk, posedge reset)
begin
if (reset)
begin
ld <= 8'b0;
ssd0 <= 4'h0;
ssd1 <= 4'h0;
ssd2 <= 4'h0;
ssd3 <= 4'h0;
end
else
begin
addrPrev <= addr;
if (wrEn)
begin
case (addr)
8'hf0: ld[0] <= wrData[0];
8'hf1: ld[1] <= wrData[0];
8'hf2: ld[2] <= wrData[0];
8'hf3: ld[3] <= wrData[0];
8'hf4: ld[4] <= wrData[0];
8'hf5: ld[5] <= wrData[0];
8'hf6: ld[6] <= wrData[0];
8'hf7: ld[7] <= wrData[0];
8'hfa: ssd0 <= wrData[3:0];
8'hfb: ssd1 <= wrData[3:0];
8'hfc: ssd2 <= wrData[3:0];
8'hfd: ssd3 <= wrData[3:0];
endcase
end
end
end
endmodule | 3 |
142,571 | data/full_repos/permissive/9931590/DataMemory.v | 9,931,590 | DataMemory.v | v | 43 | 464 | [] | [] | [] | [(12, 42)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9931590/DataMemory.v:30: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'100\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 100 bits.\n : ... In instance DataMemory\n data_out <= 100\'bx;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 314,811 | module | module DataMemory (Clk, rdEn, wrEn, addr, wrData, Data);
parameter WIDTH = 8;
parameter DEPTH = 256;
input Clk;
input rdEn, wrEn;
input [WIDTH-1:0] wrData;
input [7:0] addr;
output [WIDTH-1:0] Data;
reg [WIDTH-1:0] data_out;
reg [WIDTH-1 : 0] memory[DEPTH-1 : 0];
always @ (posedge Clk)
begin : DATA_MEM
data_out <= 100'bx;
if (wrEn)
begin
memory[addr] <= wrData;
end
if (rdEn)
begin
data_out <= memory[addr];
end
end
assign Data = data_out;
endmodule | module DataMemory (Clk, rdEn, wrEn, addr, wrData, Data); |
parameter WIDTH = 8;
parameter DEPTH = 256;
input Clk;
input rdEn, wrEn;
input [WIDTH-1:0] wrData;
input [7:0] addr;
output [WIDTH-1:0] Data;
reg [WIDTH-1:0] data_out;
reg [WIDTH-1 : 0] memory[DEPTH-1 : 0];
always @ (posedge Clk)
begin : DATA_MEM
data_out <= 100'bx;
if (wrEn)
begin
memory[addr] <= wrData;
end
if (rdEn)
begin
data_out <= memory[addr];
end
end
assign Data = data_out;
endmodule | 3 |
142,575 | data/full_repos/permissive/99334690/apple_gen.v | 99,334,690 | apple_gen.v | v | 32 | 65 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/fd63bca3-02b9-4478-a90d-a9b1b02072b1.xml | null | 314,815 | module | module apple_gen(
output reg [5:0] avaliable_apple_x, avaliable_apple_y,
input [5:0] pixel_x, pixel_y, apple_x, apple_y,
input pixel_data,
input clk_25M, rst
);
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
always @ (posedge clk_25M)
if (!pixel_data && pixel_x < WIDTH && pixel_y < HEIGHT && !rst
&& pixel_x != apple_x && pixel_y != apple_y)
begin
avaliable_apple_x <= pixel_x;
avaliable_apple_y <= pixel_y;
end
endmodule | module apple_gen(
output reg [5:0] avaliable_apple_x, avaliable_apple_y,
input [5:0] pixel_x, pixel_y, apple_x, apple_y,
input pixel_data,
input clk_25M, rst
); |
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
always @ (posedge clk_25M)
if (!pixel_data && pixel_x < WIDTH && pixel_y < HEIGHT && !rst
&& pixel_x != apple_x && pixel_y != apple_y)
begin
avaliable_apple_x <= pixel_x;
avaliable_apple_y <= pixel_y;
end
endmodule | 0 |
142,576 | data/full_repos/permissive/99334690/freq_devider.v | 99,334,690 | freq_devider.v | v | 36 | 39 | [] | [] | [] | [(13, 35)] | null | data/verilator_xmls/f2f3bc4f-31d2-414c-af1d-8841016d2340.xml | null | 314,816 | module | module freq_devider(
output reg clk_25M,
output reg clk_400,
output reg clk_5,
input clk_100M
);
reg [22:0] counter;
always @ (posedge clk_100M)
counter <= counter + 1;
always @ (posedge clk_100M)
begin
if (counter[0])
clk_25M <= ~clk_25M;
if (counter[16:0] == 17'hFFFFF)
clk_400 <= ~clk_400;
if (counter == 23'hFFFFFF)
clk_5 <= ~clk_5;
end
endmodule | module freq_devider(
output reg clk_25M,
output reg clk_400,
output reg clk_5,
input clk_100M
); |
reg [22:0] counter;
always @ (posedge clk_100M)
counter <= counter + 1;
always @ (posedge clk_100M)
begin
if (counter[0])
clk_25M <= ~clk_25M;
if (counter[16:0] == 17'hFFFFF)
clk_400 <= ~clk_400;
if (counter == 23'hFFFFFF)
clk_5 <= ~clk_5;
end
endmodule | 0 |
142,577 | data/full_repos/permissive/99334690/input_ctrl.v | 99,334,690 | input_ctrl.v | v | 35 | 70 | [] | [] | [] | [(13, 34)] | null | data/verilator_xmls/ff167249-2809-4399-bab0-765ff3a987aa.xml | null | 314,817 | module | module input_ctrl(
output reg [2:0] key_stroke,
input key_up, key_down, key_left, key_right, pause,
input clk_25M, rst
);
parameter UP = 3'b000, DOWN = 3'b001, LEFT = 3'b010, RIGHT = 3'b011;
parameter PAUSE = 3'b100;
always @ (posedge clk_25M or posedge rst)
if (rst)
key_stroke <= RIGHT;
else
casex ({key_up, key_down, key_left, key_right, pause})
5'b????1: key_stroke <= PAUSE;
5'b???10: key_stroke <= RIGHT;
5'b??100: key_stroke <= LEFT;
5'b?1000: key_stroke <= DOWN;
5'b10000: key_stroke <= UP;
endcase
endmodule | module input_ctrl(
output reg [2:0] key_stroke,
input key_up, key_down, key_left, key_right, pause,
input clk_25M, rst
); |
parameter UP = 3'b000, DOWN = 3'b001, LEFT = 3'b010, RIGHT = 3'b011;
parameter PAUSE = 3'b100;
always @ (posedge clk_25M or posedge rst)
if (rst)
key_stroke <= RIGHT;
else
casex ({key_up, key_down, key_left, key_right, pause})
5'b????1: key_stroke <= PAUSE;
5'b???10: key_stroke <= RIGHT;
5'b??100: key_stroke <= LEFT;
5'b?1000: key_stroke <= DOWN;
5'b10000: key_stroke <= UP;
endcase
endmodule | 0 |
142,578 | data/full_repos/permissive/99334690/pixel_ram_ctrl.v | 99,334,690 | pixel_ram_ctrl.v | v | 91 | 73 | [] | [] | [] | [(13, 90)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99334690/pixel_ram_ctrl.v:31: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'head_x\' generates 6 bits.\n : ... In instance pixel_ram_ctrl\n : (wea ? head_y*WIDTH+head_x : check_y*WIDTH+check_x);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99334690/pixel_ram_ctrl.v:31: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'check_x\' generates 6 bits.\n : ... In instance pixel_ram_ctrl\n : (wea ? head_y*WIDTH+head_x : check_y*WIDTH+check_x);\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/pixel_ram_ctrl.v:32: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'tail_x\' generates 6 bits.\n : ... In instance pixel_ram_ctrl\n assign pixel_pos_b = web ? tail_y*WIDTH+tail_x : pixel_y*WIDTH+pixel_x;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/pixel_ram_ctrl.v:32: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'pixel_x\' generates 6 bits.\n : ... In instance pixel_ram_ctrl\n assign pixel_pos_b = web ? tail_y*WIDTH+tail_x : pixel_y*WIDTH+pixel_x;\n ^\n%Error: data/full_repos/permissive/99334690/pixel_ram_ctrl.v:34: Cannot find file containing module: \'pixel_ram\'\n pixel_ram pr0 (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/pixel_ram\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/pixel_ram.v\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/pixel_ram.sv\n pixel_ram\n pixel_ram.v\n pixel_ram.sv\n obj_dir/pixel_ram\n obj_dir/pixel_ram.v\n obj_dir/pixel_ram.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n' | 314,818 | module | module pixel_ram_ctrl(
output douta, doutb,
input [5:0] head_x, head_y, tail_x, tail_y,
input [5:0] check_x, check_y,
input [5:0] pixel_x, pixel_y,
input clk_25M, clk_5, rst
);
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
wire [10:0] pixel_pos_a, pixel_pos_b;
reg [10:0] rst_pos;
reg wea, web;
reg [1:0] w_pd_counter;
reg dina;
assign pixel_pos_a = rst ? rst_pos
: (wea ? head_y*WIDTH+head_x : check_y*WIDTH+check_x);
assign pixel_pos_b = web ? tail_y*WIDTH+tail_x : pixel_y*WIDTH+pixel_x;
pixel_ram pr0 (
.clka(clk_25M),
.wea(wea),
.addra(pixel_pos_a),
.dina(dina),
.douta(douta),
.clkb(clk_25M),
.web(web),
.addrb(pixel_pos_b),
.dinb(1'b0),
.doutb(doutb)
);
always @ (posedge clk_25M)
if (rst)
begin
web <= 1'b0;
if (rst_pos == 11'd1200)
wea <= 1'b0;
else
wea <= 1'b1;
if (rst_pos == 11'd607 || rst_pos == 11'd608 || rst_pos == 11'd609
|| rst_pos == 11'd1200)
dina <= 1'b1;
else
dina <= 1'b0;
end
else
begin
dina <= 1'b1;
if (~^w_pd_counter)
begin
wea <= 1'b0;
web <= 1'b0;
end
else
begin
wea <= 1'b1;
web <= 1'b1;
end
end
always @ (posedge clk_25M)
if (clk_5 && w_pd_counter != 2'b11)
w_pd_counter <= w_pd_counter + 2'b01;
else if (~clk_5)
w_pd_counter <= 2'b00;
always @ (posedge clk_25M)
if (!rst)
rst_pos <= 11'hFFF;
else if (rst_pos != 11'd1200)
rst_pos <= rst_pos + 11'd1;
endmodule | module pixel_ram_ctrl(
output douta, doutb,
input [5:0] head_x, head_y, tail_x, tail_y,
input [5:0] check_x, check_y,
input [5:0] pixel_x, pixel_y,
input clk_25M, clk_5, rst
); |
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
wire [10:0] pixel_pos_a, pixel_pos_b;
reg [10:0] rst_pos;
reg wea, web;
reg [1:0] w_pd_counter;
reg dina;
assign pixel_pos_a = rst ? rst_pos
: (wea ? head_y*WIDTH+head_x : check_y*WIDTH+check_x);
assign pixel_pos_b = web ? tail_y*WIDTH+tail_x : pixel_y*WIDTH+pixel_x;
pixel_ram pr0 (
.clka(clk_25M),
.wea(wea),
.addra(pixel_pos_a),
.dina(dina),
.douta(douta),
.clkb(clk_25M),
.web(web),
.addrb(pixel_pos_b),
.dinb(1'b0),
.doutb(doutb)
);
always @ (posedge clk_25M)
if (rst)
begin
web <= 1'b0;
if (rst_pos == 11'd1200)
wea <= 1'b0;
else
wea <= 1'b1;
if (rst_pos == 11'd607 || rst_pos == 11'd608 || rst_pos == 11'd609
|| rst_pos == 11'd1200)
dina <= 1'b1;
else
dina <= 1'b0;
end
else
begin
dina <= 1'b1;
if (~^w_pd_counter)
begin
wea <= 1'b0;
web <= 1'b0;
end
else
begin
wea <= 1'b1;
web <= 1'b1;
end
end
always @ (posedge clk_25M)
if (clk_5 && w_pd_counter != 2'b11)
w_pd_counter <= w_pd_counter + 2'b01;
else if (~clk_5)
w_pd_counter <= 2'b00;
always @ (posedge clk_25M)
if (!rst)
rst_pos <= 11'hFFF;
else if (rst_pos != 11'd1200)
rst_pos <= rst_pos + 11'd1;
endmodule | 0 |
142,579 | data/full_repos/permissive/99334690/ram_ctrl.v | 99,334,690 | ram_ctrl.v | v | 25 | 52 | [] | [] | [] | [(15, 24)] | null | data/verilator_xmls/54f6c9c3-7553-4a96-93e4-5c440295f978.xml | null | 314,819 | module | module ram_ctrl(
output [26:1] MemAdr,
inout [15:0] MemDB,
output MemOE, MemWR,
output RamAdv, RamCS, RamClk_25M,
RamCRE, RamLB, RamUB, RamWait
);
endmodule | module ram_ctrl(
output [26:1] MemAdr,
inout [15:0] MemDB,
output MemOE, MemWR,
output RamAdv, RamCS, RamClk_25M,
RamCRE, RamLB, RamUB, RamWait
); |
endmodule | 0 |
142,580 | data/full_repos/permissive/99334690/score_disp.v | 99,334,690 | score_disp.v | v | 55 | 46 | [] | [] | [] | [(13, 54)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:23: Operator MODDIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'ha\' generates 10 bits.\n : ... In instance score_disp\n assign num[0] = score % 10\'d10;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:23: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 11 bits.\n : ... In instance score_disp\n assign num[0] = score % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:24: Operator DIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'ha\' generates 10 bits.\n : ... In instance score_disp\n assign num[1] = (score / 10\'d10) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:24: Operator MODDIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'ha\' generates 10 bits.\n : ... In instance score_disp\n assign num[1] = (score / 10\'d10) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:24: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 11 bits.\n : ... In instance score_disp\n assign num[1] = (score / 10\'d10) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:25: Operator DIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'h64\' generates 10 bits.\n : ... In instance score_disp\n assign num[2] = (score / 10\'d100) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:25: Operator MODDIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'ha\' generates 10 bits.\n : ... In instance score_disp\n assign num[2] = (score / 10\'d100) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:25: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 11 bits.\n : ... In instance score_disp\n assign num[2] = (score / 10\'d100) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:26: Operator DIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'h3e8\' generates 10 bits.\n : ... In instance score_disp\n assign num[3] = (score / 10\'d1000) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:26: Operator MODDIV expects 11 bits on the RHS, but RHS\'s CONST \'10\'ha\' generates 10 bits.\n : ... In instance score_disp\n assign num[3] = (score / 10\'d1000) % 10\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/score_disp.v:26: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 11 bits.\n : ... In instance score_disp\n assign num[3] = (score / 10\'d1000) % 10\'d10;\n ^\n%Error: data/full_repos/permissive/99334690/score_disp.v:28: Cannot find file containing module: \'seven_seg_decoder\'\n seven_seg_decoder ssd0 (seg, bcd);\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/seven_seg_decoder\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/seven_seg_decoder.v\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/seven_seg_decoder.sv\n seven_seg_decoder\n seven_seg_decoder.v\n seven_seg_decoder.sv\n obj_dir/seven_seg_decoder\n obj_dir/seven_seg_decoder.v\n obj_dir/seven_seg_decoder.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n' | 314,820 | module | module score_disp(
output [7:0] seg,
output reg [3:0] an,
input [10:0] score,
input clk_400
);
wire [3:0] num[3:0];
reg [3:0] bcd;
assign num[0] = score % 10'd10;
assign num[1] = (score / 10'd10) % 10'd10;
assign num[2] = (score / 10'd100) % 10'd10;
assign num[3] = (score / 10'd1000) % 10'd10;
seven_seg_decoder ssd0 (seg, bcd);
always @ (posedge clk_400)
case (an)
4'b1110:
begin
an <= 4'b1101;
bcd <= num[1];
end
4'b1101:
begin
an <= 4'b1011;
bcd <= num[2];
end
4'b1011:
begin
an <= 4'b0111;
bcd <= num[3];
end
default:
begin
an <= 4'b1110;
bcd <= num[0];
end
endcase
endmodule | module score_disp(
output [7:0] seg,
output reg [3:0] an,
input [10:0] score,
input clk_400
); |
wire [3:0] num[3:0];
reg [3:0] bcd;
assign num[0] = score % 10'd10;
assign num[1] = (score / 10'd10) % 10'd10;
assign num[2] = (score / 10'd100) % 10'd10;
assign num[3] = (score / 10'd1000) % 10'd10;
seven_seg_decoder ssd0 (seg, bcd);
always @ (posedge clk_400)
case (an)
4'b1110:
begin
an <= 4'b1101;
bcd <= num[1];
end
4'b1101:
begin
an <= 4'b1011;
bcd <= num[2];
end
4'b1011:
begin
an <= 4'b0111;
bcd <= num[3];
end
default:
begin
an <= 4'b1110;
bcd <= num[0];
end
endcase
endmodule | 0 |
142,581 | data/full_repos/permissive/99334690/seven_seg_decoder.v | 99,334,690 | seven_seg_decoder.v | v | 38 | 39 | [] | [] | [] | [(13, 37)] | null | data/verilator_xmls/1125a6ec-631f-44c8-a0bd-2aef2bdb8aa8.xml | null | 314,821 | module | module seven_seg_decoder(
output reg [7:0] seg,
input [3:0] bcd
);
always @ (*)
case (bcd)
4'b0000: seg = 8'b1100_0000;
4'b0001: seg = 8'b1111_1001;
4'b0010: seg = 8'b1010_0100;
4'b0011: seg = 8'b1011_0000;
4'b0100: seg = 8'b1001_1001;
4'b0101: seg = 8'b1001_0010;
4'b0110: seg = 8'b1000_0010;
4'b0111: seg = 8'b1111_1000;
4'b1000: seg = 8'b1000_0000;
4'b1001: seg = 8'b1001_0000;
4'b1010: seg = 8'b1000_1000;
4'b1011: seg = 8'b1000_0011;
4'b1100: seg = 8'b1100_0110;
4'b1101: seg = 8'b1010_0001;
4'b1110: seg = 8'b1000_0110;
4'b1111: seg = 8'b1000_1110;
endcase
endmodule | module seven_seg_decoder(
output reg [7:0] seg,
input [3:0] bcd
); |
always @ (*)
case (bcd)
4'b0000: seg = 8'b1100_0000;
4'b0001: seg = 8'b1111_1001;
4'b0010: seg = 8'b1010_0100;
4'b0011: seg = 8'b1011_0000;
4'b0100: seg = 8'b1001_1001;
4'b0101: seg = 8'b1001_0010;
4'b0110: seg = 8'b1000_0010;
4'b0111: seg = 8'b1111_1000;
4'b1000: seg = 8'b1000_0000;
4'b1001: seg = 8'b1001_0000;
4'b1010: seg = 8'b1000_1000;
4'b1011: seg = 8'b1000_0011;
4'b1100: seg = 8'b1100_0110;
4'b1101: seg = 8'b1010_0001;
4'b1110: seg = 8'b1000_0110;
4'b1111: seg = 8'b1000_1110;
endcase
endmodule | 0 |
142,582 | data/full_repos/permissive/99334690/snake.v | 99,334,690 | snake.v | v | 51 | 76 | [] | [] | [] | [(13, 50)] | null | null | 1: b"%Error: data/full_repos/permissive/99334690/snake.v:35: Cannot find file containing module: 'snake_state'\n snake_state ss0 (head_x, head_y, tail_x, tail_y, apple_x, apple_y, score,\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/snake_state\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/snake_state.v\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/snake_state.sv\n snake_state\n snake_state.v\n snake_state.sv\n obj_dir/snake_state\n obj_dir/snake_state.v\n obj_dir/snake_state.sv\n%Error: data/full_repos/permissive/99334690/snake.v:38: Cannot find file containing module: 'freq_devider'\n freq_devider fd0 (clk_25M, clk_400, clk_5, clk_100M);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/99334690/snake.v:39: Cannot find file containing module: 'pixel_ram_ctrl'\n pixel_ram_ctrl prc0 (head_pos_data, pixel_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99334690/snake.v:42: Cannot find file containing module: 'input_ctrl'\n input_ctrl ic0 (key_stroke,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99334690/snake.v:44: Cannot find file containing module: 'vga_ctrl'\n vga_ctrl vc0 (vgaRed, vgaGreen, vgaBlue, Hsync, Vsync,\n ^~~~~~~~\n%Error: data/full_repos/permissive/99334690/snake.v:46: Cannot find file containing module: 'apple_gen'\n apple_gen ag0 (avaliable_apple_x, avaliable_apple_y,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99334690/snake.v:48: Cannot find file containing module: 'score_disp'\n score_disp sd0 (seg, an, score, clk_400);\n ^~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 314,822 | module | module snake(
output [2:0] vgaRed, vgaGreen,
output [2:1] vgaBlue,
output Hsync, Vsync,
output [7:0] seg,
output [3:0] an,
input key_up, key_down, key_left, key_right, pause,
input clk_100M, rst
);
parameter WIDTH = 40;
parameter HEIGHT = 30;
wire [5:0] head_x, head_y, tail_x, tail_y, apple_x, apple_y;
wire [5:0] pixel_x, pixel_y;
wire [5:0] next_head_x, next_head_y;
wire [5:0] avaliable_apple_x, avaliable_apple_y;
wire [10:0] score;
wire [2:0] key_stroke;
wire head_pos_data, pixel_data;
wire clk_25M, clk_5;
snake_state ss0 (head_x, head_y, tail_x, tail_y, apple_x, apple_y, score,
key_stroke, avaliable_apple_x, avaliable_apple_y,
next_head_x, next_head_y, head_pos_data, clk_25M, clk_5, rst);
freq_devider fd0 (clk_25M, clk_400, clk_5, clk_100M);
pixel_ram_ctrl prc0 (head_pos_data, pixel_data,
head_x, head_y, tail_x, tail_y, next_head_x, next_head_y,
pixel_x, pixel_y, clk_25M, clk_5, rst);
input_ctrl ic0 (key_stroke,
key_up, key_down, key_left, key_right, pause, clk_25M, rst);
vga_ctrl vc0 (vgaRed, vgaGreen, vgaBlue, Hsync, Vsync,
pixel_x, pixel_y, head_x, head_y, apple_x, apple_y, pixel_data, clk_25M);
apple_gen ag0 (avaliable_apple_x, avaliable_apple_y,
pixel_x, pixel_y, apple_x, apple_y, pixel_data, clk_25M, rst);
score_disp sd0 (seg, an, score, clk_400);
endmodule | module snake(
output [2:0] vgaRed, vgaGreen,
output [2:1] vgaBlue,
output Hsync, Vsync,
output [7:0] seg,
output [3:0] an,
input key_up, key_down, key_left, key_right, pause,
input clk_100M, rst
); |
parameter WIDTH = 40;
parameter HEIGHT = 30;
wire [5:0] head_x, head_y, tail_x, tail_y, apple_x, apple_y;
wire [5:0] pixel_x, pixel_y;
wire [5:0] next_head_x, next_head_y;
wire [5:0] avaliable_apple_x, avaliable_apple_y;
wire [10:0] score;
wire [2:0] key_stroke;
wire head_pos_data, pixel_data;
wire clk_25M, clk_5;
snake_state ss0 (head_x, head_y, tail_x, tail_y, apple_x, apple_y, score,
key_stroke, avaliable_apple_x, avaliable_apple_y,
next_head_x, next_head_y, head_pos_data, clk_25M, clk_5, rst);
freq_devider fd0 (clk_25M, clk_400, clk_5, clk_100M);
pixel_ram_ctrl prc0 (head_pos_data, pixel_data,
head_x, head_y, tail_x, tail_y, next_head_x, next_head_y,
pixel_x, pixel_y, clk_25M, clk_5, rst);
input_ctrl ic0 (key_stroke,
key_up, key_down, key_left, key_right, pause, clk_25M, rst);
vga_ctrl vc0 (vgaRed, vgaGreen, vgaBlue, Hsync, Vsync,
pixel_x, pixel_y, head_x, head_y, apple_x, apple_y, pixel_data, clk_25M);
apple_gen ag0 (avaliable_apple_x, avaliable_apple_y,
pixel_x, pixel_y, apple_x, apple_y, pixel_data, clk_25M, rst);
score_disp sd0 (seg, an, score, clk_400);
endmodule | 0 |
142,583 | data/full_repos/permissive/99334690/snake_state.v | 99,334,690 | snake_state.v | v | 503 | 76 | [] | [] | [] | null | line:121: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99334690/snake_state.v:56: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'head_x\' generates 6 bits.\n : ... In instance snake_state\n assign pixel_pos_a = rst ? rst_pos : head_y*WIDTH+head_x;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99334690/snake_state.v:57: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'tail_x\' generates 6 bits.\n : ... In instance snake_state\n assign tail_pos = tail_y*WIDTH+tail_x;\n ^\n%Error: data/full_repos/permissive/99334690/snake_state.v:59: Cannot find file containing module: \'turn_info\'\n turn_info ti0 (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/turn_info\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/turn_info.v\n data/full_repos/permissive/99334690,data/full_repos/permissive/99334690/turn_info.sv\n turn_info\n turn_info.v\n turn_info.sv\n obj_dir/turn_info\n obj_dir/turn_info.v\n obj_dir/turn_info.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 314,823 | module | module snake_state(
output reg [5:0] head_x, head_y, tail_x, tail_y,
output reg [5:0] apple_x, apple_y,
output reg [10:0] score,
input [2:0] key_stroke,
input [5:0] avaliable_apple_x, avaliable_apple_y,
output reg [5:0] check_x, check_y,
input body_exist,
input clk_25M, clk_5, rst
);
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
parameter UP = 3'b000, DOWN = 3'b001, LEFT = 3'b010, RIGHT = 3'b011;
parameter PAUSE = 3'b100, STOPPED = 3'b111;
reg [2:0] head_dir, tail_dir;
reg [5:0] next_head_x, next_head_y;
reg [5:0] next_apple_x, next_apple_y;
reg [2:0] next_head_dir;
wire [2:0] next_tail_dir;
reg [10:0] next_score;
wire [10:0] pixel_pos_a, tail_pos;
reg [10:0] rst_pos;
assign pixel_pos_a = rst ? rst_pos : head_y*WIDTH+head_x;
assign tail_pos = tail_y*WIDTH+tail_x;
turn_info ti0 (
.clka(clk_5),
.wea(1'b1),
.addra(pixel_pos_a),
.dina(next_head_dir),
.clkb(clk_25M),
.web(1'b0),
.addrb(tail_pos),
.dinb(3'b000),
.doutb(next_tail_dir)
);
always @ (posedge clk_5)
case (rst_pos)
11'd607, 11'd608: rst_pos <= rst_pos + 11'd1;
default: rst_pos <= 11'd607;
endcase
always @ (posedge clk_5)
if (rst)
begin
head_x <= 6'd10;
head_y <= 6'd15;
head_dir <= RIGHT;
apple_x <= avaliable_apple_x;
apple_y <= avaliable_apple_y;
score <= 11'd0;
end
else
begin
head_x <= next_head_x;
head_y <= next_head_y;
head_dir <= next_head_dir;
apple_x <= next_apple_x;
apple_y <= next_apple_y;
score <= next_score;
end
always @ (*)
case (head_dir)
LEFT:
case (key_stroke)
LEFT, RIGHT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
UP:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
RIGHT:
case (key_stroke)
LEFT, RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
UP:
case (key_stroke)
LEFT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP, DOWN:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
DOWN:
case (key_stroke)
LEFT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP, DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
PAUSE:
case (key_stroke)
LEFT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
next_head_dir = STOPPED;
end
endcase
task update_score_and_apple;
begin
if (next_head_x == apple_x && head_y == apple_y)
begin
next_score = score + 11'd1;
next_apple_x = avaliable_apple_x;
next_apple_y = avaliable_apple_y;
end
else
begin
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
end
endtask
always @ (posedge clk_5)
if (rst)
begin
tail_x <= 6'd7;
tail_y <= 6'd15;
end
else if (next_head_dir[2]
|| (next_head_x == apple_x && next_head_y == apple_y))
begin
tail_x <= tail_x;
tail_y <= tail_y;
end
else
begin
case (next_tail_dir)
LEFT:
tail_x <= tail_x - 6'd1;
RIGHT:
tail_x <= tail_x + 6'd1;
UP:
tail_y <= tail_y - 6'd1;
DOWN:
tail_y <= tail_y + 6'd1;
endcase
end
endmodule | module snake_state(
output reg [5:0] head_x, head_y, tail_x, tail_y,
output reg [5:0] apple_x, apple_y,
output reg [10:0] score,
input [2:0] key_stroke,
input [5:0] avaliable_apple_x, avaliable_apple_y,
output reg [5:0] check_x, check_y,
input body_exist,
input clk_25M, clk_5, rst
); |
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
parameter UP = 3'b000, DOWN = 3'b001, LEFT = 3'b010, RIGHT = 3'b011;
parameter PAUSE = 3'b100, STOPPED = 3'b111;
reg [2:0] head_dir, tail_dir;
reg [5:0] next_head_x, next_head_y;
reg [5:0] next_apple_x, next_apple_y;
reg [2:0] next_head_dir;
wire [2:0] next_tail_dir;
reg [10:0] next_score;
wire [10:0] pixel_pos_a, tail_pos;
reg [10:0] rst_pos;
assign pixel_pos_a = rst ? rst_pos : head_y*WIDTH+head_x;
assign tail_pos = tail_y*WIDTH+tail_x;
turn_info ti0 (
.clka(clk_5),
.wea(1'b1),
.addra(pixel_pos_a),
.dina(next_head_dir),
.clkb(clk_25M),
.web(1'b0),
.addrb(tail_pos),
.dinb(3'b000),
.doutb(next_tail_dir)
);
always @ (posedge clk_5)
case (rst_pos)
11'd607, 11'd608: rst_pos <= rst_pos + 11'd1;
default: rst_pos <= 11'd607;
endcase
always @ (posedge clk_5)
if (rst)
begin
head_x <= 6'd10;
head_y <= 6'd15;
head_dir <= RIGHT;
apple_x <= avaliable_apple_x;
apple_y <= avaliable_apple_y;
score <= 11'd0;
end
else
begin
head_x <= next_head_x;
head_y <= next_head_y;
head_dir <= next_head_dir;
apple_x <= next_apple_x;
apple_y <= next_apple_y;
score <= next_score;
end
always @ (*)
case (head_dir)
LEFT:
case (key_stroke)
LEFT, RIGHT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
UP:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
RIGHT:
case (key_stroke)
LEFT, RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
UP:
case (key_stroke)
LEFT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP, DOWN:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
DOWN:
case (key_stroke)
LEFT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP, DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
PAUSE:
case (key_stroke)
LEFT:
begin
check_x = head_x - 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == 6'b0 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x - 6'd1;
next_head_dir = LEFT;
end
update_score_and_apple;
end
RIGHT:
begin
check_x = head_x + 6'd1;
check_y = head_y;
next_head_y = head_y;
if (head_x == WIDTH - 6'b1 || body_exist)
begin
next_head_x = head_x;
next_head_dir = STOPPED;
end
else
begin
next_head_x = head_x + 6'd1;
next_head_dir = RIGHT;
end
update_score_and_apple;
end
UP:
begin
check_x = head_x;
check_y = head_y - 6'd1;
next_head_x = head_x;
if (head_y == 6'b0 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y - 6'd1;
next_head_dir = UP;
end
update_score_and_apple;
end
DOWN:
begin
check_x = head_x;
check_y = head_y + 6'd1;
next_head_x = head_x;
if (head_y == HEIGHT - 6'b1 || body_exist)
begin
next_head_y = head_y;
next_head_dir = STOPPED;
end
else
begin
next_head_y = head_y + 6'd1;
next_head_dir = DOWN;
end
update_score_and_apple;
end
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_head_dir = PAUSE;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
endcase
default:
begin
check_x = head_x;
check_y = head_y;
next_head_x = head_x;
next_head_y = head_y;
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
next_head_dir = STOPPED;
end
endcase
task update_score_and_apple;
begin
if (next_head_x == apple_x && head_y == apple_y)
begin
next_score = score + 11'd1;
next_apple_x = avaliable_apple_x;
next_apple_y = avaliable_apple_y;
end
else
begin
next_score = score;
next_apple_x = apple_x;
next_apple_y = apple_y;
end
end
endtask
always @ (posedge clk_5)
if (rst)
begin
tail_x <= 6'd7;
tail_y <= 6'd15;
end
else if (next_head_dir[2]
|| (next_head_x == apple_x && next_head_y == apple_y))
begin
tail_x <= tail_x;
tail_y <= tail_y;
end
else
begin
case (next_tail_dir)
LEFT:
tail_x <= tail_x - 6'd1;
RIGHT:
tail_x <= tail_x + 6'd1;
UP:
tail_y <= tail_y - 6'd1;
DOWN:
tail_y <= tail_y + 6'd1;
endcase
end
endmodule | 0 |
142,584 | data/full_repos/permissive/99334690/vga_ctrl.v | 99,334,690 | vga_ctrl.v | v | 93 | 84 | [] | [] | [] | [(13, 92)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99334690/vga_ctrl.v:42: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n : ... In instance vga_ctrl\n assign pixel_x = (H_counter - THpw - THbp + 10\'d1) >> 4;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99334690/vga_ctrl.v:43: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n : ... In instance vga_ctrl\n assign pixel_y = (V_counter - TVpw - TVbp) >> 4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/99334690/vga_ctrl.v:45: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n : ... In instance vga_ctrl\n assign real_pixel_x = (H_counter - THpw - THbp) >> 4;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 314,824 | module | module vga_ctrl(
output reg [2:0] vgaRed, vgaGreen,
output reg [2:1] vgaBlue,
output reg Hsync, Vsync,
output [5:0] pixel_x, pixel_y,
input [5:0] head_x, head_y, apple_x, apple_y,
input pixel_data,
input clk_25M
);
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
parameter TVpw = 10'd2, TVbp = 10'd29, TVdisp = 10'd480, TVs = 10'd521;
parameter THpw = 10'd96, THbp = 10'd48, THdisp = 10'd640, THs = 10'd800;
reg [9:0] V_counter;
reg [9:0] H_counter;
reg [2:0] next_vgaRed, next_vgaGreen;
reg [1:0] next_vgaBlue;
wire [5:0] real_pixel_x;
assign pixel_x = (H_counter - THpw - THbp + 10'd1) >> 4;
assign pixel_y = (V_counter - TVpw - TVbp) >> 4;
assign real_pixel_x = (H_counter - THpw - THbp) >> 4;
always @ (posedge clk_25M)
if (H_counter == THs)
begin
H_counter <= 10'b0;
Hsync <= 1'b0;
end
else
begin
H_counter <= H_counter + 10'd1;
if (H_counter == THpw - 10'd2)
Hsync <= 1'b1;
end
always @ (posedge clk_25M)
if (H_counter == THs)
if (V_counter == TVs)
begin
V_counter <= 10'd0;
Vsync <= 1'b0;
end
else
begin
V_counter <= V_counter + 10'd1;
if (V_counter == TVpw - 10'd2)
Vsync <= 1'b1;
end
always @ (posedge clk_25M)
{vgaRed, vgaGreen, vgaBlue} <= {next_vgaRed, next_vgaGreen, next_vgaBlue};
always @ (*)
if (V_counter > TVpw + TVbp - 10'd1 && V_counter <= TVpw + TVbp + TVdisp - 10'd1
&& H_counter >= THpw + THbp - 10'd1 && H_counter < THpw + THbp + THdisp - 10'd1)
if (pixel_data)
if (real_pixel_x == head_x && pixel_y == head_y)
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b00011100;
else
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b11111100;
else if (real_pixel_x == apple_x && pixel_y == apple_y)
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b11100000;
else
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b01101101;
else
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b0;
endmodule | module vga_ctrl(
output reg [2:0] vgaRed, vgaGreen,
output reg [2:1] vgaBlue,
output reg Hsync, Vsync,
output [5:0] pixel_x, pixel_y,
input [5:0] head_x, head_y, apple_x, apple_y,
input pixel_data,
input clk_25M
); |
parameter WIDTH = 6'd40;
parameter HEIGHT = 6'd30;
parameter TVpw = 10'd2, TVbp = 10'd29, TVdisp = 10'd480, TVs = 10'd521;
parameter THpw = 10'd96, THbp = 10'd48, THdisp = 10'd640, THs = 10'd800;
reg [9:0] V_counter;
reg [9:0] H_counter;
reg [2:0] next_vgaRed, next_vgaGreen;
reg [1:0] next_vgaBlue;
wire [5:0] real_pixel_x;
assign pixel_x = (H_counter - THpw - THbp + 10'd1) >> 4;
assign pixel_y = (V_counter - TVpw - TVbp) >> 4;
assign real_pixel_x = (H_counter - THpw - THbp) >> 4;
always @ (posedge clk_25M)
if (H_counter == THs)
begin
H_counter <= 10'b0;
Hsync <= 1'b0;
end
else
begin
H_counter <= H_counter + 10'd1;
if (H_counter == THpw - 10'd2)
Hsync <= 1'b1;
end
always @ (posedge clk_25M)
if (H_counter == THs)
if (V_counter == TVs)
begin
V_counter <= 10'd0;
Vsync <= 1'b0;
end
else
begin
V_counter <= V_counter + 10'd1;
if (V_counter == TVpw - 10'd2)
Vsync <= 1'b1;
end
always @ (posedge clk_25M)
{vgaRed, vgaGreen, vgaBlue} <= {next_vgaRed, next_vgaGreen, next_vgaBlue};
always @ (*)
if (V_counter > TVpw + TVbp - 10'd1 && V_counter <= TVpw + TVbp + TVdisp - 10'd1
&& H_counter >= THpw + THbp - 10'd1 && H_counter < THpw + THbp + THdisp - 10'd1)
if (pixel_data)
if (real_pixel_x == head_x && pixel_y == head_y)
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b00011100;
else
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b11111100;
else if (real_pixel_x == apple_x && pixel_y == apple_y)
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b11100000;
else
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b01101101;
else
{next_vgaRed, next_vgaGreen, next_vgaBlue} = 8'b0;
endmodule | 0 |
142,585 | data/full_repos/permissive/99344209/src/add.v | 99,344,209 | add.v | v | 21 | 39 | [] | [] | [] | [(13, 20)] | null | data/verilator_xmls/872b3b1a-2f86-4a28-bc75-90256fa6b70c.xml | null | 314,825 | module | module add(
output [31:0] result,
input signed [31:0] op1, op2
);
assign result = op1 + op2;
endmodule | module add(
output [31:0] result,
input signed [31:0] op1, op2
); |
assign result = op1 + op2;
endmodule | 0 |
142,586 | data/full_repos/permissive/99344209/src/ALU.v | 99,344,209 | ALU.v | v | 72 | 64 | [] | [] | [] | [(13, 71)] | null | data/verilator_xmls/c19ad495-2b3c-418d-8028-83318475191f.xml | null | 314,826 | module | module ALU(
output reg [31:0] alu_out,
output alu_overflow,
input [31:0] alu_a, alu_b,
input [4:0] shamt,
input [3:0] alu_op
);
parameter A_AND = 4'b0000;
parameter A_OR = 4'b0001;
parameter A_ADD = 4'b0010;
parameter A_SUB = 4'b0110;
parameter A_SLT = 4'b0111;
parameter A_NOR = 4'b1100;
parameter A_ADDU = 4'b0011;
parameter A_SUBU = 4'b0100;
parameter A_SLTU = 4'b0101;
parameter A_SLL = 4'b1000;
parameter A_SLLV = 4'b1001;
parameter A_SRA = 4'b1010;
parameter A_SRAV = 4'b1011;
parameter A_SRL = 4'b1101;
parameter A_SRLV = 4'b1110;
parameter A_XOR = 4'b1111;
reg carry_out;
wire signed [31:0] signed_a, signed_b;
assign alu_overflow = (alu_op == A_ADD || alu_op == A_SUB)
&& (carry_out ^ alu_out[31]);
assign signed_a = alu_a;
assign signed_b = alu_b;
always @ (*)
case (alu_op)
A_AND: {carry_out, alu_out} = {1'bx, alu_a & alu_b};
A_OR : {carry_out, alu_out} = {1'bx, alu_a | alu_b};
A_ADD: {carry_out, alu_out} = signed_a + signed_b;
A_SUB: {carry_out, alu_out} = signed_a - signed_b;
A_SLT: {carry_out, alu_out} = (signed_a < signed_b)
? {1'bx, 32'b1} : {1'bx, 32'b0};
A_NOR: {carry_out, alu_out} = {1'bx, ~(alu_a | alu_b)};
A_ADDU: {carry_out, alu_out} = {1'bx, alu_a + alu_b};
A_SUBU: {carry_out, alu_out} = {1'bx, alu_a - alu_b};
A_SLTU: {carry_out, alu_out} = (alu_a < alu_b)
? {1'bx, 32'b1} : {1'bx, 32'b0};
A_SLL: {carry_out, alu_out} = {1'bx, alu_b << shamt};
A_SLLV: {carry_out, alu_out} = {1'bx, alu_b << alu_a[4:0]};
A_SRA: {carry_out, alu_out} = {1'bx, alu_b >>> shamt};
A_SRAV: {carry_out, alu_out} = {1'bx, alu_b >>> alu_a[4:0]};
A_SRL: {carry_out, alu_out} = {1'bx, alu_b >> shamt};
A_SRLV: {carry_out, alu_out} = {1'bx, alu_b >> alu_a[4:0]};
A_XOR: {carry_out, alu_out} = {1'bx, alu_a ^ alu_b};
default: {carry_out, alu_out} = 33'hx;
endcase
endmodule | module ALU(
output reg [31:0] alu_out,
output alu_overflow,
input [31:0] alu_a, alu_b,
input [4:0] shamt,
input [3:0] alu_op
); |
parameter A_AND = 4'b0000;
parameter A_OR = 4'b0001;
parameter A_ADD = 4'b0010;
parameter A_SUB = 4'b0110;
parameter A_SLT = 4'b0111;
parameter A_NOR = 4'b1100;
parameter A_ADDU = 4'b0011;
parameter A_SUBU = 4'b0100;
parameter A_SLTU = 4'b0101;
parameter A_SLL = 4'b1000;
parameter A_SLLV = 4'b1001;
parameter A_SRA = 4'b1010;
parameter A_SRAV = 4'b1011;
parameter A_SRL = 4'b1101;
parameter A_SRLV = 4'b1110;
parameter A_XOR = 4'b1111;
reg carry_out;
wire signed [31:0] signed_a, signed_b;
assign alu_overflow = (alu_op == A_ADD || alu_op == A_SUB)
&& (carry_out ^ alu_out[31]);
assign signed_a = alu_a;
assign signed_b = alu_b;
always @ (*)
case (alu_op)
A_AND: {carry_out, alu_out} = {1'bx, alu_a & alu_b};
A_OR : {carry_out, alu_out} = {1'bx, alu_a | alu_b};
A_ADD: {carry_out, alu_out} = signed_a + signed_b;
A_SUB: {carry_out, alu_out} = signed_a - signed_b;
A_SLT: {carry_out, alu_out} = (signed_a < signed_b)
? {1'bx, 32'b1} : {1'bx, 32'b0};
A_NOR: {carry_out, alu_out} = {1'bx, ~(alu_a | alu_b)};
A_ADDU: {carry_out, alu_out} = {1'bx, alu_a + alu_b};
A_SUBU: {carry_out, alu_out} = {1'bx, alu_a - alu_b};
A_SLTU: {carry_out, alu_out} = (alu_a < alu_b)
? {1'bx, 32'b1} : {1'bx, 32'b0};
A_SLL: {carry_out, alu_out} = {1'bx, alu_b << shamt};
A_SLLV: {carry_out, alu_out} = {1'bx, alu_b << alu_a[4:0]};
A_SRA: {carry_out, alu_out} = {1'bx, alu_b >>> shamt};
A_SRAV: {carry_out, alu_out} = {1'bx, alu_b >>> alu_a[4:0]};
A_SRL: {carry_out, alu_out} = {1'bx, alu_b >> shamt};
A_SRLV: {carry_out, alu_out} = {1'bx, alu_b >> alu_a[4:0]};
A_XOR: {carry_out, alu_out} = {1'bx, alu_a ^ alu_b};
default: {carry_out, alu_out} = 33'hx;
endcase
endmodule | 0 |
142,587 | data/full_repos/permissive/99344209/src/alu_control.v | 99,344,209 | alu_control.v | v | 73 | 70 | [] | [] | [] | [(13, 72)] | null | data/verilator_xmls/ad4b1c81-ab1b-4815-ba6e-e5a4d55b59b8.xml | null | 314,827 | module | module alu_control(
output reg [3:0] alu_control_input,
input [3:0] alu_op,
input [5:0] funct
);
parameter lw = 4'b0000, sw = 4'b0000, addi = 4'b0000, addiu = 4'b0001
, andi = 4'b0010, ori = 4'b0011, xori = 4'b0100, slti = 4'b0101
, sltiu = 4'b0110, r_type = 4'b1111;
parameter A_AND = 4'b0000;
parameter A_OR = 4'b0001;
parameter A_ADD = 4'b0010;
parameter A_SUB = 4'b0110;
parameter A_SLT = 4'b0111;
parameter A_NOR = 4'b1100;
parameter A_ADDU = 4'b0011;
parameter A_SUBU = 4'b0100;
parameter A_SLTU = 4'b0101;
parameter A_SLL = 4'b1000;
parameter A_SLLV = 4'b1001;
parameter A_SRA = 4'b1010;
parameter A_SRAV = 4'b1011;
parameter A_SRL = 4'b1101;
parameter A_SRLV = 4'b1110;
parameter A_XOR = 4'b1111;
always @ (*)
case (alu_op)
lw: alu_control_input = A_ADD;
addiu: alu_control_input = A_ADDU;
andi: alu_control_input = A_AND;
ori: alu_control_input = A_OR;
xori: alu_control_input = A_XOR;
slti: alu_control_input = A_SLT;
sltiu: alu_control_input = A_SLTU;
r_type:
case (funct)
6'b100000: alu_control_input = A_ADD;
6'b100001: alu_control_input = A_ADDU;
6'b100010: alu_control_input = A_SUB;
6'b100011: alu_control_input = A_SUBU;
6'b100100: alu_control_input = A_AND;
6'b100101: alu_control_input = A_OR;
6'b100111: alu_control_input = A_NOR;
6'b101010: alu_control_input = A_SLT;
6'b101011: alu_control_input = A_SLTU;
6'b000000: alu_control_input = A_SLL;
6'b000100: alu_control_input = A_SLLV;
6'b000011: alu_control_input = A_SRA;
6'b000111: alu_control_input = A_SRAV;
6'b000010: alu_control_input = A_SRL;
6'b000110: alu_control_input = A_SRLV;
6'b100110: alu_control_input = A_XOR;
default: alu_control_input = 4'bx;
endcase
default: alu_control_input = 4'bx;
endcase
endmodule | module alu_control(
output reg [3:0] alu_control_input,
input [3:0] alu_op,
input [5:0] funct
); |
parameter lw = 4'b0000, sw = 4'b0000, addi = 4'b0000, addiu = 4'b0001
, andi = 4'b0010, ori = 4'b0011, xori = 4'b0100, slti = 4'b0101
, sltiu = 4'b0110, r_type = 4'b1111;
parameter A_AND = 4'b0000;
parameter A_OR = 4'b0001;
parameter A_ADD = 4'b0010;
parameter A_SUB = 4'b0110;
parameter A_SLT = 4'b0111;
parameter A_NOR = 4'b1100;
parameter A_ADDU = 4'b0011;
parameter A_SUBU = 4'b0100;
parameter A_SLTU = 4'b0101;
parameter A_SLL = 4'b1000;
parameter A_SLLV = 4'b1001;
parameter A_SRA = 4'b1010;
parameter A_SRAV = 4'b1011;
parameter A_SRL = 4'b1101;
parameter A_SRLV = 4'b1110;
parameter A_XOR = 4'b1111;
always @ (*)
case (alu_op)
lw: alu_control_input = A_ADD;
addiu: alu_control_input = A_ADDU;
andi: alu_control_input = A_AND;
ori: alu_control_input = A_OR;
xori: alu_control_input = A_XOR;
slti: alu_control_input = A_SLT;
sltiu: alu_control_input = A_SLTU;
r_type:
case (funct)
6'b100000: alu_control_input = A_ADD;
6'b100001: alu_control_input = A_ADDU;
6'b100010: alu_control_input = A_SUB;
6'b100011: alu_control_input = A_SUBU;
6'b100100: alu_control_input = A_AND;
6'b100101: alu_control_input = A_OR;
6'b100111: alu_control_input = A_NOR;
6'b101010: alu_control_input = A_SLT;
6'b101011: alu_control_input = A_SLTU;
6'b000000: alu_control_input = A_SLL;
6'b000100: alu_control_input = A_SLLV;
6'b000011: alu_control_input = A_SRA;
6'b000111: alu_control_input = A_SRAV;
6'b000010: alu_control_input = A_SRL;
6'b000110: alu_control_input = A_SRLV;
6'b100110: alu_control_input = A_XOR;
default: alu_control_input = 4'bx;
endcase
default: alu_control_input = 4'bx;
endcase
endmodule | 0 |
142,588 | data/full_repos/permissive/99344209/src/branch_validate.v | 99,344,209 | branch_validate.v | v | 32 | 39 | [] | [] | [] | [(13, 31)] | null | data/verilator_xmls/061639cd-dc86-479e-abcb-f27e1daef72b.xml | null | 314,828 | module | module branch_validate(
output reg branch_taken,
input [5:0] op,
input [31:0] rs, rt
);
parameter beq = 6'b000100;
parameter bne = 6'b000101;
parameter bgtz = 6'b000111;
always @ (*)
case (op)
beq: branch_taken = rs == rt;
bne: branch_taken = rs != rt;
bgtz: branch_taken = rs > 32'b0;
default: branch_taken = 1'b0;
endcase
endmodule | module branch_validate(
output reg branch_taken,
input [5:0] op,
input [31:0] rs, rt
); |
parameter beq = 6'b000100;
parameter bne = 6'b000101;
parameter bgtz = 6'b000111;
always @ (*)
case (op)
beq: branch_taken = rs == rt;
bne: branch_taken = rs != rt;
bgtz: branch_taken = rs > 32'b0;
default: branch_taken = 1'b0;
endcase
endmodule | 0 |
142,589 | data/full_repos/permissive/99344209/src/control.v | 99,344,209 | control.v | v | 134 | 70 | [] | [] | [] | [(13, 133)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/control.v:46: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 8 bits.\n : ... In instance control\n assign inta = status[0] && !status[1] && status[15:8] & cause[15:8];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 314,829 | module | module control(
output [5:0] ex_ctrl,
output [2:0] mem_ctrl,
output [2:0] wb_ctrl,
output inta, excp_ret,
input [5:0] op,
input [4:0] rs,
input [31:0] status, cause
);
parameter r_format = 6'b000000;
parameter lw = 6'b100011;
parameter sw = 6'b101011;
parameter addi = 6'b001000;
parameter addiu = 6'b001001;
parameter andi = 6'b001100;
parameter ori = 6'b001101;
parameter xori = 6'b001110;
parameter slti = 6'b001010;
parameter sltiu = 6'b001011;
parameter cp0_instr = 6'b010000;
parameter mfc0 = 5'b00000;
parameter mtc0 = 5'b00100;
parameter eret = 5'b10000;
reg reg_dst, alu_src, mem_to_reg, reg_write, mem_read, mem_write;
wire cp0_read, cp0_write;
reg [3:0] alu_op;
assign ex_ctrl = {alu_op, alu_src, reg_dst};
assign mem_ctrl = {cp0_read, mem_read, mem_write};
assign wb_ctrl = {cp0_write, reg_write, mem_to_reg};
assign inta = status[0] && !status[1] && status[15:8] & cause[15:8];
assign excp_ret = op == cp0_instr && rs == eret;
assign cp0_read = op == cp0_instr && rs == mfc0;
assign cp0_write = op == cp0_instr && rs == mtc0;
always @ (*)
case (op)
r_format:
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
alu_op = 4'b1111;
end
lw:
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b1;
reg_write = 1'b1;
mem_read = 1'b1;
mem_write = 1'b0;
alu_op = 4'b0000;
end
sw:
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'bx;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b1;
alu_op = 4'b0000;
end
addi, addiu, andi, ori, xori, slti, sltiu:
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
case (op)
addi: alu_op = 4'b0000;
addiu: alu_op = 4'b0001;
andi: alu_op = 4'b0010;
ori: alu_op = 4'b0011;
xori: alu_op = 4'b0100;
slti: alu_op = 4'b0101;
sltiu: alu_op = 4'b0110;
default: alu_op = 4'bx;
endcase
end
cp0_instr:
begin
if (rs == mfc0)
reg_dst = 1'b0;
else if (rs == mtc0)
reg_dst = 1'b1;
else
reg_dst = 1'bx;
alu_src = 1'bx;
mem_to_reg = 1'b0;
if (rs == mfc0)
reg_write = 1'b1;
else
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
alu_op = 4'bx;
end
default:
begin
reg_dst = 1'bx;
alu_src = 1'bx;
mem_to_reg = 1'bx;
reg_write = 1'b0;
mem_read = 1'bx;
mem_write = 1'b0;
alu_op = 4'bx;
end
endcase
endmodule | module control(
output [5:0] ex_ctrl,
output [2:0] mem_ctrl,
output [2:0] wb_ctrl,
output inta, excp_ret,
input [5:0] op,
input [4:0] rs,
input [31:0] status, cause
); |
parameter r_format = 6'b000000;
parameter lw = 6'b100011;
parameter sw = 6'b101011;
parameter addi = 6'b001000;
parameter addiu = 6'b001001;
parameter andi = 6'b001100;
parameter ori = 6'b001101;
parameter xori = 6'b001110;
parameter slti = 6'b001010;
parameter sltiu = 6'b001011;
parameter cp0_instr = 6'b010000;
parameter mfc0 = 5'b00000;
parameter mtc0 = 5'b00100;
parameter eret = 5'b10000;
reg reg_dst, alu_src, mem_to_reg, reg_write, mem_read, mem_write;
wire cp0_read, cp0_write;
reg [3:0] alu_op;
assign ex_ctrl = {alu_op, alu_src, reg_dst};
assign mem_ctrl = {cp0_read, mem_read, mem_write};
assign wb_ctrl = {cp0_write, reg_write, mem_to_reg};
assign inta = status[0] && !status[1] && status[15:8] & cause[15:8];
assign excp_ret = op == cp0_instr && rs == eret;
assign cp0_read = op == cp0_instr && rs == mfc0;
assign cp0_write = op == cp0_instr && rs == mtc0;
always @ (*)
case (op)
r_format:
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
alu_op = 4'b1111;
end
lw:
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b1;
reg_write = 1'b1;
mem_read = 1'b1;
mem_write = 1'b0;
alu_op = 4'b0000;
end
sw:
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'bx;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b1;
alu_op = 4'b0000;
end
addi, addiu, andi, ori, xori, slti, sltiu:
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
case (op)
addi: alu_op = 4'b0000;
addiu: alu_op = 4'b0001;
andi: alu_op = 4'b0010;
ori: alu_op = 4'b0011;
xori: alu_op = 4'b0100;
slti: alu_op = 4'b0101;
sltiu: alu_op = 4'b0110;
default: alu_op = 4'bx;
endcase
end
cp0_instr:
begin
if (rs == mfc0)
reg_dst = 1'b0;
else if (rs == mtc0)
reg_dst = 1'b1;
else
reg_dst = 1'bx;
alu_src = 1'bx;
mem_to_reg = 1'b0;
if (rs == mfc0)
reg_write = 1'b1;
else
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
alu_op = 4'bx;
end
default:
begin
reg_dst = 1'bx;
alu_src = 1'bx;
mem_to_reg = 1'bx;
reg_write = 1'b0;
mem_read = 1'bx;
mem_write = 1'b0;
alu_op = 4'bx;
end
endcase
endmodule | 0 |
142,590 | data/full_repos/permissive/99344209/src/cp0.v | 99,344,209 | cp0.v | v | 62 | 86 | [] | [] | [] | [(13, 61)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/cp0.v:47: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n : ... In instance cp0\n cp0_reg[in_addr] <= din;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/cp0.v:56: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 34 bits.\n : ... In instance cp0\n dout <= {cp0_reg[13][31:16], int_level, cp0_reg[13][9:5], 5\'d0, cp0_reg[13][1:0]};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/cp0.v:58: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n : ... In instance cp0\n dout <= cp0_reg[out_addr];\n ^\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/cp0.v:55: Operator EQ expects 5 bits on the LHS, but LHS\'s CONST \'4\'hd\' generates 4 bits.\n : ... In instance cp0\n if (intr && 4\'d13 == out_addr)\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 314,830 | module | module cp0(
output reg [31:0] dout,
output [31:0] status, cause,
input [31:0] din, epc,
input [4:0] in_addr, out_addr,
input [5:0] int_level,
input reg_w, intr, inta, excp_ret, clk, rst_n
);
reg [31:0] cp0_reg[32:0];
assign status = cp0_reg[12];
assign cause = cp0_reg[13];
always @ (posedge clk)
begin
if (!rst_n)
begin
cp0_reg[12][15:8] <= 8'hFF;
cp0_reg[12][4] <= 1'b1;
cp0_reg[12][1:0] <= 2'b01;
cp0_reg[13][15:8] <= 8'h0;
end
else if (inta)
begin
cp0_reg[12][1:0] <= 2'b10;
cp0_reg[14] <= epc;
end
else if (excp_ret)
begin
cp0_reg[12][1] <= 1'b0;
end
else if (reg_w)
begin
cp0_reg[in_addr] <= din;
end
else if (intr)
begin
cp0_reg[13][15:10] <= int_level;
cp0_reg[13][6:2] <= 5'd0;
end
if (intr && 4'd13 == out_addr)
dout <= {cp0_reg[13][31:16], int_level, cp0_reg[13][9:5], 5'd0, cp0_reg[13][1:0]};
else
dout <= cp0_reg[out_addr];
end
endmodule | module cp0(
output reg [31:0] dout,
output [31:0] status, cause,
input [31:0] din, epc,
input [4:0] in_addr, out_addr,
input [5:0] int_level,
input reg_w, intr, inta, excp_ret, clk, rst_n
); |
reg [31:0] cp0_reg[32:0];
assign status = cp0_reg[12];
assign cause = cp0_reg[13];
always @ (posedge clk)
begin
if (!rst_n)
begin
cp0_reg[12][15:8] <= 8'hFF;
cp0_reg[12][4] <= 1'b1;
cp0_reg[12][1:0] <= 2'b01;
cp0_reg[13][15:8] <= 8'h0;
end
else if (inta)
begin
cp0_reg[12][1:0] <= 2'b10;
cp0_reg[14] <= epc;
end
else if (excp_ret)
begin
cp0_reg[12][1] <= 1'b0;
end
else if (reg_w)
begin
cp0_reg[in_addr] <= din;
end
else if (intr)
begin
cp0_reg[13][15:10] <= int_level;
cp0_reg[13][6:2] <= 5'd0;
end
if (intr && 4'd13 == out_addr)
dout <= {cp0_reg[13][31:16], int_level, cp0_reg[13][9:5], 5'd0, cp0_reg[13][1:0]};
else
dout <= cp0_reg[out_addr];
end
endmodule | 0 |
142,591 | data/full_repos/permissive/99344209/src/CPU.v | 99,344,209 | CPU.v | v | 162 | 86 | [] | [] | [] | null | line:80: before: "," | null | 1: b"%Error: data/full_repos/permissive/99344209/src/CPU.v:76: Cannot find file containing module: 'PC'\n PC pc (im_addr, npc, pc_write, clk, rst_n);\n ^~\n ... Looked in:\n data/full_repos/permissive/99344209/src,data/full_repos/permissive/99344209/PC\n data/full_repos/permissive/99344209/src,data/full_repos/permissive/99344209/PC.v\n data/full_repos/permissive/99344209/src,data/full_repos/permissive/99344209/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/99344209/src/CPU.v:77: Cannot find file containing module: 'registers'\n registers rf (read_data_1, read_data_2\n ^~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:80: Cannot find file containing module: 'ALU'\n ALU alu (alu_result_ex, , alu_src_1, alu_src_mux_to_alu, shamt, alu_control_to_alu);\n ^~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:82: Cannot find file containing module: 'alu_control'\n alu_control ac (alu_control_to_alu, alu_op, funct);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:83: Cannot find file containing module: 'control'\n control cu (ex_ctrl_id, mem_ctrl_id, wb_ctrl_id, inta, excp_ret\n ^~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:85: Cannot find file containing module: 'forwarding_unit_id'\n forwarding_unit_id fui (forward_br_a, forward_br_b, wb_ctrl_mem[1]\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:87: Cannot find file containing module: 'forwarding_unit_ex'\n forwarding_unit_ex fue (forward_a, forward_b\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:92: Cannot find file containing module: 'forwarding_unit_mem'\n forwarding_unit_mem fum (forward_mem, reg_write\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:94: Cannot find file containing module: 'hazard_detection_unit'\n hazard_detection_unit hdu (pc_write, if_id_write, if_id_flush, id_ex_flush\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:99: Cannot find file containing module: 'branch_validate'\n branch_validate bv (branch_taken, instruction[31:26], branch_rs, branch_rt);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:100: Cannot find file containing module: 'jump_detect'\n jump_detect jd (jump_addr_sel, jump, instruction[31:26], instruction[5:0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:102: Cannot find file containing module: 'cp0'\n cp0 cp (cp0_out, status, cause, alu_result_wb, epc, reg_w_addr_wb, cp0_out_addr\n ^~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:105: Cannot find file containing module: 'add'\n add add_4 (pc_plus_4_if, im_addr, 32'd4);\n ^~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:106: Cannot find file containing module: 'add'\n add branch_alu (branch_target, pc_plus_4_id, {immi[29:0], 2'b0});\n ^~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:108: Cannot find file containing module: 'mux_4_1'\n mux_4_1 forward_a_mux (alu_src_1, reg_to_alu_1, alu_result_mem\n ^~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:110: Cannot find file containing module: 'mux_4_1'\n mux_4_1 forward_b_mux (alu_src_2_ex, reg_to_alu_2, alu_result_mem\n ^~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:112: Cannot find file containing module: 'mux_32'\n mux_32 forward_br_a_mux (branch_rs, read_data_1, alu_result_mem, forward_br_a);\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:113: Cannot find file containing module: 'mux_32'\n mux_32 forward_br_b_mux (branch_rt, read_data_2, alu_result_mem, forward_br_b);\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:114: Cannot find file containing module: 'mux_32'\n mux_32 alu_src_mux (alu_src_mux_to_alu\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:116: Cannot find file containing module: 'mux_32'\n mux_32 forward_mem_mux (dm_w_data, alu_src_2_mem, mem_to_reg_mux_to_reg\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:118: Cannot find file containing module: 'mux_32'\n mux_32 mem_to_reg_mux (mem_to_reg_mux_to_reg\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:120: Cannot find file containing module: 'mux_5'\n mux_5 reg_dst_mux (reg_w_addr_ex, rt_ex, rd_ex, reg_dst);\n ^~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:121: Cannot find file containing module: 'sign_extend'\n sign_extend se (immi, instruction[15:0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:122: Cannot find file containing module: 'mux_32'\n mux_32 branch_mux (pc_plus_4_or_br, pc_plus_4_if, branch_target\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:124: Cannot find file containing module: 'mux_32'\n mux_32 jump_addr_mux (jump_addr\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:127: Cannot find file containing module: 'mux_32'\n mux_32 jump_mux (pc_plus_4_or_br_or_jump, pc_plus_4_or_br, jump_addr, jump);\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:128: Cannot find file containing module: 'mux_4_1'\n mux_4_1 excp_mux (npc, pc_plus_4_or_br_or_jump, 32'h80000180, cp0_out,\n ^~~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:130: Cannot find file containing module: 'mux_32'\n mux_32 cp0_data_id_mux (read_data_2_excp, read_data_2, cp0_out, mem_ctrl_id[2]);\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:131: Cannot find file containing module: 'mux_5'\n mux_5 cp0_out_addr_mux (cp0_out_addr, instruction[15:11], 5'd14, excp_ret);\n ^~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:132: Cannot find file containing module: 'mux_32'\n mux_32 cp0_data_mem_mux (alu_result_mem_excp, alu_result_mem, alu_src_2_mem\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:141: Cannot find file containing module: 'IF_ID'\n IF_ID if_id (instruction, pc_plus_4_id, address_id, id_valid\n ^~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:144: Cannot find file containing module: 'ID_EX'\n ID_EX id_ex (reg_to_alu_1, reg_to_alu_2, sign_extend_to_alu_src_mux\n ^~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:151: Cannot find file containing module: 'EX_MEM'\n EX_MEM ex_mem (alu_result_mem, alu_src_2_mem, reg_w_addr_mem\n ^~~~~~\n%Error: data/full_repos/permissive/99344209/src/CPU.v:156: Cannot find file containing module: 'MEM_WB'\n MEM_WB mem_wb (dm_r_data_wb, alu_result_wb, reg_w_addr_wb\n ^~~~~~\n%Error: Exiting due to 34 error(s)\n" | 314,831 | module | module CPU(
output [31:0] im_addr, dm_addr,
input [31:0] im_data,
output [31:0] dm_w_data,
input [31:0] dm_r_data_mem,
output mem_read, mem_write,
input [5:0] int_level,
input intr, clk, rst_n
);
wire [31:0] branch_target, jump_addr, pc_plus_4_or_br, pc_plus_4_or_br_or_jump;
wire [31:0] instruction, branch_rs, branch_rt, address_id;
wire [31:0] read_data_1, read_data_2, read_data_2_excp, immi;
wire [31:0] reg_to_alu_1, reg_to_alu_2
, alu_src_mux_to_alu, sign_extend_to_alu_src_mux;
wire [31:0] alu_src_1, alu_src_2_ex;
wire [4:0] rs_ex, rt_ex, rd_ex, shamt;
wire [31:0] alu_src_2_mem;
wire [31:0] dm_r_data_wb;
wire [31:0] mem_to_reg_mux_to_reg;
wire [31:0] alu_result_ex, alu_result_mem, alu_result_mem_excp, alu_result_wb;
wire [31:0] pc_plus_4_if, pc_plus_4_id, npc;
wire [4:0] reg_w_addr_ex, reg_w_addr_mem, reg_w_addr_wb;
wire [5:0] ex_ctrl_id, ex_ctrl_ex;
wire [2:0] mem_ctrl_id, mem_ctrl_ex, mem_ctrl_mem;
wire [2:0] wb_ctrl_id, wb_ctrl_ex, wb_ctrl_mem, wb_ctrl_wb;
wire [5:0] funct;
wire reg_write, alu_src, mem_to_reg, reg_dst;
wire [3:0] alu_op;
wire [3:0] alu_control_to_alu;
wire pc_write, if_id_write, id_ex_flush, if_id_flush
, forward_mem, forward_br_a, forward_br_b, jump_addr_sel, jump;
wire [1:0] forward_a, forward_b;
wire [31:0] cp0_out, status, cause;
reg [31:0] epc;
wire [4:0] cp0_out_addr;
wire inta, excp_ret, cp0_read, cp0_write, id_valid;
reg inta_pending;
always @ (posedge clk)
inta_pending <= inta;
always @ (negedge clk)
epc <= id_valid ? address_id : im_addr;
PC pc (im_addr, npc, pc_write, clk, rst_n);
registers rf (read_data_1, read_data_2
, instruction[25:21], instruction[20:16], reg_w_addr_wb
, mem_to_reg_mux_to_reg, reg_write, clk);
ALU alu (alu_result_ex, , alu_src_1, alu_src_mux_to_alu, shamt, alu_control_to_alu);
alu_control ac (alu_control_to_alu, alu_op, funct);
control cu (ex_ctrl_id, mem_ctrl_id, wb_ctrl_id, inta, excp_ret
, instruction[31:26], instruction[25:21], status, cause);
forwarding_unit_id fui (forward_br_a, forward_br_b, wb_ctrl_mem[1]
, reg_w_addr_mem, instruction[25:21], instruction[20:16]);
forwarding_unit_ex fue (forward_a, forward_b
, wb_ctrl_mem[1], reg_write
, reg_w_addr_mem, reg_w_addr_wb, rs_ex, rt_ex);
forwarding_unit_mem fum (forward_mem, reg_write
, reg_w_addr_wb, reg_w_addr_mem);
hazard_detection_unit hdu (pc_write, if_id_write, if_id_flush, id_ex_flush
, mem_ctrl_ex[1], mem_ctrl_mem[1], wb_ctrl_ex[1], ex_ctrl_id[1]
, reg_w_addr_ex, reg_w_addr_mem
, instruction[25:21], instruction[20:16]
, instruction[31:26], instruction[5:0], branch_taken, inta);
branch_validate bv (branch_taken, instruction[31:26], branch_rs, branch_rt);
jump_detect jd (jump_addr_sel, jump, instruction[31:26], instruction[5:0]);
cp0 cp (cp0_out, status, cause, alu_result_wb, epc, reg_w_addr_wb, cp0_out_addr
, int_level, cp0_write, intr, inta, excp_ret, clk, rst_n);
add add_4 (pc_plus_4_if, im_addr, 32'd4);
add branch_alu (branch_target, pc_plus_4_id, {immi[29:0], 2'b0});
mux_4_1 forward_a_mux (alu_src_1, reg_to_alu_1, alu_result_mem
, mem_to_reg_mux_to_reg, , forward_a);
mux_4_1 forward_b_mux (alu_src_2_ex, reg_to_alu_2, alu_result_mem
, mem_to_reg_mux_to_reg, , forward_b);
mux_32 forward_br_a_mux (branch_rs, read_data_1, alu_result_mem, forward_br_a);
mux_32 forward_br_b_mux (branch_rt, read_data_2, alu_result_mem, forward_br_b);
mux_32 alu_src_mux (alu_src_mux_to_alu
, alu_src_2_ex, sign_extend_to_alu_src_mux, alu_src);
mux_32 forward_mem_mux (dm_w_data, alu_src_2_mem, mem_to_reg_mux_to_reg
, forward_mem);
mux_32 mem_to_reg_mux (mem_to_reg_mux_to_reg
, alu_result_wb, dm_r_data_wb, mem_to_reg);
mux_5 reg_dst_mux (reg_w_addr_ex, rt_ex, rd_ex, reg_dst);
sign_extend se (immi, instruction[15:0]);
mux_32 branch_mux (pc_plus_4_or_br, pc_plus_4_if, branch_target
, branch_taken);
mux_32 jump_addr_mux (jump_addr
, {pc_plus_4_id[31:28], instruction[25:0], 2'b0}
, branch_rs, jump_addr_sel);
mux_32 jump_mux (pc_plus_4_or_br_or_jump, pc_plus_4_or_br, jump_addr, jump);
mux_4_1 excp_mux (npc, pc_plus_4_or_br_or_jump, 32'h80000180, cp0_out,
, {excp_ret, inta});
mux_32 cp0_data_id_mux (read_data_2_excp, read_data_2, cp0_out, mem_ctrl_id[2]);
mux_5 cp0_out_addr_mux (cp0_out_addr, instruction[15:11], 5'd14, excp_ret);
mux_32 cp0_data_mem_mux (alu_result_mem_excp, alu_result_mem, alu_src_2_mem
, cp0_read | wb_ctrl_mem[2]);
assign dm_addr = alu_result_mem;
assign {alu_op, alu_src, reg_dst} = ex_ctrl_ex;
assign {cp0_read, mem_read, mem_write} = mem_ctrl_mem;
assign {cp0_write, reg_write, mem_to_reg} = wb_ctrl_wb;
IF_ID if_id (instruction, pc_plus_4_id, address_id, id_valid
, im_data, pc_plus_4_if, im_addr
, if_id_write, if_id_flush, clk, rst_n);
ID_EX id_ex (reg_to_alu_1, reg_to_alu_2, sign_extend_to_alu_src_mux
, read_data_1, read_data_2_excp, immi
, rs_ex, rt_ex, rd_ex
, instruction[25:21], instruction[20:16], instruction[15:11]
, shamt, funct, ex_ctrl_ex, mem_ctrl_ex, wb_ctrl_ex
, instruction[10:6], instruction[5:0], ex_ctrl_id, mem_ctrl_id, wb_ctrl_id
, id_ex_flush, clk, rst_n);
EX_MEM ex_mem (alu_result_mem, alu_src_2_mem, reg_w_addr_mem
, alu_result_ex, alu_src_2_ex, reg_w_addr_ex
, mem_ctrl_mem, wb_ctrl_mem
, mem_ctrl_ex, wb_ctrl_ex
, clk, rst_n);
MEM_WB mem_wb (dm_r_data_wb, alu_result_wb, reg_w_addr_wb
, dm_r_data_mem, alu_result_mem_excp, reg_w_addr_mem
, wb_ctrl_wb, wb_ctrl_mem
, clk, rst_n);
endmodule | module CPU(
output [31:0] im_addr, dm_addr,
input [31:0] im_data,
output [31:0] dm_w_data,
input [31:0] dm_r_data_mem,
output mem_read, mem_write,
input [5:0] int_level,
input intr, clk, rst_n
); |
wire [31:0] branch_target, jump_addr, pc_plus_4_or_br, pc_plus_4_or_br_or_jump;
wire [31:0] instruction, branch_rs, branch_rt, address_id;
wire [31:0] read_data_1, read_data_2, read_data_2_excp, immi;
wire [31:0] reg_to_alu_1, reg_to_alu_2
, alu_src_mux_to_alu, sign_extend_to_alu_src_mux;
wire [31:0] alu_src_1, alu_src_2_ex;
wire [4:0] rs_ex, rt_ex, rd_ex, shamt;
wire [31:0] alu_src_2_mem;
wire [31:0] dm_r_data_wb;
wire [31:0] mem_to_reg_mux_to_reg;
wire [31:0] alu_result_ex, alu_result_mem, alu_result_mem_excp, alu_result_wb;
wire [31:0] pc_plus_4_if, pc_plus_4_id, npc;
wire [4:0] reg_w_addr_ex, reg_w_addr_mem, reg_w_addr_wb;
wire [5:0] ex_ctrl_id, ex_ctrl_ex;
wire [2:0] mem_ctrl_id, mem_ctrl_ex, mem_ctrl_mem;
wire [2:0] wb_ctrl_id, wb_ctrl_ex, wb_ctrl_mem, wb_ctrl_wb;
wire [5:0] funct;
wire reg_write, alu_src, mem_to_reg, reg_dst;
wire [3:0] alu_op;
wire [3:0] alu_control_to_alu;
wire pc_write, if_id_write, id_ex_flush, if_id_flush
, forward_mem, forward_br_a, forward_br_b, jump_addr_sel, jump;
wire [1:0] forward_a, forward_b;
wire [31:0] cp0_out, status, cause;
reg [31:0] epc;
wire [4:0] cp0_out_addr;
wire inta, excp_ret, cp0_read, cp0_write, id_valid;
reg inta_pending;
always @ (posedge clk)
inta_pending <= inta;
always @ (negedge clk)
epc <= id_valid ? address_id : im_addr;
PC pc (im_addr, npc, pc_write, clk, rst_n);
registers rf (read_data_1, read_data_2
, instruction[25:21], instruction[20:16], reg_w_addr_wb
, mem_to_reg_mux_to_reg, reg_write, clk);
ALU alu (alu_result_ex, , alu_src_1, alu_src_mux_to_alu, shamt, alu_control_to_alu);
alu_control ac (alu_control_to_alu, alu_op, funct);
control cu (ex_ctrl_id, mem_ctrl_id, wb_ctrl_id, inta, excp_ret
, instruction[31:26], instruction[25:21], status, cause);
forwarding_unit_id fui (forward_br_a, forward_br_b, wb_ctrl_mem[1]
, reg_w_addr_mem, instruction[25:21], instruction[20:16]);
forwarding_unit_ex fue (forward_a, forward_b
, wb_ctrl_mem[1], reg_write
, reg_w_addr_mem, reg_w_addr_wb, rs_ex, rt_ex);
forwarding_unit_mem fum (forward_mem, reg_write
, reg_w_addr_wb, reg_w_addr_mem);
hazard_detection_unit hdu (pc_write, if_id_write, if_id_flush, id_ex_flush
, mem_ctrl_ex[1], mem_ctrl_mem[1], wb_ctrl_ex[1], ex_ctrl_id[1]
, reg_w_addr_ex, reg_w_addr_mem
, instruction[25:21], instruction[20:16]
, instruction[31:26], instruction[5:0], branch_taken, inta);
branch_validate bv (branch_taken, instruction[31:26], branch_rs, branch_rt);
jump_detect jd (jump_addr_sel, jump, instruction[31:26], instruction[5:0]);
cp0 cp (cp0_out, status, cause, alu_result_wb, epc, reg_w_addr_wb, cp0_out_addr
, int_level, cp0_write, intr, inta, excp_ret, clk, rst_n);
add add_4 (pc_plus_4_if, im_addr, 32'd4);
add branch_alu (branch_target, pc_plus_4_id, {immi[29:0], 2'b0});
mux_4_1 forward_a_mux (alu_src_1, reg_to_alu_1, alu_result_mem
, mem_to_reg_mux_to_reg, , forward_a);
mux_4_1 forward_b_mux (alu_src_2_ex, reg_to_alu_2, alu_result_mem
, mem_to_reg_mux_to_reg, , forward_b);
mux_32 forward_br_a_mux (branch_rs, read_data_1, alu_result_mem, forward_br_a);
mux_32 forward_br_b_mux (branch_rt, read_data_2, alu_result_mem, forward_br_b);
mux_32 alu_src_mux (alu_src_mux_to_alu
, alu_src_2_ex, sign_extend_to_alu_src_mux, alu_src);
mux_32 forward_mem_mux (dm_w_data, alu_src_2_mem, mem_to_reg_mux_to_reg
, forward_mem);
mux_32 mem_to_reg_mux (mem_to_reg_mux_to_reg
, alu_result_wb, dm_r_data_wb, mem_to_reg);
mux_5 reg_dst_mux (reg_w_addr_ex, rt_ex, rd_ex, reg_dst);
sign_extend se (immi, instruction[15:0]);
mux_32 branch_mux (pc_plus_4_or_br, pc_plus_4_if, branch_target
, branch_taken);
mux_32 jump_addr_mux (jump_addr
, {pc_plus_4_id[31:28], instruction[25:0], 2'b0}
, branch_rs, jump_addr_sel);
mux_32 jump_mux (pc_plus_4_or_br_or_jump, pc_plus_4_or_br, jump_addr, jump);
mux_4_1 excp_mux (npc, pc_plus_4_or_br_or_jump, 32'h80000180, cp0_out,
, {excp_ret, inta});
mux_32 cp0_data_id_mux (read_data_2_excp, read_data_2, cp0_out, mem_ctrl_id[2]);
mux_5 cp0_out_addr_mux (cp0_out_addr, instruction[15:11], 5'd14, excp_ret);
mux_32 cp0_data_mem_mux (alu_result_mem_excp, alu_result_mem, alu_src_2_mem
, cp0_read | wb_ctrl_mem[2]);
assign dm_addr = alu_result_mem;
assign {alu_op, alu_src, reg_dst} = ex_ctrl_ex;
assign {cp0_read, mem_read, mem_write} = mem_ctrl_mem;
assign {cp0_write, reg_write, mem_to_reg} = wb_ctrl_wb;
IF_ID if_id (instruction, pc_plus_4_id, address_id, id_valid
, im_data, pc_plus_4_if, im_addr
, if_id_write, if_id_flush, clk, rst_n);
ID_EX id_ex (reg_to_alu_1, reg_to_alu_2, sign_extend_to_alu_src_mux
, read_data_1, read_data_2_excp, immi
, rs_ex, rt_ex, rd_ex
, instruction[25:21], instruction[20:16], instruction[15:11]
, shamt, funct, ex_ctrl_ex, mem_ctrl_ex, wb_ctrl_ex
, instruction[10:6], instruction[5:0], ex_ctrl_id, mem_ctrl_id, wb_ctrl_id
, id_ex_flush, clk, rst_n);
EX_MEM ex_mem (alu_result_mem, alu_src_2_mem, reg_w_addr_mem
, alu_result_ex, alu_src_2_ex, reg_w_addr_ex
, mem_ctrl_mem, wb_ctrl_mem
, mem_ctrl_ex, wb_ctrl_ex
, clk, rst_n);
MEM_WB mem_wb (dm_r_data_wb, alu_result_wb, reg_w_addr_wb
, dm_r_data_mem, alu_result_mem_excp, reg_w_addr_mem
, wb_ctrl_wb, wb_ctrl_mem
, clk, rst_n);
endmodule | 0 |
142,592 | data/full_repos/permissive/99344209/src/EX_MEM.v | 99,344,209 | EX_MEM.v | v | 43 | 50 | [] | [] | [] | [(13, 42)] | null | data/verilator_xmls/e0c7cb6b-1d8d-4b04-b652-86a2f5115c4e.xml | null | 314,832 | module | module EX_MEM(
output reg [31:0] alu_result_mem, alu_src_2_mem,
output reg [4:0] reg_w_addr_mem,
input [31:0] alu_result_ex, alu_src_2_ex,
input [4:0] reg_w_addr_ex,
output reg [2:0] mem_ctrl_mem,
output reg [2:0] wb_ctrl_mem,
input [2:0] mem_ctrl_ex,
input [2:0] wb_ctrl_ex,
input clk, rst_n
);
always @ (negedge clk)
begin
alu_result_mem <= alu_result_ex;
alu_src_2_mem <= alu_src_2_ex;
reg_w_addr_mem <= reg_w_addr_ex;
if (!rst_n)
begin
mem_ctrl_mem <= 3'b0;
wb_ctrl_mem <= 3'b0;
end
else
begin
mem_ctrl_mem <= mem_ctrl_ex;
wb_ctrl_mem <= wb_ctrl_ex;
end
end
endmodule | module EX_MEM(
output reg [31:0] alu_result_mem, alu_src_2_mem,
output reg [4:0] reg_w_addr_mem,
input [31:0] alu_result_ex, alu_src_2_ex,
input [4:0] reg_w_addr_ex,
output reg [2:0] mem_ctrl_mem,
output reg [2:0] wb_ctrl_mem,
input [2:0] mem_ctrl_ex,
input [2:0] wb_ctrl_ex,
input clk, rst_n
); |
always @ (negedge clk)
begin
alu_result_mem <= alu_result_ex;
alu_src_2_mem <= alu_src_2_ex;
reg_w_addr_mem <= reg_w_addr_ex;
if (!rst_n)
begin
mem_ctrl_mem <= 3'b0;
wb_ctrl_mem <= 3'b0;
end
else
begin
mem_ctrl_mem <= mem_ctrl_ex;
wb_ctrl_mem <= wb_ctrl_ex;
end
end
endmodule | 0 |
142,593 | data/full_repos/permissive/99344209/src/forwarding_unit_ex.v | 99,344,209 | forwarding_unit_ex.v | v | 42 | 68 | [] | [] | [] | [(13, 41)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_ex.v:28: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_wb\' generates 5 bits.\n : ... In instance forwarding_unit_ex\n else if (reg_write_wb && reg_w_addr_wb && reg_w_addr_wb == rs_ex)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_ex.v:26: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_mem\' generates 5 bits.\n : ... In instance forwarding_unit_ex\n if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rs_ex)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_ex.v:35: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_wb\' generates 5 bits.\n : ... In instance forwarding_unit_ex\n else if (reg_write_wb && reg_w_addr_wb && reg_w_addr_wb == rt_ex)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_ex.v:33: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_mem\' generates 5 bits.\n : ... In instance forwarding_unit_ex\n if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rt_ex)\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 314,833 | module | module forwarding_unit_ex(
output reg [1:0] forward_a, forward_b,
input reg_write_mem, reg_write_wb,
input [4:0] reg_w_addr_mem, reg_w_addr_wb, rs_ex, rt_ex
);
always @ (*)
begin
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rs_ex)
forward_a = 2'b01;
else if (reg_write_wb && reg_w_addr_wb && reg_w_addr_wb == rs_ex)
forward_a = 2'b10;
else
forward_a = 2'b00;
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rt_ex)
forward_b = 2'b01;
else if (reg_write_wb && reg_w_addr_wb && reg_w_addr_wb == rt_ex)
forward_b = 2'b10;
else
forward_b = 2'b00;
end
endmodule | module forwarding_unit_ex(
output reg [1:0] forward_a, forward_b,
input reg_write_mem, reg_write_wb,
input [4:0] reg_w_addr_mem, reg_w_addr_wb, rs_ex, rt_ex
); |
always @ (*)
begin
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rs_ex)
forward_a = 2'b01;
else if (reg_write_wb && reg_w_addr_wb && reg_w_addr_wb == rs_ex)
forward_a = 2'b10;
else
forward_a = 2'b00;
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rt_ex)
forward_b = 2'b01;
else if (reg_write_wb && reg_w_addr_wb && reg_w_addr_wb == rt_ex)
forward_b = 2'b10;
else
forward_b = 2'b00;
end
endmodule | 0 |
142,594 | data/full_repos/permissive/99344209/src/forwarding_unit_id.v | 99,344,209 | forwarding_unit_id.v | v | 33 | 66 | [] | [] | [] | [(13, 32)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_id.v:21: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_mem\' generates 5 bits.\n : ... In instance forwarding_unit_id\n if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rs_id)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_id.v:26: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_mem\' generates 5 bits.\n : ... In instance forwarding_unit_id\n if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rt_id)\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 314,834 | module | module forwarding_unit_id(
output reg forward_a, forward_b,
input reg_write_mem,
input [4:0] reg_w_addr_mem, rs_id, rt_id
);
always @ (*)
begin
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rs_id)
forward_a = 1'b1;
else
forward_a = 1'b0;
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rt_id)
forward_b = 1'b1;
else
forward_b = 1'b0;
end
endmodule | module forwarding_unit_id(
output reg forward_a, forward_b,
input reg_write_mem,
input [4:0] reg_w_addr_mem, rs_id, rt_id
); |
always @ (*)
begin
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rs_id)
forward_a = 1'b1;
else
forward_a = 1'b0;
if (reg_write_mem && reg_w_addr_mem && reg_w_addr_mem == rt_id)
forward_b = 1'b1;
else
forward_b = 1'b0;
end
endmodule | 0 |
142,595 | data/full_repos/permissive/99344209/src/forwarding_unit_mem.v | 99,344,209 | forwarding_unit_mem.v | v | 27 | 43 | [] | [] | [] | [(13, 26)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/forwarding_unit_mem.v:20: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_wb\' generates 5 bits.\n : ... In instance forwarding_unit_mem\n if (reg_write_wb && reg_w_addr_wb\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 314,835 | module | module forwarding_unit_mem(
output reg forward,
input reg_write_wb,
input [4:0] reg_w_addr_wb, reg_w_addr_mem
);
always @ (*)
if (reg_write_wb && reg_w_addr_wb
&& reg_w_addr_wb == reg_w_addr_mem)
forward = 1'b1;
else
forward = 1'b0;
endmodule | module forwarding_unit_mem(
output reg forward,
input reg_write_wb,
input [4:0] reg_w_addr_wb, reg_w_addr_mem
); |
always @ (*)
if (reg_write_wb && reg_w_addr_wb
&& reg_w_addr_wb == reg_w_addr_mem)
forward = 1'b1;
else
forward = 1'b0;
endmodule | 0 |
142,596 | data/full_repos/permissive/99344209/src/hazard_detection_unit.v | 99,344,209 | hazard_detection_unit.v | v | 73 | 81 | [] | [] | [] | [(13, 72)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/hazard_detection_unit.v:39: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_ex\' generates 5 bits.\n : ... In instance hazard_detection_unit\n else if (mem_read_ex && reg_w_addr_ex\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/hazard_detection_unit.v:42: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_ex\' generates 5 bits.\n : ... In instance hazard_detection_unit\n && (reg_write_ex && reg_w_addr_ex && reg_w_addr_ex == rs_id\n ^~\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/hazard_detection_unit.v:43: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_mem\' generates 5 bits.\n : ... In instance hazard_detection_unit\n || mem_read_mem && reg_w_addr_mem && reg_w_addr_mem == rs_id)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/hazard_detection_unit.v:45: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_ex\' generates 5 bits.\n : ... In instance hazard_detection_unit\n && (reg_write_ex && reg_w_addr_ex && reg_w_addr_ex == rt_id\n ^~\n%Warning-WIDTH: data/full_repos/permissive/99344209/src/hazard_detection_unit.v:46: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'reg_w_addr_mem\' generates 5 bits.\n : ... In instance hazard_detection_unit\n || mem_read_mem && reg_w_addr_mem && reg_w_addr_mem == rt_id))\n ^~\n%Error: Exiting due to 5 warning(s)\n' | 314,836 | module | module hazard_detection_unit(
output reg pc_write, if_id_write, if_id_flush, id_ex_flush,
input mem_read_ex, mem_read_mem, reg_write_ex, alu_src_id,
input [4:0] reg_w_addr_ex, reg_w_addr_mem, rs_id, rt_id,
input [5:0] op, funct,
input branch_taken, inta
);
parameter beq = 6'b000100;
parameter bne = 6'b000101;
parameter bgtz = 6'b000111;
parameter j = 6'b000010;
parameter jr_op = 6'b000000;
parameter jr_funct = 6'b001000;
parameter cp0_instr = 6'b010000;
parameter eret = 5'b10000;
always @ (*)
if (inta)
begin
pc_write = 1'b1;
if_id_write = 1'b1;
if_id_flush = 1'b1;
id_ex_flush = 1'b1;
end
else if (mem_read_ex && reg_w_addr_ex
&& (reg_w_addr_ex == rs_id || (reg_w_addr_ex == rt_id && !alu_src_id))
|| (op == beq || op == bne || op == bgtz || op == jr_op && funct == jr_funct)
&& (reg_write_ex && reg_w_addr_ex && reg_w_addr_ex == rs_id
|| mem_read_mem && reg_w_addr_mem && reg_w_addr_mem == rs_id)
|| (op == beq || op == bne)
&& (reg_write_ex && reg_w_addr_ex && reg_w_addr_ex == rt_id
|| mem_read_mem && reg_w_addr_mem && reg_w_addr_mem == rt_id))
begin
pc_write = 1'b0;
if_id_write = 1'b0;
if_id_flush = 1'b0;
id_ex_flush = 1'b1;
end
else if ((op == beq || op == bne || op == bgtz) && branch_taken
|| op == j || op == cp0_instr && rs_id == eret)
begin
pc_write = 1'b1;
if_id_write = 1'b1;
if_id_flush = 1'b1;
id_ex_flush = 1'b0;
end
else
begin
pc_write = 1'b1;
if_id_write = 1'b1;
if_id_flush = 1'b0;
id_ex_flush = 1'b0;
end
endmodule | module hazard_detection_unit(
output reg pc_write, if_id_write, if_id_flush, id_ex_flush,
input mem_read_ex, mem_read_mem, reg_write_ex, alu_src_id,
input [4:0] reg_w_addr_ex, reg_w_addr_mem, rs_id, rt_id,
input [5:0] op, funct,
input branch_taken, inta
); |
parameter beq = 6'b000100;
parameter bne = 6'b000101;
parameter bgtz = 6'b000111;
parameter j = 6'b000010;
parameter jr_op = 6'b000000;
parameter jr_funct = 6'b001000;
parameter cp0_instr = 6'b010000;
parameter eret = 5'b10000;
always @ (*)
if (inta)
begin
pc_write = 1'b1;
if_id_write = 1'b1;
if_id_flush = 1'b1;
id_ex_flush = 1'b1;
end
else if (mem_read_ex && reg_w_addr_ex
&& (reg_w_addr_ex == rs_id || (reg_w_addr_ex == rt_id && !alu_src_id))
|| (op == beq || op == bne || op == bgtz || op == jr_op && funct == jr_funct)
&& (reg_write_ex && reg_w_addr_ex && reg_w_addr_ex == rs_id
|| mem_read_mem && reg_w_addr_mem && reg_w_addr_mem == rs_id)
|| (op == beq || op == bne)
&& (reg_write_ex && reg_w_addr_ex && reg_w_addr_ex == rt_id
|| mem_read_mem && reg_w_addr_mem && reg_w_addr_mem == rt_id))
begin
pc_write = 1'b0;
if_id_write = 1'b0;
if_id_flush = 1'b0;
id_ex_flush = 1'b1;
end
else if ((op == beq || op == bne || op == bgtz) && branch_taken
|| op == j || op == cp0_instr && rs_id == eret)
begin
pc_write = 1'b1;
if_id_write = 1'b1;
if_id_flush = 1'b1;
id_ex_flush = 1'b0;
end
else
begin
pc_write = 1'b1;
if_id_write = 1'b1;
if_id_flush = 1'b0;
id_ex_flush = 1'b0;
end
endmodule | 0 |
142,597 | data/full_repos/permissive/99344209/src/ID_EX.v | 99,344,209 | ID_EX.v | v | 57 | 46 | [] | [] | [] | [(13, 56)] | null | data/verilator_xmls/484aa238-7e40-4abe-bad3-c8ecf8c9b541.xml | null | 314,837 | module | module ID_EX(
output reg [31:0] reg_to_alu_1, reg_to_alu_2
, sign_extend_to_alu_src_mux,
input [31:0] read_data_1, read_data_2, immi,
output reg [4:0] rs_ex, rt_ex, rd_ex,
input [4:0] rs_id, rt_id, rd_id,
output reg [4:0] shamt_ex,
output reg [5:0] funct_ex,
output reg [5:0] ex_ctrl_ex,
output reg [2:0] mem_ctrl_ex,
output reg [2:0] wb_ctrl_ex,
input [4:0] shamt_id,
input [5:0] funct_id,
input [5:0] ex_ctrl_id,
input [2:0] mem_ctrl_id,
input [2:0] wb_ctrl_id,
input id_ex_flush, clk, rst_n
);
always @ (negedge clk)
begin
reg_to_alu_1 <= read_data_1;
reg_to_alu_2 <= read_data_2;
sign_extend_to_alu_src_mux <= immi;
shamt_ex <= shamt_id;
funct_ex <= funct_id;
rs_ex <= rs_id;
rt_ex <= rt_id;
rd_ex <= rd_id;
if (!rst_n || id_ex_flush)
begin
ex_ctrl_ex <= 6'b0;
mem_ctrl_ex <= 3'b0;
wb_ctrl_ex <= 3'b0;
end
else
begin
ex_ctrl_ex <= ex_ctrl_id;
mem_ctrl_ex <= mem_ctrl_id;
wb_ctrl_ex <= wb_ctrl_id;
end
end
endmodule | module ID_EX(
output reg [31:0] reg_to_alu_1, reg_to_alu_2
, sign_extend_to_alu_src_mux,
input [31:0] read_data_1, read_data_2, immi,
output reg [4:0] rs_ex, rt_ex, rd_ex,
input [4:0] rs_id, rt_id, rd_id,
output reg [4:0] shamt_ex,
output reg [5:0] funct_ex,
output reg [5:0] ex_ctrl_ex,
output reg [2:0] mem_ctrl_ex,
output reg [2:0] wb_ctrl_ex,
input [4:0] shamt_id,
input [5:0] funct_id,
input [5:0] ex_ctrl_id,
input [2:0] mem_ctrl_id,
input [2:0] wb_ctrl_id,
input id_ex_flush, clk, rst_n
); |
always @ (negedge clk)
begin
reg_to_alu_1 <= read_data_1;
reg_to_alu_2 <= read_data_2;
sign_extend_to_alu_src_mux <= immi;
shamt_ex <= shamt_id;
funct_ex <= funct_id;
rs_ex <= rs_id;
rt_ex <= rt_id;
rd_ex <= rd_id;
if (!rst_n || id_ex_flush)
begin
ex_ctrl_ex <= 6'b0;
mem_ctrl_ex <= 3'b0;
wb_ctrl_ex <= 3'b0;
end
else
begin
ex_ctrl_ex <= ex_ctrl_id;
mem_ctrl_ex <= mem_ctrl_id;
wb_ctrl_ex <= wb_ctrl_id;
end
end
endmodule | 0 |
142,598 | data/full_repos/permissive/99344209/src/IF_ID.v | 99,344,209 | IF_ID.v | v | 41 | 58 | [] | [] | [] | [(13, 40)] | null | data/verilator_xmls/8410cfba-c827-4a68-be69-8c8bff92f6dc.xml | null | 314,838 | module | module IF_ID(
output reg [31:0] instruction, pc_plus_4_id, address_id,
output reg valid,
input [31:0] im_data, pc_plus_4_if, address_if,
input if_id_write, if_id_flush, clk, rst_n
);
always @ (negedge clk)
begin
if (if_id_write)
begin
pc_plus_4_id <= pc_plus_4_if;
address_id <= address_if;
end
if (!rst_n || if_id_flush)
begin
instruction <= 32'b0;
valid <= 1'b0;
end
else if (if_id_write)
begin
instruction <= im_data;
valid <= 1'b1;
end
end
endmodule | module IF_ID(
output reg [31:0] instruction, pc_plus_4_id, address_id,
output reg valid,
input [31:0] im_data, pc_plus_4_if, address_if,
input if_id_write, if_id_flush, clk, rst_n
); |
always @ (negedge clk)
begin
if (if_id_write)
begin
pc_plus_4_id <= pc_plus_4_if;
address_id <= address_if;
end
if (!rst_n || if_id_flush)
begin
instruction <= 32'b0;
valid <= 1'b0;
end
else if (if_id_write)
begin
instruction <= im_data;
valid <= 1'b1;
end
end
endmodule | 0 |
142,599 | data/full_repos/permissive/99344209/src/jump_detect.v | 99,344,209 | jump_detect.v | v | 40 | 45 | [] | [] | [] | [(13, 39)] | null | data/verilator_xmls/e99e574c-d23d-4eb6-9790-938c7ddadeef.xml | null | 314,839 | module | module jump_detect(
output reg jump_addr_sel, jump,
input [5:0] op, funct
);
parameter j = 6'b000010;
parameter jr_op = 6'b000000;
parameter jr_funct = 6'b001000;
always @ (*)
if (op == j)
begin
jump = 1'b1;
jump_addr_sel = 1'b0;
end
else if (op == jr_op && funct == jr_funct)
begin
jump = 1'b1;
jump_addr_sel = 1'b1;
end
else
begin
jump = 1'b0;
jump_addr_sel = 1'bx;
end
endmodule | module jump_detect(
output reg jump_addr_sel, jump,
input [5:0] op, funct
); |
parameter j = 6'b000010;
parameter jr_op = 6'b000000;
parameter jr_funct = 6'b001000;
always @ (*)
if (op == j)
begin
jump = 1'b1;
jump_addr_sel = 1'b0;
end
else if (op == jr_op && funct == jr_funct)
begin
jump = 1'b1;
jump_addr_sel = 1'b1;
end
else
begin
jump = 1'b0;
jump_addr_sel = 1'bx;
end
endmodule | 0 |
142,600 | data/full_repos/permissive/99344209/src/MEM_WB.v | 99,344,209 | MEM_WB.v | v | 35 | 48 | [] | [] | [] | [(13, 34)] | null | data/verilator_xmls/af1e0211-af91-4a4b-a54c-6e85406e9ba7.xml | null | 314,840 | module | module MEM_WB(
output reg [31:0] dm_r_data_wb, alu_result_wb,
output reg [4:0] reg_w_addr_wb,
input [31:0] dm_r_data_mem, alu_result_mem,
input [4:0] reg_w_addr_mem,
output reg [2:0] wb_ctrl_wb,
input [2:0] wb_ctrl_mem,
input clk, rst_n
);
always @ (negedge clk)
begin
dm_r_data_wb <= dm_r_data_mem;
alu_result_wb <= alu_result_mem;
reg_w_addr_wb <= reg_w_addr_mem;
if (!rst_n)
wb_ctrl_wb <= 3'b0;
else
wb_ctrl_wb <= wb_ctrl_mem;
end
endmodule | module MEM_WB(
output reg [31:0] dm_r_data_wb, alu_result_wb,
output reg [4:0] reg_w_addr_wb,
input [31:0] dm_r_data_mem, alu_result_mem,
input [4:0] reg_w_addr_mem,
output reg [2:0] wb_ctrl_wb,
input [2:0] wb_ctrl_mem,
input clk, rst_n
); |
always @ (negedge clk)
begin
dm_r_data_wb <= dm_r_data_mem;
alu_result_wb <= alu_result_mem;
reg_w_addr_wb <= reg_w_addr_mem;
if (!rst_n)
wb_ctrl_wb <= 3'b0;
else
wb_ctrl_wb <= wb_ctrl_mem;
end
endmodule | 0 |
142,601 | data/full_repos/permissive/99344209/src/mux_32.v | 99,344,209 | mux_32.v | v | 22 | 39 | [] | [] | [] | [(13, 21)] | null | data/verilator_xmls/9d8eeef6-85e1-4bf7-9f88-e4b9f0267d66.xml | null | 314,841 | module | module mux_32(
output [31:0] out,
input [31:0] a, b,
input sel
);
assign out = sel ? b : a;
endmodule | module mux_32(
output [31:0] out,
input [31:0] a, b,
input sel
); |
assign out = sel ? b : a;
endmodule | 0 |
142,602 | data/full_repos/permissive/99344209/src/mux_4_1.v | 99,344,209 | mux_4_1.v | v | 28 | 39 | [] | [] | [] | [(13, 27)] | null | data/verilator_xmls/e49b0354-9785-49fa-b3d8-acca168ecc2b.xml | null | 314,842 | module | module mux_4_1(
output reg [31:0] out,
input [31:0] a, b, c, d,
input [1:0] sel
);
always @ (*)
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
endcase
endmodule | module mux_4_1(
output reg [31:0] out,
input [31:0] a, b, c, d,
input [1:0] sel
); |
always @ (*)
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
endcase
endmodule | 0 |
142,603 | data/full_repos/permissive/99344209/src/mux_5.v | 99,344,209 | mux_5.v | v | 22 | 39 | [] | [] | [] | [(13, 21)] | null | data/verilator_xmls/f228ed33-0eea-4e15-90c6-70ad07f9ea87.xml | null | 314,843 | module | module mux_5(
output [4:0] out,
input [4:0] a, b,
input sel
);
assign out = sel ? b : a;
endmodule | module mux_5(
output [4:0] out,
input [4:0] a, b,
input sel
); |
assign out = sel ? b : a;
endmodule | 0 |
142,604 | data/full_repos/permissive/99344209/src/PC.v | 99,344,209 | PC.v | v | 26 | 39 | [] | [] | [] | [(13, 25)] | null | data/verilator_xmls/4cf51e50-2cf0-4e4b-b071-ed8a0a66f211.xml | null | 314,844 | module | module PC(
output reg [31:0] pc,
input [31:0] npc,
input pc_write, clk, rst_n
);
always @ (negedge clk)
if (~rst_n)
pc <= 32'b0;
else if (pc_write)
pc <= npc;
endmodule | module PC(
output reg [31:0] pc,
input [31:0] npc,
input pc_write, clk, rst_n
); |
always @ (negedge clk)
if (~rst_n)
pc <= 32'b0;
else if (pc_write)
pc <= npc;
endmodule | 0 |
142,605 | data/full_repos/permissive/99344209/src/reg_file_v4.v | 99,344,209 | reg_file_v4.v | v | 47 | 40 | [] | [] | [] | [(13, 46)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/99344209/src/reg_file_v4.v:28: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'r3_addr\' generates 5 bits.\n : ... In instance registers\n if (r3_wr && r3_addr)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 314,845 | module | module registers(
output reg [31:0] r1_dout,
output reg [31:0] r2_dout,
input [4:0] r1_addr,
input [4:0] r2_addr,
input [4:0] r3_addr,
input [31:0] r3_din,
input r3_wr, clk
);
reg [31:0] register[31:0];
always @ (posedge clk)
begin
if (r3_wr && r3_addr)
register[r3_addr] <= r3_din;
if (r1_addr == 5'b0)
r1_dout <= 32'b0;
else if (r3_wr && r1_addr == r3_addr)
r1_dout <= r3_din;
else
r1_dout <= register[r1_addr];
if (r2_addr == 5'b0)
r2_dout <= 32'b0;
else if (r3_wr && r2_addr == r3_addr)
r2_dout <= r3_din;
else
r2_dout <= register[r2_addr];
end
endmodule | module registers(
output reg [31:0] r1_dout,
output reg [31:0] r2_dout,
input [4:0] r1_addr,
input [4:0] r2_addr,
input [4:0] r3_addr,
input [31:0] r3_din,
input r3_wr, clk
); |
reg [31:0] register[31:0];
always @ (posedge clk)
begin
if (r3_wr && r3_addr)
register[r3_addr] <= r3_din;
if (r1_addr == 5'b0)
r1_dout <= 32'b0;
else if (r3_wr && r1_addr == r3_addr)
r1_dout <= r3_din;
else
r1_dout <= register[r1_addr];
if (r2_addr == 5'b0)
r2_dout <= 32'b0;
else if (r3_wr && r2_addr == r3_addr)
r2_dout <= r3_din;
else
r2_dout <= register[r2_addr];
end
endmodule | 0 |
142,606 | data/full_repos/permissive/99344209/src/sign_extend.v | 99,344,209 | sign_extend.v | v | 21 | 61 | [] | [] | [] | [(13, 20)] | null | data/verilator_xmls/5efae1f1-e4a8-4dec-83e7-e718d02e5870.xml | null | 314,846 | module | module sign_extend(
output [31:0] extended,
input [15:0] src
);
assign extended = src[15] ? {16'hFFFF, src} : {16'h0, src};
endmodule | module sign_extend(
output [31:0] extended,
input [15:0] src
); |
assign extended = src[15] ? {16'hFFFF, src} : {16'h0, src};
endmodule | 0 |
142,607 | data/full_repos/permissive/99344209/test/cpu_test.v | 99,344,209 | cpu_test.v | v | 83 | 81 | [] | [] | [] | [(25, 82)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/99344209/test/cpu_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n forever #50\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/99344209/test/cpu_test.v:69: syntax error, unexpected \'@\'\n @ (posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/99344209/test/cpu_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1545;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/99344209/test/cpu_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #90;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 314,847 | module | module cpu_test;
wire [31:0] im_data;
wire [31:0] dm_r_data;
reg [5:0] int_level;
reg intr, clk, rst_n;
wire [31:0] im_addr;
wire [31:0] dm_addr;
wire [31:0] dm_w_data;
wire mem_read;
wire mem_write;
CPU uut (
.im_addr(im_addr),
.dm_addr(dm_addr),
.im_data(im_data),
.dm_w_data(dm_w_data),
.dm_r_data_mem(dm_r_data),
.mem_read(mem_read),
.mem_write(mem_write),
.int_level(int_level),
.intr(intr),
.clk(clk),
.rst_n(rst_n)
);
im im0 (clk, im_addr[8:2], im_data);
dm dm0 (clk, mem_write, dm_addr[7:2], dm_w_data
, clk, mem_read, dm_addr[7:2], dm_r_data);
initial
begin
clk = 1'b0;
forever #50
clk = ~clk;
end
initial
begin
rst_n = 1'b0;
intr = 1'b0;
int_level = 6'b0;
@ (posedge clk);
@ (negedge clk);
rst_n = 1'b1;
#1545;
intr = 1'b1;
int_level = 6'b001000;
#90;
intr = 1'b0;
int_level = 6'b0;
end
endmodule | module cpu_test; |
wire [31:0] im_data;
wire [31:0] dm_r_data;
reg [5:0] int_level;
reg intr, clk, rst_n;
wire [31:0] im_addr;
wire [31:0] dm_addr;
wire [31:0] dm_w_data;
wire mem_read;
wire mem_write;
CPU uut (
.im_addr(im_addr),
.dm_addr(dm_addr),
.im_data(im_data),
.dm_w_data(dm_w_data),
.dm_r_data_mem(dm_r_data),
.mem_read(mem_read),
.mem_write(mem_write),
.int_level(int_level),
.intr(intr),
.clk(clk),
.rst_n(rst_n)
);
im im0 (clk, im_addr[8:2], im_data);
dm dm0 (clk, mem_write, dm_addr[7:2], dm_w_data
, clk, mem_read, dm_addr[7:2], dm_r_data);
initial
begin
clk = 1'b0;
forever #50
clk = ~clk;
end
initial
begin
rst_n = 1'b0;
intr = 1'b0;
int_level = 6'b0;
@ (posedge clk);
@ (negedge clk);
rst_n = 1'b1;
#1545;
intr = 1'b1;
int_level = 6'b001000;
#90;
intr = 1'b0;
int_level = 6'b0;
end
endmodule | 0 |
142,608 | data/full_repos/permissive/99514691/Processor.v | 99,514,691 | Processor.v | v | 526 | 199 | [] | [] | [] | [(155, 675)] | null | null | 1: b'%Error: data/full_repos/permissive/99514691/Processor.v:3: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99514691,data/full_repos/permissive/99514691/Constants.v\n data/full_repos/permissive/99514691,data/full_repos/permissive/99514691/Constants.v.v\n data/full_repos/permissive/99514691,data/full_repos/permissive/99514691/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: Exiting due to 1 error(s)\n' | 314,861 | module | module Processor (
input clock,
input reset,
output [31:0] dif_instruction,
output [31:0] dif_pc_usable,
output [31:0] did_instruction,
output [31:0] did_pc_usable,
output [31:0] did_rt_data,
output [31:0] did_rs_data,
output [31:0] did_se_immediate,
output [4:0] did_rt,
output [4:0] did_rs,
output [31:0] dwb_write_data,
output [31:0] dex_alu_result,
output [31:0] dex_alu_a,
output [31:0] dex_alu_b,
output [4:0] dex_alu_op,
output [4:0] dme_rt_rd,
output [31:0] dme_data_mem,
output [31:0] dme_data_write_mem,
output [4:0] dwb_rt_rd,
output dif_flush,
output did_flush,
output dex_alu_src,
output [1:0] dex_fwd_rt_sel,
output [1:0] dex_fwd_rs_sel,
output dif_stall,
output did_stall,
output dwb_write_reg,
output dme_write_mem,
output dme_read_mem,
output did_branch_delay_slot
);
parameter INSTRUCTIONS = "C:/Outros/Full Processor/MIPS32_Processor/Final Project/MIPS32_Full/Testing Codes/Exponential.txt";
wire if_stall;
wire if_flush;
wire [31:0] if_pc;
wire [31:0] if_pc_out;
wire [31:0] if_pc_usable;
wire [31:0] if_pc_add_4;
wire [31:0] if_instruction;
wire if_bra_delay;
wire id_stall;
wire id_reg_dst;
wire id_alu_src;
wire id_mem_write;
wire id_mem_read;
wire id_mem_to_reg;
wire id_reg_write;
wire id_cmp_eq;
wire id_sign_extend;
wire id_jump_link;
wire [4:0] id_alu_op;
wire id_branch_delay_slot;
wire [1:0] id_fwd_rs_sel;
wire [1:0] id_fwd_rt_sel;
wire id_w_rs_ex;
wire id_n_rs_ex;
wire id_w_rt_ex;
wire id_n_rt_ex;
wire [1:0] id_pc_source_sel;
wire [31:0] id_instruction;
wire [4:0] id_rs = id_instruction[25:21];
wire [4:0] id_rt = id_instruction[20:16];
wire [5:0] id_opcode = id_instruction[31:26];
wire [5:0] id_funct = id_instruction[5:0];
wire [31:0] id_reg1_data;
wire [31:0] id_reg1_end;
wire [31:0] id_reg2_data;
wire [31:0] id_reg2_end;
wire [31:0] id_immediate = id_instruction[15:0];
wire [31:0] id_pc_add_4;
wire [31:0] id_pc;
wire [31:0] id_jump_address = id_instruction[25:0];
wire [31:0] id_jump_address_usable = {id_pc_add_4[31:28], id_jump_address[25:0], 2'b00};
wire [31:0] id_sign_extended_immediate = (id_sign_extend & id_immediate[15]) ? {14'h3fff, id_immediate[15:0]} : {14'h0000, id_immediate[15:0]};
wire [31:0] id_immediate_left_shifted2 = {id_sign_extended_immediate[29:0], 2'b00};
wire [31:0] id_branch_address;
wire ex_stall;
wire ex_mem_read;
wire ex_mem_write;
wire ex_mem_to_reg;
wire ex_reg_write;
wire ex_alu_src;
wire ex_jump_link;
wire [1:0] ex_jump_link_reg_dst;
wire [4:0] ex_alu_op;
wire [1:0] ex_fwd_rs_sel;
wire [1:0] ex_fwd_rt_sel;
wire ex_w_rs_ex;
wire ex_n_rs_ex;
wire ex_w_rt_ex;
wire ex_n_rt_ex;
wire [4:0] ex_rs;
wire [4:0] ex_rt;
wire [4:0] ex_rd;
wire [4:0] ex_rt_rd;
wire [4:0] ex_shamt;
wire [31:0] ex_reg1_data;
wire [31:0] ex_reg1_fwd;
wire [31:0] ex_reg2_data;
wire [31:0] ex_reg2_fwd;
wire [31:0] ex_data2_imm;
wire [31:0] ex_sign_extended_immediate;
wire [31:0] ex_alu_result;
wire [31:0] ex_pc;
wire ex_alu_overflow;
wire me_mem_read;
wire me_mem_write;
wire me_mem_to_reg;
wire me_reg_write;
wire me_write_data_fwd_sel;
wire [4:0] me_rt_rd;
wire [31:0] me_alu_result;
wire [31:0] me_data2_reg;
wire [31:0] me_pc;
wire [31:0] me_mem_read_data;
wire [31:0] me_mem_write_data;
wire wb_mem_to_reg;
wire wb_reg_write;
wire [4:0] wb_rt_rd;
wire [31:0] wb_data_memory;
wire [31:0] wb_alu_result;
wire [31:0] wb_write_data;
wire [7:0] id_signal_forwarding;
wire [7:0] final_signal_forwarding;
assign final_signal_forwarding = {id_signal_forwarding[7:4], ex_w_rs_ex, ex_n_rs_ex, ex_w_rt_ex, ex_n_rt_ex};
assign if_bra_delay = id_branch_delay_slot;
assign dif_instruction = if_instruction;
assign dif_pc_usable = if_pc_add_4;
assign did_instruction = id_instruction;
assign did_pc_usable = id_pc_add_4;
assign did_rs_data = id_reg1_end;
assign did_rt_data = id_reg2_end;
assign did_rt = id_rt;
assign did_rs = id_rs;
assign did_se_immediate = id_sign_extended_immediate;
assign dwb_rt_rd = wb_rt_rd;
assign dwb_write_data = wb_write_data;
assign dex_alu_result = ex_alu_result;
assign dex_alu_a = ex_reg1_fwd;
assign dex_alu_b = ex_data2_imm;
assign dex_alu_op = ex_alu_op;
assign dme_rt_rd = me_rt_rd;
assign dme_data_mem = me_mem_read_data;
assign dme_data_write_mem = me_mem_write_data;
assign dif_flush = if_flush;
assign dex_alu_src = ex_alu_src;
assign dex_fwd_rt_sel = ex_fwd_rt_sel;
assign dex_fwd_rs_sel = ex_fwd_rs_sel;
assign dif_stall = if_stall;
assign did_stall = id_stall;
assign dwb_write_reg = wb_reg_write;
assign dme_write_mem = me_mem_write;
assign dme_read_mem = me_mem_read;
assign did_branch_delay_slot = if_bra_delay;
Multiplex4 #(.WIDTH(32)) PC_Source_Selection_Mux (
.sel (id_pc_source_sel),
.in0 (if_pc_add_4),
.in1 (id_jump_address_usable),
.in2 (id_branch_address),
.in3 (id_reg1_end),
.out (if_pc_out)
);
PC_Latch PC (
.clock (clock),
.reset (reset),
.enable (~(if_stall | id_stall)),
.data (if_pc_out),
.value (if_pc_usable)
);
InstructionMemoryInterface #(.INSTRUCTION_FILE(INSTRUCTIONS)) instruction_memory (
.if_stall (if_stall),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction)
);
SimpleAdder PC_Increment (
.A (if_pc_usable),
.B (32'h00000004),
.C (if_pc_add_4)
);
Instruction_Fetch_Decode_Pipeline IF_ID (
.clock (clock),
.reset (reset),
.if_flush (if_flush),
.if_stall (if_stall),
.id_stall (id_stall),
.if_bra_delay (if_bra_delay),
.if_pc_add_4 (if_pc_add_4),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction),
.id_pc_add_4 (id_pc_add_4),
.id_instruction (id_instruction),
.id_pc (id_pc)
);
RegisterFile RegisterAccess (
.clock (clock),
.reset (reset),
.read_reg1 (id_rs),
.read_reg2 (id_rt),
.wb_rt_rd (wb_rt_rd),
.wb_write_data (wb_write_data),
.wb_reg_write (wb_reg_write),
.id_reg1_data (id_reg1_data),
.id_reg2_data (id_reg2_data)
);
Multiplex4 #(.WIDTH(32)) ID_RS_Forwarding_Mux (
.sel (id_fwd_rs_sel),
.in0 (id_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg1_end)
);
Multiplex4 #(.WIDTH(32)) ID_RT_Forwarding_Mux (
.sel (id_fwd_rt_sel),
.in0 (id_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg2_end)
);
Comparator Branch_Antecipation (
.A (id_reg1_end),
.B (id_reg2_end),
.Equals (id_cmp_eq)
);
SimpleAdder Branch_Address_Calculation (
.A (id_pc_add_4),
.B (id_immediate_left_shifted2),
.C (id_branch_address)
);
ControlUnity Control (
.id_stall (id_stall),
.id_opcode (id_opcode),
.id_funct (id_funct),
.id_cmp_eq (id_cmp_eq),
.if_flush (if_flush),
.id_signal_forwarding (id_signal_forwarding),
.id_pc_source_sel (id_pc_source_sel),
.id_sign_extend (id_sign_extend),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_branch_delay_slot (id_branch_delay_slot)
);
Forwarding_Hazard_Unity ForwardingHazardControl (
.sig_hazards (final_signal_forwarding),
.id_rs (id_rs),
.id_rt (id_rt),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_rt_rd (ex_rt_rd),
.me_rt_rd (me_rt_rd),
.wb_rt_rd (wb_rt_rd),
.ex_jump_link (ex_jump_link),
.ex_reg_write (ex_reg_write),
.me_reg_write (me_reg_write),
.wb_reg_write (wb_reg_write),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_fwd_rs_sel (id_fwd_rs_sel),
.id_fwd_rt_sel (id_fwd_rt_sel),
.ex_fwd_rs_sel (ex_fwd_rs_sel),
.ex_fwd_rt_sel (ex_fwd_rt_sel),
.me_write_data_fwd_sel (me_write_data_fwd_sel)
);
Instruction_Decode_Execute_Pipeline ID_EX (
.clock (clock),
.reset (reset),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_rs (id_rs),
.id_rt (id_rt),
.id_w_rs_ex (id_signal_forwarding[3]),
.id_n_rs_ex (id_signal_forwarding[2]),
.id_w_rt_ex (id_signal_forwarding[1]),
.id_n_rt_ex (id_signal_forwarding[0]),
.id_reg1_end (id_reg1_end),
.id_reg2_end (id_reg2_end),
.id_sign_extended_immediate (id_sign_extended_immediate[16:0]),
.id_pc (id_pc),
.ex_jump_link (ex_jump_link),
.ex_jump_link_reg_dst (ex_jump_link_reg_dst),
.ex_alu_src (ex_alu_src),
.ex_alu_op (ex_alu_op),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_w_rs_ex (ex_w_rs_ex),
.ex_n_rs_ex (ex_n_rs_ex),
.ex_w_rt_ex (ex_w_rt_ex),
.ex_n_rt_ex (ex_n_rt_ex),
.ex_reg1_data (ex_reg1_data),
.ex_reg2_data (ex_reg2_data),
.ex_sign_extended_immediate (ex_sign_extended_immediate),
.ex_rd (ex_rd),
.ex_shamt (ex_shamt),
.ex_pc (ex_pc)
);
Multiplex4 #(.WIDTH(32)) EX_RS_Forwarding_Mux (
.sel (ex_fwd_rs_sel),
.in0 (ex_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (ex_pc),
.out (ex_reg1_fwd)
);
Multiplex4 #(.WIDTH(32)) EX_RT_Forwarding_Mux (
.sel (ex_fwd_rt_sel),
.in0 (ex_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'h00000004),
.out (ex_reg2_fwd)
);
assign ex_data2_imm = (ex_alu_src) ? ex_sign_extended_immediate : ex_reg2_fwd;
Multiplex4 #(.WIDTH(5)) EX_Reg_Destination_Mux (
.sel (ex_jump_link_reg_dst),
.in0 (ex_rt),
.in1 (ex_rd),
.in2 (5'b11111),
.in3 (5'bxxxxx),
.out (ex_rt_rd)
);
ArithmeticLogicUnit ALU (
.A (ex_reg1_fwd),
.B (ex_data2_imm),
.operation (ex_alu_op),
.shamt (ex_shamt),
.result (ex_alu_result),
.overflow (ex_alu_overflow)
);
Execute_Memory_Pipeline EX_MEM (
.clock (clock),
.reset (reset),
.ex_stall (ex_stall),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_alu_result (ex_alu_result),
.ex_reg2_fwd (ex_reg2_fwd),
.ex_rt_rd (ex_rt_rd),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.me_reg_write (me_reg_write),
.me_alu_result (me_alu_result),
.me_data2_reg (me_data2_reg),
.me_rt_rd (me_rt_rd)
);
assign me_mem_write_data = (me_write_data_fwd_sel) ? wb_write_data : me_data2_reg;
DataMemoryInterface DataMemory(
.clock (clock),
.reset (reset),
.address (me_alu_result),
.mem_write (me_mem_write),
.data_write (me_mem_write_data),
.mem_read (me_mem_read),
.read_data (me_mem_read_data)
);
Memory_WriteBack_Pipeline MEM_WB (
.clock (clock),
.reset (reset),
.me_reg_write (me_reg_write),
.me_mem_to_reg (me_mem_to_reg),
.me_mem_read_data (me_mem_read_data),
.me_alu_result (me_alu_result),
.me_rt_rd (me_rt_rd),
.wb_reg_write (wb_reg_write),
.wb_mem_to_reg (wb_mem_to_reg),
.wb_data_memory (wb_data_memory),
.wb_alu_result (wb_alu_result),
.wb_rt_rd (wb_rt_rd)
);
assign wb_write_data = (wb_mem_to_reg) ? wb_data_memory : wb_alu_result;
endmodule | module Processor (
input clock,
input reset,
output [31:0] dif_instruction,
output [31:0] dif_pc_usable,
output [31:0] did_instruction,
output [31:0] did_pc_usable,
output [31:0] did_rt_data,
output [31:0] did_rs_data,
output [31:0] did_se_immediate,
output [4:0] did_rt,
output [4:0] did_rs,
output [31:0] dwb_write_data,
output [31:0] dex_alu_result,
output [31:0] dex_alu_a,
output [31:0] dex_alu_b,
output [4:0] dex_alu_op,
output [4:0] dme_rt_rd,
output [31:0] dme_data_mem,
output [31:0] dme_data_write_mem,
output [4:0] dwb_rt_rd,
output dif_flush,
output did_flush,
output dex_alu_src,
output [1:0] dex_fwd_rt_sel,
output [1:0] dex_fwd_rs_sel,
output dif_stall,
output did_stall,
output dwb_write_reg,
output dme_write_mem,
output dme_read_mem,
output did_branch_delay_slot
); |
parameter INSTRUCTIONS = "C:/Outros/Full Processor/MIPS32_Processor/Final Project/MIPS32_Full/Testing Codes/Exponential.txt";
wire if_stall;
wire if_flush;
wire [31:0] if_pc;
wire [31:0] if_pc_out;
wire [31:0] if_pc_usable;
wire [31:0] if_pc_add_4;
wire [31:0] if_instruction;
wire if_bra_delay;
wire id_stall;
wire id_reg_dst;
wire id_alu_src;
wire id_mem_write;
wire id_mem_read;
wire id_mem_to_reg;
wire id_reg_write;
wire id_cmp_eq;
wire id_sign_extend;
wire id_jump_link;
wire [4:0] id_alu_op;
wire id_branch_delay_slot;
wire [1:0] id_fwd_rs_sel;
wire [1:0] id_fwd_rt_sel;
wire id_w_rs_ex;
wire id_n_rs_ex;
wire id_w_rt_ex;
wire id_n_rt_ex;
wire [1:0] id_pc_source_sel;
wire [31:0] id_instruction;
wire [4:0] id_rs = id_instruction[25:21];
wire [4:0] id_rt = id_instruction[20:16];
wire [5:0] id_opcode = id_instruction[31:26];
wire [5:0] id_funct = id_instruction[5:0];
wire [31:0] id_reg1_data;
wire [31:0] id_reg1_end;
wire [31:0] id_reg2_data;
wire [31:0] id_reg2_end;
wire [31:0] id_immediate = id_instruction[15:0];
wire [31:0] id_pc_add_4;
wire [31:0] id_pc;
wire [31:0] id_jump_address = id_instruction[25:0];
wire [31:0] id_jump_address_usable = {id_pc_add_4[31:28], id_jump_address[25:0], 2'b00};
wire [31:0] id_sign_extended_immediate = (id_sign_extend & id_immediate[15]) ? {14'h3fff, id_immediate[15:0]} : {14'h0000, id_immediate[15:0]};
wire [31:0] id_immediate_left_shifted2 = {id_sign_extended_immediate[29:0], 2'b00};
wire [31:0] id_branch_address;
wire ex_stall;
wire ex_mem_read;
wire ex_mem_write;
wire ex_mem_to_reg;
wire ex_reg_write;
wire ex_alu_src;
wire ex_jump_link;
wire [1:0] ex_jump_link_reg_dst;
wire [4:0] ex_alu_op;
wire [1:0] ex_fwd_rs_sel;
wire [1:0] ex_fwd_rt_sel;
wire ex_w_rs_ex;
wire ex_n_rs_ex;
wire ex_w_rt_ex;
wire ex_n_rt_ex;
wire [4:0] ex_rs;
wire [4:0] ex_rt;
wire [4:0] ex_rd;
wire [4:0] ex_rt_rd;
wire [4:0] ex_shamt;
wire [31:0] ex_reg1_data;
wire [31:0] ex_reg1_fwd;
wire [31:0] ex_reg2_data;
wire [31:0] ex_reg2_fwd;
wire [31:0] ex_data2_imm;
wire [31:0] ex_sign_extended_immediate;
wire [31:0] ex_alu_result;
wire [31:0] ex_pc;
wire ex_alu_overflow;
wire me_mem_read;
wire me_mem_write;
wire me_mem_to_reg;
wire me_reg_write;
wire me_write_data_fwd_sel;
wire [4:0] me_rt_rd;
wire [31:0] me_alu_result;
wire [31:0] me_data2_reg;
wire [31:0] me_pc;
wire [31:0] me_mem_read_data;
wire [31:0] me_mem_write_data;
wire wb_mem_to_reg;
wire wb_reg_write;
wire [4:0] wb_rt_rd;
wire [31:0] wb_data_memory;
wire [31:0] wb_alu_result;
wire [31:0] wb_write_data;
wire [7:0] id_signal_forwarding;
wire [7:0] final_signal_forwarding;
assign final_signal_forwarding = {id_signal_forwarding[7:4], ex_w_rs_ex, ex_n_rs_ex, ex_w_rt_ex, ex_n_rt_ex};
assign if_bra_delay = id_branch_delay_slot;
assign dif_instruction = if_instruction;
assign dif_pc_usable = if_pc_add_4;
assign did_instruction = id_instruction;
assign did_pc_usable = id_pc_add_4;
assign did_rs_data = id_reg1_end;
assign did_rt_data = id_reg2_end;
assign did_rt = id_rt;
assign did_rs = id_rs;
assign did_se_immediate = id_sign_extended_immediate;
assign dwb_rt_rd = wb_rt_rd;
assign dwb_write_data = wb_write_data;
assign dex_alu_result = ex_alu_result;
assign dex_alu_a = ex_reg1_fwd;
assign dex_alu_b = ex_data2_imm;
assign dex_alu_op = ex_alu_op;
assign dme_rt_rd = me_rt_rd;
assign dme_data_mem = me_mem_read_data;
assign dme_data_write_mem = me_mem_write_data;
assign dif_flush = if_flush;
assign dex_alu_src = ex_alu_src;
assign dex_fwd_rt_sel = ex_fwd_rt_sel;
assign dex_fwd_rs_sel = ex_fwd_rs_sel;
assign dif_stall = if_stall;
assign did_stall = id_stall;
assign dwb_write_reg = wb_reg_write;
assign dme_write_mem = me_mem_write;
assign dme_read_mem = me_mem_read;
assign did_branch_delay_slot = if_bra_delay;
Multiplex4 #(.WIDTH(32)) PC_Source_Selection_Mux (
.sel (id_pc_source_sel),
.in0 (if_pc_add_4),
.in1 (id_jump_address_usable),
.in2 (id_branch_address),
.in3 (id_reg1_end),
.out (if_pc_out)
);
PC_Latch PC (
.clock (clock),
.reset (reset),
.enable (~(if_stall | id_stall)),
.data (if_pc_out),
.value (if_pc_usable)
);
InstructionMemoryInterface #(.INSTRUCTION_FILE(INSTRUCTIONS)) instruction_memory (
.if_stall (if_stall),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction)
);
SimpleAdder PC_Increment (
.A (if_pc_usable),
.B (32'h00000004),
.C (if_pc_add_4)
);
Instruction_Fetch_Decode_Pipeline IF_ID (
.clock (clock),
.reset (reset),
.if_flush (if_flush),
.if_stall (if_stall),
.id_stall (id_stall),
.if_bra_delay (if_bra_delay),
.if_pc_add_4 (if_pc_add_4),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction),
.id_pc_add_4 (id_pc_add_4),
.id_instruction (id_instruction),
.id_pc (id_pc)
);
RegisterFile RegisterAccess (
.clock (clock),
.reset (reset),
.read_reg1 (id_rs),
.read_reg2 (id_rt),
.wb_rt_rd (wb_rt_rd),
.wb_write_data (wb_write_data),
.wb_reg_write (wb_reg_write),
.id_reg1_data (id_reg1_data),
.id_reg2_data (id_reg2_data)
);
Multiplex4 #(.WIDTH(32)) ID_RS_Forwarding_Mux (
.sel (id_fwd_rs_sel),
.in0 (id_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg1_end)
);
Multiplex4 #(.WIDTH(32)) ID_RT_Forwarding_Mux (
.sel (id_fwd_rt_sel),
.in0 (id_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg2_end)
);
Comparator Branch_Antecipation (
.A (id_reg1_end),
.B (id_reg2_end),
.Equals (id_cmp_eq)
);
SimpleAdder Branch_Address_Calculation (
.A (id_pc_add_4),
.B (id_immediate_left_shifted2),
.C (id_branch_address)
);
ControlUnity Control (
.id_stall (id_stall),
.id_opcode (id_opcode),
.id_funct (id_funct),
.id_cmp_eq (id_cmp_eq),
.if_flush (if_flush),
.id_signal_forwarding (id_signal_forwarding),
.id_pc_source_sel (id_pc_source_sel),
.id_sign_extend (id_sign_extend),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_branch_delay_slot (id_branch_delay_slot)
);
Forwarding_Hazard_Unity ForwardingHazardControl (
.sig_hazards (final_signal_forwarding),
.id_rs (id_rs),
.id_rt (id_rt),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_rt_rd (ex_rt_rd),
.me_rt_rd (me_rt_rd),
.wb_rt_rd (wb_rt_rd),
.ex_jump_link (ex_jump_link),
.ex_reg_write (ex_reg_write),
.me_reg_write (me_reg_write),
.wb_reg_write (wb_reg_write),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_fwd_rs_sel (id_fwd_rs_sel),
.id_fwd_rt_sel (id_fwd_rt_sel),
.ex_fwd_rs_sel (ex_fwd_rs_sel),
.ex_fwd_rt_sel (ex_fwd_rt_sel),
.me_write_data_fwd_sel (me_write_data_fwd_sel)
);
Instruction_Decode_Execute_Pipeline ID_EX (
.clock (clock),
.reset (reset),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_rs (id_rs),
.id_rt (id_rt),
.id_w_rs_ex (id_signal_forwarding[3]),
.id_n_rs_ex (id_signal_forwarding[2]),
.id_w_rt_ex (id_signal_forwarding[1]),
.id_n_rt_ex (id_signal_forwarding[0]),
.id_reg1_end (id_reg1_end),
.id_reg2_end (id_reg2_end),
.id_sign_extended_immediate (id_sign_extended_immediate[16:0]),
.id_pc (id_pc),
.ex_jump_link (ex_jump_link),
.ex_jump_link_reg_dst (ex_jump_link_reg_dst),
.ex_alu_src (ex_alu_src),
.ex_alu_op (ex_alu_op),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_w_rs_ex (ex_w_rs_ex),
.ex_n_rs_ex (ex_n_rs_ex),
.ex_w_rt_ex (ex_w_rt_ex),
.ex_n_rt_ex (ex_n_rt_ex),
.ex_reg1_data (ex_reg1_data),
.ex_reg2_data (ex_reg2_data),
.ex_sign_extended_immediate (ex_sign_extended_immediate),
.ex_rd (ex_rd),
.ex_shamt (ex_shamt),
.ex_pc (ex_pc)
);
Multiplex4 #(.WIDTH(32)) EX_RS_Forwarding_Mux (
.sel (ex_fwd_rs_sel),
.in0 (ex_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (ex_pc),
.out (ex_reg1_fwd)
);
Multiplex4 #(.WIDTH(32)) EX_RT_Forwarding_Mux (
.sel (ex_fwd_rt_sel),
.in0 (ex_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'h00000004),
.out (ex_reg2_fwd)
);
assign ex_data2_imm = (ex_alu_src) ? ex_sign_extended_immediate : ex_reg2_fwd;
Multiplex4 #(.WIDTH(5)) EX_Reg_Destination_Mux (
.sel (ex_jump_link_reg_dst),
.in0 (ex_rt),
.in1 (ex_rd),
.in2 (5'b11111),
.in3 (5'bxxxxx),
.out (ex_rt_rd)
);
ArithmeticLogicUnit ALU (
.A (ex_reg1_fwd),
.B (ex_data2_imm),
.operation (ex_alu_op),
.shamt (ex_shamt),
.result (ex_alu_result),
.overflow (ex_alu_overflow)
);
Execute_Memory_Pipeline EX_MEM (
.clock (clock),
.reset (reset),
.ex_stall (ex_stall),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_alu_result (ex_alu_result),
.ex_reg2_fwd (ex_reg2_fwd),
.ex_rt_rd (ex_rt_rd),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.me_reg_write (me_reg_write),
.me_alu_result (me_alu_result),
.me_data2_reg (me_data2_reg),
.me_rt_rd (me_rt_rd)
);
assign me_mem_write_data = (me_write_data_fwd_sel) ? wb_write_data : me_data2_reg;
DataMemoryInterface DataMemory(
.clock (clock),
.reset (reset),
.address (me_alu_result),
.mem_write (me_mem_write),
.data_write (me_mem_write_data),
.mem_read (me_mem_read),
.read_data (me_mem_read_data)
);
Memory_WriteBack_Pipeline MEM_WB (
.clock (clock),
.reset (reset),
.me_reg_write (me_reg_write),
.me_mem_to_reg (me_mem_to_reg),
.me_mem_read_data (me_mem_read_data),
.me_alu_result (me_alu_result),
.me_rt_rd (me_rt_rd),
.wb_reg_write (wb_reg_write),
.wb_mem_to_reg (wb_mem_to_reg),
.wb_data_memory (wb_data_memory),
.wb_alu_result (wb_alu_result),
.wb_rt_rd (wb_rt_rd)
);
assign wb_write_data = (wb_mem_to_reg) ? wb_data_memory : wb_alu_result;
endmodule | 0 |
142,609 | data/full_repos/permissive/99544345/clkgen.sv | 99,544,345 | clkgen.sv | sv | 33 | 74 | [] | [] | [] | null | line:26: before: "hw_top" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/99544345/clkgen.sv:20: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk0 = ~clk0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/99544345/clkgen.sv:21: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk1 = ~clk1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/99544345/clkgen.sv:22: Unsupported: Ignoring delay on this delayed statement.\nalways #3 clk2 = ~clk2;\n ^\n%Error: data/full_repos/permissive/99544345/clkgen.sv:26: Unsupported: Verilog 1995 force\n force hw_top.u_dut.clk0 = clk0;\n ^~~~~\n%Error: data/full_repos/permissive/99544345/clkgen.sv:27: Unsupported: Verilog 1995 force\n force hw_top.u_dut.clk1 = clk1;\n ^~~~~\n%Error: data/full_repos/permissive/99544345/clkgen.sv:28: Unsupported: Verilog 1995 force\n force hw_top.u_dut.clk2 = clk2;\n ^~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 314,870 | module | module clkgen;
reg clk0=0;
reg clk1=0;
reg clk2=0;
always #1 clk0 = ~clk0;
always #2 clk1 = ~clk1;
always #3 clk2 = ~clk2;
initial
begin
force hw_top.u_dut.clk0 = clk0;
force hw_top.u_dut.clk1 = clk1;
force hw_top.u_dut.clk2 = clk2;
end
endmodule | module clkgen; |
reg clk0=0;
reg clk1=0;
reg clk2=0;
always #1 clk0 = ~clk0;
always #2 clk1 = ~clk1;
always #3 clk2 = ~clk2;
initial
begin
force hw_top.u_dut.clk0 = clk0;
force hw_top.u_dut.clk1 = clk1;
force hw_top.u_dut.clk2 = clk2;
end
endmodule | 1 |
142,612 | data/full_repos/permissive/99544345/hw_top.sv | 99,544,345 | hw_top.sv | sv | 22 | 74 | [] | [] | [] | [(14, 21)] | null | null | 1: b"%Error: data/full_repos/permissive/99544345/hw_top.sv:16: Cannot find file containing module: 'memBFM'\nmemBFM u_membfm();\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/99544345,data/full_repos/permissive/99544345/memBFM\n data/full_repos/permissive/99544345,data/full_repos/permissive/99544345/memBFM.v\n data/full_repos/permissive/99544345,data/full_repos/permissive/99544345/memBFM.sv\n memBFM\n memBFM.v\n memBFM.sv\n obj_dir/memBFM\n obj_dir/memBFM.v\n obj_dir/memBFM.sv\n%Error: data/full_repos/permissive/99544345/hw_top.sv:17: Cannot find file containing module: 'dut'\ndut u_dut();\n^~~\n%Error: data/full_repos/permissive/99544345/hw_top.sv:19: Cannot find file containing module: 'clkgen'\nclkgen u_clkgen();\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 314,875 | module | module hw_top;
memBFM u_membfm();
dut u_dut();
clkgen u_clkgen();
endmodule | module hw_top; |
memBFM u_membfm();
dut u_dut();
clkgen u_clkgen();
endmodule | 1 |