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data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v

Pipe_CPU_1.v

v

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[]

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'utf-8' codec can't decode byte 0xa8 in position 462: invalid start byte

1: b"%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:82: Cannot find file containing module: 'MUX_2to1'\nMUX_2to1 #(.size(32)) Mux1(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98702386/CPU,data/full_repos/permissive/98702386/MUX_2to1\n data/full_repos/permissive/98702386/CPU,data/full_repos/permissive/98702386/MUX_2to1.v\n data/full_repos/permissive/98702386/CPU,data/full_repos/permissive/98702386/MUX_2to1.sv\n MUX_2to1\n MUX_2to1.v\n MUX_2to1.sv\n obj_dir/MUX_2to1\n obj_dir/MUX_2to1.v\n obj_dir/MUX_2to1.sv\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:89: Cannot find file containing module: 'ProgramCounter'\nProgramCounter PC(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:97: Cannot find file containing module: 'Instr_Memory'\nInstr_Memory IM(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:102: Cannot find file containing module: 'Adder'\nAdder Add_pc(\n^~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:109: Cannot find file containing module: 'Stall_Pipe_Reg'\nStall_Pipe_Reg #(.size(64)) IF_ID( \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:119: Cannot find file containing module: 'Hazard_Detection_Unit'\nHazard_Detection_Unit Hazard(\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:132: Cannot find file containing module: 'Reg_File'\nReg_File RF(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:144: Cannot find file containing module: 'Decoder'\nDecoder Control(\n^~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:156: Cannot find file containing module: 'Sign_Extend'\nSign_Extend Sign_Extend(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:161: Cannot find file containing module: 'Pipe_Reg'\nPipe_Reg #(.size(153)) ID_EX(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:171: Cannot find file containing module: 'Adder'\nAdder Add_branch_addr(\n^~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:176: Cannot find file containing module: 'Shift_Left_Two_32'\nShift_Left_Two_32 shift2(\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:181: Cannot find file containing module: 'Forwarding_Unit'\nForwarding_Unit Forwarding_Unit(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:192: Cannot find file containing module: 'ALU'\nALU ALU(\n^~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:200: Cannot find file containing module: 'ALU_Ctrl'\nALU_Ctrl ALU_Control(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:208: Cannot find file containing module: 'MUX_2to1'\nMUX_2to1 #(.size(32)) MUX_ALU_Src1(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:215: Cannot find file containing module: 'MUX_2to1'\nMUX_2to1 #(.size(32)) MUX_ALU_Src2(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:222: Cannot find file containing module: 'MUX_2to1'\nMUX_2to1 #(.size(5)) RDRT_Mux(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:229: Cannot find file containing module: 'MUX_3to1'\nMUX_3to1 #(.size(32)) Forward_A(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:237: Cannot find file containing module: 'MUX_3to1'\nMUX_3to1 #(.size(32)) Forward_B(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:245: Cannot find file containing module: 'Pipe_Reg'\nPipe_Reg #(.size(107)) EX_MEM(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:253: Cannot find file containing module: 'Data_Memory'\nData_Memory DM(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:262: Cannot find file containing module: 'Pipe_Reg'\nPipe_Reg #(.size(71)) MEM_WB(\n^~~~~~~~\n%Error: data/full_repos/permissive/98702386/CPU/Pipe_CPU_1.v:270: Cannot find file containing module: 'MUX_2to1'\nMUX_2to1 #(.size(32)) Mux3(\n^~~~~~~~\n%Error: Exiting due to 24 error(s)\n"

module

module Pipe_CPU_1( clk_i, rst_i ); input clk_i; input rst_i; wire [31:0] if_pc_in_i, if_pc_out_o, if_instr_o, if_Add_pc_sum_o; wire check; assign check = (~PCSrc && mem_Branch)? 1 : 0; wire [31:0] if_pc_in_ii; assign if_pc_in_ii = (check)? if_pc_in_i-32'd4 : if_pc_in_i; wire [31:0] id_instr_o, id_Add_pc_sum_o; wire [31:0] id_rs_o, id_rt_o; wire id_RegWrite, id_ALUSrc, id_RegDst, id_Branch, id_MemRead, id_MemWrite, id_MemtoReg; wire [2:0] id_ALU_op; wire [31:0] id_sign_extend_o; wire PCWrite, ifid_Write, if_flush; wire [4:0] ex_rs, ex_rt, ex_rd; wire [31:0] ex_Add_pc_sum_o, ex_branch_addr; wire [31:0] ex_rs_o, ex_rt_o; wire ex_RegWrite, ex_ALUSrc, ex_RegDst, ex_Branch, ex_MemRead, ex_MemWrite, ex_MemtoReg; wire [2:0] ex_ALU_op; wire [31:0] ex_sign_extend_o, ex_se_shift2; wire [31:0] ex_sign_extend_oo; assign ex_sign_extend_oo = (ex_ALU_op==3'b101)?(ex_sign_extend_o & 32'b00000000000000001111111111111111) : ex_sign_extend_o; wire [31:0] ALUsrc1, ALU_Src2; wire [4:0] ex_write_address; wire [31:0] ex_ALU_result; wire ex_zero; wire [3:0] ex_ALUCtrl; wire ex_shamt_o, ex_bne_beq_o, ex_is_nop; wire [31:0] ex_shamt_to32; assign ex_shamt_to32 = {27'b0,ex_sign_extend_o[10:6]}; wire zero; assign zero = (ex_bne_beq_o)? ex_zero : ~ex_zero; wire ex_RegWritee; assign ex_RegWritee = (ex_is_nop)? 0 : ex_RegWrite; wire [31:0] forwardA_data_o, forwardB_data_o; wire [1:0] forwardA, forwardB; wire mem_RegWrite, mem_Branch, mem_MemRead, mem_MemWrite, mem_MemtoReg; wire [31:0] mem_branch_addr, mem_ALU_result, mem_rt_o; wire [4:0] mem_write_address; wire mem_zero; wire [31:0] mem_DM_o; wire PCSrc; assign PCSrc = (mem_zero & mem_Branch); wire wb_MemtoReg, wb_RegWrite; wire [31:0] wb_ALU_result, wb_DM_o; wire [4:0] wb_write_address; wire [31:0] wb_data_o; MUX_2to1 #(.size(32)) Mux1( .data0_i(if_Add_pc_sum_o), .data1_i(mem_branch_addr), .select_i(PCSrc), .data_o(if_pc_in_i) ); ProgramCounter PC( .clk_i(clk_i), .rst_i(rst_i), .pc_in_i(if_pc_in_ii), .PCWrite(PCWrite), .pc_out_o(if_pc_out_o) ); Instr_Memory IM( .pc_addr_i(if_pc_out_o), .instr_o(if_instr_o) ); Adder Add_pc( .src1_i(if_pc_out_o), .src2_i(32'd4), .sum_o(if_Add_pc_sum_o) ); Stall_Pipe_Reg #(.size(64)) IF_ID( .clk_i(clk_i), .rst_i(rst_i), .ifid_Write(ifid_Write), .if_flush(if_flush), .data_i({if_Add_pc_sum_o, if_instr_o}), .data_o({id_Add_pc_sum_o, id_instr_o}) ); Hazard_Detection_Unit Hazard( .idex_MemRead(ex_MemRead), .idex_rt(ex_rt), .ifid_rs(id_instr_o[25:21]), .ifid_rt(id_instr_o[20:16]), .PCWrite(PCWrite), .ifid_Write(ifid_Write), .ex_branch(ex_Branch), .id_branch(id_Branch), .if_flush(if_flush), .mem_branch(mem_Branch) ); Reg_File RF( .clk_i(clk_i), .rst_i(rst_i), .RSaddr_i(id_instr_o[25:21]), .RTaddr_i(id_instr_o[20:16]), .RDaddr_i(wb_write_address), .RDdata_i(wb_data_o), .RegWrite_i(wb_RegWrite), .RSdata_o(id_rs_o), .RTdata_o(id_rt_o) ); Decoder Control( .instr_op_i(id_instr_o[31:26]), .RegWrite_o(id_RegWrite), .ALU_op_o(id_ALU_op), .ALUSrc_o(id_ALUSrc), .RegDst_o(id_RegDst), .Branch_o(id_Branch), .MemRead_o(id_MemRead), .MemWrite_o(id_MemWrite), .MemToReg_o(id_MemtoReg) ); Sign_Extend Sign_Extend( .data_i(id_instr_o[15:0]), .data_o(id_sign_extend_o) ); Pipe_Reg #(.size(153)) ID_EX( .clk_i(clk_i), .rst_i(rst_i), .data_i({id_RegWrite, id_ALU_op, id_ALUSrc, id_RegDst, id_Branch, id_MemRead, id_MemWrite, id_MemtoReg, id_Add_pc_sum_o, id_rs_o, id_rt_o, id_sign_extend_o, id_instr_o[25:21], id_instr_o[20:16], id_instr_o[15:11]}), .data_o({ex_RegWrite, ex_ALU_op, ex_ALUSrc, ex_RegDst, ex_Branch, ex_MemRead, ex_MemWrite, ex_MemtoReg, ex_Add_pc_sum_o, ex_rs_o, ex_rt_o, ex_sign_extend_o, ex_rs, ex_rt, ex_rd}) ); Adder Add_branch_addr( .src1_i(ex_Add_pc_sum_o), .src2_i(ex_se_shift2), .sum_o(ex_branch_addr) ); Shift_Left_Two_32 shift2( .data_i(ex_sign_extend_o), .data_o(ex_se_shift2) ); Forwarding_Unit Forwarding_Unit( .exmem_rd(mem_write_address), .idex_rs(ex_rs), .idex_rt(ex_rt), .memwb_rd(wb_write_address), .exmem_RegWrite(mem_RegWrite), .memwb_RegWrite(wb_RegWrite), .forwardA(forwardA), .forwardB(forwardB) ); ALU ALU( .src1_i(ALUsrc1), .src2_i(ALU_Src2), .ctrl_i(ex_ALUCtrl), .result_o(ex_ALU_result), .zero_o(ex_zero) ); ALU_Ctrl ALU_Control( .funct_i(ex_sign_extend_o[5:0]), .ALUOp_i(ex_ALU_op), .ALUCtrl_o(ex_ALUCtrl), .shamt_o(ex_shamt_o), .bne_beq_o(ex_bne_beq_o), .is_nop(ex_is_nop) ); MUX_2to1 #(.size(32)) MUX_ALU_Src1( .data0_i(forwardA_data_o), .data1_i(ex_shamt_to32), .select_i(ex_shamt_o), .data_o(ALUsrc1) ); MUX_2to1 #(.size(32)) MUX_ALU_Src2( .data0_i(forwardB_data_o), .data1_i(ex_sign_extend_oo), .select_i(ex_ALUSrc), .data_o(ALU_Src2) ); MUX_2to1 #(.size(5)) RDRT_Mux( .data0_i(ex_rt), .data1_i(ex_rd), .select_i(ex_RegDst), .data_o(ex_write_address) ); MUX_3to1 #(.size(32)) Forward_A( .data0_i(ex_rs_o), .data1_i(wb_data_o), .data2_i(mem_ALU_result), .select_i(forwardA), .data_o(forwardA_data_o) ); MUX_3to1 #(.size(32)) Forward_B( .data0_i(ex_rt_o), .data1_i(wb_data_o), .data2_i(mem_ALU_result), .select_i(forwardB), .data_o(forwardB_data_o) ); Pipe_Reg #(.size(107)) EX_MEM( .clk_i(clk_i), .rst_i(rst_i), .data_i({ex_RegWritee, ex_Branch, ex_MemRead, ex_MemWrite, ex_MemtoReg, ex_branch_addr, ex_ALU_result, zero, forwardB_data_o, ex_write_address}), .data_o({mem_RegWrite, mem_Branch, mem_MemRead, mem_MemWrite, mem_MemtoReg, mem_branch_addr, mem_ALU_result, mem_zero, mem_rt_o, mem_write_address}) ); Data_Memory DM( .clk_i(clk_i), .addr_i(mem_ALU_result), .data_i(mem_rt_o), .MemRead_i(mem_MemRead), .MemWrite_i(mem_MemWrite), .data_o(mem_DM_o) ); Pipe_Reg #(.size(71)) MEM_WB( .clk_i(clk_i), .rst_i(rst_i), .data_i({mem_MemtoReg, mem_RegWrite, mem_DM_o, mem_ALU_result, mem_write_address}), .data_o({wb_MemtoReg, wb_RegWrite, wb_DM_o, wb_ALU_result, wb_write_address}) ); MUX_2to1 #(.size(32)) Mux3( .data0_i(wb_ALU_result), .data1_i(wb_DM_o), .select_i(wb_MemtoReg), .data_o(wb_data_o) ); endmodule

module Pipe_CPU_1( clk_i, rst_i );

input clk_i; input rst_i; wire [31:0] if_pc_in_i, if_pc_out_o, if_instr_o, if_Add_pc_sum_o; wire check; assign check = (~PCSrc && mem_Branch)? 1 : 0; wire [31:0] if_pc_in_ii; assign if_pc_in_ii = (check)? if_pc_in_i-32'd4 : if_pc_in_i; wire [31:0] id_instr_o, id_Add_pc_sum_o; wire [31:0] id_rs_o, id_rt_o; wire id_RegWrite, id_ALUSrc, id_RegDst, id_Branch, id_MemRead, id_MemWrite, id_MemtoReg; wire [2:0] id_ALU_op; wire [31:0] id_sign_extend_o; wire PCWrite, ifid_Write, if_flush; wire [4:0] ex_rs, ex_rt, ex_rd; wire [31:0] ex_Add_pc_sum_o, ex_branch_addr; wire [31:0] ex_rs_o, ex_rt_o; wire ex_RegWrite, ex_ALUSrc, ex_RegDst, ex_Branch, ex_MemRead, ex_MemWrite, ex_MemtoReg; wire [2:0] ex_ALU_op; wire [31:0] ex_sign_extend_o, ex_se_shift2; wire [31:0] ex_sign_extend_oo; assign ex_sign_extend_oo = (ex_ALU_op==3'b101)?(ex_sign_extend_o & 32'b00000000000000001111111111111111) : ex_sign_extend_o; wire [31:0] ALUsrc1, ALU_Src2; wire [4:0] ex_write_address; wire [31:0] ex_ALU_result; wire ex_zero; wire [3:0] ex_ALUCtrl; wire ex_shamt_o, ex_bne_beq_o, ex_is_nop; wire [31:0] ex_shamt_to32; assign ex_shamt_to32 = {27'b0,ex_sign_extend_o[10:6]}; wire zero; assign zero = (ex_bne_beq_o)? ex_zero : ~ex_zero; wire ex_RegWritee; assign ex_RegWritee = (ex_is_nop)? 0 : ex_RegWrite; wire [31:0] forwardA_data_o, forwardB_data_o; wire [1:0] forwardA, forwardB; wire mem_RegWrite, mem_Branch, mem_MemRead, mem_MemWrite, mem_MemtoReg; wire [31:0] mem_branch_addr, mem_ALU_result, mem_rt_o; wire [4:0] mem_write_address; wire mem_zero; wire [31:0] mem_DM_o; wire PCSrc; assign PCSrc = (mem_zero & mem_Branch); wire wb_MemtoReg, wb_RegWrite; wire [31:0] wb_ALU_result, wb_DM_o; wire [4:0] wb_write_address; wire [31:0] wb_data_o; MUX_2to1 #(.size(32)) Mux1( .data0_i(if_Add_pc_sum_o), .data1_i(mem_branch_addr), .select_i(PCSrc), .data_o(if_pc_in_i) ); ProgramCounter PC( .clk_i(clk_i), .rst_i(rst_i), .pc_in_i(if_pc_in_ii), .PCWrite(PCWrite), .pc_out_o(if_pc_out_o) ); Instr_Memory IM( .pc_addr_i(if_pc_out_o), .instr_o(if_instr_o) ); Adder Add_pc( .src1_i(if_pc_out_o), .src2_i(32'd4), .sum_o(if_Add_pc_sum_o) ); Stall_Pipe_Reg #(.size(64)) IF_ID( .clk_i(clk_i), .rst_i(rst_i), .ifid_Write(ifid_Write), .if_flush(if_flush), .data_i({if_Add_pc_sum_o, if_instr_o}), .data_o({id_Add_pc_sum_o, id_instr_o}) ); Hazard_Detection_Unit Hazard( .idex_MemRead(ex_MemRead), .idex_rt(ex_rt), .ifid_rs(id_instr_o[25:21]), .ifid_rt(id_instr_o[20:16]), .PCWrite(PCWrite), .ifid_Write(ifid_Write), .ex_branch(ex_Branch), .id_branch(id_Branch), .if_flush(if_flush), .mem_branch(mem_Branch) ); Reg_File RF( .clk_i(clk_i), .rst_i(rst_i), .RSaddr_i(id_instr_o[25:21]), .RTaddr_i(id_instr_o[20:16]), .RDaddr_i(wb_write_address), .RDdata_i(wb_data_o), .RegWrite_i(wb_RegWrite), .RSdata_o(id_rs_o), .RTdata_o(id_rt_o) ); Decoder Control( .instr_op_i(id_instr_o[31:26]), .RegWrite_o(id_RegWrite), .ALU_op_o(id_ALU_op), .ALUSrc_o(id_ALUSrc), .RegDst_o(id_RegDst), .Branch_o(id_Branch), .MemRead_o(id_MemRead), .MemWrite_o(id_MemWrite), .MemToReg_o(id_MemtoReg) ); Sign_Extend Sign_Extend( .data_i(id_instr_o[15:0]), .data_o(id_sign_extend_o) ); Pipe_Reg #(.size(153)) ID_EX( .clk_i(clk_i), .rst_i(rst_i), .data_i({id_RegWrite, id_ALU_op, id_ALUSrc, id_RegDst, id_Branch, id_MemRead, id_MemWrite, id_MemtoReg, id_Add_pc_sum_o, id_rs_o, id_rt_o, id_sign_extend_o, id_instr_o[25:21], id_instr_o[20:16], id_instr_o[15:11]}), .data_o({ex_RegWrite, ex_ALU_op, ex_ALUSrc, ex_RegDst, ex_Branch, ex_MemRead, ex_MemWrite, ex_MemtoReg, ex_Add_pc_sum_o, ex_rs_o, ex_rt_o, ex_sign_extend_o, ex_rs, ex_rt, ex_rd}) ); Adder Add_branch_addr( .src1_i(ex_Add_pc_sum_o), .src2_i(ex_se_shift2), .sum_o(ex_branch_addr) ); Shift_Left_Two_32 shift2( .data_i(ex_sign_extend_o), .data_o(ex_se_shift2) ); Forwarding_Unit Forwarding_Unit( .exmem_rd(mem_write_address), .idex_rs(ex_rs), .idex_rt(ex_rt), .memwb_rd(wb_write_address), .exmem_RegWrite(mem_RegWrite), .memwb_RegWrite(wb_RegWrite), .forwardA(forwardA), .forwardB(forwardB) ); ALU ALU( .src1_i(ALUsrc1), .src2_i(ALU_Src2), .ctrl_i(ex_ALUCtrl), .result_o(ex_ALU_result), .zero_o(ex_zero) ); ALU_Ctrl ALU_Control( .funct_i(ex_sign_extend_o[5:0]), .ALUOp_i(ex_ALU_op), .ALUCtrl_o(ex_ALUCtrl), .shamt_o(ex_shamt_o), .bne_beq_o(ex_bne_beq_o), .is_nop(ex_is_nop) ); MUX_2to1 #(.size(32)) MUX_ALU_Src1( .data0_i(forwardA_data_o), .data1_i(ex_shamt_to32), .select_i(ex_shamt_o), .data_o(ALUsrc1) ); MUX_2to1 #(.size(32)) MUX_ALU_Src2( .data0_i(forwardB_data_o), .data1_i(ex_sign_extend_oo), .select_i(ex_ALUSrc), .data_o(ALU_Src2) ); MUX_2to1 #(.size(5)) RDRT_Mux( .data0_i(ex_rt), .data1_i(ex_rd), .select_i(ex_RegDst), .data_o(ex_write_address) ); MUX_3to1 #(.size(32)) Forward_A( .data0_i(ex_rs_o), .data1_i(wb_data_o), .data2_i(mem_ALU_result), .select_i(forwardA), .data_o(forwardA_data_o) ); MUX_3to1 #(.size(32)) Forward_B( .data0_i(ex_rt_o), .data1_i(wb_data_o), .data2_i(mem_ALU_result), .select_i(forwardB), .data_o(forwardB_data_o) ); Pipe_Reg #(.size(107)) EX_MEM( .clk_i(clk_i), .rst_i(rst_i), .data_i({ex_RegWritee, ex_Branch, ex_MemRead, ex_MemWrite, ex_MemtoReg, ex_branch_addr, ex_ALU_result, zero, forwardB_data_o, ex_write_address}), .data_o({mem_RegWrite, mem_Branch, mem_MemRead, mem_MemWrite, mem_MemtoReg, mem_branch_addr, mem_ALU_result, mem_zero, mem_rt_o, mem_write_address}) ); Data_Memory DM( .clk_i(clk_i), .addr_i(mem_ALU_result), .data_i(mem_rt_o), .MemRead_i(mem_MemRead), .MemWrite_i(mem_MemWrite), .data_o(mem_DM_o) ); Pipe_Reg #(.size(71)) MEM_WB( .clk_i(clk_i), .rst_i(rst_i), .data_i({mem_MemtoReg, mem_RegWrite, mem_DM_o, mem_ALU_result, mem_write_address}), .data_o({wb_MemtoReg, wb_RegWrite, wb_DM_o, wb_ALU_result, wb_write_address}) ); MUX_2to1 #(.size(32)) Mux3( .data0_i(wb_ALU_result), .data1_i(wb_DM_o), .select_i(wb_MemtoReg), .data_o(wb_data_o) ); endmodule

data/full_repos/permissive/98702386/CPU/Pipe_Reg.v

Pipe_Reg.v

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'utf-8' codec can't decode byte 0xa8 in position 465: invalid start byte

1: b'%Warning-LITENDIAN: data/full_repos/permissive/98702386/CPU/Pipe_Reg.v:23: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [size-1: 0] data_i;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/98702386/CPU/Pipe_Reg.v:24: Little bit endian vector: MSB < LSB of bit range: -1:0\noutput reg [size-1: 0] data_o;\n ^\n%Error: Exiting due to 2 warning(s)\n'

module

module Pipe_Reg( clk_i, rst_i, data_i, data_o ); parameter size = 0; input clk_i; input rst_i; input [size-1: 0] data_i; output reg [size-1: 0] data_o; always @(posedge clk_i) begin if(~rst_i) data_o <= 0; else data_o <= data_i; end endmodule

module Pipe_Reg( clk_i, rst_i, data_i, data_o );

parameter size = 0; input clk_i; input rst_i; input [size-1: 0] data_i; output reg [size-1: 0] data_o; always @(posedge clk_i) begin if(~rst_i) data_o <= 0; else data_o <= data_i; end endmodule

data/full_repos/permissive/98702386/CPU/ProgramCounter.v

ProgramCounter.v

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'utf-8' codec can't decode byte 0xa8 in position 454: invalid start byte

data/verilator_xmls/cece18c0-5832-4d12-85be-36075569acfb.xml

module

module ProgramCounter( clk_i, rst_i, pc_in_i, pc_out_o, PCWrite ); input clk_i; input rst_i; input [32-1:0] pc_in_i; input PCWrite; output [32-1:0] pc_out_o; reg [32-1:0] pc_out_o; reg [32-1:0] pc_stall; always @(posedge clk_i) begin if(~rst_i)begin pc_out_o <= 0; pc_stall <= 0; end else if(PCWrite)begin pc_out_o <= pc_in_i; pc_stall <= pc_in_i; end else begin pc_out_o <= pc_stall; pc_stall <= pc_stall; end end endmodule

module ProgramCounter( clk_i, rst_i, pc_in_i, pc_out_o, PCWrite );

input clk_i; input rst_i; input [32-1:0] pc_in_i; input PCWrite; output [32-1:0] pc_out_o; reg [32-1:0] pc_out_o; reg [32-1:0] pc_stall; always @(posedge clk_i) begin if(~rst_i)begin pc_out_o <= 0; pc_stall <= 0; end else if(PCWrite)begin pc_out_o <= pc_in_i; pc_stall <= pc_in_i; end else begin pc_out_o <= pc_stall; pc_stall <= pc_stall; end end endmodule

data/full_repos/permissive/98702386/CPU/Reg_File.v

Reg_File.v

v

[]

[]

[]

[Errno 2] No such file or directory: 'preprocess.output'

data/verilator_xmls/51c92917-1175-4816-89e1-eeab997a75bd.xml

module

module Reg_File( clk_i, rst_i, RSaddr_i, RTaddr_i, RDaddr_i, RDdata_i, RegWrite_i, RSdata_o, RTdata_o ); input clk_i; input rst_i; input RegWrite_i; input [5-1:0] RSaddr_i; input [5-1:0] RTaddr_i; input [5-1:0] RDaddr_i; input [32-1:0] RDdata_i; output [32-1:0] RSdata_o; output [32-1:0] RTdata_o; reg signed [32-1:0] Reg_File [0:32-1]; wire [32-1:0] RSdata_o; wire [32-1:0] RTdata_o; assign RSdata_o = ((RDaddr_i!=0) && (RDaddr_i==RSaddr_i))? RDdata_i : Reg_File[RSaddr_i] ; assign RTdata_o = ((RDaddr_i!=0) && (RDaddr_i==RTaddr_i))? RDdata_i : Reg_File[RTaddr_i] ; always @( posedge rst_i or posedge clk_i ) begin if(rst_i == 0) begin Reg_File[0] <= 0; Reg_File[1] <= 0; Reg_File[2] <= 0; Reg_File[3] <= 0; Reg_File[4] <= 0; Reg_File[5] <= 0; Reg_File[6] <= 0; Reg_File[7] <= 0; Reg_File[8] <= 0; Reg_File[9] <= 0; Reg_File[10] <= 0; Reg_File[11] <= 0; Reg_File[12] <= 0; Reg_File[13] <= 0; Reg_File[14] <= 0; Reg_File[15] <= 0; Reg_File[16] <= 0; Reg_File[17] <= 0; Reg_File[18] <= 0; Reg_File[19] <= 0; Reg_File[20] <= 0; Reg_File[21] <= 0; Reg_File[22] <= 0; Reg_File[23] <= 0; Reg_File[24] <= 0; Reg_File[25] <= 0; Reg_File[26] <= 0; Reg_File[27] <= 0; Reg_File[28] <= 0; Reg_File[29] <= 0; Reg_File[30] <= 0; Reg_File[31] <= 0; end else begin if(RegWrite_i) Reg_File[RDaddr_i] <= RDdata_i; else Reg_File[RDaddr_i] <= Reg_File[RDaddr_i]; end end endmodule

module Reg_File( clk_i, rst_i, RSaddr_i, RTaddr_i, RDaddr_i, RDdata_i, RegWrite_i, RSdata_o, RTdata_o );

input clk_i; input rst_i; input RegWrite_i; input [5-1:0] RSaddr_i; input [5-1:0] RTaddr_i; input [5-1:0] RDaddr_i; input [32-1:0] RDdata_i; output [32-1:0] RSdata_o; output [32-1:0] RTdata_o; reg signed [32-1:0] Reg_File [0:32-1]; wire [32-1:0] RSdata_o; wire [32-1:0] RTdata_o; assign RSdata_o = ((RDaddr_i!=0) && (RDaddr_i==RSaddr_i))? RDdata_i : Reg_File[RSaddr_i] ; assign RTdata_o = ((RDaddr_i!=0) && (RDaddr_i==RTaddr_i))? RDdata_i : Reg_File[RTaddr_i] ; always @( posedge rst_i or posedge clk_i ) begin if(rst_i == 0) begin Reg_File[0] <= 0; Reg_File[1] <= 0; Reg_File[2] <= 0; Reg_File[3] <= 0; Reg_File[4] <= 0; Reg_File[5] <= 0; Reg_File[6] <= 0; Reg_File[7] <= 0; Reg_File[8] <= 0; Reg_File[9] <= 0; Reg_File[10] <= 0; Reg_File[11] <= 0; Reg_File[12] <= 0; Reg_File[13] <= 0; Reg_File[14] <= 0; Reg_File[15] <= 0; Reg_File[16] <= 0; Reg_File[17] <= 0; Reg_File[18] <= 0; Reg_File[19] <= 0; Reg_File[20] <= 0; Reg_File[21] <= 0; Reg_File[22] <= 0; Reg_File[23] <= 0; Reg_File[24] <= 0; Reg_File[25] <= 0; Reg_File[26] <= 0; Reg_File[27] <= 0; Reg_File[28] <= 0; Reg_File[29] <= 0; Reg_File[30] <= 0; Reg_File[31] <= 0; end else begin if(RegWrite_i) Reg_File[RDaddr_i] <= RDdata_i; else Reg_File[RDaddr_i] <= Reg_File[RDaddr_i]; end end endmodule

data/full_repos/permissive/98702386/CPU/Shift_Left_Two_32.v

Shift_Left_Two_32.v

v

[]

[]

[]

'utf-8' codec can't decode byte 0xa8 in position 340: invalid start byte

data/verilator_xmls/dcbc614a-3bb5-45ee-8f20-9b292bab0656.xml

module

module Shift_Left_Two_32( data_i, data_o ); input [32-1:0] data_i; output [32-1:0] data_o; wire [31:0]data_o; assign data_o = data_i << 2; endmodule

module Shift_Left_Two_32( data_i, data_o );

input [32-1:0] data_i; output [32-1:0] data_o; wire [31:0]data_o; assign data_o = data_i << 2; endmodule

data/full_repos/permissive/98702386/CPU/Sign_Extend.v

Sign_Extend.v

v

[]

[]

[]

'utf-8' codec can't decode byte 0xa8 in position 463: invalid start byte

data/verilator_xmls/11f93e6c-9e1c-463e-9c0f-e47e8309f957.xml

module

module Sign_Extend( data_i, data_o ); input [16-1:0] data_i; output [32-1:0] data_o; reg [32-1:0] data_o; always @(*) begin data_o[0] <= data_i[0]; data_o[1] <= data_i[1]; data_o[2] <= data_i[2]; data_o[3] <= data_i[3]; data_o[4] <= data_i[4]; data_o[5] <= data_i[5]; data_o[6] <= data_i[6]; data_o[7] <= data_i[7]; data_o[8] <= data_i[8]; data_o[9] <= data_i[9]; data_o[10] <= data_i[10]; data_o[11] <= data_i[11]; data_o[12] <= data_i[12]; data_o[13] <= data_i[13]; data_o[14] <= data_i[14]; data_o[15] <= data_i[15]; data_o[16] <= data_i[15]; data_o[17] <= data_i[15]; data_o[18] <= data_i[15]; data_o[19] <= data_i[15]; data_o[20] <= data_i[15]; data_o[21] <= data_i[15]; data_o[22] <= data_i[15]; data_o[23] <= data_i[15]; data_o[24] <= data_i[15]; data_o[25] <= data_i[15]; data_o[26] <= data_i[15]; data_o[27] <= data_i[15]; data_o[28] <= data_i[15]; data_o[29] <= data_i[15]; data_o[30] <= data_i[15]; data_o[31] <= data_i[15]; end endmodule

module Sign_Extend( data_i, data_o );

input [16-1:0] data_i; output [32-1:0] data_o; reg [32-1:0] data_o; always @(*) begin data_o[0] <= data_i[0]; data_o[1] <= data_i[1]; data_o[2] <= data_i[2]; data_o[3] <= data_i[3]; data_o[4] <= data_i[4]; data_o[5] <= data_i[5]; data_o[6] <= data_i[6]; data_o[7] <= data_i[7]; data_o[8] <= data_i[8]; data_o[9] <= data_i[9]; data_o[10] <= data_i[10]; data_o[11] <= data_i[11]; data_o[12] <= data_i[12]; data_o[13] <= data_i[13]; data_o[14] <= data_i[14]; data_o[15] <= data_i[15]; data_o[16] <= data_i[15]; data_o[17] <= data_i[15]; data_o[18] <= data_i[15]; data_o[19] <= data_i[15]; data_o[20] <= data_i[15]; data_o[21] <= data_i[15]; data_o[22] <= data_i[15]; data_o[23] <= data_i[15]; data_o[24] <= data_i[15]; data_o[25] <= data_i[15]; data_o[26] <= data_i[15]; data_o[27] <= data_i[15]; data_o[28] <= data_i[15]; data_o[29] <= data_i[15]; data_o[30] <= data_i[15]; data_o[31] <= data_i[15]; end endmodule

data/full_repos/permissive/98702386/CPU/Stall_Pipe_Reg.v

Stall_Pipe_Reg.v

v

[]

[]

[]

'utf-8' codec can't decode byte 0xa8 in position 465: invalid start byte

1: b'%Warning-LITENDIAN: data/full_repos/permissive/98702386/CPU/Stall_Pipe_Reg.v:25: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [size-1: 0] data_i;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/98702386/CPU/Stall_Pipe_Reg.v:28: Little bit endian vector: MSB < LSB of bit range: -1:0\noutput reg [size-1: 0] data_o;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/98702386/CPU/Stall_Pipe_Reg.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [size-1: 0] stall;\n ^\n%Error: Exiting due to 3 warning(s)\n'

module

module Stall_Pipe_Reg( clk_i, rst_i, data_i, data_o, ifid_Write, if_flush ); parameter size = 0; input clk_i; input rst_i; input [size-1: 0] data_i; input ifid_Write; input if_flush; output reg [size-1: 0] data_o; reg [size-1: 0] stall; always @(posedge clk_i) begin if(~rst_i || if_flush)begin data_o <= 0; stall <= 0; end else if(ifid_Write)begin data_o <= data_i; stall <= data_i; end else data_o <= stall; end endmodule

module Stall_Pipe_Reg( clk_i, rst_i, data_i, data_o, ifid_Write, if_flush );

parameter size = 0; input clk_i; input rst_i; input [size-1: 0] data_i; input ifid_Write; input if_flush; output reg [size-1: 0] data_o; reg [size-1: 0] stall; always @(posedge clk_i) begin if(~rst_i || if_flush)begin data_o <= 0; stall <= 0; end else if(ifid_Write)begin data_o <= data_i; stall <= data_i; end else data_o <= stall; end endmodule

data/full_repos/permissive/98729405/verilog code/final_project.v

final_project.v

v

[]

[]

[]

[(1, 982)]

1: b'%Error: Cannot find file containing module: code,data/full_repos/permissive/98729405\n ... Looked in:\n data/full_repos/permissive/98729405/verilog/code,data/full_repos/permissive/98729405\n data/full_repos/permissive/98729405/verilog/code,data/full_repos/permissive/98729405.v\n data/full_repos/permissive/98729405/verilog/code,data/full_repos/permissive/98729405.sv\n code,data/full_repos/permissive/98729405\n code,data/full_repos/permissive/98729405.v\n code,data/full_repos/permissive/98729405.sv\n obj_dir/code,data/full_repos/permissive/98729405\n obj_dir/code,data/full_repos/permissive/98729405.v\n obj_dir/code,data/full_repos/permissive/98729405.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98729405/verilog\n%Error: Cannot find file containing module: code/final_project.v\n%Error: Exiting due to 3 error(s)\n'

module

module final_project ( input clk, input reset, input ROT_A, input ROT_B, input button_west, input btn_center, input button_east, input button_north, output [7:0]led, output wire hsync, output wire vsync, output reg R, output reg G, output reg B ); reg [9:0] cnt; wire visible; reg [12:0] pixel_x, pixel_y; reg [12:0] rect_x = 12'd500; reg [12:0] rect_y; reg [12:0] tr1_x = 12'd250; reg [12:0] tr1_y; reg [12:0] tr2_x = 12'd400; reg [12:0] tr2_y; reg [12:0] cir_x = 12'd87; reg [12:0] cir_y; reg [12:0] cir1_x = 12'd329; reg [12:0] cir1_y; reg [12:0] GP_x, GP_y; wire rotary_event,rotary_right; wire [9:0] rand_num1, rand_num2, rand_num3, rand_num4, rand_num5; wire [7:0] scores; reg [7:0] tp1_score, tp2_score, tp3_score, tp4_score, tp5_score; reg [5:0] tp1_num, tp2_num, tp3_num, tp4_num, tp5_num; reg [7:0] less_numbers; wire [7:0] less_number; reg [5:0] less_num2; reg [5:0] less_num1; wire btn_west_out, btn_west_pressed; reg prev_btn_west_out; wire btn_east_out, btn_east_pressed; reg prev_btn_east_out; wire btn_center_out, btn_center_pressed; reg prev_btn_center_out; wire btn_north_out, btn_north_pressed; reg prev_btn_north_out; reg resume, start; reg [6:0]GP_v; reg [7:0] tp11, tp22, tp33, tp44, tp55; wire [7:0] cirr, rectt, trii; assign cirr = (reset)? 0 : tp33+tp55; assign rectt = (reset)? 0 : tp11; assign trii = (reset)? 0 : tp22+tp44; assign less_number = (reset)? 0 : (less_number==50)? 50 : tp1_num+ tp2_num+ tp3_num+ tp4_num+ tp5_num; assign scores = tp1_score+ tp2_score+ tp3_score+ tp4_score+ tp5_score; assign led = scores; Rotation_direction rd( .CLK(clk), .ROT_A(ROT_A), .ROT_B(ROT_B), .rotary_event(rotary_event), .rotary_right(rotary_right) ); debounce btn_db0( .clk(clk), .btn_input(button_west), .btn_output(btn_west_out) ); always @(posedge clk) begin if (reset) prev_btn_west_out <= 0; else prev_btn_west_out <= btn_west_out; end assign btn_west_pressed = (btn_west_out == 1 && prev_btn_west_out == 0)? 1 : 0; debounce btn_db3( .clk(clk), .btn_input(button_north), .btn_output(btn_north_out) ); always @(posedge clk) begin if (reset) prev_btn_north_out <= 0; else prev_btn_north_out <= btn_north_out; end assign btn_north_pressed = (btn_north_out == 1 && prev_btn_north_out == 0)? 1 : 0; debounce btn_db2( .clk(clk), .btn_input(button_east), .btn_output(btn_east_out) ); always @(posedge clk) begin if (reset) prev_btn_east_out <= 0; else prev_btn_east_out <= btn_east_out; end assign btn_east_pressed = (btn_east_out == 1 && prev_btn_east_out == 0)? 1 : 0; debounce btn_db1( .clk(clk), .btn_input(btn_center), .btn_output(btn_center_out) ); always @(posedge clk) begin if (reset) prev_btn_center_out <= 0; else prev_btn_center_out <= btn_center_out; end assign btn_center_pressed = (btn_center_out == 1 && prev_btn_center_out == 0)? 1 : 0; always@(posedge clk)begin if(reset)begin cnt<= 0; end else begin if(btn_center_pressed) cnt <= cnt +1; else cnt <= (cnt!=0)? cnt+1:0; end end always @(posedge clk) begin if (reset) less_numbers <= 0; else less_numbers <= less_number; end always@(posedge clk) begin if(reset)begin less_num2<=2; less_num1<=0; end else if(less_numbers != less_number)begin less_num2 <= (less_num2==0) ? 0 : (less_num1==0)? less_num2-1: less_num2; less_num1 <= (less_num1==0)? 9 : less_num1-1; end end lfsrr1 randdd( .clk(clk), .lfsr(rand_num1) ); lfsrr2 randdfdd( .clk(clk), .lfsr(rand_num2) ); lfsrr3 randddsd( .clk(clk), .lfsr(rand_num3) ); lfsrr4 randdfdfd( .clk(clk), .lfsr(rand_num4) ); lfsrr5 randsddd( .clk(clk), .lfsr(rand_num5) ); parameter DEFAULT = 3'b000; parameter BLACK = 3'b000; parameter RED = 3'b100; parameter GREEN = 3'b010; parameter BLUE = 3'b001; parameter CYAN = 3'b011; parameter MAGEN = 3'b101; parameter YELLOW= 3'b110; parameter WHITE = 3'b111; always@(posedge clk) begin if(reset) pixel_x <=0; else if(pixel_x==1039) pixel_x <=0; else pixel_x <= pixel_x+1; end always@(posedge clk) begin if(reset) pixel_y <=0; else if(pixel_y==665) pixel_y <=0; else if(pixel_x==1039) pixel_y <= pixel_y+1; else pixel_y <= pixel_y; end assign hsync = ~((pixel_x>=919)&(pixel_x<1039)); assign vsync = ~((pixel_y>=659)&(pixel_y<665)); assign visible = ((pixel_x>=104)&(pixel_x<904)&(pixel_y>=23)&(pixel_y<623)); reg flag; always@(posedge clk) begin if(reset) begin GP_x <= 0; flag <= 0; end else if (rotary_event && rotary_right) begin flag <= 0; if(GP_x <= 720) if(start) if(resume) GP_x <= GP_x+GP_v; end else if (rotary_event && !rotary_right) begin flag <=1; if(GP_x >= 10) if(start) if(resume) GP_x <= GP_x-GP_v; end else GP_x <= GP_x; end reg rand; reg [31:0]counter1, counter2, counter3, counter4, counter5, counter6; always@(posedge clk) begin if(reset) begin counter1 <=0; rect_y <= 0; rect_x <= rand_num1; tp1_score <= 0; tp1_num <= 0; tp11 <= 0; end else if(counter1==500000) begin counter1 <= 0; if(rect_y==620) begin rect_y <= 0; rect_x <= rand_num1; tp1_num <= tp1_num+1; end else if( (rect_y<=530) && (rect_y>=500) && (104+30+GP_x -5<= 104+rect_x) && (104+62+GP_x+5 >= 104+20+rect_x) ) begin rect_y <= 0; rect_x <= rand_num1; tp1_score <= tp1_score+1; tp1_num <= tp1_num+1; tp11 <= tp11+1; end else begin rect_y <= rect_y + 1; end end else if(start) if(resume) if(less_number<20) counter1 <= counter1+1; end always@(posedge clk) begin if(reset) begin counter2 <=0; tr1_y <= 0; tr1_x <= rand_num2; tp2_score <= 0; tp2_num <= 0; tp22 <= 0; end else if(counter2==1000000) begin counter2 <= 0; if(tr1_y==620) begin tr1_y <= 0; tr1_x <= rand_num2; tp2_num <= tp2_num+1; end else if( (tr1_y<=530) && (tr1_y>=500) && (104+30+GP_x -5<= 104+tr1_x) && (104+62+GP_x+5 >= 104+20+tr1_x) ) begin tr1_y <= 0; tr1_x <= rand_num2; tp2_score <= tp2_score+1; tp2_num <= tp2_num+1; tp22 <= tp22+1; end else begin tr1_y <= tr1_y + 1; end end else if(start) if(resume) if(less_number<20) counter2 <= counter2+1; end always@(posedge clk) begin if(reset) begin counter3 <=0; cir_y <= 0; cir_x <= rand_num3; tp3_score <= 0; tp3_num <= 0; tp33<=0; end else if(counter3==700000) begin counter3 <= 0; if(cir_y==620) begin cir_y <= 0; cir_x <= rand_num3; tp3_num <= tp3_num+1; end else if( (cir_y<=530) && (cir_y>=500) && (104+30+GP_x-5 <= 104+cir_x) && (104+62+GP_x+5 >= 104+20+cir_x) ) begin cir_y <= 0; cir_x <= rand_num3; tp3_score <= tp3_score+1; tp3_num <= tp3_num+1; tp33 <= tp33+1; end else begin cir_y <= cir_y + 1; end end else if(start) if(resume) if(less_number<20) counter3 <= counter3+1; end always@(posedge clk) begin if(reset) begin counter4 <=0; tr2_y <= 0; tr2_x <= rand_num4; tp4_score <= 0; tp4_num <= 0; tp44<=0; end else if(counter4==200000) begin counter4 <= 0; if(tr2_y==620) begin tr2_y <= 0; tr2_x <= rand_num4; tp4_num <= tp4_num+1; end else if( (tr2_y<=530) && (tr2_y>=500) && (104+30+GP_x-5 <= 104+tr2_x) && (104+62+GP_x+5 >= 104+20+tr2_x) ) begin tr2_y <= 0; tr2_x <= rand_num4; tp4_score <= tp4_score+1; tp4_num <= tp4_num+1; tp44 <= tp44+1; end else begin tr2_y <= tr2_y + 1; end end else if(start) if(resume) if(less_number<20) counter4 <= counter4+1; end always@(posedge clk) begin if(reset) begin counter5 <=0; cir1_y <= 0; cir1_x <= rand_num5; tp5_score <= 0; tp5_num <= 0; tp55<=0; end else if(counter5==400000) begin counter5 <= 0; if(cir1_y==620) begin cir1_y <= 0; cir1_x <= rand_num5; tp5_num <= tp5_num+1; end else if( (cir1_y<=530) && (cir1_y>=500) && (104+30+GP_x-5 <= 104+cir1_x) && (104+62+GP_x+5 >= 104+20+cir1_x) ) begin cir1_y <= 0; cir1_x <= rand_num5; tp5_score <= tp5_score+1; tp5_num <= tp5_num+1; tp55 <= tp55+1; end else begin if(start) if(resume) if(less_number<20) cir1_y <= cir1_y + 1; end end else counter5 <= counter5+1; end reg GPopen; always@(posedge clk) begin if(reset)begin GPopen <= 0; counter6 <= 0; end else if(5000000<counter6 && counter6<=10000000) begin GPopen <= 1; counter6 <= counter6+1; end else if(0<=counter6 && counter6<=5000000) begin GPopen <= 0; counter6 <= counter6+1; end else counter6 <= 0; end reg [2:0]GP_color, BACKGROUND_color, tp1_color, tp2_color, tp3_color, tp4_color, tp5_color; reg [2:0]sel, sell; always@(posedge clk) begin if(reset) begin start <= 0; resume <= 1; sel <= 0; sell <= 0; GP_v <= 10; GP_color <= YELLOW; BACKGROUND_color <= WHITE; tp1_color <= BLACK; tp2_color <= CYAN; tp3_color <= RED; tp4_color <= MAGEN; tp5_color <= YELLOW; end else begin if(btn_west_pressed==1) begin if(resume==1) resume <= 0; else resume <= 1; end else if(btn_center_pressed==1) start <= 1; else if(btn_north_pressed==1)begin case(sell) 0:GP_v <=5; 1:GP_v <=25; 2:GP_v <= 10; endcase if(sell==2) sell <= 0; else sell <= sell+1; end else if(btn_east_pressed==1) begin if(start)begin case(sel) 0:begin GP_color <= WHITE; BACKGROUND_color <= MAGEN; tp1_color <= RED; tp2_color <= YELLOW; tp3_color <= BLACK; tp4_color <= GREEN; tp5_color <= WHITE; end 1:begin GP_color <= GREEN; BACKGROUND_color <= BLACK; tp1_color <= MAGEN; tp2_color <= CYAN; tp3_color <= GREEN; tp4_color <= RED; tp5_color <= YELLOW; end 2:begin GP_color <= BLACK; BACKGROUND_color <= RED; tp1_color <= WHITE; tp2_color <= YELLOW; tp3_color <= GREEN; tp4_color <= MAGEN; tp5_color <= CYAN; end 3:begin GP_color <= YELLOW; BACKGROUND_color <= WHITE; tp1_color <= BLACK; tp2_color <= CYAN; tp3_color <= RED; tp4_color <= MAGEN; tp5_color <= YELLOW; end endcase if(sel==3) sel <= 0; else sel <= sel+1; end end end end always@(posedge clk) begin if(visible) begin if(!start)begin {R,G,B} <= WHITE; if( (pixel_x >= 104 + 100) && (pixel_x < 104+700) && (pixel_y >= 23 + 50) && (pixel_y < 623 -50) ) {R,G,B} <= BLUE; end else begin if(resume)begin if( (less_number<20) && (pixel_x >= rect_x + 104) && (pixel_x < rect_x + 104 + 20 ) && (pixel_y >= rect_y + 23) && (pixel_y < rect_y + 23 + 20) ) {R,G,B} <= tp1_color; else if( (less_number<20) && (pixel_x >= tr1_x + 104 ) && (pixel_x < tr1_x + 104 +20 ) && (pixel_y >= tr1_y + 23) && (pixel_y < tr1_y + 23 + 20 )) {R,G,B} <= ((pixel_y - 23 -tr1_y<= 2*(pixel_x - 104 - tr1_x )) && (pixel_y - 23 - tr1_y <= -2*(pixel_x - 104 - tr1_x )+40) )? tp2_color : BACKGROUND_color; else if( (less_number<20) && (pixel_x >= tr2_x + 104 ) && (pixel_x < tr2_x + 104 + 20 ) && (pixel_y >= tr2_y + 23) && (pixel_y < tr2_y + 23 + 20 )) {R,G,B} <= ((pixel_y - 23 -tr2_y<= 2*(pixel_x - 104 - tr2_x )) && (pixel_y - 23 - tr2_y <= -2*(pixel_x - 104 - tr2_x )+40) )? tp3_color : BACKGROUND_color; else if( (less_number<20) && (pixel_x >= cir_x + 104 ) && (pixel_x < cir_x + 104 + 20) && (pixel_y >= cir_y + 23) && (pixel_y < cir_y + 23 + 20 )) {R,G,B} <= ((pixel_x-cir_x-104 - 10 )*(pixel_x-cir_x-104 -10 )+(pixel_y-23-cir_y -10)*(pixel_y-23-cir_y -10)<=100)? tp4_color : BACKGROUND_color; else if( (less_number<20) && (pixel_x >= cir1_x + 104 ) && (pixel_x < cir1_x + 104 + 20 ) && (pixel_y >= cir1_y + 23) && (pixel_y < cir1_y + 23 + 20 )) {R,G,B} <= ((pixel_x-cir1_x-104 - 10)*(pixel_x-cir1_x-104 -10)+(pixel_y-23-cir1_y -10)*(pixel_y-23-cir1_y -10)<=100)? tp5_color : BACKGROUND_color; else if(less_number==20) begin if( (pixel_x >= 104 + 100) && (pixel_x < 104+700) && (pixel_y >= 23 + 50) && (pixel_y < 623 -50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLUE; if( (pixel_x >= 104 +375 ) && (pixel_x < 104 + 375 + 50) && (pixel_y >= 23 +175) && (pixel_y < 23 + 225 )) {R,G,B} <= ((pixel_x-104-375 - 25 )*(pixel_x-104-375 -25 )+(pixel_y-23-175 -25)*(pixel_y-23-175 -25)<=625)? BLACK : WHITE; else if( (pixel_x >= 104 +375) && (pixel_x < 104 + 375 +50 ) && (pixel_y >= 23 +275) && (pixel_y < + 23 + 325) ) {R,G,B} <= BLACK; else if( (pixel_x >= 104 +375) && (pixel_x < 104 + 375 +50 ) && (pixel_y >= 23 +375) && (pixel_y < + 23 + 425) ) {R,G,B} <= ((pixel_y - 23-375 <= 2*(pixel_x - 104 -375 )) && (pixel_y - 23 -375 <= -2*(pixel_x - 104 -375 )+100) )? BLACK : WHITE; if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +100) && (pixel_y < 23 + 150 -15+100) ) begin case(cirr) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100) && (pixel_y < 23 + 150 -15 -10+100) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100) && (pixel_y < 23 + 150 -15+100 ) ) {R,G,B} <= BLACK; else {R,G,B} <= WHITE; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15+100) && (pixel_y < 23 + 150 -15 - 40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15+100) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100) && (pixel_y < 23 + 150 -15-40+100)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100) && (pixel_y < 23 + 150 -15-40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end endcase end if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +100+50+50) && (pixel_y < 23 + 150 -15+100+50+50) ) begin case(rectt) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50 ) ) {R,G,B} <= BLACK; else {R,G,B} <= WHITE; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15+100+50+50) && (pixel_y < 23 + 150 -15 - 40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end endcase end if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50) ) begin case(trii) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50 ) ) {R,G,B} <= BLACK; else {R,G,B} <= WHITE; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15+100+50+50+50+50) && (pixel_y < 23 + 150 -15 - 40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end endcase end end else if((pixel_x >= 104 + 600) && (pixel_x < 104 + 750) && (pixel_y >= 23 + 50) && (pixel_y < 23 + 150) ) begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15) ) begin case(less_num2) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15 -10) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 ) ) {R,G,B} <= BLACK; else {R,G,B} <= CYAN; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 - 40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end endcase end else {R,G,B} <= CYAN; if((pixel_x >= 104 + 600 +95) && (pixel_x < 104 + 600 +130) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15) ) begin case(less_num1) 0:begin if((pixel_x >= 104 + 600 +95 + 10) && (pixel_x < 104 + 600 +130-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15 -10) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +95 + 25) && (pixel_x < 104 + 600 +130) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 ) ) {R,G,B} <= BLACK; else {R,G,B} <= CYAN; end 2:begin if( ((pixel_x >= 104 + 600 +20 + 75) && (pixel_x < 104 + 600 +55 - 10 +75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10 +75) && (pixel_x < 104 + 600 +55 +75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20 +75) && (pixel_x < 104 + 600 +55 - 10 +75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +75) && (pixel_x < 104 + 600 +55 -10 +75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10+75) && (pixel_x < 104 + 600 +55 - 10 +75) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 - 40)) || ((pixel_x >= 104 + 600 +20 +75) && (pixel_x < 104 + 600 +55 -10 +75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10+75) && (pixel_x < 104 + 600 +55+75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10+75) && (pixel_x < 104 + 600 +55+75) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10+75) && (pixel_x < 104 + 600 +55-10+75) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20 +10+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10+75) && (pixel_x < 104 + 600 +55-10+75) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end endcase end end else if((pixel_x >= 104 + 30 + GP_x) && (pixel_x < 104 + 62 + GP_x) && (pixel_y >= 23 + 518) && (pixel_y < 23 + 550)) begin if( (pixel_x-104-30-GP_x -16)*(pixel_x-104-30-GP_x -16)+(pixel_y-23-518 -16)*(pixel_y-23-518 -16) <= 256 ) begin if( (pixel_y - 23 -518<= (pixel_x - 104 - 30 - GP_x)) && (pixel_y - 23 - 518) <= -1*(pixel_x - 104 - 30 - GP_x)+32 ) begin if(GPopen) {R,G,B} <= RED; else {R,G,B} <= GP_color; end else {R,G,B} <= GP_color; end else {R,G,B} <= BACKGROUND_color; end else {R,G,B} <= BACKGROUND_color; end else {R,G,B} <= DEFAULT; end end else {R,G,B} <= DEFAULT; end endmodule

module final_project ( input clk, input reset, input ROT_A, input ROT_B, input button_west, input btn_center, input button_east, input button_north, output [7:0]led, output wire hsync, output wire vsync, output reg R, output reg G, output reg B );

reg [9:0] cnt; wire visible; reg [12:0] pixel_x, pixel_y; reg [12:0] rect_x = 12'd500; reg [12:0] rect_y; reg [12:0] tr1_x = 12'd250; reg [12:0] tr1_y; reg [12:0] tr2_x = 12'd400; reg [12:0] tr2_y; reg [12:0] cir_x = 12'd87; reg [12:0] cir_y; reg [12:0] cir1_x = 12'd329; reg [12:0] cir1_y; reg [12:0] GP_x, GP_y; wire rotary_event,rotary_right; wire [9:0] rand_num1, rand_num2, rand_num3, rand_num4, rand_num5; wire [7:0] scores; reg [7:0] tp1_score, tp2_score, tp3_score, tp4_score, tp5_score; reg [5:0] tp1_num, tp2_num, tp3_num, tp4_num, tp5_num; reg [7:0] less_numbers; wire [7:0] less_number; reg [5:0] less_num2; reg [5:0] less_num1; wire btn_west_out, btn_west_pressed; reg prev_btn_west_out; wire btn_east_out, btn_east_pressed; reg prev_btn_east_out; wire btn_center_out, btn_center_pressed; reg prev_btn_center_out; wire btn_north_out, btn_north_pressed; reg prev_btn_north_out; reg resume, start; reg [6:0]GP_v; reg [7:0] tp11, tp22, tp33, tp44, tp55; wire [7:0] cirr, rectt, trii; assign cirr = (reset)? 0 : tp33+tp55; assign rectt = (reset)? 0 : tp11; assign trii = (reset)? 0 : tp22+tp44; assign less_number = (reset)? 0 : (less_number==50)? 50 : tp1_num+ tp2_num+ tp3_num+ tp4_num+ tp5_num; assign scores = tp1_score+ tp2_score+ tp3_score+ tp4_score+ tp5_score; assign led = scores; Rotation_direction rd( .CLK(clk), .ROT_A(ROT_A), .ROT_B(ROT_B), .rotary_event(rotary_event), .rotary_right(rotary_right) ); debounce btn_db0( .clk(clk), .btn_input(button_west), .btn_output(btn_west_out) ); always @(posedge clk) begin if (reset) prev_btn_west_out <= 0; else prev_btn_west_out <= btn_west_out; end assign btn_west_pressed = (btn_west_out == 1 && prev_btn_west_out == 0)? 1 : 0; debounce btn_db3( .clk(clk), .btn_input(button_north), .btn_output(btn_north_out) ); always @(posedge clk) begin if (reset) prev_btn_north_out <= 0; else prev_btn_north_out <= btn_north_out; end assign btn_north_pressed = (btn_north_out == 1 && prev_btn_north_out == 0)? 1 : 0; debounce btn_db2( .clk(clk), .btn_input(button_east), .btn_output(btn_east_out) ); always @(posedge clk) begin if (reset) prev_btn_east_out <= 0; else prev_btn_east_out <= btn_east_out; end assign btn_east_pressed = (btn_east_out == 1 && prev_btn_east_out == 0)? 1 : 0; debounce btn_db1( .clk(clk), .btn_input(btn_center), .btn_output(btn_center_out) ); always @(posedge clk) begin if (reset) prev_btn_center_out <= 0; else prev_btn_center_out <= btn_center_out; end assign btn_center_pressed = (btn_center_out == 1 && prev_btn_center_out == 0)? 1 : 0; always@(posedge clk)begin if(reset)begin cnt<= 0; end else begin if(btn_center_pressed) cnt <= cnt +1; else cnt <= (cnt!=0)? cnt+1:0; end end always @(posedge clk) begin if (reset) less_numbers <= 0; else less_numbers <= less_number; end always@(posedge clk) begin if(reset)begin less_num2<=2; less_num1<=0; end else if(less_numbers != less_number)begin less_num2 <= (less_num2==0) ? 0 : (less_num1==0)? less_num2-1: less_num2; less_num1 <= (less_num1==0)? 9 : less_num1-1; end end lfsrr1 randdd( .clk(clk), .lfsr(rand_num1) ); lfsrr2 randdfdd( .clk(clk), .lfsr(rand_num2) ); lfsrr3 randddsd( .clk(clk), .lfsr(rand_num3) ); lfsrr4 randdfdfd( .clk(clk), .lfsr(rand_num4) ); lfsrr5 randsddd( .clk(clk), .lfsr(rand_num5) ); parameter DEFAULT = 3'b000; parameter BLACK = 3'b000; parameter RED = 3'b100; parameter GREEN = 3'b010; parameter BLUE = 3'b001; parameter CYAN = 3'b011; parameter MAGEN = 3'b101; parameter YELLOW= 3'b110; parameter WHITE = 3'b111; always@(posedge clk) begin if(reset) pixel_x <=0; else if(pixel_x==1039) pixel_x <=0; else pixel_x <= pixel_x+1; end always@(posedge clk) begin if(reset) pixel_y <=0; else if(pixel_y==665) pixel_y <=0; else if(pixel_x==1039) pixel_y <= pixel_y+1; else pixel_y <= pixel_y; end assign hsync = ~((pixel_x>=919)&(pixel_x<1039)); assign vsync = ~((pixel_y>=659)&(pixel_y<665)); assign visible = ((pixel_x>=104)&(pixel_x<904)&(pixel_y>=23)&(pixel_y<623)); reg flag; always@(posedge clk) begin if(reset) begin GP_x <= 0; flag <= 0; end else if (rotary_event && rotary_right) begin flag <= 0; if(GP_x <= 720) if(start) if(resume) GP_x <= GP_x+GP_v; end else if (rotary_event && !rotary_right) begin flag <=1; if(GP_x >= 10) if(start) if(resume) GP_x <= GP_x-GP_v; end else GP_x <= GP_x; end reg rand; reg [31:0]counter1, counter2, counter3, counter4, counter5, counter6; always@(posedge clk) begin if(reset) begin counter1 <=0; rect_y <= 0; rect_x <= rand_num1; tp1_score <= 0; tp1_num <= 0; tp11 <= 0; end else if(counter1==500000) begin counter1 <= 0; if(rect_y==620) begin rect_y <= 0; rect_x <= rand_num1; tp1_num <= tp1_num+1; end else if( (rect_y<=530) && (rect_y>=500) && (104+30+GP_x -5<= 104+rect_x) && (104+62+GP_x+5 >= 104+20+rect_x) ) begin rect_y <= 0; rect_x <= rand_num1; tp1_score <= tp1_score+1; tp1_num <= tp1_num+1; tp11 <= tp11+1; end else begin rect_y <= rect_y + 1; end end else if(start) if(resume) if(less_number<20) counter1 <= counter1+1; end always@(posedge clk) begin if(reset) begin counter2 <=0; tr1_y <= 0; tr1_x <= rand_num2; tp2_score <= 0; tp2_num <= 0; tp22 <= 0; end else if(counter2==1000000) begin counter2 <= 0; if(tr1_y==620) begin tr1_y <= 0; tr1_x <= rand_num2; tp2_num <= tp2_num+1; end else if( (tr1_y<=530) && (tr1_y>=500) && (104+30+GP_x -5<= 104+tr1_x) && (104+62+GP_x+5 >= 104+20+tr1_x) ) begin tr1_y <= 0; tr1_x <= rand_num2; tp2_score <= tp2_score+1; tp2_num <= tp2_num+1; tp22 <= tp22+1; end else begin tr1_y <= tr1_y + 1; end end else if(start) if(resume) if(less_number<20) counter2 <= counter2+1; end always@(posedge clk) begin if(reset) begin counter3 <=0; cir_y <= 0; cir_x <= rand_num3; tp3_score <= 0; tp3_num <= 0; tp33<=0; end else if(counter3==700000) begin counter3 <= 0; if(cir_y==620) begin cir_y <= 0; cir_x <= rand_num3; tp3_num <= tp3_num+1; end else if( (cir_y<=530) && (cir_y>=500) && (104+30+GP_x-5 <= 104+cir_x) && (104+62+GP_x+5 >= 104+20+cir_x) ) begin cir_y <= 0; cir_x <= rand_num3; tp3_score <= tp3_score+1; tp3_num <= tp3_num+1; tp33 <= tp33+1; end else begin cir_y <= cir_y + 1; end end else if(start) if(resume) if(less_number<20) counter3 <= counter3+1; end always@(posedge clk) begin if(reset) begin counter4 <=0; tr2_y <= 0; tr2_x <= rand_num4; tp4_score <= 0; tp4_num <= 0; tp44<=0; end else if(counter4==200000) begin counter4 <= 0; if(tr2_y==620) begin tr2_y <= 0; tr2_x <= rand_num4; tp4_num <= tp4_num+1; end else if( (tr2_y<=530) && (tr2_y>=500) && (104+30+GP_x-5 <= 104+tr2_x) && (104+62+GP_x+5 >= 104+20+tr2_x) ) begin tr2_y <= 0; tr2_x <= rand_num4; tp4_score <= tp4_score+1; tp4_num <= tp4_num+1; tp44 <= tp44+1; end else begin tr2_y <= tr2_y + 1; end end else if(start) if(resume) if(less_number<20) counter4 <= counter4+1; end always@(posedge clk) begin if(reset) begin counter5 <=0; cir1_y <= 0; cir1_x <= rand_num5; tp5_score <= 0; tp5_num <= 0; tp55<=0; end else if(counter5==400000) begin counter5 <= 0; if(cir1_y==620) begin cir1_y <= 0; cir1_x <= rand_num5; tp5_num <= tp5_num+1; end else if( (cir1_y<=530) && (cir1_y>=500) && (104+30+GP_x-5 <= 104+cir1_x) && (104+62+GP_x+5 >= 104+20+cir1_x) ) begin cir1_y <= 0; cir1_x <= rand_num5; tp5_score <= tp5_score+1; tp5_num <= tp5_num+1; tp55 <= tp55+1; end else begin if(start) if(resume) if(less_number<20) cir1_y <= cir1_y + 1; end end else counter5 <= counter5+1; end reg GPopen; always@(posedge clk) begin if(reset)begin GPopen <= 0; counter6 <= 0; end else if(5000000<counter6 && counter6<=10000000) begin GPopen <= 1; counter6 <= counter6+1; end else if(0<=counter6 && counter6<=5000000) begin GPopen <= 0; counter6 <= counter6+1; end else counter6 <= 0; end reg [2:0]GP_color, BACKGROUND_color, tp1_color, tp2_color, tp3_color, tp4_color, tp5_color; reg [2:0]sel, sell; always@(posedge clk) begin if(reset) begin start <= 0; resume <= 1; sel <= 0; sell <= 0; GP_v <= 10; GP_color <= YELLOW; BACKGROUND_color <= WHITE; tp1_color <= BLACK; tp2_color <= CYAN; tp3_color <= RED; tp4_color <= MAGEN; tp5_color <= YELLOW; end else begin if(btn_west_pressed==1) begin if(resume==1) resume <= 0; else resume <= 1; end else if(btn_center_pressed==1) start <= 1; else if(btn_north_pressed==1)begin case(sell) 0:GP_v <=5; 1:GP_v <=25; 2:GP_v <= 10; endcase if(sell==2) sell <= 0; else sell <= sell+1; end else if(btn_east_pressed==1) begin if(start)begin case(sel) 0:begin GP_color <= WHITE; BACKGROUND_color <= MAGEN; tp1_color <= RED; tp2_color <= YELLOW; tp3_color <= BLACK; tp4_color <= GREEN; tp5_color <= WHITE; end 1:begin GP_color <= GREEN; BACKGROUND_color <= BLACK; tp1_color <= MAGEN; tp2_color <= CYAN; tp3_color <= GREEN; tp4_color <= RED; tp5_color <= YELLOW; end 2:begin GP_color <= BLACK; BACKGROUND_color <= RED; tp1_color <= WHITE; tp2_color <= YELLOW; tp3_color <= GREEN; tp4_color <= MAGEN; tp5_color <= CYAN; end 3:begin GP_color <= YELLOW; BACKGROUND_color <= WHITE; tp1_color <= BLACK; tp2_color <= CYAN; tp3_color <= RED; tp4_color <= MAGEN; tp5_color <= YELLOW; end endcase if(sel==3) sel <= 0; else sel <= sel+1; end end end end always@(posedge clk) begin if(visible) begin if(!start)begin {R,G,B} <= WHITE; if( (pixel_x >= 104 + 100) && (pixel_x < 104+700) && (pixel_y >= 23 + 50) && (pixel_y < 623 -50) ) {R,G,B} <= BLUE; end else begin if(resume)begin if( (less_number<20) && (pixel_x >= rect_x + 104) && (pixel_x < rect_x + 104 + 20 ) && (pixel_y >= rect_y + 23) && (pixel_y < rect_y + 23 + 20) ) {R,G,B} <= tp1_color; else if( (less_number<20) && (pixel_x >= tr1_x + 104 ) && (pixel_x < tr1_x + 104 +20 ) && (pixel_y >= tr1_y + 23) && (pixel_y < tr1_y + 23 + 20 )) {R,G,B} <= ((pixel_y - 23 -tr1_y<= 2*(pixel_x - 104 - tr1_x )) && (pixel_y - 23 - tr1_y <= -2*(pixel_x - 104 - tr1_x )+40) )? tp2_color : BACKGROUND_color; else if( (less_number<20) && (pixel_x >= tr2_x + 104 ) && (pixel_x < tr2_x + 104 + 20 ) && (pixel_y >= tr2_y + 23) && (pixel_y < tr2_y + 23 + 20 )) {R,G,B} <= ((pixel_y - 23 -tr2_y<= 2*(pixel_x - 104 - tr2_x )) && (pixel_y - 23 - tr2_y <= -2*(pixel_x - 104 - tr2_x )+40) )? tp3_color : BACKGROUND_color; else if( (less_number<20) && (pixel_x >= cir_x + 104 ) && (pixel_x < cir_x + 104 + 20) && (pixel_y >= cir_y + 23) && (pixel_y < cir_y + 23 + 20 )) {R,G,B} <= ((pixel_x-cir_x-104 - 10 )*(pixel_x-cir_x-104 -10 )+(pixel_y-23-cir_y -10)*(pixel_y-23-cir_y -10)<=100)? tp4_color : BACKGROUND_color; else if( (less_number<20) && (pixel_x >= cir1_x + 104 ) && (pixel_x < cir1_x + 104 + 20 ) && (pixel_y >= cir1_y + 23) && (pixel_y < cir1_y + 23 + 20 )) {R,G,B} <= ((pixel_x-cir1_x-104 - 10)*(pixel_x-cir1_x-104 -10)+(pixel_y-23-cir1_y -10)*(pixel_y-23-cir1_y -10)<=100)? tp5_color : BACKGROUND_color; else if(less_number==20) begin if( (pixel_x >= 104 + 100) && (pixel_x < 104+700) && (pixel_y >= 23 + 50) && (pixel_y < 623 -50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLUE; if( (pixel_x >= 104 +375 ) && (pixel_x < 104 + 375 + 50) && (pixel_y >= 23 +175) && (pixel_y < 23 + 225 )) {R,G,B} <= ((pixel_x-104-375 - 25 )*(pixel_x-104-375 -25 )+(pixel_y-23-175 -25)*(pixel_y-23-175 -25)<=625)? BLACK : WHITE; else if( (pixel_x >= 104 +375) && (pixel_x < 104 + 375 +50 ) && (pixel_y >= 23 +275) && (pixel_y < + 23 + 325) ) {R,G,B} <= BLACK; else if( (pixel_x >= 104 +375) && (pixel_x < 104 + 375 +50 ) && (pixel_y >= 23 +375) && (pixel_y < + 23 + 425) ) {R,G,B} <= ((pixel_y - 23-375 <= 2*(pixel_x - 104 -375 )) && (pixel_y - 23 -375 <= -2*(pixel_x - 104 -375 )+100) )? BLACK : WHITE; if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +100) && (pixel_y < 23 + 150 -15+100) ) begin case(cirr) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100) && (pixel_y < 23 + 150 -15 -10+100) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100) && (pixel_y < 23 + 150 -15+100 ) ) {R,G,B} <= BLACK; else {R,G,B} <= WHITE; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15+100) && (pixel_y < 23 + 150 -15 - 40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100) && (pixel_y < 23 + 150 -15 -40+100)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10+100) && (pixel_y < 23 + 150 -15+100) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100) && (pixel_y < 23 + 150 -15-40+100)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15 -10+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100) && (pixel_y < 23 + 150 -15-40+100)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100) && (pixel_y < 23 + 150 -15+100)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end endcase end if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +100+50+50) && (pixel_y < 23 + 150 -15+100+50+50) ) begin case(rectt) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50 ) ) {R,G,B} <= BLACK; else {R,G,B} <= WHITE; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15+100+50+50) && (pixel_y < 23 + 150 -15 - 40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50) && (pixel_y < 23 + 150 -15+100+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end endcase end if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50) ) begin case(trii) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50 ) ) {R,G,B} <= BLACK; else {R,G,B} <= WHITE; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15+100+50+50+50+50) && (pixel_y < 23 + 150 -15 - 40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15 -10+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10+100+50+50+50+50) && (pixel_y < 23 + 150 -15-40+100+50+50+50+50)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40+100+50+50+50+50) && (pixel_y < 23 + 150 -15+100+50+50+50+50)) ) {R,G,B} <= WHITE; else {R,G,B} <= BLACK; end endcase end end else if((pixel_x >= 104 + 600) && (pixel_x < 104 + 750) && (pixel_y >= 23 + 50) && (pixel_y < 23 + 150) ) begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15) ) begin case(less_num2) 0:begin if((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15 -10) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +20 + 25) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 ) ) {R,G,B} <= BLACK; else {R,G,B} <= CYAN; end 2:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10) && (pixel_x < 104 + 600 +55 - 10) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 - 40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20 +10) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10) && (pixel_x < 104 + 600 +55-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20) && (pixel_x < 104 + 600 +55 -10) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end endcase end else {R,G,B} <= CYAN; if((pixel_x >= 104 + 600 +95) && (pixel_x < 104 + 600 +130) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15) ) begin case(less_num1) 0:begin if((pixel_x >= 104 + 600 +95 + 10) && (pixel_x < 104 + 600 +130-10) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15 -10) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 1:begin if((pixel_x >= 104 + 600 +95 + 25) && (pixel_x < 104 + 600 +130) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 ) ) {R,G,B} <= BLACK; else {R,G,B} <= CYAN; end 2:begin if( ((pixel_x >= 104 + 600 +20 + 75) && (pixel_x < 104 + 600 +55 - 10 +75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10 +75) && (pixel_x < 104 + 600 +55 +75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 3:begin if( ((pixel_x >= 104 + 600 +20 +75) && (pixel_x < 104 + 600 +55 - 10 +75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +75) && (pixel_x < 104 + 600 +55 -10 +75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 4:begin if( ((pixel_x >= 104 + 600 +20 + 10+75) && (pixel_x < 104 + 600 +55 - 10 +75) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 - 40)) || ((pixel_x >= 104 + 600 +20 +75) && (pixel_x < 104 + 600 +55 -10 +75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 5:begin if( ((pixel_x >= 104 + 600 +20+10+75) && (pixel_x < 104 + 600 +55+75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 6:begin if( ((pixel_x >= 104 + 600 +20 +10+75) && (pixel_x < 104 + 600 +55+75) && (pixel_y >= 23 + 50 +15) && (pixel_y < 23 + 150 -15 -40)) || ((pixel_x >= 104 + 600 +20 +10+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 7:begin if( (pixel_x >= 104 + 600 +20+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +10) && (pixel_y < 23 + 150 -15) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 8:begin if( ((pixel_x >= 104 + 600 +20+10+75) && (pixel_x < 104 + 600 +55-10+75) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20 +10+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15 -10)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end 9:begin if( ((pixel_x >= 104 + 600 +20+10+75) && (pixel_x < 104 + 600 +55-10+75) && (pixel_y >= 23 + 50 +15+10) && (pixel_y < 23 + 150 -15-40)) || ((pixel_x >= 104 + 600 +20+75) && (pixel_x < 104 + 600 +55 -10+75) && (pixel_y >= 23 + 50 +15 +40) && (pixel_y < 23 + 150 -15)) ) {R,G,B} <= CYAN; else {R,G,B} <= BLACK; end endcase end end else if((pixel_x >= 104 + 30 + GP_x) && (pixel_x < 104 + 62 + GP_x) && (pixel_y >= 23 + 518) && (pixel_y < 23 + 550)) begin if( (pixel_x-104-30-GP_x -16)*(pixel_x-104-30-GP_x -16)+(pixel_y-23-518 -16)*(pixel_y-23-518 -16) <= 256 ) begin if( (pixel_y - 23 -518<= (pixel_x - 104 - 30 - GP_x)) && (pixel_y - 23 - 518) <= -1*(pixel_x - 104 - 30 - GP_x)+32 ) begin if(GPopen) {R,G,B} <= RED; else {R,G,B} <= GP_color; end else {R,G,B} <= GP_color; end else {R,G,B} <= BACKGROUND_color; end else {R,G,B} <= BACKGROUND_color; end else {R,G,B} <= DEFAULT; end end else {R,G,B} <= DEFAULT; end endmodule

data/full_repos/permissive/98767051/led.v

led.v

v

[]

[]

[]

[Errno 2] No such file or directory: 'preprocess.output'

1: b"%Error: data/full_repos/permissive/98767051/led.v:34: syntax error, unexpected <=, expecting '='\nassign led_flash <= led_temp;\n ^~\n%Error: Exiting due to 1 error(s)\n"

module

module led( input clk, input rst_n, output led_flash ); reg [31:0] cnt; reg led_temp; always@(posedge clk, negedge rst_n) begin if(~rst_n) begin cnt <= 32'd0; end else if(cnt == 32'd49_999_999) begin cnt <= 32'd0; end else begin cnt <= cnt + 32'd1; end end always@(posedge clk, negedge rst_n) begin if(~rst_n) begin led_temp <= 1'd0; end else if(cnt == 32'd49_999_999) begin led_temp <= ~led_temp; end else begin led_temp <= led_temp; end end assign led_flash <= led_temp; endmodule

module led( input clk, input rst_n, output led_flash );

reg [31:0] cnt; reg led_temp; always@(posedge clk, negedge rst_n) begin if(~rst_n) begin cnt <= 32'd0; end else if(cnt == 32'd49_999_999) begin cnt <= 32'd0; end else begin cnt <= cnt + 32'd1; end end always@(posedge clk, negedge rst_n) begin if(~rst_n) begin led_temp <= 1'd0; end else if(cnt == 32'd49_999_999) begin led_temp <= ~led_temp; end else begin led_temp <= led_temp; end end assign led_flash <= led_temp; endmodule

data/full_repos/permissive/9877430/rtl/gci_std_display.v

gci_std_display.v

v

[]

[]

[]

[(49, 218)]

1: b"%Error: data/full_repos/permissive/9877430/rtl/gci_std_display.v:132: Cannot find file containing module: 'gci_std_display_device_special_memory'\n gci_std_display_device_special_memory #(32'h001383FC + 32'h4, 32'h00000000, 32'h00000002) VGA640X480_60HZ_SPECIAL_MEM(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl,data/full_repos/permissive/9877430/gci_std_display_device_special_memory\n data/full_repos/permissive/9877430/rtl,data/full_repos/permissive/9877430/gci_std_display_device_special_memory.v\n data/full_repos/permissive/9877430/rtl,data/full_repos/permissive/9877430/gci_std_display_device_special_memory.sv\n gci_std_display_device_special_memory\n gci_std_display_device_special_memory.v\n gci_std_display_device_special_memory.sv\n obj_dir/gci_std_display_device_special_memory\n obj_dir/gci_std_display_device_special_memory.v\n obj_dir/gci_std_display_device_special_memory.sv\n%Error: data/full_repos/permissive/9877430/rtl/gci_std_display.v:145: Cannot find file containing module: 'gci_std_display_display_controller'\n gci_std_display_display_controller DISPLAY_MODULE(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"

module

module gci_std_display( input wire iCLOCK, input wire inRESET, input wire iDEV_REQ, output wire oDEV_BUSY, input wire iDEV_RW, input wire [31:0] iDEV_ADDR, input wire [31:0] iDEV_DATA, output wire oDEV_REQ, input wire iDEV_BUSY, output wire [31:0] oDEV_DATA, output wire oDEV_IRQ_REQ, input wire iDEV_IRQ_BUSY, output wire [23:0] oDEV_IRQ_DATA, input wire iDEV_IRQ_ACK, input wire iVGA_CLOCK, `ifdef GCI_STD_DISPLAY_SRAM output wire onSRAM_CE, output wire onSRAM_WE, output wire onSRAM_OE, output wire onSRAM_UB, output wire onSRAM_LB, output wire [19:0] oSRAM_ADDR, inout wire [15:0] ioSRAM_DATA, `elsif GCI_STD_DISPLAY_SSRAM output wire oSSRAM_CLOCK, output wire onSSRAM_ADSC, output wire onSSRAM_ADSP, output wire onSSRAM_ADV, output wire onSSRAM_GW, output wire onSSRAM_OE, output wire onSSRAM_WE, output wire [3:0] onSSRAM_BE, output wire onSSRAM_CE1, output wire oSSRAM_CE2, output wire onSSRAM_CE3, output wire [18:0] oSSRAM_ADDR, inout wire [31:0] ioSSRAM_DATA, inout wire [3:0] ioSSRAM_PARITY, `endif output wire oDISP_CLOCK, output wire onDISP_RESET, output wire oDISP_ENA, output wire oDISP_BLANK, output wire onDISP_HSYNC, output wire onDISP_VSYNC, output wire [9:0] oDISP_DATA_R, output wire [9:0] oDISP_DATA_G, output wire [9:0] oDISP_DATA_B ); wire displaycontroller_wait; wire special_addr_use_condition; wire display_addr_wr_condition; wire [31:0] special_memory_rd_data; reg b_req; reg [31:0] b_data; assign special_addr_use_condition = iDEV_REQ && (iDEV_ADDR < 32'h00000400) && !displaycontroller_wait; assign display_addr_wr_condition = iDEV_REQ && (iDEV_ADDR >= 32'h00000400) && !displaycontroller_wait; gci_std_display_device_special_memory #(32'h001383FC + 32'h4, 32'h00000000, 32'h00000002) VGA640X480_60HZ_SPECIAL_MEM( .iCLOCK(iCLOCK), .inRESET(inRESET), .iSPECIAL_REQ(special_addr_use_condition), .iSPECIAL_RW(iDEV_RW), .iSPECIAL_ADDR(iDEV_ADDR[9:2]), .iSPECIAL_DATA(iDEV_DATA), .oSPECIAL_DATA(special_memory_rd_data) ); gci_std_display_display_controller DISPLAY_MODULE( .iCLOCK(iCLOCK), .inRESET(inRESET), .iDISP_CLOCK(iVGA_CLOCK), .iIF_WR_REQ(display_addr_wr_condition), .oIF_WR_BUSY(displaycontroller_wait), .iIF_WR_ADDR({2'h0, iDEV_ADDR[31:2]}), .iIF_WR_DATA(iDEV_DATA), `ifdef GCI_STD_DISPLAY_SRAM .onSRAM_CE(onSRAM_CE), .onSRAM_WE(onSRAM_WE), .onSRAM_OE(onSRAM_OE), .onSRAM_UB(onSRAM_UB), .onSRAM_LB(onSRAM_LB), .oSRAM_ADDR(oSRAM_ADDR), .ioSRAM_DATA(ioSRAM_DATA), `elsif GCI_STD_DISPLAY_SSRAM .oSSRAM_CLOCK(oSSRAM_CLOCK), .onSSRAM_ADSC(onSSRAM_ADSC), .onSSRAM_ADSP(onSSRAM_ADSP), .onSSRAM_ADV(onSSRAM_ADV), .onSSRAM_GW(onSSRAM_GW), .onSSRAM_OE(onSSRAM_OE), .onSSRAM_WE(onSSRAM_WE), .onSSRAM_BE(onSSRAM_BE), .onSSRAM_CE1(onSSRAM_CE1), .oSSRAM_CE2(oSSRAM_CE2), .onSSRAM_CE3(onSSRAM_CE3), .oSSRAM_ADDR(oSSRAM_ADDR), .ioSSRAM_DATA(ioSSRAM_DATA), .ioSSRAM_PARITY(ioSSRAM_PARITY), `endif .oDISP_CLOCK(oDISP_CLOCK), .onDISP_RESET(onDISP_RESET), .oDISP_ENA(oDISP_ENA), .oDISP_BLANK(oDISP_BLANK), .onDISP_HSYNC(onDISP_HSYNC), .onDISP_VSYNC(onDISP_VSYNC), .oDISP_DATA_R(oDISP_DATA_R), .oDISP_DATA_G(oDISP_DATA_G), .oDISP_DATA_B(oDISP_DATA_B) ); always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_req <= 1'b0; b_data <= {32{1'b0}}; end else begin b_req <= (special_addr_use_condition || display_addr_wr_condition); b_data <= (special_addr_use_condition)? special_memory_rd_data : {32{1'b0}}; end end assign oDEV_BUSY = displaycontroller_wait; assign oDEV_REQ = b_req; assign oDEV_DATA = b_data; assign oDEV_IRQ_REQ = 1'b0; assign oDEV_IRQ_DATA = {24{1'b0}}; endmodule

module gci_std_display( input wire iCLOCK, input wire inRESET, input wire iDEV_REQ, output wire oDEV_BUSY, input wire iDEV_RW, input wire [31:0] iDEV_ADDR, input wire [31:0] iDEV_DATA, output wire oDEV_REQ, input wire iDEV_BUSY, output wire [31:0] oDEV_DATA, output wire oDEV_IRQ_REQ, input wire iDEV_IRQ_BUSY, output wire [23:0] oDEV_IRQ_DATA, input wire iDEV_IRQ_ACK, input wire iVGA_CLOCK, `ifdef GCI_STD_DISPLAY_SRAM output wire onSRAM_CE, output wire onSRAM_WE, output wire onSRAM_OE, output wire onSRAM_UB, output wire onSRAM_LB, output wire [19:0] oSRAM_ADDR, inout wire [15:0] ioSRAM_DATA, `elsif GCI_STD_DISPLAY_SSRAM output wire oSSRAM_CLOCK, output wire onSSRAM_ADSC, output wire onSSRAM_ADSP, output wire onSSRAM_ADV, output wire onSSRAM_GW, output wire onSSRAM_OE, output wire onSSRAM_WE, output wire [3:0] onSSRAM_BE, output wire onSSRAM_CE1, output wire oSSRAM_CE2, output wire onSSRAM_CE3, output wire [18:0] oSSRAM_ADDR, inout wire [31:0] ioSSRAM_DATA, inout wire [3:0] ioSSRAM_PARITY, `endif output wire oDISP_CLOCK, output wire onDISP_RESET, output wire oDISP_ENA, output wire oDISP_BLANK, output wire onDISP_HSYNC, output wire onDISP_VSYNC, output wire [9:0] oDISP_DATA_R, output wire [9:0] oDISP_DATA_G, output wire [9:0] oDISP_DATA_B );

wire displaycontroller_wait; wire special_addr_use_condition; wire display_addr_wr_condition; wire [31:0] special_memory_rd_data; reg b_req; reg [31:0] b_data; assign special_addr_use_condition = iDEV_REQ && (iDEV_ADDR < 32'h00000400) && !displaycontroller_wait; assign display_addr_wr_condition = iDEV_REQ && (iDEV_ADDR >= 32'h00000400) && !displaycontroller_wait; gci_std_display_device_special_memory #(32'h001383FC + 32'h4, 32'h00000000, 32'h00000002) VGA640X480_60HZ_SPECIAL_MEM( .iCLOCK(iCLOCK), .inRESET(inRESET), .iSPECIAL_REQ(special_addr_use_condition), .iSPECIAL_RW(iDEV_RW), .iSPECIAL_ADDR(iDEV_ADDR[9:2]), .iSPECIAL_DATA(iDEV_DATA), .oSPECIAL_DATA(special_memory_rd_data) ); gci_std_display_display_controller DISPLAY_MODULE( .iCLOCK(iCLOCK), .inRESET(inRESET), .iDISP_CLOCK(iVGA_CLOCK), .iIF_WR_REQ(display_addr_wr_condition), .oIF_WR_BUSY(displaycontroller_wait), .iIF_WR_ADDR({2'h0, iDEV_ADDR[31:2]}), .iIF_WR_DATA(iDEV_DATA), `ifdef GCI_STD_DISPLAY_SRAM .onSRAM_CE(onSRAM_CE), .onSRAM_WE(onSRAM_WE), .onSRAM_OE(onSRAM_OE), .onSRAM_UB(onSRAM_UB), .onSRAM_LB(onSRAM_LB), .oSRAM_ADDR(oSRAM_ADDR), .ioSRAM_DATA(ioSRAM_DATA), `elsif GCI_STD_DISPLAY_SSRAM .oSSRAM_CLOCK(oSSRAM_CLOCK), .onSSRAM_ADSC(onSSRAM_ADSC), .onSSRAM_ADSP(onSSRAM_ADSP), .onSSRAM_ADV(onSSRAM_ADV), .onSSRAM_GW(onSSRAM_GW), .onSSRAM_OE(onSSRAM_OE), .onSSRAM_WE(onSSRAM_WE), .onSSRAM_BE(onSSRAM_BE), .onSSRAM_CE1(onSSRAM_CE1), .oSSRAM_CE2(oSSRAM_CE2), .onSSRAM_CE3(onSSRAM_CE3), .oSSRAM_ADDR(oSSRAM_ADDR), .ioSSRAM_DATA(ioSSRAM_DATA), .ioSSRAM_PARITY(ioSSRAM_PARITY), `endif .oDISP_CLOCK(oDISP_CLOCK), .onDISP_RESET(onDISP_RESET), .oDISP_ENA(oDISP_ENA), .oDISP_BLANK(oDISP_BLANK), .onDISP_HSYNC(onDISP_HSYNC), .onDISP_VSYNC(onDISP_VSYNC), .oDISP_DATA_R(oDISP_DATA_R), .oDISP_DATA_G(oDISP_DATA_G), .oDISP_DATA_B(oDISP_DATA_B) ); always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_req <= 1'b0; b_data <= {32{1'b0}}; end else begin b_req <= (special_addr_use_condition || display_addr_wr_condition); b_data <= (special_addr_use_condition)? special_memory_rd_data : {32{1'b0}}; end end assign oDEV_BUSY = displaycontroller_wait; assign oDEV_REQ = b_req; assign oDEV_DATA = b_data; assign oDEV_IRQ_REQ = 1'b0; assign oDEV_IRQ_DATA = {24{1'b0}}; endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_character.v

gci_std_display_character.v

v

[]

[]

[]

line:134: before: "="

1: b"%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_character.v:134: syntax error, unexpected '=', expecting ',' or ';'\n assign oIF_ADDR = charact_addr = b_charact_base_addr[13:8]*(640*14) + (b_charact_counter/8)*640 + b_charact_base_addr[7:0]*8 + b_charact_counter[2:0];;\n ^\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_character.v:138: syntax error, unexpected ')'\n );\n ^\n%Error: Exiting due to 2 error(s)\n"

module

module gci_std_display_character #( parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_AREAA_HV_N = 19, parameter P_MEM_ADDR_N = 23 )( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF_VALID, output wire oIF_BUSY, input wire [13:0] iIF_ADDR, input wire [31:0] iIF_DATA, output wire oIF_FINISH, output wire oIF_VALID, input wire iIF_BUSY, output wire [P_MEM_ADDR_N-1:0] oIF_ADDR, output wire [23:0] oIF_DATA ); localparam P_L_CHARACT_STT_IDLE = 2'h0; localparam P_L_CHARACT_STT_OUT = 2'h1; localparam P_L_CHARACT_STT_END = 2'h2; reg [1:0] b_charact_state; reg [7:0] b_charact_font_color_r; reg [7:0] b_charact_font_color_g; reg [7:0] b_charact_font_color_b; reg [7:0] b_charact_back_color_r; reg [7:0] b_charact_back_color_g; reg [7:0] b_charact_back_color_b; reg [13:0] b_charact_base_addr; reg [6:0] b_charact_font; reg [P_AREAA_HV_N-1:0] b_charact_counter; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_charact_state <= P_L_CHARACT_STT_IDLE; b_charact_font_color_r <= 8'h0; b_charact_font_color_g <= 8'h0; b_charact_font_color_b <= 8'h0; b_charact_back_color_r <= 8'h0; b_charact_back_color_g <= 8'h0; b_charact_back_color_b <= 8'h0; b_charact_base_addr <= 14'h0; b_charact_font <= 7'h0; end else if(iRESET_SYNC)begin b_charact_state <= P_L_CHARACT_STT_IDLE; b_charact_font_color_r <= 8'h0; b_charact_font_color_g <= 8'h0; b_charact_font_color_b <= 8'h0; b_charact_back_color_r <= 8'h0; b_charact_back_color_g <= 8'h0; b_charact_back_color_b <= 8'h0; b_charact_base_addr <= 14'h0; b_charact_font <= 7'h0; end else begin case(b_charact_state) P_L_CHARACT_STT_IDLE: begin if(iIF_VALID)begin b_charact_state <= P_L_CHARACT_STT_OUT; {b_charact_font_color_r, b_charact_font_color_g, b_charact_font_color_b} <= {iIF_DATA[19:16], iIF_DATA[16], iIF_DATA[15:12], {2{iIF_DATA[12]}}, iIF_DATA[11:8], iIF_DATA[8]}; {b_charact_back_color_r, b_charact_back_color_g, b_charact_back_color_b} <= {iIF_DATA[31:28], iIF_DATA[28], iIF_DATA[27:24], {2{iIF_DATA[24]}}, iIF_DATA[23:20], iIF_DATA[20]}; b_charact_base_addr <= iIF_ADDR; b_charact_font <= iIF_DATA[6:0]; end end P_L_CHARACT_STT_OUT: begin if(b_charact_counter == 7'd112)begin b_charact_state <= P_L_CHARACT_STT_END; end end P_L_CHARACT_STT_END: begin b_charact_state <= P_L_CLEAR_STT_IDLE; end default: begin b_charact_state <= P_L_CLEAR_STT_IDLE; end endcase end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_charact_counter <= 7'h0; end else if(iRESET_SYNC)begin b_charact_counter <= 7'h0; end else begin if(b_charact_state == P_L_CHARACT_STT_OUT)begin if(!iIF_BUSY)begin b_charact_counter <= b_charact_counter + 7'h1; end end else begin b_charact_counter <= 7'h0; end end end wire [111:0] font_rom_data; gci_std_display_font FONT14X8( .iADDR(b_charact_font), .oDATA(font_rom_data) ); assign oIF_BUSY = b_charact_state != P_L_CHARACT_STT_IDLE; assign oIF_FINISH = b_charact_state == P_L_CHARACT_STT_END; assign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR || b_charact_state == P_L_CHARACT_STT_OUT); assign oIF_ADDR = charact_addr = b_charact_base_addr[13:8]*(640*14) + (b_charact_counter/8)*640 + b_charact_base_addr[7:0]*8 + b_charact_counter[2:0];; assign oIF_DATA = ((font_rom_data[7'd111 - b_charact_counter + 7'h01])? ( {b_charact_font_color_r, b_charact_font_color_g, b_charact_font_color_b} : {b_charact_back_color_r, b_charact_back_color_g, b_charact_back_color_b} ); endmodule

module gci_std_display_character #( parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_AREAA_HV_N = 19, parameter P_MEM_ADDR_N = 23 )( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF_VALID, output wire oIF_BUSY, input wire [13:0] iIF_ADDR, input wire [31:0] iIF_DATA, output wire oIF_FINISH, output wire oIF_VALID, input wire iIF_BUSY, output wire [P_MEM_ADDR_N-1:0] oIF_ADDR, output wire [23:0] oIF_DATA );

localparam P_L_CHARACT_STT_IDLE = 2'h0; localparam P_L_CHARACT_STT_OUT = 2'h1; localparam P_L_CHARACT_STT_END = 2'h2; reg [1:0] b_charact_state; reg [7:0] b_charact_font_color_r; reg [7:0] b_charact_font_color_g; reg [7:0] b_charact_font_color_b; reg [7:0] b_charact_back_color_r; reg [7:0] b_charact_back_color_g; reg [7:0] b_charact_back_color_b; reg [13:0] b_charact_base_addr; reg [6:0] b_charact_font; reg [P_AREAA_HV_N-1:0] b_charact_counter; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_charact_state <= P_L_CHARACT_STT_IDLE; b_charact_font_color_r <= 8'h0; b_charact_font_color_g <= 8'h0; b_charact_font_color_b <= 8'h0; b_charact_back_color_r <= 8'h0; b_charact_back_color_g <= 8'h0; b_charact_back_color_b <= 8'h0; b_charact_base_addr <= 14'h0; b_charact_font <= 7'h0; end else if(iRESET_SYNC)begin b_charact_state <= P_L_CHARACT_STT_IDLE; b_charact_font_color_r <= 8'h0; b_charact_font_color_g <= 8'h0; b_charact_font_color_b <= 8'h0; b_charact_back_color_r <= 8'h0; b_charact_back_color_g <= 8'h0; b_charact_back_color_b <= 8'h0; b_charact_base_addr <= 14'h0; b_charact_font <= 7'h0; end else begin case(b_charact_state) P_L_CHARACT_STT_IDLE: begin if(iIF_VALID)begin b_charact_state <= P_L_CHARACT_STT_OUT; {b_charact_font_color_r, b_charact_font_color_g, b_charact_font_color_b} <= {iIF_DATA[19:16], iIF_DATA[16], iIF_DATA[15:12], {2{iIF_DATA[12]}}, iIF_DATA[11:8], iIF_DATA[8]}; {b_charact_back_color_r, b_charact_back_color_g, b_charact_back_color_b} <= {iIF_DATA[31:28], iIF_DATA[28], iIF_DATA[27:24], {2{iIF_DATA[24]}}, iIF_DATA[23:20], iIF_DATA[20]}; b_charact_base_addr <= iIF_ADDR; b_charact_font <= iIF_DATA[6:0]; end end P_L_CHARACT_STT_OUT: begin if(b_charact_counter == 7'd112)begin b_charact_state <= P_L_CHARACT_STT_END; end end P_L_CHARACT_STT_END: begin b_charact_state <= P_L_CLEAR_STT_IDLE; end default: begin b_charact_state <= P_L_CLEAR_STT_IDLE; end endcase end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_charact_counter <= 7'h0; end else if(iRESET_SYNC)begin b_charact_counter <= 7'h0; end else begin if(b_charact_state == P_L_CHARACT_STT_OUT)begin if(!iIF_BUSY)begin b_charact_counter <= b_charact_counter + 7'h1; end end else begin b_charact_counter <= 7'h0; end end end wire [111:0] font_rom_data; gci_std_display_font FONT14X8( .iADDR(b_charact_font), .oDATA(font_rom_data) ); assign oIF_BUSY = b_charact_state != P_L_CHARACT_STT_IDLE; assign oIF_FINISH = b_charact_state == P_L_CHARACT_STT_END; assign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR || b_charact_state == P_L_CHARACT_STT_OUT); assign oIF_ADDR = charact_addr = b_charact_base_addr[13:8]*(640*14) + (b_charact_counter/8)*640 + b_charact_base_addr[7:0]*8 + b_charact_counter[2:0];; assign oIF_DATA = ((font_rom_data[7'd111 - b_charact_counter + 7'h01])? ( {b_charact_font_color_r, b_charact_font_color_g, b_charact_font_color_b} : {b_charact_back_color_r, b_charact_back_color_g, b_charact_back_color_b} ); endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_device_special_memory.v

gci_std_display_device_special_memory.v

v

[]

[]

[]

[(12, 59)]

1: b'%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_device_special_memory.v:51: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'iSPECIAL_ADDR\' generates 8 bits.\n : ... In instance gci_std_display_device_special_memory\n b_mem [iSPECIAL_ADDR] <= iSPECIAL_ADDR;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'

module

module gci_std_display_device_special_memory #( parameter USEMEMSIZE = 32'h00000000, parameter PRIORITY = 32'h00000000, parameter DEVICECAT = 32'h00000000 )( input wire iCLOCK, input wire inRESET, input wire iSPECIAL_REQ, input wire iSPECIAL_RW, input wire [7:0] iSPECIAL_ADDR, input wire [31:0] iSPECIAL_DATA, output wire [31:0] oSPECIAL_DATA ); integer i; reg [31:0] b_mem[0:255]; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin for(i = 0; i < 256; i = i + 1)begin if(i == 0)begin b_mem[i] <= USEMEMSIZE; end else if(i == 1)begin b_mem[i] <= PRIORITY; end else begin b_mem[i] <= 32'h00000000; end end end else begin if(iSPECIAL_REQ && iSPECIAL_RW)begin b_mem [iSPECIAL_ADDR] <= iSPECIAL_ADDR; end end end assign oSPECIAL_DATA = b_mem[iSPECIAL_ADDR]; endmodule

module gci_std_display_device_special_memory #( parameter USEMEMSIZE = 32'h00000000, parameter PRIORITY = 32'h00000000, parameter DEVICECAT = 32'h00000000 )( input wire iCLOCK, input wire inRESET, input wire iSPECIAL_REQ, input wire iSPECIAL_RW, input wire [7:0] iSPECIAL_ADDR, input wire [31:0] iSPECIAL_DATA, output wire [31:0] oSPECIAL_DATA );

integer i; reg [31:0] b_mem[0:255]; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin for(i = 0; i < 256; i = i + 1)begin if(i == 0)begin b_mem[i] <= USEMEMSIZE; end else if(i == 1)begin b_mem[i] <= PRIORITY; end else begin b_mem[i] <= 32'h00000000; end end end else begin if(iSPECIAL_REQ && iSPECIAL_RW)begin b_mem [iSPECIAL_ADDR] <= iSPECIAL_ADDR; end end end assign oSPECIAL_DATA = b_mem[iSPECIAL_ADDR]; endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_font.v

gci_std_display_font.v

v

[]

[]

[]

[(3, 113)]

1: b'%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_font.v:111: Operator FUNCREF \'rom\' expects 7 bits on the Function Argument, but Function Argument\'s SUB generates 8 bits.\n : ... In instance gci_std_display_font\n assign oDATA = rom(iADDR - 8\'h20); \n ^~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'

module

module gci_std_display_font( input wire [6:0] iADDR, output wire [111:0] oDATA ); function [111:0] rom; input [6:0] funcADDR; begin case(funcADDR) 7'd0: rom = 112'h0000000000000000000000000000; 7'd1: rom = 112'h0000181818181010100000181800; 7'd2: rom = 112'h006c6c2448000000000000000000; 7'd3: rom = 112'h00002424247e2424487e48484800; 7'd4: rom = 112'h0000103c525250381452523c1000; 7'd5: rom = 112'h0000225254542818142a2a4A4400; 7'd6: rom = 112'h0000102828102652524c442a1000; 7'd7: rom = 112'h0030301020000000000000000000; 7'd8: rom = 112'h0004081010202020202010100804; 7'd9: rom = 112'h0020100808040404040408081020; 7'd10: rom = 112'h0000001010d6543854d610100000; 7'd11: rom = 112'h000000101010107e101010100000; 7'd12: rom = 112'h0000000000000000000030301020; 7'd13: rom = 112'h000000000000007e000000000000; 7'd14: rom = 112'h0000000000000000000000303000; 7'd15: rom = 112'h0202040408081010202040408080; 7'd16: rom = 112'h0000182424424242411224180000; 7'd17: rom = 112'h00001070101010101010107c0000; 7'd18: rom = 112'h00001824422204081020227e0000; 7'd19: rom = 112'h0000182442441804424112180000; 7'd20: rom = 112'h0000040C141424247e04040e0000; 7'd21: rom = 112'h00007c4040586442024112180000; 7'd22: rom = 112'h00001c1122586442424112180000; 7'd23: rom = 112'h00003e1122040408080808080000; 7'd24: rom = 112'h0000182441121824424112180000; 7'd25: rom = 112'h000018244242261a024424180000; 7'd26: rom = 112'h0000000018180000001818000000; 7'd27: rom = 112'h0000000018180000001818081000; 7'd28: rom = 112'h0000020408102040201008040200; 7'd29: rom = 112'h000000007e0000007E0000000000; 7'd30: rom = 112'h0000402010080402040810204000; 7'd31: rom = 112'h0000182442420408101000181800; 7'd32: rom = 112'h00001824112A5656564A20221C00; 7'd33: rom = 112'h00001010282828247c4444ee0000; 7'd34: rom = 112'h0000782424283c22222112780000; 7'd35: rom = 112'h00001a2611224040402226180000; 7'd36: rom = 112'h0000782424222222211224780000; 7'd37: rom = 112'h00007c2220243c242020227e0000; 7'd38: rom = 112'h00007c2220243c24202020780000; 7'd39: rom = 112'h00001a261122404e4222261a0000; 7'd40: rom = 112'h0000ee4444447c44444444ee0000; 7'd41: rom = 112'h00007c10101010101010107c0000; 7'd42: rom = 112'h00001e0404040404444448300000; 7'd43: rom = 112'h00006e2428283028242422760000; 7'd44: rom = 112'h00007020202020202020227c0000; 7'd45: rom = 112'h00004266666a5a52524242660000; 7'd46: rom = 112'h000046626252524A4a4646620000; 7'd47: rom = 112'h0000182442424242424112180000; 7'd48: rom = 112'h0000782422211238202020700000; 7'd49: rom = 112'h0000182442424242724e24180600; 7'd50: rom = 112'h0000782422211238282424720000; 7'd51: rom = 112'h00001a2642201804024264580000; 7'd52: rom = 112'h00007e5210101010101010380000; 7'd53: rom = 112'h0000762222222222222214080000; 7'd54: rom = 112'h0000664112242428181010100000; 7'd55: rom = 112'h0000929292525A6A6c2424240000; 7'd56: rom = 112'h00006244242810182824444e0000; 7'd57: rom = 112'h0000e64112281810101010380000; 7'd58: rom = 112'h00003e44040808102020427c0000; 7'd59: rom = 112'h003c20202020202020202020203C; 7'd60: rom = 112'h8080404020201010080804040202; 7'd61: rom = 112'h003c04040404040404040404043C; 7'd62: rom = 112'h0010284482000000000000000000; 7'd63: rom = 112'h00000000000000000000000000FE; 7'd64: rom = 112'h0018181008000000000000000000; 7'd65: rom = 112'h000000003844441c2444443a0000; 7'd66: rom = 112'h0000602028342222222112380000; 7'd67: rom = 112'h000000001a264240404226180000; 7'd68: rom = 112'h00000c04142c44444444241e0000; 7'd69: rom = 112'h000000001824427e4042221c0000; 7'd70: rom = 112'h00000c12127c1010101010380000; 7'd71: rom = 112'h000000001a24242418205c42423C; 7'd72: rom = 112'h0000c04050684444444444c60000; 7'd73: rom = 112'h00001818003808080808083c0000; 7'd74: rom = 112'h00000c0c001c0404040404444830; 7'd75: rom = 112'h0000c04046444858684444ce0000; 7'd76: rom = 112'h00003808080808080808083e0000; 7'd77: rom = 112'h00000000acd29292929292920000; 7'd78: rom = 112'h00000000d8644444444444c60000; 7'd79: rom = 112'h0000000018244242424112180000; 7'd80: rom = 112'h0000000058242222222112382070; 7'd81: rom = 112'h000000001a2444444444241c040E; 7'd82: rom = 112'h000000005c222220202020700000; 7'd83: rom = 112'h000000003c4440300c42625c0000; 7'd84: rom = 112'h00001010107c10101010120c0000; 7'd85: rom = 112'h00000000cc44444444444c320000; 7'd86: rom = 112'h0000000066424424281810100000; 7'd87: rom = 112'h00000000929292925A6c24240000; 7'd88: rom = 112'h0000000066242818181424660000; 7'd89: rom = 112'h0000000066222214140808485020; 7'd90: rom = 112'h000000003e4408081010227e0000; 7'd91: rom = 112'h0006081010101020101010100806; 7'd92: rom = 112'h0010101010101010101010101010; 7'd93: rom = 112'h0060100808080804080808081060; default: rom = 112'h0000000000000000000000000000; endcase end endfunction assign oDATA = rom(iADDR - 8'h20); endmodule

module gci_std_display_font( input wire [6:0] iADDR, output wire [111:0] oDATA );

function [111:0] rom; input [6:0] funcADDR; begin case(funcADDR) 7'd0: rom = 112'h0000000000000000000000000000; 7'd1: rom = 112'h0000181818181010100000181800; 7'd2: rom = 112'h006c6c2448000000000000000000; 7'd3: rom = 112'h00002424247e2424487e48484800; 7'd4: rom = 112'h0000103c525250381452523c1000; 7'd5: rom = 112'h0000225254542818142a2a4A4400; 7'd6: rom = 112'h0000102828102652524c442a1000; 7'd7: rom = 112'h0030301020000000000000000000; 7'd8: rom = 112'h0004081010202020202010100804; 7'd9: rom = 112'h0020100808040404040408081020; 7'd10: rom = 112'h0000001010d6543854d610100000; 7'd11: rom = 112'h000000101010107e101010100000; 7'd12: rom = 112'h0000000000000000000030301020; 7'd13: rom = 112'h000000000000007e000000000000; 7'd14: rom = 112'h0000000000000000000000303000; 7'd15: rom = 112'h0202040408081010202040408080; 7'd16: rom = 112'h0000182424424242411224180000; 7'd17: rom = 112'h00001070101010101010107c0000; 7'd18: rom = 112'h00001824422204081020227e0000; 7'd19: rom = 112'h0000182442441804424112180000; 7'd20: rom = 112'h0000040C141424247e04040e0000; 7'd21: rom = 112'h00007c4040586442024112180000; 7'd22: rom = 112'h00001c1122586442424112180000; 7'd23: rom = 112'h00003e1122040408080808080000; 7'd24: rom = 112'h0000182441121824424112180000; 7'd25: rom = 112'h000018244242261a024424180000; 7'd26: rom = 112'h0000000018180000001818000000; 7'd27: rom = 112'h0000000018180000001818081000; 7'd28: rom = 112'h0000020408102040201008040200; 7'd29: rom = 112'h000000007e0000007E0000000000; 7'd30: rom = 112'h0000402010080402040810204000; 7'd31: rom = 112'h0000182442420408101000181800; 7'd32: rom = 112'h00001824112A5656564A20221C00; 7'd33: rom = 112'h00001010282828247c4444ee0000; 7'd34: rom = 112'h0000782424283c22222112780000; 7'd35: rom = 112'h00001a2611224040402226180000; 7'd36: rom = 112'h0000782424222222211224780000; 7'd37: rom = 112'h00007c2220243c242020227e0000; 7'd38: rom = 112'h00007c2220243c24202020780000; 7'd39: rom = 112'h00001a261122404e4222261a0000; 7'd40: rom = 112'h0000ee4444447c44444444ee0000; 7'd41: rom = 112'h00007c10101010101010107c0000; 7'd42: rom = 112'h00001e0404040404444448300000; 7'd43: rom = 112'h00006e2428283028242422760000; 7'd44: rom = 112'h00007020202020202020227c0000; 7'd45: rom = 112'h00004266666a5a52524242660000; 7'd46: rom = 112'h000046626252524A4a4646620000; 7'd47: rom = 112'h0000182442424242424112180000; 7'd48: rom = 112'h0000782422211238202020700000; 7'd49: rom = 112'h0000182442424242724e24180600; 7'd50: rom = 112'h0000782422211238282424720000; 7'd51: rom = 112'h00001a2642201804024264580000; 7'd52: rom = 112'h00007e5210101010101010380000; 7'd53: rom = 112'h0000762222222222222214080000; 7'd54: rom = 112'h0000664112242428181010100000; 7'd55: rom = 112'h0000929292525A6A6c2424240000; 7'd56: rom = 112'h00006244242810182824444e0000; 7'd57: rom = 112'h0000e64112281810101010380000; 7'd58: rom = 112'h00003e44040808102020427c0000; 7'd59: rom = 112'h003c20202020202020202020203C; 7'd60: rom = 112'h8080404020201010080804040202; 7'd61: rom = 112'h003c04040404040404040404043C; 7'd62: rom = 112'h0010284482000000000000000000; 7'd63: rom = 112'h00000000000000000000000000FE; 7'd64: rom = 112'h0018181008000000000000000000; 7'd65: rom = 112'h000000003844441c2444443a0000; 7'd66: rom = 112'h0000602028342222222112380000; 7'd67: rom = 112'h000000001a264240404226180000; 7'd68: rom = 112'h00000c04142c44444444241e0000; 7'd69: rom = 112'h000000001824427e4042221c0000; 7'd70: rom = 112'h00000c12127c1010101010380000; 7'd71: rom = 112'h000000001a24242418205c42423C; 7'd72: rom = 112'h0000c04050684444444444c60000; 7'd73: rom = 112'h00001818003808080808083c0000; 7'd74: rom = 112'h00000c0c001c0404040404444830; 7'd75: rom = 112'h0000c04046444858684444ce0000; 7'd76: rom = 112'h00003808080808080808083e0000; 7'd77: rom = 112'h00000000acd29292929292920000; 7'd78: rom = 112'h00000000d8644444444444c60000; 7'd79: rom = 112'h0000000018244242424112180000; 7'd80: rom = 112'h0000000058242222222112382070; 7'd81: rom = 112'h000000001a2444444444241c040E; 7'd82: rom = 112'h000000005c222220202020700000; 7'd83: rom = 112'h000000003c4440300c42625c0000; 7'd84: rom = 112'h00001010107c10101010120c0000; 7'd85: rom = 112'h00000000cc44444444444c320000; 7'd86: rom = 112'h0000000066424424281810100000; 7'd87: rom = 112'h00000000929292925A6c24240000; 7'd88: rom = 112'h0000000066242818181424660000; 7'd89: rom = 112'h0000000066222214140808485020; 7'd90: rom = 112'h000000003e4408081010227e0000; 7'd91: rom = 112'h0006081010101020101010100806; 7'd92: rom = 112'h0010101010101010101010101010; 7'd93: rom = 112'h0060100808080804080808081060; default: rom = 112'h0000000000000000000000000000; endcase end endfunction assign oDATA = rom(iADDR - 8'h20); endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_font.v

gci_std_display_font.v

v

[]

[]

[]

[(3, 113)]

1: b'%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_font.v:111: Operator FUNCREF \'rom\' expects 7 bits on the Function Argument, but Function Argument\'s SUB generates 8 bits.\n : ... In instance gci_std_display_font\n assign oDATA = rom(iADDR - 8\'h20); \n ^~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'

function

function [111:0] rom; input [6:0] funcADDR; begin case(funcADDR) 7'd0: rom = 112'h0000000000000000000000000000; 7'd1: rom = 112'h0000181818181010100000181800; 7'd2: rom = 112'h006c6c2448000000000000000000; 7'd3: rom = 112'h00002424247e2424487e48484800; 7'd4: rom = 112'h0000103c525250381452523c1000; 7'd5: rom = 112'h0000225254542818142a2a4A4400; 7'd6: rom = 112'h0000102828102652524c442a1000; 7'd7: rom = 112'h0030301020000000000000000000; 7'd8: rom = 112'h0004081010202020202010100804; 7'd9: rom = 112'h0020100808040404040408081020; 7'd10: rom = 112'h0000001010d6543854d610100000; 7'd11: rom = 112'h000000101010107e101010100000; 7'd12: rom = 112'h0000000000000000000030301020; 7'd13: rom = 112'h000000000000007e000000000000; 7'd14: rom = 112'h0000000000000000000000303000; 7'd15: rom = 112'h0202040408081010202040408080; 7'd16: rom = 112'h0000182424424242411224180000; 7'd17: rom = 112'h00001070101010101010107c0000; 7'd18: rom = 112'h00001824422204081020227e0000; 7'd19: rom = 112'h0000182442441804424112180000; 7'd20: rom = 112'h0000040C141424247e04040e0000; 7'd21: rom = 112'h00007c4040586442024112180000; 7'd22: rom = 112'h00001c1122586442424112180000; 7'd23: rom = 112'h00003e1122040408080808080000; 7'd24: rom = 112'h0000182441121824424112180000; 7'd25: rom = 112'h000018244242261a024424180000; 7'd26: rom = 112'h0000000018180000001818000000; 7'd27: rom = 112'h0000000018180000001818081000; 7'd28: rom = 112'h0000020408102040201008040200; 7'd29: rom = 112'h000000007e0000007E0000000000; 7'd30: rom = 112'h0000402010080402040810204000; 7'd31: rom = 112'h0000182442420408101000181800; 7'd32: rom = 112'h00001824112A5656564A20221C00; 7'd33: rom = 112'h00001010282828247c4444ee0000; 7'd34: rom = 112'h0000782424283c22222112780000; 7'd35: rom = 112'h00001a2611224040402226180000; 7'd36: rom = 112'h0000782424222222211224780000; 7'd37: rom = 112'h00007c2220243c242020227e0000; 7'd38: rom = 112'h00007c2220243c24202020780000; 7'd39: rom = 112'h00001a261122404e4222261a0000; 7'd40: rom = 112'h0000ee4444447c44444444ee0000; 7'd41: rom = 112'h00007c10101010101010107c0000; 7'd42: rom = 112'h00001e0404040404444448300000; 7'd43: rom = 112'h00006e2428283028242422760000; 7'd44: rom = 112'h00007020202020202020227c0000; 7'd45: rom = 112'h00004266666a5a52524242660000; 7'd46: rom = 112'h000046626252524A4a4646620000; 7'd47: rom = 112'h0000182442424242424112180000; 7'd48: rom = 112'h0000782422211238202020700000; 7'd49: rom = 112'h0000182442424242724e24180600; 7'd50: rom = 112'h0000782422211238282424720000; 7'd51: rom = 112'h00001a2642201804024264580000; 7'd52: rom = 112'h00007e5210101010101010380000; 7'd53: rom = 112'h0000762222222222222214080000; 7'd54: rom = 112'h0000664112242428181010100000; 7'd55: rom = 112'h0000929292525A6A6c2424240000; 7'd56: rom = 112'h00006244242810182824444e0000; 7'd57: rom = 112'h0000e64112281810101010380000; 7'd58: rom = 112'h00003e44040808102020427c0000; 7'd59: rom = 112'h003c20202020202020202020203C; 7'd60: rom = 112'h8080404020201010080804040202; 7'd61: rom = 112'h003c04040404040404040404043C; 7'd62: rom = 112'h0010284482000000000000000000; 7'd63: rom = 112'h00000000000000000000000000FE; 7'd64: rom = 112'h0018181008000000000000000000; 7'd65: rom = 112'h000000003844441c2444443a0000; 7'd66: rom = 112'h0000602028342222222112380000; 7'd67: rom = 112'h000000001a264240404226180000; 7'd68: rom = 112'h00000c04142c44444444241e0000; 7'd69: rom = 112'h000000001824427e4042221c0000; 7'd70: rom = 112'h00000c12127c1010101010380000; 7'd71: rom = 112'h000000001a24242418205c42423C; 7'd72: rom = 112'h0000c04050684444444444c60000; 7'd73: rom = 112'h00001818003808080808083c0000; 7'd74: rom = 112'h00000c0c001c0404040404444830; 7'd75: rom = 112'h0000c04046444858684444ce0000; 7'd76: rom = 112'h00003808080808080808083e0000; 7'd77: rom = 112'h00000000acd29292929292920000; 7'd78: rom = 112'h00000000d8644444444444c60000; 7'd79: rom = 112'h0000000018244242424112180000; 7'd80: rom = 112'h0000000058242222222112382070; 7'd81: rom = 112'h000000001a2444444444241c040E; 7'd82: rom = 112'h000000005c222220202020700000; 7'd83: rom = 112'h000000003c4440300c42625c0000; 7'd84: rom = 112'h00001010107c10101010120c0000; 7'd85: rom = 112'h00000000cc44444444444c320000; 7'd86: rom = 112'h0000000066424424281810100000; 7'd87: rom = 112'h00000000929292925A6c24240000; 7'd88: rom = 112'h0000000066242818181424660000; 7'd89: rom = 112'h0000000066222214140808485020; 7'd90: rom = 112'h000000003e4408081010227e0000; 7'd91: rom = 112'h0006081010101020101010100806; 7'd92: rom = 112'h0010101010101010101010101010; 7'd93: rom = 112'h0060100808080804080808081060; default: rom = 112'h0000000000000000000000000000; endcase end endfunction

function [111:0] rom;

input [6:0] funcADDR; begin case(funcADDR) 7'd0: rom = 112'h0000000000000000000000000000; 7'd1: rom = 112'h0000181818181010100000181800; 7'd2: rom = 112'h006c6c2448000000000000000000; 7'd3: rom = 112'h00002424247e2424487e48484800; 7'd4: rom = 112'h0000103c525250381452523c1000; 7'd5: rom = 112'h0000225254542818142a2a4A4400; 7'd6: rom = 112'h0000102828102652524c442a1000; 7'd7: rom = 112'h0030301020000000000000000000; 7'd8: rom = 112'h0004081010202020202010100804; 7'd9: rom = 112'h0020100808040404040408081020; 7'd10: rom = 112'h0000001010d6543854d610100000; 7'd11: rom = 112'h000000101010107e101010100000; 7'd12: rom = 112'h0000000000000000000030301020; 7'd13: rom = 112'h000000000000007e000000000000; 7'd14: rom = 112'h0000000000000000000000303000; 7'd15: rom = 112'h0202040408081010202040408080; 7'd16: rom = 112'h0000182424424242411224180000; 7'd17: rom = 112'h00001070101010101010107c0000; 7'd18: rom = 112'h00001824422204081020227e0000; 7'd19: rom = 112'h0000182442441804424112180000; 7'd20: rom = 112'h0000040C141424247e04040e0000; 7'd21: rom = 112'h00007c4040586442024112180000; 7'd22: rom = 112'h00001c1122586442424112180000; 7'd23: rom = 112'h00003e1122040408080808080000; 7'd24: rom = 112'h0000182441121824424112180000; 7'd25: rom = 112'h000018244242261a024424180000; 7'd26: rom = 112'h0000000018180000001818000000; 7'd27: rom = 112'h0000000018180000001818081000; 7'd28: rom = 112'h0000020408102040201008040200; 7'd29: rom = 112'h000000007e0000007E0000000000; 7'd30: rom = 112'h0000402010080402040810204000; 7'd31: rom = 112'h0000182442420408101000181800; 7'd32: rom = 112'h00001824112A5656564A20221C00; 7'd33: rom = 112'h00001010282828247c4444ee0000; 7'd34: rom = 112'h0000782424283c22222112780000; 7'd35: rom = 112'h00001a2611224040402226180000; 7'd36: rom = 112'h0000782424222222211224780000; 7'd37: rom = 112'h00007c2220243c242020227e0000; 7'd38: rom = 112'h00007c2220243c24202020780000; 7'd39: rom = 112'h00001a261122404e4222261a0000; 7'd40: rom = 112'h0000ee4444447c44444444ee0000; 7'd41: rom = 112'h00007c10101010101010107c0000; 7'd42: rom = 112'h00001e0404040404444448300000; 7'd43: rom = 112'h00006e2428283028242422760000; 7'd44: rom = 112'h00007020202020202020227c0000; 7'd45: rom = 112'h00004266666a5a52524242660000; 7'd46: rom = 112'h000046626252524A4a4646620000; 7'd47: rom = 112'h0000182442424242424112180000; 7'd48: rom = 112'h0000782422211238202020700000; 7'd49: rom = 112'h0000182442424242724e24180600; 7'd50: rom = 112'h0000782422211238282424720000; 7'd51: rom = 112'h00001a2642201804024264580000; 7'd52: rom = 112'h00007e5210101010101010380000; 7'd53: rom = 112'h0000762222222222222214080000; 7'd54: rom = 112'h0000664112242428181010100000; 7'd55: rom = 112'h0000929292525A6A6c2424240000; 7'd56: rom = 112'h00006244242810182824444e0000; 7'd57: rom = 112'h0000e64112281810101010380000; 7'd58: rom = 112'h00003e44040808102020427c0000; 7'd59: rom = 112'h003c20202020202020202020203C; 7'd60: rom = 112'h8080404020201010080804040202; 7'd61: rom = 112'h003c04040404040404040404043C; 7'd62: rom = 112'h0010284482000000000000000000; 7'd63: rom = 112'h00000000000000000000000000FE; 7'd64: rom = 112'h0018181008000000000000000000; 7'd65: rom = 112'h000000003844441c2444443a0000; 7'd66: rom = 112'h0000602028342222222112380000; 7'd67: rom = 112'h000000001a264240404226180000; 7'd68: rom = 112'h00000c04142c44444444241e0000; 7'd69: rom = 112'h000000001824427e4042221c0000; 7'd70: rom = 112'h00000c12127c1010101010380000; 7'd71: rom = 112'h000000001a24242418205c42423C; 7'd72: rom = 112'h0000c04050684444444444c60000; 7'd73: rom = 112'h00001818003808080808083c0000; 7'd74: rom = 112'h00000c0c001c0404040404444830; 7'd75: rom = 112'h0000c04046444858684444ce0000; 7'd76: rom = 112'h00003808080808080808083e0000; 7'd77: rom = 112'h00000000acd29292929292920000; 7'd78: rom = 112'h00000000d8644444444444c60000; 7'd79: rom = 112'h0000000018244242424112180000; 7'd80: rom = 112'h0000000058242222222112382070; 7'd81: rom = 112'h000000001a2444444444241c040E; 7'd82: rom = 112'h000000005c222220202020700000; 7'd83: rom = 112'h000000003c4440300c42625c0000; 7'd84: rom = 112'h00001010107c10101010120c0000; 7'd85: rom = 112'h00000000cc44444444444c320000; 7'd86: rom = 112'h0000000066424424281810100000; 7'd87: rom = 112'h00000000929292925A6c24240000; 7'd88: rom = 112'h0000000066242818181424660000; 7'd89: rom = 112'h0000000066222214140808485020; 7'd90: rom = 112'h000000003e4408081010227e0000; 7'd91: rom = 112'h0006081010101020101010100806; 7'd92: rom = 112'h0010101010101010101010101010; 7'd93: rom = 112'h0060100808080804080808081060; default: rom = 112'h0000000000000000000000000000; endcase end endfunction

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_hub_interface.v

gci_std_display_hub_interface.v

v

[]

[]

[]

line:44: before: "assign"

1: b"%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_hub_interface.v:44: syntax error, unexpected assign, expecting TYPE-IDENTIFIER\n assign oHUB_VALID = \n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_hub_interface.v:53: syntax error, unexpected assign, expecting TYPE-IDENTIFIER\n assign oCOMM_VALID = display_ctrl_condition || sequence_ctrl_condition;\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_hub_interface.v:63: syntax error, unexpected wire, expecting TYPE-IDENTIFIER\n wire register_busy_condition = \n ^~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_hub_interface.v:93: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n if(!iHUB_BUSY && ())begin\n ^\n%Error: Cannot continue\n"

module

module gci_std_display_hub_interface( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iHUB_REQ, output wire oHUB_BUSY, input wire iHUB_RW, input wire [31:0] iHUB_ADDR, input wire [31:0] iHUB_DATA, output wire oHUB_VALID, input wire iHUB_BUSY, output wire oHUB_DATA, output wire oREG_ENA, output wire oREG_RW, output wire [3:0] oREG_ADDR, output wire [31:0] oREG_DATA, input wire iREG_VALID, output wire oREG_BUSY, input wire [31:0] iREG_DATA, output wire oCOMM_VALID, output wire oCOMM_SEQ, input wire iCOMM_BUSY, output wire oCOMM_RW, output wire [31:0] oCOMM_ADDR, output wire [31:0] oCOMM_DATA, input wire iCOMM_VALID, output wire oCOMM_BUSY, input wire [31:0] iCOMM_ADDR, input wire [23:0] iCOMM_DATA ); assign oHUB_BUSY = assign oHUB_VALID = assign oHUB_DATA = assign oREG_ENA = register_ctrl_condition; assign oREG_RW = iHUB_RW; assign oREG_ADDR = iHUB_ADDR; assign oREG_DATA = iHUB_DATA; assign oREG_BUSY = assign oCOMM_VALID = display_ctrl_condition || sequence_ctrl_condition; assign oCOMM_SEQ = sequence_ctrl_condition; assign oCOMM_RW = iHUB_RW; assign oCOMM_ADDR = iHUB_ADDR; assign oCOMM_DATA = iHUB_DATA; assign oCOMM_BUSY = wire register_busy_condition = wire display_busy_condition = wire sequence_busy_condition = wire register_ctrl_condition = iHUB_ADDR <= 32'hF && (iHUB_ADDR == 32'h4)? !iHUB_RW : 1'b1; wire display_ctrl_condition = iHUB_ADDR > 32'hF; wire sequence_ctrl_condition = (iHUB_ADDR == 32'h4) && iHUB_RW; localparam P_L_MAIN_STT_WRITE = 1'b0; localparam P_L_MAIN_STT_READ_WAIT = 1'b1; reg b_main_state; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_main_state <= P_L_MAIN_STT_WRITE; end else if(iRESET_SYNC)begin b_main_state <= P_L_MAIN_STT_WRITE; end else begin case(b_main_state) P_L_MAIN_STT_WRITE: begin if(!iHUB_RW)begin b_main_state <= P_L_MAIN_STT_READ_WAIT; end end P_L_MAIN_STT_READ_WAIT: begin if(!iHUB_BUSY && ())begin b_main_state <= P_L_MAIN_STT_WRITE; end end endcase end end assign oIF_WR_BUSY = (iIF_WR_RW)? ??? : endmodule

module gci_std_display_hub_interface( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iHUB_REQ, output wire oHUB_BUSY, input wire iHUB_RW, input wire [31:0] iHUB_ADDR, input wire [31:0] iHUB_DATA, output wire oHUB_VALID, input wire iHUB_BUSY, output wire oHUB_DATA, output wire oREG_ENA, output wire oREG_RW, output wire [3:0] oREG_ADDR, output wire [31:0] oREG_DATA, input wire iREG_VALID, output wire oREG_BUSY, input wire [31:0] iREG_DATA, output wire oCOMM_VALID, output wire oCOMM_SEQ, input wire iCOMM_BUSY, output wire oCOMM_RW, output wire [31:0] oCOMM_ADDR, output wire [31:0] oCOMM_DATA, input wire iCOMM_VALID, output wire oCOMM_BUSY, input wire [31:0] iCOMM_ADDR, input wire [23:0] iCOMM_DATA );

assign oHUB_BUSY = assign oHUB_VALID = assign oHUB_DATA = assign oREG_ENA = register_ctrl_condition; assign oREG_RW = iHUB_RW; assign oREG_ADDR = iHUB_ADDR; assign oREG_DATA = iHUB_DATA; assign oREG_BUSY = assign oCOMM_VALID = display_ctrl_condition || sequence_ctrl_condition; assign oCOMM_SEQ = sequence_ctrl_condition; assign oCOMM_RW = iHUB_RW; assign oCOMM_ADDR = iHUB_ADDR; assign oCOMM_DATA = iHUB_DATA; assign oCOMM_BUSY = wire register_busy_condition = wire display_busy_condition = wire sequence_busy_condition = wire register_ctrl_condition = iHUB_ADDR <= 32'hF && (iHUB_ADDR == 32'h4)? !iHUB_RW : 1'b1; wire display_ctrl_condition = iHUB_ADDR > 32'hF; wire sequence_ctrl_condition = (iHUB_ADDR == 32'h4) && iHUB_RW; localparam P_L_MAIN_STT_WRITE = 1'b0; localparam P_L_MAIN_STT_READ_WAIT = 1'b1; reg b_main_state; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_main_state <= P_L_MAIN_STT_WRITE; end else if(iRESET_SYNC)begin b_main_state <= P_L_MAIN_STT_WRITE; end else begin case(b_main_state) P_L_MAIN_STT_WRITE: begin if(!iHUB_RW)begin b_main_state <= P_L_MAIN_STT_READ_WAIT; end end P_L_MAIN_STT_READ_WAIT: begin if(!iHUB_BUSY && ())begin b_main_state <= P_L_MAIN_STT_WRITE; end end endcase end end assign oIF_WR_BUSY = (iIF_WR_RW)? ??? : endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v

gci_std_display_register.v

v

[]

[]

[]

line:6: before: "("

1: b"%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:7: syntax error, unexpected '(', expecting ')' or ','\n input wire iCLOCK,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire inRESET,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire iRESET_SYNC,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire iWR_VALID,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [3:0] iWR_ADDR,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [31:0] iWR_DATA,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire iRD_VALID,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire oRD_BUSY,\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [3:0] iRD_ADDR,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire oRD_VALID,\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire iRD_BUSY,\n ^~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [31:0] oRD_DATA,\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output oINFO_CHARACTER,\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:38: syntax error, unexpected always\n always@(posedge iCLOCK or negedge inRESET)begin\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:62: syntax error, unexpected always\n always@(posedge iCLOCK or negedge inRESET)begin\n ^~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_register.v:88: syntax error, unexpected always\n always@(posedge iCLOCK or negedge inRESET)begin\n ^~~~~~\n%Error: Exiting due to 16 error(s)\n"

module

module gci_std_display_register #( parameter P_VRAM_SIZE = 307200 ( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iWR_VALID, input wire [3:0] iWR_ADDR, input wire [31:0] iWR_DATA, input wire iRD_VALID, output wire oRD_BUSY, input wire [3:0] iRD_ADDR, output wire oRD_VALID, input wire iRD_BUSY, output wire [31:0] oRD_DATA, output oINFO_CHARACTER, output [1:0] oINFO_COLOR ); localparam P_L_REG_ADDR_RESOLUT = 4'h0; localparam P_L_REG_ADDR_MODE = 4'h2; localparam P_L_REG_ADDR_SIZE = 4'h3; wire ds_resolut_write_condition = iWR_VALID && iWR_ADDR == P_L_REG_ADDR_RESOLUT; wire ds_mode_write_condition = iWR_VALID && iWR_ADDR == P_L_REG_ADDR_MODE; reg [11:0] b_ds_resolut_h; reg [11:0] b_ds_resolut_v; reg [6:0] b_ds_resolut_refresh; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_ds_resolut_h <= 12'h0; b_ds_resolut_v <= 12'h0; b_ds_resolut_refresh <= 7'h0; end else if(!iRESET_SYNC)begin b_ds_resolut_h <= 12'h0; b_ds_resolut_v <= 12'h0; b_ds_resolut_refresh <= 7'h0; end else begin if(ds_resolut_write_condition)begin b_ds_resolut_h <= iWR_DATA[11:1]; b_ds_resolut_v <= iWR_DATA[23:12]; b_ds_resolut_refresh <= iWR_DATA[30:24]; end end end wire [31:0] ds_resolut_data = {1'b0, b_ds_resolut_refresh, b_ds_resolut_v, b_ds_resolut_h}; reg [1:0] b_ds_mode_color; reg b_ds_mode_character; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_ds_mode_color <= 2'h0; b_ds_mode_character <= 1'b0; end else if(!iRESET_SYNC)begin b_ds_mode_color <= 2'h0; b_ds_mode_character <= 1'b0; end else begin if(ds_mode_write_condition)begin b_ds_mode_color <= iWR_DATA[2:1]; b_ds_mode_character <= iWR_DATA[0]; end end end wire [31:0] ds_mode_data = {29'h0, b_ds_mode_color, b_ds_mode_character}; wire [31:0] ds_size_data = P_VRAM_SIZE; reg b_read_valid; reg [31:0] b_read_buffer; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_read_valid <= 1'b0; b_read_buffer <= 32'h0; end else if(iRESET_SYNC)begin b_read_valid <= 1'b0; b_read_buffer <= 32'h0; end else begin if(!iRD_BUSY)begin b_read_valid <= iRD_VALID; case(iRD_ADDR) P_L_REG_ADDR_RESOLUT : b_read_buffer <= ds_resolut_data; P_L_REG_ADDR_MODE : b_read_buffer <= ds_mode_data; P_L_REG_ADDR_SIZE : b_read_buffer <= ds_size_data; default : b_read_buffer <= 32'h0; endcase end end end assign oRD_BUSY = iRD_BUSY; assign oRD_VALID = !iRD_BUSY && b_read_valid; assign oRD_DATA = b_read_buffer; assign oINFO_CHARACTER = b_ds_mode_character; assign oINFO_COLOR = b_ds_mode_color; endmodule

module gci_std_display_register #( parameter P_VRAM_SIZE = 307200 ( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iWR_VALID, input wire [3:0] iWR_ADDR, input wire [31:0] iWR_DATA, input wire iRD_VALID, output wire oRD_BUSY, input wire [3:0] iRD_ADDR, output wire oRD_VALID, input wire iRD_BUSY, output wire [31:0] oRD_DATA, output oINFO_CHARACTER, output [1:0] oINFO_COLOR );

localparam P_L_REG_ADDR_RESOLUT = 4'h0; localparam P_L_REG_ADDR_MODE = 4'h2; localparam P_L_REG_ADDR_SIZE = 4'h3; wire ds_resolut_write_condition = iWR_VALID && iWR_ADDR == P_L_REG_ADDR_RESOLUT; wire ds_mode_write_condition = iWR_VALID && iWR_ADDR == P_L_REG_ADDR_MODE; reg [11:0] b_ds_resolut_h; reg [11:0] b_ds_resolut_v; reg [6:0] b_ds_resolut_refresh; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_ds_resolut_h <= 12'h0; b_ds_resolut_v <= 12'h0; b_ds_resolut_refresh <= 7'h0; end else if(!iRESET_SYNC)begin b_ds_resolut_h <= 12'h0; b_ds_resolut_v <= 12'h0; b_ds_resolut_refresh <= 7'h0; end else begin if(ds_resolut_write_condition)begin b_ds_resolut_h <= iWR_DATA[11:1]; b_ds_resolut_v <= iWR_DATA[23:12]; b_ds_resolut_refresh <= iWR_DATA[30:24]; end end end wire [31:0] ds_resolut_data = {1'b0, b_ds_resolut_refresh, b_ds_resolut_v, b_ds_resolut_h}; reg [1:0] b_ds_mode_color; reg b_ds_mode_character; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_ds_mode_color <= 2'h0; b_ds_mode_character <= 1'b0; end else if(!iRESET_SYNC)begin b_ds_mode_color <= 2'h0; b_ds_mode_character <= 1'b0; end else begin if(ds_mode_write_condition)begin b_ds_mode_color <= iWR_DATA[2:1]; b_ds_mode_character <= iWR_DATA[0]; end end end wire [31:0] ds_mode_data = {29'h0, b_ds_mode_color, b_ds_mode_character}; wire [31:0] ds_size_data = P_VRAM_SIZE; reg b_read_valid; reg [31:0] b_read_buffer; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_read_valid <= 1'b0; b_read_buffer <= 32'h0; end else if(iRESET_SYNC)begin b_read_valid <= 1'b0; b_read_buffer <= 32'h0; end else begin if(!iRD_BUSY)begin b_read_valid <= iRD_VALID; case(iRD_ADDR) P_L_REG_ADDR_RESOLUT : b_read_buffer <= ds_resolut_data; P_L_REG_ADDR_MODE : b_read_buffer <= ds_mode_data; P_L_REG_ADDR_SIZE : b_read_buffer <= ds_size_data; default : b_read_buffer <= 32'h0; endcase end end end assign oRD_BUSY = iRD_BUSY; assign oRD_VALID = !iRD_BUSY && b_read_valid; assign oRD_DATA = b_read_buffer; assign oINFO_CHARACTER = b_ds_mode_character; assign oINFO_COLOR = b_ds_mode_color; endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_sequencer.v

gci_std_display_sequencer.v

v

[]

[]

[]

[(4, 107)]

1: b'%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_sequencer.v:104: Operator ASSIGNW expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_clear_counter\' generates 19 bits.\n : ... In instance gci_std_display_sequencer\n assign oIF_ADDR = b_clear_counter;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'

module

module gci_std_display_sequencer #( parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_AREAA_HV_N = 19, parameter P_MEM_ADDR_N = 23 )( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF_VALID, output wire oIF_BUSY, input wire [31:0] iIF_DATA, output wire oIF_FINISH, output wire oIF_VALID, input wire iIF_BUSY, output wire [P_MEM_ADDR_N-1:0] oIF_ADDR, output wire [23:0] oIF_DATA ); localparam P_L_CLEAR_STT_IDLE = 2'h0; localparam P_L_CLEAR_STT_CLEAR = 2'h1; localparam P_L_CLEAR_STT_END = 2'h2; reg [1:0] b_clear_state; reg [7:0] b_clear_color_r; reg [7:0] b_clear_color_g; reg [7:0] b_clear_color_b; reg [P_AREAA_HV_N-1:0] b_clear_counter; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_clear_state <= P_L_CLEAR_STT_IDLE; b_clear_color_r <= 8'h0; b_clear_color_g <= 8'h0; b_clear_color_b <= 8'h0; end else if(iRESET_SYNC)begin b_clear_state <= P_L_CLEAR_STT_IDLE; b_clear_color_r <= 8'h0; b_clear_color_g <= 8'h0; b_clear_color_b <= 8'h0; end else begin case(b_clear_state) P_L_CLEAR_STT_IDLE: begin if(iIF_VALID)begin b_clear_state <= P_L_CLEAR_STT_CLEAR; {b_clear_color_r, b_clear_color_g, b_clear_color_b} <= iIF_DATA[23:0]; end end P_L_CLEAR_STT_CLEAR: begin if(b_clear_counter == (P_AREA_H*P_AREA_V))begin b_clear_state <= P_L_CLEAR_STT_END; end end P_L_CLEAR_STT_END: begin b_clear_state <= P_L_CLEAR_STT_IDLE; end default: begin b_clear_state <= P_L_CLEAR_STT_IDLE; end endcase end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_clear_counter <= {P_AREAA_HV_N{1'b0}}; end else if(iRESET_SYNC)begin b_clear_counter <= {P_AREAA_HV_N{1'b0}}; end else begin if(b_clear_state == P_L_CLEAR_STT_CLEAR)begin if(!iIF_BUSY)begin b_clear_counter <= b_clear_counter + {{P_AREAA_HV_N-1{1'b0}}, 1'b1}; end end else begin b_clear_counter <= {P_AREAA_HV_N{1'b0}}; end end end assign oIF_BUSY = b_clear_state != P_L_CLEAR_STT_IDLE; assign oIF_FINISH = b_clear_state == P_L_CLEAR_STT_END; assign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR); assign oIF_ADDR = b_clear_counter; assign oIF_DATA = {b_clear_color_r, b_clear_color_g, b_clear_color_b}; endmodule

module gci_std_display_sequencer #( parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_AREAA_HV_N = 19, parameter P_MEM_ADDR_N = 23 )( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF_VALID, output wire oIF_BUSY, input wire [31:0] iIF_DATA, output wire oIF_FINISH, output wire oIF_VALID, input wire iIF_BUSY, output wire [P_MEM_ADDR_N-1:0] oIF_ADDR, output wire [23:0] oIF_DATA );

localparam P_L_CLEAR_STT_IDLE = 2'h0; localparam P_L_CLEAR_STT_CLEAR = 2'h1; localparam P_L_CLEAR_STT_END = 2'h2; reg [1:0] b_clear_state; reg [7:0] b_clear_color_r; reg [7:0] b_clear_color_g; reg [7:0] b_clear_color_b; reg [P_AREAA_HV_N-1:0] b_clear_counter; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_clear_state <= P_L_CLEAR_STT_IDLE; b_clear_color_r <= 8'h0; b_clear_color_g <= 8'h0; b_clear_color_b <= 8'h0; end else if(iRESET_SYNC)begin b_clear_state <= P_L_CLEAR_STT_IDLE; b_clear_color_r <= 8'h0; b_clear_color_g <= 8'h0; b_clear_color_b <= 8'h0; end else begin case(b_clear_state) P_L_CLEAR_STT_IDLE: begin if(iIF_VALID)begin b_clear_state <= P_L_CLEAR_STT_CLEAR; {b_clear_color_r, b_clear_color_g, b_clear_color_b} <= iIF_DATA[23:0]; end end P_L_CLEAR_STT_CLEAR: begin if(b_clear_counter == (P_AREA_H*P_AREA_V))begin b_clear_state <= P_L_CLEAR_STT_END; end end P_L_CLEAR_STT_END: begin b_clear_state <= P_L_CLEAR_STT_IDLE; end default: begin b_clear_state <= P_L_CLEAR_STT_IDLE; end endcase end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_clear_counter <= {P_AREAA_HV_N{1'b0}}; end else if(iRESET_SYNC)begin b_clear_counter <= {P_AREAA_HV_N{1'b0}}; end else begin if(b_clear_state == P_L_CLEAR_STT_CLEAR)begin if(!iIF_BUSY)begin b_clear_counter <= b_clear_counter + {{P_AREAA_HV_N-1{1'b0}}, 1'b1}; end end else begin b_clear_counter <= {P_AREAA_HV_N{1'b0}}; end end end assign oIF_BUSY = b_clear_state != P_L_CLEAR_STT_IDLE; assign oIF_FINISH = b_clear_state == P_L_CLEAR_STT_END; assign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR); assign oIF_ADDR = b_clear_counter; assign oIF_DATA = {b_clear_color_r, b_clear_color_g, b_clear_color_b}; endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_timing_generator.v

gci_std_display_timing_generator.v

v

[]

[]

[]

[(6, 245)]

data/verilator_xmls/efad2a39-16f9-4d16-8cd3-b28b61cd5733.xml

module

module gci_std_display_timing_generator #( parameter P_H_WIDTH = 10, parameter P_V_WIDTH = 10, parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_THP = 95, parameter P_THB = 48, parameter P_THF = 15, parameter P_TVP = 2, parameter P_TVB = 33, parameter P_TVF = 10 )( input wire iDISP_CLOCK, input wire inRESET, input wire iRESET_SYNC, output wire oDATA_REQ, output wire oDATA_SYNC, output wire onDISP_RESET, output wire oDISP_ENA, output wire oDISP_BLANK, output wire onDISP_VSYNC, output wire onDISP_HSYNC ); reg [P_H_WIDTH-1:0] b_hsync_counter; reg [P_V_WIDTH-1:0] b_vsync_counter; reg bn_disp_reset; reg b_buff_sync; reg b_buff_ena; reg bn_buff_blank; reg bn_buff_hsync; reg bn_buff_vsync; wire hsync_restart_condition = !(b_hsync_counter < (P_THP + P_THB + P_AREA_H + P_THF-1)); wire vsync_restart_condition = !(b_vsync_counter < (P_TVP + P_TVB + P_AREA_V + P_TVF-1)); wire data_active_condition = func_data_enable_area(b_hsync_counter, b_vsync_counter); wire hsync_active_condition = func_hsync_enable_area(b_hsync_counter); wire vsync_active_condition = func_vsync_enable_area(b_vsync_counter); function func_data_enable_area; input [P_H_WIDTH-1:0] func_hsync; input [P_V_WIDTH-1:0] func_vsync; begin if(func_hsync >= (P_THP + P_THB) && func_hsync < (P_THP + P_THB + P_AREA_H))begin if(func_vsync >= (P_TVP + P_TVB) && func_vsync < (P_TVP + P_TVB + P_AREA_V))begin func_data_enable_area = 1'b1; end else begin func_data_enable_area = 1'b0; end end else begin func_data_enable_area = 1'b0; end end endfunction function func_hsync_enable_area; input [P_H_WIDTH-1:0] func_hsync; begin if(func_hsync < P_THP)begin func_hsync_enable_area = 1'b1; end else begin func_hsync_enable_area = 1'b0; end end endfunction function func_vsync_enable_area; input [P_H_WIDTH-1:0] func_vsync; begin if(func_vsync < P_TVP)begin func_vsync_enable_area = 1'b1; end else begin func_vsync_enable_area = 1'b0; end end endfunction always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_hsync_counter <= {P_H_WIDTH{1'b0}}; end else if(iRESET_SYNC)begin b_hsync_counter <= {P_H_WIDTH{1'b0}}; end else begin if(hsync_restart_condition)begin b_hsync_counter <= {P_H_WIDTH{1'b0}}; end else begin b_hsync_counter <= b_hsync_counter + {{P_H_WIDTH-1{1'b0}}, 1'b1}; end end end always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_vsync_counter <= {P_V_WIDTH{1'b0}}; end else if(iRESET_SYNC)begin b_vsync_counter <= {P_V_WIDTH{1'b0}}; end else begin if(hsync_restart_condition)begin if(vsync_restart_condition)begin b_vsync_counter <= {P_V_WIDTH{1'b0}}; end else begin b_vsync_counter <= b_vsync_counter + {{P_V_WIDTH-1{1'b0}}, 1'b1}; end end end end always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin bn_disp_reset <= 1'b0; end else if(iRESET_SYNC)begin bn_disp_reset <= 1'b0; end else begin bn_disp_reset <= 1'b1; end end always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_buff_sync <= 1'b0; b_buff_ena <= 1'b0; bn_buff_blank <= 1'b0; bn_buff_hsync <= 1'b0; bn_buff_vsync <= 1'b0; end else if(iRESET_SYNC)begin b_buff_sync <= 1'b0; b_buff_ena <= 1'b0; bn_buff_blank <= 1'b0; bn_buff_hsync <= 1'b0; bn_buff_vsync <= 1'b0; end else begin b_buff_sync <= vsync_restart_condition; b_buff_ena <= data_active_condition; bn_buff_blank <= data_active_condition; bn_buff_hsync <= hsync_active_condition; bn_buff_vsync <= vsync_active_condition; end end assign oDATA_REQ = data_active_condition; assign oDATA_SYNC = b_buff_sync; assign onDISP_RESET = bn_disp_reset; assign oDISP_ENA = b_buff_ena; assign oDISP_BLANK = !bn_buff_blank; assign onDISP_HSYNC = !bn_buff_hsync; assign onDISP_VSYNC = !bn_buff_vsync; `ifdef GCI_STD_DISPLAY_SVA_ASSERTION property THP_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) ($past(onDISP_HSYNC, 1) and !onDISP_HSYNC) |-> (!onDISP_HSYNC[*P_THP] and ##(P_THP)onDISP_HSYNC); endproperty assert property(THP_CHECK)else begin $display("[Error][Assertion] : THP - Start%d, End%d", $past(onDISP_HSYNC, P_THP), onDISP_HSYNC); $stop; end property THB_HAREA_THF_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) (!$past(oDISP_ENA, 1) and oDISP_ENA) |-> (onDISP_HSYNC[*(P_THB+P_AREA_H+P_THF)]); endproperty assert property(THB_HAREA_THF_CHECK)else begin $display("[Error][Assertion] : Display Area-H - Start%d, End%d", $past(onDISP_HSYNC, (P_THB+P_AREA_H+P_THF)), onDISP_HSYNC); $stop; end property HAREA_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) (!$past(oDISP_ENA, 1) and oDISP_ENA) |-> (oDISP_ENA[*P_AREA_H] and ##(P_AREA_H)!oDISP_ENA); endproperty assert property(HAREA_CHECK)else begin $display("[Error][Assertion] : Display Area-H - Start%d, End%d", $past(oDISP_ENA, P_THP), oDISP_ENA); $stop; end property TVP_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) ($past(onDISP_VSYNC, 1) and !onDISP_VSYNC) |-> (!onDISP_VSYNC[*(P_TVP*(P_THP+P_THB+P_AREA_H+P_THF))] and ##((P_TVP*(P_THP+P_THB+P_AREA_H+P_THF)))onDISP_VSYNC); endproperty assert property(TVP_CHECK)else begin $display("[Error][Assertion] : TVP - Start%d, End%d", $past(onDISP_VSYNC, (P_TVP*(P_THP+P_THB+P_AREA_H+P_THF))), onDISP_VSYNC); $stop; end `endif endmodule

module gci_std_display_timing_generator #( parameter P_H_WIDTH = 10, parameter P_V_WIDTH = 10, parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_THP = 95, parameter P_THB = 48, parameter P_THF = 15, parameter P_TVP = 2, parameter P_TVB = 33, parameter P_TVF = 10 )( input wire iDISP_CLOCK, input wire inRESET, input wire iRESET_SYNC, output wire oDATA_REQ, output wire oDATA_SYNC, output wire onDISP_RESET, output wire oDISP_ENA, output wire oDISP_BLANK, output wire onDISP_VSYNC, output wire onDISP_HSYNC );

reg [P_H_WIDTH-1:0] b_hsync_counter; reg [P_V_WIDTH-1:0] b_vsync_counter; reg bn_disp_reset; reg b_buff_sync; reg b_buff_ena; reg bn_buff_blank; reg bn_buff_hsync; reg bn_buff_vsync; wire hsync_restart_condition = !(b_hsync_counter < (P_THP + P_THB + P_AREA_H + P_THF-1)); wire vsync_restart_condition = !(b_vsync_counter < (P_TVP + P_TVB + P_AREA_V + P_TVF-1)); wire data_active_condition = func_data_enable_area(b_hsync_counter, b_vsync_counter); wire hsync_active_condition = func_hsync_enable_area(b_hsync_counter); wire vsync_active_condition = func_vsync_enable_area(b_vsync_counter); function func_data_enable_area; input [P_H_WIDTH-1:0] func_hsync; input [P_V_WIDTH-1:0] func_vsync; begin if(func_hsync >= (P_THP + P_THB) && func_hsync < (P_THP + P_THB + P_AREA_H))begin if(func_vsync >= (P_TVP + P_TVB) && func_vsync < (P_TVP + P_TVB + P_AREA_V))begin func_data_enable_area = 1'b1; end else begin func_data_enable_area = 1'b0; end end else begin func_data_enable_area = 1'b0; end end endfunction function func_hsync_enable_area; input [P_H_WIDTH-1:0] func_hsync; begin if(func_hsync < P_THP)begin func_hsync_enable_area = 1'b1; end else begin func_hsync_enable_area = 1'b0; end end endfunction function func_vsync_enable_area; input [P_H_WIDTH-1:0] func_vsync; begin if(func_vsync < P_TVP)begin func_vsync_enable_area = 1'b1; end else begin func_vsync_enable_area = 1'b0; end end endfunction always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_hsync_counter <= {P_H_WIDTH{1'b0}}; end else if(iRESET_SYNC)begin b_hsync_counter <= {P_H_WIDTH{1'b0}}; end else begin if(hsync_restart_condition)begin b_hsync_counter <= {P_H_WIDTH{1'b0}}; end else begin b_hsync_counter <= b_hsync_counter + {{P_H_WIDTH-1{1'b0}}, 1'b1}; end end end always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_vsync_counter <= {P_V_WIDTH{1'b0}}; end else if(iRESET_SYNC)begin b_vsync_counter <= {P_V_WIDTH{1'b0}}; end else begin if(hsync_restart_condition)begin if(vsync_restart_condition)begin b_vsync_counter <= {P_V_WIDTH{1'b0}}; end else begin b_vsync_counter <= b_vsync_counter + {{P_V_WIDTH-1{1'b0}}, 1'b1}; end end end end always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin bn_disp_reset <= 1'b0; end else if(iRESET_SYNC)begin bn_disp_reset <= 1'b0; end else begin bn_disp_reset <= 1'b1; end end always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_buff_sync <= 1'b0; b_buff_ena <= 1'b0; bn_buff_blank <= 1'b0; bn_buff_hsync <= 1'b0; bn_buff_vsync <= 1'b0; end else if(iRESET_SYNC)begin b_buff_sync <= 1'b0; b_buff_ena <= 1'b0; bn_buff_blank <= 1'b0; bn_buff_hsync <= 1'b0; bn_buff_vsync <= 1'b0; end else begin b_buff_sync <= vsync_restart_condition; b_buff_ena <= data_active_condition; bn_buff_blank <= data_active_condition; bn_buff_hsync <= hsync_active_condition; bn_buff_vsync <= vsync_active_condition; end end assign oDATA_REQ = data_active_condition; assign oDATA_SYNC = b_buff_sync; assign onDISP_RESET = bn_disp_reset; assign oDISP_ENA = b_buff_ena; assign oDISP_BLANK = !bn_buff_blank; assign onDISP_HSYNC = !bn_buff_hsync; assign onDISP_VSYNC = !bn_buff_vsync; `ifdef GCI_STD_DISPLAY_SVA_ASSERTION property THP_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) ($past(onDISP_HSYNC, 1) and !onDISP_HSYNC) |-> (!onDISP_HSYNC[*P_THP] and ##(P_THP)onDISP_HSYNC); endproperty assert property(THP_CHECK)else begin $display("[Error][Assertion] : THP - Start%d, End%d", $past(onDISP_HSYNC, P_THP), onDISP_HSYNC); $stop; end property THB_HAREA_THF_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) (!$past(oDISP_ENA, 1) and oDISP_ENA) |-> (onDISP_HSYNC[*(P_THB+P_AREA_H+P_THF)]); endproperty assert property(THB_HAREA_THF_CHECK)else begin $display("[Error][Assertion] : Display Area-H - Start%d, End%d", $past(onDISP_HSYNC, (P_THB+P_AREA_H+P_THF)), onDISP_HSYNC); $stop; end property HAREA_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) (!$past(oDISP_ENA, 1) and oDISP_ENA) |-> (oDISP_ENA[*P_AREA_H] and ##(P_AREA_H)!oDISP_ENA); endproperty assert property(HAREA_CHECK)else begin $display("[Error][Assertion] : Display Area-H - Start%d, End%d", $past(oDISP_ENA, P_THP), oDISP_ENA); $stop; end property TVP_CHECK; @(posedge iDISP_CLOCK) disable iff (!inRESET) ($past(onDISP_VSYNC, 1) and !onDISP_VSYNC) |-> (!onDISP_VSYNC[*(P_TVP*(P_THP+P_THB+P_AREA_H+P_THF))] and ##((P_TVP*(P_THP+P_THB+P_AREA_H+P_THF)))onDISP_VSYNC); endproperty assert property(TVP_CHECK)else begin $display("[Error][Assertion] : TVP - Start%d, End%d", $past(onDISP_VSYNC, (P_TVP*(P_THP+P_THB+P_AREA_H+P_THF))), onDISP_VSYNC); $stop; end `endif endmodule

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_timing_generator.v

gci_std_display_timing_generator.v

v

[]

[]

[]

[(6, 245)]

data/verilator_xmls/efad2a39-16f9-4d16-8cd3-b28b61cd5733.xml

function

function func_data_enable_area; input [P_H_WIDTH-1:0] func_hsync; input [P_V_WIDTH-1:0] func_vsync; begin if(func_hsync >= (P_THP + P_THB) && func_hsync < (P_THP + P_THB + P_AREA_H))begin if(func_vsync >= (P_TVP + P_TVB) && func_vsync < (P_TVP + P_TVB + P_AREA_V))begin func_data_enable_area = 1'b1; end else begin func_data_enable_area = 1'b0; end end else begin func_data_enable_area = 1'b0; end end endfunction

function func_data_enable_area;

input [P_H_WIDTH-1:0] func_hsync; input [P_V_WIDTH-1:0] func_vsync; begin if(func_hsync >= (P_THP + P_THB) && func_hsync < (P_THP + P_THB + P_AREA_H))begin if(func_vsync >= (P_TVP + P_TVB) && func_vsync < (P_TVP + P_TVB + P_AREA_V))begin func_data_enable_area = 1'b1; end else begin func_data_enable_area = 1'b0; end end else begin func_data_enable_area = 1'b0; end end endfunction

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_timing_generator.v

gci_std_display_timing_generator.v

v

[]

[]

[]

[(6, 245)]

data/verilator_xmls/efad2a39-16f9-4d16-8cd3-b28b61cd5733.xml

function

function func_hsync_enable_area; input [P_H_WIDTH-1:0] func_hsync; begin if(func_hsync < P_THP)begin func_hsync_enable_area = 1'b1; end else begin func_hsync_enable_area = 1'b0; end end endfunction

function func_hsync_enable_area;

input [P_H_WIDTH-1:0] func_hsync; begin if(func_hsync < P_THP)begin func_hsync_enable_area = 1'b1; end else begin func_hsync_enable_area = 1'b0; end end endfunction

data/full_repos/permissive/9877430/rtl/display_controller/gci_std_display_timing_generator.v

gci_std_display_timing_generator.v

v

[]

[]

[]

[(6, 245)]

data/verilator_xmls/efad2a39-16f9-4d16-8cd3-b28b61cd5733.xml

function

function func_vsync_enable_area; input [P_H_WIDTH-1:0] func_vsync; begin if(func_vsync < P_TVP)begin func_vsync_enable_area = 1'b1; end else begin func_vsync_enable_area = 1'b0; end end endfunction

function func_vsync_enable_area;

input [P_H_WIDTH-1:0] func_vsync; begin if(func_vsync < P_TVP)begin func_vsync_enable_area = 1'b1; end else begin func_vsync_enable_area = 1'b0; end end endfunction

data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v

gci_std_display_async_fifo.v

v

[]

[]

[]

line:136: before: "("

1: b'%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:76: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_wr_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:79: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_wr_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:92: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_rd_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:95: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_rd_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n%Error: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:108: Cannot find file containing module: \'gci_std_display_async_fifo_double_flipflop\'\n gci_std_display_async_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_READ(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/lib,data/full_repos/permissive/9877430/gci_std_display_async_fifo_double_flipflop\n data/full_repos/permissive/9877430/rtl/lib,data/full_repos/permissive/9877430/gci_std_display_async_fifo_double_flipflop.v\n data/full_repos/permissive/9877430/rtl/lib,data/full_repos/permissive/9877430/gci_std_display_async_fifo_double_flipflop.sv\n gci_std_display_async_fifo_double_flipflop\n gci_std_display_async_fifo_double_flipflop.v\n gci_std_display_async_fifo_double_flipflop.sv\n obj_dir/gci_std_display_async_fifo_double_flipflop\n obj_dir/gci_std_display_async_fifo_double_flipflop.v\n obj_dir/gci_std_display_async_fifo_double_flipflop.sv\n%Error: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:117: Cannot find file containing module: \'gci_std_async_display_fifo_double_flipflop\'\n gci_std_async_display_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_WRITE(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'

module

module gci_std_display_async_fifo #( parameter P_N = 16, parameter P_DEPTH = 4, parameter P_DEPTH_N = 2 )( input inRESET, input iREMOVE, input iWR_CLOCK, input iWR_EN, input [P_N-1:0] iWR_DATA, output oWR_FULL, input iRD_CLOCK, input iRD_EN, output [P_N-1:0] oRD_DATA, output oRD_EMPTY ); wire [P_DEPTH_N:0] full_count; wire full; wire [P_DEPTH_N:0] empty_count; wire empty; reg [P_N-1:0] b_memory[0:P_DEPTH-1]; reg [P_DEPTH_N:0] b_wr_counter; reg [P_DEPTH_N:0] b_rd_counter; wire [P_DEPTH_N:0] gray_d_fifo_rd_counter; wire [P_DEPTH_N:0] binary_d_fifo_rd_counter; wire [P_DEPTH_N:0] gray_d_fifo_wr_counter; wire [P_DEPTH_N:0] binary_d_fifo_wr_counter; assign full_count = b_wr_counter - binary_d_fifo_rd_counter; assign full = full_count[P_DEPTH_N] || (full_count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}})? 1'b1 : 1'b0; assign empty_count = binary_d_fifo_wr_counter - (b_rd_counter); assign empty = (empty_count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0; always@(posedge iWR_CLOCK or negedge inRESET)begin if(!inRESET)begin b_wr_counter <= {P_DEPTH_N{1'b0}}; end else if(iREMOVE)begin b_wr_counter <= {P_DEPTH_N{1'b0}}; end else begin if(iWR_EN && !full)begin b_memory[b_wr_counter[P_DEPTH_N-1:0]] <= iWR_DATA; b_wr_counter <= b_wr_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end always@(posedge iRD_CLOCK or negedge inRESET)begin if(!inRESET)begin b_rd_counter <= {P_DEPTH_N{1'b0}}; end else if(iREMOVE)begin b_rd_counter <= {P_DEPTH_N{1'b0}}; end else begin if(iRD_EN && !empty)begin b_rd_counter <= b_rd_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end gci_std_display_async_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_READ( .iCLOCK(iWR_CLOCK), .inRESET(inRESET), .iREQ_DATA(bin2gray(b_rd_counter)), .oOUT_DATA(gray_d_fifo_rd_counter) ); assign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter); gci_std_async_display_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_WRITE( .iCLOCK(iRD_CLOCK), .inRESET(inRESET), .iREQ_DATA(bin2gray(b_wr_counter)), .oOUT_DATA(gray_d_fifo_wr_counter) ); assign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter); function [P_DEPTH_N:0] bin2gray; input [P_DEPTH_N:0] binary; begin bin2gray = binary ^ (binary >> 1'b1); end endfunction function[P_DEPTH_N:0] gray2bin(input[P_DEPTH_N:0] gray); integer i; for(i=P_DEPTH_N; i>=0; i=i-1)begin if(i==P_DEPTH_N)begin gray2bin[i] = gray[i]; end else begin gray2bin[i] = gray[i] ^ gray2bin[i+1]; end end endfunction assign oWR_FULL = full; assign oRD_EMPTY = empty; assign oRD_DATA = b_memory[b_rd_counter[P_DEPTH_N-1:0]]; endmodule

module gci_std_display_async_fifo #( parameter P_N = 16, parameter P_DEPTH = 4, parameter P_DEPTH_N = 2 )( input inRESET, input iREMOVE, input iWR_CLOCK, input iWR_EN, input [P_N-1:0] iWR_DATA, output oWR_FULL, input iRD_CLOCK, input iRD_EN, output [P_N-1:0] oRD_DATA, output oRD_EMPTY );

wire [P_DEPTH_N:0] full_count; wire full; wire [P_DEPTH_N:0] empty_count; wire empty; reg [P_N-1:0] b_memory[0:P_DEPTH-1]; reg [P_DEPTH_N:0] b_wr_counter; reg [P_DEPTH_N:0] b_rd_counter; wire [P_DEPTH_N:0] gray_d_fifo_rd_counter; wire [P_DEPTH_N:0] binary_d_fifo_rd_counter; wire [P_DEPTH_N:0] gray_d_fifo_wr_counter; wire [P_DEPTH_N:0] binary_d_fifo_wr_counter; assign full_count = b_wr_counter - binary_d_fifo_rd_counter; assign full = full_count[P_DEPTH_N] || (full_count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}})? 1'b1 : 1'b0; assign empty_count = binary_d_fifo_wr_counter - (b_rd_counter); assign empty = (empty_count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0; always@(posedge iWR_CLOCK or negedge inRESET)begin if(!inRESET)begin b_wr_counter <= {P_DEPTH_N{1'b0}}; end else if(iREMOVE)begin b_wr_counter <= {P_DEPTH_N{1'b0}}; end else begin if(iWR_EN && !full)begin b_memory[b_wr_counter[P_DEPTH_N-1:0]] <= iWR_DATA; b_wr_counter <= b_wr_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end always@(posedge iRD_CLOCK or negedge inRESET)begin if(!inRESET)begin b_rd_counter <= {P_DEPTH_N{1'b0}}; end else if(iREMOVE)begin b_rd_counter <= {P_DEPTH_N{1'b0}}; end else begin if(iRD_EN && !empty)begin b_rd_counter <= b_rd_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end gci_std_display_async_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_READ( .iCLOCK(iWR_CLOCK), .inRESET(inRESET), .iREQ_DATA(bin2gray(b_rd_counter)), .oOUT_DATA(gray_d_fifo_rd_counter) ); assign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter); gci_std_async_display_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_WRITE( .iCLOCK(iRD_CLOCK), .inRESET(inRESET), .iREQ_DATA(bin2gray(b_wr_counter)), .oOUT_DATA(gray_d_fifo_wr_counter) ); assign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter); function [P_DEPTH_N:0] bin2gray; input [P_DEPTH_N:0] binary; begin bin2gray = binary ^ (binary >> 1'b1); end endfunction function[P_DEPTH_N:0] gray2bin(input[P_DEPTH_N:0] gray); integer i; for(i=P_DEPTH_N; i>=0; i=i-1)begin if(i==P_DEPTH_N)begin gray2bin[i] = gray[i]; end else begin gray2bin[i] = gray[i] ^ gray2bin[i+1]; end end endfunction assign oWR_FULL = full; assign oRD_EMPTY = empty; assign oRD_DATA = b_memory[b_rd_counter[P_DEPTH_N-1:0]]; endmodule

data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v

gci_std_display_async_fifo.v

v

[]

[]

[]

line:136: before: "("

1: b'%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:76: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_wr_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:79: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_wr_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:92: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_rd_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:95: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance gci_std_display_async_fifo\n b_rd_counter <= {P_DEPTH_N{1\'b0}};\n ^~\n%Error: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:108: Cannot find file containing module: \'gci_std_display_async_fifo_double_flipflop\'\n gci_std_display_async_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_READ(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/lib,data/full_repos/permissive/9877430/gci_std_display_async_fifo_double_flipflop\n data/full_repos/permissive/9877430/rtl/lib,data/full_repos/permissive/9877430/gci_std_display_async_fifo_double_flipflop.v\n data/full_repos/permissive/9877430/rtl/lib,data/full_repos/permissive/9877430/gci_std_display_async_fifo_double_flipflop.sv\n gci_std_display_async_fifo_double_flipflop\n gci_std_display_async_fifo_double_flipflop.v\n gci_std_display_async_fifo_double_flipflop.sv\n obj_dir/gci_std_display_async_fifo_double_flipflop\n obj_dir/gci_std_display_async_fifo_double_flipflop.v\n obj_dir/gci_std_display_async_fifo_double_flipflop.sv\n%Error: data/full_repos/permissive/9877430/rtl/lib/gci_std_display_async_fifo.v:117: Cannot find file containing module: \'gci_std_async_display_fifo_double_flipflop\'\n gci_std_async_display_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_WRITE(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'

function

function [P_DEPTH_N:0] bin2gray; input [P_DEPTH_N:0] binary; begin bin2gray = binary ^ (binary >> 1'b1); end endfunction

function [P_DEPTH_N:0] bin2gray;

input [P_DEPTH_N:0] binary; begin bin2gray = binary ^ (binary >> 1'b1); end endfunction

data/full_repos/permissive/9877430/rtl/lib/gci_std_display_sync_fifo.v

gci_std_display_sync_fifo.v

v

[]

[]

[]

[(26, 112)]

data/verilator_xmls/3a34c81d-2745-45e0-b848-defc2e1d9cfc.xml

module

module gci_std_display_sync_fifo #( parameter P_N = 16, parameter P_DEPTH = 4, parameter P_DEPTH_N = 2 )( input iCLOCK, input inRESET, input iREMOVE, output [P_DEPTH_N:0] oCOUNT, input iWR_EN, input [P_N-1:0] iWR_DATA, output oWR_FULL, output oWR_ALMOST_FULL, input iRD_EN, output [P_N-1:0] oRD_DATA, output oRD_EMPTY, output oRD_ALMOST_EMPTY ); reg [P_DEPTH_N:0] b_write_pointer; reg [P_DEPTH_N:0] b_read_pointer; reg [P_N-1:0] b_memory [0:P_DEPTH-1]; wire [P_DEPTH_N:0] count = b_write_pointer - b_read_pointer; wire full = count[P_DEPTH_N]; wire empty = (count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0; wire almost_full = full || (count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}}); wire almost_empty = empty || (count[P_DEPTH_N:0] == {{P_DEPTH_N{1'b0}}, 1'b1}); wire read_condition = iRD_EN && !empty; wire write_condition = iWR_EN && !full; always@(posedge iCLOCK)begin if(write_condition)begin b_memory [b_write_pointer[P_DEPTH_N-1:0]] <= iWR_DATA; end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_write_pointer <= {P_DEPTH_N+1{1'b0}}; end else if(iREMOVE)begin b_write_pointer <= {P_DEPTH_N+1{1'b0}}; end else begin if(write_condition)begin b_write_pointer <= b_write_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_read_pointer <= {P_DEPTH_N+1{1'b0}}; end else if(iREMOVE)begin b_read_pointer <= {P_DEPTH_N+1{1'b0}}; end else begin if(read_condition)begin b_read_pointer <= b_read_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end assign oRD_DATA = b_memory[b_read_pointer[P_DEPTH_N-1:0]]; assign oRD_EMPTY = empty; assign oRD_ALMOST_EMPTY = almost_empty; assign oWR_FULL = full; assign oWR_ALMOST_FULL = almost_full; assign oCOUNT = count[P_DEPTH_N:0]; endmodule

module gci_std_display_sync_fifo #( parameter P_N = 16, parameter P_DEPTH = 4, parameter P_DEPTH_N = 2 )( input iCLOCK, input inRESET, input iREMOVE, output [P_DEPTH_N:0] oCOUNT, input iWR_EN, input [P_N-1:0] iWR_DATA, output oWR_FULL, output oWR_ALMOST_FULL, input iRD_EN, output [P_N-1:0] oRD_DATA, output oRD_EMPTY, output oRD_ALMOST_EMPTY );

reg [P_DEPTH_N:0] b_write_pointer; reg [P_DEPTH_N:0] b_read_pointer; reg [P_N-1:0] b_memory [0:P_DEPTH-1]; wire [P_DEPTH_N:0] count = b_write_pointer - b_read_pointer; wire full = count[P_DEPTH_N]; wire empty = (count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0; wire almost_full = full || (count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}}); wire almost_empty = empty || (count[P_DEPTH_N:0] == {{P_DEPTH_N{1'b0}}, 1'b1}); wire read_condition = iRD_EN && !empty; wire write_condition = iWR_EN && !full; always@(posedge iCLOCK)begin if(write_condition)begin b_memory [b_write_pointer[P_DEPTH_N-1:0]] <= iWR_DATA; end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_write_pointer <= {P_DEPTH_N+1{1'b0}}; end else if(iREMOVE)begin b_write_pointer <= {P_DEPTH_N+1{1'b0}}; end else begin if(write_condition)begin b_write_pointer <= b_write_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_read_pointer <= {P_DEPTH_N+1{1'b0}}; end else if(iREMOVE)begin b_read_pointer <= {P_DEPTH_N+1{1'b0}}; end else begin if(read_condition)begin b_read_pointer <= b_read_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1}; end end end assign oRD_DATA = b_memory[b_read_pointer[P_DEPTH_N-1:0]]; assign oRD_EMPTY = empty; assign oRD_ALMOST_EMPTY = almost_empty; assign oWR_FULL = full; assign oWR_ALMOST_FULL = almost_full; assign oCOUNT = count[P_DEPTH_N:0]; endmodule

data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v

memory_resource_controller.v

v

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[]

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line:2: before: "none"

1: b"%Error: data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v:2: Define or directive not defined: '`default_netype'\n : ... Suggested alternative: '`default_nettype'\n`default_netype none\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v:2: syntax error, unexpected IDENTIFIER\n`default_netype none\n ^~~~\n%Error: Exiting due to 2 error(s)\n"

module

module memory_resource_controller #( parameter P_MEM_ADDR_N = 22 )( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF0_ARBIT_REQ, output wire oIF0_ARBIT_ACK, input wire iIF0_ARBIT_FINISH, input wire iIF0_ENA, output wire oIF0_BUSY, input wire iIF0_RW, input wire [P_MEM_ADDR_N-1:0] iIF0_ADDR, input wire [31:0] iIF0_DATA, output wire oIF0_VALID, input wire iIF0_BUSY, output wire [31:0] oIF0_DATA, input wire iIF1_ARBIT_REQ, output wire oIF1_ARBIT_ACK, input wire iIF1_ARBIT_FINISH, input wire iIF1_ENA, output wire oIF1_BUSY, input wire iIF1_RW, input wire [P_MEM_ADDR_N-1:0] iIF1_ADDR, input wire [31:0] iIF1_DATA, output wire oIF1_VALID, input wire iIF1_BUSY, output wire [31:0] oIF1_DATA, output wire oMEM_ENA, input wire iMEM_BUSY, output wire oMEM_RW, output wire [P_MEM_ADDR_N-1:0] oMEM_ADDR, output wire [31:0] oMEM_DATA, input wire iMEM_VALID, output wire oMEM_BUSY, input wire [31:0] iMEM_DATA ); localparam L_PARAM_STT_IDLE = 2'h0; localparam L_PARAM_STT_ACK = 2'h1; localparam L_PARAM_STT_WORK = 2'h2; reg [1:0] b_state; reg b_authority; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_state <= L_PARAM_STT_IDLE; end else if(iRESET_SYNC)begin b_state <= L_PARAM_STT_IDLE; end else begin case(b_state) L_PARAM_STT_IDLE: begin if(iIF0_ARBIT_REQ || iIF1_ARBIT_REQ)begin b_state <= L_PARAM_STT_ACK; end end L_PARAM_STT_ACK: begin b_state <= L_PARAM_STT_WORK; end L_PARAM_STT_WORK: begin if(func_if_finish_check(b_authority, iIF0_ARBIT_FINISH, iIF1_ARBIT_FINISH))begin b_state <= L_PARAM_STT_IDLE; end end default: begin b_state <= L_PARAM_STT_IDLE; end endcase end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_authority <= 1'b0; end else if(iRESET_SYNC)begin b_authority <= 1'b0; end else begin if(b_state == L_PARAM_STT_IDLE)begin b_authority <= func_priority_encoder(b_authority, iIF0_ARBIT_REQ, iIF1_ARBIT_REQ); end end end function func_if_finish_check; input func_now; input func_if0_finish; input func_if1_finish; begin if(!func_now && func_if0_finish)begin func_if_finish_check = 1'b1; end else if(func_now && func_if1_finish)begin func_if_finish_check = 1'b1; end else begin func_if_finish_check = 1'b0; end end endfunction function func_priority_encoder; input func_now; input func_if0_req; input func_if1_req; begin case(func_now) 1'b0: begin if(func_if1_req)begin func_priority_encoder = 1'b1; end else if(func_if0_req)begin func_priority_encoder = 1'b0; end else begin func_priority_encoder = 1'b0; end end 1'b1: begin if(func_if0_req)begin func_priority_encoder = 1'b0; end else if(func_if1_req)begin func_priority_encoder = 1'b1; end else begin func_priority_encoder = 1'b0; end end endcase end endfunction reg b_if2mem_ena; reg b_if2mem_rw; reg [P_MEM_ADDR_N-1:0] b_if2mem_addr; reg [31:0] b_if2mem_data; reg b_mem2if0_valid; reg [31:0] b_mem2if0_data; reg b_mem2if1_valid; reg [31:0] b_mem2if1_data; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_if2mem_ena <= 1'b0; b_if2mem_rw <= 1'b0; b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}}; b_if2mem_data <= 32'h0; b_mem2if0_valid <= 1'b0; b_mem2if0_data <= 32'h0; b_mem2if1_valid <= 1'b0; b_mem2if1_data <= 32'h0; end else if(b_state != L_PARAM_STT_WORK || iRESET_SYNC)begin b_if2mem_ena <= 1'b0; b_if2mem_rw <= 1'b0; b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}}; b_if2mem_data <= 32'h0; b_mem2if0_valid <= 1'b0; b_mem2if0_data <= 32'h0; b_mem2if1_valid <= 1'b0; b_mem2if1_data <= 32'h0; end else begin case(b_authority) 1'b0: begin b_if2mem_ena <= iIF0_ENA; b_if2mem_rw <= iIF0_RW; b_if2mem_addr <= iIF0_ADDR; b_if2mem_data <= iIF0_DATA; b_mem2if0_valid <= iMEM_VALID; b_mem2if0_data <= iMEM_DATA; b_mem2if1_valid <= 1'b0; b_mem2if1_data <= 32'h0; end 1'b1: begin b_if2mem_ena <= iIF1_ENA; b_if2mem_rw <= iIF1_RW; b_if2mem_addr <= iIF1_ADDR; b_if2mem_data <= iIF1_DATA; b_mem2if0_valid <= 1'b0; b_mem2if0_data <= 32'h0; b_mem2if1_valid <= iMEM_VALID; b_mem2if1_data <= iMEM_DATA; end endcase end end assign oIF0_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && !b_authority; assign oIF1_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && b_authority; assign oIF0_VALID = b_mem2if0_valid; assign oIF0_DATA = b_mem2if0_data; assign oIF1_VALID = b_mem2if1_valid; assign oIF1_DATA = b_mem2if1_data; assign oMEM_ENA = b_if2mem_ena; assign oMEM_RW = b_if2mem_rw; assign oMEM_ADDR = b_if2mem_addr; assign oMEM_DATA = b_if2mem_data; endmodule

module memory_resource_controller #( parameter P_MEM_ADDR_N = 22 )( input wire iCLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF0_ARBIT_REQ, output wire oIF0_ARBIT_ACK, input wire iIF0_ARBIT_FINISH, input wire iIF0_ENA, output wire oIF0_BUSY, input wire iIF0_RW, input wire [P_MEM_ADDR_N-1:0] iIF0_ADDR, input wire [31:0] iIF0_DATA, output wire oIF0_VALID, input wire iIF0_BUSY, output wire [31:0] oIF0_DATA, input wire iIF1_ARBIT_REQ, output wire oIF1_ARBIT_ACK, input wire iIF1_ARBIT_FINISH, input wire iIF1_ENA, output wire oIF1_BUSY, input wire iIF1_RW, input wire [P_MEM_ADDR_N-1:0] iIF1_ADDR, input wire [31:0] iIF1_DATA, output wire oIF1_VALID, input wire iIF1_BUSY, output wire [31:0] oIF1_DATA, output wire oMEM_ENA, input wire iMEM_BUSY, output wire oMEM_RW, output wire [P_MEM_ADDR_N-1:0] oMEM_ADDR, output wire [31:0] oMEM_DATA, input wire iMEM_VALID, output wire oMEM_BUSY, input wire [31:0] iMEM_DATA );

localparam L_PARAM_STT_IDLE = 2'h0; localparam L_PARAM_STT_ACK = 2'h1; localparam L_PARAM_STT_WORK = 2'h2; reg [1:0] b_state; reg b_authority; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_state <= L_PARAM_STT_IDLE; end else if(iRESET_SYNC)begin b_state <= L_PARAM_STT_IDLE; end else begin case(b_state) L_PARAM_STT_IDLE: begin if(iIF0_ARBIT_REQ || iIF1_ARBIT_REQ)begin b_state <= L_PARAM_STT_ACK; end end L_PARAM_STT_ACK: begin b_state <= L_PARAM_STT_WORK; end L_PARAM_STT_WORK: begin if(func_if_finish_check(b_authority, iIF0_ARBIT_FINISH, iIF1_ARBIT_FINISH))begin b_state <= L_PARAM_STT_IDLE; end end default: begin b_state <= L_PARAM_STT_IDLE; end endcase end end always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_authority <= 1'b0; end else if(iRESET_SYNC)begin b_authority <= 1'b0; end else begin if(b_state == L_PARAM_STT_IDLE)begin b_authority <= func_priority_encoder(b_authority, iIF0_ARBIT_REQ, iIF1_ARBIT_REQ); end end end function func_if_finish_check; input func_now; input func_if0_finish; input func_if1_finish; begin if(!func_now && func_if0_finish)begin func_if_finish_check = 1'b1; end else if(func_now && func_if1_finish)begin func_if_finish_check = 1'b1; end else begin func_if_finish_check = 1'b0; end end endfunction function func_priority_encoder; input func_now; input func_if0_req; input func_if1_req; begin case(func_now) 1'b0: begin if(func_if1_req)begin func_priority_encoder = 1'b1; end else if(func_if0_req)begin func_priority_encoder = 1'b0; end else begin func_priority_encoder = 1'b0; end end 1'b1: begin if(func_if0_req)begin func_priority_encoder = 1'b0; end else if(func_if1_req)begin func_priority_encoder = 1'b1; end else begin func_priority_encoder = 1'b0; end end endcase end endfunction reg b_if2mem_ena; reg b_if2mem_rw; reg [P_MEM_ADDR_N-1:0] b_if2mem_addr; reg [31:0] b_if2mem_data; reg b_mem2if0_valid; reg [31:0] b_mem2if0_data; reg b_mem2if1_valid; reg [31:0] b_mem2if1_data; always@(posedge iCLOCK or negedge inRESET)begin if(!inRESET)begin b_if2mem_ena <= 1'b0; b_if2mem_rw <= 1'b0; b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}}; b_if2mem_data <= 32'h0; b_mem2if0_valid <= 1'b0; b_mem2if0_data <= 32'h0; b_mem2if1_valid <= 1'b0; b_mem2if1_data <= 32'h0; end else if(b_state != L_PARAM_STT_WORK || iRESET_SYNC)begin b_if2mem_ena <= 1'b0; b_if2mem_rw <= 1'b0; b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}}; b_if2mem_data <= 32'h0; b_mem2if0_valid <= 1'b0; b_mem2if0_data <= 32'h0; b_mem2if1_valid <= 1'b0; b_mem2if1_data <= 32'h0; end else begin case(b_authority) 1'b0: begin b_if2mem_ena <= iIF0_ENA; b_if2mem_rw <= iIF0_RW; b_if2mem_addr <= iIF0_ADDR; b_if2mem_data <= iIF0_DATA; b_mem2if0_valid <= iMEM_VALID; b_mem2if0_data <= iMEM_DATA; b_mem2if1_valid <= 1'b0; b_mem2if1_data <= 32'h0; end 1'b1: begin b_if2mem_ena <= iIF1_ENA; b_if2mem_rw <= iIF1_RW; b_if2mem_addr <= iIF1_ADDR; b_if2mem_data <= iIF1_DATA; b_mem2if0_valid <= 1'b0; b_mem2if0_data <= 32'h0; b_mem2if1_valid <= iMEM_VALID; b_mem2if1_data <= iMEM_DATA; end endcase end end assign oIF0_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && !b_authority; assign oIF1_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && b_authority; assign oIF0_VALID = b_mem2if0_valid; assign oIF0_DATA = b_mem2if0_data; assign oIF1_VALID = b_mem2if1_valid; assign oIF1_DATA = b_mem2if1_data; assign oMEM_ENA = b_if2mem_ena; assign oMEM_RW = b_if2mem_rw; assign oMEM_ADDR = b_if2mem_addr; assign oMEM_DATA = b_if2mem_data; endmodule

data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v

memory_resource_controller.v

v

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[]

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line:2: before: "none"

1: b"%Error: data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v:2: Define or directive not defined: '`default_netype'\n : ... Suggested alternative: '`default_nettype'\n`default_netype none\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v:2: syntax error, unexpected IDENTIFIER\n`default_netype none\n ^~~~\n%Error: Exiting due to 2 error(s)\n"

function

function func_if_finish_check; input func_now; input func_if0_finish; input func_if1_finish; begin if(!func_now && func_if0_finish)begin func_if_finish_check = 1'b1; end else if(func_now && func_if1_finish)begin func_if_finish_check = 1'b1; end else begin func_if_finish_check = 1'b0; end end endfunction

function func_if_finish_check;

input func_now; input func_if0_finish; input func_if1_finish; begin if(!func_now && func_if0_finish)begin func_if_finish_check = 1'b1; end else if(func_now && func_if1_finish)begin func_if_finish_check = 1'b1; end else begin func_if_finish_check = 1'b0; end end endfunction

data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v

memory_resource_controller.v

v

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line:2: before: "none"

1: b"%Error: data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v:2: Define or directive not defined: '`default_netype'\n : ... Suggested alternative: '`default_nettype'\n`default_netype none\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/resource_controller/memory_resource_controller.v:2: syntax error, unexpected IDENTIFIER\n`default_netype none\n ^~~~\n%Error: Exiting due to 2 error(s)\n"

function

function func_priority_encoder; input func_now; input func_if0_req; input func_if1_req; begin case(func_now) 1'b0: begin if(func_if1_req)begin func_priority_encoder = 1'b1; end else if(func_if0_req)begin func_priority_encoder = 1'b0; end else begin func_priority_encoder = 1'b0; end end 1'b1: begin if(func_if0_req)begin func_priority_encoder = 1'b0; end else if(func_if1_req)begin func_priority_encoder = 1'b1; end else begin func_priority_encoder = 1'b0; end end endcase end endfunction

function func_priority_encoder;

input func_now; input func_if0_req; input func_if1_req; begin case(func_now) 1'b0: begin if(func_if1_req)begin func_priority_encoder = 1'b1; end else if(func_if0_req)begin func_priority_encoder = 1'b0; end else begin func_priority_encoder = 1'b0; end end 1'b1: begin if(func_if0_req)begin func_priority_encoder = 1'b0; end else if(func_if1_req)begin func_priority_encoder = 1'b1; end else begin func_priority_encoder = 1'b0; end end endcase end endfunction

data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v

gci_std_display_vram_controller_sram.v

v

[]

[]

[]

[(5, 409)]

1: b"%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v:230: Cannot find file containing module: 'gci_std_sync_fifo'\n gci_std_sync_fifo #(16+P_MEM_ADDR_N, 64, 6) VRAMWRITE_FIFO(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.v\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.sv\n gci_std_sync_fifo\n gci_std_sync_fifo.v\n gci_std_sync_fifo.sv\n obj_dir/gci_std_sync_fifo\n obj_dir/gci_std_sync_fifo.v\n obj_dir/gci_std_sync_fifo.sv\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v:379: Cannot find file containing module: 'gci_std_sync_fifo'\n gci_std_sync_fifo #(16, 16, 4) VRAMREAD_FIFO0(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v:391: Cannot find file containing module: 'gci_std_async_fifo'\n gci_std_async_fifo #(16, 16, 4) VRAMREAD_FIFO1(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"

module

module gci_std_display_vram_controller_sram #( parameter P_MEM_ADDR_N = 20, parameter P_AREA_H = 640, parameter P_AREA_V = 480 )( input wire iGCI_CLOCK, input wire iDISP_CLOCK, input wire inRESET, input wire iIF_WRITE_REQ, input wire [P_MEM_ADDR_N-1:0] iIF_WRITE_ADDR, input wire [15:0] iIF_WRITE_DATA, output wire oIF_WRITE_FULL, input wire iDISP_REQ, input wire iDISP_SYNC, output wire [9:0] oDISP_DATA_R, output wire [9:0] oDISP_DATA_G, output wire [9:0] oDISP_DATA_B, output wire onSRAM_CE, output wire onSRAM_WE, output wire onSRAM_OE, output wire onSRAM_UB, output wire onSRAM_LB, output wire [P_MEM_ADDR_N-1:0] oSRAM_ADDR, inout wire [15:0] ioSRAM_DATA ); wire writefifo_empty; wire [P_MEM_ADDR_N-1:0] writefifo_addr; wire [15:0] writefifo_data; wire vramfifo0_full; wire [15:0] vramfifo0_data; wire vramfifo0_empty; wire vramfifo1_full; reg b_buff_osram_rw; reg b_buff_onsram_we; reg b_buff_onsram_oe; reg b_buff_onsram_ub; reg b_buff_onsram_lb; reg [P_MEM_ADDR_N-1:0] b_buff_osram_addr; reg [15:0] b_buff_osram_data; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b0; b_buff_onsram_oe <= 1'b0; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= {P_MEM_ADDR_N{1'b0}}; b_buff_osram_data <= 16'h0; end else begin b_buff_onsram_oe <= 1'b0; case(b_main_state) L_PARAM_MAIN_STT_READ: begin case(b_rd_req_state) L_PARAM_READ_REQ_STT_ADDR_SET: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= b_rd_req_addr; b_buff_osram_data <= b_buff_osram_data; end default: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}}; b_buff_osram_data <= 16'h0; end endcase end L_PARAM_MAIN_STT_WRITE: begin case(b_wr_state) L_PARAM_WRITE_STT_ADDR_SET: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= writefifo_addr; b_buff_osram_data <= writefifo_data; end L_PARAM_WRITE_STT_LATCH_CONDITION: begin b_buff_osram_rw <= 1'b1; b_buff_onsram_we <= 1'b0; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= b_buff_osram_addr; b_buff_osram_data <= b_buff_osram_data; end L_PARAM_WRITE_STT_DATA_SET: begin b_buff_osram_rw <= 1'b1; b_buff_onsram_we <= 1'b0; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= b_buff_osram_addr; b_buff_osram_data <= b_buff_osram_data; end default: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}}; b_buff_osram_data <= 16'h0; end endcase end default: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}}; b_buff_osram_data <= 16'h0; end endcase end end assign onSRAM_CE = 1'b0; assign onSRAM_WE = b_buff_onsram_we; assign onSRAM_OE = b_buff_onsram_oe; assign onSRAM_UB = b_buff_onsram_ub; assign onSRAM_LB = b_buff_onsram_lb; assign oSRAM_ADDR = b_buff_osram_addr; assign ioSRAM_DATA = (b_buff_osram_rw)? b_buff_osram_data : 16'hzzzz; localparam L_PARAM_MAIN_STT_IDLE = 2'h0; localparam L_PARAM_MAIN_STT_READ = 2'h1; localparam L_PARAM_MAIN_STT_WRITE = 2'h2; reg [1:0] b_main_state; reg b_main_wait; reg b_main_req; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; b_main_req <= 1'b0; end else if(b_main_wait)begin b_main_req <= 1'b0; if(b_wr_end || b_rd_req_end)begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; end end else begin case(b_main_state) L_PARAM_MAIN_STT_IDLE: begin if(vramfifo0_empty)begin b_main_state <= L_PARAM_MAIN_STT_READ; b_main_req <= 1'b1; end else if(!writefifo_empty)begin b_main_state <= L_PARAM_MAIN_STT_WRITE; b_main_req <= 1'b1; end else begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; b_main_req <= 1'b0; end end L_PARAM_MAIN_STT_READ: begin b_main_state <= L_PARAM_MAIN_STT_READ; b_main_wait <= 1; b_main_req <= 1'b0; end L_PARAM_MAIN_STT_WRITE: begin b_main_state <= L_PARAM_MAIN_STT_WRITE; b_main_wait <= 1; b_main_req <= 1'b0; end default: begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; b_main_req <= 1'b0; end endcase end end localparam L_PARAM_WRITE_STT_IDLE = 3'h0; localparam L_PARAM_WRITE_STT_ADDR_SET = 3'h1; localparam L_PARAM_WRITE_STT_LATCH_CONDITION = 3'h2; localparam L_PARAM_WRITE_STT_DATA_SET = 3'h3; localparam L_PARAM_WRITE_STT_END = 3'h4; gci_std_sync_fifo #(16+P_MEM_ADDR_N, 64, 6) VRAMWRITE_FIFO( .inRESET(inRESET), .iCLOCK(iGCI_CLOCK), .iREMOVE(1'b0), .oCOUNT(), .iWR_EN(iIF_WRITE_REQ), .iWR_DATA({iIF_WRITE_ADDR, iIF_WRITE_DATA}), .oWR_FULL(oIF_WRITE_FULL), .iRD_EN(b_wr_state == L_PARAM_WRITE_STT_DATA_SET && !writefifo_empty), .oRD_DATA({writefifo_addr, writefifo_data}), .oRD_EMPTY(writefifo_empty) ); reg [2:0] b_wr_state; reg b_wr_end; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_wr_state <= L_PARAM_WRITE_STT_IDLE; b_wr_end <= 1'b0; end else begin case(b_wr_state) L_PARAM_WRITE_STT_IDLE: begin if(b_main_req && (b_main_state == L_PARAM_MAIN_STT_WRITE))begin b_wr_state <= L_PARAM_WRITE_STT_ADDR_SET; end b_wr_end <= 1'b0; end L_PARAM_WRITE_STT_ADDR_SET: begin b_wr_state <= L_PARAM_WRITE_STT_LATCH_CONDITION; end L_PARAM_WRITE_STT_LATCH_CONDITION: begin b_wr_state <= L_PARAM_WRITE_STT_DATA_SET; end L_PARAM_WRITE_STT_DATA_SET: begin if(writefifo_empty || vramfifo0_empty)begin b_wr_state <= L_PARAM_WRITE_STT_END; end else begin b_wr_state <= L_PARAM_WRITE_STT_ADDR_SET; end end L_PARAM_WRITE_STT_END: begin b_wr_state <= L_PARAM_WRITE_STT_IDLE; b_wr_end <= 1'b1; end default: begin b_wr_state <= L_PARAM_WRITE_STT_IDLE; end endcase end end localparam L_PARAM_READ_REQ_STT_IDLE = 2'h0; localparam L_PARAM_READ_REQ_STT_ADDR_SET = 2'h1; localparam L_PARAM_READ_REQ_STT_RD_END = 2'h2; reg [1:0] b_rd_req_state; reg [P_MEM_ADDR_N-1:0] b_rd_req_addr; reg b_rd_req_end; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE; b_rd_req_addr <= 20'h0; b_rd_req_end <= 1'b0; end else begin case(b_rd_req_state) L_PARAM_READ_REQ_STT_IDLE: begin if(b_main_req && (b_main_state == L_PARAM_MAIN_STT_READ))begin b_rd_req_state <= L_PARAM_READ_REQ_STT_ADDR_SET; end b_rd_req_end <= 1'b0; end L_PARAM_READ_REQ_STT_ADDR_SET: begin if(vramfifo0_full)begin b_rd_req_state <= L_PARAM_READ_REQ_STT_RD_END; end else begin b_rd_req_addr <= func_read_next_addr(b_rd_req_addr); b_rd_req_state <= L_PARAM_READ_REQ_STT_ADDR_SET; end end L_PARAM_READ_REQ_STT_RD_END: begin b_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE; b_rd_req_end <= 1'b1; end default: begin b_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE; b_rd_req_end <= 1'b0; end endcase end end function [P_MEM_ADDR_N-1:0] func_read_next_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction localparam L_PARAM_READ_LATCH_STT_IDLE = 2'h0; localparam L_PARAM_READ_LATCH_STT_ADDR_SET = 2'h1; localparam L_PARAM_READ_LATCH_STT_RD = 2'h2; localparam L_PARAM_READ_LATCH_STT_RD_END = 2'h3; reg b_rd_latch_condition; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_rd_latch_condition <= 1'b0; end else begin b_rd_latch_condition <= (b_rd_req_state == L_PARAM_READ_REQ_STT_ADDR_SET) && !vramfifo0_full; end end wire [15:0] vramfifo1_data; gci_std_sync_fifo #(16, 16, 4) VRAMREAD_FIFO0( .inRESET(inRESET), .iREMOVE(1'b0), .iCLOCK(iGCI_CLOCK), .iWR_EN(b_rd_latch_condition), .iWR_DATA(ioSRAM_DATA), .oWR_FULL(), .oWR_ALMOST_FULL(vramfifo0_full), .iRD_EN(!vramfifo0_empty && !vramfifo1_full), .oRD_DATA(vramfifo0_data), .oRD_EMPTY(vramfifo0_empty) ); gci_std_async_fifo #(16, 16, 4) VRAMREAD_FIFO1( .inRESET(inRESET), .iREMOVE(1'b0), .iWR_CLOCK(iGCI_CLOCK), .iWR_EN(!vramfifo0_empty && !vramfifo1_full), .iWR_DATA(vramfifo0_data), .oWR_FULL(vramfifo1_full), .iRD_CLOCK(iDISP_CLOCK), .iRD_EN(iDISP_REQ), .oRD_DATA(vramfifo1_data), .oRD_EMPTY() ); assign oDISP_DATA_R = {vramfifo1_data[15:11], {5{vramfifo1_data[11]}}}; assign oDISP_DATA_G = {vramfifo1_data[10:5], {4{vramfifo1_data[5]}}}; assign oDISP_DATA_B = {vramfifo1_data[4:0], {5{vramfifo1_data[0]}}}; endmodule

module gci_std_display_vram_controller_sram #( parameter P_MEM_ADDR_N = 20, parameter P_AREA_H = 640, parameter P_AREA_V = 480 )( input wire iGCI_CLOCK, input wire iDISP_CLOCK, input wire inRESET, input wire iIF_WRITE_REQ, input wire [P_MEM_ADDR_N-1:0] iIF_WRITE_ADDR, input wire [15:0] iIF_WRITE_DATA, output wire oIF_WRITE_FULL, input wire iDISP_REQ, input wire iDISP_SYNC, output wire [9:0] oDISP_DATA_R, output wire [9:0] oDISP_DATA_G, output wire [9:0] oDISP_DATA_B, output wire onSRAM_CE, output wire onSRAM_WE, output wire onSRAM_OE, output wire onSRAM_UB, output wire onSRAM_LB, output wire [P_MEM_ADDR_N-1:0] oSRAM_ADDR, inout wire [15:0] ioSRAM_DATA );

wire writefifo_empty; wire [P_MEM_ADDR_N-1:0] writefifo_addr; wire [15:0] writefifo_data; wire vramfifo0_full; wire [15:0] vramfifo0_data; wire vramfifo0_empty; wire vramfifo1_full; reg b_buff_osram_rw; reg b_buff_onsram_we; reg b_buff_onsram_oe; reg b_buff_onsram_ub; reg b_buff_onsram_lb; reg [P_MEM_ADDR_N-1:0] b_buff_osram_addr; reg [15:0] b_buff_osram_data; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b0; b_buff_onsram_oe <= 1'b0; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= {P_MEM_ADDR_N{1'b0}}; b_buff_osram_data <= 16'h0; end else begin b_buff_onsram_oe <= 1'b0; case(b_main_state) L_PARAM_MAIN_STT_READ: begin case(b_rd_req_state) L_PARAM_READ_REQ_STT_ADDR_SET: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= b_rd_req_addr; b_buff_osram_data <= b_buff_osram_data; end default: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}}; b_buff_osram_data <= 16'h0; end endcase end L_PARAM_MAIN_STT_WRITE: begin case(b_wr_state) L_PARAM_WRITE_STT_ADDR_SET: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= writefifo_addr; b_buff_osram_data <= writefifo_data; end L_PARAM_WRITE_STT_LATCH_CONDITION: begin b_buff_osram_rw <= 1'b1; b_buff_onsram_we <= 1'b0; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= b_buff_osram_addr; b_buff_osram_data <= b_buff_osram_data; end L_PARAM_WRITE_STT_DATA_SET: begin b_buff_osram_rw <= 1'b1; b_buff_onsram_we <= 1'b0; b_buff_onsram_ub <= 1'b0; b_buff_onsram_lb <= 1'b0; b_buff_osram_addr <= b_buff_osram_addr; b_buff_osram_data <= b_buff_osram_data; end default: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}}; b_buff_osram_data <= 16'h0; end endcase end default: begin b_buff_osram_rw <= 1'b0; b_buff_onsram_we <= 1'b1; b_buff_onsram_ub <= 1'b1; b_buff_onsram_lb <= 1'b1; b_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}}; b_buff_osram_data <= 16'h0; end endcase end end assign onSRAM_CE = 1'b0; assign onSRAM_WE = b_buff_onsram_we; assign onSRAM_OE = b_buff_onsram_oe; assign onSRAM_UB = b_buff_onsram_ub; assign onSRAM_LB = b_buff_onsram_lb; assign oSRAM_ADDR = b_buff_osram_addr; assign ioSRAM_DATA = (b_buff_osram_rw)? b_buff_osram_data : 16'hzzzz; localparam L_PARAM_MAIN_STT_IDLE = 2'h0; localparam L_PARAM_MAIN_STT_READ = 2'h1; localparam L_PARAM_MAIN_STT_WRITE = 2'h2; reg [1:0] b_main_state; reg b_main_wait; reg b_main_req; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; b_main_req <= 1'b0; end else if(b_main_wait)begin b_main_req <= 1'b0; if(b_wr_end || b_rd_req_end)begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; end end else begin case(b_main_state) L_PARAM_MAIN_STT_IDLE: begin if(vramfifo0_empty)begin b_main_state <= L_PARAM_MAIN_STT_READ; b_main_req <= 1'b1; end else if(!writefifo_empty)begin b_main_state <= L_PARAM_MAIN_STT_WRITE; b_main_req <= 1'b1; end else begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; b_main_req <= 1'b0; end end L_PARAM_MAIN_STT_READ: begin b_main_state <= L_PARAM_MAIN_STT_READ; b_main_wait <= 1; b_main_req <= 1'b0; end L_PARAM_MAIN_STT_WRITE: begin b_main_state <= L_PARAM_MAIN_STT_WRITE; b_main_wait <= 1; b_main_req <= 1'b0; end default: begin b_main_state <= L_PARAM_MAIN_STT_IDLE; b_main_wait <= 1'b0; b_main_req <= 1'b0; end endcase end end localparam L_PARAM_WRITE_STT_IDLE = 3'h0; localparam L_PARAM_WRITE_STT_ADDR_SET = 3'h1; localparam L_PARAM_WRITE_STT_LATCH_CONDITION = 3'h2; localparam L_PARAM_WRITE_STT_DATA_SET = 3'h3; localparam L_PARAM_WRITE_STT_END = 3'h4; gci_std_sync_fifo #(16+P_MEM_ADDR_N, 64, 6) VRAMWRITE_FIFO( .inRESET(inRESET), .iCLOCK(iGCI_CLOCK), .iREMOVE(1'b0), .oCOUNT(), .iWR_EN(iIF_WRITE_REQ), .iWR_DATA({iIF_WRITE_ADDR, iIF_WRITE_DATA}), .oWR_FULL(oIF_WRITE_FULL), .iRD_EN(b_wr_state == L_PARAM_WRITE_STT_DATA_SET && !writefifo_empty), .oRD_DATA({writefifo_addr, writefifo_data}), .oRD_EMPTY(writefifo_empty) ); reg [2:0] b_wr_state; reg b_wr_end; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_wr_state <= L_PARAM_WRITE_STT_IDLE; b_wr_end <= 1'b0; end else begin case(b_wr_state) L_PARAM_WRITE_STT_IDLE: begin if(b_main_req && (b_main_state == L_PARAM_MAIN_STT_WRITE))begin b_wr_state <= L_PARAM_WRITE_STT_ADDR_SET; end b_wr_end <= 1'b0; end L_PARAM_WRITE_STT_ADDR_SET: begin b_wr_state <= L_PARAM_WRITE_STT_LATCH_CONDITION; end L_PARAM_WRITE_STT_LATCH_CONDITION: begin b_wr_state <= L_PARAM_WRITE_STT_DATA_SET; end L_PARAM_WRITE_STT_DATA_SET: begin if(writefifo_empty || vramfifo0_empty)begin b_wr_state <= L_PARAM_WRITE_STT_END; end else begin b_wr_state <= L_PARAM_WRITE_STT_ADDR_SET; end end L_PARAM_WRITE_STT_END: begin b_wr_state <= L_PARAM_WRITE_STT_IDLE; b_wr_end <= 1'b1; end default: begin b_wr_state <= L_PARAM_WRITE_STT_IDLE; end endcase end end localparam L_PARAM_READ_REQ_STT_IDLE = 2'h0; localparam L_PARAM_READ_REQ_STT_ADDR_SET = 2'h1; localparam L_PARAM_READ_REQ_STT_RD_END = 2'h2; reg [1:0] b_rd_req_state; reg [P_MEM_ADDR_N-1:0] b_rd_req_addr; reg b_rd_req_end; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE; b_rd_req_addr <= 20'h0; b_rd_req_end <= 1'b0; end else begin case(b_rd_req_state) L_PARAM_READ_REQ_STT_IDLE: begin if(b_main_req && (b_main_state == L_PARAM_MAIN_STT_READ))begin b_rd_req_state <= L_PARAM_READ_REQ_STT_ADDR_SET; end b_rd_req_end <= 1'b0; end L_PARAM_READ_REQ_STT_ADDR_SET: begin if(vramfifo0_full)begin b_rd_req_state <= L_PARAM_READ_REQ_STT_RD_END; end else begin b_rd_req_addr <= func_read_next_addr(b_rd_req_addr); b_rd_req_state <= L_PARAM_READ_REQ_STT_ADDR_SET; end end L_PARAM_READ_REQ_STT_RD_END: begin b_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE; b_rd_req_end <= 1'b1; end default: begin b_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE; b_rd_req_end <= 1'b0; end endcase end end function [P_MEM_ADDR_N-1:0] func_read_next_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction localparam L_PARAM_READ_LATCH_STT_IDLE = 2'h0; localparam L_PARAM_READ_LATCH_STT_ADDR_SET = 2'h1; localparam L_PARAM_READ_LATCH_STT_RD = 2'h2; localparam L_PARAM_READ_LATCH_STT_RD_END = 2'h3; reg b_rd_latch_condition; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_rd_latch_condition <= 1'b0; end else begin b_rd_latch_condition <= (b_rd_req_state == L_PARAM_READ_REQ_STT_ADDR_SET) && !vramfifo0_full; end end wire [15:0] vramfifo1_data; gci_std_sync_fifo #(16, 16, 4) VRAMREAD_FIFO0( .inRESET(inRESET), .iREMOVE(1'b0), .iCLOCK(iGCI_CLOCK), .iWR_EN(b_rd_latch_condition), .iWR_DATA(ioSRAM_DATA), .oWR_FULL(), .oWR_ALMOST_FULL(vramfifo0_full), .iRD_EN(!vramfifo0_empty && !vramfifo1_full), .oRD_DATA(vramfifo0_data), .oRD_EMPTY(vramfifo0_empty) ); gci_std_async_fifo #(16, 16, 4) VRAMREAD_FIFO1( .inRESET(inRESET), .iREMOVE(1'b0), .iWR_CLOCK(iGCI_CLOCK), .iWR_EN(!vramfifo0_empty && !vramfifo1_full), .iWR_DATA(vramfifo0_data), .oWR_FULL(vramfifo1_full), .iRD_CLOCK(iDISP_CLOCK), .iRD_EN(iDISP_REQ), .oRD_DATA(vramfifo1_data), .oRD_EMPTY() ); assign oDISP_DATA_R = {vramfifo1_data[15:11], {5{vramfifo1_data[11]}}}; assign oDISP_DATA_G = {vramfifo1_data[10:5], {4{vramfifo1_data[5]}}}; assign oDISP_DATA_B = {vramfifo1_data[4:0], {5{vramfifo1_data[0]}}}; endmodule

data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v

gci_std_display_vram_controller_sram.v

v

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[]

[]

[(5, 409)]

1: b"%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v:230: Cannot find file containing module: 'gci_std_sync_fifo'\n gci_std_sync_fifo #(16+P_MEM_ADDR_N, 64, 6) VRAMWRITE_FIFO(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.v\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.sv\n gci_std_sync_fifo\n gci_std_sync_fifo.v\n gci_std_sync_fifo.sv\n obj_dir/gci_std_sync_fifo\n obj_dir/gci_std_sync_fifo.v\n obj_dir/gci_std_sync_fifo.sv\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v:379: Cannot find file containing module: 'gci_std_sync_fifo'\n gci_std_sync_fifo #(16, 16, 4) VRAMREAD_FIFO0(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_sram.v:391: Cannot find file containing module: 'gci_std_async_fifo'\n gci_std_async_fifo #(16, 16, 4) VRAMREAD_FIFO1(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"

function

function [P_MEM_ADDR_N-1:0] func_read_next_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction

function [P_MEM_ADDR_N-1:0] func_read_next_addr;

input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction

data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v

gci_std_display_vram_controller_ssram.v

v

[]

[]

[]

[(5, 597)]

1: b'%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:103: Cannot find file containing module: \'gci_std_sync_fifo\'\n gci_std_sync_fifo #(36, P_WRITE_FIFO_DEPTH, P_WRITE_FIFO_DEPTH_N) VRAMWRITE_FIFO(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.v\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.sv\n gci_std_sync_fifo\n gci_std_sync_fifo.v\n gci_std_sync_fifo.sv\n obj_dir/gci_std_sync_fifo\n obj_dir/gci_std_sync_fifo.v\n obj_dir/gci_std_sync_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:195: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:195: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:200: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:200: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:206: Operator FUNCREF \'func_read_2prev_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_2prev_addr(b_read_addr); \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:206: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_2prev_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_2prev_addr(b_read_addr); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:210: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr); \n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:210: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr); \n ^~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:304: Cannot find file containing module: \'gci_std_sync_fifo\'\n gci_std_sync_fifo #(32, P_READ_SYNC_FIFO_DEPTH, P_READ_SYNC_FIFO_DEPTH_N) VRAMREAD_FIFO0(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:316: Cannot find file containing module: \'gci_std_async_fifo\'\n gci_std_async_fifo #(32, P_READ_ASYNC_FIFO_DEPTH, P_READ_ASYNC_FIFO_DEPTH_N) VRAMREAD_FIFO1(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'

module

module gci_std_display_vram_controller_ssram #( parameter P_MEM_ADDR_N = 20, parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_WRITE_FIFO_DEPTH = 64, parameter P_WRITE_FIFO_DEPTH_N = 6, parameter P_READ_SYNC_FIFO_DEPTH = 64, parameter P_READ_SYNC_FIFO_DEPTH_N = 6, parameter P_READ_ASYNC_FIFO_DEPTH = 16, parameter P_READ_ASYNC_FIFO_DEPTH_N = 4 )( input wire iGCI_CLOCK, input wire iDISP_CLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF_WRITE_REQ, input wire [19:0] iIF_WRITE_ADDR, input wire [15:0] iIF_WRITE_DATA, output wire oIF_WRITE_FULL, input wire iDISP_REQ, input wire iDISP_SYNC, output [9:0] oDISP_DATA_R, output [9:0] oDISP_DATA_G, output [9:0] oDISP_DATA_B, output wire oSSRAM_CLOCK, output wire onSSRAM_ADSC, output wire onSSRAM_ADSP, output wire onSSRAM_ADV, output wire onSSRAM_GW, output wire onSSRAM_OE, output wire onSSRAM_WE, output wire [3:0] onSSRAM_BE, output wire onSSRAM_CE1, output wire oSSRAM_CE2, output wire onSSRAM_CE3, output wire [18:0] oSSRAM_ADDR, inout wire [31:0] ioSSRAM_DATA, inout wire [3:0] ioSSRAM_PARITY ); localparam P_L_MAIN_STT_IDLE = 2'h0; localparam P_L_MAIN_STT_READ = 2'h1; localparam P_L_MAIN_STT_WRITE = 2'h2; localparam P_L_READ_STT_IDLE = 2'h0; localparam P_L_READ_STT_SET_ADDR = 2'h1; localparam P_L_READ_STT_WAIT = 2'h2; localparam P_L_READ_STT_GET_DATA = 2'h3; localparam P_L_WRITE_STT_IDLE = 2'h0; localparam P_L_WRITE_STT_WRITE = 2'h1; localparam P_L_WRITE_STT_STOP = 2'h2; wire [19:0] writefifo_addr; wire [15:0] writefifo_data; wire writefifo_empty; reg [1:0] b_main_state; reg b_main_job_start; reg [1:0] b_read_state; reg [18:0] b_read_addr; reg b_read_finish; reg [1:0] b_write_state; reg b_write_finish; reg b_get_data_valid; wire vramfifo0_almost_full; wire vramfifo0_empty; wire [31:0] vramfifo0_data; wire vramfifo1_full; wire vram_read_start_condition = b_main_job_start && (b_main_state == P_L_MAIN_STT_READ); wire vram_write_start_condition = b_main_job_start && (b_main_state == P_L_MAIN_STT_WRITE); wire vram_read_sequence_condition = (b_read_state == P_L_READ_STT_GET_DATA); wire vram_write_sequence_condition = (b_write_state == P_L_WRITE_STT_WRITE); gci_std_sync_fifo #(36, P_WRITE_FIFO_DEPTH, P_WRITE_FIFO_DEPTH_N) VRAMWRITE_FIFO( .inRESET(inRESET), .iCLOCK(iGCI_CLOCK), .iREMOVE(iRESET_SYNC), .oCOUNT(), .iWR_EN(iIF_WRITE_REQ), .iWR_DATA({iIF_WRITE_ADDR, iIF_WRITE_DATA}), .oWR_FULL(oIF_WRITE_FULL), .iRD_EN(vram_write_sequence_condition), .oRD_DATA({writefifo_addr, writefifo_data}), .oRD_EMPTY(writefifo_empty), .oRD_ALMOST_EMPTY() ); always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_main_state <= P_L_MAIN_STT_IDLE; b_main_job_start <= 1'b0; end else if(iRESET_SYNC)begin b_main_state <= P_L_MAIN_STT_IDLE; b_main_job_start <= 1'b0; end else begin case(b_main_state) P_L_MAIN_STT_IDLE: begin if(vramfifo0_empty)begin b_main_state <= P_L_MAIN_STT_READ; b_main_job_start <= 1'b1; end else if(!writefifo_empty)begin b_main_state <= P_L_MAIN_STT_WRITE; b_main_job_start <= 1'b1; end else begin b_main_job_start <= 1'b0; end end P_L_MAIN_STT_READ: begin b_main_job_start <= 1'b0; if(b_read_finish)begin b_main_state <= P_L_MAIN_STT_IDLE; end end P_L_MAIN_STT_WRITE: begin b_main_job_start <= 1'b0; if(b_write_finish)begin b_main_state <= P_L_MAIN_STT_IDLE; end end default: begin b_main_job_start <= 1'b0; b_main_state <= P_L_MAIN_STT_IDLE; end endcase end end always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_read_state <= P_L_READ_STT_IDLE; b_read_addr <= 19'h0; b_read_finish <= 1'b0; end else if(iRESET_SYNC)begin b_read_state <= P_L_READ_STT_IDLE; b_read_addr <= 19'h0; b_read_finish <= 1'b0; end else begin case(b_read_state) P_L_READ_STT_IDLE: begin b_read_finish <= 1'b0; if(vram_read_start_condition)begin b_read_state <= P_L_READ_STT_SET_ADDR; end end P_L_READ_STT_SET_ADDR: begin b_read_state <= P_L_READ_STT_WAIT; b_read_addr <= func_read_next_addr(b_read_addr); end P_L_READ_STT_WAIT: begin b_read_state <= P_L_READ_STT_GET_DATA; b_read_addr <= func_read_next_addr(b_read_addr); end P_L_READ_STT_GET_DATA: begin if(vramfifo0_almost_full)begin b_read_state <= P_L_READ_STT_IDLE; b_read_addr <= func_read_2prev_addr(b_read_addr); b_read_finish <= 1'b1; end else begin b_read_addr <= func_read_next_addr(b_read_addr); end end endcase end end function [P_MEM_ADDR_N-1:0] func_read_next_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < ((P_AREA_H*P_AREA_V)/2)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction function [P_MEM_ADDR_N-1:0] func_read_2prev_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr == {P_MEM_ADDR_N{1'b0}})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-2; end else if(func_now_addr == {{P_MEM_ADDR_N-1{1'b0}}, 1'b1})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-1; end else begin func_read_2prev_addr = func_now_addr - 2; end end endfunction always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_write_state <= P_L_WRITE_STT_IDLE; b_write_finish <= 1'b0; end else if(iRESET_SYNC)begin b_write_state <= P_L_WRITE_STT_IDLE; b_write_finish <= 1'b0; end else begin case(b_write_state) P_L_WRITE_STT_IDLE: begin b_write_finish <= 1'b0; if(vram_write_start_condition)begin b_write_state <= P_L_WRITE_STT_WRITE; end end P_L_WRITE_STT_WRITE: begin if(writefifo_empty || vramfifo0_empty)begin b_write_state <= P_L_WRITE_STT_STOP; end end P_L_WRITE_STT_STOP: begin b_write_state <= P_L_WRITE_STT_IDLE; b_write_finish <= 1'b1; end endcase end end reg b_get_data_tmp; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_get_data_valid <= 1'b0; b_get_data_tmp <= 1'b0; end else if(iRESET_SYNC)begin b_get_data_valid <= 1'b0; b_get_data_tmp <= 1'b0; end else begin b_get_data_tmp <= vram_read_sequence_condition; b_get_data_valid <= vram_read_sequence_condition; end end wire [31:0] vramfifo1_data; wire vramfifo0_full; wire vramfifo1_empty; gci_std_sync_fifo #(32, P_READ_SYNC_FIFO_DEPTH, P_READ_SYNC_FIFO_DEPTH_N) VRAMREAD_FIFO0( .inRESET(inRESET), .iREMOVE(iRESET_SYNC), .iCLOCK(iGCI_CLOCK), .iWR_EN(b_get_data_valid && !vramfifo0_full), .iWR_DATA(ioSSRAM_DATA), .oWR_FULL(vramfifo0_full), .oWR_ALMOST_FULL(vramfifo0_almost_full), .iRD_EN(!vramfifo0_empty && !vramfifo1_full), .oRD_DATA(vramfifo0_data), .oRD_EMPTY(vramfifo0_empty) ); gci_std_async_fifo #(32, P_READ_ASYNC_FIFO_DEPTH, P_READ_ASYNC_FIFO_DEPTH_N) VRAMREAD_FIFO1( .inRESET(inRESET), .iREMOVE(iRESET_SYNC), .iWR_CLOCK(iGCI_CLOCK), .iWR_EN(!vramfifo0_empty && !vramfifo1_full), .iWR_DATA(vramfifo0_data), .oWR_FULL(vramfifo1_full), .iRD_CLOCK(iDISP_CLOCK), .iRD_EN(!vramfifo1_empty && b_dispout_state == P_L_DISPOUT_STT_1ST), .oRD_DATA(vramfifo1_data), .oRD_EMPTY(vramfifo1_empty) ); parameter P_L_DISPOUT_STT_1ST = 1'b0; parameter P_L_DISPOUT_STT_2RD = 1'b1; reg b_dispout_state; reg [15:0] b_dispout_current_data; reg [15:0] b_dispout_next_data; always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_dispout_state <= P_L_DISPOUT_STT_1ST; b_dispout_current_data <= 16'h0; b_dispout_next_data <= 16'h0; end else if(iRESET_SYNC)begin b_dispout_state <= P_L_DISPOUT_STT_1ST; b_dispout_current_data <= 16'h0; b_dispout_next_data <= 16'h0; end else begin case(b_dispout_state) P_L_DISPOUT_STT_1ST: begin if(!vramfifo1_empty)begin {b_dispout_next_data, b_dispout_current_data} <= vramfifo1_data; b_dispout_state <= P_L_DISPOUT_STT_2RD; end end P_L_DISPOUT_STT_2RD: begin if(iDISP_REQ)begin b_dispout_current_data <= b_dispout_next_data; b_dispout_state <= P_L_DISPOUT_STT_1ST; end end endcase end end reg bn_ram_buff_adsc; reg bn_ram_buff_adsp; reg bn_ram_buff_adv; reg bn_ram_buff_gw; reg bn_ram_buff_oe; reg bn_ram_buff_we; reg [3:0] bn_ram_buff_be; reg bn_ram_buff_ce3; reg [18:0] b_ram_buff_addr; reg [31:0] b_ram_buff_data; reg [3:0] b_ram_buff_parity; reg b_ram_buff_rw; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end else if(iRESET_SYNC)begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end else begin if(vram_write_sequence_condition)begin case(b_write_state) P_L_WRITE_STT_IDLE: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_WRITE_STT_WRITE: begin bn_ram_buff_adsc <= 1'b1; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b1; bn_ram_buff_be <= (!writefifo_addr[0])? 4'b0011 : 4'b1100; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= writefifo_addr[19:1]; b_ram_buff_data <= {writefifo_data, writefifo_data}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b1; end P_L_WRITE_STT_STOP: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end endcase end else if(b_main_state == P_L_MAIN_STT_READ)begin case(b_read_state) P_L_READ_STT_IDLE: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_READ_STT_SET_ADDR: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b1; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= b_read_addr; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_READ_STT_WAIT: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b1; bn_ram_buff_adv <= 1'b1; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= b_read_addr; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_READ_STT_GET_DATA: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b1; bn_ram_buff_adv <= 1'b1; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b1; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= b_read_addr; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end endcase end else begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end end end assign oSSRAM_CLOCK = iGCI_CLOCK; assign onSSRAM_ADSC = !bn_ram_buff_adsc; assign onSSRAM_ADSP = !bn_ram_buff_adsp; assign onSSRAM_ADV = !bn_ram_buff_adv; assign onSSRAM_GW = !bn_ram_buff_gw; assign onSSRAM_OE = !bn_ram_buff_oe; assign onSSRAM_WE = !bn_ram_buff_we; assign onSSRAM_BE = ~bn_ram_buff_be; assign onSSRAM_CE1 = 1'b0; assign oSSRAM_CE2 = 1'b1; assign onSSRAM_CE3 = !bn_ram_buff_ce3; assign oSSRAM_ADDR = b_ram_buff_addr; assign ioSSRAM_DATA = (b_ram_buff_rw)? b_ram_buff_data : {32{1'bz}}; assign ioSSRAM_PARITY = (b_ram_buff_rw)? b_ram_buff_parity : {4{1'bz}}; assign oDISP_DATA_B = {b_dispout_current_data[15:11], {5{b_dispout_current_data[11]}}}; assign oDISP_DATA_G = {b_dispout_current_data[10:5], {4{b_dispout_current_data[5]}}}; assign oDISP_DATA_R = {b_dispout_current_data[4:0], {5{b_dispout_current_data[0]}}}; endmodule

module gci_std_display_vram_controller_ssram #( parameter P_MEM_ADDR_N = 20, parameter P_AREA_H = 640, parameter P_AREA_V = 480, parameter P_WRITE_FIFO_DEPTH = 64, parameter P_WRITE_FIFO_DEPTH_N = 6, parameter P_READ_SYNC_FIFO_DEPTH = 64, parameter P_READ_SYNC_FIFO_DEPTH_N = 6, parameter P_READ_ASYNC_FIFO_DEPTH = 16, parameter P_READ_ASYNC_FIFO_DEPTH_N = 4 )( input wire iGCI_CLOCK, input wire iDISP_CLOCK, input wire inRESET, input wire iRESET_SYNC, input wire iIF_WRITE_REQ, input wire [19:0] iIF_WRITE_ADDR, input wire [15:0] iIF_WRITE_DATA, output wire oIF_WRITE_FULL, input wire iDISP_REQ, input wire iDISP_SYNC, output [9:0] oDISP_DATA_R, output [9:0] oDISP_DATA_G, output [9:0] oDISP_DATA_B, output wire oSSRAM_CLOCK, output wire onSSRAM_ADSC, output wire onSSRAM_ADSP, output wire onSSRAM_ADV, output wire onSSRAM_GW, output wire onSSRAM_OE, output wire onSSRAM_WE, output wire [3:0] onSSRAM_BE, output wire onSSRAM_CE1, output wire oSSRAM_CE2, output wire onSSRAM_CE3, output wire [18:0] oSSRAM_ADDR, inout wire [31:0] ioSSRAM_DATA, inout wire [3:0] ioSSRAM_PARITY );

localparam P_L_MAIN_STT_IDLE = 2'h0; localparam P_L_MAIN_STT_READ = 2'h1; localparam P_L_MAIN_STT_WRITE = 2'h2; localparam P_L_READ_STT_IDLE = 2'h0; localparam P_L_READ_STT_SET_ADDR = 2'h1; localparam P_L_READ_STT_WAIT = 2'h2; localparam P_L_READ_STT_GET_DATA = 2'h3; localparam P_L_WRITE_STT_IDLE = 2'h0; localparam P_L_WRITE_STT_WRITE = 2'h1; localparam P_L_WRITE_STT_STOP = 2'h2; wire [19:0] writefifo_addr; wire [15:0] writefifo_data; wire writefifo_empty; reg [1:0] b_main_state; reg b_main_job_start; reg [1:0] b_read_state; reg [18:0] b_read_addr; reg b_read_finish; reg [1:0] b_write_state; reg b_write_finish; reg b_get_data_valid; wire vramfifo0_almost_full; wire vramfifo0_empty; wire [31:0] vramfifo0_data; wire vramfifo1_full; wire vram_read_start_condition = b_main_job_start && (b_main_state == P_L_MAIN_STT_READ); wire vram_write_start_condition = b_main_job_start && (b_main_state == P_L_MAIN_STT_WRITE); wire vram_read_sequence_condition = (b_read_state == P_L_READ_STT_GET_DATA); wire vram_write_sequence_condition = (b_write_state == P_L_WRITE_STT_WRITE); gci_std_sync_fifo #(36, P_WRITE_FIFO_DEPTH, P_WRITE_FIFO_DEPTH_N) VRAMWRITE_FIFO( .inRESET(inRESET), .iCLOCK(iGCI_CLOCK), .iREMOVE(iRESET_SYNC), .oCOUNT(), .iWR_EN(iIF_WRITE_REQ), .iWR_DATA({iIF_WRITE_ADDR, iIF_WRITE_DATA}), .oWR_FULL(oIF_WRITE_FULL), .iRD_EN(vram_write_sequence_condition), .oRD_DATA({writefifo_addr, writefifo_data}), .oRD_EMPTY(writefifo_empty), .oRD_ALMOST_EMPTY() ); always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_main_state <= P_L_MAIN_STT_IDLE; b_main_job_start <= 1'b0; end else if(iRESET_SYNC)begin b_main_state <= P_L_MAIN_STT_IDLE; b_main_job_start <= 1'b0; end else begin case(b_main_state) P_L_MAIN_STT_IDLE: begin if(vramfifo0_empty)begin b_main_state <= P_L_MAIN_STT_READ; b_main_job_start <= 1'b1; end else if(!writefifo_empty)begin b_main_state <= P_L_MAIN_STT_WRITE; b_main_job_start <= 1'b1; end else begin b_main_job_start <= 1'b0; end end P_L_MAIN_STT_READ: begin b_main_job_start <= 1'b0; if(b_read_finish)begin b_main_state <= P_L_MAIN_STT_IDLE; end end P_L_MAIN_STT_WRITE: begin b_main_job_start <= 1'b0; if(b_write_finish)begin b_main_state <= P_L_MAIN_STT_IDLE; end end default: begin b_main_job_start <= 1'b0; b_main_state <= P_L_MAIN_STT_IDLE; end endcase end end always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_read_state <= P_L_READ_STT_IDLE; b_read_addr <= 19'h0; b_read_finish <= 1'b0; end else if(iRESET_SYNC)begin b_read_state <= P_L_READ_STT_IDLE; b_read_addr <= 19'h0; b_read_finish <= 1'b0; end else begin case(b_read_state) P_L_READ_STT_IDLE: begin b_read_finish <= 1'b0; if(vram_read_start_condition)begin b_read_state <= P_L_READ_STT_SET_ADDR; end end P_L_READ_STT_SET_ADDR: begin b_read_state <= P_L_READ_STT_WAIT; b_read_addr <= func_read_next_addr(b_read_addr); end P_L_READ_STT_WAIT: begin b_read_state <= P_L_READ_STT_GET_DATA; b_read_addr <= func_read_next_addr(b_read_addr); end P_L_READ_STT_GET_DATA: begin if(vramfifo0_almost_full)begin b_read_state <= P_L_READ_STT_IDLE; b_read_addr <= func_read_2prev_addr(b_read_addr); b_read_finish <= 1'b1; end else begin b_read_addr <= func_read_next_addr(b_read_addr); end end endcase end end function [P_MEM_ADDR_N-1:0] func_read_next_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < ((P_AREA_H*P_AREA_V)/2)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction function [P_MEM_ADDR_N-1:0] func_read_2prev_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr == {P_MEM_ADDR_N{1'b0}})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-2; end else if(func_now_addr == {{P_MEM_ADDR_N-1{1'b0}}, 1'b1})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-1; end else begin func_read_2prev_addr = func_now_addr - 2; end end endfunction always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_write_state <= P_L_WRITE_STT_IDLE; b_write_finish <= 1'b0; end else if(iRESET_SYNC)begin b_write_state <= P_L_WRITE_STT_IDLE; b_write_finish <= 1'b0; end else begin case(b_write_state) P_L_WRITE_STT_IDLE: begin b_write_finish <= 1'b0; if(vram_write_start_condition)begin b_write_state <= P_L_WRITE_STT_WRITE; end end P_L_WRITE_STT_WRITE: begin if(writefifo_empty || vramfifo0_empty)begin b_write_state <= P_L_WRITE_STT_STOP; end end P_L_WRITE_STT_STOP: begin b_write_state <= P_L_WRITE_STT_IDLE; b_write_finish <= 1'b1; end endcase end end reg b_get_data_tmp; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin b_get_data_valid <= 1'b0; b_get_data_tmp <= 1'b0; end else if(iRESET_SYNC)begin b_get_data_valid <= 1'b0; b_get_data_tmp <= 1'b0; end else begin b_get_data_tmp <= vram_read_sequence_condition; b_get_data_valid <= vram_read_sequence_condition; end end wire [31:0] vramfifo1_data; wire vramfifo0_full; wire vramfifo1_empty; gci_std_sync_fifo #(32, P_READ_SYNC_FIFO_DEPTH, P_READ_SYNC_FIFO_DEPTH_N) VRAMREAD_FIFO0( .inRESET(inRESET), .iREMOVE(iRESET_SYNC), .iCLOCK(iGCI_CLOCK), .iWR_EN(b_get_data_valid && !vramfifo0_full), .iWR_DATA(ioSSRAM_DATA), .oWR_FULL(vramfifo0_full), .oWR_ALMOST_FULL(vramfifo0_almost_full), .iRD_EN(!vramfifo0_empty && !vramfifo1_full), .oRD_DATA(vramfifo0_data), .oRD_EMPTY(vramfifo0_empty) ); gci_std_async_fifo #(32, P_READ_ASYNC_FIFO_DEPTH, P_READ_ASYNC_FIFO_DEPTH_N) VRAMREAD_FIFO1( .inRESET(inRESET), .iREMOVE(iRESET_SYNC), .iWR_CLOCK(iGCI_CLOCK), .iWR_EN(!vramfifo0_empty && !vramfifo1_full), .iWR_DATA(vramfifo0_data), .oWR_FULL(vramfifo1_full), .iRD_CLOCK(iDISP_CLOCK), .iRD_EN(!vramfifo1_empty && b_dispout_state == P_L_DISPOUT_STT_1ST), .oRD_DATA(vramfifo1_data), .oRD_EMPTY(vramfifo1_empty) ); parameter P_L_DISPOUT_STT_1ST = 1'b0; parameter P_L_DISPOUT_STT_2RD = 1'b1; reg b_dispout_state; reg [15:0] b_dispout_current_data; reg [15:0] b_dispout_next_data; always@(posedge iDISP_CLOCK or negedge inRESET)begin if(!inRESET)begin b_dispout_state <= P_L_DISPOUT_STT_1ST; b_dispout_current_data <= 16'h0; b_dispout_next_data <= 16'h0; end else if(iRESET_SYNC)begin b_dispout_state <= P_L_DISPOUT_STT_1ST; b_dispout_current_data <= 16'h0; b_dispout_next_data <= 16'h0; end else begin case(b_dispout_state) P_L_DISPOUT_STT_1ST: begin if(!vramfifo1_empty)begin {b_dispout_next_data, b_dispout_current_data} <= vramfifo1_data; b_dispout_state <= P_L_DISPOUT_STT_2RD; end end P_L_DISPOUT_STT_2RD: begin if(iDISP_REQ)begin b_dispout_current_data <= b_dispout_next_data; b_dispout_state <= P_L_DISPOUT_STT_1ST; end end endcase end end reg bn_ram_buff_adsc; reg bn_ram_buff_adsp; reg bn_ram_buff_adv; reg bn_ram_buff_gw; reg bn_ram_buff_oe; reg bn_ram_buff_we; reg [3:0] bn_ram_buff_be; reg bn_ram_buff_ce3; reg [18:0] b_ram_buff_addr; reg [31:0] b_ram_buff_data; reg [3:0] b_ram_buff_parity; reg b_ram_buff_rw; always@(posedge iGCI_CLOCK or negedge inRESET)begin if(!inRESET)begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end else if(iRESET_SYNC)begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end else begin if(vram_write_sequence_condition)begin case(b_write_state) P_L_WRITE_STT_IDLE: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_WRITE_STT_WRITE: begin bn_ram_buff_adsc <= 1'b1; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b1; bn_ram_buff_be <= (!writefifo_addr[0])? 4'b0011 : 4'b1100; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= writefifo_addr[19:1]; b_ram_buff_data <= {writefifo_data, writefifo_data}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b1; end P_L_WRITE_STT_STOP: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end endcase end else if(b_main_state == P_L_MAIN_STT_READ)begin case(b_read_state) P_L_READ_STT_IDLE: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_READ_STT_SET_ADDR: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b1; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= b_read_addr; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_READ_STT_WAIT: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b1; bn_ram_buff_adv <= 1'b1; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= b_read_addr; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end P_L_READ_STT_GET_DATA: begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b1; bn_ram_buff_adv <= 1'b1; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b1; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b1; b_ram_buff_addr <= b_read_addr; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end endcase end else begin bn_ram_buff_adsc <= 1'b0; bn_ram_buff_adsp <= 1'b0; bn_ram_buff_adv <= 1'b0; bn_ram_buff_gw <= 1'b0; bn_ram_buff_oe <= 1'b0; bn_ram_buff_we <= 1'b0; bn_ram_buff_be <= {4{1'b0}}; bn_ram_buff_ce3 <= 1'b0; b_ram_buff_addr <= {19{1'b0}}; b_ram_buff_data <= {32{1'b0}}; b_ram_buff_parity <= {4{1'b0}}; b_ram_buff_rw <= 1'b0; end end end assign oSSRAM_CLOCK = iGCI_CLOCK; assign onSSRAM_ADSC = !bn_ram_buff_adsc; assign onSSRAM_ADSP = !bn_ram_buff_adsp; assign onSSRAM_ADV = !bn_ram_buff_adv; assign onSSRAM_GW = !bn_ram_buff_gw; assign onSSRAM_OE = !bn_ram_buff_oe; assign onSSRAM_WE = !bn_ram_buff_we; assign onSSRAM_BE = ~bn_ram_buff_be; assign onSSRAM_CE1 = 1'b0; assign oSSRAM_CE2 = 1'b1; assign onSSRAM_CE3 = !bn_ram_buff_ce3; assign oSSRAM_ADDR = b_ram_buff_addr; assign ioSSRAM_DATA = (b_ram_buff_rw)? b_ram_buff_data : {32{1'bz}}; assign ioSSRAM_PARITY = (b_ram_buff_rw)? b_ram_buff_parity : {4{1'bz}}; assign oDISP_DATA_B = {b_dispout_current_data[15:11], {5{b_dispout_current_data[11]}}}; assign oDISP_DATA_G = {b_dispout_current_data[10:5], {4{b_dispout_current_data[5]}}}; assign oDISP_DATA_R = {b_dispout_current_data[4:0], {5{b_dispout_current_data[0]}}}; endmodule

data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v

gci_std_display_vram_controller_ssram.v

v

[]

[]

[]

[(5, 597)]

1: b'%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:103: Cannot find file containing module: \'gci_std_sync_fifo\'\n gci_std_sync_fifo #(36, P_WRITE_FIFO_DEPTH, P_WRITE_FIFO_DEPTH_N) VRAMWRITE_FIFO(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.v\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.sv\n gci_std_sync_fifo\n gci_std_sync_fifo.v\n gci_std_sync_fifo.sv\n obj_dir/gci_std_sync_fifo\n obj_dir/gci_std_sync_fifo.v\n obj_dir/gci_std_sync_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:195: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:195: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:200: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:200: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:206: Operator FUNCREF \'func_read_2prev_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_2prev_addr(b_read_addr); \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:206: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_2prev_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_2prev_addr(b_read_addr); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:210: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr); \n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:210: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr); \n ^~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:304: Cannot find file containing module: \'gci_std_sync_fifo\'\n gci_std_sync_fifo #(32, P_READ_SYNC_FIFO_DEPTH, P_READ_SYNC_FIFO_DEPTH_N) VRAMREAD_FIFO0(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:316: Cannot find file containing module: \'gci_std_async_fifo\'\n gci_std_async_fifo #(32, P_READ_ASYNC_FIFO_DEPTH, P_READ_ASYNC_FIFO_DEPTH_N) VRAMREAD_FIFO1(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'

function

function [P_MEM_ADDR_N-1:0] func_read_next_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < ((P_AREA_H*P_AREA_V)/2)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction

function [P_MEM_ADDR_N-1:0] func_read_next_addr;

input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr < ((P_AREA_H*P_AREA_V)/2)-1)begin func_read_next_addr = func_now_addr + 1; end else begin func_read_next_addr = {P_MEM_ADDR_N{1'b0}}; end end endfunction

data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v

gci_std_display_vram_controller_ssram.v

v

[]

[]

[]

[(5, 597)]

1: b'%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:103: Cannot find file containing module: \'gci_std_sync_fifo\'\n gci_std_sync_fifo #(36, P_WRITE_FIFO_DEPTH, P_WRITE_FIFO_DEPTH_N) VRAMWRITE_FIFO(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.v\n data/full_repos/permissive/9877430/rtl/vram_controller,data/full_repos/permissive/9877430/gci_std_sync_fifo.sv\n gci_std_sync_fifo\n gci_std_sync_fifo.v\n gci_std_sync_fifo.sv\n obj_dir/gci_std_sync_fifo\n obj_dir/gci_std_sync_fifo.v\n obj_dir/gci_std_sync_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:195: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:195: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:200: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:200: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:206: Operator FUNCREF \'func_read_2prev_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_2prev_addr(b_read_addr); \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:206: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_2prev_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_2prev_addr(b_read_addr); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:210: Operator FUNCREF \'func_read_next_addr\' expects 20 bits on the Function Argument, but Function Argument\'s VARREF \'b_read_addr\' generates 19 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr); \n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:210: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'func_read_next_addr\' generates 20 bits.\n : ... In instance gci_std_display_vram_controller_ssram\n b_read_addr <= func_read_next_addr(b_read_addr); \n ^~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:304: Cannot find file containing module: \'gci_std_sync_fifo\'\n gci_std_sync_fifo #(32, P_READ_SYNC_FIFO_DEPTH, P_READ_SYNC_FIFO_DEPTH_N) VRAMREAD_FIFO0(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9877430/rtl/vram_controller/gci_std_display_vram_controller_ssram.v:316: Cannot find file containing module: \'gci_std_async_fifo\'\n gci_std_async_fifo #(32, P_READ_ASYNC_FIFO_DEPTH, P_READ_ASYNC_FIFO_DEPTH_N) VRAMREAD_FIFO1(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'

function

function [P_MEM_ADDR_N-1:0] func_read_2prev_addr; input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr == {P_MEM_ADDR_N{1'b0}})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-2; end else if(func_now_addr == {{P_MEM_ADDR_N-1{1'b0}}, 1'b1})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-1; end else begin func_read_2prev_addr = func_now_addr - 2; end end endfunction

function [P_MEM_ADDR_N-1:0] func_read_2prev_addr;

input [P_MEM_ADDR_N-1:0] func_now_addr; begin if(func_now_addr == {P_MEM_ADDR_N{1'b0}})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-2; end else if(func_now_addr == {{P_MEM_ADDR_N-1{1'b0}}, 1'b1})begin func_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-1; end else begin func_read_2prev_addr = func_now_addr - 2; end end endfunction

data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v

is61wv102416bll.v

v

[]

[]

[]

line:104: before: "begin"

1: b'%Warning-STMTDLY: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:103: Unsupported: Ignoring delay on this delayed statement.\n #Thzwe\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:101: Unsupported: Ignoring delay on this delayed statement.\n #Tsa\n ^\n%Warning-WIDTH: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:79: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n : ... In instance is61wv102416bll\nassign dout [(dqbits/2 - 1) : 0] = LB_ ? 8\'bz : bank0[A];\n ^\n%Warning-WIDTH: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:80: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n : ... In instance is61wv102416bll\nassign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8\'bz : bank1[A];\n ^\n%Warning-WIDTH: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:105: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n : ... In instance is61wv102416bll\n bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:105: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n : ... In instance is61wv102416bll\n bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:106: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n : ... In instance is61wv102416bll\n bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];\n ^\n%Warning-WIDTH: data/full_repos/permissive/9877430/sim/model/is61wv102416bll.v:106: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n : ... In instance is61wv102416bll\n bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'

module

module is61wv102416bll (A, IO, CE_, OE_, WE_, LB_, UB_); parameter SPEED_RANK = 10; localparam dqbits = 16; localparam memdepth = 1048576; localparam addbits = 20; localparam Taa = 10; localparam Toha = 3; localparam Thzce = 4; localparam Tsa = 0; localparam Thzwe = 5; input CE_, OE_, WE_, LB_, UB_; input [(addbits - 1) : 0] A; inout [(dqbits - 1) : 0] IO; wire [(dqbits - 1) : 0] dout; reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth]; reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth]; wire r_en = WE_ & (~CE_) & (~OE_); wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz; assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A]; assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A]; always @(A or w_en) begin #Tsa if (w_en) #Thzwe begin bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0]; bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)]; end end specify specparam tSA = 0, tAW = 8, tSCE = 8, tSD = 6, tPWE2 = 8, tPWE1 = 8, tPBW = 8; $setup (A, negedge CE_, tSA); $setup (A, posedge CE_, tAW); $setup (IO, posedge CE_, tSD); $setup (A, negedge WE_, tSA); $setup (IO, posedge WE_, tSD); $setup (A, negedge LB_, tSA); $setup (A, negedge UB_, tSA); $width (negedge CE_, tSCE); $width (negedge LB_, tPBW); $width (negedge UB_, tPBW); `ifdef OEb $width (negedge WE_, tPWE1); `else $width (negedge WE_, tPWE2); `endif endspecify endmodule

module is61wv102416bll (A, IO, CE_, OE_, WE_, LB_, UB_);

parameter SPEED_RANK = 10; localparam dqbits = 16; localparam memdepth = 1048576; localparam addbits = 20; localparam Taa = 10; localparam Toha = 3; localparam Thzce = 4; localparam Tsa = 0; localparam Thzwe = 5; input CE_, OE_, WE_, LB_, UB_; input [(addbits - 1) : 0] A; inout [(dqbits - 1) : 0] IO; wire [(dqbits - 1) : 0] dout; reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth]; reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth]; wire r_en = WE_ & (~CE_) & (~OE_); wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz; assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A]; assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A]; always @(A or w_en) begin #Tsa if (w_en) #Thzwe begin bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0]; bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)]; end end specify specparam tSA = 0, tAW = 8, tSCE = 8, tSD = 6, tPWE2 = 8, tPWE1 = 8, tPBW = 8; $setup (A, negedge CE_, tSA); $setup (A, posedge CE_, tAW); $setup (IO, posedge CE_, tSD); $setup (A, negedge WE_, tSA); $setup (IO, posedge WE_, tSD); $setup (A, negedge LB_, tSA); $setup (A, negedge UB_, tSA); $width (negedge CE_, tSCE); $width (negedge LB_, tPBW); $width (negedge UB_, tPBW); `ifdef OEb $width (negedge WE_, tPWE1); `else $width (negedge WE_, tPWE2); `endif endspecify endmodule

data/full_repos/permissive/98795616/UNROMproj/UNROM_quartus/hc161_like.v

hc161_like.v

v

[]

[]

[]

[(1, 33)]

data/verilator_xmls/0c36900a-6795-415a-899b-8f3ff926a991.xml

module

module hc161_like ( input wire [3:0] cpu_d , input wire cpu_rw , input wire Ncpu_romsel , output wire hc161_out0 , output wire hc161_out1 , output wire hc161_out2 , output wire hc161_out3 ); reg [3:0] hc161_krn; assign hc161_out0 = hc161_krn [0:0]; assign hc161_out1 = hc161_krn [1:1]; assign hc161_out2 = hc161_krn [2:2]; assign hc161_out3 = hc161_krn [3:3]; always @(posedge Ncpu_romsel) begin if (!cpu_rw) begin hc161_krn <= cpu_d; end end endmodule

module hc161_like ( input wire [3:0] cpu_d , input wire cpu_rw , input wire Ncpu_romsel , output wire hc161_out0 , output wire hc161_out1 , output wire hc161_out2 , output wire hc161_out3 );

reg [3:0] hc161_krn; assign hc161_out0 = hc161_krn [0:0]; assign hc161_out1 = hc161_krn [1:1]; assign hc161_out2 = hc161_krn [2:2]; assign hc161_out3 = hc161_krn [3:3]; always @(posedge Ncpu_romsel) begin if (!cpu_rw) begin hc161_krn <= cpu_d; end end endmodule

data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02 Instances.v

02 Instances.v

v

[]

[]

[]

line:6: before: "-"

1: b'%Error: Cannot find file containing module: data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n ... Looked in:\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.sv\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.sv\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.v\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.sv\n%Error: Cannot find file containing module: Instances.v\n%Error: Exiting due to 2 error(s)\n'

module

module ripple-carry-counter(q, clk, reset); output [3:0] q; input clk, reset; T-FF tffO(q[O],clk,reset); T-FF tffl(q[l],g[0],reset); T-FF tff2(q[2],q[1], reset); T-FF tff3(q[3],q[2],reset); endmodule

module ripple-carry-counter(q, clk, reset);

output [3:0] q; input clk, reset; T-FF tffO(q[O],clk,reset); T-FF tffl(q[l],g[0],reset); T-FF tff2(q[2],q[1], reset); T-FF tff3(q[3],q[2],reset); endmodule

data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02 Instances.v

02 Instances.v

v

[]

[]

[]

line:6: before: "-"

1: b'%Error: Cannot find file containing module: data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n ... Looked in:\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.sv\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.sv\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.v\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/02.sv\n%Error: Cannot find file containing module: Instances.v\n%Error: Exiting due to 2 error(s)\n'

module

module T-FF(q, clk, reset); output q; input clk, reset; wire d; D-FF dff0(q,d, clk, reset); not nl(d, q); endmodule

module T-FF(q, clk, reset);

output q; input clk, reset; wire d; D-FF dff0(q,d, clk, reset); not nl(d, q); endmodule

data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03 Eg Ripple Counter.v

03 Eg Ripple Counter.v

v

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[]

line:1: before: "let"

1: b'%Error: Cannot find file containing module: data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n ... Looked in:\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n%Error: Cannot find file containing module: Eg\n%Error: Cannot find file containing module: Ripple\n%Error: Cannot find file containing module: Counter.v\n%Error: Exiting due to 4 error(s)\n'

module

module ripple-carry-counter(q, clk, reset); output [3:01 q; input clk, reset; T-FF tffO(q[O],clk,reset); T-FF tff1(q[1],q[O],reset); T-FF tff2(q[2],q[1],reset); T-FF tff3(q[3l,q[2],reset); endmodule

module ripple-carry-counter(q, clk, reset);

output [3:01 q; input clk, reset; T-FF tffO(q[O],clk,reset); T-FF tff1(q[1],q[O],reset); T-FF tff2(q[2],q[1],reset); T-FF tff3(q[3l,q[2],reset); endmodule

data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03 Eg Ripple Counter.v

03 Eg Ripple Counter.v

v

[]

[]

[]

line:1: before: "let"

1: b'%Error: Cannot find file containing module: data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n ... Looked in:\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n%Error: Cannot find file containing module: Eg\n%Error: Cannot find file containing module: Ripple\n%Error: Cannot find file containing module: Counter.v\n%Error: Exiting due to 4 error(s)\n'

module

module T F F (T-flipflop) are used. Therefore, we must now define the internals of the module T-FF module T-FF (q, clk, reset); output q; input clk, reset; wire d; D-FF dff0(q,d, clk, reset); not n1(d,q); endmodule

module T F F (T-flipflop) are used. Therefore, we must now define the internals of the module T-FF module T-FF (q, clk, reset);

output q; input clk, reset; wire d; D-FF dff0(q,d, clk, reset); not n1(d,q); endmodule

data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03 Eg Ripple Counter.v

03 Eg Ripple Counter.v

v

[]

[]

[]

line:1: before: "let"

1: b'%Error: Cannot find file containing module: data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n ... Looked in:\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n%Error: Cannot find file containing module: Eg\n%Error: Cannot find file containing module: Ripple\n%Error: Cannot find file containing module: Counter.v\n%Error: Exiting due to 4 error(s)\n'

module

module D-FF. module D-FF(q, d, clk, reset); output q; input d, clk, reset; reg q; always @(posedge reset or negedge clk) if (reset) q = l'bO; else q=d; endmodule

module D-FF. module D-FF(q, d, clk, reset);

output q; input d, clk, reset; reg q; always @(posedge reset or negedge clk) if (reset) q = l'bO; else q=d; endmodule

data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03 Eg Ripple Counter.v

03 Eg Ripple Counter.v

v

[]

[]

[]

line:1: before: "let"

1: b'%Error: Cannot find file containing module: data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n ... Looked in:\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling,data/full_repos/permissive/98800189/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.v\n obj_dir/data/full_repos/permissive/98800189/Verilog/HierarchialModelling/03.sv\n%Error: Cannot find file containing module: Eg\n%Error: Cannot find file containing module: Ripple\n%Error: Cannot find file containing module: Counter.v\n%Error: Exiting due to 4 error(s)\n'

module

module stimulus; reg clk; reg reset; wire[3:01 q; ripple-carry-counter r1(q, clk, reset); initial clk = l'bO; always #5 clk = ~clk; initial begin reset = 1'bl; #15 reset = 1'bO; #180 reset = 1'b1; #10 reset = 1'bO; #20 $finish; end $monitor($time, " Output q = %d", q); endmodule

module stimulus;

reg clk; reg reset; wire[3:01 q; ripple-carry-counter r1(q, clk, reset); initial clk = l'bO; always #5 clk = ~clk; initial begin reset = 1'bl; #15 reset = 1'bO; #180 reset = 1'b1; #10 reset = 1'bO; #20 $finish; end $monitor($time, " Output q = %d", q); endmodule

data/full_repos/permissive/98817686/ff.v

ff.v

v

[]

[]

[]

[(1, 8), (9, 14)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/ff.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dff\'\nmodule dff(output q,input d,clk);\n ^~~\n : ... Top module \'dffnew\'\nmodule dffnew(q,d,clk);\n ^~~~~~\n%Error: data/full_repos/permissive/98817686/ff.v:2: Duplicate declaration of signal: \'d\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/ff.v:1: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/ff.v:2: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/ff.v:1: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/ff.v:3: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/ff.v:1: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'

module

module dff(output q,input d,clk); wire d,clk; reg q; initial q<=0; always@(negedge clk) q<=d; endmodule

module dff(output q,input d,clk);

wire d,clk; reg q; initial q<=0; always@(negedge clk) q<=d; endmodule

data/full_repos/permissive/98817686/ff.v

ff.v

v

[]

[]

[]

[(1, 8), (9, 14)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/ff.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dff\'\nmodule dff(output q,input d,clk);\n ^~~\n : ... Top module \'dffnew\'\nmodule dffnew(q,d,clk);\n ^~~~~~\n%Error: data/full_repos/permissive/98817686/ff.v:2: Duplicate declaration of signal: \'d\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/ff.v:1: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/ff.v:2: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/ff.v:1: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/ff.v:3: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/ff.v:1: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'

module

module dffnew(q,d,clk); input d, clk; output reg q; always @(posedge clk) q <= d; endmodule

module dffnew(q,d,clk);

input d, clk; output reg q; always @(posedge clk) q <= d; endmodule

data/full_repos/permissive/98817686/ff_tb.v

ff_tb.v

v

[]

[]

[]

line:19: before: "$"

1: b'%Error: data/full_repos/permissive/98817686/ff_tb.v:7: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ff.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98817686/ff_tb.v:8: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98817686/ff_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #5 d<=~d;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98817686/ff_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n always #4 clk<=~clk;\n ^\n%Error: data/full_repos/permissive/98817686/ff_tb.v:16: Unsupported or unknown PLI call: $monitor\n $monitor("%d,\\t%b,\\t%b",$time,d,q); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98817686/ff_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'

module

module testbench; reg clk,d; wire q; dffnew d1 (q,d,clk); initial begin $dumpfile("ff.vcd"); $dumpvars; clk=0; d=0; end always #5 d<=~d; always #4 clk<=~clk; initial begin $display("time,\td,\tq"); $monitor("%d,\t%b,\t%b",$time,d,q); end initial #100 $finish; endmodule

module testbench;

reg clk,d; wire q; dffnew d1 (q,d,clk); initial begin $dumpfile("ff.vcd"); $dumpvars; clk=0; d=0; end always #5 d<=~d; always #4 clk<=~clk; initial begin $display("time,\td,\tq"); $monitor("%d,\t%b,\t%b",$time,d,q); end initial #100 $finish; endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module mux2to1(output z,input s,input x,y); wire s_,o1,o2; reg z; always @ (s or x or y)begin z<=(s)?x:y; end endmodule

module mux2to1(output z,input s,input x,y);

wire s_,o1,o2; reg z; always @ (s or x or y)begin z<=(s)?x:y; end endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module dff(output q,input d,clk); wire d,clk; reg q; initial begin q<=0; end always@(posedge clk) if(d==1'b0 || d==1'b1)begin q<=d; end else begin q<=0; end endmodule

module dff(output q,input d,clk);

wire d,clk; reg q; initial begin q<=0; end always@(posedge clk) if(d==1'b0 || d==1'b1)begin q<=d; end else begin q<=0; end endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module layer1(output o1,o2,o3,o4,o5,o6,o7,o8, input an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); mux2to1 m1(o1,an_1,an,en); mux2to1 m2(o2,bn_1,an,en); mux2to1 m3(o3,cn_1,bn,fn); mux2to1 m4(o4,dn_1,bn,fn); mux2to1 m5(o5,en_1,cn,gn); mux2to1 m6(o6,fn_1,cn,gn); mux2to1 m7(o7,gn_1,dn,hn); mux2to1 m8(o8,hn_1,dn,hn); endmodule

module layer1(output o1,o2,o3,o4,o5,o6,o7,o8, input an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1);

mux2to1 m1(o1,an_1,an,en); mux2to1 m2(o2,bn_1,an,en); mux2to1 m3(o3,cn_1,bn,fn); mux2to1 m4(o4,dn_1,bn,fn); mux2to1 m5(o5,en_1,cn,gn); mux2to1 m6(o6,fn_1,cn,gn); mux2to1 m7(o7,gn_1,dn,hn); mux2to1 m8(o8,hn_1,dn,hn); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module layer2(output t1,t2,t3,t4, input a_4, o1,o2,o3,o4,o5,o6,o7,o8); mux2to1 m1(t1,a_4,o1,o2); mux2to1 m2(t2,a_4,o3,o4); mux2to1 m3(t3,a_4,o5,o6); mux2to1 m4(t4,a_4,o7,o8); endmodule

module layer2(output t1,t2,t3,t4, input a_4, o1,o2,o3,o4,o5,o6,o7,o8);

mux2to1 m1(t1,a_4,o1,o2); mux2to1 m2(t2,a_4,o3,o4); mux2to1 m3(t3,a_4,o5,o6); mux2to1 m4(t4,a_4,o7,o8); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module layer3(output u1,u2, input a_3, t1,t2,t3,t4); mux2to1 m1(u1,a_3,t1,t2); mux2to1 m2(u2,a_3,t3,t4); endmodule

module layer3(output u1,u2, input a_3, t1,t2,t3,t4);

mux2to1 m1(u1,a_3,t1,t2); mux2to1 m2(u2,a_3,t3,t4); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module layer4(output v, input a_2, u1,u2); mux2to1 m1(v,a_2,u1,u2); endmodule

module layer4(output v, input a_2, u1,u2);

mux2to1 m1(v,a_2,u1,u2); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, input clk, an,bn,cn,dn,en,fn,gn,hn); reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1; wire clk,an,bn,cn,dn,en,fn,gn,hn; always@(posedge clk)begin an_1<=an; bn_1<=bn; cn_1<=cn; dn_1<=dn; en_1<=en; fn_1<=fn; gn_1<=gn; hn_1<=hn; end endmodule

module previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, input clk, an,bn,cn,dn,en,fn,gn,hn);

reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1; wire clk,an,bn,cn,dn,en,fn,gn,hn; always@(posedge clk)begin an_1<=an; bn_1<=bn; cn_1<=cn; dn_1<=dn; en_1<=en; fn_1<=fn; gn_1<=gn; hn_1<=hn; end endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module regvals(output An_4,An_3,An_2, input An,clk); wire An_1; dff d1(An_1,An,clk); dff d2(An_2,An_1,clk); dff d3(An_3,An_2,clk); dff d4(An_4,An_3,clk); endmodule

module regvals(output An_4,An_3,An_2, input An,clk);

wire An_1; dff d1(An_1,An,clk); dff d2(An_2,An_1,clk); dff d3(An_3,An_2,clk); dff d4(An_4,An_3,clk); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module hardware(inout An_2, input clk, an,bn,cn,dn,en,fn,gn,hn); wire o1,o2,o3,o4,o5,o6,o7,o8, t1,t2,t3,t4, u1,u2; inout An,An_3,An_4, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1; previnputs pvi(an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, clk, an,bn,cn,dn,en,fn,gn,hn); regvals rv(An_4,An_3,An_2, An,clk); layer1 l1(o1,o2,o3,o4,o5,o6,o7,o8, an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); layer2 l2(t1,t2,t3,t4, An_4, o1,o2,o3,o4,o5,o6,o7,o8); layer3 l3(u1,u2, An_3, t1,t2,t3,t4); layer4 l4(An,An_2,u1,u2); endmodule

module hardware(inout An_2, input clk, an,bn,cn,dn,en,fn,gn,hn);

wire o1,o2,o3,o4,o5,o6,o7,o8, t1,t2,t3,t4, u1,u2; inout An,An_3,An_4, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1; previnputs pvi(an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, clk, an,bn,cn,dn,en,fn,gn,hn); regvals rv(An_4,An_3,An_2, An,clk); layer1 l1(o1,o2,o3,o4,o5,o6,o7,o8, an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); layer2 l2(t1,t2,t3,t4, An_4, o1,o2,o3,o4,o5,o6,o7,o8); layer3 l3(u1,u2, An_3, t1,t2,t3,t4); layer4 l4(An,An_2,u1,u2); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module hardware2(output v,input [3:0]A, input an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, an,bn,cn,dn,en,fn,gn,hn); wire o1,o2,o3,o4,o5,o6,o7,o8, t1,t2,t3,t4, u1,u2, v; layer1 l1(o1,o2,o3,o4,o5,o6,o7,o8, an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); layer2 l2(t1,t2,t3,t4, A[3], o1,o2,o3,o4,o5,o6,o7,o8); layer3 l3(u1,u2, A[2], t1,t2,t3,t4); layer4 l4(v,A[0],u1,u2); endmodule

module hardware2(output v,input [3:0]A, input an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, an,bn,cn,dn,en,fn,gn,hn);

wire o1,o2,o3,o4,o5,o6,o7,o8, t1,t2,t3,t4, u1,u2, v; layer1 l1(o1,o2,o3,o4,o5,o6,o7,o8, an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); layer2 l2(t1,t2,t3,t4, A[3], o1,o2,o3,o4,o5,o6,o7,o8); layer3 l3(u1,u2, A[2], t1,t2,t3,t4); layer4 l4(v,A[0],u1,u2); endmodule

data/full_repos/permissive/98817686/hardware.v

hardware.v

v

[]

[]

[]

[(2, 8), (11, 27), (32, 43), (47, 54), (59, 64), (68, 72), (76, 102), (107, 114), (116, 145), (146, 166), (167, 172)]

1: b'%Warning-MULTITOP: data/full_repos/permissive/98817686/hardware.v:146: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hardware\'\nmodule hardware(inout An_2,\n ^~~~~~~~\n : ... Top module \'hardware2\'\nmodule hardware2(output v,input [3:0]A, input\n ^~~~~~~~~\n : ... Top module \'regvals2\'\nmodule regvals2 (output [3:0]A,input v,clk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'an_1\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'bn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'cn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'dn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'en_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'fn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'gn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:79: Duplicate declaration of signal: \'hn_1\'\n reg an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n data/full_repos/permissive/98817686/hardware.v:76: ... Location of original declaration\nmodule previnputs(output an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'clk\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:77: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'an\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'bn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'cn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'dn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'en\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'fn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'gn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:80: Duplicate declaration of signal: \'hn\'\n wire clk,an,bn,cn,dn,en,fn,gn,hn;\n ^~\n data/full_repos/permissive/98817686/hardware.v:78: ... Location of original declaration\n an,bn,cn,dn,en,fn,gn,hn);\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'d\'\n wire d,clk;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:12: Duplicate declaration of signal: \'clk\'\n wire d,clk;\n ^~~\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^~~\n%Error: data/full_repos/permissive/98817686/hardware.v:13: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/98817686/hardware.v:11: ... Location of original declaration\nmodule dff(output q,input d,clk);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:4: Duplicate declaration of signal: \'z\'\n reg z;\n ^\n data/full_repos/permissive/98817686/hardware.v:2: ... Location of original declaration\nmodule mux2to1(output z,input s,input x,y);\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:152: Duplicate declaration of signal: \'v\'\n v;\n ^\n data/full_repos/permissive/98817686/hardware.v:146: ... Location of original declaration\nmodule hardware2(output v,input [3:0]A, input\n ^\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An\'\n inout An,An_3,An_4,\n ^~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_3\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:123: Input/output/inout does not appear in port list: \'An_4\'\n inout An,An_3,An_4,\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'an_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'bn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'cn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'dn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'en_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'fn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'gn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: data/full_repos/permissive/98817686/hardware.v:124: Input/output/inout does not appear in port list: \'hn_1\'\n an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1;\n ^~~~\n%Error: Exiting due to 33 error(s), 1 warning(s)\n'

module

module regvals2 (output [3:0]A,input v,clk); dff d1(A[3],A[2],clk); dff d2(A[2],A[1],clk); dff d3(A[1],A[0],clk); dff d4(A[0],v,clk); endmodule

module regvals2 (output [3:0]A,input v,clk);

dff d1(A[3],A[2],clk); dff d2(A[2],A[1],clk); dff d3(A[1],A[0],clk); dff d4(A[0],v,clk); endmodule

data/full_repos/permissive/98817686/hardware_tb.v

hardware_tb.v

v

[]

[]

[]

line:84: before: "$"

1: b'%Error: data/full_repos/permissive/98817686/hardware_tb.v:57: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("hardware.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98817686/hardware_tb.v:58: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #4 clk<=!clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n always #5 an<=!an;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n always #10 bn<=!bn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n always #20 cn<=!cn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n always #40 dn<=!dn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n always #80 en<=!en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n always #160 fn<=!fn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n always #320 gn<=!gn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n always #640 hn<=!hn;\n ^\n%Error: data/full_repos/permissive/98817686/hardware_tb.v:78: Unsupported or unknown PLI call: $monitor\n $monitor("%d\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b : \\tb",$time,\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hardware_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #1300 $finish;\n ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'

module

module testbench; reg clk,an,bn,cn,dn,en,fn,gn,hn; wire a_1,a_2,a_3,a_4; wire an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,v; dff d2(a_1,v,clk); dff d3(a_2,a_1,clk); dff d4(a_3,a_2,clk); dff d5(a_4,a_3,clk); previnputs pi(an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, clk, an,bn,cn,dn,en,fn,gn,hn); initial begin $dumpfile("hardware.vcd"); $dumpvars; clk=0; an=0;bn=0;cn=0;dn=0;en=0;fn=0;gn=0;hn=0; end always #4 clk<=!clk; always #5 an<=!an; always #10 bn<=!bn; always #20 cn<=!cn; always #40 dn<=!dn; always #80 en<=!en; always #160 fn<=!fn; always #320 gn<=!gn; always #640 hn<=!hn; initial begin $display("time\tan\tbn\tcn\tdn\ten\tfn\tgn\thn : \tv\n"); $monitor("%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b : \tb",$time, an,bn,cn,dn,en,fn,gn,hn,v); end initial #1300 $finish; endmodule

module testbench;

reg clk,an,bn,cn,dn,en,fn,gn,hn; wire a_1,a_2,a_3,a_4; wire an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,v; dff d2(a_1,v,clk); dff d3(a_2,a_1,clk); dff d4(a_3,a_2,clk); dff d5(a_4,a_3,clk); previnputs pi(an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, clk, an,bn,cn,dn,en,fn,gn,hn); initial begin $dumpfile("hardware.vcd"); $dumpvars; clk=0; an=0;bn=0;cn=0;dn=0;en=0;fn=0;gn=0;hn=0; end always #4 clk<=!clk; always #5 an<=!an; always #10 bn<=!bn; always #20 cn<=!cn; always #40 dn<=!dn; always #80 en<=!en; always #160 fn<=!fn; always #320 gn<=!gn; always #640 hn<=!hn; initial begin $display("time\tan\tbn\tcn\tdn\ten\tfn\tgn\thn : \tv\n"); $monitor("%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b : \tb",$time, an,bn,cn,dn,en,fn,gn,hn,v); end initial #1300 $finish; endmodule

data/full_repos/permissive/98817686/hrd_main_tb.v

hrd_main_tb.v

v

[]

[]

[]

line:84: before: "$"

1: b'%Error: data/full_repos/permissive/98817686/hrd_main_tb.v:57: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("hardware.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98817686/hrd_main_tb.v:58: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #2 clk<=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n always #4 an<=~an;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n always #8 bn<=~bn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n always #16 cn<=~cn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n always #32 dn<=~dn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n always #64 en<=~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n always #128 fn<=~fn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n always #256 gn<=~gn;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n always #512 hn<=~hn;\n ^\n%Error: data/full_repos/permissive/98817686/hrd_main_tb.v:78: Unsupported or unknown PLI call: $monitor\n $monitor("%d\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b : \\tb",$time,\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98817686/hrd_main_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #1300 $finish;\n ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'

module

module testbench; reg clk,an,bn,cn,dn,en,fn,gn,hn; wire a_1,a_2,a_3,a_4; wire an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,v; dff d2(a_1,v,clk); dff d3(a_2,a_1,clk); dff d4(a_3,a_2,clk); dff d5(a_4,a_3,clk); previnputs pi(an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, clk, an,bn,cn,dn,en,fn,gn,hn); wire o1,o2,o3,o4,o5,o6,o7,o8; layer1 l1(o1,o2,o3,o4,o5,o6,o7,o8, an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); wire t1,t2,t3,t4; layer2 l2(t1,t2,t3,t4, a_4, o1,o2,o3,o4,o5,o6,o7,o8); wire u1,u2; layer3 l3(u1,u2, a_3, t1,t2,t3,t4); layer4 l4(v,a_2,u1,u2); initial begin $dumpfile("hardware.vcd"); $dumpvars; clk=0; an=0;bn=0;cn=0;dn=0;en=0;fn=0;gn=0;hn=0; end always #2 clk<=~clk; always #4 an<=~an; always #8 bn<=~bn; always #16 cn<=~cn; always #32 dn<=~dn; always #64 en<=~en; always #128 fn<=~fn; always #256 gn<=~gn; always #512 hn<=~hn; initial begin $display("time\tan\tbn\tcn\tdn\ten\tfn\tgn\thn : \tv\n"); $monitor("%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b : \tb",$time, an,bn,cn,dn,en,fn,gn,hn,v); end initial #1300 $finish; endmodule

module testbench;

reg clk,an,bn,cn,dn,en,fn,gn,hn; wire a_1,a_2,a_3,a_4; wire an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1,v; dff d2(a_1,v,clk); dff d3(a_2,a_1,clk); dff d4(a_3,a_2,clk); dff d5(a_4,a_3,clk); previnputs pi(an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1, clk, an,bn,cn,dn,en,fn,gn,hn); wire o1,o2,o3,o4,o5,o6,o7,o8; layer1 l1(o1,o2,o3,o4,o5,o6,o7,o8, an,bn,cn,dn,en,fn,gn,hn, an_1,bn_1,cn_1,dn_1,en_1,fn_1,gn_1,hn_1); wire t1,t2,t3,t4; layer2 l2(t1,t2,t3,t4, a_4, o1,o2,o3,o4,o5,o6,o7,o8); wire u1,u2; layer3 l3(u1,u2, a_3, t1,t2,t3,t4); layer4 l4(v,a_2,u1,u2); initial begin $dumpfile("hardware.vcd"); $dumpvars; clk=0; an=0;bn=0;cn=0;dn=0;en=0;fn=0;gn=0;hn=0; end always #2 clk<=~clk; always #4 an<=~an; always #8 bn<=~bn; always #16 cn<=~cn; always #32 dn<=~dn; always #64 en<=~en; always #128 fn<=~fn; always #256 gn<=~gn; always #512 hn<=~hn; initial begin $display("time\tan\tbn\tcn\tdn\ten\tfn\tgn\thn : \tv\n"); $monitor("%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b : \tb",$time, an,bn,cn,dn,en,fn,gn,hn,v); end initial #1300 $finish; endmodule

data/full_repos/permissive/98817686/mux.v

mux.v

v

[]

[]

[]

[(1, 7)]

data/verilator_xmls/28178a13-8eeb-44a7-9f84-80d28b81047e.xml

module

module mux2to1(output z,input s,input x0,x1); wire s_,o1,o2; not(s_,s); and(o1,s_,x0); and(o2,s,x1); or(z,o1,o2); endmodule

module mux2to1(output z,input s,input x0,x1);

wire s_,o1,o2; not(s_,s); and(o1,s_,x0); and(o2,s,x1); or(z,o1,o2); endmodule

data/full_repos/permissive/98884710/MBScore_alu.v

MBScore_alu.v

v

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[(79, 115)]

1: b'%Error: data/full_repos/permissive/98884710/MBScore_alu.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:4: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] alu_in_a,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:5: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] alu_in_b,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:6: Define or directive not defined: \'`ALU_OP_WIDTH\'\n input [`ALU_OP_WIDTH-1:0] alu_op_type,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:7: Define or directive not defined: \'`DATA_WIDTH\'\n output reg [`DATA_WIDTH-1:0] alu_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:17: Define or directive not defined: \'`ALU_OP_ADD\'\n `ALU_OP_ADD: {cf,alu_out} = {1\'b0 + alu_in_a} + {1\'b0 + alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:17: syntax error, unexpected \':\', expecting endcase\n `ALU_OP_ADD: {cf,alu_out} = {1\'b0 + alu_in_a} + {1\'b0 + alu_in_b};\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:18: Define or directive not defined: \'`ALU_OP_ADDU\'\n `ALU_OP_ADDU: {cf,alu_out} = {1\'b0,alu_in_a + alu_in_b};\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:19: Define or directive not defined: \'`ALU_OP_SUB\'\n `ALU_OP_SUB: {cf,alu_out} = {1\'b0 + alu_in_a} - {1\'b0 + alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:20: Define or directive not defined: \'`ALU_OP_SUBU\'\n `ALU_OP_SUBU: {cf,alu_out} = {1\'b0,alu_in_a - alu_in_b};\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:21: Define or directive not defined: \'`ALU_OP_AND\'\n `ALU_OP_AND: {cf,alu_out} = {1\'b0,alu_in_a & alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:22: Define or directive not defined: \'`ALU_OP_OR\'\n `ALU_OP_OR: {cf,alu_out} = {1\'b0,alu_in_a | alu_in_b};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:23: Define or directive not defined: \'`ALU_OP_XOR\'\n `ALU_OP_XOR: {cf,alu_out} = {1\'b0,alu_in_a ^ alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:24: Define or directive not defined: \'`ALU_OP_NOR\'\n `ALU_OP_NOR: {cf,alu_out} = {1\'b0,~(alu_in_a | alu_in_b)};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:25: Define or directive not defined: \'`ALU_OP_SLL\'\n `ALU_OP_SLL: {cf,alu_out} = {1\'b0,alu_in_a << alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:26: Define or directive not defined: \'`ALU_OP_SRL\'\n `ALU_OP_SRL: {cf,alu_out} = {1\'b0,alu_in_a >> alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:27: Define or directive not defined: \'`ALU_OP_SRA\'\n `ALU_OP_SRA: {cf,alu_out} = {1\'b0,$signed(alu_in_a) >>> alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:28: Define or directive not defined: \'`ALU_OP_EQ\'\n `ALU_OP_EQ: {cf,alu_out} = {1\'b0,(alu_in_a == alu_in_b) ? 32\'d1 : 32\'d0};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:29: Define or directive not defined: \'`ALU_OP_NE\'\n `ALU_OP_NE: {cf,alu_out} = {1\'b0,(alu_in_a != alu_in_b) ? 32\'d1 : 32\'d0};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:30: Define or directive not defined: \'`ALU_OP_LT\'\n `ALU_OP_LT: {cf,alu_out} = {1\'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32\'d1 : 32\'d0}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu.v:31: Define or directive not defined: \'`ALU_OP_LTU\'\n `ALU_OP_LTU: {cf,alu_out} = {1\'b0,( $unsigned(alu_in_a) < $unsigned(alu_in_b) ) ? 32\'d1 : 32\'d0}; \n ^~~~~~~~~~~\n%Error: Cannot continue\n'

module

module MBScore_alu( input rst, input [`DATA_WIDTH-1:0] alu_in_a, input [`DATA_WIDTH-1:0] alu_in_b, input [`ALU_OP_WIDTH-1:0] alu_op_type, output reg [`DATA_WIDTH-1:0] alu_out, output reg cf ); always @(alu_op_type or rst) begin if(rst) {cf,alu_out} = {1'b0,32'b0}; else case(alu_op_type) `ALU_OP_ADD: {cf,alu_out} = {1'b0 + alu_in_a} + {1'b0 + alu_in_b}; `ALU_OP_ADDU: {cf,alu_out} = {1'b0,alu_in_a + alu_in_b}; `ALU_OP_SUB: {cf,alu_out} = {1'b0 + alu_in_a} - {1'b0 + alu_in_b}; `ALU_OP_SUBU: {cf,alu_out} = {1'b0,alu_in_a - alu_in_b}; `ALU_OP_AND: {cf,alu_out} = {1'b0,alu_in_a & alu_in_b}; `ALU_OP_OR: {cf,alu_out} = {1'b0,alu_in_a | alu_in_b}; `ALU_OP_XOR: {cf,alu_out} = {1'b0,alu_in_a ^ alu_in_b}; `ALU_OP_NOR: {cf,alu_out} = {1'b0,~(alu_in_a | alu_in_b)}; `ALU_OP_SLL: {cf,alu_out} = {1'b0,alu_in_a << alu_in_b}; `ALU_OP_SRL: {cf,alu_out} = {1'b0,alu_in_a >> alu_in_b}; `ALU_OP_SRA: {cf,alu_out} = {1'b0,$signed(alu_in_a) >>> alu_in_b}; `ALU_OP_EQ: {cf,alu_out} = {1'b0,(alu_in_a == alu_in_b) ? 32'd1 : 32'd0}; `ALU_OP_NE: {cf,alu_out} = {1'b0,(alu_in_a != alu_in_b) ? 32'd1 : 32'd0}; `ALU_OP_LT: {cf,alu_out} = {1'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32'd1 : 32'd0}; `ALU_OP_LTU: {cf,alu_out} = {1'b0,( $unsigned(alu_in_a) < $unsigned(alu_in_b) ) ? 32'd1 : 32'd0}; default: {cf,alu_out} = {1'b0,32'b0}; endcase end endmodule

module MBScore_alu( input rst, input [`DATA_WIDTH-1:0] alu_in_a, input [`DATA_WIDTH-1:0] alu_in_b, input [`ALU_OP_WIDTH-1:0] alu_op_type, output reg [`DATA_WIDTH-1:0] alu_out, output reg cf );

always @(alu_op_type or rst) begin if(rst) {cf,alu_out} = {1'b0,32'b0}; else case(alu_op_type) `ALU_OP_ADD: {cf,alu_out} = {1'b0 + alu_in_a} + {1'b0 + alu_in_b}; `ALU_OP_ADDU: {cf,alu_out} = {1'b0,alu_in_a + alu_in_b}; `ALU_OP_SUB: {cf,alu_out} = {1'b0 + alu_in_a} - {1'b0 + alu_in_b}; `ALU_OP_SUBU: {cf,alu_out} = {1'b0,alu_in_a - alu_in_b}; `ALU_OP_AND: {cf,alu_out} = {1'b0,alu_in_a & alu_in_b}; `ALU_OP_OR: {cf,alu_out} = {1'b0,alu_in_a | alu_in_b}; `ALU_OP_XOR: {cf,alu_out} = {1'b0,alu_in_a ^ alu_in_b}; `ALU_OP_NOR: {cf,alu_out} = {1'b0,~(alu_in_a | alu_in_b)}; `ALU_OP_SLL: {cf,alu_out} = {1'b0,alu_in_a << alu_in_b}; `ALU_OP_SRL: {cf,alu_out} = {1'b0,alu_in_a >> alu_in_b}; `ALU_OP_SRA: {cf,alu_out} = {1'b0,$signed(alu_in_a) >>> alu_in_b}; `ALU_OP_EQ: {cf,alu_out} = {1'b0,(alu_in_a == alu_in_b) ? 32'd1 : 32'd0}; `ALU_OP_NE: {cf,alu_out} = {1'b0,(alu_in_a != alu_in_b) ? 32'd1 : 32'd0}; `ALU_OP_LT: {cf,alu_out} = {1'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32'd1 : 32'd0}; `ALU_OP_LTU: {cf,alu_out} = {1'b0,( $unsigned(alu_in_a) < $unsigned(alu_in_b) ) ? 32'd1 : 32'd0}; default: {cf,alu_out} = {1'b0,32'b0}; endcase end endmodule

data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v

MBScore_alu_operator_mux.v

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[(81, 94)]

1: b'%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:2: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:6: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n input [`ALU_SEL_WIDTH-1:0] alu_sel_a,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:7: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n input [`ALU_SEL_WIDTH-1:0] alu_sel_b,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:8: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] rs,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:9: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] rt,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] alu_in_a,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] alu_in_b\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:14: Define or directive not defined: \'`ALU_SEL_RS\'\n assign alu_in_a = (alu_sel_a == `ALU_SEL_RS)? rs : imm;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:14: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign alu_in_a = (alu_sel_a == `ALU_SEL_RS)? rs : imm;\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:15: Define or directive not defined: \'`ALU_SEL_RT\'\n assign alu_in_b = (alu_sel_b == `ALU_SEL_RT)? rt : imm;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_alu_operator_mux.v:15: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign alu_in_b = (alu_sel_b == `ALU_SEL_RT)? rt : imm;\n ^\n%Error: Exiting due to 11 error(s)\n'

module

module MBScore_alu_operator_mux( input [15:0] imm, input [`ALU_SEL_WIDTH-1:0] alu_sel_a, input [`ALU_SEL_WIDTH-1:0] alu_sel_b, input [`DATA_WIDTH-1:0] rs, input [`DATA_WIDTH-1:0] rt, output [`DATA_WIDTH-1:0] alu_in_a, output [`DATA_WIDTH-1:0] alu_in_b ); assign alu_in_a = (alu_sel_a == `ALU_SEL_RS)? rs : imm; assign alu_in_b = (alu_sel_b == `ALU_SEL_RT)? rt : imm; endmodule

module MBScore_alu_operator_mux( input [15:0] imm, input [`ALU_SEL_WIDTH-1:0] alu_sel_a, input [`ALU_SEL_WIDTH-1:0] alu_sel_b, input [`DATA_WIDTH-1:0] rs, input [`DATA_WIDTH-1:0] rt, output [`DATA_WIDTH-1:0] alu_in_a, output [`DATA_WIDTH-1:0] alu_in_b );

assign alu_in_a = (alu_sel_a == `ALU_SEL_RS)? rs : imm; assign alu_in_b = (alu_sel_b == `ALU_SEL_RT)? rt : imm; endmodule

data/full_repos/permissive/98884710/MBScore_ctrl.v

MBScore_ctrl.v

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line:282: before: ";"

1: b'%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:6: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] inst,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:9: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n output reg [`ALU_SEL_WIDTH-1:0] alu_sel_a,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:10: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n output reg [`ALU_SEL_WIDTH-1:0] alu_sel_b,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:11: Define or directive not defined: \'`ALU_OP_WIDTH\'\n output reg [`ALU_OP_WIDTH-1:0] alu_op_type,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:12: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n output [`REG_ADDR_WIDTH-1:0] rs_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:13: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n output [`REG_ADDR_WIDTH-1:0] rd_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:14: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n output [`REG_ADDR_WIDTH-1:0] rt_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:16: Define or directive not defined: \'`IMM_WIDTH\'\n output [`IMM_WIDTH-1:0] imm,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:17: Define or directive not defined: \'`WB_SEL_WIDTH\'\n output [`WB_SEL_WIDTH-1:0] WB_sel,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:28: Define or directive not defined: \'`OPCODE_JAL\'\n assign rt_addr = ( inst[31:26] == `OPCODE_JAL )? 5\'d31 : inst[20:16];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:28: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign rt_addr = ( inst[31:26] == `OPCODE_JAL )? 5\'d31 : inst[20:16];\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:36: Define or directive not defined: \'`IDLE\'\n curState <= `IDLE;\n ^~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n curState <= `IDLE;\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:47: Define or directive not defined: \'`IF\'\n nextState <= `IF;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:47: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n nextState <= `IF;\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:52: Define or directive not defined: \'`IDLE\'\n `IDLE: nextState = `IF;\n ^~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:52: syntax error, unexpected \':\', expecting endcase\n `IDLE: nextState = `IF;\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:52: Define or directive not defined: \'`IF\'\n `IDLE: nextState = `IF;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:53: Define or directive not defined: \'`IF\'\n `IF: nextState = `ID;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:53: Define or directive not defined: \'`ID\'\n `IF: nextState = `ID;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:54: Define or directive not defined: \'`ID\'\n `ID:\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:56: Define or directive not defined: \'`OPCODE_CALC\'\n if( (inst[31:26] == `OPCODE_CALC && inst[5:0] == `FUNCT_JR) ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:56: Define or directive not defined: \'`FUNCT_JR\'\n if( (inst[31:26] == `OPCODE_CALC && inst[5:0] == `FUNCT_JR) ||\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:57: Define or directive not defined: \'`OPCODE_J\'\n inst[31:26] == `OPCODE_J ||\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:58: Define or directive not defined: \'`OPCODE_JAL\'\n inst[31:26] == `OPCODE_JAL ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:59: Define or directive not defined: \'`OPCODE_HLT\'\n inst[31:26] == `OPCODE_HLT)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:60: Define or directive not defined: \'`IF\'\n nextState = `IF;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:62: Define or directive not defined: \'`OPCODE_LUI\'\n if(inst[31:26] == `OPCODE_LUI || inst[31:26] == `OPCODE_SPECIAL)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:62: Define or directive not defined: \'`OPCODE_SPECIAL\'\n if(inst[31:26] == `OPCODE_LUI || inst[31:26] == `OPCODE_SPECIAL)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:63: Define or directive not defined: \'`WB\'\n nextState = `WB;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:65: Define or directive not defined: \'`EXE\'\n nextState = `EXE;\n ^~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:68: Define or directive not defined: \'`EXE\'\n `EXE:\n ^~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:70: Define or directive not defined: \'`OPCODE_BEQ\'\n if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:70: Define or directive not defined: \'`OPCODE_BNE\'\n if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:71: Define or directive not defined: \'`IF\'\n nextState = `IF;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:73: Define or directive not defined: \'`WB\'\n nextState = `WB;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:75: Define or directive not defined: \'`WB\'\n `WB: nextState = `IF;\n ^~~\n%Warning-ENDLABEL: data/full_repos/permissive/98884710/MBScore_ctrl.v:75: End label \'nextState\' does not match begin label \'\'\n `WB: nextState = `IF;\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:75: syntax error, unexpected \'=\'\n `WB: nextState = `IF;\n ^\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:75: Define or directive not defined: \'`IF\'\n `WB: nextState = `IF;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:76: Define or directive not defined: \'`IF\'\n default: nextState = `IF;\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:86: Define or directive not defined: \'`IF\'\n `IF:\n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:91: Define or directive not defined: \'`ID\'\n `ID: \n ^~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:92: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:94: Define or directive not defined: \'`OPCODE_CALC\'\n `OPCODE_CALC:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:97: Define or directive not defined: \'`FUNCT_ADD\'\n `FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:97: Define or directive not defined: \'`FUNCT_ADDU\'\n `FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:97: Define or directive not defined: \'`FUNCT_SUB\'\n `FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_ctrl.v:97: Define or directive not defined: \'`FUNCT_SUBU\'\n `FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND,\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

module

module MBScore_ctrl( input clk, input rst, input [`DATA_WIDTH-1:0] inst, output reg pc_we, output reg IR_we, output reg [`ALU_SEL_WIDTH-1:0] alu_sel_a, output reg [`ALU_SEL_WIDTH-1:0] alu_sel_b, output reg [`ALU_OP_WIDTH-1:0] alu_op_type, output [`REG_ADDR_WIDTH-1:0] rs_addr, output [`REG_ADDR_WIDTH-1:0] rd_addr, output [`REG_ADDR_WIDTH-1:0] rt_addr, output reg_we, output [`IMM_WIDTH-1:0] imm, output [`WB_SEL_WIDTH-1:0] WB_sel, output reg JAL_or_J,BEQ_or_BNE,JR,hlt, output [3:0] state ); reg [3:0] curState,nextState; assign state = curState; assign rs_addr = inst[25:21]; assign rt_addr = ( inst[31:26] == `OPCODE_JAL )? 5'd31 : inst[20:16]; assign rd_addr = inst[16:12]; always @(posedge clk or posedge rst) begin if(rst) begin curState <= `IDLE; end else curState <= nextState; end always @(curState or inst) begin if(rst) begin nextState <= `IF; end else begin case(curState) `IDLE: nextState = `IF; `IF: nextState = `ID; `ID: begin if( (inst[31:26] == `OPCODE_CALC && inst[5:0] == `FUNCT_JR) || inst[31:26] == `OPCODE_J || inst[31:26] == `OPCODE_JAL || inst[31:26] == `OPCODE_HLT) nextState = `IF; else if(inst[31:26] == `OPCODE_LUI || inst[31:26] == `OPCODE_SPECIAL) nextState = `WB; else nextState = `EXE; end `EXE: begin if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE) nextState = `IF; else nextState = `WB; end `WB: nextState = `IF; default: nextState = `IF; endcase end end always @(curState) begin if(!rst) begin case(curState) `IF: begin pc_we = 1'b1; IR_we = 1'b1; end `ID: begin case(inst[31:26]) `OPCODE_CALC: begin case(inst[5:0]) `FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND, `FUNCT_OR,`FUNCT_XOR,`FUNCT_NOR,`FUNCT_SLT,`FUNCT_SLTU, `FUNCT_SLLV,`FUNCT_SRLV,`FUNCT_SRAV: begin alu_sel_a = `ALU_SEL_RS; alu_sel_b = `ALU_SEL_RT; end `FUNCT_SLL,`FUNCT_SRL,`FUNCT_SRA: begin alu_sel_a = `ALU_SEL_IMM; alu_sel_b = `ALU_SEL_RT; end `FUNCT_JR: begin JR = 1'b1; next = 1'b1; end default: ; endcase end `OPCODE_ADDI,`OPCODE_ADDIU,`OPCODE_ANDI,`OPCODE_ORI, `OPCODE_XORI,`OPCODE_SLTI,`OPCODE_SLTI: begin alu_sel_a = `ALU_SEL_RS; alu_sel_b = `ALU_SEL_IMM; end `OPCODE_BEQ,`OPCODE_BNE: begin alu_sel_a = `ALU_SEL_RS; alu_sel_b = `ALU_SEL_RT; end `OPCODE_HLT: begin hlt = 1'b1; next = 1'b1; end `OPCODE_J: begin JAL_or_J = 1'b1; next = 1'b1; end `OPCODE_JAL: begin reg_we = 1'b1; JAL_or_J = 1'b1; next = 1'b1; end default: ; endcase end `EXE: begin case(inst[31:26]) `OPCODE_CALC : begin case(inst[5:0]) `FUNCT_ADD : alu_op_type = `ALU_OP_ADD; `FUNCT_ADDU : alu_op_type = `ALU_OP_ADDU; `FUNCT_SUB : alu_op_type = `ALU_OP_SUB; `FUNCT_SUBU : alu_op_type = `ALU_OP_SUBU; `FUNCT_AND : alu_op_type = `ALU_OP_AND; `FUNCT_OR : alu_op_type = `ALU_OP_OR; `FUNCT_XOR : alu_op_type = `ALU_OP_XOR; `FUNCT_NOR : alu_op_type = `ALU_OP_NOR; `FUNCT_SLT : alu_op_type = `ALU_OP_LT; `FUNCT_SLTU : alu_op_type = `ALU_OP_LTU; `FUNCT_SLLV,`FUNCT_SLL : alu_op_type = `ALU_OP_SLL; `FUNCT_SRLV,`FUNCT_SRL : alu_op_type = `ALU_OP_SRL; `FUNCT_SRAV,`FUNCT_SRA : alu_op_type = `ALU_OP_SRA; default: ; endcase end `OPCODE_ADDI : alu_op_type = `ALU_OP_ADD; `OPCODE_ADDIU : alu_op_type = `ALU_OP_ADD; `OPCODE_ANDI : alu_op_type = `ALU_OP_AND; `OPCODE_ORI : alu_op_type = `ALU_OP_OR; `OPCODE_XORI : alu_op_type = `ALU_OP_XOR; `OPCODE_BEQ : alu_op_type = `ALU_OP_EQ; `OPCODE_BNE : alu_op_type = `ALU_OP_NE; `OPCODE_SLTI : alu_op_type = `ALU_OP_LT; `OPCODE_SLTIU : alu_op_type = `ALU_OP_LTU; default:; endcase end `WB: begin if(inst[31:26] == `OPCODE_LW) begin WB_sel = WB_SEL_MEMtoReg; reg_we = 1'b1; end else if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE) WB_sel = WB_SEL_ALUtoIR; else if(inst[31:26] == OPCODE_SW) WB_sel = WB_SEL_ALUtoMEM; else begin WB_sel = WB_SEL_ALUtoReg; reg_we = 1'b1; end next = 1'b1; end; default:; endcase end end endmodule

module MBScore_ctrl( input clk, input rst, input [`DATA_WIDTH-1:0] inst, output reg pc_we, output reg IR_we, output reg [`ALU_SEL_WIDTH-1:0] alu_sel_a, output reg [`ALU_SEL_WIDTH-1:0] alu_sel_b, output reg [`ALU_OP_WIDTH-1:0] alu_op_type, output [`REG_ADDR_WIDTH-1:0] rs_addr, output [`REG_ADDR_WIDTH-1:0] rd_addr, output [`REG_ADDR_WIDTH-1:0] rt_addr, output reg_we, output [`IMM_WIDTH-1:0] imm, output [`WB_SEL_WIDTH-1:0] WB_sel, output reg JAL_or_J,BEQ_or_BNE,JR,hlt, output [3:0] state );

reg [3:0] curState,nextState; assign state = curState; assign rs_addr = inst[25:21]; assign rt_addr = ( inst[31:26] == `OPCODE_JAL )? 5'd31 : inst[20:16]; assign rd_addr = inst[16:12]; always @(posedge clk or posedge rst) begin if(rst) begin curState <= `IDLE; end else curState <= nextState; end always @(curState or inst) begin if(rst) begin nextState <= `IF; end else begin case(curState) `IDLE: nextState = `IF; `IF: nextState = `ID; `ID: begin if( (inst[31:26] == `OPCODE_CALC && inst[5:0] == `FUNCT_JR) || inst[31:26] == `OPCODE_J || inst[31:26] == `OPCODE_JAL || inst[31:26] == `OPCODE_HLT) nextState = `IF; else if(inst[31:26] == `OPCODE_LUI || inst[31:26] == `OPCODE_SPECIAL) nextState = `WB; else nextState = `EXE; end `EXE: begin if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE) nextState = `IF; else nextState = `WB; end `WB: nextState = `IF; default: nextState = `IF; endcase end end always @(curState) begin if(!rst) begin case(curState) `IF: begin pc_we = 1'b1; IR_we = 1'b1; end `ID: begin case(inst[31:26]) `OPCODE_CALC: begin case(inst[5:0]) `FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND, `FUNCT_OR,`FUNCT_XOR,`FUNCT_NOR,`FUNCT_SLT,`FUNCT_SLTU, `FUNCT_SLLV,`FUNCT_SRLV,`FUNCT_SRAV: begin alu_sel_a = `ALU_SEL_RS; alu_sel_b = `ALU_SEL_RT; end `FUNCT_SLL,`FUNCT_SRL,`FUNCT_SRA: begin alu_sel_a = `ALU_SEL_IMM; alu_sel_b = `ALU_SEL_RT; end `FUNCT_JR: begin JR = 1'b1; next = 1'b1; end default: ; endcase end `OPCODE_ADDI,`OPCODE_ADDIU,`OPCODE_ANDI,`OPCODE_ORI, `OPCODE_XORI,`OPCODE_SLTI,`OPCODE_SLTI: begin alu_sel_a = `ALU_SEL_RS; alu_sel_b = `ALU_SEL_IMM; end `OPCODE_BEQ,`OPCODE_BNE: begin alu_sel_a = `ALU_SEL_RS; alu_sel_b = `ALU_SEL_RT; end `OPCODE_HLT: begin hlt = 1'b1; next = 1'b1; end `OPCODE_J: begin JAL_or_J = 1'b1; next = 1'b1; end `OPCODE_JAL: begin reg_we = 1'b1; JAL_or_J = 1'b1; next = 1'b1; end default: ; endcase end `EXE: begin case(inst[31:26]) `OPCODE_CALC : begin case(inst[5:0]) `FUNCT_ADD : alu_op_type = `ALU_OP_ADD; `FUNCT_ADDU : alu_op_type = `ALU_OP_ADDU; `FUNCT_SUB : alu_op_type = `ALU_OP_SUB; `FUNCT_SUBU : alu_op_type = `ALU_OP_SUBU; `FUNCT_AND : alu_op_type = `ALU_OP_AND; `FUNCT_OR : alu_op_type = `ALU_OP_OR; `FUNCT_XOR : alu_op_type = `ALU_OP_XOR; `FUNCT_NOR : alu_op_type = `ALU_OP_NOR; `FUNCT_SLT : alu_op_type = `ALU_OP_LT; `FUNCT_SLTU : alu_op_type = `ALU_OP_LTU; `FUNCT_SLLV,`FUNCT_SLL : alu_op_type = `ALU_OP_SLL; `FUNCT_SRLV,`FUNCT_SRL : alu_op_type = `ALU_OP_SRL; `FUNCT_SRAV,`FUNCT_SRA : alu_op_type = `ALU_OP_SRA; default: ; endcase end `OPCODE_ADDI : alu_op_type = `ALU_OP_ADD; `OPCODE_ADDIU : alu_op_type = `ALU_OP_ADD; `OPCODE_ANDI : alu_op_type = `ALU_OP_AND; `OPCODE_ORI : alu_op_type = `ALU_OP_OR; `OPCODE_XORI : alu_op_type = `ALU_OP_XOR; `OPCODE_BEQ : alu_op_type = `ALU_OP_EQ; `OPCODE_BNE : alu_op_type = `ALU_OP_NE; `OPCODE_SLTI : alu_op_type = `ALU_OP_LT; `OPCODE_SLTIU : alu_op_type = `ALU_OP_LTU; default:; endcase end `WB: begin if(inst[31:26] == `OPCODE_LW) begin WB_sel = WB_SEL_MEMtoReg; reg_we = 1'b1; end else if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE) WB_sel = WB_SEL_ALUtoIR; else if(inst[31:26] == OPCODE_SW) WB_sel = WB_SEL_ALUtoMEM; else begin WB_sel = WB_SEL_ALUtoReg; reg_we = 1'b1; end next = 1'b1; end; default:; endcase end end endmodule

data/full_repos/permissive/98884710/MBScore_IR.v

MBScore_IR.v

v

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1: b'%Error: data/full_repos/permissive/98884710/MBScore_IR.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] next_addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:12: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] inst_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] inst_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] pc_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:15: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:17: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] pc,inst;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_IR.v:18: syntax error, unexpected assign\n assign pc_out = pc;\n ^~~~~~\n%Error: Exiting due to 8 error(s)\n'

module

module MBScore_IR( input clk, input rst, input IR_we, input next, input JAL_or_J, input BEQ_or_BNE, input JR, input hlt, input [`DATA_WIDTH-1:0] next_addr, input [`DATA_WIDTH-1:0] inst_in, output [`DATA_WIDTH-1:0] inst_out, output [`DATA_WIDTH-1:0] pc_out, ); reg [`DATA_WIDTH-1:0] pc,inst; assign pc_out = pc; assign inst_out = inst; always @(posedge clk) begin if(rst) {pc,inst} = {32'b0,32'b0}; else begin if(IR_we) inst = inst_in; end end always @(posedge next) begin if(hlt) pc = pc; else if(JAL_or_J) pc = {(pc + 4)[31:28],inst[25:0],0,0}; else if(BEQ_or_BNE) pc = pc + 4 + $signed(inst[15:0]) << 2; else if(JR) pc = next_addr; else pc = pc + 4; end endmodule

module MBScore_IR( input clk, input rst, input IR_we, input next, input JAL_or_J, input BEQ_or_BNE, input JR, input hlt, input [`DATA_WIDTH-1:0] next_addr, input [`DATA_WIDTH-1:0] inst_in, output [`DATA_WIDTH-1:0] inst_out, output [`DATA_WIDTH-1:0] pc_out, );

reg [`DATA_WIDTH-1:0] pc,inst; assign pc_out = pc; assign inst_out = inst; always @(posedge clk) begin if(rst) {pc,inst} = {32'b0,32'b0}; else begin if(IR_we) inst = inst_in; end end always @(posedge next) begin if(hlt) pc = pc; else if(JAL_or_J) pc = {(pc + 4)[31:28],inst[25:0],0,0}; else if(BEQ_or_BNE) pc = pc + 4 + $signed(inst[15:0]) << 2; else if(JR) pc = next_addr; else pc = pc + 4; end endmodule

data/full_repos/permissive/98884710/MBScore_pipeline.v

MBScore_pipeline.v

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[]

[(80, 100)]

1: b'%Error: data/full_repos/permissive/98884710/MBScore_pipeline.v:2: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/98884710/MBScore_pipeline.v:8: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] inst;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_pipeline.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] alu_sel_a,alu_sel_b,alu_out;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_pipeline.v:11: Define or directive not defined: \'`ALU_OP_WIDTH\'\n wire [`ALU_OP_WIDTH-1:0] alu_op_type;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_pipeline.v:17: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] WB_to_reg,WB_to_mem;\n ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'

module

module MBScore_pipeline( input clk, input rst ); wire [`DATA_WIDTH-1:0] inst; wire pc_we,IR_we; wire [`DATA_WIDTH-1:0] alu_sel_a,alu_sel_b,alu_out; wire [`ALU_OP_WIDTH-1:0] alu_op_type; wire [4:0] rs_addr,rd_addr,rt_addr; wire reg_we; wire [15:0] imm; wire [25:0] jump_addr; wire [1:0] WB_sel; wire [`DATA_WIDTH-1:0] WB_to_reg,WB_to_mem; wire jump; wire [3:0] state; endmodule

module MBScore_pipeline( input clk, input rst );

wire [`DATA_WIDTH-1:0] inst; wire pc_we,IR_we; wire [`DATA_WIDTH-1:0] alu_sel_a,alu_sel_b,alu_out; wire [`ALU_OP_WIDTH-1:0] alu_op_type; wire [4:0] rs_addr,rd_addr,rt_addr; wire reg_we; wire [15:0] imm; wire [25:0] jump_addr; wire [1:0] WB_sel; wire [`DATA_WIDTH-1:0] WB_to_reg,WB_to_mem; wire jump; wire [3:0] state; endmodule

data/full_repos/permissive/98884710/MBScore_WB_mux.v

MBScore_WB_mux.v

v

[]

[]

[]

[(84, 103)]

1: b'%Error: data/full_repos/permissive/98884710/MBScore_WB_mux.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.v\n data/full_repos/permissive/98884710,data/full_repos/permissive/98884710/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/98884710/MBScore_WB_mux.v:9: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] alu_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_WB_mux.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] mem_data_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_WB_mux.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n output reg [`DATA_WIDTH-1:0] WB_to_reg,WB_to_mem,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_WB_mux.v:21: Define or directive not defined: \'`WB_SEL_ALUtoIR\'\n : ... Suggested alternative: \'`WB_SEL_ALUtoMEM\'\n `WB_SEL_ALUtoIR : jump = alu_out[0];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98884710/MBScore_WB_mux.v:21: syntax error, unexpected \':\', expecting endcase\n `WB_SEL_ALUtoIR : jump = alu_out[0];\n ^\n%Error: Cannot continue\n'

module

module MBScore_WB_mux( input [1:0] WB_sel, input [`DATA_WIDTH-1:0] alu_out, input [`DATA_WIDTH-1:0] mem_data_in, output reg [`DATA_WIDTH-1:0] WB_to_reg,WB_to_mem, output reg jump ); always @(WB_sel) begin case(WB_sel) `WB_SEL_ALUtoReg: WB_to_reg = alu_out; `WB_SEL_ALUtoMEM: WB_to_mem = alu_out; `WB_SEL_MEMtoReg: WB_to_reg = mem_data_in; `WB_SEL_ALUtoIR : jump = alu_out[0]; default:; endcase end endmodule

module MBScore_WB_mux( input [1:0] WB_sel, input [`DATA_WIDTH-1:0] alu_out, input [`DATA_WIDTH-1:0] mem_data_in, output reg [`DATA_WIDTH-1:0] WB_to_reg,WB_to_mem, output reg jump );

always @(WB_sel) begin case(WB_sel) `WB_SEL_ALUtoReg: WB_to_reg = alu_out; `WB_SEL_ALUtoMEM: WB_to_mem = alu_out; `WB_SEL_MEMtoReg: WB_to_reg = mem_data_in; `WB_SEL_ALUtoIR : jump = alu_out[0]; default:; endcase end endmodule

data/full_repos/permissive/98916810/modules/wishbone/wb_afc_diag/spi2wb_dpram.v

spi2wb_dpram.v

v

[]

[]

[]

[(39, 192)]

1: b"%Error: data/full_repos/permissive/98916810/modules/wishbone/wb_afc_diag/spi2wb_dpram.v:67: Cannot find file containing module: 'BLK_MEM_GEN_V7_3'\n BLK_MEM_GEN_V7_3 #(\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/modules/wishbone/wb_afc_diag,data/full_repos/permissive/98916810/BLK_MEM_GEN_V7_3\n data/full_repos/permissive/98916810/modules/wishbone/wb_afc_diag,data/full_repos/permissive/98916810/BLK_MEM_GEN_V7_3.v\n data/full_repos/permissive/98916810/modules/wishbone/wb_afc_diag,data/full_repos/permissive/98916810/BLK_MEM_GEN_V7_3.sv\n BLK_MEM_GEN_V7_3\n BLK_MEM_GEN_V7_3.v\n BLK_MEM_GEN_V7_3.sv\n obj_dir/BLK_MEM_GEN_V7_3\n obj_dir/BLK_MEM_GEN_V7_3.v\n obj_dir/BLK_MEM_GEN_V7_3.sv\n%Error: Exiting due to 1 error(s)\n"

module

module spi2wb_dpram( clka, wea, addra, dina, douta, clkb, enb, web, addrb, dinb, doutb ); input clka; input [0 : 0] wea; input [7 : 0] addra; input [31 : 0] dina; output [31 : 0] douta; input clkb; input enb; input [0 : 0] web; input [7 : 0] addrb; input [31 : 0] dinb; output [31 : 0] doutb; BLK_MEM_GEN_V7_3 #( .C_ADDRA_WIDTH(8), .C_ADDRB_WIDTH(8), .C_ALGORITHM(1), .C_AXI_ID_WIDTH(4), .C_AXI_SLAVE_TYPE(0), .C_AXI_TYPE(1), .C_BYTE_SIZE(9), .C_COMMON_CLK(1), .C_DEFAULT_DATA("00000000"), .C_DISABLE_WARN_BHV_COLL(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_ENABLE_32BIT_ADDRESS(0), .C_FAMILY("artix7"), .C_HAS_AXI_ID(0), .C_HAS_ENA(0), .C_HAS_ENB(1), .C_HAS_INJECTERR(0), .C_HAS_MEM_OUTPUT_REGS_A(0), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_HAS_REGCEA(0), .C_HAS_REGCEB(0), .C_HAS_RSTA(0), .C_HAS_RSTB(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_INIT_FILE("BlankString"), .C_INIT_FILE_NAME("../rtl/spi2wb/spi2wb_dpram.mif"), .C_INITA_VAL("0"), .C_INITB_VAL("0"), .C_INTERFACE_TYPE(0), .C_LOAD_INIT_FILE(1), .C_MEM_TYPE(2), .C_MUX_PIPELINE_STAGES(0), .C_PRIM_TYPE(1), .C_READ_DEPTH_A(256), .C_READ_DEPTH_B(256), .C_READ_WIDTH_A(32), .C_READ_WIDTH_B(32), .C_RST_PRIORITY_A("CE"), .C_RST_PRIORITY_B("CE"), .C_RST_TYPE("SYNC"), .C_RSTRAM_A(0), .C_RSTRAM_B(0), .C_SIM_COLLISION_CHECK("ALL"), .C_USE_BRAM_BLOCK(0), .C_USE_BYTE_WEA(0), .C_USE_BYTE_WEB(0), .C_USE_DEFAULT_DATA(1), .C_USE_ECC(0), .C_USE_SOFTECC(0), .C_WEA_WIDTH(1), .C_WEB_WIDTH(1), .C_WRITE_DEPTH_A(256), .C_WRITE_DEPTH_B(256), .C_WRITE_MODE_A("READ_FIRST"), .C_WRITE_MODE_B("READ_FIRST"), .C_WRITE_WIDTH_A(32), .C_WRITE_WIDTH_B(32), .C_XDEVICEFAMILY("artix7") ) inst ( .CLKA(clka), .WEA(wea), .ADDRA(addra), .DINA(dina), .DOUTA(douta), .CLKB(clkb), .ENB(enb), .WEB(web), .ADDRB(addrb), .DINB(dinb), .DOUTB(doutb), .RSTA(), .ENA(), .REGCEA(), .RSTB(), .REGCEB(), .INJECTSBITERR(), .INJECTDBITERR(), .SBITERR(), .DBITERR(), .RDADDRECC(), .S_ACLK(), .S_ARESETN(), .S_AXI_AWID(), .S_AXI_AWADDR(), .S_AXI_AWLEN(), .S_AXI_AWSIZE(), .S_AXI_AWBURST(), .S_AXI_AWVALID(), .S_AXI_AWREADY(), .S_AXI_WDATA(), .S_AXI_WSTRB(), .S_AXI_WLAST(), .S_AXI_WVALID(), .S_AXI_WREADY(), .S_AXI_BID(), .S_AXI_BRESP(), .S_AXI_BVALID(), .S_AXI_BREADY(), .S_AXI_ARID(), .S_AXI_ARADDR(), .S_AXI_ARLEN(), .S_AXI_ARSIZE(), .S_AXI_ARBURST(), .S_AXI_ARVALID(), .S_AXI_ARREADY(), .S_AXI_RID(), .S_AXI_RDATA(), .S_AXI_RRESP(), .S_AXI_RLAST(), .S_AXI_RVALID(), .S_AXI_RREADY(), .S_AXI_INJECTSBITERR(), .S_AXI_INJECTDBITERR(), .S_AXI_SBITERR(), .S_AXI_DBITERR(), .S_AXI_RDADDRECC() ); endmodule

module spi2wb_dpram( clka, wea, addra, dina, douta, clkb, enb, web, addrb, dinb, doutb );

input clka; input [0 : 0] wea; input [7 : 0] addra; input [31 : 0] dina; output [31 : 0] douta; input clkb; input enb; input [0 : 0] web; input [7 : 0] addrb; input [31 : 0] dinb; output [31 : 0] doutb; BLK_MEM_GEN_V7_3 #( .C_ADDRA_WIDTH(8), .C_ADDRB_WIDTH(8), .C_ALGORITHM(1), .C_AXI_ID_WIDTH(4), .C_AXI_SLAVE_TYPE(0), .C_AXI_TYPE(1), .C_BYTE_SIZE(9), .C_COMMON_CLK(1), .C_DEFAULT_DATA("00000000"), .C_DISABLE_WARN_BHV_COLL(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_ENABLE_32BIT_ADDRESS(0), .C_FAMILY("artix7"), .C_HAS_AXI_ID(0), .C_HAS_ENA(0), .C_HAS_ENB(1), .C_HAS_INJECTERR(0), .C_HAS_MEM_OUTPUT_REGS_A(0), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_HAS_REGCEA(0), .C_HAS_REGCEB(0), .C_HAS_RSTA(0), .C_HAS_RSTB(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_INIT_FILE("BlankString"), .C_INIT_FILE_NAME("../rtl/spi2wb/spi2wb_dpram.mif"), .C_INITA_VAL("0"), .C_INITB_VAL("0"), .C_INTERFACE_TYPE(0), .C_LOAD_INIT_FILE(1), .C_MEM_TYPE(2), .C_MUX_PIPELINE_STAGES(0), .C_PRIM_TYPE(1), .C_READ_DEPTH_A(256), .C_READ_DEPTH_B(256), .C_READ_WIDTH_A(32), .C_READ_WIDTH_B(32), .C_RST_PRIORITY_A("CE"), .C_RST_PRIORITY_B("CE"), .C_RST_TYPE("SYNC"), .C_RSTRAM_A(0), .C_RSTRAM_B(0), .C_SIM_COLLISION_CHECK("ALL"), .C_USE_BRAM_BLOCK(0), .C_USE_BYTE_WEA(0), .C_USE_BYTE_WEB(0), .C_USE_DEFAULT_DATA(1), .C_USE_ECC(0), .C_USE_SOFTECC(0), .C_WEA_WIDTH(1), .C_WEB_WIDTH(1), .C_WRITE_DEPTH_A(256), .C_WRITE_DEPTH_B(256), .C_WRITE_MODE_A("READ_FIRST"), .C_WRITE_MODE_B("READ_FIRST"), .C_WRITE_WIDTH_A(32), .C_WRITE_WIDTH_B(32), .C_XDEVICEFAMILY("artix7") ) inst ( .CLKA(clka), .WEA(wea), .ADDRA(addra), .DINA(dina), .DOUTA(douta), .CLKB(clkb), .ENB(enb), .WEB(web), .ADDRB(addrb), .DINB(dinb), .DOUTB(doutb), .RSTA(), .ENA(), .REGCEA(), .RSTB(), .REGCEB(), .INJECTSBITERR(), .INJECTDBITERR(), .SBITERR(), .DBITERR(), .RDADDRECC(), .S_ACLK(), .S_ARESETN(), .S_AXI_AWID(), .S_AXI_AWADDR(), .S_AXI_AWLEN(), .S_AXI_AWSIZE(), .S_AXI_AWBURST(), .S_AXI_AWVALID(), .S_AXI_AWREADY(), .S_AXI_WDATA(), .S_AXI_WSTRB(), .S_AXI_WLAST(), .S_AXI_WVALID(), .S_AXI_WREADY(), .S_AXI_BID(), .S_AXI_BRESP(), .S_AXI_BVALID(), .S_AXI_BREADY(), .S_AXI_ARID(), .S_AXI_ARADDR(), .S_AXI_ARLEN(), .S_AXI_ARSIZE(), .S_AXI_ARBURST(), .S_AXI_ARVALID(), .S_AXI_ARREADY(), .S_AXI_RID(), .S_AXI_RDATA(), .S_AXI_RRESP(), .S_AXI_RLAST(), .S_AXI_RVALID(), .S_AXI_RREADY(), .S_AXI_INJECTSBITERR(), .S_AXI_INJECTDBITERR(), .S_AXI_SBITERR(), .S_AXI_DBITERR(), .S_AXI_RDADDRECC() ); endmodule

data/full_repos/permissive/98916810/modules/wishbone/wb_ethmac/eth_fifo.v

eth_fifo.v

v

[]

['general public license', 'free software foundation']

[]

[(348, 602)]

1: b'%Error: data/full_repos/permissive/98916810/modules/wishbone/wb_ethmac/eth_fifo.v:42: Cannot find include file: ethmac_defines.v\n`include "ethmac_defines.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/modules/wishbone/wb_ethmac,data/full_repos/permissive/98916810/ethmac_defines.v\n data/full_repos/permissive/98916810/modules/wishbone/wb_ethmac,data/full_repos/permissive/98916810/ethmac_defines.v.v\n data/full_repos/permissive/98916810/modules/wishbone/wb_ethmac,data/full_repos/permissive/98916810/ethmac_defines.v.sv\n ethmac_defines.v\n ethmac_defines.v.v\n ethmac_defines.v.sv\n obj_dir/ethmac_defines.v\n obj_dir/ethmac_defines.v.v\n obj_dir/ethmac_defines.v.sv\n%Error: data/full_repos/permissive/98916810/modules/wishbone/wb_ethmac/eth_fifo.v:43: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'

module

module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt); parameter DATA_WIDTH = 32; parameter DEPTH = 8; parameter CNT_WIDTH = 3; input clk; input reset; input write; input read; input clear; input [DATA_WIDTH-1:0] data_in; output [DATA_WIDTH-1:0] data_out; output almost_full; output full; output almost_empty; output empty; output [CNT_WIDTH-1:0] cnt; reg [CNT_WIDTH-1:0] read_pointer; reg [CNT_WIDTH-1:0] cnt; reg final_read; always @ (posedge clk or posedge reset) begin if(reset) cnt <= 0; else if(clear) cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; else if(read ^ write) if(read) cnt <= cnt - 1; else cnt <= cnt + 1; end `ifdef ETH_FIFO_GENERIC reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg; reg clear_reg; reg fallthrough_read; reg [CNT_WIDTH-1:0] fallthrough_read_addr; always @(posedge clk) if (reset) fallthrough_read <= 0; else fallthrough_read <= empty & write; always @(posedge clk) if (empty & write) fallthrough_read_addr <= waddr; always @(posedge clk) if (reset) waddr <= 0; else if (write) waddr <= waddr + 1; always @(posedge clk) if (reset) raddr <= 0; else if (clear) raddr <= waddr; else if (read | clear_reg) raddr <= raddr + 1; always @ (posedge clk) if (write & ~full) fifo[waddr] <= data_in; always @(posedge clk) clear_reg <= clear; always @ (posedge clk) if (read | clear_reg) raddr_reg <= raddr; else if (fallthrough_read) raddr_reg <= fallthrough_read_addr; assign data_out = fifo[raddr_reg]; always @(posedge clk) if (reset) final_read <= 0; else if (final_read & read & !write) final_read <= ~final_read; else if ((cnt == 1) & read & !write) final_read <= 1; assign empty = ~(|cnt); assign almost_empty = cnt==1; assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1); assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2); always @ (posedge clk or posedge reset) begin if(reset) read_pointer <= 0; else if(clear) read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1}; else if(read & ~empty) read_pointer <= read_pointer + 1'b1; end `else reg [CNT_WIDTH-1:0] write_pointer; always @ (posedge clk or posedge reset) begin if(reset) read_pointer <= 0; else if(clear) read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read}; else if(read & ~empty) read_pointer <= read_pointer + 1'b1; end always @ (posedge clk or posedge reset) begin if(reset) write_pointer <= 0; else if(clear) write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write}; else if(write & ~full) write_pointer <= write_pointer + 1'b1; end `ifdef ETH_FIFO_XILINX generate if (CNT_WIDTH==4) begin xilinx_dist_ram_16x32 fifo ( .data_out(data_out), .we(write & ~full), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); end else if (CNT_WIDTH==6) begin wire [DATA_WIDTH-1:0] data_out0; wire [DATA_WIDTH-1:0] data_out1; wire [DATA_WIDTH-1:0] data_out2; wire [DATA_WIDTH-1:0] data_out3; wire we_ram0,we_ram1,we_ram2,we_ram3; assign we_ram0 = (write_pointer[5:4]==2'b00); assign we_ram1 = (write_pointer[5:4]==2'b01); assign we_ram2 = (write_pointer[5:4]==2'b10); assign we_ram3 = (write_pointer[5:4]==2'b11); assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 : (read_pointer[5:4]==2'b10) ? data_out2 : (read_pointer[5:4]==2'b01) ? data_out1 : data_out0; xilinx_dist_ram_16x32 fifo0 ( .data_out(data_out0), .we(write & ~full & we_ram0), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); xilinx_dist_ram_16x32 fifo1 ( .data_out(data_out1), .we(write & ~full & we_ram1), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); xilinx_dist_ram_16x32 fifo2 ( .data_out(data_out2), .we(write & ~full & we_ram2), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); xilinx_dist_ram_16x32 fifo3 ( .data_out(data_out3), .we(write & ~full & we_ram3), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); end endgenerate `else `ifdef ETH_ALTERA_ALTSYNCRAM altera_dpram_16x32 altera_dpram_16x32_inst ( .data (data_in), .wren (write & ~full), .wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), .rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), .clock (clk), .q (data_out) ); `endif `endif assign empty = ~(|cnt); assign almost_empty = cnt == 1; assign full = cnt == (DEPTH-1); assign almost_full = &cnt[CNT_WIDTH-1:0]; `endif endmodule

module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);

parameter DATA_WIDTH = 32; parameter DEPTH = 8; parameter CNT_WIDTH = 3; input clk; input reset; input write; input read; input clear; input [DATA_WIDTH-1:0] data_in; output [DATA_WIDTH-1:0] data_out; output almost_full; output full; output almost_empty; output empty; output [CNT_WIDTH-1:0] cnt; reg [CNT_WIDTH-1:0] read_pointer; reg [CNT_WIDTH-1:0] cnt; reg final_read; always @ (posedge clk or posedge reset) begin if(reset) cnt <= 0; else if(clear) cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; else if(read ^ write) if(read) cnt <= cnt - 1; else cnt <= cnt + 1; end `ifdef ETH_FIFO_GENERIC reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg; reg clear_reg; reg fallthrough_read; reg [CNT_WIDTH-1:0] fallthrough_read_addr; always @(posedge clk) if (reset) fallthrough_read <= 0; else fallthrough_read <= empty & write; always @(posedge clk) if (empty & write) fallthrough_read_addr <= waddr; always @(posedge clk) if (reset) waddr <= 0; else if (write) waddr <= waddr + 1; always @(posedge clk) if (reset) raddr <= 0; else if (clear) raddr <= waddr; else if (read | clear_reg) raddr <= raddr + 1; always @ (posedge clk) if (write & ~full) fifo[waddr] <= data_in; always @(posedge clk) clear_reg <= clear; always @ (posedge clk) if (read | clear_reg) raddr_reg <= raddr; else if (fallthrough_read) raddr_reg <= fallthrough_read_addr; assign data_out = fifo[raddr_reg]; always @(posedge clk) if (reset) final_read <= 0; else if (final_read & read & !write) final_read <= ~final_read; else if ((cnt == 1) & read & !write) final_read <= 1; assign empty = ~(|cnt); assign almost_empty = cnt==1; assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1); assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2); always @ (posedge clk or posedge reset) begin if(reset) read_pointer <= 0; else if(clear) read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1}; else if(read & ~empty) read_pointer <= read_pointer + 1'b1; end `else reg [CNT_WIDTH-1:0] write_pointer; always @ (posedge clk or posedge reset) begin if(reset) read_pointer <= 0; else if(clear) read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read}; else if(read & ~empty) read_pointer <= read_pointer + 1'b1; end always @ (posedge clk or posedge reset) begin if(reset) write_pointer <= 0; else if(clear) write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write}; else if(write & ~full) write_pointer <= write_pointer + 1'b1; end `ifdef ETH_FIFO_XILINX generate if (CNT_WIDTH==4) begin xilinx_dist_ram_16x32 fifo ( .data_out(data_out), .we(write & ~full), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); end else if (CNT_WIDTH==6) begin wire [DATA_WIDTH-1:0] data_out0; wire [DATA_WIDTH-1:0] data_out1; wire [DATA_WIDTH-1:0] data_out2; wire [DATA_WIDTH-1:0] data_out3; wire we_ram0,we_ram1,we_ram2,we_ram3; assign we_ram0 = (write_pointer[5:4]==2'b00); assign we_ram1 = (write_pointer[5:4]==2'b01); assign we_ram2 = (write_pointer[5:4]==2'b10); assign we_ram3 = (write_pointer[5:4]==2'b11); assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 : (read_pointer[5:4]==2'b10) ? data_out2 : (read_pointer[5:4]==2'b01) ? data_out1 : data_out0; xilinx_dist_ram_16x32 fifo0 ( .data_out(data_out0), .we(write & ~full & we_ram0), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); xilinx_dist_ram_16x32 fifo1 ( .data_out(data_out1), .we(write & ~full & we_ram1), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); xilinx_dist_ram_16x32 fifo2 ( .data_out(data_out2), .we(write & ~full & we_ram2), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); xilinx_dist_ram_16x32 fifo3 ( .data_out(data_out3), .we(write & ~full & we_ram3), .data_in(data_in), .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), .wclk(clk) ); end endgenerate `else `ifdef ETH_ALTERA_ALTSYNCRAM altera_dpram_16x32 altera_dpram_16x32_inst ( .data (data_in), .wren (write & ~full), .wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), .rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), .clock (clk), .q (data_out) ); `endif `endif assign empty = ~(|cnt); assign almost_empty = cnt == 1; assign full = cnt == (DEPTH-1); assign almost_full = &cnt[CNT_WIDTH-1:0]; `endif endmodule

data/full_repos/permissive/98916810/sim/wishbone_test_master.v

wishbone_test_master.v

v

[]

[]

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/sim/wishbone_test_master.v:12: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/sim,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/sim,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/sim,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/98916810/sim/wishbone_test_master.v:63: Unsupported: Ignoring delay on this delayed statement.\n #(100*2) ready <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98916810/sim/wishbone_test_master.v:102: syntax error, unexpected \'@\'\n @(posedge wb_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98916810/sim/wishbone_test_master.v:134: Unsupported: Ignoring delay on this delayed statement.\n #(100-1);\n ^\n%Error: data/full_repos/permissive/98916810/sim/wishbone_test_master.v:138: syntax error, unexpected \'@\'\n while(wb_ack_i == 0) begin @(posedge wb_clk); end\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'

module

module WB_TEST_MASTER( wb_clk ); reg [`WB_ADDRESS_BUS_WIDTH - 1 : 0] wb_addr = 0; reg [`WB_DATA_BUS_WIDTH - 1 : 0] wb_data_o = 0; reg [`WB_BWSEL_WIDTH - 1 : 0] wb_bwsel = 0; wire [`WB_DATA_BUS_WIDTH -1 : 0] wb_data_i; wire wb_ack_i; reg wb_cyc = 0; reg wb_stb = 0; reg wb_we = 0; input wb_clk; reg wb_tb_verbose = 1; reg wb_monitor_bus = 1; time last_access_t = 0; reg [`WB_DATA_BUS_WIDTH -1 : 0] dummy; reg ready = 0; initial begin #(`WB_CLOCK_PERIOD*2) ready <= 1; end task verbose; input onoff; begin wb_tb_verbose = onoff; end endtask task monitor_bus; input onoff; begin wb_monitor_bus = onoff; end endtask task rw_generic; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; input [`WB_DATA_BUS_WIDTH - 1 : 0] data_i; output [`WB_DATA_BUS_WIDTH - 1 : 0] data_o; input rw; input [3:0] size; begin : rw_generic_main if(wb_tb_verbose) begin if(rw) $display("@%0d: WB write %s: addr %x, data %x", $time, (size==1?"byte":((size==2)?"short":"int")), addr, data_i); else $display("@%0d: WB read %s: addr %x", $time, (size==1?"byte":((size==2)?"short":"int")), addr); end if($time != last_access_t) begin @(posedge wb_clk); end wb_stb<=1; wb_cyc<=1; wb_addr <= addr; wb_we <= rw; if(rw) begin case(size) 4: begin wb_data_o<=data_i; wb_bwsel <= 4'b1111; end 2: begin if(addr[1]) begin wb_data_o[31:16] = data_i[15:0]; wb_bwsel = 4'b1100; end else begin wb_data_o[15:0] = data_i[15:0]; wb_bwsel = 4'b0011; end end 1: begin case(addr[1:0]) 0: begin wb_data_o[31:24] = data_i[7:0]; wb_bwsel <= 4'b1000; end 1: begin wb_data_o[23:16] = data_i[7:0]; wb_bwsel <= 4'b0100; end 2: begin wb_data_o[15:8] = data_i[7:0]; wb_bwsel <= 4'b0010; end 3: begin wb_data_o[7:0] = data_i[7:0]; wb_bwsel <= 4'b0001; end endcase end endcase end #(`WB_CLOCK_PERIOD-1); while(wb_ack_i == 0) begin @(posedge wb_clk); end data_o = wb_data_i; wb_cyc <= 0; wb_we <= 0; wb_stb <= 0; last_access_t = $time; end endtask task write8; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; input [7 : 0] data_i; begin rw_generic(addr, data_i, dummy, 1, 1); end endtask task read8; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; output [7 : 0] data_o; begin : read8_body reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval; rw_generic(addr, 0, rval, 0, 1); data_o = rval[7:0]; end endtask task write32; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; input [31 : 0] data_i; begin rw_generic(addr, data_i, dummy, 1, 4); end endtask task read32; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; output [31 : 0] data_o; begin : read32_body reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval; rw_generic(addr, 0, rval, 0, 4); data_o = rval[31:0]; end endtask always@(posedge wb_clk) begin if(wb_monitor_bus && wb_cyc && wb_stb && wb_ack_i)begin if(wb_we) $display("@%0d: ACK-Write: addr %x wdata %x bwsel %b", $time, wb_addr, wb_data_o, wb_bwsel); else $display("@%0d: ACK-Read: addr %x rdata %x", $time, wb_addr, wb_data_i); end end endmodule

module WB_TEST_MASTER( wb_clk );

reg [`WB_ADDRESS_BUS_WIDTH - 1 : 0] wb_addr = 0; reg [`WB_DATA_BUS_WIDTH - 1 : 0] wb_data_o = 0; reg [`WB_BWSEL_WIDTH - 1 : 0] wb_bwsel = 0; wire [`WB_DATA_BUS_WIDTH -1 : 0] wb_data_i; wire wb_ack_i; reg wb_cyc = 0; reg wb_stb = 0; reg wb_we = 0; input wb_clk; reg wb_tb_verbose = 1; reg wb_monitor_bus = 1; time last_access_t = 0; reg [`WB_DATA_BUS_WIDTH -1 : 0] dummy; reg ready = 0; initial begin #(`WB_CLOCK_PERIOD*2) ready <= 1; end task verbose; input onoff; begin wb_tb_verbose = onoff; end endtask task monitor_bus; input onoff; begin wb_monitor_bus = onoff; end endtask task rw_generic; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; input [`WB_DATA_BUS_WIDTH - 1 : 0] data_i; output [`WB_DATA_BUS_WIDTH - 1 : 0] data_o; input rw; input [3:0] size; begin : rw_generic_main if(wb_tb_verbose) begin if(rw) $display("@%0d: WB write %s: addr %x, data %x", $time, (size==1?"byte":((size==2)?"short":"int")), addr, data_i); else $display("@%0d: WB read %s: addr %x", $time, (size==1?"byte":((size==2)?"short":"int")), addr); end if($time != last_access_t) begin @(posedge wb_clk); end wb_stb<=1; wb_cyc<=1; wb_addr <= addr; wb_we <= rw; if(rw) begin case(size) 4: begin wb_data_o<=data_i; wb_bwsel <= 4'b1111; end 2: begin if(addr[1]) begin wb_data_o[31:16] = data_i[15:0]; wb_bwsel = 4'b1100; end else begin wb_data_o[15:0] = data_i[15:0]; wb_bwsel = 4'b0011; end end 1: begin case(addr[1:0]) 0: begin wb_data_o[31:24] = data_i[7:0]; wb_bwsel <= 4'b1000; end 1: begin wb_data_o[23:16] = data_i[7:0]; wb_bwsel <= 4'b0100; end 2: begin wb_data_o[15:8] = data_i[7:0]; wb_bwsel <= 4'b0010; end 3: begin wb_data_o[7:0] = data_i[7:0]; wb_bwsel <= 4'b0001; end endcase end endcase end #(`WB_CLOCK_PERIOD-1); while(wb_ack_i == 0) begin @(posedge wb_clk); end data_o = wb_data_i; wb_cyc <= 0; wb_we <= 0; wb_stb <= 0; last_access_t = $time; end endtask task write8; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; input [7 : 0] data_i; begin rw_generic(addr, data_i, dummy, 1, 1); end endtask task read8; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; output [7 : 0] data_o; begin : read8_body reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval; rw_generic(addr, 0, rval, 0, 1); data_o = rval[7:0]; end endtask task write32; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; input [31 : 0] data_i; begin rw_generic(addr, data_i, dummy, 1, 4); end endtask task read32; input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr; output [31 : 0] data_o; begin : read32_body reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval; rw_generic(addr, 0, rval, 0, 4); data_o = rval[31:0]; end endtask always@(posedge wb_clk) begin if(wb_monitor_bus && wb_cyc && wb_stb && wb_ack_i)begin if(wb_we) $display("@%0d: ACK-Write: addr %x wdata %x bwsel %b", $time, wb_addr, wb_data_o, wb_bwsel); else $display("@%0d: ACK-Read: addr %x rdata %x", $time, wb_addr, wb_data_i); end end endmodule

data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs/rtm8sfp_ohwr_serial_regs_tb.v

rtm8sfp_ohwr_serial_regs_tb.v

v

[]

['general public license']

[]

line:107: before: "("

1: b'%Error: data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs/rtm8sfp_ohwr_serial_regs_tb.v:20: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs,data/full_repos/permissive/98916810/timescale.v\n data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs,data/full_repos/permissive/98916810/timescale.v.v\n data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs,data/full_repos/permissive/98916810/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs/rtm8sfp_ohwr_serial_regs_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs/rtm8sfp_ohwr_serial_regs_tb.v:90: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs/rtm8sfp_ohwr_serial_regs_tb.v:91: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/rtm8sfp_ohwr_serial_regs/rtm8sfp_ohwr_serial_regs_tb.v:98: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: Exiting due to 5 error(s)\n'

module

module rtm8sfp_ohwr_serial_regs_tb; wire sys_clk; wire sys_rstn; clk_rst cmp_clk_rst( .clk_sys_o (sys_clk), .sys_rstn_o (sys_rstn) ); wire sfp_sta_ctl_rw = 1'b1; wire sfp_status_reg_out = 1'b0; wire sfp_status_reg_clk_n; wire sfp_ctl_oe_n; wire sfp_ctl_din_n; wire sfp_ctl_str_n; wire sfp_status_reg_pl; wire [7:0] sfp_led1_out; wire [7:0] sfp_los; wire [7:0] sfp_txfault; wire [7:0] sfp_detect_n; wire [7:0] sfp_txdisable = 8'h55; wire [7:0] sfp_rs0 = 8'h55; wire [7:0] sfp_rs1 = 8'h55; wire [7:0] sfp_led1_in = 8'h55; wire [7:0] sfp_led2_in = 8'h55; rtm8sfp_ohwr_serial_regs #( .g_SYS_CLOCK_FREQ ('d100000000), .g_SERIAL_FREQ ('d100000) ) dut ( .clk_sys_i (sys_clk), .rst_n_i (sys_rstn), .sfp_sta_ctl_rw_i (sfp_sta_ctl_rw), .sfp_status_reg_clk_n_o (sfp_status_reg_clk_n), .sfp_status_reg_out_i (sfp_status_reg_out), .sfp_status_reg_pl_o (sfp_status_reg_pl), .sfp_ctl_reg_oe_n_o (sfp_ctl_oe_n), .sfp_ctl_reg_din_n_o (sfp_ctl_din_n), .sfp_ctl_reg_str_n_o (sfp_ctl_str_n), .sfp_led1_o (sfp_led1_out), .sfp_los_o (sfp_los), .sfp_txfault_o (sfp_txfault), .sfp_detect_n_o (sfp_detect_n), .sfp_txdisable_i (sfp_txdisable), .sfp_rs0_i (sfp_rs0), .sfp_rs1_i (sfp_rs1), .sfp_led1_i (sfp_led1_in), .sfp_led2_i (sfp_led2_in) ); initial begin $display("-----------------------------------"); $display("@%0d: Waiting for all resets...", $time); $display("-----------------------------------"); wait (sys_rstn); @(posedge sys_clk); $display("-------------------------------------"); $display("@%0d: Initialization Done!", $time); $display("-------------------------------------"); repeat (100000) begin @(posedge sys_clk); end $finish(); end endmodule

module rtm8sfp_ohwr_serial_regs_tb;

wire sys_clk; wire sys_rstn; clk_rst cmp_clk_rst( .clk_sys_o (sys_clk), .sys_rstn_o (sys_rstn) ); wire sfp_sta_ctl_rw = 1'b1; wire sfp_status_reg_out = 1'b0; wire sfp_status_reg_clk_n; wire sfp_ctl_oe_n; wire sfp_ctl_din_n; wire sfp_ctl_str_n; wire sfp_status_reg_pl; wire [7:0] sfp_led1_out; wire [7:0] sfp_los; wire [7:0] sfp_txfault; wire [7:0] sfp_detect_n; wire [7:0] sfp_txdisable = 8'h55; wire [7:0] sfp_rs0 = 8'h55; wire [7:0] sfp_rs1 = 8'h55; wire [7:0] sfp_led1_in = 8'h55; wire [7:0] sfp_led2_in = 8'h55; rtm8sfp_ohwr_serial_regs #( .g_SYS_CLOCK_FREQ ('d100000000), .g_SERIAL_FREQ ('d100000) ) dut ( .clk_sys_i (sys_clk), .rst_n_i (sys_rstn), .sfp_sta_ctl_rw_i (sfp_sta_ctl_rw), .sfp_status_reg_clk_n_o (sfp_status_reg_clk_n), .sfp_status_reg_out_i (sfp_status_reg_out), .sfp_status_reg_pl_o (sfp_status_reg_pl), .sfp_ctl_reg_oe_n_o (sfp_ctl_oe_n), .sfp_ctl_reg_din_n_o (sfp_ctl_din_n), .sfp_ctl_reg_str_n_o (sfp_ctl_str_n), .sfp_led1_o (sfp_led1_out), .sfp_los_o (sfp_los), .sfp_txfault_o (sfp_txfault), .sfp_detect_n_o (sfp_detect_n), .sfp_txdisable_i (sfp_txdisable), .sfp_rs0_i (sfp_rs0), .sfp_rs1_i (sfp_rs1), .sfp_led1_i (sfp_led1_in), .sfp_led2_i (sfp_led2_in) ); initial begin $display("-----------------------------------"); $display("@%0d: Waiting for all resets...", $time); $display("-----------------------------------"); wait (sys_rstn); @(posedge sys_clk); $display("-------------------------------------"); $display("@%0d: Initialization Done!", $time); $display("-------------------------------------"); repeat (100000) begin @(posedge sys_clk); end $finish(); end endmodule

data/full_repos/permissive/98916810/testbench/si57x_interface/si57x_interface_tb.v

si57x_interface_tb.v

v

[]

['general public license']

[]

line:96: before: "("

1: b'%Error: data/full_repos/permissive/98916810/testbench/si57x_interface/si57x_interface_tb.v:20: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/si57x_interface,data/full_repos/permissive/98916810/timescale.v\n data/full_repos/permissive/98916810/testbench/si57x_interface,data/full_repos/permissive/98916810/timescale.v.v\n data/full_repos/permissive/98916810/testbench/si57x_interface,data/full_repos/permissive/98916810/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/si57x_interface/si57x_interface_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/si57x_interface/si57x_interface_tb.v:79: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/si57x_interface/si57x_interface_tb.v:80: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/si57x_interface/si57x_interface_tb.v:87: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: Exiting due to 5 error(s)\n'

module

module si57x_interface_tb; wire sys_clk; wire sys_rstn; clk_rst cmp_clk_rst( .clk_sys_o (sys_clk), .sys_rstn_o (sys_rstn) ); wire ext_wr = 1'b0; wire [37:0] ext_rfreq_value = 'h0; wire [6:0] ext_n1_value = 'h0; wire [2:0] ext_hs_value = 'h0; wire scl_pad_oen; wire sda_pad_oen; wire si57x_oe_in = 1'b1; wire [7:0] si57x_addr = 8'b10101010; wire si57x_oe_out; si57x_interface #( .g_SYS_CLOCK_FREQ ('d100000000), .g_I2C_FREQ ('d400000), .g_INIT_OSC (1'b1), .g_INIT_RFREQ_VALUE (38'h03017a66ad), .g_INIT_N1_VALUE (7'b0000011), .g_INIT_HS_VALUE (3'b111) ) dut ( .clk_sys_i (sys_clk), .rst_n_i (sys_rstn), .ext_wr_i (ext_wr), .ext_rfreq_value_i (ext_rfreq_value), .ext_n1_value_i (ext_n1_value), .ext_hs_value_i (ext_hs_value), .scl_pad_oen_o (scl_pad_oen), .sda_pad_oen_o (sda_pad_oen), .si57x_oe_i (si57x_oe_in), .si57x_addr_i (si57x_addr), .si57x_oe_o (si57x_oe_out) ); initial begin $display("-----------------------------------"); $display("@%0d: Waiting for all resets...", $time); $display("-----------------------------------"); wait (sys_rstn); @(posedge sys_clk); $display("-------------------------------------"); $display("@%0d: Initialization Done!", $time); $display("-------------------------------------"); repeat (100000) begin @(posedge sys_clk); end $finish(); end endmodule

module si57x_interface_tb;

wire sys_clk; wire sys_rstn; clk_rst cmp_clk_rst( .clk_sys_o (sys_clk), .sys_rstn_o (sys_rstn) ); wire ext_wr = 1'b0; wire [37:0] ext_rfreq_value = 'h0; wire [6:0] ext_n1_value = 'h0; wire [2:0] ext_hs_value = 'h0; wire scl_pad_oen; wire sda_pad_oen; wire si57x_oe_in = 1'b1; wire [7:0] si57x_addr = 8'b10101010; wire si57x_oe_out; si57x_interface #( .g_SYS_CLOCK_FREQ ('d100000000), .g_I2C_FREQ ('d400000), .g_INIT_OSC (1'b1), .g_INIT_RFREQ_VALUE (38'h03017a66ad), .g_INIT_N1_VALUE (7'b0000011), .g_INIT_HS_VALUE (3'b111) ) dut ( .clk_sys_i (sys_clk), .rst_n_i (sys_rstn), .ext_wr_i (ext_wr), .ext_rfreq_value_i (ext_rfreq_value), .ext_n1_value_i (ext_n1_value), .ext_hs_value_i (ext_hs_value), .scl_pad_oen_o (scl_pad_oen), .sda_pad_oen_o (sda_pad_oen), .si57x_oe_i (si57x_oe_in), .si57x_addr_i (si57x_addr), .si57x_oe_o (si57x_oe_out) ); initial begin $display("-----------------------------------"); $display("@%0d: Waiting for all resets...", $time); $display("-----------------------------------"); wait (sys_rstn); @(posedge sys_clk); $display("-------------------------------------"); $display("@%0d: Initialization Done!", $time); $display("-------------------------------------"); repeat (100000) begin @(posedge sys_clk); end $finish(); end endmodule

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v

clk_rst.v

v

[]

[]

[]

line:107: before: "("

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:1: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb,data/full_repos/permissive/98916810/timescale.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb,data/full_repos/permissive/98916810/timescale.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb,data/full_repos/permissive/98916810/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:2: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:16: Define or directive not defined: \'`CLK_SYS_PERIOD\'\n parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:17: Define or directive not defined: \'`CLK_ADC_PERIOD\'\n parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:19: Define or directive not defined: \'`CLK_100MHZ_PERIOD\'\n localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:20: Define or directive not defined: \'`CLK_200MHZ_PERIOD\'\n localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:49: Define or directive not defined: \'`RST_SYS_DELAY\'\n repeat (`RST_SYS_DELAY) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n repeat (`RST_SYS_DELAY) begin\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:64: Define or directive not defined: \'`RST_SYS_DELAY\'\n repeat (`RST_SYS_DELAY) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:79: Define or directive not defined: \'`RST_SYS_DELAY\'\n repeat (`RST_SYS_DELAY) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:94: Define or directive not defined: \'`RST_200MHZ_DELAY\'\n repeat (`RST_200MHZ_DELAY) begin\n ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:104: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:105: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v:106: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o;\n ^\n%Error: Exiting due to 15 error(s), 3 warning(s)\n'

module

module clk_rst( clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o, sys_rstn_o, adc_rstn_o, clk100mhz_rstn_o, clk200mhz_rstn_o ); parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD; parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD; localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD; localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD; output reg clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o; output reg sys_rstn_o, adc_rstn_o, clk100mhz_rstn_o, clk200mhz_rstn_o; initial begin clk_sys_o = 0; clk_adc_o = 0; clk_100mhz_o = 0; clk_200mhz_o = 0; end initial begin sys_rstn_o <= 1'b0; repeat (`RST_SYS_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_sys_o); sys_rstn_o <= 1'b1; end initial begin adc_rstn_o <= 1'b0; repeat (`RST_SYS_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_adc_o); adc_rstn_o <= 1'b1; end initial begin clk100mhz_rstn_o <= 1'b0; repeat (`RST_SYS_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_100mhz_o); clk100mhz_rstn_o <= 1'b1; end initial begin clk200mhz_rstn_o <= 1'b0; repeat (`RST_200MHZ_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_200mhz_o); clk200mhz_rstn_o <= 1'b1; end always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o; always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o; always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o; always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o; endmodule

module clk_rst( clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o, sys_rstn_o, adc_rstn_o, clk100mhz_rstn_o, clk200mhz_rstn_o );

parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD; parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD; localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD; localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD; output reg clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o; output reg sys_rstn_o, adc_rstn_o, clk100mhz_rstn_o, clk200mhz_rstn_o; initial begin clk_sys_o = 0; clk_adc_o = 0; clk_100mhz_o = 0; clk_200mhz_o = 0; end initial begin sys_rstn_o <= 1'b0; repeat (`RST_SYS_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_sys_o); sys_rstn_o <= 1'b1; end initial begin adc_rstn_o <= 1'b0; repeat (`RST_SYS_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_adc_o); adc_rstn_o <= 1'b1; end initial begin clk100mhz_rstn_o <= 1'b0; repeat (`RST_SYS_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_100mhz_o); clk100mhz_rstn_o <= 1'b1; end initial begin clk200mhz_rstn_o <= 1'b0; repeat (`RST_200MHZ_DELAY) begin @(posedge clk_sys_o); end @(posedge clk_200mhz_o); clk200mhz_rstn_o <= 1'b1; end always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o; always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o; always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o; always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o; endmodule

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v

wb_acq_core_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:26: Cannot find include file: regs/wb_acq_core_regs.vh\n`include "regs/wb_acq_core_regs.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:741: Unsupported: wait statements\n wait (WB.ready);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:742: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:743: Unsupported: wait statements\n wait (adc_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:751: Unsupported: wait statements\n wait (init_calib_complete);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:757: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:950: Define or directive not defined: \'`DATA_TEST_WIDTH\'\n function [`DATA_TEST_WIDTH-1:0] f_data_gen;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1008: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1009: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] mask;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1010: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] offset;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1013: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1024: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1064: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1071: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ADDR_ACQ_CORE_SHOTS\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ACQ_CORE_SHOTS_NB_OFFSET\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1075: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`ADDR_ACQ_CORE_PRE_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1079: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`ADDR_ACQ_CORE_POST_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET\'\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1086: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1090: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`ADDR_ACQ_CORE_DDR3_START_ADDR\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_START_ACQ_OFFSET\'\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1098: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1103: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: Define or directive not defined: \'`ADDR_ACQ_CORE_STA\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: syntax error, unexpected >>, expecting \')\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

module

module wb_acq_core_tb; localparam c_data_max = (2**`ADC_DATA_WIDTH)-1; localparam c_wait_acquisition_done = 128; parameter REFCLK_FREQ = 200; parameter SIM_BYPASS_INIT_CAL = "FAST"; parameter RST_ACT_LOW = 1; parameter IODELAY_GRP = "IODELAY_MIG"; parameter nCK_PER_CLK = 2; parameter nCS_PER_RANK = 1; parameter DQS_CNT_WIDTH = 3; parameter RANK_WIDTH = 1; parameter BANK_WIDTH = 3; parameter CK_WIDTH = 1; parameter CKE_WIDTH = 1; parameter COL_WIDTH = 10; parameter CS_WIDTH = 1; parameter DM_WIDTH = 8; parameter DQ_WIDTH = 64; parameter DQS_WIDTH = 8; parameter ROW_WIDTH = 14; parameter BURST_MODE = "4"; parameter INPUT_CLK_TYPE = "SINGLE_ENDED"; parameter BM_CNT_WIDTH = 2; parameter ADDR_CMD_MODE = "1T" ; parameter ORDERING = "STRICT"; parameter RTT_NOM = "60"; parameter RTT_WR = "OFF"; parameter OUTPUT_DRV = "HIGH"; parameter REG_CTRL = "OFF"; parameter CLKFBOUT_MULT_F = 6; parameter DIVCLK_DIVIDE = 2; parameter CLKOUT_DIVIDE = 3; parameter tCK = 2500; parameter DEBUG_PORT = "OFF"; parameter tPRDI = 1_000_000; parameter tREFI = 7800000; parameter tZQI = 128_000_000; parameter ADDR_WIDTH = 28; parameter STARVE_LIMIT = 2; parameter TCQ = 100; parameter ECC = "OFF"; parameter ECC_TEST = "OFF"; localparam real TPROP_DQS = 0.00; localparam real TPROP_DQS_RD = 0.00; localparam real TPROP_PCB_CTRL = 0.00; localparam real TPROP_PCB_DATA = 0.00; localparam real TPROP_PCB_DATA_RD = 0.00; localparam MEMORY_WIDTH = 16; localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH; localparam real CLK_PERIOD = tCK; localparam real REFCLK_HALF_PERIOD = (1000000.0/(2*REFCLK_FREQ)); localparam DRAM_DEVICE = "SODIMM"; localparam VT_ENABLE = "OFF"; localparam VT_RATE = CLK_PERIOD/500; localparam VT_UPDATE_INTERVAL = CLK_PERIOD*50; localparam VT_MAX = CLK_PERIOD/40; localparam SYSCLK_PERIOD = tCK * nCK_PER_CLK; localparam DATA_WIDTH = 64; localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH; localparam DATA_CHECK_FIFO_SIZE = 8192; localparam c_n_shots_width = 16; localparam c_n_pre_samples_width = 32; localparam c_n_post_samples_width = 32; reg [DATA_WIDTH-1:0] data_test; reg data_test_valid; reg data_test_valid_t; reg trigger_test; real data_ext_stall_threshold; real data_ext_rdy_threshold; real data_valid_threshold; reg data_gen_start; reg test_in_progress; reg stop_on_error; integer test_id = 1; reg [c_n_shots_width-1:0] n_shots; reg [c_n_pre_samples_width-1:0] pre_trig_samples; reg [c_n_post_samples_width-1:0] post_trig_samples; reg [32-1:0] ddr3_start_addr; reg [32-1:0] lmt_pkt_size; reg skip_trig; reg wait_finish; real data_valid_prob; integer min_wait_gnt; integer max_wait_gnt; reg [31:0] acq_core_fsm_ctl_reg = 'h0; reg [31:0] acq_core_fsm_sta_reg = 'h0; wire error; wire phy_init_done; wire ddr3_parity; wire ddr3_reset_n; wire [DQ_WIDTH-1:0] ddr3_dq_fpga; wire [ROW_WIDTH-1:0] ddr3_addr_fpga; wire [BANK_WIDTH-1:0] ddr3_ba_fpga; wire ddr3_ras_n_fpga; wire ddr3_cas_n_fpga; wire ddr3_we_n_fpga; wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga; wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_fpga; wire [CKE_WIDTH-1:0] ddr3_cke_fpga; wire [DM_WIDTH-1:0] ddr3_dm_fpga; wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga; wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga; wire [CK_WIDTH-1:0] ddr3_ck_p_fpga; wire [CK_WIDTH-1:0] ddr3_ck_n_fpga; wire [DQ_WIDTH-1:0] ddr3_dq_sdram; reg [ROW_WIDTH-1:0] ddr3_addr_sdram; reg [BANK_WIDTH-1:0] ddr3_ba_sdram; reg ddr3_ras_n_sdram; reg ddr3_cas_n_sdram; reg ddr3_we_n_sdram; reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram; reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_sdram; reg [CKE_WIDTH-1:0] ddr3_cke_sdram; wire [DM_WIDTH-1:0] ddr3_dm_sdram; reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp; wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram; wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram; reg [CK_WIDTH-1:0] ddr3_ck_p_sdram; reg [CK_WIDTH-1:0] ddr3_ck_n_sdram; wire init_calib_complete; wire tg_compare_error; reg ddr_sys_clk_i; reg clk_ref_i; wire [DATA_WIDTH-1:0] ext_dout; wire [ADDR_WIDTH-1:0] ext_addr; wire ext_valid; wire ext_sof; wire ext_eof; wire ui_app_wdf_wren; wire [4*PAYLOAD_WIDTH-1:0] ui_app_wdf_data; wire [4*PAYLOAD_WIDTH/8-1:0] ui_app_wdf_mask; wire ui_app_wdf_end; wire [ADDR_WIDTH-1:0] ui_app_addr; wire [2:0] ui_app_cmd; wire ui_app_en; wire ui_app_rdy; wire ui_app_wdf_rdy; wire [4*PAYLOAD_WIDTH-1:0] ui_app_rd_data; wire ui_app_rd_data_end; wire ui_app_rd_data_valid; wire ui_clk_sync_rst; wire ui_clk_sync_rst_n; wire ui_clk; wire ui_phy_init_done; wire ui_app_req; wire ui_app_gnt; wire [DATA_WIDTH-1:0] dbg_ddr_rb_data; wire [ADDR_WIDTH-1:0] dbg_ddr_rb_addr; wire dbg_ddr_rb_valid; wire chk_data_err; wire [16-1:0] chk_data_err_cnt; wire chk_addr_err; wire [16-1:0] chk_addr_err_cnt; wire chk_end; wire chk_pass; wire sys_clk; wire sys_rstn; wire sys_rst; wire adc_clk; wire adc_rstn; wire clk_200mhz; wire clk200mhz_rstn; wire ddr3_sys_clk; wire ddr3_sys_rstn; wire clk_ref; wire sda; wire scl; clk_rst cmp_clk_rst( .clk_sys_o(sys_clk), .clk_adc_o(adc_clk), .clk_100mhz_o(), .clk_200mhz_o(clk_200mhz), .sys_rstn_o(sys_rstn), .adc_rstn_o(adc_rstn), .clk100mhz_rstn_o(), .clk200mhz_rstn_o(clk200mhz_rstn) ); assign sys_rst = ~sys_rstn; assign clk_ref = clk_200mhz; assign ddr3_sys_clk = clk_200mhz; assign ddr3_sys_rstn = clk200mhz_rstn; WB_TEST_MASTER WB( .wb_clk (sys_clk) ); wb_acq_core #(.g_ddr_addr_width(ADDR_WIDTH), .g_addr_width(ADDR_WIDTH), .g_sim_readback(1) ) dut( .fs_clk_i (adc_clk), .fs_ce_i (1'b1), .fs_rst_n_i (adc_rstn), .sys_clk_i (sys_clk), .sys_rst_n_i (sys_rstn), .ext_clk_i (ui_clk), .ext_rst_n_i (ui_clk_sync_rst_n), .wb_adr_i (WB.wb_addr), .wb_dat_i (WB.wb_data_o), .wb_dat_o (WB.wb_data_i), .wb_cyc_i (WB.wb_cyc), .wb_sel_i (WB.wb_bwsel), .wb_stb_i (WB.wb_stb), .wb_we_i (WB.wb_we), .wb_ack_o (WB.wb_ack_i), .wb_err_o (), .wb_rty_o (), .wb_stall_o (), .data_i (data_test), .dvalid_i (data_test_valid), .ext_trig_i (trigger_test), .dpram_dout_o (), .dpram_valid_o (), .ext_dout_o (ext_dout), .ext_valid_o (ext_valid), .ext_addr_o (ext_addr), .ext_sof_o (ext_sof), .ext_eof_o (ext_eof), .ext_dreq_o (ext_dreq), .ext_stall_o (ext_stall), .ui_app_addr_o (ui_app_addr), .ui_app_cmd_o (ui_app_cmd), .ui_app_en_o (ui_app_en), .ui_app_rdy_i (ui_app_rdy), .ui_app_wdf_data_o (ui_app_wdf_data), .ui_app_wdf_end_o (ui_app_wdf_end), .ui_app_wdf_mask_o (ui_app_wdf_mask), .ui_app_wdf_wren_o (ui_app_wdf_wren), .ui_app_wdf_rdy_i (ui_app_wdf_rdy), .ui_app_rd_data_i (ui_app_rd_data), .ui_app_rd_data_end_i (ui_app_rd_data_end), .ui_app_rd_data_valid_i (ui_app_rd_data_valid), .ui_app_req_o (ui_app_req), .ui_app_gnt_i (ui_app_gnt), .dbg_ddr_rb_data_o (dbg_ddr_rb_data), .dbg_ddr_rb_addr_o (dbg_ddr_rb_addr), .dbg_ddr_rb_valid_o (dbg_ddr_rb_valid) ); assign ui_app_gnt = 1'b1; data_checker #(.g_addr_width(ADDR_WIDTH), .g_data_width(DATA_WIDTH), .g_fifo_size(DATA_CHECK_FIFO_SIZE) ) cmp_data_checker( .ext_clk_i (ui_clk), .ext_rst_n_i (ui_clk_sync_rst_n & test_in_progress), .exp_din_i (ext_dout), .exp_addr_i (ext_addr), .exp_valid_i (ext_valid & ~ext_stall), .act_din_i (dbg_ddr_rb_data), .act_addr_i (dbg_ddr_rb_addr), .act_valid_i (dbg_ddr_rb_valid), .lmt_pkt_size_i (lmt_pkt_size), .lmt_shots_nb_i (n_shots), .lmt_valid_i (test_in_progress), .chk_data_err_o (chk_data_err), .chk_data_err_cnt_o (chk_data_err_cnt), .chk_addr_err_o (chk_addr_err), .chk_addr_err_cnt_o (chk_addr_err_cnt), .chk_end_o (chk_end), .chk_pass_o (chk_pass) ); ddr_v6 #( .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), .RST_ACT_LOW (RST_ACT_LOW) ) cmp_ddr_v6( .sys_clk (ddr3_sys_clk), .sys_rst (ddr3_sys_rstn), .clk_ref (clk_ref), .ddr3_dq (ddr3_dq_fpga), .ddr3_dm (ddr3_dm_fpga), .ddr3_addr (ddr3_addr_fpga), .ddr3_ba (ddr3_ba_fpga), .ddr3_ras_n (ddr3_ras_n_fpga), .ddr3_cas_n (ddr3_cas_n_fpga), .ddr3_we_n (ddr3_we_n_fpga), .ddr3_reset_n (ddr3_reset_n), .ddr3_cs_n (ddr3_cs_n_fpga), .ddr3_odt (ddr3_odt_fpga), .ddr3_cke (ddr3_cke_fpga), .ddr3_dqs_p (ddr3_dqs_p_fpga), .ddr3_dqs_n (ddr3_dqs_n_fpga), .ddr3_ck_p (ddr3_ck_p_fpga), .ddr3_ck_n (ddr3_ck_n_fpga), .app_wdf_wren (ui_app_wdf_wren), .app_wdf_data (ui_app_wdf_data), .app_wdf_mask (ui_app_wdf_mask), .app_wdf_end (ui_app_wdf_end), .app_addr (ui_app_addr), .app_cmd (ui_app_cmd), .app_en (ui_app_en), .app_rdy (ui_app_rdy), .app_wdf_rdy (ui_app_wdf_rdy), .app_rd_data (ui_app_rd_data), .app_rd_data_end (ui_app_rd_data_end), .app_rd_data_valid (ui_app_rd_data_valid), .ui_clk_sync_rst (ui_clk_sync_rst), .ui_clk (ui_clk), .phy_init_done (ui_phy_init_done) ); assign ui_clk_sync_rst_n = ~ui_clk_sync_rst; genvar r,i,dqs_x; generate for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk if(MEMORY_WIDTH == 16) begin: mem_16 if(DQ_WIDTH/16) begin: gen_mem for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem ddr3_model u_comp_ddr3 ( .rst_n (ddr3_reset_n), .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]), .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]), .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .ras_n (ddr3_ras_n_sdram), .cas_n (ddr3_cas_n_sdram), .we_n (ddr3_we_n_sdram), .dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]), .ba (ddr3_ba_sdram), .addr (ddr3_addr_sdram), .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]), .dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]), .dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]), .tdqs_n (), .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]) ); end end if (DQ_WIDTH%16) begin: gen_mem_extrabits ddr3_model u_comp_ddr3 ( .rst_n (ddr3_reset_n), .ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]), .ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]), .cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]), .cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]), .ras_n (ddr3_ras_n_sdram), .cas_n (ddr3_cas_n_sdram), .we_n (ddr3_we_n_sdram), .dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}), .ba (ddr3_ba_sdram), .addr (ddr3_addr_sdram), .dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)], ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}), .dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1], ddr3_dqs_p_sdram[DQS_WIDTH-1]}), .dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1], ddr3_dqs_n_sdram[DQS_WIDTH-1]}), .tdqs_n (), .odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]) ); end end if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4 for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem ddr3_model u_comp_ddr3 ( .rst_n (ddr3_reset_n), .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]), .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]), .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .ras_n (ddr3_ras_n_sdram), .cas_n (ddr3_cas_n_sdram), .we_n (ddr3_we_n_sdram), .dm_tdqs (ddr3_dm_sdram[i]), .ba (ddr3_ba_sdram), .addr (ddr3_addr_sdram), .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]), .dqs (ddr3_dqs_p_sdram[i]), .dqs_n (ddr3_dqs_n_sdram[i]), .tdqs_n (), .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]) ); end end end endgenerate always @( * ) begin ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga; ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga; ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga; ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga; ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga; ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga; ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga; ddr3_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga; ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga; ddr3_odt_sdram <= #(TPROP_PCB_CTRL) ddr3_odt_fpga; ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga; end assign ddr3_dm_sdram = ddr3_dm_sdram_tmp; assign init_calib_complete = ui_phy_init_done; genvar dqwd; generate for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay WireDelay # ( .Delay_g (TPROP_PCB_DATA), .Delay_rd (TPROP_PCB_DATA_RD), .ERR_INSERT ("OFF") ) u_delay_dq ( .A (ddr3_dq_fpga[dqwd]), .B (ddr3_dq_sdram[dqwd]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); end WireDelay # ( .Delay_g (TPROP_PCB_DATA), .Delay_rd (TPROP_PCB_DATA_RD), .ERR_INSERT (ECC) ) u_delay_dq_0 ( .A (ddr3_dq_fpga[0]), .B (ddr3_dq_sdram[0]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); endgenerate genvar dqswd; generate for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay WireDelay # ( .Delay_g (TPROP_DQS), .Delay_rd (TPROP_DQS_RD), .ERR_INSERT ("OFF") ) u_delay_dqs_p ( .A (ddr3_dqs_p_fpga[dqswd]), .B (ddr3_dqs_p_sdram[dqswd]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); WireDelay # ( .Delay_g (TPROP_DQS), .Delay_rd (TPROP_DQS_RD), .ERR_INSERT ("OFF") ) u_delay_dqs_n ( .A (ddr3_dqs_n_fpga[dqswd]), .B (ddr3_dqs_n_sdram[dqswd]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); end endgenerate initial begin data_gen_start = 1'b0; test_in_progress = 1'b0; trigger_test = 1'b0; min_wait_gnt = 0; max_wait_gnt = 0; $display("-----------------------------------"); $display("@%0d: Simulation of BPM ACQ FSM starting!", $time); $display("-----------------------------------"); $display("-----------------------------------"); $display("@%0d: Initialization Begin", $time); $display("-----------------------------------"); $display("-----------------------------------"); $display("@%0d: Waiting for all resets...", $time); $display("-----------------------------------"); wait (WB.ready); wait (sys_rstn); wait (adc_rstn); $display("@%0d: Reset done!", $time); $display("-----------------------------------"); $display("@%0d: Waiting for Memory initilization/calibration...", $time); $display("-----------------------------------"); wait (init_calib_complete); $display("@%0d: Memory initialization/calibration done!", $time); data_gen_start = 1'b1; @(posedge sys_clk); $display("-------------------------------------"); $display("@%0d: Initialization Done!", $time); $display("-------------------------------------"); test_id = 1; n_shots = 16'h0001; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; stop_on_error = 1'b1; data_valid_prob = 1.0; min_wait_gnt = 32; max_wait_gnt = 128; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 2; n_shots = 16'h0001; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.7; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 3; n_shots = 16'h0001; pre_trig_samples = 32'h00000100; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.7; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 4; n_shots = 16'h0001; pre_trig_samples = 32'h00001000; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.5; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 5; n_shots = 16'h0002; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.7; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 6; n_shots = 16'h0010; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.6; min_wait_gnt = 64; max_wait_gnt = 128; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 7; n_shots = 16'h0010; pre_trig_samples = 32'h00000020; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.6; min_wait_gnt = 128; max_wait_gnt = 512; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); $display("Simulation Done!"); $display("All Tests Passed!"); $display("---------------------------------------------"); $finish; end always @(posedge adc_clk) begin if (data_gen_start) begin if (data_test_valid_t) data_test <= data_test + 1; data_test_valid_t <= f_gen_data_rdy_gen(data_valid_threshold); data_test_valid <= data_test_valid_t; end else begin data_test <= 'h0; data_test_valid <= 1'b0; data_test_valid_t <= 1'b0; end end function [`DATA_TEST_WIDTH-1:0] f_data_gen; input integer max_size; begin f_data_gen = {$random} % max_size; end endfunction function f_gen_data_rdy_gen; input real prob; real temp; begin f_gen_data_rdy_gen = f_gen_bit_one(prob); end endfunction function f_gen_data_stall; input real prob; real temp; begin f_gen_data_stall = f_gen_bit_one(1.0-prob); end endfunction function f_gen_bit_one; input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp <= prob) f_gen_bit_one = 1'b1; else f_gen_bit_one = 1'b0; end endfunction function integer f_gen_lmt; input integer min; input integer max; real temp; begin f_gen_lmt = ({$random} % (max-min) + min); end endfunction task wb_busy_wait; input [`WB_ADDRESS_BUS_WIDTH-1:0] addr; input [`WB_DATA_BUS_WIDTH-1:0] mask; input [`WB_DATA_BUS_WIDTH-1:0] offset; input verbose; reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg; begin WB.monitor_bus(1'b0); WB.verbose(1'b0); WB.read32(addr, tmp_reg); while (((tmp_reg & mask) >> offset) != 'h1) begin if (verbose) $write("."); @(posedge sys_clk); WB.read32(addr, tmp_reg); end WB.monitor_bus(1'b1); WB.verbose(1'b1); end endtask task wb_acq; input integer test_id; input [15:0] n_shots; input [31:0] pre_trig_samples; input [31:0] post_trig_samples; input [31:0] ddr3_start_addr; input skip_trig; input wait_finish; input stop_on_error; input real data_valid_prob; reg [31:0] acq_core_fsm_ctl_reg; begin $display("#############################"); $display("######## TEST #%03d ######", test_id); $display("#############################"); $display("## Number of shots = %03d", n_shots); $display("## Number of pre samples = %03d", pre_trig_samples); $display("## Skip trigger = %d", skip_trig); $display("## Number of post samples = %03d", post_trig_samples); $display("Setting throttling parameters scenario"); $display("Setting source data valid input probability = %.2f%%", data_valid_prob*100); test_in_progress = 1'b1; @(posedge sys_clk); data_valid_threshold = data_valid_prob; $display("Setting # of shots to %03d", n_shots); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET)); $display("Setting # of pre-trigger to %03d", pre_trig_samples); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples)); $display("Setting # of pos-trigger to %03d", post_trig_samples); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples)); acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET; $display("Setting skip trigger parameter to %d", skip_trig); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg); $display("Setting DDR3 start address for the next acquistion %d", skip_trig); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr); acq_core_fsm_ctl_reg = acq_core_fsm_ctl_reg | (32'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET; $display("Starting acquisition... "); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg); if (wait_finish) begin $display("Waiting until all data have been acquired...\n"); @(posedge sys_clk); wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE, `ACQ_CORE_STA_DDR3_TRANS_DONE_OFFSET, 1'b1); end $display("Done!"); wait (chk_end); $display("Data checker detected a total of %03d data mismatch errors", chk_data_err_cnt); $display("Data checker detected a total of %03d addr mismatch errors", chk_addr_err_cnt); if (stop_on_error & (chk_data_err | chk_addr_err)) begin $display("TEST #%03d NOT PASS!", test_id); $finish; end $display("\n"); @(posedge sys_clk); test_in_progress = 1'b0; repeat (2) begin @(posedge sys_clk); end end endtask endmodule

module wb_acq_core_tb;

localparam c_data_max = (2**`ADC_DATA_WIDTH)-1; localparam c_wait_acquisition_done = 128; parameter REFCLK_FREQ = 200; parameter SIM_BYPASS_INIT_CAL = "FAST"; parameter RST_ACT_LOW = 1; parameter IODELAY_GRP = "IODELAY_MIG"; parameter nCK_PER_CLK = 2; parameter nCS_PER_RANK = 1; parameter DQS_CNT_WIDTH = 3; parameter RANK_WIDTH = 1; parameter BANK_WIDTH = 3; parameter CK_WIDTH = 1; parameter CKE_WIDTH = 1; parameter COL_WIDTH = 10; parameter CS_WIDTH = 1; parameter DM_WIDTH = 8; parameter DQ_WIDTH = 64; parameter DQS_WIDTH = 8; parameter ROW_WIDTH = 14; parameter BURST_MODE = "4"; parameter INPUT_CLK_TYPE = "SINGLE_ENDED"; parameter BM_CNT_WIDTH = 2; parameter ADDR_CMD_MODE = "1T" ; parameter ORDERING = "STRICT"; parameter RTT_NOM = "60"; parameter RTT_WR = "OFF"; parameter OUTPUT_DRV = "HIGH"; parameter REG_CTRL = "OFF"; parameter CLKFBOUT_MULT_F = 6; parameter DIVCLK_DIVIDE = 2; parameter CLKOUT_DIVIDE = 3; parameter tCK = 2500; parameter DEBUG_PORT = "OFF"; parameter tPRDI = 1_000_000; parameter tREFI = 7800000; parameter tZQI = 128_000_000; parameter ADDR_WIDTH = 28; parameter STARVE_LIMIT = 2; parameter TCQ = 100; parameter ECC = "OFF"; parameter ECC_TEST = "OFF"; localparam real TPROP_DQS = 0.00; localparam real TPROP_DQS_RD = 0.00; localparam real TPROP_PCB_CTRL = 0.00; localparam real TPROP_PCB_DATA = 0.00; localparam real TPROP_PCB_DATA_RD = 0.00; localparam MEMORY_WIDTH = 16; localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH; localparam real CLK_PERIOD = tCK; localparam real REFCLK_HALF_PERIOD = (1000000.0/(2*REFCLK_FREQ)); localparam DRAM_DEVICE = "SODIMM"; localparam VT_ENABLE = "OFF"; localparam VT_RATE = CLK_PERIOD/500; localparam VT_UPDATE_INTERVAL = CLK_PERIOD*50; localparam VT_MAX = CLK_PERIOD/40; localparam SYSCLK_PERIOD = tCK * nCK_PER_CLK; localparam DATA_WIDTH = 64; localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH; localparam DATA_CHECK_FIFO_SIZE = 8192; localparam c_n_shots_width = 16; localparam c_n_pre_samples_width = 32; localparam c_n_post_samples_width = 32; reg [DATA_WIDTH-1:0] data_test; reg data_test_valid; reg data_test_valid_t; reg trigger_test; real data_ext_stall_threshold; real data_ext_rdy_threshold; real data_valid_threshold; reg data_gen_start; reg test_in_progress; reg stop_on_error; integer test_id = 1; reg [c_n_shots_width-1:0] n_shots; reg [c_n_pre_samples_width-1:0] pre_trig_samples; reg [c_n_post_samples_width-1:0] post_trig_samples; reg [32-1:0] ddr3_start_addr; reg [32-1:0] lmt_pkt_size; reg skip_trig; reg wait_finish; real data_valid_prob; integer min_wait_gnt; integer max_wait_gnt; reg [31:0] acq_core_fsm_ctl_reg = 'h0; reg [31:0] acq_core_fsm_sta_reg = 'h0; wire error; wire phy_init_done; wire ddr3_parity; wire ddr3_reset_n; wire [DQ_WIDTH-1:0] ddr3_dq_fpga; wire [ROW_WIDTH-1:0] ddr3_addr_fpga; wire [BANK_WIDTH-1:0] ddr3_ba_fpga; wire ddr3_ras_n_fpga; wire ddr3_cas_n_fpga; wire ddr3_we_n_fpga; wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga; wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_fpga; wire [CKE_WIDTH-1:0] ddr3_cke_fpga; wire [DM_WIDTH-1:0] ddr3_dm_fpga; wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga; wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga; wire [CK_WIDTH-1:0] ddr3_ck_p_fpga; wire [CK_WIDTH-1:0] ddr3_ck_n_fpga; wire [DQ_WIDTH-1:0] ddr3_dq_sdram; reg [ROW_WIDTH-1:0] ddr3_addr_sdram; reg [BANK_WIDTH-1:0] ddr3_ba_sdram; reg ddr3_ras_n_sdram; reg ddr3_cas_n_sdram; reg ddr3_we_n_sdram; reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram; reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_sdram; reg [CKE_WIDTH-1:0] ddr3_cke_sdram; wire [DM_WIDTH-1:0] ddr3_dm_sdram; reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp; wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram; wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram; reg [CK_WIDTH-1:0] ddr3_ck_p_sdram; reg [CK_WIDTH-1:0] ddr3_ck_n_sdram; wire init_calib_complete; wire tg_compare_error; reg ddr_sys_clk_i; reg clk_ref_i; wire [DATA_WIDTH-1:0] ext_dout; wire [ADDR_WIDTH-1:0] ext_addr; wire ext_valid; wire ext_sof; wire ext_eof; wire ui_app_wdf_wren; wire [4*PAYLOAD_WIDTH-1:0] ui_app_wdf_data; wire [4*PAYLOAD_WIDTH/8-1:0] ui_app_wdf_mask; wire ui_app_wdf_end; wire [ADDR_WIDTH-1:0] ui_app_addr; wire [2:0] ui_app_cmd; wire ui_app_en; wire ui_app_rdy; wire ui_app_wdf_rdy; wire [4*PAYLOAD_WIDTH-1:0] ui_app_rd_data; wire ui_app_rd_data_end; wire ui_app_rd_data_valid; wire ui_clk_sync_rst; wire ui_clk_sync_rst_n; wire ui_clk; wire ui_phy_init_done; wire ui_app_req; wire ui_app_gnt; wire [DATA_WIDTH-1:0] dbg_ddr_rb_data; wire [ADDR_WIDTH-1:0] dbg_ddr_rb_addr; wire dbg_ddr_rb_valid; wire chk_data_err; wire [16-1:0] chk_data_err_cnt; wire chk_addr_err; wire [16-1:0] chk_addr_err_cnt; wire chk_end; wire chk_pass; wire sys_clk; wire sys_rstn; wire sys_rst; wire adc_clk; wire adc_rstn; wire clk_200mhz; wire clk200mhz_rstn; wire ddr3_sys_clk; wire ddr3_sys_rstn; wire clk_ref; wire sda; wire scl; clk_rst cmp_clk_rst( .clk_sys_o(sys_clk), .clk_adc_o(adc_clk), .clk_100mhz_o(), .clk_200mhz_o(clk_200mhz), .sys_rstn_o(sys_rstn), .adc_rstn_o(adc_rstn), .clk100mhz_rstn_o(), .clk200mhz_rstn_o(clk200mhz_rstn) ); assign sys_rst = ~sys_rstn; assign clk_ref = clk_200mhz; assign ddr3_sys_clk = clk_200mhz; assign ddr3_sys_rstn = clk200mhz_rstn; WB_TEST_MASTER WB( .wb_clk (sys_clk) ); wb_acq_core #(.g_ddr_addr_width(ADDR_WIDTH), .g_addr_width(ADDR_WIDTH), .g_sim_readback(1) ) dut( .fs_clk_i (adc_clk), .fs_ce_i (1'b1), .fs_rst_n_i (adc_rstn), .sys_clk_i (sys_clk), .sys_rst_n_i (sys_rstn), .ext_clk_i (ui_clk), .ext_rst_n_i (ui_clk_sync_rst_n), .wb_adr_i (WB.wb_addr), .wb_dat_i (WB.wb_data_o), .wb_dat_o (WB.wb_data_i), .wb_cyc_i (WB.wb_cyc), .wb_sel_i (WB.wb_bwsel), .wb_stb_i (WB.wb_stb), .wb_we_i (WB.wb_we), .wb_ack_o (WB.wb_ack_i), .wb_err_o (), .wb_rty_o (), .wb_stall_o (), .data_i (data_test), .dvalid_i (data_test_valid), .ext_trig_i (trigger_test), .dpram_dout_o (), .dpram_valid_o (), .ext_dout_o (ext_dout), .ext_valid_o (ext_valid), .ext_addr_o (ext_addr), .ext_sof_o (ext_sof), .ext_eof_o (ext_eof), .ext_dreq_o (ext_dreq), .ext_stall_o (ext_stall), .ui_app_addr_o (ui_app_addr), .ui_app_cmd_o (ui_app_cmd), .ui_app_en_o (ui_app_en), .ui_app_rdy_i (ui_app_rdy), .ui_app_wdf_data_o (ui_app_wdf_data), .ui_app_wdf_end_o (ui_app_wdf_end), .ui_app_wdf_mask_o (ui_app_wdf_mask), .ui_app_wdf_wren_o (ui_app_wdf_wren), .ui_app_wdf_rdy_i (ui_app_wdf_rdy), .ui_app_rd_data_i (ui_app_rd_data), .ui_app_rd_data_end_i (ui_app_rd_data_end), .ui_app_rd_data_valid_i (ui_app_rd_data_valid), .ui_app_req_o (ui_app_req), .ui_app_gnt_i (ui_app_gnt), .dbg_ddr_rb_data_o (dbg_ddr_rb_data), .dbg_ddr_rb_addr_o (dbg_ddr_rb_addr), .dbg_ddr_rb_valid_o (dbg_ddr_rb_valid) ); assign ui_app_gnt = 1'b1; data_checker #(.g_addr_width(ADDR_WIDTH), .g_data_width(DATA_WIDTH), .g_fifo_size(DATA_CHECK_FIFO_SIZE) ) cmp_data_checker( .ext_clk_i (ui_clk), .ext_rst_n_i (ui_clk_sync_rst_n & test_in_progress), .exp_din_i (ext_dout), .exp_addr_i (ext_addr), .exp_valid_i (ext_valid & ~ext_stall), .act_din_i (dbg_ddr_rb_data), .act_addr_i (dbg_ddr_rb_addr), .act_valid_i (dbg_ddr_rb_valid), .lmt_pkt_size_i (lmt_pkt_size), .lmt_shots_nb_i (n_shots), .lmt_valid_i (test_in_progress), .chk_data_err_o (chk_data_err), .chk_data_err_cnt_o (chk_data_err_cnt), .chk_addr_err_o (chk_addr_err), .chk_addr_err_cnt_o (chk_addr_err_cnt), .chk_end_o (chk_end), .chk_pass_o (chk_pass) ); ddr_v6 #( .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), .RST_ACT_LOW (RST_ACT_LOW) ) cmp_ddr_v6( .sys_clk (ddr3_sys_clk), .sys_rst (ddr3_sys_rstn), .clk_ref (clk_ref), .ddr3_dq (ddr3_dq_fpga), .ddr3_dm (ddr3_dm_fpga), .ddr3_addr (ddr3_addr_fpga), .ddr3_ba (ddr3_ba_fpga), .ddr3_ras_n (ddr3_ras_n_fpga), .ddr3_cas_n (ddr3_cas_n_fpga), .ddr3_we_n (ddr3_we_n_fpga), .ddr3_reset_n (ddr3_reset_n), .ddr3_cs_n (ddr3_cs_n_fpga), .ddr3_odt (ddr3_odt_fpga), .ddr3_cke (ddr3_cke_fpga), .ddr3_dqs_p (ddr3_dqs_p_fpga), .ddr3_dqs_n (ddr3_dqs_n_fpga), .ddr3_ck_p (ddr3_ck_p_fpga), .ddr3_ck_n (ddr3_ck_n_fpga), .app_wdf_wren (ui_app_wdf_wren), .app_wdf_data (ui_app_wdf_data), .app_wdf_mask (ui_app_wdf_mask), .app_wdf_end (ui_app_wdf_end), .app_addr (ui_app_addr), .app_cmd (ui_app_cmd), .app_en (ui_app_en), .app_rdy (ui_app_rdy), .app_wdf_rdy (ui_app_wdf_rdy), .app_rd_data (ui_app_rd_data), .app_rd_data_end (ui_app_rd_data_end), .app_rd_data_valid (ui_app_rd_data_valid), .ui_clk_sync_rst (ui_clk_sync_rst), .ui_clk (ui_clk), .phy_init_done (ui_phy_init_done) ); assign ui_clk_sync_rst_n = ~ui_clk_sync_rst; genvar r,i,dqs_x; generate for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk if(MEMORY_WIDTH == 16) begin: mem_16 if(DQ_WIDTH/16) begin: gen_mem for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem ddr3_model u_comp_ddr3 ( .rst_n (ddr3_reset_n), .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]), .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]), .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .ras_n (ddr3_ras_n_sdram), .cas_n (ddr3_cas_n_sdram), .we_n (ddr3_we_n_sdram), .dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]), .ba (ddr3_ba_sdram), .addr (ddr3_addr_sdram), .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]), .dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]), .dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]), .tdqs_n (), .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]) ); end end if (DQ_WIDTH%16) begin: gen_mem_extrabits ddr3_model u_comp_ddr3 ( .rst_n (ddr3_reset_n), .ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]), .ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]), .cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]), .cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]), .ras_n (ddr3_ras_n_sdram), .cas_n (ddr3_cas_n_sdram), .we_n (ddr3_we_n_sdram), .dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}), .ba (ddr3_ba_sdram), .addr (ddr3_addr_sdram), .dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)], ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}), .dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1], ddr3_dqs_p_sdram[DQS_WIDTH-1]}), .dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1], ddr3_dqs_n_sdram[DQS_WIDTH-1]}), .tdqs_n (), .odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]) ); end end if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4 for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem ddr3_model u_comp_ddr3 ( .rst_n (ddr3_reset_n), .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]), .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]), .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]), .ras_n (ddr3_ras_n_sdram), .cas_n (ddr3_cas_n_sdram), .we_n (ddr3_we_n_sdram), .dm_tdqs (ddr3_dm_sdram[i]), .ba (ddr3_ba_sdram), .addr (ddr3_addr_sdram), .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]), .dqs (ddr3_dqs_p_sdram[i]), .dqs_n (ddr3_dqs_n_sdram[i]), .tdqs_n (), .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]) ); end end end endgenerate always @( * ) begin ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga; ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga; ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga; ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga; ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga; ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga; ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga; ddr3_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga; ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga; ddr3_odt_sdram <= #(TPROP_PCB_CTRL) ddr3_odt_fpga; ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga; end assign ddr3_dm_sdram = ddr3_dm_sdram_tmp; assign init_calib_complete = ui_phy_init_done; genvar dqwd; generate for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay WireDelay # ( .Delay_g (TPROP_PCB_DATA), .Delay_rd (TPROP_PCB_DATA_RD), .ERR_INSERT ("OFF") ) u_delay_dq ( .A (ddr3_dq_fpga[dqwd]), .B (ddr3_dq_sdram[dqwd]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); end WireDelay # ( .Delay_g (TPROP_PCB_DATA), .Delay_rd (TPROP_PCB_DATA_RD), .ERR_INSERT (ECC) ) u_delay_dq_0 ( .A (ddr3_dq_fpga[0]), .B (ddr3_dq_sdram[0]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); endgenerate genvar dqswd; generate for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay WireDelay # ( .Delay_g (TPROP_DQS), .Delay_rd (TPROP_DQS_RD), .ERR_INSERT ("OFF") ) u_delay_dqs_p ( .A (ddr3_dqs_p_fpga[dqswd]), .B (ddr3_dqs_p_sdram[dqswd]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); WireDelay # ( .Delay_g (TPROP_DQS), .Delay_rd (TPROP_DQS_RD), .ERR_INSERT ("OFF") ) u_delay_dqs_n ( .A (ddr3_dqs_n_fpga[dqswd]), .B (ddr3_dqs_n_sdram[dqswd]), .reset (sys_rst_n), .phy_init_done (ui_phy_init_done) ); end endgenerate initial begin data_gen_start = 1'b0; test_in_progress = 1'b0; trigger_test = 1'b0; min_wait_gnt = 0; max_wait_gnt = 0; $display("-----------------------------------"); $display("@%0d: Simulation of BPM ACQ FSM starting!", $time); $display("-----------------------------------"); $display("-----------------------------------"); $display("@%0d: Initialization Begin", $time); $display("-----------------------------------"); $display("-----------------------------------"); $display("@%0d: Waiting for all resets...", $time); $display("-----------------------------------"); wait (WB.ready); wait (sys_rstn); wait (adc_rstn); $display("@%0d: Reset done!", $time); $display("-----------------------------------"); $display("@%0d: Waiting for Memory initilization/calibration...", $time); $display("-----------------------------------"); wait (init_calib_complete); $display("@%0d: Memory initialization/calibration done!", $time); data_gen_start = 1'b1; @(posedge sys_clk); $display("-------------------------------------"); $display("@%0d: Initialization Done!", $time); $display("-------------------------------------"); test_id = 1; n_shots = 16'h0001; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; stop_on_error = 1'b1; data_valid_prob = 1.0; min_wait_gnt = 32; max_wait_gnt = 128; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 2; n_shots = 16'h0001; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.7; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 3; n_shots = 16'h0001; pre_trig_samples = 32'h00000100; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.7; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 4; n_shots = 16'h0001; pre_trig_samples = 32'h00001000; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.5; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 5; n_shots = 16'h0002; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.7; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 6; n_shots = 16'h0010; pre_trig_samples = 32'h00000010; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.6; min_wait_gnt = 64; max_wait_gnt = 128; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); test_id = 7; n_shots = 16'h0010; pre_trig_samples = 32'h00000020; post_trig_samples = 32'h00000000; ddr3_start_addr = 32'h00000000; lmt_pkt_size = pre_trig_samples + post_trig_samples; skip_trig = 1'b1; wait_finish = 1'b1; data_valid_prob = 0.6; min_wait_gnt = 128; max_wait_gnt = 512; wb_acq(test_id, n_shots, pre_trig_samples, post_trig_samples, ddr3_start_addr, skip_trig, wait_finish, stop_on_error, data_valid_prob); $display("Simulation Done!"); $display("All Tests Passed!"); $display("---------------------------------------------"); $finish; end always @(posedge adc_clk) begin if (data_gen_start) begin if (data_test_valid_t) data_test <= data_test + 1; data_test_valid_t <= f_gen_data_rdy_gen(data_valid_threshold); data_test_valid <= data_test_valid_t; end else begin data_test <= 'h0; data_test_valid <= 1'b0; data_test_valid_t <= 1'b0; end end function [`DATA_TEST_WIDTH-1:0] f_data_gen; input integer max_size; begin f_data_gen = {$random} % max_size; end endfunction function f_gen_data_rdy_gen; input real prob; real temp; begin f_gen_data_rdy_gen = f_gen_bit_one(prob); end endfunction function f_gen_data_stall; input real prob; real temp; begin f_gen_data_stall = f_gen_bit_one(1.0-prob); end endfunction function f_gen_bit_one; input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp <= prob) f_gen_bit_one = 1'b1; else f_gen_bit_one = 1'b0; end endfunction function integer f_gen_lmt; input integer min; input integer max; real temp; begin f_gen_lmt = ({$random} % (max-min) + min); end endfunction task wb_busy_wait; input [`WB_ADDRESS_BUS_WIDTH-1:0] addr; input [`WB_DATA_BUS_WIDTH-1:0] mask; input [`WB_DATA_BUS_WIDTH-1:0] offset; input verbose; reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg; begin WB.monitor_bus(1'b0); WB.verbose(1'b0); WB.read32(addr, tmp_reg); while (((tmp_reg & mask) >> offset) != 'h1) begin if (verbose) $write("."); @(posedge sys_clk); WB.read32(addr, tmp_reg); end WB.monitor_bus(1'b1); WB.verbose(1'b1); end endtask task wb_acq; input integer test_id; input [15:0] n_shots; input [31:0] pre_trig_samples; input [31:0] post_trig_samples; input [31:0] ddr3_start_addr; input skip_trig; input wait_finish; input stop_on_error; input real data_valid_prob; reg [31:0] acq_core_fsm_ctl_reg; begin $display("#############################"); $display("######## TEST #%03d ######", test_id); $display("#############################"); $display("## Number of shots = %03d", n_shots); $display("## Number of pre samples = %03d", pre_trig_samples); $display("## Skip trigger = %d", skip_trig); $display("## Number of post samples = %03d", post_trig_samples); $display("Setting throttling parameters scenario"); $display("Setting source data valid input probability = %.2f%%", data_valid_prob*100); test_in_progress = 1'b1; @(posedge sys_clk); data_valid_threshold = data_valid_prob; $display("Setting # of shots to %03d", n_shots); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET)); $display("Setting # of pre-trigger to %03d", pre_trig_samples); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples)); $display("Setting # of pos-trigger to %03d", post_trig_samples); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples)); acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET; $display("Setting skip trigger parameter to %d", skip_trig); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg); $display("Setting DDR3 start address for the next acquistion %d", skip_trig); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr); acq_core_fsm_ctl_reg = acq_core_fsm_ctl_reg | (32'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET; $display("Starting acquisition... "); @(posedge sys_clk); WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg); if (wait_finish) begin $display("Waiting until all data have been acquired...\n"); @(posedge sys_clk); wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE, `ACQ_CORE_STA_DDR3_TRANS_DONE_OFFSET, 1'b1); end $display("Done!"); wait (chk_end); $display("Data checker detected a total of %03d data mismatch errors", chk_data_err_cnt); $display("Data checker detected a total of %03d addr mismatch errors", chk_addr_err_cnt); if (stop_on_error & (chk_data_err | chk_addr_err)) begin $display("TEST #%03d NOT PASS!", test_id); $finish; end $display("\n"); @(posedge sys_clk); test_in_progress = 1'b0; repeat (2) begin @(posedge sys_clk); end end endtask endmodule

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v

wb_acq_core_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:26: Cannot find include file: regs/wb_acq_core_regs.vh\n`include "regs/wb_acq_core_regs.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:741: Unsupported: wait statements\n wait (WB.ready);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:742: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:743: Unsupported: wait statements\n wait (adc_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:751: Unsupported: wait statements\n wait (init_calib_complete);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:757: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:950: Define or directive not defined: \'`DATA_TEST_WIDTH\'\n function [`DATA_TEST_WIDTH-1:0] f_data_gen;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1008: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1009: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] mask;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1010: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] offset;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1013: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1024: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1064: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1071: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ADDR_ACQ_CORE_SHOTS\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ACQ_CORE_SHOTS_NB_OFFSET\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1075: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`ADDR_ACQ_CORE_PRE_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1079: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`ADDR_ACQ_CORE_POST_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET\'\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1086: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1090: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`ADDR_ACQ_CORE_DDR3_START_ADDR\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_START_ACQ_OFFSET\'\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1098: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1103: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: Define or directive not defined: \'`ADDR_ACQ_CORE_STA\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: syntax error, unexpected >>, expecting \')\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function [`DATA_TEST_WIDTH-1:0] f_data_gen; input integer max_size; begin f_data_gen = {$random} % max_size; end endfunction

function [`DATA_TEST_WIDTH-1:0] f_data_gen;

input integer max_size; begin f_data_gen = {$random} % max_size; end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v

wb_acq_core_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:26: Cannot find include file: regs/wb_acq_core_regs.vh\n`include "regs/wb_acq_core_regs.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:741: Unsupported: wait statements\n wait (WB.ready);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:742: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:743: Unsupported: wait statements\n wait (adc_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:751: Unsupported: wait statements\n wait (init_calib_complete);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:757: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:950: Define or directive not defined: \'`DATA_TEST_WIDTH\'\n function [`DATA_TEST_WIDTH-1:0] f_data_gen;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1008: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1009: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] mask;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1010: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] offset;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1013: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1024: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1064: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1071: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ADDR_ACQ_CORE_SHOTS\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ACQ_CORE_SHOTS_NB_OFFSET\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1075: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`ADDR_ACQ_CORE_PRE_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1079: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`ADDR_ACQ_CORE_POST_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET\'\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1086: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1090: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`ADDR_ACQ_CORE_DDR3_START_ADDR\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_START_ACQ_OFFSET\'\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1098: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1103: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: Define or directive not defined: \'`ADDR_ACQ_CORE_STA\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: syntax error, unexpected >>, expecting \')\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function f_gen_data_rdy_gen; input real prob; real temp; begin f_gen_data_rdy_gen = f_gen_bit_one(prob); end endfunction

function f_gen_data_rdy_gen;

input real prob; real temp; begin f_gen_data_rdy_gen = f_gen_bit_one(prob); end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v

wb_acq_core_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:26: Cannot find include file: regs/wb_acq_core_regs.vh\n`include "regs/wb_acq_core_regs.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:741: Unsupported: wait statements\n wait (WB.ready);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:742: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:743: Unsupported: wait statements\n wait (adc_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:751: Unsupported: wait statements\n wait (init_calib_complete);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:757: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:950: Define or directive not defined: \'`DATA_TEST_WIDTH\'\n function [`DATA_TEST_WIDTH-1:0] f_data_gen;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1008: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1009: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] mask;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1010: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] offset;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1013: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1024: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1064: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1071: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ADDR_ACQ_CORE_SHOTS\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ACQ_CORE_SHOTS_NB_OFFSET\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1075: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`ADDR_ACQ_CORE_PRE_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1079: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`ADDR_ACQ_CORE_POST_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET\'\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1086: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1090: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`ADDR_ACQ_CORE_DDR3_START_ADDR\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_START_ACQ_OFFSET\'\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1098: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1103: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: Define or directive not defined: \'`ADDR_ACQ_CORE_STA\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: syntax error, unexpected >>, expecting \')\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function f_gen_data_stall; input real prob; real temp; begin f_gen_data_stall = f_gen_bit_one(1.0-prob); end endfunction

function f_gen_data_stall;

input real prob; real temp; begin f_gen_data_stall = f_gen_bit_one(1.0-prob); end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v

wb_acq_core_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:26: Cannot find include file: regs/wb_acq_core_regs.vh\n`include "regs/wb_acq_core_regs.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:741: Unsupported: wait statements\n wait (WB.ready);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:742: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:743: Unsupported: wait statements\n wait (adc_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:751: Unsupported: wait statements\n wait (init_calib_complete);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:757: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:950: Define or directive not defined: \'`DATA_TEST_WIDTH\'\n function [`DATA_TEST_WIDTH-1:0] f_data_gen;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1008: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1009: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] mask;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1010: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] offset;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1013: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1024: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1064: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1071: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ADDR_ACQ_CORE_SHOTS\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ACQ_CORE_SHOTS_NB_OFFSET\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1075: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`ADDR_ACQ_CORE_PRE_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1079: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`ADDR_ACQ_CORE_POST_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET\'\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1086: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1090: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`ADDR_ACQ_CORE_DDR3_START_ADDR\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_START_ACQ_OFFSET\'\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1098: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1103: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: Define or directive not defined: \'`ADDR_ACQ_CORE_STA\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: syntax error, unexpected >>, expecting \')\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function f_gen_bit_one; input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp <= prob) f_gen_bit_one = 1'b1; else f_gen_bit_one = 1'b0; end endfunction

function f_gen_bit_one;

input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp <= prob) f_gen_bit_one = 1'b1; else f_gen_bit_one = 1'b0; end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v

wb_acq_core_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:26: Cannot find include file: regs/wb_acq_core_regs.vh\n`include "regs/wb_acq_core_regs.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam c_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:741: Unsupported: wait statements\n wait (WB.ready);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:742: Unsupported: wait statements\n wait (sys_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:743: Unsupported: wait statements\n wait (adc_rstn);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:751: Unsupported: wait statements\n wait (init_calib_complete);\n ^~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:757: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:950: Define or directive not defined: \'`DATA_TEST_WIDTH\'\n function [`DATA_TEST_WIDTH-1:0] f_data_gen;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1008: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1009: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] mask;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1010: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n input [`WB_DATA_BUS_WIDTH-1:0] offset;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1013: Define or directive not defined: \'`WB_DATA_BUS_WIDTH\'\n reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1024: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1064: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1071: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ADDR_ACQ_CORE_SHOTS\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1072: Define or directive not defined: \'`ACQ_CORE_SHOTS_NB_OFFSET\'\n WB.write32(`ADDR_ACQ_CORE_SHOTS >> `WB_WORD_ACC, (n_shots << `ACQ_CORE_SHOTS_NB_OFFSET));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1075: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`ADDR_ACQ_CORE_PRE_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1076: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_PRE_SAMPLES >> `WB_WORD_ACC, (pre_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1079: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`ADDR_ACQ_CORE_POST_SAMPLES\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1080: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_POST_SAMPLES >> `WB_WORD_ACC, (post_trig_samples));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET\'\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n acq_core_fsm_ctl_reg = (skip_trig) << `ACQ_CORE_CTL_FSM_ACQ_NOW_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1086: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1087: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1090: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`ADDR_ACQ_CORE_DDR3_START_ADDR\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1091: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_DDR3_START_ADDR >> `WB_WORD_ACC, ddr3_start_addr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: Define or directive not defined: \'`ACQ_CORE_CTL_FSM_START_ACQ_OFFSET\'\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1095: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n (32\'h00000001) << `ACQ_CORE_CTL_FSM_START_ACQ_OFFSET;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1098: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`ADDR_ACQ_CORE_CTL\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: syntax error, unexpected >>, expecting \')\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1099: Define or directive not defined: \'`WB_WORD_ACC\'\n WB.write32(`ADDR_ACQ_CORE_CTL >> `WB_WORD_ACC, acq_core_fsm_ctl_reg);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1103: syntax error, unexpected \'@\'\n @(posedge sys_clk);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: Define or directive not defined: \'`ADDR_ACQ_CORE_STA\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wb_acq_core_tb.v:1106: syntax error, unexpected >>, expecting \')\'\n wb_busy_wait(`ADDR_ACQ_CORE_STA >> `WB_WORD_ACC, `ACQ_CORE_STA_DDR3_TRANS_DONE,\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function integer f_gen_lmt; input integer min; input integer max; real temp; begin f_gen_lmt = ({$random} % (max-min) + min); end endfunction

function integer f_gen_lmt;

input integer min; input integer max; real temp; begin f_gen_lmt = ({$random} % (max-min) + min); end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v

clk_rst.v

v

[]

[]

[]

[(38, 81)]

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:1: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/timescale.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/timescale.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:2: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:13: Define or directive not defined: \'`CLK_SYS_PERIOD\'\n parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:13: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:14: Define or directive not defined: \'`CLK_ADC_PERIOD\'\n parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:14: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:16: Define or directive not defined: \'`CLK_100MHZ_PERIOD\'\n localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:17: Define or directive not defined: \'`CLK_200MHZ_PERIOD\'\n localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:37: Define or directive not defined: \'`RST_SYS_DELAY\'\n #(`RST_SYS_DELAY)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n #(`RST_SYS_DELAY)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:42: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:43: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o;\n ^\n%Error: Exiting due to 12 error(s), 4 warning(s)\n'

module

module clk_rst( clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o, rstn_o ); parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD; parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD; localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD; localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD; output reg clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o; output reg rstn_o; initial begin clk_sys_o = 0; clk_adc_o = 0; clk_100mhz_o = 0; clk_200mhz_o = 0; rstn_o = 0; #(`RST_SYS_DELAY) rstn_o = 1; end always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o; always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o; always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o; always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o; endmodule

module clk_rst( clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o, rstn_o );

parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD; parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD; localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD; localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD; output reg clk_sys_o, clk_adc_o, clk_100mhz_o, clk_200mhz_o; output reg rstn_o; initial begin clk_sys_o = 0; clk_adc_o = 0; clk_100mhz_o = 0; clk_200mhz_o = 0; rstn_o = 0; #(`RST_SYS_DELAY) rstn_o = 1; end always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o; always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o; always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o; always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o; endmodule

data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v

wb_fmc516_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:27: Cannot find include file: wb_fmc516_regs.vh\n`include "wb_fmc516_regs.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:69: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:130: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:135: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:144: syntax error, unexpected \'@\'\n repeat (6) @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:154: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:161: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:165: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:169: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:173: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:179: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: Define or directive not defined: \'`ADDR_FMC516_CH0_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: Define or directive not defined: \'`ADDR_FMC516_ADC_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY_OFFSET\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:431: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:438: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:441: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:442: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:451: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:458: syntax error, unexpected \'=\', expecting IDENTIFIER\n adc_data_valid_gen = 1\'b1;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

module

module wb_fmc516_tb; wire clk_sys, clk_adc; wire clk_100mhz, clk_200mhz; wire rstn; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n; reg adc_data_valid; localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1; localparam adc_gen_threshold = 0.5; localparam g_granularity = 4; localparam g_after_reset_delay = 16; localparam CLASSIC = 0; localparam PIPELINED = 1; localparam BYTE = 0; localparam WORD = 1; localparam TEST_DATA = 32'hcababaee; reg zero_bit = 1'b0; reg one_bit = 1'b1; reg spi_busy = 1'b0; reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out; reg sys_spi_datas_reg = 1'b0; reg [32-1 : 0]sys_spi_datap_reg = 'h0; reg sys_spi_data_en = 1'b0; wire sys_spi_data; wire sys_spi_data_b; wire sys_spi_cs_0; wire sys_spi_cs_1; wire sys_spi_cs_2; wire sys_spi_cs_3; wire sys_spi_miosio_oe_n; wire sys_spi_dout; wire sys_spi_din; integer i; clk_rst cmp_rst( .clk_sys_o(clk_sys), .clk_adc_o(clk_adc), .clk_100mhz_o(clk_100mhz), .clk_200mhz_o(clk_200mhz), .rstn_o(rstn) ); WB_TEST_MASTER cmp_wishbone_bfm(.wb_clk(clk_100mhz)); assign sys_spi_din = sys_spi_data_en ? sys_spi_datas_reg : 1'bz; initial begin wb_fmc516_tb.cmp_wishbone_bfm.verbose(1); wb_fmc516_tb.cmp_wishbone_bfm.monitor_bus(1); adc_ch0_data_p <= 'h0; adc_ch1_data_p <= 'h0; adc_ch2_data_p <= 'h0; adc_ch3_data_p <= 'h0; adc_data_valid <= 'h0; @(posedge clk_sys); while (!rstn) begin $display("@%0d: Waiting for reset completion...", $time); @(posedge clk_sys); end $display("@%0d: Reset and MMCM done!", $time); while (!fmc_mmcm_lock) begin $display("@%0d: Waiting for MMCM lock...", $time); repeat (6) @(posedge clk_sys); end $display("@%0d: MMCM locked!", $time); $display("----------------------------------------"); $display("@%0d: TESTING SPI COMMUNICATION", $time); $display("----------------------------------------"); @(posedge clk_sys); $display("---------"); $display("@%0d: Writing data: FPGA -> external...", $time); $display("---------"); cmp_wishbone_bfm.write32(32'h00000200, 32'hdeadbeef); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000200 + (4 << 2), 32'h00006420); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000200 + (6 << 2), 32'h00000001); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000200 + (4 << 2), 32'h00006520); @(posedge clk_sys); wait_spi_busy(); repeat (8) @(posedge clk_sys); @(posedge clk_sys); $display("---------"); $display("@%0d: Reading data: external -> FPGA...", $time); $display("---------"); $display("----------------------------------------"); $display("@%0d: START OF SIMPLE DELAY TEST", $time); $display("----------------------------------------"); cmp_wishbone_bfm.write32(32'h00000000 + `ADDR_FMC516_CH0_CTL, (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000000 + `ADDR_FMC516_ADC_CTL, (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY); @(posedge clk_sys); $display("----------------------------------------"); $display("@%0d: END OF SIMPLE DELAY TEST", $time); $display("----------------------------------------"); end wb_fmc516 #( .g_fpga_device("VIRTEX6"), .g_interface_mode(CLASSIC), .g_address_granularity(BYTE), .g_use_clk_chains(4'b0011), .g_use_data_chains(4'b1111), .g_packet_size(32), .g_sim(1)) cmp_wb_fmc516 ( .sys_clk_i (clk_sys), .sys_rst_n_i (rstn), .sys_clk_200Mhz_i (clk_200mhz), .wb_adr_i (cmp_wishbone_bfm.wb_addr), .wb_dat_i (cmp_wishbone_bfm.wb_data_o), .wb_dat_o (cmp_wishbone_bfm.wb_data_i), .wb_sel_i (cmp_wishbone_bfm.wb_bwsel), .wb_we_i (cmp_wishbone_bfm.wb_we), .wb_cyc_i (cmp_wishbone_bfm.wb_cyc), .wb_stb_i (cmp_wishbone_bfm.wb_stb), .wb_ack_o (cmp_wishbone_bfm.wb_ack_i), .wb_err_o (), .wb_rty_o (), .wb_stall_o (), .sys_i2c_scl_b (), .sys_i2c_sda_b (), .adc_clk0_p_i (clk_adc), .adc_clk0_n_i (~clk_adc), .adc_clk1_p_i (clk_adc), .adc_clk1_n_i (~clk_adc), .adc_clk2_p_i (clk_adc), .adc_clk2_n_i (~clk_adc), .adc_clk3_p_i (clk_adc), .adc_clk3_n_i (~clk_adc), .adc_data_ch0_p_i (adc_ch0_data_p), .adc_data_ch0_n_i (toggle_adc_data(adc_ch0_data_n)), .adc_data_ch1_p_i (adc_ch1_data_p), .adc_data_ch1_n_i (toggle_adc_data(adc_ch1_data_n)), .adc_data_ch2_p_i (adc_ch2_data_p), .adc_data_ch2_n_i (toggle_adc_data(adc_ch2_data_n)), .adc_data_ch3_p_i (adc_ch3_data_p), .adc_data_ch3_n_i (toggle_adc_data(adc_ch3_data_n)), .adc_clk_div_rst_p_o (), .adc_clk_div_rst_n_o (), .fmc_leds_o (), .sys_spi_clk_o (sys_spi_clk), .sys_spi_dout_o (sys_spi_dout), .sys_spi_din_i (sys_spi_din), .sys_spi_cs_adc0_n_o (sys_spi_cs_0), .sys_spi_cs_adc1_n_o (sys_spi_cs_1), .sys_spi_cs_adc2_n_o (sys_spi_cs_2), .sys_spi_cs_adc3_n_o (sys_spi_cs_3), .sys_spi_miosio_oe_n_o (sys_spi_miosio_oe_n), .m2c_trig_p_i (zero_bit), .m2c_trig_n_i (zero_bit), .c2m_trig_p_o (), .c2m_trig_n_o (), .lmk_lock_i (one_bit), .lmk_sync_o (), .lmk_uwire_latch_en_o (), .lmk_uwire_data_o (), .lmk_uwire_clock_o (), .vcxo_i2c_sda_b (), .vcxo_i2c_scl_o (), .vcxo_pd_l_o (), .fmc_id_dq_b (), .fmc_key_dq_b (), .fmc_pwr_good_i (zero_bit), .fmc_clk_sel_o (), .fmc_reset_adcs_n_o (), .fmc_prsnt_m2c_l_i (zero_bit), .adc_clk_o (), .adc_data_o (), .adc_data_valid_o (), .trig_hw_o (), .trig_hw_i (zero_bit), .fmc_mmcm_lock_o (fmc_mmcm_lock), .fmc_lmk_lock_o (), .wbs_adr_o (), .wbs_dat_o (), .wbs_cyc_o (), .wbs_stb_o (), .wbs_we_o (), .wbs_sel_o (), .wbs_ack_i (4'h0), .wbs_stall_i (4'h0), .wbs_err_i (4'h0), .wbs_rty_i (4'h0), .adc_dly_reg_debug_o (), .fifo_debug_valid_o (), .fifo_debug_full_o (), .fifo_debug_empty_o () ); assign sys_spi_data_b = (~sys_spi_miosio_oe_n) ? sys_spi_dout : 1'bz; assign sys_spi_din = sys_spi_data_b; always @(posedge clk_adc) begin adc_ch0_data_p <= adc_data_gen(adc_data_max); adc_ch1_data_p <= adc_data_gen(adc_data_max); adc_ch2_data_p <= adc_data_gen(adc_data_max); adc_ch3_data_p <= adc_data_gen(adc_data_max); adc_ch0_data_n <= toggle_adc_data(adc_ch0_data_p); adc_ch1_data_n <= toggle_adc_data(adc_ch1_data_p); adc_ch2_data_n <= toggle_adc_data(adc_ch2_data_p); adc_ch3_data_n <= toggle_adc_data(adc_ch3_data_p); adc_data_valid <= adc_data_valid_gen(adc_gen_threshold); end function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen; input integer max_size; begin adc_data_gen = {$random} % max_size; end endfunction function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data; input [`ADC_DATA_WIDTH/2 -1 : 0] data; integer i; begin for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin toggle_adc_data[i] = ~data[i]; end end endfunction function adc_data_valid_gen; input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp > prob) adc_data_valid_gen = 1'b1; else adc_data_valid_gen = 1'b0; end endfunction task wait_spi_busy(); begin cmp_wishbone_bfm.read32(32'h00000200 + (4 << 2), data_out); @(posedge clk_sys); $display("@%0d: Waiting for SPI...", $time); while (data_out & (1 << 8)) begin cmp_wishbone_bfm.read32(32'h00000200 + (4 << 2), data_out); repeat (16) @(posedge clk_sys); $display("@%0d: Waiting for SPI...", $time); end $display("@%0d: SPI completed its transcation", $time); end endtask endmodule

module wb_fmc516_tb;

wire clk_sys, clk_adc; wire clk_100mhz, clk_200mhz; wire rstn; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n; reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n; reg adc_data_valid; localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1; localparam adc_gen_threshold = 0.5; localparam g_granularity = 4; localparam g_after_reset_delay = 16; localparam CLASSIC = 0; localparam PIPELINED = 1; localparam BYTE = 0; localparam WORD = 1; localparam TEST_DATA = 32'hcababaee; reg zero_bit = 1'b0; reg one_bit = 1'b1; reg spi_busy = 1'b0; reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out; reg sys_spi_datas_reg = 1'b0; reg [32-1 : 0]sys_spi_datap_reg = 'h0; reg sys_spi_data_en = 1'b0; wire sys_spi_data; wire sys_spi_data_b; wire sys_spi_cs_0; wire sys_spi_cs_1; wire sys_spi_cs_2; wire sys_spi_cs_3; wire sys_spi_miosio_oe_n; wire sys_spi_dout; wire sys_spi_din; integer i; clk_rst cmp_rst( .clk_sys_o(clk_sys), .clk_adc_o(clk_adc), .clk_100mhz_o(clk_100mhz), .clk_200mhz_o(clk_200mhz), .rstn_o(rstn) ); WB_TEST_MASTER cmp_wishbone_bfm(.wb_clk(clk_100mhz)); assign sys_spi_din = sys_spi_data_en ? sys_spi_datas_reg : 1'bz; initial begin wb_fmc516_tb.cmp_wishbone_bfm.verbose(1); wb_fmc516_tb.cmp_wishbone_bfm.monitor_bus(1); adc_ch0_data_p <= 'h0; adc_ch1_data_p <= 'h0; adc_ch2_data_p <= 'h0; adc_ch3_data_p <= 'h0; adc_data_valid <= 'h0; @(posedge clk_sys); while (!rstn) begin $display("@%0d: Waiting for reset completion...", $time); @(posedge clk_sys); end $display("@%0d: Reset and MMCM done!", $time); while (!fmc_mmcm_lock) begin $display("@%0d: Waiting for MMCM lock...", $time); repeat (6) @(posedge clk_sys); end $display("@%0d: MMCM locked!", $time); $display("----------------------------------------"); $display("@%0d: TESTING SPI COMMUNICATION", $time); $display("----------------------------------------"); @(posedge clk_sys); $display("---------"); $display("@%0d: Writing data: FPGA -> external...", $time); $display("---------"); cmp_wishbone_bfm.write32(32'h00000200, 32'hdeadbeef); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000200 + (4 << 2), 32'h00006420); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000200 + (6 << 2), 32'h00000001); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000200 + (4 << 2), 32'h00006520); @(posedge clk_sys); wait_spi_busy(); repeat (8) @(posedge clk_sys); @(posedge clk_sys); $display("---------"); $display("@%0d: Reading data: external -> FPGA...", $time); $display("---------"); $display("----------------------------------------"); $display("@%0d: START OF SIMPLE DELAY TEST", $time); $display("----------------------------------------"); cmp_wishbone_bfm.write32(32'h00000000 + `ADDR_FMC516_CH0_CTL, (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY); @(posedge clk_sys); cmp_wishbone_bfm.write32(32'h00000000 + `ADDR_FMC516_ADC_CTL, (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY); @(posedge clk_sys); $display("----------------------------------------"); $display("@%0d: END OF SIMPLE DELAY TEST", $time); $display("----------------------------------------"); end wb_fmc516 #( .g_fpga_device("VIRTEX6"), .g_interface_mode(CLASSIC), .g_address_granularity(BYTE), .g_use_clk_chains(4'b0011), .g_use_data_chains(4'b1111), .g_packet_size(32), .g_sim(1)) cmp_wb_fmc516 ( .sys_clk_i (clk_sys), .sys_rst_n_i (rstn), .sys_clk_200Mhz_i (clk_200mhz), .wb_adr_i (cmp_wishbone_bfm.wb_addr), .wb_dat_i (cmp_wishbone_bfm.wb_data_o), .wb_dat_o (cmp_wishbone_bfm.wb_data_i), .wb_sel_i (cmp_wishbone_bfm.wb_bwsel), .wb_we_i (cmp_wishbone_bfm.wb_we), .wb_cyc_i (cmp_wishbone_bfm.wb_cyc), .wb_stb_i (cmp_wishbone_bfm.wb_stb), .wb_ack_o (cmp_wishbone_bfm.wb_ack_i), .wb_err_o (), .wb_rty_o (), .wb_stall_o (), .sys_i2c_scl_b (), .sys_i2c_sda_b (), .adc_clk0_p_i (clk_adc), .adc_clk0_n_i (~clk_adc), .adc_clk1_p_i (clk_adc), .adc_clk1_n_i (~clk_adc), .adc_clk2_p_i (clk_adc), .adc_clk2_n_i (~clk_adc), .adc_clk3_p_i (clk_adc), .adc_clk3_n_i (~clk_adc), .adc_data_ch0_p_i (adc_ch0_data_p), .adc_data_ch0_n_i (toggle_adc_data(adc_ch0_data_n)), .adc_data_ch1_p_i (adc_ch1_data_p), .adc_data_ch1_n_i (toggle_adc_data(adc_ch1_data_n)), .adc_data_ch2_p_i (adc_ch2_data_p), .adc_data_ch2_n_i (toggle_adc_data(adc_ch2_data_n)), .adc_data_ch3_p_i (adc_ch3_data_p), .adc_data_ch3_n_i (toggle_adc_data(adc_ch3_data_n)), .adc_clk_div_rst_p_o (), .adc_clk_div_rst_n_o (), .fmc_leds_o (), .sys_spi_clk_o (sys_spi_clk), .sys_spi_dout_o (sys_spi_dout), .sys_spi_din_i (sys_spi_din), .sys_spi_cs_adc0_n_o (sys_spi_cs_0), .sys_spi_cs_adc1_n_o (sys_spi_cs_1), .sys_spi_cs_adc2_n_o (sys_spi_cs_2), .sys_spi_cs_adc3_n_o (sys_spi_cs_3), .sys_spi_miosio_oe_n_o (sys_spi_miosio_oe_n), .m2c_trig_p_i (zero_bit), .m2c_trig_n_i (zero_bit), .c2m_trig_p_o (), .c2m_trig_n_o (), .lmk_lock_i (one_bit), .lmk_sync_o (), .lmk_uwire_latch_en_o (), .lmk_uwire_data_o (), .lmk_uwire_clock_o (), .vcxo_i2c_sda_b (), .vcxo_i2c_scl_o (), .vcxo_pd_l_o (), .fmc_id_dq_b (), .fmc_key_dq_b (), .fmc_pwr_good_i (zero_bit), .fmc_clk_sel_o (), .fmc_reset_adcs_n_o (), .fmc_prsnt_m2c_l_i (zero_bit), .adc_clk_o (), .adc_data_o (), .adc_data_valid_o (), .trig_hw_o (), .trig_hw_i (zero_bit), .fmc_mmcm_lock_o (fmc_mmcm_lock), .fmc_lmk_lock_o (), .wbs_adr_o (), .wbs_dat_o (), .wbs_cyc_o (), .wbs_stb_o (), .wbs_we_o (), .wbs_sel_o (), .wbs_ack_i (4'h0), .wbs_stall_i (4'h0), .wbs_err_i (4'h0), .wbs_rty_i (4'h0), .adc_dly_reg_debug_o (), .fifo_debug_valid_o (), .fifo_debug_full_o (), .fifo_debug_empty_o () ); assign sys_spi_data_b = (~sys_spi_miosio_oe_n) ? sys_spi_dout : 1'bz; assign sys_spi_din = sys_spi_data_b; always @(posedge clk_adc) begin adc_ch0_data_p <= adc_data_gen(adc_data_max); adc_ch1_data_p <= adc_data_gen(adc_data_max); adc_ch2_data_p <= adc_data_gen(adc_data_max); adc_ch3_data_p <= adc_data_gen(adc_data_max); adc_ch0_data_n <= toggle_adc_data(adc_ch0_data_p); adc_ch1_data_n <= toggle_adc_data(adc_ch1_data_p); adc_ch2_data_n <= toggle_adc_data(adc_ch2_data_p); adc_ch3_data_n <= toggle_adc_data(adc_ch3_data_p); adc_data_valid <= adc_data_valid_gen(adc_gen_threshold); end function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen; input integer max_size; begin adc_data_gen = {$random} % max_size; end endfunction function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data; input [`ADC_DATA_WIDTH/2 -1 : 0] data; integer i; begin for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin toggle_adc_data[i] = ~data[i]; end end endfunction function adc_data_valid_gen; input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp > prob) adc_data_valid_gen = 1'b1; else adc_data_valid_gen = 1'b0; end endfunction task wait_spi_busy(); begin cmp_wishbone_bfm.read32(32'h00000200 + (4 << 2), data_out); @(posedge clk_sys); $display("@%0d: Waiting for SPI...", $time); while (data_out & (1 << 8)) begin cmp_wishbone_bfm.read32(32'h00000200 + (4 << 2), data_out); repeat (16) @(posedge clk_sys); $display("@%0d: Waiting for SPI...", $time); end $display("@%0d: SPI completed its transcation", $time); end endtask endmodule

data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v

wb_fmc516_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:27: Cannot find include file: wb_fmc516_regs.vh\n`include "wb_fmc516_regs.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:69: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:130: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:135: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:144: syntax error, unexpected \'@\'\n repeat (6) @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:154: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:161: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:165: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:169: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:173: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:179: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: Define or directive not defined: \'`ADDR_FMC516_CH0_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: Define or directive not defined: \'`ADDR_FMC516_ADC_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY_OFFSET\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:431: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:438: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:441: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:442: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:451: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:458: syntax error, unexpected \'=\', expecting IDENTIFIER\n adc_data_valid_gen = 1\'b1;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen; input integer max_size; begin adc_data_gen = {$random} % max_size; end endfunction

function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;

input integer max_size; begin adc_data_gen = {$random} % max_size; end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v

wb_fmc516_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:27: Cannot find include file: wb_fmc516_regs.vh\n`include "wb_fmc516_regs.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:69: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:130: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:135: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:144: syntax error, unexpected \'@\'\n repeat (6) @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:154: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:161: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:165: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:169: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:173: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:179: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: Define or directive not defined: \'`ADDR_FMC516_CH0_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: Define or directive not defined: \'`ADDR_FMC516_ADC_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY_OFFSET\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:431: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:438: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:441: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:442: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:451: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:458: syntax error, unexpected \'=\', expecting IDENTIFIER\n adc_data_valid_gen = 1\'b1;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data; input [`ADC_DATA_WIDTH/2 -1 : 0] data; integer i; begin for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin toggle_adc_data[i] = ~data[i]; end end endfunction

function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data;

input [`ADC_DATA_WIDTH/2 -1 : 0] data; integer i; begin for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin toggle_adc_data[i] = ~data[i]; end end endfunction

data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v

wb_fmc516_tb.v

v

[]

['general public license']

[]

None: at end of input

1: b'%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:20: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.v\n data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog,data/full_repos/permissive/98916810/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:22: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:24: Cannot find include file: wishbone_test_master.v\n`include "wishbone_test_master.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:27: Cannot find include file: wb_fmc516_regs.vh\n`include "wb_fmc516_regs.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:38: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:39: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:40: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:41: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_p;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:42: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch0_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:43: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch1_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:44: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch2_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:45: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n reg [`ADC_DATA_WIDTH/2-1:0] adc_ch3_data_n;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:69: Define or directive not defined: \'`WB_ADDRESS_BUS_WIDTH\'\n reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:130: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:135: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:144: syntax error, unexpected \'@\'\n repeat (6) @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:154: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:161: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:165: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:169: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:173: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:179: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: Define or directive not defined: \'`ADDR_FMC516_CH0_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:246: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_CH0_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:247: Define or directive not defined: \'`FMC516_CH0_CTL_DATA_CHAIN_DLY\'\n (4 << `FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET) & `FMC516_CH0_CTL_DATA_CHAIN_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: Define or directive not defined: \'`ADDR_FMC516_ADC_CTL\'\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:250: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n cmp_wishbone_bfm.write32(32\'h00000000 + `ADDR_FMC516_ADC_CTL,\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY_OFFSET\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:251: Define or directive not defined: \'`FMC516_ADC_CTL_UPDATE_DLY\'\n (1 << `FMC516_ADC_CTL_UPDATE_DLY_OFFSET) & `FMC516_ADC_CTL_UPDATE_DLY);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:429: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n function [`ADC_DATA_WIDTH/2-1:0] adc_data_gen;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:431: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:438: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n function [`ADC_DATA_WIDTH/2 - 1 : 0] toggle_adc_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:439: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n input [`ADC_DATA_WIDTH/2 -1 : 0] data;\n ^\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:441: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:442: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n for (i = 0; i < `ADC_DATA_WIDTH/2; i = i+1) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:451: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/98916810/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v:458: syntax error, unexpected \'=\', expecting IDENTIFIER\n adc_data_valid_gen = 1\'b1;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'

function

function adc_data_valid_gen; input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp > prob) adc_data_valid_gen = 1'b1; else adc_data_valid_gen = 1'b0; end endfunction

function adc_data_valid_gen;

input real prob; real temp; begin temp = ({$random} % 100 + 1)/100.00; if (temp > prob) adc_data_valid_gen = 1'b1; else adc_data_valid_gen = 1'b0; end endfunction

data/full_repos/permissive/98927919/GuitarHero.v

GuitarHero.v

v

[]

[]

[]

line:47: before: "."

1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module final_project(LEDR, CLOCK_50, VGA_CLK, VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N, VGA_R, VGA_B, VGA_G, KEY, SW); input [17:0] SW; input CLOCK_50; input [1:0] KEY; output [17:0] LEDR; output VGA_CLK; output VGA_HS; output VGA_VS; output VGA_BLANK_N; output VGA_SYNC_N; output [9:0] VGA_R; output [9:0] VGA_G; output [9:0] VGA_B; vga_adapter VGA( .resetn(1'b1), .clock(CLOCK_50), .colour(colour), .x(x), .y(y), .plot(writeEn), .VGA_R(VGA_R), .VGA_G(VGA_G), .VGA_B(VGA_B), .VGA_HS(VGA_HS), .VGA_VS(VGA_VS), .VGA_BLANK(VGA_BLANK_N), .VGA_SYNC(VGA_SYNC_N), .VGA_CLK(VGA_CLK)); defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE"; defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "background.mif"; main master( .clock_50(CLOCK_50), .data(SW[11:0]), .clock(KEY[0]), .LEDoutput(LEDR) ); endmodule

module final_project(LEDR, CLOCK_50, VGA_CLK, VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N, VGA_R, VGA_B, VGA_G, KEY, SW);

input [17:0] SW; input CLOCK_50; input [1:0] KEY; output [17:0] LEDR; output VGA_CLK; output VGA_HS; output VGA_VS; output VGA_BLANK_N; output VGA_SYNC_N; output [9:0] VGA_R; output [9:0] VGA_G; output [9:0] VGA_B; vga_adapter VGA( .resetn(1'b1), .clock(CLOCK_50), .colour(colour), .x(x), .y(y), .plot(writeEn), .VGA_R(VGA_R), .VGA_G(VGA_G), .VGA_B(VGA_B), .VGA_HS(VGA_HS), .VGA_VS(VGA_VS), .VGA_BLANK(VGA_BLANK_N), .VGA_SYNC(VGA_SYNC_N), .VGA_CLK(VGA_CLK)); defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE"; defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "background.mif"; main master( .clock_50(CLOCK_50), .data(SW[11:0]), .clock(KEY[0]), .LEDoutput(LEDR) ); endmodule

data/full_repos/permissive/98927919/GuitarHero.v

GuitarHero.v

v

[]

[]

[]

line:47: before: "."

1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module main(clock_50, data, clock, LEDoutput); input [11:0] data; input clock_50; input clock; output [17:0] LEDoutput; wire [33:0] results; assign results[33:16] = LEDoutput[17:0]; function_one func1( .a(clock_50), .result(results[0]) ); function_two func2( .clock(results[3]), .load_n(data[0]), .result(LEDoutput[17:0]) ); function_2 func22( .a(clock_50), .result(results[1]) ); function_3 func33333( .a(clock_50), .result(results[2]) ); mux3to1 muxxx( .select(data[11:10]), .d(results[2:0]), .q(results[3]) ); endmodule

module main(clock_50, data, clock, LEDoutput);

input [11:0] data; input clock_50; input clock; output [17:0] LEDoutput; wire [33:0] results; assign results[33:16] = LEDoutput[17:0]; function_one func1( .a(clock_50), .result(results[0]) ); function_two func2( .clock(results[3]), .load_n(data[0]), .result(LEDoutput[17:0]) ); function_2 func22( .a(clock_50), .result(results[1]) ); function_3 func33333( .a(clock_50), .result(results[2]) ); mux3to1 muxxx( .select(data[11:10]), .d(results[2:0]), .q(results[3]) ); endmodule

data/full_repos/permissive/98927919/GuitarHero.v

GuitarHero.v

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1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module function_one(a, result); input a; wire enable; reg flip; output reg [7:0] result; RateDivider RD1( .clock(a), .enable(enable), ); always @ (posedge enable) begin if (flip == 1'b0) begin result = 1'b1; flip = 1'b1; end else if (flip == 1'b1) begin result = 1'b0; flip = 1'b0; end end endmodule

module function_one(a, result);

input a; wire enable; reg flip; output reg [7:0] result; RateDivider RD1( .clock(a), .enable(enable), ); always @ (posedge enable) begin if (flip == 1'b0) begin result = 1'b1; flip = 1'b1; end else if (flip == 1'b1) begin result = 1'b0; flip = 1'b0; end end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

GuitarHero.v

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1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module function_2(a, result); input a; wire enable; reg flip; output reg result; RateDividerTwo RD2( .clock(a), .enable(enable), ); always @ (posedge enable) begin if (flip == 1'b0) begin result = 1'b1; flip = 1'b1; end else if (flip == 1'b1) begin result = 1'b0; flip = 1'b0; end end endmodule

module function_2(a, result);

input a; wire enable; reg flip; output reg result; RateDividerTwo RD2( .clock(a), .enable(enable), ); always @ (posedge enable) begin if (flip == 1'b0) begin result = 1'b1; flip = 1'b1; end else if (flip == 1'b1) begin result = 1'b0; flip = 1'b0; end end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

GuitarHero.v

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1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module function_3(a, result); input a; wire enable; reg flip; output reg result; RateDividerThree RD3( .clock(a), .enable(enable), ); always @ (posedge enable) begin if (flip == 1'b0) begin result = 1'b1; flip = 1'b1; end else if (flip == 1'b1) begin result = 1'b0; flip = 1'b0; end end endmodule

module function_3(a, result);

input a; wire enable; reg flip; output reg result; RateDividerThree RD3( .clock(a), .enable(enable), ); always @ (posedge enable) begin if (flip == 1'b0) begin result = 1'b1; flip = 1'b1; end else if (flip == 1'b1) begin result = 1'b0; flip = 1'b0; end end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

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1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module mux3to1(select, d, q ); input[1:0] select; input[3:0] d; output q; reg q; wire[1:0] select; wire[3:0] d; always @( select or d ) begin if( select == 0) q = d[0]; if( select == 1) q = d[1]; if( select == 2) q = d[2]; if( select == 3) q = d[3]; end endmodule

module mux3to1(select, d, q );

input[1:0] select; input[3:0] d; output q; reg q; wire[1:0] select; wire[3:0] d; always @( select or d ) begin if( select == 0) q = d[0]; if( select == 1) q = d[1]; if( select == 2) q = d[2]; if( select == 3) q = d[3]; end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

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line:47: before: "."

1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module function_two(clock, load_n, result); input clock; input load_n; wire [319:0] shifterbit; wire timetopressleft; output reg [17:0] result; register320bit displayleft( .inputnum(319'b00000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000111000000011100000111000000001110000000000000000001110000000000000000000000000000000000000111000000000000000001110000000000000000000000000000000000000111000000000000000001110000000000000000000000000000000000000000001111110), .clock(clock), .clear_n(0), .load_n(load_n), .q(shifterbit), .outputbutton(timetopressleft) ); always @ (negedge clock) begin result[17:0] = shifterbit[17:0]; end endmodule

module function_two(clock, load_n, result);

input clock; input load_n; wire [319:0] shifterbit; wire timetopressleft; output reg [17:0] result; register320bit displayleft( .inputnum(319'b00000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000111000000011100000111000000001110000000000000000001110000000000000000000000000000000000000111000000000000000001110000000000000000000000000000000000000111000000000000000001110000000000000000000000000000000000000000001111110), .clock(clock), .clear_n(0), .load_n(load_n), .q(shifterbit), .outputbutton(timetopressleft) ); always @ (negedge clock) begin result[17:0] = shifterbit[17:0]; end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

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1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module RateDivider(clock, enable); input clock; output reg enable; reg [24:0] q = 25'b0000000000000000000000000; reg [24:0] d = 25'b0111001001110000111000000; always @(posedge clock) begin if (q == d) begin q <= 0; enable = 1'b1; end else begin q <= q + 1'b1; enable = 1'b0; end end endmodule

module RateDivider(clock, enable);

input clock; output reg enable; reg [24:0] q = 25'b0000000000000000000000000; reg [24:0] d = 25'b0111001001110000111000000; always @(posedge clock) begin if (q == d) begin q <= 0; enable = 1'b1; end else begin q <= q + 1'b1; enable = 1'b0; end end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

GuitarHero.v

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line:47: before: "."

1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module RateDividerTwo(clock, enable); input clock; output reg enable; reg [24:0] q = 25'b0000000000000000000000000; reg [24:0] d = 25'b0011001001110000111000000; always @(posedge clock) begin if (q == d) begin q <= 0; enable = 1'b1; end else begin q <= q + 1'b1; enable = 1'b0; end end endmodule

module RateDividerTwo(clock, enable);

input clock; output reg enable; reg [24:0] q = 25'b0000000000000000000000000; reg [24:0] d = 25'b0011001001110000111000000; always @(posedge clock) begin if (q == d) begin q <= 0; enable = 1'b1; end else begin q <= q + 1'b1; enable = 1'b0; end end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

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line:47: before: "."

1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module RateDividerThree(clock, enable); input clock; output reg enable; reg [24:0] q = 25'b0000000000000000000000000; reg [24:0] d = 25'b0001001001110000111000000; always @(posedge clock) begin if (q == d) begin q <= 0; enable = 1'b1; end else begin q <= q + 1'b1; enable = 1'b0; end end endmodule

module RateDividerThree(clock, enable);

input clock; output reg enable; reg [24:0] q = 25'b0000000000000000000000000; reg [24:0] d = 25'b0001001001110000111000000; always @(posedge clock) begin if (q == d) begin q <= 0; enable = 1'b1; end else begin q <= q + 1'b1; enable = 1'b0; end end endmodule

data/full_repos/permissive/98927919/GuitarHero.v

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line:47: before: "."

1: b"%Error: data/full_repos/permissive/98927919/GuitarHero.v:171: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:142: Pin not found: '__pinNumber3'\n );\n ^\n%Error: data/full_repos/permissive/98927919/GuitarHero.v:112: Pin not found: '__pinNumber3'\n );\n ^\n%Error: Exiting due to 3 error(s)\n"

module

module register320bit(inputnum, clock, load_n, clear_n, q, outputbutton); input clock; input clear_n; input load_n; input [319:0] inputnum; reg [319:0] shifterbit; output reg outputbutton = 1'b0; output reg [119:0] q; always @ (negedge clock) begin if (clear_n == 1) q <= 0; else if (load_n == 1) shifterbit = inputnum; else begin shifterbit[318:0] = shifterbit[319:1]; shifterbit[319] <= 0; q[119:0] = shifterbit[119:0]; outputbutton <= q[10]; end end endmodule

module register320bit(inputnum, clock, load_n, clear_n, q, outputbutton);

input clock; input clear_n; input load_n; input [319:0] inputnum; reg [319:0] shifterbit; output reg outputbutton = 1'b0; output reg [119:0] q; always @ (negedge clock) begin if (clear_n == 1) q <= 0; else if (load_n == 1) shifterbit = inputnum; else begin shifterbit[318:0] = shifterbit[319:1]; shifterbit[319] <= 0; q[119:0] = shifterbit[119:0]; outputbutton <= q[10]; end end endmodule

data/full_repos/permissive/99182535/bjx1c32b/Dc2Tile.v

Dc2Tile.v

v

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1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/Dc2Tile.v:11: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: Exiting due to 1 error(s)\n'

module

module Dc2Tile( clock, reset, regInAddr, regInData, regOutData, regOutOK, regInOE, regInWR, regInOp, memInData, memOutData, memAddr, memOE, memWR, memOK, mmioInData, mmioOutData, mmioAddr, mmioOE, mmioWR, mmioOK ); input clock; input reset; input[31:0] regInAddr; input[127:0] regInData; input regInOE; input regInWR; input[4:0] regInOp; output[127:0] regOutData; output[1:0] regOutOK; input[127:0] memInData; output[127:0] memOutData; output[31:0] memAddr; output memOE; output memWR; input[1:0] memOK; reg[127:0] tMemOutData; reg[31:0] tMemAddr; reg tMemOE; reg tMemWR; assign memOutData = tMemOutData; assign memAddr = tMemAddr; assign memOE = tMemOE; assign memWR = tMemWR; input[31:0] mmioInData; output[31:0] mmioOutData; output[31:0] mmioAddr; output mmioOE; output mmioWR; input[1:0] mmioOK; reg[31:0] tMmioOutData; reg[31:0] tMmioAddr; reg tMmioOE; reg tMmioWR; assign mmioOutData = tMmioOutData; assign mmioAddr = tMmioAddr; assign mmioOE = tMmioOE; assign mmioWR = tMmioWR; (* ram_style="block" *) reg[31:0] memTileA[0:2047]; (* ram_style="block" *) reg[31:0] memTileB[0:2047]; (* ram_style="block" *) reg[31:0] memTileC[0:2047]; (* ram_style="block" *) reg[31:0] memTileD[0:2047]; (* ram_style="block" *) reg[127:0] romTile[255:0]; reg[127:0] tRamTile; reg[10:0] tAccTileIx; reg[127:0] tMemTile; reg[127:0] tOutData; reg[127:0] tNextTile; reg[10:0] tRegTileIx; reg[10:0] tNextTileIx; reg tNextTileSt; reg[1:0] tRegOutOK; wire addrIsRam; assign addrIsRam = (regInAddr[28:0] >= 29'h0C00_0000) && (regInAddr[28:0] <= 29'h1E00_0000) ; wire addrIsRom; assign addrIsRom = (regInAddr[28:0] <= 29'h0010_0000) ; assign regOutData = tOutData; assign regOutOK = tRegOutOK; initial begin $readmemh("bootrom.txt", romTile); end always @* begin tMemTile = 0; tOutData = 0; tNextTile = 0; tRegTileIx = regInAddr[14:4]; tNextTileIx = tRegTileIx; tNextTileSt = 0; tRegOutOK = 0; tMemOutData = 0; tMemAddr = 0; tMemOE = 0; tMemWR = 0; tMmioOutData = 0; tMmioAddr = 0; tMmioOE = 0; tMmioWR = 0; if(regInOE || regInWR) begin $display("DcTile2 %X %d %d", regInAddr, addrIsRom, addrIsRam); if(addrIsRom) begin tMemTile = romTile[tRegTileIx[7:0]]; tNextTile = tMemTile; tRegOutOK = 1; $display("Rom: %X", tMemTile); case(regInOp[1:0]) 2'b00: tOutData=tMemTile; 2'b01: tOutData=tMemTile; 2'b10: case(regInAddr[3:2]) 2'b00: tOutData={96'h0, tMemTile[ 31: 0]}; 2'b01: tOutData={96'h0, tMemTile[ 63:32]}; 2'b10: tOutData={96'h0, tMemTile[ 95:64]}; 2'b11: tOutData={96'h0, tMemTile[127:96]}; endcase 2'b11: begin if(regInAddr[3]) tOutData={64'h0, tMemTile[127:64]}; else tOutData={64'h0, tMemTile[ 63: 0]}; end endcase $display("Rom: Out=%X", tOutData); end else if(addrIsRam) begin tMemTile = tRamTile; tNextTile = tMemTile; tRegOutOK = (tAccTileIx == tRegTileIx) ? UMEM_OK_OK : UMEM_OK_HOLD; case(regInOp[1:0]) 2'b00: tOutData=tMemTile; 2'b01: tOutData=tMemTile; 2'b10: case(regInAddr[3:2]) 2'b00: tOutData={96'h0, tMemTile[ 31: 0]}; 2'b01: tOutData={96'h0, tMemTile[ 63:32]}; 2'b10: tOutData={96'h0, tMemTile[ 95:64]}; 2'b11: tOutData={96'h0, tMemTile[127:96]}; endcase 2'b11: begin if(regInAddr[3]) tOutData={64'h0, tMemTile[127:64]}; else tOutData={64'h0, tMemTile[ 63: 0]}; end endcase if(regInWR) begin tNextTileIx = tRegTileIx; tNextTileSt = 1; case(regInOp[1:0]) 2'b00: tNextTile=regInData; 2'b01: tNextTile=regInData; 2'b10: case(regInAddr[3:2]) 2'b00: tNextTile[ 31: 0] = regInData[31:0]; 2'b01: tNextTile[ 63:32] = regInData[31:0]; 2'b10: tNextTile[ 95:64] = regInData[31:0]; 2'b11: tNextTile[127:96] = regInData[31:0]; endcase 2'b11: begin if(regInAddr[3]) tNextTile[127:64] = regInData[63:0]; else tNextTile[ 63: 0] = regInData[63:0]; end endcase end end else begin tMmioOutData = regInData[31:0]; tMmioAddr = regInAddr; tMmioOE = regInOE; tMmioWR = regInWR; tRegOutOK = mmioOK; tOutData = { 96'h0, mmioInData[31:0] }; end end end always @ (posedge clock) begin tRamTile[ 31: 0] <= memTileA[tRegTileIx]; tRamTile[ 63:32] <= memTileB[tRegTileIx]; tRamTile[ 95:64] <= memTileC[tRegTileIx]; tRamTile[127:96] <= memTileD[tRegTileIx]; tAccTileIx <= tRegTileIx; if(tNextTileSt) begin memTileA[tNextTileIx] <= tNextTile[ 31: 0]; memTileB[tNextTileIx] <= tNextTile[ 63:32]; memTileC[tNextTileIx] <= tNextTile[ 95:64]; memTileD[tNextTileIx] <= tNextTile[127:96]; end end endmodule

module Dc2Tile( clock, reset, regInAddr, regInData, regOutData, regOutOK, regInOE, regInWR, regInOp, memInData, memOutData, memAddr, memOE, memWR, memOK, mmioInData, mmioOutData, mmioAddr, mmioOE, mmioWR, mmioOK );

input clock; input reset; input[31:0] regInAddr; input[127:0] regInData; input regInOE; input regInWR; input[4:0] regInOp; output[127:0] regOutData; output[1:0] regOutOK; input[127:0] memInData; output[127:0] memOutData; output[31:0] memAddr; output memOE; output memWR; input[1:0] memOK; reg[127:0] tMemOutData; reg[31:0] tMemAddr; reg tMemOE; reg tMemWR; assign memOutData = tMemOutData; assign memAddr = tMemAddr; assign memOE = tMemOE; assign memWR = tMemWR; input[31:0] mmioInData; output[31:0] mmioOutData; output[31:0] mmioAddr; output mmioOE; output mmioWR; input[1:0] mmioOK; reg[31:0] tMmioOutData; reg[31:0] tMmioAddr; reg tMmioOE; reg tMmioWR; assign mmioOutData = tMmioOutData; assign mmioAddr = tMmioAddr; assign mmioOE = tMmioOE; assign mmioWR = tMmioWR; (* ram_style="block" *) reg[31:0] memTileA[0:2047]; (* ram_style="block" *) reg[31:0] memTileB[0:2047]; (* ram_style="block" *) reg[31:0] memTileC[0:2047]; (* ram_style="block" *) reg[31:0] memTileD[0:2047]; (* ram_style="block" *) reg[127:0] romTile[255:0]; reg[127:0] tRamTile; reg[10:0] tAccTileIx; reg[127:0] tMemTile; reg[127:0] tOutData; reg[127:0] tNextTile; reg[10:0] tRegTileIx; reg[10:0] tNextTileIx; reg tNextTileSt; reg[1:0] tRegOutOK; wire addrIsRam; assign addrIsRam = (regInAddr[28:0] >= 29'h0C00_0000) && (regInAddr[28:0] <= 29'h1E00_0000) ; wire addrIsRom; assign addrIsRom = (regInAddr[28:0] <= 29'h0010_0000) ; assign regOutData = tOutData; assign regOutOK = tRegOutOK; initial begin $readmemh("bootrom.txt", romTile); end always @* begin tMemTile = 0; tOutData = 0; tNextTile = 0; tRegTileIx = regInAddr[14:4]; tNextTileIx = tRegTileIx; tNextTileSt = 0; tRegOutOK = 0; tMemOutData = 0; tMemAddr = 0; tMemOE = 0; tMemWR = 0; tMmioOutData = 0; tMmioAddr = 0; tMmioOE = 0; tMmioWR = 0; if(regInOE || regInWR) begin $display("DcTile2 %X %d %d", regInAddr, addrIsRom, addrIsRam); if(addrIsRom) begin tMemTile = romTile[tRegTileIx[7:0]]; tNextTile = tMemTile; tRegOutOK = 1; $display("Rom: %X", tMemTile); case(regInOp[1:0]) 2'b00: tOutData=tMemTile; 2'b01: tOutData=tMemTile; 2'b10: case(regInAddr[3:2]) 2'b00: tOutData={96'h0, tMemTile[ 31: 0]}; 2'b01: tOutData={96'h0, tMemTile[ 63:32]}; 2'b10: tOutData={96'h0, tMemTile[ 95:64]}; 2'b11: tOutData={96'h0, tMemTile[127:96]}; endcase 2'b11: begin if(regInAddr[3]) tOutData={64'h0, tMemTile[127:64]}; else tOutData={64'h0, tMemTile[ 63: 0]}; end endcase $display("Rom: Out=%X", tOutData); end else if(addrIsRam) begin tMemTile = tRamTile; tNextTile = tMemTile; tRegOutOK = (tAccTileIx == tRegTileIx) ? UMEM_OK_OK : UMEM_OK_HOLD; case(regInOp[1:0]) 2'b00: tOutData=tMemTile; 2'b01: tOutData=tMemTile; 2'b10: case(regInAddr[3:2]) 2'b00: tOutData={96'h0, tMemTile[ 31: 0]}; 2'b01: tOutData={96'h0, tMemTile[ 63:32]}; 2'b10: tOutData={96'h0, tMemTile[ 95:64]}; 2'b11: tOutData={96'h0, tMemTile[127:96]}; endcase 2'b11: begin if(regInAddr[3]) tOutData={64'h0, tMemTile[127:64]}; else tOutData={64'h0, tMemTile[ 63: 0]}; end endcase if(regInWR) begin tNextTileIx = tRegTileIx; tNextTileSt = 1; case(regInOp[1:0]) 2'b00: tNextTile=regInData; 2'b01: tNextTile=regInData; 2'b10: case(regInAddr[3:2]) 2'b00: tNextTile[ 31: 0] = regInData[31:0]; 2'b01: tNextTile[ 63:32] = regInData[31:0]; 2'b10: tNextTile[ 95:64] = regInData[31:0]; 2'b11: tNextTile[127:96] = regInData[31:0]; endcase 2'b11: begin if(regInAddr[3]) tNextTile[127:64] = regInData[63:0]; else tNextTile[ 63: 0] = regInData[63:0]; end endcase end end else begin tMmioOutData = regInData[31:0]; tMmioAddr = regInAddr; tMmioOE = regInOE; tMmioWR = regInWR; tRegOutOK = mmioOK; tOutData = { 96'h0, mmioInData[31:0] }; end end end always @ (posedge clock) begin tRamTile[ 31: 0] <= memTileA[tRegTileIx]; tRamTile[ 63:32] <= memTileB[tRegTileIx]; tRamTile[ 95:64] <= memTileC[tRegTileIx]; tRamTile[127:96] <= memTileD[tRegTileIx]; tAccTileIx <= tRegTileIx; if(tNextTileSt) begin memTileA[tNextTileIx] <= tNextTile[ 31: 0]; memTileB[tNextTileIx] <= tNextTile[ 63:32]; memTileC[tNextTileIx] <= tNextTile[ 95:64]; memTileD[tNextTileIx] <= tNextTile[127:96]; end end endmodule

data/full_repos/permissive/99182535/bjx1c32b/DecOp2.v

DecOp2.v

v

[]

[]

[]

line:34: before: "parameter"

1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/DecOp2.v:7: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: Exiting due to 1 error(s)\n'

module

module DecOp2( clk, istrWord, regCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idUCmd ); input clk; input[31:0] istrWord; input[15:0] regCsFl; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[3:0] idStepPc; output[7:0] idUCmd; reg isOp32; reg isOp8E; reg[7:0] opPfxImm; reg[15:0] opCmdWord; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; always @ (clk) begin idStepPc = 2; opPfxImm=0; opCmdWord=0; opRegN=0; opRegS=0; opRegT=0; opUCmd=UCMD_UDBRK; opImm=0; isOp32=0; isOp8E=0; case(istrWord[15:8]) 8'h8A: begin isOp32=1; opCmdWord=istrWord[15:0]; opImm[31:24]=istrWord[7]?8'hFF:8'h00; opImm[23:16]=istrWord[7:0]; opImm[15: 0]=istrWord[31:16]; end 8'h8E: begin isOp32=1; isOp8E=1; opPfxImm=istrWord[7:0]; opCmdWord=istrWord[31:16]; end default: begin opCmdWord=istrWord[15:0]; end endcase if(isOp32) idStepPc = 4; case(opCmdWord[15:12]) 4'h0: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_R0; case(opCmdWord[3:0]) 4'h0: begin end 4'h1: begin end 4'h2: begin opUCmd=UCMD_MOV_RR; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h5, opCmdWord[ 7:4]}; end 4'h3: begin case(opCmdWord[7:4]) 4'h3: begin end default: begin end endcase end 4'h4: begin opUCmd=UCMD_MOVB_RM; end 4'h5: begin opUCmd=UCMD_MOVW_RM; end 4'h6: begin opUCmd=UCMD_MOVL_RM; end 4'h7: begin opUCmd=UCMD_ALU_DMULS; opRegN[6:4]=3'h0; opRegS[6:4]=3'h4; end 4'h8: begin case(opCmdWord[7:4]) 4'h3: begin end default: begin end endcase end 4'h9: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_NONE; end 4'h3: begin end default: begin end endcase end 4'hA: begin opUCmd=UCMD_MOV_RR; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h4, opCmdWord[ 7:4]}; end 4'hB: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_RTS; end 4'h2: begin opUCmd=UCMD_RTE; end 4'h3: begin opUCmd=UCMD_UDBRK; opImm=1; if(opCmdWord[11:8]==4'hF) begin opUCmd=UCMD_NONE; idStepPc=0; end end 4'h6: begin opUCmd=UCMD_RTSN; end default: begin end endcase end 4'hC: begin opUCmd=UCMD_MOVB_MR; end 4'hD: begin opUCmd=UCMD_MOVW_MR; end 4'hE: begin opUCmd=UCMD_MOVL_MR; end 4'hF: begin end default: begin end endcase end 4'h1: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; opImm[3:0]=opCmdWord[ 3:0]; opUCmd=UCMD_MOVL_RM; end 4'h2: begin case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_MOVB_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; end 4'h1: begin opUCmd=UCMD_MOVW_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; end 4'h2: begin opUCmd=UCMD_MOVL_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; end 4'h4: begin opUCmd=UCMD_MOVB_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_MR_MEMDEC; end 4'h5: begin opUCmd=UCMD_MOVW_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_MR_MEMDEC; end 4'h6: begin opUCmd=UCMD_MOVL_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_MR_MEMDEC; end 4'h8: begin opUCmd=UCMD_CMP_TST; opRegT={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; end 4'h9: begin opUCmd=UCMD_ALU_AND; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT={3'h0, opCmdWord[11:8]}; end 4'hA: begin opUCmd=UCMD_ALU_XOR; opRegT=opRegN; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT={3'h0, opCmdWord[11:8]}; end 4'hB: begin opUCmd=UCMD_ALU_OR; opRegT=opRegN; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT={3'h0, opCmdWord[11:8]}; end 4'hE: begin opUCmd=UCMD_ALU_MULUW; opRegT={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; end 4'hF: begin opUCmd=UCMD_ALU_MULSW; opRegT={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; end default: begin end endcase end 4'h3: begin opRegN[3:0]=opCmdWord[11:8]; opRegS[3:0]=opCmdWord[ 7:4]; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_CMP_EQ; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h2: begin opUCmd=UCMD_CMP_HS; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h3: begin opUCmd=UCMD_CMP_GE; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h5: begin opUCmd=UCMD_ALU_DMULU; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h6: begin opUCmd=UCMD_CMP_HI; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h7: begin opUCmd=UCMD_CMP_GT; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h8: begin opUCmd=UCMD_ALU_SUB; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hA: begin opUCmd=UCMD_ALU_SUBC; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hB: begin opUCmd=UCMD_ALU_SUBV; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hC: begin opUCmd=UCMD_ALU_ADD; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hD: begin opUCmd=UCMD_ALU_DMULS; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hE: begin opUCmd=UCMD_ALU_ADDC; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hF: begin opUCmd=UCMD_ALU_ADDV; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end default: begin end endcase end 4'h4: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin end 4'hB: begin opRegS={3'h0, opCmdWord[11:8]}; case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_JSR; end 4'h2: begin opUCmd=UCMD_JMP; end 4'h3: begin end 4'h4: begin opUCmd=UCMD_JSRN; end default: begin end endcase end 4'hC: begin opUCmd=UCMD_ALU_SHAD; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hD: begin opUCmd=UCMD_ALU_SHLD; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end default: begin end endcase end 4'h5: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; opImm[3:0]=opCmdWord[ 3:0]; opUCmd=UCMD_MOVL_MR; end 4'h6: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin end default: begin end endcase end 4'h7: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT=UREG_MR_IMM; opImm[7:0]=opCmdWord[ 7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_ALU_ADD; end 4'h8: begin opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; case(opCmdWord[11:8]) 4'h0: begin end 4'h2: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BRAN; end 4'h9: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BT; end 4'hA: begin opRegN=UREG_R0; opUCmd=UCMD_MOV_RI; end 4'hB: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BF; end 4'hD: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BTS; end 4'hF: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BFS; end default: begin end endcase end 4'h9: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCW; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVW_MR; end 4'hA: begin opImm[11:0]=opCmdWord[11:0]; opImm[31:12]=opCmdWord[11]?20'hFFFFF:20'h00000; opUCmd=UCMD_BRA; end 4'hB: begin opImm[11:0]=opCmdWord[11:0]; opImm[31:12]=opCmdWord[11]?20'hFFFFF:20'h00000; opUCmd=UCMD_BSR; end 4'hC: begin case(opCmdWord[11:8]) 4'h0: begin end default: begin end endcase end 4'hD: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCL; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVL_MR; end 4'hE: begin opRegN[3:0]=opCmdWord[11:8]; opRegS[3:0]=opCmdWord[11:8]; opRegT=UREG_MR_IMM; opImm[7:0]=opCmdWord[ 7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_MOV_RI; end 4'hF: begin opRegN[3:0]=opCmdWord[11:8]; opRegS[3:0]=opCmdWord[ 7:4]; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin end default: begin end endcase end default: begin end endcase end endmodule

module DecOp2( clk, istrWord, regCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idUCmd );

input clk; input[31:0] istrWord; input[15:0] regCsFl; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[3:0] idStepPc; output[7:0] idUCmd; reg isOp32; reg isOp8E; reg[7:0] opPfxImm; reg[15:0] opCmdWord; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; always @ (clk) begin idStepPc = 2; opPfxImm=0; opCmdWord=0; opRegN=0; opRegS=0; opRegT=0; opUCmd=UCMD_UDBRK; opImm=0; isOp32=0; isOp8E=0; case(istrWord[15:8]) 8'h8A: begin isOp32=1; opCmdWord=istrWord[15:0]; opImm[31:24]=istrWord[7]?8'hFF:8'h00; opImm[23:16]=istrWord[7:0]; opImm[15: 0]=istrWord[31:16]; end 8'h8E: begin isOp32=1; isOp8E=1; opPfxImm=istrWord[7:0]; opCmdWord=istrWord[31:16]; end default: begin opCmdWord=istrWord[15:0]; end endcase if(isOp32) idStepPc = 4; case(opCmdWord[15:12]) 4'h0: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_R0; case(opCmdWord[3:0]) 4'h0: begin end 4'h1: begin end 4'h2: begin opUCmd=UCMD_MOV_RR; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h5, opCmdWord[ 7:4]}; end 4'h3: begin case(opCmdWord[7:4]) 4'h3: begin end default: begin end endcase end 4'h4: begin opUCmd=UCMD_MOVB_RM; end 4'h5: begin opUCmd=UCMD_MOVW_RM; end 4'h6: begin opUCmd=UCMD_MOVL_RM; end 4'h7: begin opUCmd=UCMD_ALU_DMULS; opRegN[6:4]=3'h0; opRegS[6:4]=3'h4; end 4'h8: begin case(opCmdWord[7:4]) 4'h3: begin end default: begin end endcase end 4'h9: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_NONE; end 4'h3: begin end default: begin end endcase end 4'hA: begin opUCmd=UCMD_MOV_RR; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h4, opCmdWord[ 7:4]}; end 4'hB: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_RTS; end 4'h2: begin opUCmd=UCMD_RTE; end 4'h3: begin opUCmd=UCMD_UDBRK; opImm=1; if(opCmdWord[11:8]==4'hF) begin opUCmd=UCMD_NONE; idStepPc=0; end end 4'h6: begin opUCmd=UCMD_RTSN; end default: begin end endcase end 4'hC: begin opUCmd=UCMD_MOVB_MR; end 4'hD: begin opUCmd=UCMD_MOVW_MR; end 4'hE: begin opUCmd=UCMD_MOVL_MR; end 4'hF: begin end default: begin end endcase end 4'h1: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; opImm[3:0]=opCmdWord[ 3:0]; opUCmd=UCMD_MOVL_RM; end 4'h2: begin case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_MOVB_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; end 4'h1: begin opUCmd=UCMD_MOVW_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; end 4'h2: begin opUCmd=UCMD_MOVL_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; end 4'h4: begin opUCmd=UCMD_MOVB_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_MR_MEMDEC; end 4'h5: begin opUCmd=UCMD_MOVW_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_MR_MEMDEC; end 4'h6: begin opUCmd=UCMD_MOVL_RM; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_MR_MEMDEC; end 4'h8: begin opUCmd=UCMD_CMP_TST; opRegT={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; end 4'h9: begin opUCmd=UCMD_ALU_AND; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT={3'h0, opCmdWord[11:8]}; end 4'hA: begin opUCmd=UCMD_ALU_XOR; opRegT=opRegN; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT={3'h0, opCmdWord[11:8]}; end 4'hB: begin opUCmd=UCMD_ALU_OR; opRegT=opRegN; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT={3'h0, opCmdWord[11:8]}; end 4'hE: begin opUCmd=UCMD_ALU_MULUW; opRegT={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; end 4'hF: begin opUCmd=UCMD_ALU_MULSW; opRegT={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; end default: begin end endcase end 4'h3: begin opRegN[3:0]=opCmdWord[11:8]; opRegS[3:0]=opCmdWord[ 7:4]; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_CMP_EQ; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h2: begin opUCmd=UCMD_CMP_HS; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h3: begin opUCmd=UCMD_CMP_GE; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h5: begin opUCmd=UCMD_ALU_DMULU; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h6: begin opUCmd=UCMD_CMP_HI; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h7: begin opUCmd=UCMD_CMP_GT; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'h8: begin opUCmd=UCMD_ALU_SUB; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hA: begin opUCmd=UCMD_ALU_SUBC; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hB: begin opUCmd=UCMD_ALU_SUBV; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hC: begin opUCmd=UCMD_ALU_ADD; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hD: begin opUCmd=UCMD_ALU_DMULS; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hE: begin opUCmd=UCMD_ALU_ADDC; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hF: begin opUCmd=UCMD_ALU_ADDV; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end default: begin end endcase end 4'h4: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin end 4'hB: begin opRegS={3'h0, opCmdWord[11:8]}; case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_JSR; end 4'h2: begin opUCmd=UCMD_JMP; end 4'h3: begin end 4'h4: begin opUCmd=UCMD_JSRN; end default: begin end endcase end 4'hC: begin opUCmd=UCMD_ALU_SHAD; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end 4'hD: begin opUCmd=UCMD_ALU_SHLD; opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT={3'h0, opCmdWord[ 7:4]}; end default: begin end endcase end 4'h5: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; opImm[3:0]=opCmdWord[ 3:0]; opUCmd=UCMD_MOVL_MR; end 4'h6: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[ 7:4]}; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin end default: begin end endcase end 4'h7: begin opRegN={3'h0, opCmdWord[11:8]}; opRegS={3'h0, opCmdWord[11:8]}; opRegT=UREG_MR_IMM; opImm[7:0]=opCmdWord[ 7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_ALU_ADD; end 4'h8: begin opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; case(opCmdWord[11:8]) 4'h0: begin end 4'h2: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BRAN; end 4'h9: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BT; end 4'hA: begin opRegN=UREG_R0; opUCmd=UCMD_MOV_RI; end 4'hB: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BF; end 4'hD: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BTS; end 4'hF: begin opImm[7:0]=opCmdWord[7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_BFS; end default: begin end endcase end 4'h9: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCW; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVW_MR; end 4'hA: begin opImm[11:0]=opCmdWord[11:0]; opImm[31:12]=opCmdWord[11]?20'hFFFFF:20'h00000; opUCmd=UCMD_BRA; end 4'hB: begin opImm[11:0]=opCmdWord[11:0]; opImm[31:12]=opCmdWord[11]?20'hFFFFF:20'h00000; opUCmd=UCMD_BSR; end 4'hC: begin case(opCmdWord[11:8]) 4'h0: begin end default: begin end endcase end 4'hD: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCL; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVL_MR; end 4'hE: begin opRegN[3:0]=opCmdWord[11:8]; opRegS[3:0]=opCmdWord[11:8]; opRegT=UREG_MR_IMM; opImm[7:0]=opCmdWord[ 7:0]; opImm[31:8]=opCmdWord[7]?24'hFFFFFF:24'h000000; opUCmd=UCMD_MOV_RI; end 4'hF: begin opRegN[3:0]=opCmdWord[11:8]; opRegS[3:0]=opCmdWord[ 7:4]; opRegT=UREG_ZZR; case(opCmdWord[3:0]) 4'h0: begin end default: begin end endcase end default: begin end endcase end endmodule

data/full_repos/permissive/99182535/bjx1c32b/DecOp4_0.v

DecOp4_0.v

v

[]

[]

[]

line:34: before: "parameter"

1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/DecOp4_0.v:7: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1c32b/DecOp4_0.v:8: Cannot find include file: DecOp4_XE.v\n`include "DecOp4_XE.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'

module

module DecOp4( clk, istrWord, regCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idStepPc2, idUCmd ); parameter decEnable64 = 0; parameter decEnable64A = 0; parameter decEnableBJX1 = 1; input clk; input[47:0] istrWord; input[15:0] regCsFl; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[3:0] idStepPc; output[3:0] idStepPc2; output[7:0] idUCmd; reg isOp32; reg isOp8E; reg isOpCE; reg isOpXE; reg opPsDQ; reg opPwDQ; reg opPlDQ; reg opJQ; reg opUseBase16; reg[15:0] opCmdWord; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; reg[3:0] opStepPc; reg[3:0] opStepPc2; reg[3:0] opStepPc2A; reg[3:0] opStepPc2B; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; assign idStepPc = opStepPc; assign idStepPc2 = opStepPc2; reg[4:0] tOpDecXfrm; reg[3:0] tOpDecXfrmZx; reg[6:0] opRegN_Dfl; reg[6:0] opRegM_Dfl; reg[6:0] opRegO_Dfl; reg[6:0] opRegM_CR; reg[6:0] opRegM_SR; reg[6:0] opRegN_FR; reg[6:0] opRegM_FR; reg[6:0] opRegO_FR; reg[6:0] opRegS_FR; reg[6:0] opRegT_FR; reg[6:0] opRegN_N3; reg[6:0] opRegM_N3; reg[31:0] opImm_Zx4; reg[31:0] opImm_Zx8; reg[31:0] opImm_Sx8; reg[31:0] opImm_Sx12; reg opIsRegM_CR; reg opIsRegM_SR; wire[6:0] opRegXeN; wire[6:0] opRegXeS; wire[6:0] opRegXeT; wire[31:0] opImmXe; wire[7:0] opUCmdXe; DecOp4_XE decXe(istrWord[31:0], opRegXeN, opRegXeS, opRegXeT, opImmXe, opUCmdXe); always @* begin opStepPc = 2; opCmdWord=0; opUCmd=UCMD_UDBRK; opImm=0; isOp32=0; isOp8E=0; isOpCE=0; isOpXE=0; opUseBase16=1; opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; tOpDecXfrm=UXFORM_CST; tOpDecXfrmZx=UXFORMZX_SX; if(decEnable64 && regCsFl[5]) begin opJQ=1; opPsDQ=regCsFl[6]; opPwDQ=opPsDQ; opPlDQ=0; end else begin opJQ=0; opPsDQ=0; opPwDQ=0; opPlDQ=0; end opCmdWord=istrWord[15:0]; opStepPc2 = 2; opStepPc2A=2; opStepPc2B=2; if(decEnableBJX1) begin if(istrWord[47:44]==4'h8) begin if( (istrWord[43:40]==4'hA) || (istrWord[43:40]==4'hC) || (istrWord[43:40]==4'hE)) opStepPc2A=4; end if(istrWord[31:28]==4'h8) begin if( (istrWord[27:24]==4'hA) || (istrWord[27:24]==4'hC) || (istrWord[27:24]==4'hE)) opStepPc2B=4; end end casez(opCmdWord[15:0]) 16'h0zz2: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_CR; end 16'h0zz4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz7: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 16'h0z08: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRT; tOpDecXfrm=UXFORM_CST; end 16'h0z18: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETT; tOpDecXfrm=UXFORM_CST; end 16'h0z28: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRMAC; tOpDecXfrm=UXFORM_CST; end 16'h0z38: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_LDTLB; tOpDecXfrm=UXFORM_CST; end 16'h0z48: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRS; tOpDecXfrm=UXFORM_CST; end 16'h0z58: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETS; tOpDecXfrm=UXFORM_CST; end 16'h0z68: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_NOTT; tOpDecXfrm=UXFORM_CST; end 16'h0z09: begin opUCmd=UCMD_NONE; tOpDecXfrm=UXFORM_Z; end 16'h0z19: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_DIV0U; tOpDecXfrm=UXFORM_CST; end 16'h0z29: begin opUCmd=UCMD_ALU_MOVT; tOpDecXfrm=UXFORM_N; end 16'h0z39: begin opUCmd=UCMD_ALU_MOVRT; tOpDecXfrm=UXFORM_N; end 16'h0zzA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_SR; end 16'h0z0B: begin opUCmd=UCMD_RTS; tOpDecXfrm=UXFORM_Z; end 16'h0z1B: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SLEEP; tOpDecXfrm=UXFORM_CST; end 16'h0z2B: begin opUCmd=UCMD_RTE; tOpDecXfrm=UXFORM_Z; end 16'h0z3B: begin opUCmd=UCMD_UDBRK; tOpDecXfrm=UXFORM_Z; opImm=1; if(opCmdWord[11:8]==4'hF) begin opUCmd=UCMD_NONE; opStepPc=0; end end 16'h0z6B: begin opUCmd=UCMD_RTSN; tOpDecXfrm=UXFORM_Z; end 16'h0zzC: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzD: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzE: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h1zzz: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h2zz0: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz1: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz2: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz3: begin opUCmd=UCMD_CASL; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h2zz4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 16'h2zz5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 16'h2zz6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 16'h2zz7: begin opUCmd=UCMD_ALU_DIV0S; tOpDecXfrm=UXFORM_ARI_ST; end 16'h2zz8: begin opUCmd=UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_ST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zz9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzC: begin opUCmd=UCMD_ALU_CMPSTR; tOpDecXfrm=UXFORM_ARI_NST; end 16'h2zzD: begin opUCmd=UCMD_ALU_XTRCT; tOpDecXfrm=UXFORM_ARI_NST; end 16'h2zzE: begin opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h2zzF: begin opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zz0: begin opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz2: begin opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz3: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz4: begin opUCmd=UCMD_ALU_DIV1; tOpDecXfrm=UXFORM_ARI_NST; end 16'h3zz5: begin opUCmd=UCMD_ALU_DMULU; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zz6: begin opUCmd=opPsDQ ? UCMD_CMPQ_HI : UCMD_CMP_HI; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz7: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz8: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzA: begin opUCmd=UCMD_ALU_SUBC; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzB: begin opUCmd=UCMD_ALU_SUBV; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzC: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzD: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zzE: begin opUCmd=UCMD_ALU_ADDC; tOpDecXfrm=UXFORM_ARI_NST; end 16'h3zzF: begin opUCmd=UCMD_ALU_ADDV; tOpDecXfrm=UXFORM_ARI_NST; end 16'h4z00: begin opUCmd=UCMD_ALU_SHLL; tOpDecXfrm=UXFORM_N; end 16'h4z10: begin opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N; end 16'h4z20: begin opUCmd=UCMD_ALU_SHAL; tOpDecXfrm=UXFORM_N; end 16'h4z01: begin opUCmd=UCMD_ALU_SHLR; tOpDecXfrm=UXFORM_N; end 16'h4z11: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_M; end 16'h4z21: begin opUCmd=UCMD_ALU_SHAR; tOpDecXfrm=UXFORM_N; end 16'h4zz2: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_SR; end 16'h4zz3: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_CR; end 16'h4z04: begin opUCmd=UCMD_ALU_ROTL; tOpDecXfrm=UXFORM_N; end 16'h4z24: begin opUCmd=UCMD_ALU_ROTCL; tOpDecXfrm=UXFORM_N; end 16'h4z05: begin opUCmd=UCMD_ALU_ROTR; tOpDecXfrm=UXFORM_N; end 16'h4z15: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_M; end 16'h4z25: begin opUCmd=UCMD_ALU_ROTCR; tOpDecXfrm=UXFORM_N; end 16'h4zz6: begin opUCmd = opJQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RS; end 16'h4zz7: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RC; end 16'h4z08: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=2; end 16'h4z18: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=8; end 16'h4z28: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=16; end 16'h4z09: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-2; end 16'h4z19: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-8; end 16'h4z29: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-16; end 16'h4zzA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_RS; end 16'h4z0B: begin opUCmd=UCMD_JSR; tOpDecXfrm=UXFORM_M; end 16'h4z2B: begin opUCmd=UCMD_JMP; tOpDecXfrm=UXFORM_M; end 16'h4z3B: begin end 16'h4z4B: begin opUCmd=UCMD_JSRN; tOpDecXfrm=UXFORM_M; end 16'h4zzC: begin opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzD: begin opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzE: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_RC; end 16'h5zzz: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h6zz0: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz1: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz2: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz3: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zz4: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 16'h6zz5: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 16'h6zz6: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 16'h6zz7: begin opUCmd=UCMD_ALU_NOT; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zz8: begin opUCmd=UCMD_ALU_SWAPB; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zz9: begin opUCmd=UCMD_ALU_SWAPW; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzA: begin opUCmd=UCMD_ALU_NEGC; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzB: begin opUCmd=UCMD_ALU_NEG; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzC: begin opUCmd=UCMD_ALU_EXTUB; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzD: begin opUCmd=UCMD_ALU_EXTUW; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzE: begin opUCmd=UCMD_ALU_EXTSB; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzF: begin opUCmd=UCMD_ALU_EXTSW; tOpDecXfrm=UXFORM_ARI_NS; end 16'h7zzz: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI; end 16'h80zz: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 16'h81zz: begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 16'h82zz: begin opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8; end 16'h83zz: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MR3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_RM3; end end 16'h84zz: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 16'h85zz: begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 16'h86zz: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MF3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_FM3; end end 16'h87zz: begin end 16'h88zz: begin opUCmd=UCMD_CMP_EQ; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'h89zz: begin opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Azz: begin if(decEnableBJX1) begin opRegN=UREG_R0; opUCmd=UCMD_MOV_RI; opImm={istrWord[7] ? 8'hFF : 8'h00, istrWord[7:0], istrWord[31:16]}; tOpDecXfrm=UXFORM_CST; end end 16'h8Bzz: begin opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Czz: begin end 16'h8Dzz: begin opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Ezz: begin if(decEnableBJX1) begin isOpXE = 1; opStepPc = 4; end end 16'h8Fzz: begin opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8; end 16'h9zzz: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCW; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_CST; end 16'hAzzz: begin opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12; end 16'hBzzz: begin opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12; end 16'hC0zz: begin if(opJQ) begin opUCmd=UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM; end else begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 16'hC1zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 16'hC2zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 16'hC4zz: begin if(opJQ) begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR; end else begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 16'hC5zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 16'hC6zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 16'hC8zz: begin opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_I8R0; end 16'hC9zz: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCAzz: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCBzz: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hDzzz: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCL; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_CST; end 16'hEzzz: begin opUCmd=UCMD_MOV_RI; tOpDecXfrm=UXFORM_ARI_NNI; end 16'hFzz0: begin opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz1: begin opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz2: begin opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz4: begin opUCmd=UCMD_FPU_CMPEQ; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz5: begin opUCmd=UCMD_FPU_CMPGT; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz6: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_RF; end 16'hFzz7: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_FR; end 16'hFzz8: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_RF; end 16'hFzz9: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RFI; end 16'hFzzA: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_FR; end default: begin end endcase opRegN_Dfl = {3'b000, opCmdWord[11:8]}; opRegM_Dfl = {3'b000, opCmdWord[ 7:4]}; opRegO_Dfl = {3'b000, opCmdWord[ 3:0]}; if(opCmdWord[11]) opRegM_CR={3'h2, 1'b0, opCmdWord[6:4]}; else opRegM_CR={3'h7, opCmdWord[7:4]}; opRegM_SR={3'h6, opCmdWord[7:4]}; opRegN_FR = {3'h4, opCmdWord[11:8]}; opRegM_FR = {3'h4, opCmdWord[ 7:4]}; opRegO_FR = {3'h4, opCmdWord[ 3:0]}; opRegN_N3 = (opCmdWord[6:4]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[6:4]}; opRegM_N3 = (opCmdWord[2:0]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[2:0]}; opImm_Zx4 = {28'h0, opCmdWord[ 3:0]}; opImm_Zx8 = {24'h0, opCmdWord[ 7:0]}; opImm_Sx8 = {opCmdWord[ 7] ? 24'hFFFFFF : 24'h000000, opCmdWord [ 7:0]}; opImm_Sx12 = {opCmdWord[11] ? 20'hFFFFF : 20'h00000 , opCmdWord [11:0]}; case(tOpDecXfrm) UXFORM_CST: begin end UXFORM_N: begin opRegN=opRegN_Dfl; opRegS=opRegN; end UXFORM_MOV_NS: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_MOV_NSO: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_R0; opImm=0; end UXFORM_MOV_NSJ: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opImm = opImm_Zx4; end UXFORM_MOV_NSDEC: begin case(tOpDecXfrmZx) UXFORMZX_PDEC: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_MR_MEMDEC; end UXFORMZX_PINC: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_FRD: begin opRegN=opRegN_Dfl; opRegS=opRegM_FR; opRegT=UREG_MR_MEMDEC; end UXFORMZX_RFI: begin opRegN=opRegN_FR; opRegS=opRegM_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_RS: begin opRegN=opRegM_SR; opRegS=opRegN_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_RC: begin opRegN=opRegM_CR; opRegS=opRegN_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_SR: begin opRegN=opRegN_Dfl; opRegS=opRegM_SR; opRegT=UREG_MR_MEMDEC; end UXFORMZX_CR: begin opRegN=opRegN_Dfl; opRegS=opRegM_CR; opRegT=UREG_MR_MEMDEC; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_FPARI_NS: begin opRegN=opRegN_FR; opRegS=opRegM_FR; end UXFORM_ARI_NS: begin case(tOpDecXfrmZx) UXFORMZX_RR: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORMZX_FF: begin opRegN=opRegN_FR; opRegS=opRegM_FR; end UXFORMZX_RS: begin opRegN=opRegM_SR; opRegS=opRegN_Dfl; end UXFORMZX_RC: begin opRegN=opRegM_CR; opRegS=opRegN_Dfl; end UXFORMZX_SR: begin opRegN=opRegN_Dfl; opRegS=opRegM_SR; end UXFORMZX_CR: begin opRegN=opRegN_Dfl; opRegS=opRegM_CR; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_ARI_NST: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=opRegM_Dfl; end UXFORM_CMP_ST: begin opRegS=opRegN_Dfl; opRegT=opRegM_Dfl; end UXFORM_ARI_ST: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_ARI_NNI: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; opImm=opImm_Sx8; end UXFORM_BR_D8: begin opImm = opImm_Sx8; end UXFORM_BR_D12: begin opImm = opImm_Sx12; end UXFORM_ARI_I8R0: begin opRegN=UREG_R0; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm_Zx8; end UXFORM_N_C: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; end UXFORM_MOV_GD8R0: begin case(tOpDecXfrmZx) UXFORMZX_RM: begin opRegN=UREG_GBR; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm_Zx8; end UXFORMZX_MR: begin opRegN=UREG_R0; opRegS=UREG_GBR; opRegT=UREG_MR_IMM; opImm=opImm_Zx8; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_MOV_SP4RN: begin case(tOpDecXfrmZx) UXFORMZX_RM: begin opRegN=UREG_R15; opRegS=opRegM_Dfl; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_MR: begin opRegN=opRegM_Dfl; opRegS=UREG_R15; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_RM3: begin opRegN=UREG_R15; opRegS=opRegN_N3; opRegT=UREG_MR_IMM; opImm[3:0]=opCmdWord[3:0]; opImm[31:4]=1; end UXFORMZX_MR3: begin opRegN=opRegN_N3; opRegS=UREG_R15; opRegT=UREG_MR_IMM; opImm[3:0]=opCmdWord[3:0]; opImm[31:4]=1; end UXFORMZX_FM3: begin opRegN=UREG_R15; opRegS={3'h4, 1'b1, opCmdWord[6:4]}; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_MF3: begin opRegN={3'h4, 1'b1, opCmdWord[6:4]}; opRegS=UREG_R15; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_RM0: begin opRegN=opRegM_Dfl; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_MR0: begin opRegN=UREG_R0; opRegS=opRegM_Dfl; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase if(isOpXE) begin opRegN=opRegXeN; opRegS=opRegXeS; opRegT=opRegXeT; opImm=opImmXe; opUCmd=opUCmdXe; opStepPc2=opStepPc2A; end else begin opStepPc2=opStepPc2B; end end endmodule

module DecOp4( clk, istrWord, regCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idStepPc2, idUCmd );

parameter decEnable64 = 0; parameter decEnable64A = 0; parameter decEnableBJX1 = 1; input clk; input[47:0] istrWord; input[15:0] regCsFl; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[3:0] idStepPc; output[3:0] idStepPc2; output[7:0] idUCmd; reg isOp32; reg isOp8E; reg isOpCE; reg isOpXE; reg opPsDQ; reg opPwDQ; reg opPlDQ; reg opJQ; reg opUseBase16; reg[15:0] opCmdWord; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; reg[3:0] opStepPc; reg[3:0] opStepPc2; reg[3:0] opStepPc2A; reg[3:0] opStepPc2B; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; assign idStepPc = opStepPc; assign idStepPc2 = opStepPc2; reg[4:0] tOpDecXfrm; reg[3:0] tOpDecXfrmZx; reg[6:0] opRegN_Dfl; reg[6:0] opRegM_Dfl; reg[6:0] opRegO_Dfl; reg[6:0] opRegM_CR; reg[6:0] opRegM_SR; reg[6:0] opRegN_FR; reg[6:0] opRegM_FR; reg[6:0] opRegO_FR; reg[6:0] opRegS_FR; reg[6:0] opRegT_FR; reg[6:0] opRegN_N3; reg[6:0] opRegM_N3; reg[31:0] opImm_Zx4; reg[31:0] opImm_Zx8; reg[31:0] opImm_Sx8; reg[31:0] opImm_Sx12; reg opIsRegM_CR; reg opIsRegM_SR; wire[6:0] opRegXeN; wire[6:0] opRegXeS; wire[6:0] opRegXeT; wire[31:0] opImmXe; wire[7:0] opUCmdXe; DecOp4_XE decXe(istrWord[31:0], opRegXeN, opRegXeS, opRegXeT, opImmXe, opUCmdXe); always @* begin opStepPc = 2; opCmdWord=0; opUCmd=UCMD_UDBRK; opImm=0; isOp32=0; isOp8E=0; isOpCE=0; isOpXE=0; opUseBase16=1; opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; tOpDecXfrm=UXFORM_CST; tOpDecXfrmZx=UXFORMZX_SX; if(decEnable64 && regCsFl[5]) begin opJQ=1; opPsDQ=regCsFl[6]; opPwDQ=opPsDQ; opPlDQ=0; end else begin opJQ=0; opPsDQ=0; opPwDQ=0; opPlDQ=0; end opCmdWord=istrWord[15:0]; opStepPc2 = 2; opStepPc2A=2; opStepPc2B=2; if(decEnableBJX1) begin if(istrWord[47:44]==4'h8) begin if( (istrWord[43:40]==4'hA) || (istrWord[43:40]==4'hC) || (istrWord[43:40]==4'hE)) opStepPc2A=4; end if(istrWord[31:28]==4'h8) begin if( (istrWord[27:24]==4'hA) || (istrWord[27:24]==4'hC) || (istrWord[27:24]==4'hE)) opStepPc2B=4; end end casez(opCmdWord[15:0]) 16'h0zz2: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_CR; end 16'h0zz4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz7: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 16'h0z08: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRT; tOpDecXfrm=UXFORM_CST; end 16'h0z18: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETT; tOpDecXfrm=UXFORM_CST; end 16'h0z28: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRMAC; tOpDecXfrm=UXFORM_CST; end 16'h0z38: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_LDTLB; tOpDecXfrm=UXFORM_CST; end 16'h0z48: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRS; tOpDecXfrm=UXFORM_CST; end 16'h0z58: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETS; tOpDecXfrm=UXFORM_CST; end 16'h0z68: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_NOTT; tOpDecXfrm=UXFORM_CST; end 16'h0z09: begin opUCmd=UCMD_NONE; tOpDecXfrm=UXFORM_Z; end 16'h0z19: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_DIV0U; tOpDecXfrm=UXFORM_CST; end 16'h0z29: begin opUCmd=UCMD_ALU_MOVT; tOpDecXfrm=UXFORM_N; end 16'h0z39: begin opUCmd=UCMD_ALU_MOVRT; tOpDecXfrm=UXFORM_N; end 16'h0zzA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_SR; end 16'h0z0B: begin opUCmd=UCMD_RTS; tOpDecXfrm=UXFORM_Z; end 16'h0z1B: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SLEEP; tOpDecXfrm=UXFORM_CST; end 16'h0z2B: begin opUCmd=UCMD_RTE; tOpDecXfrm=UXFORM_Z; end 16'h0z3B: begin opUCmd=UCMD_UDBRK; tOpDecXfrm=UXFORM_Z; opImm=1; if(opCmdWord[11:8]==4'hF) begin opUCmd=UCMD_NONE; opStepPc=0; end end 16'h0z6B: begin opUCmd=UCMD_RTSN; tOpDecXfrm=UXFORM_Z; end 16'h0zzC: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzD: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzE: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h1zzz: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h2zz0: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz1: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz2: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz3: begin opUCmd=UCMD_CASL; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h2zz4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 16'h2zz5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 16'h2zz6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 16'h2zz7: begin opUCmd=UCMD_ALU_DIV0S; tOpDecXfrm=UXFORM_ARI_ST; end 16'h2zz8: begin opUCmd=UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_ST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zz9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzC: begin opUCmd=UCMD_ALU_CMPSTR; tOpDecXfrm=UXFORM_ARI_NST; end 16'h2zzD: begin opUCmd=UCMD_ALU_XTRCT; tOpDecXfrm=UXFORM_ARI_NST; end 16'h2zzE: begin opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h2zzF: begin opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zz0: begin opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz2: begin opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz3: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz4: begin opUCmd=UCMD_ALU_DIV1; tOpDecXfrm=UXFORM_ARI_NST; end 16'h3zz5: begin opUCmd=UCMD_ALU_DMULU; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zz6: begin opUCmd=opPsDQ ? UCMD_CMPQ_HI : UCMD_CMP_HI; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz7: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz8: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzA: begin opUCmd=UCMD_ALU_SUBC; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzB: begin opUCmd=UCMD_ALU_SUBV; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzC: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zzD: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zzE: begin opUCmd=UCMD_ALU_ADDC; tOpDecXfrm=UXFORM_ARI_NST; end 16'h3zzF: begin opUCmd=UCMD_ALU_ADDV; tOpDecXfrm=UXFORM_ARI_NST; end 16'h4z00: begin opUCmd=UCMD_ALU_SHLL; tOpDecXfrm=UXFORM_N; end 16'h4z10: begin opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N; end 16'h4z20: begin opUCmd=UCMD_ALU_SHAL; tOpDecXfrm=UXFORM_N; end 16'h4z01: begin opUCmd=UCMD_ALU_SHLR; tOpDecXfrm=UXFORM_N; end 16'h4z11: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_M; end 16'h4z21: begin opUCmd=UCMD_ALU_SHAR; tOpDecXfrm=UXFORM_N; end 16'h4zz2: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_SR; end 16'h4zz3: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_CR; end 16'h4z04: begin opUCmd=UCMD_ALU_ROTL; tOpDecXfrm=UXFORM_N; end 16'h4z24: begin opUCmd=UCMD_ALU_ROTCL; tOpDecXfrm=UXFORM_N; end 16'h4z05: begin opUCmd=UCMD_ALU_ROTR; tOpDecXfrm=UXFORM_N; end 16'h4z15: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_M; end 16'h4z25: begin opUCmd=UCMD_ALU_ROTCR; tOpDecXfrm=UXFORM_N; end 16'h4zz6: begin opUCmd = opJQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RS; end 16'h4zz7: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RC; end 16'h4z08: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=2; end 16'h4z18: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=8; end 16'h4z28: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=16; end 16'h4z09: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-2; end 16'h4z19: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-8; end 16'h4z29: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-16; end 16'h4zzA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_RS; end 16'h4z0B: begin opUCmd=UCMD_JSR; tOpDecXfrm=UXFORM_M; end 16'h4z2B: begin opUCmd=UCMD_JMP; tOpDecXfrm=UXFORM_M; end 16'h4z3B: begin end 16'h4z4B: begin opUCmd=UCMD_JSRN; tOpDecXfrm=UXFORM_M; end 16'h4zzC: begin opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzD: begin opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzE: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; tOpDecXfrmZx=UXFORMZX_RC; end 16'h5zzz: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h6zz0: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz1: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz2: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz3: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zz4: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 16'h6zz5: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 16'h6zz6: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 16'h6zz7: begin opUCmd=UCMD_ALU_NOT; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zz8: begin opUCmd=UCMD_ALU_SWAPB; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zz9: begin opUCmd=UCMD_ALU_SWAPW; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzA: begin opUCmd=UCMD_ALU_NEGC; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzB: begin opUCmd=UCMD_ALU_NEG; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzC: begin opUCmd=UCMD_ALU_EXTUB; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzD: begin opUCmd=UCMD_ALU_EXTUW; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzE: begin opUCmd=UCMD_ALU_EXTSB; tOpDecXfrm=UXFORM_ARI_NS; end 16'h6zzF: begin opUCmd=UCMD_ALU_EXTSW; tOpDecXfrm=UXFORM_ARI_NS; end 16'h7zzz: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI; end 16'h80zz: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 16'h81zz: begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 16'h82zz: begin opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8; end 16'h83zz: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MR3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_RM3; end end 16'h84zz: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 16'h85zz: begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 16'h86zz: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MF3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_FM3; end end 16'h87zz: begin end 16'h88zz: begin opUCmd=UCMD_CMP_EQ; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'h89zz: begin opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Azz: begin if(decEnableBJX1) begin opRegN=UREG_R0; opUCmd=UCMD_MOV_RI; opImm={istrWord[7] ? 8'hFF : 8'h00, istrWord[7:0], istrWord[31:16]}; tOpDecXfrm=UXFORM_CST; end end 16'h8Bzz: begin opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Czz: begin end 16'h8Dzz: begin opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Ezz: begin if(decEnableBJX1) begin isOpXE = 1; opStepPc = 4; end end 16'h8Fzz: begin opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8; end 16'h9zzz: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCW; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_CST; end 16'hAzzz: begin opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12; end 16'hBzzz: begin opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12; end 16'hC0zz: begin if(opJQ) begin opUCmd=UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM; end else begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 16'hC1zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 16'hC2zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 16'hC4zz: begin if(opJQ) begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR; end else begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 16'hC5zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 16'hC6zz: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 16'hC8zz: begin opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_I8R0; end 16'hC9zz: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCAzz: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCBzz: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hDzzz: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCL; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_CST; end 16'hEzzz: begin opUCmd=UCMD_MOV_RI; tOpDecXfrm=UXFORM_ARI_NNI; end 16'hFzz0: begin opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz1: begin opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz2: begin opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz4: begin opUCmd=UCMD_FPU_CMPEQ; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz5: begin opUCmd=UCMD_FPU_CMPGT; tOpDecXfrm=UXFORM_FPARI_NS; end 16'hFzz6: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_RF; end 16'hFzz7: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_FR; end 16'hFzz8: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_RF; end 16'hFzz9: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RFI; end 16'hFzzA: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_FR; end default: begin end endcase opRegN_Dfl = {3'b000, opCmdWord[11:8]}; opRegM_Dfl = {3'b000, opCmdWord[ 7:4]}; opRegO_Dfl = {3'b000, opCmdWord[ 3:0]}; if(opCmdWord[11]) opRegM_CR={3'h2, 1'b0, opCmdWord[6:4]}; else opRegM_CR={3'h7, opCmdWord[7:4]}; opRegM_SR={3'h6, opCmdWord[7:4]}; opRegN_FR = {3'h4, opCmdWord[11:8]}; opRegM_FR = {3'h4, opCmdWord[ 7:4]}; opRegO_FR = {3'h4, opCmdWord[ 3:0]}; opRegN_N3 = (opCmdWord[6:4]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[6:4]}; opRegM_N3 = (opCmdWord[2:0]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[2:0]}; opImm_Zx4 = {28'h0, opCmdWord[ 3:0]}; opImm_Zx8 = {24'h0, opCmdWord[ 7:0]}; opImm_Sx8 = {opCmdWord[ 7] ? 24'hFFFFFF : 24'h000000, opCmdWord [ 7:0]}; opImm_Sx12 = {opCmdWord[11] ? 20'hFFFFF : 20'h00000 , opCmdWord [11:0]}; case(tOpDecXfrm) UXFORM_CST: begin end UXFORM_N: begin opRegN=opRegN_Dfl; opRegS=opRegN; end UXFORM_MOV_NS: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_MOV_NSO: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_R0; opImm=0; end UXFORM_MOV_NSJ: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opImm = opImm_Zx4; end UXFORM_MOV_NSDEC: begin case(tOpDecXfrmZx) UXFORMZX_PDEC: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_MR_MEMDEC; end UXFORMZX_PINC: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_FRD: begin opRegN=opRegN_Dfl; opRegS=opRegM_FR; opRegT=UREG_MR_MEMDEC; end UXFORMZX_RFI: begin opRegN=opRegN_FR; opRegS=opRegM_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_RS: begin opRegN=opRegM_SR; opRegS=opRegN_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_RC: begin opRegN=opRegM_CR; opRegS=opRegN_Dfl; opRegT=UREG_MR_MEMINC; end UXFORMZX_SR: begin opRegN=opRegN_Dfl; opRegS=opRegM_SR; opRegT=UREG_MR_MEMDEC; end UXFORMZX_CR: begin opRegN=opRegN_Dfl; opRegS=opRegM_CR; opRegT=UREG_MR_MEMDEC; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_FPARI_NS: begin opRegN=opRegN_FR; opRegS=opRegM_FR; end UXFORM_ARI_NS: begin case(tOpDecXfrmZx) UXFORMZX_RR: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORMZX_FF: begin opRegN=opRegN_FR; opRegS=opRegM_FR; end UXFORMZX_RS: begin opRegN=opRegM_SR; opRegS=opRegN_Dfl; end UXFORMZX_RC: begin opRegN=opRegM_CR; opRegS=opRegN_Dfl; end UXFORMZX_SR: begin opRegN=opRegN_Dfl; opRegS=opRegM_SR; end UXFORMZX_CR: begin opRegN=opRegN_Dfl; opRegS=opRegM_CR; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_ARI_NST: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=opRegM_Dfl; end UXFORM_CMP_ST: begin opRegS=opRegN_Dfl; opRegT=opRegM_Dfl; end UXFORM_ARI_ST: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_ARI_NNI: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; opImm=opImm_Sx8; end UXFORM_BR_D8: begin opImm = opImm_Sx8; end UXFORM_BR_D12: begin opImm = opImm_Sx12; end UXFORM_ARI_I8R0: begin opRegN=UREG_R0; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm_Zx8; end UXFORM_N_C: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; end UXFORM_MOV_GD8R0: begin case(tOpDecXfrmZx) UXFORMZX_RM: begin opRegN=UREG_GBR; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm_Zx8; end UXFORMZX_MR: begin opRegN=UREG_R0; opRegS=UREG_GBR; opRegT=UREG_MR_IMM; opImm=opImm_Zx8; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_MOV_SP4RN: begin case(tOpDecXfrmZx) UXFORMZX_RM: begin opRegN=UREG_R15; opRegS=opRegM_Dfl; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_MR: begin opRegN=opRegM_Dfl; opRegS=UREG_R15; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_RM3: begin opRegN=UREG_R15; opRegS=opRegN_N3; opRegT=UREG_MR_IMM; opImm[3:0]=opCmdWord[3:0]; opImm[31:4]=1; end UXFORMZX_MR3: begin opRegN=opRegN_N3; opRegS=UREG_R15; opRegT=UREG_MR_IMM; opImm[3:0]=opCmdWord[3:0]; opImm[31:4]=1; end UXFORMZX_FM3: begin opRegN=UREG_R15; opRegS={3'h4, 1'b1, opCmdWord[6:4]}; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_MF3: begin opRegN={3'h4, 1'b1, opCmdWord[6:4]}; opRegS=UREG_R15; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_RM0: begin opRegN=opRegM_Dfl; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end UXFORMZX_MR0: begin opRegN=UREG_R0; opRegS=opRegM_Dfl; opRegT=UREG_MR_IMM; opImm=opImm_Zx4; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase if(isOpXE) begin opRegN=opRegXeN; opRegS=opRegXeS; opRegT=opRegXeT; opImm=opImmXe; opUCmd=opUCmdXe; opStepPc2=opStepPc2A; end else begin opStepPc2=opStepPc2B; end end endmodule

data/full_repos/permissive/99182535/bjx1c32b/DecOp4_1.v

DecOp4_1.v

v

[]

[]

[]

line:34: before: "parameter"

1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/DecOp4_1.v:7: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1c32b/DecOp4_1.v:8: Cannot find include file: DecOp4_XE.v\n`include "DecOp4_XE.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'

module

module DecOp4( clk, istrWord, regCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idStepPc2, idUCmd ); parameter decEnable64 = 0; parameter decEnable64A = 0; parameter decEnableBJX1 = 1; input clk; input[47:0] istrWord; input[15:0] regCsFl; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[3:0] idStepPc; output[3:0] idStepPc2; output[7:0] idUCmd; reg isOp32; reg isOp8E; reg isOpCE; reg isOpXE; reg opPsDQ; reg opPwDQ; reg opPlDQ; reg opJQ; reg opUseBase16; reg[15:0] opCmdWord; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; reg[3:0] opStepPc; reg[3:0] opStepPc2; reg[3:0] opStepPc2A; reg[3:0] opStepPc2B; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; assign idStepPc = opStepPc; assign idStepPc2 = opStepPc2; reg[4:0] tOpDecXfrm; reg[2:0] tOpDecXfrmZx; reg[6:0] opRegN_Dfl; reg[6:0] opRegM_Dfl; reg[6:0] opRegO_Dfl; reg[6:0] opRegM_CR; reg[6:0] opRegM_SR; reg[6:0] opRegN_FR; reg[6:0] opRegM_FR; reg[6:0] opRegO_FR; reg[6:0] opRegS_FR; reg[6:0] opRegT_FR; reg[6:0] opRegN_N3; reg[6:0] opRegM_N3; reg[31:0] opImm_Zx4; reg[31:0] opImm_Zx8; reg[31:0] opImm_Sx8; reg[31:0] opImm_Sx12; reg opIsRegM_CR; reg opIsRegM_SR; wire[6:0] opRegXeN; wire[6:0] opRegXeS; wire[6:0] opRegXeT; wire[31:0] opImmXe; wire[7:0] opUCmdXe; DecOp4_XE decXe(istrWord[31:0], opRegXeN, opRegXeS, opRegXeT, opImmXe, opUCmdXe); always @* begin opStepPc = 2; opCmdWord=0; opUCmd=UCMD_UDBRK; opImm=0; isOp32=0; isOp8E=0; isOpCE=0; isOpXE=0; opUseBase16=1; opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; tOpDecXfrm=UXFORM_INVALID; tOpDecXfrmZx=UXFORMZX_SX; if(decEnable64 && regCsFl[5]) begin opJQ=1; opPsDQ=regCsFl[6]; opPwDQ=opPsDQ; opPlDQ=0; end else begin opJQ=0; opPsDQ=0; opPwDQ=0; opPlDQ=0; end opCmdWord=istrWord[15:0]; opStepPc2 = 2; opStepPc2A=2; opStepPc2B=2; if(decEnableBJX1) begin if(istrWord[47:44]==4'h8) begin if( (istrWord[43:40]==4'hA) || (istrWord[43:40]==4'hC) || (istrWord[43:40]==4'hE)) opStepPc2A=4; end if(istrWord[31:28]==4'h8) begin if( (istrWord[27:24]==4'hA) || (istrWord[27:24]==4'hC) || (istrWord[27:24]==4'hE)) opStepPc2B=4; end end casez(opCmdWord[15:12]) 4'h0: case(opCmdWord[3:0]) 4'h2: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_CR; end 4'h4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h7: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 4'h8: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRT; tOpDecXfrm=UXFORM_CST; end 4'h1: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETT; tOpDecXfrm=UXFORM_CST; end 4'h2: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRMAC; tOpDecXfrm=UXFORM_CST; end 4'h3: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_LDTLB; tOpDecXfrm=UXFORM_CST; end 4'h4: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRS; tOpDecXfrm=UXFORM_CST; end 4'h5: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETS; tOpDecXfrm=UXFORM_CST; end 4'h6: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_NOTT; tOpDecXfrm=UXFORM_CST; end default: begin end endcase 4'h9: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_NONE; tOpDecXfrm=UXFORM_Z; end 4'h1: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_DIV0U; tOpDecXfrm=UXFORM_CST; end 4'h2: begin opUCmd=UCMD_ALU_MOVT; tOpDecXfrm=UXFORM_N; end 4'h3: begin opUCmd=UCMD_ALU_MOVRT; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'hA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_SR; end 4'hB: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_RTS; tOpDecXfrm=UXFORM_Z; end 4'h1: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SLEEP; tOpDecXfrm=UXFORM_CST; end 4'h2: begin opUCmd=UCMD_RTE; tOpDecXfrm=UXFORM_Z; end 4'h3: begin opUCmd=UCMD_UDBRK; tOpDecXfrm=UXFORM_Z; opImm=1; if(opCmdWord[11:8]==4'hF) begin opUCmd=UCMD_NONE; opStepPc=0; end end 4'h6: begin opUCmd=UCMD_RTSN; tOpDecXfrm=UXFORM_Z; end default: begin end endcase 4'hC: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 4'hD: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 4'hE: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end default: begin end endcase 4'h1: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSJ; end 4'h2: case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS; end 4'h1: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NS; end 4'h2: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; end 4'h3: begin opUCmd=UCMD_CASL; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 4'h5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 4'h6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 4'h7: begin opUCmd=UCMD_ALU_DIV0S; tOpDecXfrm=UXFORM_ARI_ST; end 4'h8: begin opUCmd=UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_ST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'h9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hC: begin opUCmd=UCMD_ALU_CMPSTR; tOpDecXfrm=UXFORM_ARI_NST; end 4'hD: begin opUCmd=UCMD_ALU_XTRCT; tOpDecXfrm=UXFORM_ARI_NST; end 4'hE: begin opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST; end 4'hF: begin opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST; end default: begin end endcase 4'h3: case(opCmdWord[3:0]) 4'h0: begin opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ; tOpDecXfrm=UXFORM_CMP_ST; end 4'h2: begin opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS; tOpDecXfrm=UXFORM_CMP_ST; end 4'h3: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_CMP_ST; end 4'h4: begin opUCmd=UCMD_ALU_DIV1; tOpDecXfrm=UXFORM_ARI_NST; end 4'h5: begin opUCmd=UCMD_ALU_DMULU; tOpDecXfrm=UXFORM_ARI_ST; end 4'h6: begin opUCmd=opPsDQ ? UCMD_CMPQ_HI : UCMD_CMP_HI; tOpDecXfrm=UXFORM_CMP_ST; end 4'h7: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_CMP_ST; end 4'h8: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hA: begin opUCmd=UCMD_ALU_SUBC; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hB: begin opUCmd=UCMD_ALU_SUBV; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hC: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hD: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 4'hE: begin opUCmd=UCMD_ALU_ADDC; tOpDecXfrm=UXFORM_ARI_NST; end 4'hF: begin opUCmd=UCMD_ALU_ADDV; tOpDecXfrm=UXFORM_ARI_NST; end default: begin end endcase 4'h4: case(opCmdWord[3:0]) 4'h0: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLL; tOpDecXfrm=UXFORM_N; end 4'h1: begin opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N; end 4'h2: begin opUCmd=UCMD_ALU_SHAL; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h1: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLR; tOpDecXfrm=UXFORM_N; end 4'h1: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_M; end 4'h2: begin opUCmd=UCMD_ALU_SHAR; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h2: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_SR; end 4'h3: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_CR; end 4'h4: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_ROTL; tOpDecXfrm=UXFORM_N; end 4'h2: begin opUCmd=UCMD_ALU_ROTCL; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h5: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_ROTR; tOpDecXfrm=UXFORM_N; end 4'h1: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_M; end 4'h2: begin opUCmd=UCMD_ALU_ROTCR; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h6: begin opUCmd = opJQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_RS; end 4'h7: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_RC; end 4'h8: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=2; end 4'h1: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=8; end 4'h2: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=16; end default: begin end endcase 4'h9: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-2; end 4'h1: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-8; end 4'h2: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-16; end default: begin end endcase 4'hA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_RS; end 4'hB: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_JSR; tOpDecXfrm=UXFORM_M; end 4'h2: begin opUCmd=UCMD_JMP; tOpDecXfrm=UXFORM_M; end 4'h3: begin end 4'h4: begin opUCmd=UCMD_JSRN; tOpDecXfrm=UXFORM_M; end default: begin end endcase 4'hC: begin opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 4'hD: begin opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 4'hE: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_RC; end default: begin end endcase 4'h5: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSJ; end 4'h6: case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 4'h1: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 4'h2: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 4'h3: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; end 4'h4: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 4'h5: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 4'h6: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 4'h7: begin opUCmd=UCMD_ALU_NOT; tOpDecXfrm=UXFORM_ARI_NS; end 4'h8: begin opUCmd=UCMD_ALU_SWAPB; tOpDecXfrm=UXFORM_ARI_NS; end 4'h9: begin opUCmd=UCMD_ALU_SWAPW; tOpDecXfrm=UXFORM_ARI_NS; end 4'hA: begin opUCmd=UCMD_ALU_NEGC; tOpDecXfrm=UXFORM_ARI_NS; end 4'hB: begin opUCmd=UCMD_ALU_NEG; tOpDecXfrm=UXFORM_ARI_NS; end 4'hC: begin opUCmd=UCMD_ALU_EXTUB; tOpDecXfrm=UXFORM_ARI_NS; end 4'hD: begin opUCmd=UCMD_ALU_EXTUW; tOpDecXfrm=UXFORM_ARI_NS; end 4'hE: begin opUCmd=UCMD_ALU_EXTSB; tOpDecXfrm=UXFORM_ARI_NS; end 4'hF: begin opUCmd=UCMD_ALU_EXTSW; tOpDecXfrm=UXFORM_ARI_NS; end default: begin end endcase 4'h7: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI; end 4'h8: case(opCmdWord[11:8]) 4'h0: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 4'h1: begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 4'h2: begin opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8; end 4'h3: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MR3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_RM3; end end 4'h4: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 4'h5: begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 4'h6: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MF3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_FM3; end end 4'h7: begin end 4'h8: begin opUCmd=UCMD_CMP_EQ; tOpDecXfrm=UXFORM_ARI_I8R0; end 4'h9: begin opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8; end 4'hA: begin if(decEnableBJX1) begin opRegN=UREG_R0; opUCmd=UCMD_MOV_RI; opImm={istrWord[7] ? 8'hFF : 8'h00, istrWord[7:0], istrWord[31:16]}; tOpDecXfrm=UXFORM_CST; end end 4'hB: begin opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8; end 4'hC: begin end 4'hD: begin opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8; end 4'hE: begin if(decEnableBJX1) begin isOpXE = 1; opStepPc = 4; end end 4'hF: begin opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8; end default: begin end endcase 4'h9: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCW; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_CST; end 4'hA: begin opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12; end 4'hB: begin opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12; end 4'hC: case(opCmdWord[11:8]) 4'h0: begin if(opJQ) begin opUCmd=UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM; end else begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 4'h1: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 4'h2: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 4'h4: begin if(opJQ) begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR; end else begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 4'h5: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 4'h6: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 4'h8: begin opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_I8R0; end 4'h9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0; end 4'hA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0; end 4'hB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0; end default: begin end endcase 4'hD: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCL; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_CST; end 4'hE: begin opUCmd=UCMD_MOV_RI; tOpDecXfrm=UXFORM_ARI_NNI; end 4'hF: case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h1: begin opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h2: begin opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h4: begin opUCmd=UCMD_FPU_CMPEQ; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h5: begin opUCmd=UCMD_FPU_CMPGT; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h6: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_RF; end 4'h7: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_FR; end 4'h8: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_RF; end 4'h9: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RFI; end 4'hA: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_FR; end default: begin end endcase default: begin end endcase opRegN_Dfl = {3'b000, opCmdWord[11:8]}; opRegM_Dfl = {3'b000, opCmdWord[ 7:4]}; opRegO_Dfl = {3'b000, opCmdWord[ 3:0]}; if(opCmdWord[11]) opRegM_CR={3'h2, 1'b0, opCmdWord[6:4]}; else opRegM_CR={3'h7, opCmdWord[7:4]}; opRegM_SR={3'h6, opCmdWord[7:4]}; opRegN_FR = {3'h4, opCmdWord[11:8]}; opRegM_FR = {3'h4, opCmdWord[ 7:4]}; opRegO_FR = {3'h4, opCmdWord[ 3:0]}; opRegN_N3 = (opCmdWord[6:4]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[6:4]}; opRegM_N3 = (opCmdWord[2:0]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[2:0]}; opImm_Zx4 = {28'h0, opCmdWord[ 3:0]}; opImm_Zx8 = {24'h0, opCmdWord[ 7:0]}; opImm_Sx8 = {opCmdWord[ 7] ? 24'hFFFFFF : 24'h000000, opCmdWord [ 7:0]}; opImm_Sx12 = {opCmdWord[11] ? 20'hFFFFF : 20'h00000 , opCmdWord [11:0]}; if(0) begin opRegN=opRegXeN; opRegS=opRegXeS; opRegT=opRegXeT; opImm=opImmXe; opUCmd=opUCmdXe; opStepPc2=opStepPc2A; end else begin opStepPc2=opStepPc2B; end end endmodule

module DecOp4( clk, istrWord, regCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idStepPc2, idUCmd );

parameter decEnable64 = 0; parameter decEnable64A = 0; parameter decEnableBJX1 = 1; input clk; input[47:0] istrWord; input[15:0] regCsFl; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[3:0] idStepPc; output[3:0] idStepPc2; output[7:0] idUCmd; reg isOp32; reg isOp8E; reg isOpCE; reg isOpXE; reg opPsDQ; reg opPwDQ; reg opPlDQ; reg opJQ; reg opUseBase16; reg[15:0] opCmdWord; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; reg[3:0] opStepPc; reg[3:0] opStepPc2; reg[3:0] opStepPc2A; reg[3:0] opStepPc2B; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; assign idStepPc = opStepPc; assign idStepPc2 = opStepPc2; reg[4:0] tOpDecXfrm; reg[2:0] tOpDecXfrmZx; reg[6:0] opRegN_Dfl; reg[6:0] opRegM_Dfl; reg[6:0] opRegO_Dfl; reg[6:0] opRegM_CR; reg[6:0] opRegM_SR; reg[6:0] opRegN_FR; reg[6:0] opRegM_FR; reg[6:0] opRegO_FR; reg[6:0] opRegS_FR; reg[6:0] opRegT_FR; reg[6:0] opRegN_N3; reg[6:0] opRegM_N3; reg[31:0] opImm_Zx4; reg[31:0] opImm_Zx8; reg[31:0] opImm_Sx8; reg[31:0] opImm_Sx12; reg opIsRegM_CR; reg opIsRegM_SR; wire[6:0] opRegXeN; wire[6:0] opRegXeS; wire[6:0] opRegXeT; wire[31:0] opImmXe; wire[7:0] opUCmdXe; DecOp4_XE decXe(istrWord[31:0], opRegXeN, opRegXeS, opRegXeT, opImmXe, opUCmdXe); always @* begin opStepPc = 2; opCmdWord=0; opUCmd=UCMD_UDBRK; opImm=0; isOp32=0; isOp8E=0; isOpCE=0; isOpXE=0; opUseBase16=1; opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; tOpDecXfrm=UXFORM_INVALID; tOpDecXfrmZx=UXFORMZX_SX; if(decEnable64 && regCsFl[5]) begin opJQ=1; opPsDQ=regCsFl[6]; opPwDQ=opPsDQ; opPlDQ=0; end else begin opJQ=0; opPsDQ=0; opPwDQ=0; opPlDQ=0; end opCmdWord=istrWord[15:0]; opStepPc2 = 2; opStepPc2A=2; opStepPc2B=2; if(decEnableBJX1) begin if(istrWord[47:44]==4'h8) begin if( (istrWord[43:40]==4'hA) || (istrWord[43:40]==4'hC) || (istrWord[43:40]==4'hE)) opStepPc2A=4; end if(istrWord[31:28]==4'h8) begin if( (istrWord[27:24]==4'hA) || (istrWord[27:24]==4'hC) || (istrWord[27:24]==4'hE)) opStepPc2B=4; end end casez(opCmdWord[15:12]) 4'h0: case(opCmdWord[3:0]) 4'h2: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_CR; end 4'h4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h7: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 4'h8: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRT; tOpDecXfrm=UXFORM_CST; end 4'h1: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETT; tOpDecXfrm=UXFORM_CST; end 4'h2: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRMAC; tOpDecXfrm=UXFORM_CST; end 4'h3: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_LDTLB; tOpDecXfrm=UXFORM_CST; end 4'h4: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_CLRS; tOpDecXfrm=UXFORM_CST; end 4'h5: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SETS; tOpDecXfrm=UXFORM_CST; end 4'h6: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_NOTT; tOpDecXfrm=UXFORM_CST; end default: begin end endcase 4'h9: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_NONE; tOpDecXfrm=UXFORM_Z; end 4'h1: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_DIV0U; tOpDecXfrm=UXFORM_CST; end 4'h2: begin opUCmd=UCMD_ALU_MOVT; tOpDecXfrm=UXFORM_N; end 4'h3: begin opUCmd=UCMD_ALU_MOVRT; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'hA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_SR; end 4'hB: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_RTS; tOpDecXfrm=UXFORM_Z; end 4'h1: begin opUCmd=UCMD_ALU_SPOP; opImm[7:0]=UCMDP_ALU_SLEEP; tOpDecXfrm=UXFORM_CST; end 4'h2: begin opUCmd=UCMD_RTE; tOpDecXfrm=UXFORM_Z; end 4'h3: begin opUCmd=UCMD_UDBRK; tOpDecXfrm=UXFORM_Z; opImm=1; if(opCmdWord[11:8]==4'hF) begin opUCmd=UCMD_NONE; opStepPc=0; end end 4'h6: begin opUCmd=UCMD_RTSN; tOpDecXfrm=UXFORM_Z; end default: begin end endcase 4'hC: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 4'hD: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 4'hE: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end default: begin end endcase 4'h1: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSJ; end 4'h2: case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS; end 4'h1: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NS; end 4'h2: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; end 4'h3: begin opUCmd=UCMD_CASL; tOpDecXfrm=UXFORM_MOV_NSO; end 4'h4: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 4'h5: begin opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 4'h6: begin opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PDEC; end 4'h7: begin opUCmd=UCMD_ALU_DIV0S; tOpDecXfrm=UXFORM_ARI_ST; end 4'h8: begin opUCmd=UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_ST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'h9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hC: begin opUCmd=UCMD_ALU_CMPSTR; tOpDecXfrm=UXFORM_ARI_NST; end 4'hD: begin opUCmd=UCMD_ALU_XTRCT; tOpDecXfrm=UXFORM_ARI_NST; end 4'hE: begin opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST; end 4'hF: begin opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST; end default: begin end endcase 4'h3: case(opCmdWord[3:0]) 4'h0: begin opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ; tOpDecXfrm=UXFORM_CMP_ST; end 4'h2: begin opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS; tOpDecXfrm=UXFORM_CMP_ST; end 4'h3: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_CMP_ST; end 4'h4: begin opUCmd=UCMD_ALU_DIV1; tOpDecXfrm=UXFORM_ARI_NST; end 4'h5: begin opUCmd=UCMD_ALU_DMULU; tOpDecXfrm=UXFORM_ARI_ST; end 4'h6: begin opUCmd=opPsDQ ? UCMD_CMPQ_HI : UCMD_CMP_HI; tOpDecXfrm=UXFORM_CMP_ST; end 4'h7: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_CMP_ST; end 4'h8: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hA: begin opUCmd=UCMD_ALU_SUBC; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hB: begin opUCmd=UCMD_ALU_SUBV; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hC: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 4'hD: begin opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST; end 4'hE: begin opUCmd=UCMD_ALU_ADDC; tOpDecXfrm=UXFORM_ARI_NST; end 4'hF: begin opUCmd=UCMD_ALU_ADDV; tOpDecXfrm=UXFORM_ARI_NST; end default: begin end endcase 4'h4: case(opCmdWord[3:0]) 4'h0: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLL; tOpDecXfrm=UXFORM_N; end 4'h1: begin opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N; end 4'h2: begin opUCmd=UCMD_ALU_SHAL; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h1: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLR; tOpDecXfrm=UXFORM_N; end 4'h1: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_M; end 4'h2: begin opUCmd=UCMD_ALU_SHAR; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h2: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_SR; end 4'h3: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_CR; end 4'h4: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_ROTL; tOpDecXfrm=UXFORM_N; end 4'h2: begin opUCmd=UCMD_ALU_ROTCL; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h5: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_ROTR; tOpDecXfrm=UXFORM_N; end 4'h1: begin opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT; tOpDecXfrm=UXFORM_M; end 4'h2: begin opUCmd=UCMD_ALU_ROTCR; tOpDecXfrm=UXFORM_N; end default: begin end endcase 4'h6: begin opUCmd = opJQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_RS; end 4'h7: begin opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOVC_NSDEC; tOpDecXfrmZx=UXFORMZX_RC; end 4'h8: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=2; end 4'h1: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=8; end 4'h2: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=16; end default: begin end endcase 4'h9: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-2; end 4'h1: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-8; end 4'h2: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C; opImm=-16; end default: begin end endcase 4'hA: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_RS; end 4'hB: case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_JSR; tOpDecXfrm=UXFORM_M; end 4'h2: begin opUCmd=UCMD_JMP; tOpDecXfrm=UXFORM_M; end 4'h3: begin end 4'h4: begin opUCmd=UCMD_JSRN; tOpDecXfrm=UXFORM_M; end default: begin end endcase 4'hC: begin opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 4'hD: begin opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 4'hE: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS; tOpDecXfrmZx=UXFORMZX_RC; end default: begin end endcase 4'h5: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSJ; end 4'h6: case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 4'h1: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 4'h2: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 4'h3: begin opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS; end 4'h4: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 4'h5: begin opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 4'h6: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_PINC; end 4'h7: begin opUCmd=UCMD_ALU_NOT; tOpDecXfrm=UXFORM_ARI_NS; end 4'h8: begin opUCmd=UCMD_ALU_SWAPB; tOpDecXfrm=UXFORM_ARI_NS; end 4'h9: begin opUCmd=UCMD_ALU_SWAPW; tOpDecXfrm=UXFORM_ARI_NS; end 4'hA: begin opUCmd=UCMD_ALU_NEGC; tOpDecXfrm=UXFORM_ARI_NS; end 4'hB: begin opUCmd=UCMD_ALU_NEG; tOpDecXfrm=UXFORM_ARI_NS; end 4'hC: begin opUCmd=UCMD_ALU_EXTUB; tOpDecXfrm=UXFORM_ARI_NS; end 4'hD: begin opUCmd=UCMD_ALU_EXTUW; tOpDecXfrm=UXFORM_ARI_NS; end 4'hE: begin opUCmd=UCMD_ALU_EXTSB; tOpDecXfrm=UXFORM_ARI_NS; end 4'hF: begin opUCmd=UCMD_ALU_EXTSW; tOpDecXfrm=UXFORM_ARI_NS; end default: begin end endcase 4'h7: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI; end 4'h8: case(opCmdWord[11:8]) 4'h0: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 4'h1: begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM0; end 4'h2: begin opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8; end 4'h3: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MR3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_RM3; end end 4'h4: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 4'h5: begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR0; end 4'h6: begin tOpDecXfrm=UXFORM_MOV_SP4RN; if(opCmdWord[7]) begin opUCmd=UCMD_MOVL_MR; tOpDecXfrmZx=UXFORMZX_MF3; end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrmZx=UXFORMZX_FM3; end end 4'h7: begin end 4'h8: begin opUCmd=UCMD_CMP_EQ; tOpDecXfrm=UXFORM_ARI_I8R0; end 4'h9: begin opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8; end 4'hA: begin if(decEnableBJX1) begin opRegN=UREG_R0; opUCmd=UCMD_MOV_RI; opImm={istrWord[7] ? 8'hFF : 8'h00, istrWord[7:0], istrWord[31:16]}; tOpDecXfrm=UXFORM_CST; end end 4'hB: begin opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8; end 4'hC: begin end 4'hD: begin opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8; end 4'hE: begin if(decEnableBJX1) begin isOpXE = 1; opStepPc = 4; end end 4'hF: begin opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8; end default: begin end endcase 4'h9: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCW; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_CST; end 4'hA: begin opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12; end 4'hB: begin opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12; end 4'hC: case(opCmdWord[11:8]) 4'h0: begin if(opJQ) begin opUCmd=UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_RM; end else begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 4'h1: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 4'h2: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end end 4'h4: begin if(opJQ) begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_SP4RN; tOpDecXfrmZx=UXFORMZX_MR; end else begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 4'h5: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 4'h6: begin if(opJQ) begin end else begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end end 4'h8: begin opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_I8R0; end 4'h9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0; end 4'hA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0; end 4'hB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0; end default: begin end endcase 4'hD: begin opRegN[3:0]=opCmdWord[11:8]; opRegS=UREG_PCL; opRegT=UREG_ZZR; opImm[7:0]=opCmdWord[ 7:0]; opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_CST; end 4'hE: begin opUCmd=UCMD_MOV_RI; tOpDecXfrm=UXFORM_ARI_NNI; end 4'hF: case(opCmdWord[3:0]) 4'h0: begin opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h1: begin opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h2: begin opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h4: begin opUCmd=UCMD_FPU_CMPEQ; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h5: begin opUCmd=UCMD_FPU_CMPGT; tOpDecXfrm=UXFORM_FPARI_NS; end 4'h6: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_RF; end 4'h7: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; tOpDecXfrmZx=UXFORMZX_FR; end 4'h8: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_RF; end 4'h9: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC; tOpDecXfrmZx=UXFORMZX_RFI; end 4'hA: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; tOpDecXfrmZx=UXFORMZX_FR; end default: begin end endcase default: begin end endcase opRegN_Dfl = {3'b000, opCmdWord[11:8]}; opRegM_Dfl = {3'b000, opCmdWord[ 7:4]}; opRegO_Dfl = {3'b000, opCmdWord[ 3:0]}; if(opCmdWord[11]) opRegM_CR={3'h2, 1'b0, opCmdWord[6:4]}; else opRegM_CR={3'h7, opCmdWord[7:4]}; opRegM_SR={3'h6, opCmdWord[7:4]}; opRegN_FR = {3'h4, opCmdWord[11:8]}; opRegM_FR = {3'h4, opCmdWord[ 7:4]}; opRegO_FR = {3'h4, opCmdWord[ 3:0]}; opRegN_N3 = (opCmdWord[6:4]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[6:4]}; opRegM_N3 = (opCmdWord[2:0]==3'b111) ? UREG_R0 : {3'h0, 1'b1, opCmdWord[2:0]}; opImm_Zx4 = {28'h0, opCmdWord[ 3:0]}; opImm_Zx8 = {24'h0, opCmdWord[ 7:0]}; opImm_Sx8 = {opCmdWord[ 7] ? 24'hFFFFFF : 24'h000000, opCmdWord [ 7:0]}; opImm_Sx12 = {opCmdWord[11] ? 20'hFFFFF : 20'h00000 , opCmdWord [11:0]}; if(0) begin opRegN=opRegXeN; opRegS=opRegXeS; opRegT=opRegXeT; opImm=opImmXe; opUCmd=opUCmdXe; opStepPc2=opStepPc2A; end else begin opStepPc2=opStepPc2B; end end endmodule

data/full_repos/permissive/99182535/bjx1c32b/DecOp4_XE_0.v

DecOp4_XE_0.v

v

[]

[]

[]

line:46: before: "parameter"

1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/DecOp4_XE_0.v:19: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: Exiting due to 1 error(s)\n'

module

module DecOp4_XE( istrWord, idRegN, idRegS, idRegT, idImm, idUCmd ); input[31:0] istrWord; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[7:0] idUCmd; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; reg[6:0] opRegN_Dfl; reg[6:0] opRegM_Dfl; reg[6:0] opRegO_Dfl; reg[6:0] opRegS_Dfl; reg[6:0] opRegT_Dfl; reg[6:0] opRegN_FR; reg[6:0] opRegM_FR; reg[6:0] opRegS_FR; reg[6:0] opRegT_FR; reg[31:0] opImm8_Sx8E; reg[31:0] opImm8_Zx8E; reg[31:0] opImm8_Nx8E; reg[31:0] opImm16_Sx8E; reg[31:0] opImm20_Sx8E; reg[31:0] opImmM12_Sx8E; reg[31:0] opImmO12_Sx8E; reg[31:0] opImm4_ZxXE; reg[6:0] opRegN_CEe; reg[6:0] opRegM_CEe; reg[6:0] opRegO_CEe; reg[6:0] opRegS_CEe; reg[6:0] opRegT_CEe; reg[6:0] opRegN_CEf; reg[6:0] opRegM_CEf; reg[31:0] opImm6_SxCEf; reg[31:0] opImm6_ZxCEf; reg[31:0] opImm6_NxCEf; reg opIsCE; reg[3:0] opCEe; reg opPsDQ; reg[15:0] opPfxWord; reg[15:0] opCmdWord; reg[4:0] tOpDecXfrm; reg[3:0] tOpDecXfrmZx; always @* begin opCmdWord=istrWord[31:16]; opPfxWord=istrWord[15: 0]; opIsCE = 0; opRegN_Dfl = {3'h0, opCmdWord[11: 8]}; opRegM_Dfl = {3'h0, opCmdWord[ 7: 4]}; opRegO_Dfl = {3'h0, opCmdWord[ 3: 0]}; opRegS_Dfl = {3'h0, opPfxWord[ 7: 4]}; opRegT_Dfl = {3'h0, opPfxWord[ 3: 0]}; opRegN_FR = {3'h4, opCmdWord[11: 8]}; opRegM_FR = {3'h4, opCmdWord[ 7: 4]}; opRegS_FR = {3'h4, opPfxWord[ 7: 4]}; opRegT_FR = {3'h4, opPfxWord[ 3: 0]}; opImm8_Sx8E = {opPfxWord[7] ? 24'hFFFFFF : 24'h0, opPfxWord[ 7:0]}; opImm8_Zx8E = {24'h000000, opPfxWord[ 7:0]}; opImm8_Nx8E = {24'hFFFFFF, opPfxWord[ 7:0]}; opImmM12_Sx8E = {opPfxWord[7] ? 20'hFFFFF : 20'h0, opPfxWord[ 7:0], opCmdWord[ 7:4]}; opImmO12_Sx8E = {opPfxWord[7] ? 20'hFFFFF : 20'h0, opPfxWord[ 7:0], opCmdWord[ 3:0]}; opImm16_Sx8E = {opPfxWord[7] ? 16'hFFFF : 16'h0000, opPfxWord[ 7:0], opCmdWord[ 7:0]}; opImm20_Sx8E = {opPfxWord[7] ? 12'hFFF : 12'h000, opPfxWord[ 7:0], opCmdWord[11:0]}; opCEe=opPfxWord[ 7: 4]; opPsDQ=0; if(opIsCE) begin opPsDQ = opCEe[3]; opRegN_CEe = {2'h0, opCEe[2], opCmdWord[11: 8]}; opRegM_CEe = {2'h0, opCEe[1], opCmdWord[ 7: 4]}; opRegO_CEe = {2'h0, opCEe[0], opCmdWord[ 3: 0]}; opRegT_CEe = {2'h0, opCEe[0], opPfxWord[ 3: 0]}; opRegN_CEf = {2'h0, opPfxWord[7], opCmdWord[11: 8]}; opRegM_CEf = {2'h0, opPfxWord[6], opCmdWord[ 7: 4]}; opRegS_CEe = opRegT_CEe; opImm6_SxCEf = { opPfxWord[5] ? 26'h3FFFFFF : 26'h0000000, opPfxWord[ 5: 0]}; opImm6_ZxCEf = {26'h0000000, opPfxWord[ 5: 0]}; opImm6_NxCEf = {26'h3FFFFFF, opPfxWord[ 5: 0]}; opImm4_ZxXE = 0; end else begin opRegN_CEe = opRegN_Dfl; opRegM_CEe = opRegM_Dfl; opRegO_CEe = opRegO_Dfl; opRegT_CEe = opRegT_Dfl; opRegS_CEe = opRegS_Dfl; opRegN_CEf = opRegN_Dfl; opRegM_CEf = opRegM_Dfl; opImm6_SxCEf = opImm8_Sx8E; opImm6_ZxCEf = opImm8_Zx8E; opImm6_NxCEf = opImm8_Nx8E; opImm4_ZxXE = {28'h0000000, opPfxWord[ 3: 0]}; end opUCmd=UCMD_UDBRK; opImm=0; opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; tOpDecXfrm=UXFORM_CST; tOpDecXfrmZx=UXFORMZX_SX; casez(opCmdWord[15:0]) 16'h0zz4: begin opUCmd = UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz5: begin opUCmd = UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz6: begin opUCmd = UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz7: begin opUCmd = UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzC: begin opUCmd = UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzD: begin opUCmd = UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzE: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzF: begin opUCmd = UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h1zzz: begin opUCmd = UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h2zz0: begin opUCmd = UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz1: begin opUCmd = UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz2: begin opUCmd = UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz3: begin opUCmd = UCMD_MOVQ_RM; end 16'h2zz9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzE: begin opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h2zzF: begin opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zz0: begin opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz2: begin opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz3: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz6: begin opUCmd=UCMD_CMP_HI; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz7: begin opUCmd=UCMD_CMP_GT; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz8: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zz9: begin end 16'h3zzC: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h4zz3: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_NST_8E; end 4'h1: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_NST_8E; end 4'h2: begin opUCmd=UCMD_ALU_MUL; tOpDecXfrm=UXFORM_NST_8E; end 4'h3: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_NST_8E; end 4'h4: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_NST_8E; end 4'h5: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_NST_8E; end 4'h6: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_NST_8E; end 4'h7: begin opUCmd=UCMD_ALU_SHLDR; tOpDecXfrm=UXFORM_NST_8E; end 4'h8: begin opUCmd=UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_NST_8E; end 4'h9: begin opUCmd=UCMD_ALU_SHADR; tOpDecXfrm=UXFORM_NST_8E; end 4'hC: begin opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF; end 4'hD: begin opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF; end 4'hE: begin opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF; end default: begin end endcase end 16'h4zzC: begin opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzD: begin opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzE: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_MOVUB_MR; tOpDecXfrm=UXFORM_NST_8E; end 4'h1: begin opUCmd=UCMD_MOVUW_MR; tOpDecXfrm=UXFORM_NST_8E; end default: begin end endcase end 16'h5zzz: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h6zz0: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz1: begin opUCmd = UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz2: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz3: begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz4: begin opUCmd=UCMD_LEAB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz5: begin opUCmd=UCMD_LEAW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz6: begin opUCmd=UCMD_LEAL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz7: begin opUCmd=UCMD_LEAQ_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz8: begin opUCmd=UCMD_LEAB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz9: begin opUCmd=UCMD_LEAW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzA: begin opUCmd=UCMD_LEAL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzB: begin opUCmd=UCMD_LEAQ_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzC: begin opUCmd=UCMD_MOVUB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzD: begin opUCmd=UCMD_MOVUW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzE: begin opUCmd=UCMD_MOVUL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzF: begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h7zzz: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI; end 16'h82zz: begin opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8; end 16'h83zz: begin opUCmd=UCMD_BSRN; tOpDecXfrm=UXFORM_BR_D8; end 16'h88zz: begin opUCmd=UCMD_CMP_EQ; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'h89zz: begin opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Azz: begin end 16'h8Bzz: begin opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Czz: begin end 16'h8Dzz: begin opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Fzz: begin opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8; end 16'h9zzz: begin opUCmd=UCMD_ALU_LDSH16; tOpDecXfrm=UXFORM_ARI_NNI; end 16'hAzzz: begin opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12; end 16'hBzzz: begin opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12; end 16'hC0zz: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end 16'hC1zz: begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end 16'hC2zz: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end 16'hC4zz: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end 16'hC5zz: begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end 16'hC6zz: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end 16'hC8zz: begin opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_I8R0; end 16'hC9zz: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCAzz: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCBzz: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hEzzz: begin opUCmd=UCMD_MOV_RI; tOpDecXfrm=UXFORM_ARI_NNI; end default: begin end endcase case(tOpDecXfrm) UXFORM_CST: begin end UXFORM_N: begin opRegN=opRegN_Dfl; opRegS=opRegN; end UXFORM_MOV_NS: begin opRegN = opRegN_Dfl; opRegS = opRegM_Dfl; opImm = opImm8_Sx8E; end UXFORM_MOV_NSO: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=opRegS_Dfl; opImm=opImm4_ZxXE; end UXFORM_MOV_NSJ: begin opRegN = opRegN_Dfl; opRegS = opRegM_Dfl; opRegT = opRegO_Dfl; opImm = opImm8_Sx8E; end UXFORM_FPARI_NS: begin opRegN=opRegN_FR; opRegS=opRegM_FR; end UXFORM_ARI_NS: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_ARI_NST: begin if(opIsCE) begin opRegN=opRegN_CEf; opRegS=opRegM_CEf; opRegT=UREG_MR_IMM; case(tOpDecXfrmZx) UXFORMZX_SX: opImm=opImm6_SxCEf; UXFORMZX_ZX: opImm=opImm6_ZxCEf; UXFORMZX_NX: opImm=opImm6_NxCEf; default: begin end endcase end else begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_MR_IMM; case(tOpDecXfrmZx) UXFORMZX_SX: opImm=opImm8_Sx8E; UXFORMZX_ZX: opImm=opImm8_Zx8E; UXFORMZX_NX: opImm=opImm8_Nx8E; default: begin end endcase end end UXFORM_CMP_ST: begin opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; opImm=opImmM12_Sx8E; end UXFORM_ARI_ST: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_ARI_NNI: begin opRegN={2'h0, opIsCE, opCmdWord[11:8]}; opRegS=opRegN; opRegT=UREG_MR_IMM; opImm=opImm16_Sx8E; end UXFORM_BR_D8: begin opImm = opImm16_Sx8E; end UXFORM_BR_D12: begin opImm = opImm20_Sx8E; end UXFORM_ARI_I8R0: begin opRegN=opRegM_Dfl; opRegS=opRegN; opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E; end UXFORM_N_C: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; end UXFORM_MOV_GD8R0: begin case(tOpDecXfrmZx) UXFORMZX_RM: begin opRegN=UREG_GBR; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm8_Zx8E; end UXFORMZX_MR: begin opRegN=UREG_R0; opRegS=UREG_GBR; opRegT=UREG_MR_IMM; opImm=opImm8_Zx8E; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_NST_8E: begin case(tOpDecXfrmZx) UXFORMZX_RR: begin opRegN=opRegN_Dfl; opRegS=opRegS_Dfl; opRegT=opRegT_Dfl; end UXFORMZX_FF: begin opRegN=opRegN_FR; opRegS=opRegS_FR; opRegT=opRegT_FR; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end endmodule

module DecOp4_XE( istrWord, idRegN, idRegS, idRegT, idImm, idUCmd );

input[31:0] istrWord; output[6:0] idRegN; output[6:0] idRegS; output[6:0] idRegT; output[31:0] idImm; output[7:0] idUCmd; reg[6:0] opRegN; reg[6:0] opRegS; reg[6:0] opRegT; reg[31:0] opImm; reg[7:0] opUCmd; assign idRegN = opRegN; assign idRegS = opRegS; assign idRegT = opRegT; assign idImm = opImm; assign idUCmd = opUCmd; reg[6:0] opRegN_Dfl; reg[6:0] opRegM_Dfl; reg[6:0] opRegO_Dfl; reg[6:0] opRegS_Dfl; reg[6:0] opRegT_Dfl; reg[6:0] opRegN_FR; reg[6:0] opRegM_FR; reg[6:0] opRegS_FR; reg[6:0] opRegT_FR; reg[31:0] opImm8_Sx8E; reg[31:0] opImm8_Zx8E; reg[31:0] opImm8_Nx8E; reg[31:0] opImm16_Sx8E; reg[31:0] opImm20_Sx8E; reg[31:0] opImmM12_Sx8E; reg[31:0] opImmO12_Sx8E; reg[31:0] opImm4_ZxXE; reg[6:0] opRegN_CEe; reg[6:0] opRegM_CEe; reg[6:0] opRegO_CEe; reg[6:0] opRegS_CEe; reg[6:0] opRegT_CEe; reg[6:0] opRegN_CEf; reg[6:0] opRegM_CEf; reg[31:0] opImm6_SxCEf; reg[31:0] opImm6_ZxCEf; reg[31:0] opImm6_NxCEf; reg opIsCE; reg[3:0] opCEe; reg opPsDQ; reg[15:0] opPfxWord; reg[15:0] opCmdWord; reg[4:0] tOpDecXfrm; reg[3:0] tOpDecXfrmZx; always @* begin opCmdWord=istrWord[31:16]; opPfxWord=istrWord[15: 0]; opIsCE = 0; opRegN_Dfl = {3'h0, opCmdWord[11: 8]}; opRegM_Dfl = {3'h0, opCmdWord[ 7: 4]}; opRegO_Dfl = {3'h0, opCmdWord[ 3: 0]}; opRegS_Dfl = {3'h0, opPfxWord[ 7: 4]}; opRegT_Dfl = {3'h0, opPfxWord[ 3: 0]}; opRegN_FR = {3'h4, opCmdWord[11: 8]}; opRegM_FR = {3'h4, opCmdWord[ 7: 4]}; opRegS_FR = {3'h4, opPfxWord[ 7: 4]}; opRegT_FR = {3'h4, opPfxWord[ 3: 0]}; opImm8_Sx8E = {opPfxWord[7] ? 24'hFFFFFF : 24'h0, opPfxWord[ 7:0]}; opImm8_Zx8E = {24'h000000, opPfxWord[ 7:0]}; opImm8_Nx8E = {24'hFFFFFF, opPfxWord[ 7:0]}; opImmM12_Sx8E = {opPfxWord[7] ? 20'hFFFFF : 20'h0, opPfxWord[ 7:0], opCmdWord[ 7:4]}; opImmO12_Sx8E = {opPfxWord[7] ? 20'hFFFFF : 20'h0, opPfxWord[ 7:0], opCmdWord[ 3:0]}; opImm16_Sx8E = {opPfxWord[7] ? 16'hFFFF : 16'h0000, opPfxWord[ 7:0], opCmdWord[ 7:0]}; opImm20_Sx8E = {opPfxWord[7] ? 12'hFFF : 12'h000, opPfxWord[ 7:0], opCmdWord[11:0]}; opCEe=opPfxWord[ 7: 4]; opPsDQ=0; if(opIsCE) begin opPsDQ = opCEe[3]; opRegN_CEe = {2'h0, opCEe[2], opCmdWord[11: 8]}; opRegM_CEe = {2'h0, opCEe[1], opCmdWord[ 7: 4]}; opRegO_CEe = {2'h0, opCEe[0], opCmdWord[ 3: 0]}; opRegT_CEe = {2'h0, opCEe[0], opPfxWord[ 3: 0]}; opRegN_CEf = {2'h0, opPfxWord[7], opCmdWord[11: 8]}; opRegM_CEf = {2'h0, opPfxWord[6], opCmdWord[ 7: 4]}; opRegS_CEe = opRegT_CEe; opImm6_SxCEf = { opPfxWord[5] ? 26'h3FFFFFF : 26'h0000000, opPfxWord[ 5: 0]}; opImm6_ZxCEf = {26'h0000000, opPfxWord[ 5: 0]}; opImm6_NxCEf = {26'h3FFFFFF, opPfxWord[ 5: 0]}; opImm4_ZxXE = 0; end else begin opRegN_CEe = opRegN_Dfl; opRegM_CEe = opRegM_Dfl; opRegO_CEe = opRegO_Dfl; opRegT_CEe = opRegT_Dfl; opRegS_CEe = opRegS_Dfl; opRegN_CEf = opRegN_Dfl; opRegM_CEf = opRegM_Dfl; opImm6_SxCEf = opImm8_Sx8E; opImm6_ZxCEf = opImm8_Zx8E; opImm6_NxCEf = opImm8_Nx8E; opImm4_ZxXE = {28'h0000000, opPfxWord[ 3: 0]}; end opUCmd=UCMD_UDBRK; opImm=0; opRegN=UREG_ZZR; opRegS=UREG_ZZR; opRegT=UREG_ZZR; tOpDecXfrm=UXFORM_CST; tOpDecXfrmZx=UXFORMZX_SX; casez(opCmdWord[15:0]) 16'h0zz4: begin opUCmd = UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz5: begin opUCmd = UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz6: begin opUCmd = UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zz7: begin opUCmd = UCMD_MOVQ_RM; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzC: begin opUCmd = UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzD: begin opUCmd = UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzE: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h0zzF: begin opUCmd = UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h1zzz: begin opUCmd = UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h2zz0: begin opUCmd = UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz1: begin opUCmd = UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz2: begin opUCmd = UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS; end 16'h2zz3: begin opUCmd = UCMD_MOVQ_RM; end 16'h2zz9: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzA: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzB: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h2zzE: begin opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h2zzF: begin opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST; end 16'h3zz0: begin opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz2: begin opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz3: begin opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz6: begin opUCmd=UCMD_CMP_HI; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz7: begin opUCmd=UCMD_CMP_GT; tOpDecXfrm=UXFORM_CMP_ST; end 16'h3zz8: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h3zz9: begin end 16'h3zzC: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_ZX; end 16'h4zz3: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_NST_8E; end 4'h1: begin opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_NST_8E; end 4'h2: begin opUCmd=UCMD_ALU_MUL; tOpDecXfrm=UXFORM_NST_8E; end 4'h3: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_NST_8E; end 4'h4: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_NST_8E; end 4'h5: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_NST_8E; end 4'h6: begin opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_NST_8E; end 4'h7: begin opUCmd=UCMD_ALU_SHLDR; tOpDecXfrm=UXFORM_NST_8E; end 4'h8: begin opUCmd=UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_NST_8E; end 4'h9: begin opUCmd=UCMD_ALU_SHADR; tOpDecXfrm=UXFORM_NST_8E; end 4'hC: begin opUCmd=UCMD_FPU_ADD; tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF; end 4'hD: begin opUCmd=UCMD_FPU_SUB; tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF; end 4'hE: begin opUCmd=UCMD_FPU_MUL; tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF; end default: begin end endcase end 16'h4zzC: begin opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzD: begin opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_ARI_NST; tOpDecXfrmZx=UXFORMZX_SX; end 16'h4zzE: begin case(opCmdWord[7:4]) 4'h0: begin opUCmd=UCMD_MOVUB_MR; tOpDecXfrm=UXFORM_NST_8E; end 4'h1: begin opUCmd=UCMD_MOVUW_MR; tOpDecXfrm=UXFORM_NST_8E; end default: begin end endcase end 16'h5zzz: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSJ; end 16'h6zz0: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz1: begin opUCmd = UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz2: begin opUCmd = UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz3: begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz4: begin opUCmd=UCMD_LEAB_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz5: begin opUCmd=UCMD_LEAW_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz6: begin opUCmd=UCMD_LEAL_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz7: begin opUCmd=UCMD_LEAQ_MR; tOpDecXfrm=UXFORM_MOV_NSO; end 16'h6zz8: begin opUCmd=UCMD_LEAB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zz9: begin opUCmd=UCMD_LEAW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzA: begin opUCmd=UCMD_LEAL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzB: begin opUCmd=UCMD_LEAQ_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzC: begin opUCmd=UCMD_MOVUB_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzD: begin opUCmd=UCMD_MOVUW_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzE: begin opUCmd=UCMD_MOVUL_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h6zzF: begin opUCmd=UCMD_MOVQ_MR; tOpDecXfrm=UXFORM_MOV_NS; end 16'h7zzz: begin opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI; end 16'h82zz: begin opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8; end 16'h83zz: begin opUCmd=UCMD_BSRN; tOpDecXfrm=UXFORM_BR_D8; end 16'h88zz: begin opUCmd=UCMD_CMP_EQ; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'h89zz: begin opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Azz: begin end 16'h8Bzz: begin opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Czz: begin end 16'h8Dzz: begin opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8; end 16'h8Fzz: begin opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8; end 16'h9zzz: begin opUCmd=UCMD_ALU_LDSH16; tOpDecXfrm=UXFORM_ARI_NNI; end 16'hAzzz: begin opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12; end 16'hBzzz: begin opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12; end 16'hC0zz: begin opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end 16'hC1zz: begin opUCmd=UCMD_MOVW_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end 16'hC2zz: begin opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_RM; end 16'hC4zz: begin opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end 16'hC5zz: begin opUCmd=UCMD_MOVW_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end 16'hC6zz: begin opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_GD8R0; tOpDecXfrmZx=UXFORMZX_MR; end 16'hC8zz: begin opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_I8R0; end 16'hC9zz: begin opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCAzz: begin opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hCBzz: begin opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0; end 16'hEzzz: begin opUCmd=UCMD_MOV_RI; tOpDecXfrm=UXFORM_ARI_NNI; end default: begin end endcase case(tOpDecXfrm) UXFORM_CST: begin end UXFORM_N: begin opRegN=opRegN_Dfl; opRegS=opRegN; end UXFORM_MOV_NS: begin opRegN = opRegN_Dfl; opRegS = opRegM_Dfl; opImm = opImm8_Sx8E; end UXFORM_MOV_NSO: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=opRegS_Dfl; opImm=opImm4_ZxXE; end UXFORM_MOV_NSJ: begin opRegN = opRegN_Dfl; opRegS = opRegM_Dfl; opRegT = opRegO_Dfl; opImm = opImm8_Sx8E; end UXFORM_FPARI_NS: begin opRegN=opRegN_FR; opRegS=opRegM_FR; end UXFORM_ARI_NS: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_ARI_NST: begin if(opIsCE) begin opRegN=opRegN_CEf; opRegS=opRegM_CEf; opRegT=UREG_MR_IMM; case(tOpDecXfrmZx) UXFORMZX_SX: opImm=opImm6_SxCEf; UXFORMZX_ZX: opImm=opImm6_ZxCEf; UXFORMZX_NX: opImm=opImm6_NxCEf; default: begin end endcase end else begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; opRegT=UREG_MR_IMM; case(tOpDecXfrmZx) UXFORMZX_SX: opImm=opImm8_Sx8E; UXFORMZX_ZX: opImm=opImm8_Zx8E; UXFORMZX_NX: opImm=opImm8_Nx8E; default: begin end endcase end end UXFORM_CMP_ST: begin opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; opImm=opImmM12_Sx8E; end UXFORM_ARI_ST: begin opRegN=opRegN_Dfl; opRegS=opRegM_Dfl; end UXFORM_ARI_NNI: begin opRegN={2'h0, opIsCE, opCmdWord[11:8]}; opRegS=opRegN; opRegT=UREG_MR_IMM; opImm=opImm16_Sx8E; end UXFORM_BR_D8: begin opImm = opImm16_Sx8E; end UXFORM_BR_D12: begin opImm = opImm20_Sx8E; end UXFORM_ARI_I8R0: begin opRegN=opRegM_Dfl; opRegS=opRegN; opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E; end UXFORM_N_C: begin opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=UREG_MR_IMM; end UXFORM_MOV_GD8R0: begin case(tOpDecXfrmZx) UXFORMZX_RM: begin opRegN=UREG_GBR; opRegS=UREG_R0; opRegT=UREG_MR_IMM; opImm=opImm8_Zx8E; end UXFORMZX_MR: begin opRegN=UREG_R0; opRegS=UREG_GBR; opRegT=UREG_MR_IMM; opImm=opImm8_Zx8E; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end UXFORM_NST_8E: begin case(tOpDecXfrmZx) UXFORMZX_RR: begin opRegN=opRegN_Dfl; opRegS=opRegS_Dfl; opRegT=opRegT_Dfl; end UXFORMZX_FF: begin opRegN=opRegN_FR; opRegS=opRegS_FR; opRegT=opRegT_FR; end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end default: begin opRegN=UREG_XX; opRegS=UREG_XX; opRegT=UREG_XX; opImm=32'hXXXXXXXX; end endcase end endmodule

data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v

ExUnit.v

v

[]

[]

[]

line:28: before: "parameter"

1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:1: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:2: Cannot find include file: Dc2Tile.v\n`include "Dc2Tile.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:3: Cannot find include file: DcTile3.v\n`include "DcTile3.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:4: Cannot find include file: IcTile2.v\n`include "IcTile2.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:6: Cannot find include file: RegGPR2.v\n`include "RegGPR2.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:10: Cannot find include file: DecOp4.v\n`include "DecOp4.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:12: Cannot find include file: ExOp2.v\n`include "ExOp2.v" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/ExUnit.v:15: Cannot find include file: TxtNtModW.v\n`include "TxtNtModW.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'

module

module ExUnit( clock, reset, extAddr, extData, extOE, extWR, extOK, mmioAddr, mmioData, mmioOE, mmioWR, mmioOK ); input clock; input reset; output[31:0] extAddr; inout[127:0] extData; output extOE; output extWR; input extOK; output[31:0] mmioAddr; inout[31:0] mmioData; output mmioOE; output mmioWR; input[1:0] mmioOK; assign extAddr = 32'hZ; assign extData = 128'hZ; assign extOE = 0; assign extWR = 0; assign mmioAddr = dc2MmioAddr; assign mmioData = dc2MmioWR ? dc2MmioOutData : 32'hZ; assign mmioOE = dc2MmioOE; assign mmioWR = dc2MmioWR; assign dc2MmioOK = mmioOK; wire[3:0] ntscPwm; wire[1:0] ntscMmioOK; TxtNtModW txtntmod( clock, reset, ntscPwm, mmioAddr, mmioData, mmioOE, mmioWR, ntscMmioOK ); reg[7:0] regRstTok; reg[7:0] regNextRstTok; reg[31:0] dc2RegInAddr; reg[127:0] dc2RegInData; wire[127:0] dc2RegOutData; wire[1:0] dc2RegOutOK; reg dc2RegInOE; reg dc2RegInWR; reg[4:0] dc2RegInOp; reg[127:0] dc2MemInData; wire[127:0] dc2MemOutData; wire[31:0] dc2MemAddr; wire dc2MemOE; wire dc2MemWR; reg[1:0] dc2MemOK; reg[31:0] dc2MmioInData; wire[31:0] dc2MmioOutData; wire[31:0] dc2MmioAddr; wire dc2MmioOE; wire dc2MmioWR; wire[1:0] dc2MmioOK; Dc2Tile dcl2( clock, reset, dc2RegInAddr, dc2RegInData, dc2RegOutData, dc2RegOutOK, dc2RegInOE, dc2RegInWR, dc2RegInOp, dc2MemInData, dc2MemOutData, dc2MemAddr, dc2MemOE, dc2MemWR, dc2MemOK, dc2MmioInData, dc2MmioOutData, dc2MmioAddr, dc2MmioOE, dc2MmioWR, dc2MmioOK ); reg[31:0] dcfRegInAddr; reg[63:0] dcfRegInData; wire[63:0] dcfRegOutData; wire[1:0] dcfRegOutOK; reg dcfRegInOE; reg dcfRegInWR; reg[4:0] dcfRegInOp; reg[127:0] dcfMemInData; wire[127:0] dcfMemOutData; wire[31:0] dcfMemPcAddr; wire dcfMemPcOE; wire dcfMemPcWR; reg[1:0] dcfMemPcOK; wire[4:0] dcfMemOp; DcTile3 dcf( clock, reset, dcfRegInData, dcfRegOutData, dcfRegInAddr, dcfRegOutOK, dcfRegInOE, dcfRegInWR, dcfRegInOp, dcfMemInData, dcfMemOutData, dcfMemPcAddr, dcfMemPcOK, dcfMemPcOE, dcfMemPcWR, dcfMemOp ); reg[31:0] regIfPc; reg[31:0] regIfSr; wire[47:0] regIfPcVal; wire[1:0] regIfPcOK; reg[127:0] memIfPcData; wire[31:0] memIfPcAddr; wire memIfPcOE; reg[1:0] memIfPcOK; IcTile2 icf(clock, reset, regIfPc, regIfPcVal, regIfPcOK, memIfPcData, memIfPcAddr, memIfPcOE, memIfPcOK); reg[47:0] regIfPcVal2; reg[47:0] regIdPcVal; reg[15:0] regIdCsFl; reg[31:0] regIdPc; reg[31:0] regIdSr; wire[6:0] idRegN; wire[6:0] idRegS; wire[6:0] idRegT; wire[31:0] idImm; wire[3:0] idStepPc; wire[3:0] idStepPc2; wire[7:0] idUCmd; reg[6:0] idWbRegO; reg[31:0] idWbRegValO; reg[6:0] wbRegO; reg[31:0] wbRegValO; DecOp4 dec( clock, regIdPcVal[47:0], regIdCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idStepPc2, idUCmd); wire[31:0] idRegValN; wire[31:0] idRegValS; wire[31:0] idRegValT; RegGPR2 gpr( clock, reset || (regRstTok != 8'h55), idRegS, idRegValS, idRegT, idRegValT, idRegN, idRegValN, idWbRegO, idWbRegValO, regIdSr, tRegExHold, idImm, regSr, exNextSr2, regPr, exNextPr2, regPc, exNextPc2, regMac, exNextMac2, regSp, exNextSp2, regGbr, exNextGbr2, regVbr, exNextVbr2, regSSr, exNextSSr2, regSPc, exNextSPc2, regSGr, exNextSGr2, regFpul, exNextFpul2, regFpScr, exNextFpScr2 ); wire[63:0] idRegFpValN; wire[63:0] idRegFpValS; wire[63:0] idRegFpValT; reg[1:0] idRegFpMode; reg[1:0] idRegFpStMode; wire[31:0] idFpNextFpul; reg[6:0] idWbRegFpO; reg[63:0] idWbRegFpValO; reg[6:0] wbRegFpO; reg[63:0] wbRegFpValO; reg[7:0] idUCmd2; reg[31:0] idRegValN2; reg[31:0] idRegValS2; reg[31:0] idRegValT2; reg[63:0] idRegFpValN2; reg[63:0] idRegFpValS2; reg[63:0] idRegFpValT2; reg[47:0] regExPcVal; reg[15:0] regExCsFl; reg[31:0] regExPc; reg[31:0] regExSr; reg[6:0] exRegN; reg[6:0] exRegS; reg[6:0] exRegT; reg[31:0] exImm; reg[3:0] exStepPc; reg[3:0] exStepPc2; reg[7:0] exUCmd; reg[31:0] exRegValN; reg[31:0] exRegValS; reg[31:0] exRegValT; reg[63:0] exRegFpValN; reg[63:0] exRegFpValS; reg[63:0] exRegFpValT; wire[6:0] exRegO; wire[31:0] exRegValO; wire[1:0] exRegOutOK; wire[31:0] exMemAddr; wire[31:0] exMemData; wire exMemLoad; wire exMemStore; wire[4:0] exMemOpMode; wire[7:0] exMemOpCmd2; wire[31:0] exNextSr; wire[31:0] exNextPr; wire[31:0] exNextPc; wire[63:0] exNextMac; wire[31:0] exNextGbr; wire[31:0] exNextVbr; wire[31:0] exNextSSr; wire[31:0] exNextSPc; wire[31:0] exNextSGr; wire[31:0] exNextSp; ExOp2 exOp(clock, reset, exUCmd, exStepPc, exRegS, exRegValS, exRegT, exRegValT, exRegN, exRegValN, exImm, tRegGenIdPc, exRegO, exRegValO, exRegOutOK, exMemAddr, exMemData, exMemLoad, exMemStore, exMemOpMode, exMemOpCmd2, regSr, exNextSr, regPr, exNextPr, regExPc, exNextPc, regMac, exNextMac, regSp, exNextSp, regGbr, exNextGbr, regVbr, exNextVbr, regSSr, exNextSSr, regSPc, exNextSPc, regSGr, exNextSGr ); reg[31:0] exNextSr2; reg[31:0] exNextPr2; reg[31:0] exNextPc2; reg[63:0] exNextMac2; reg[31:0] exNextGbr2; reg[31:0] exNextVbr2; reg[31:0] exNextSSr2; reg[31:0] exNextSPc2; reg[31:0] exNextSGr2; reg[31:0] exNextFpul2; reg[31:0] exNextFpScr2; reg[31:0] exNextSp2; wire[6:0] exRegFpO; wire[63:0] exRegFpValO; wire[1:0] exRegFpModeO; wire[31:0] exFpNextSr; wire[31:0] exFpNextFpul; wire[31:0] exFpNextFpScr; assign exRegFpO = UREG_ZZR; assign exRegFpValO = 0; assign exRegFpModeO = 0; assign exFpNextFpScr = regFpScr; reg[31:0] tRegGenIdPc; reg[31:0] tRegGenIdPr; reg[15:0] tRegGenIdOpw; reg[3:0] tRegGenIdStepPc; reg tRegExHold; always @* begin regIdCsFl=0; regIdCsFl[0]=1; regIdCsFl[1]=regFpScr[19]; regIdCsFl[2]=regFpScr[20]; regIdCsFl[3]=regFpScr[21]; regIdCsFl[4]=regFpScr[24]; regIdCsFl[5]=regSr[31]; regIdCsFl[6]=regSr[12]; regNextRstTok=8'h55; if(reset) regNextRstTok=8'h00; tRegGenIdStepPc=exStepPc2; tRegExHold = 0; if(regIfPcOK!=UMEM_OK_OK) tRegExHold = 1; if(exMemLoad||exMemStore) begin if(dcfRegOutOK!=UMEM_OK_OK) tRegExHold = 1; end if(exRegOutOK==UMEM_OK_HOLD) tRegExHold = 1; dc2MemInData = 0; dc2MemOK = UMEM_OK_READY; dc2MmioInData = 0; idRegFpMode = 0; idRegFpStMode = exRegFpModeO; if(regFpScr[19]) idRegFpMode = 1; if(regFpScr[20]) idRegFpMode = 1; idUCmd2 = idUCmd; case(exUCmd) UCMD_BRAN: idUCmd2 = UCMD_NONE; UCMD_BSRN: idUCmd2 = UCMD_NONE; UCMD_BT: idUCmd2 = UCMD_NONE; UCMD_BF: idUCmd2 = UCMD_NONE; UCMD_RTSN: idUCmd2 = UCMD_NONE; UCMD_RTEN: idUCmd2 = UCMD_NONE; default: begin end endcase tRegGenIdPc = regIfPc + {28'h0, tRegGenIdStepPc}; tRegGenIdPr = regIfPc + 32'h4; idRegValN2 = idRegValN; idRegValS2 = idRegValS; idRegValT2 = idRegValT; idRegFpValS2 = idRegFpValS; idRegFpValT2 = idRegFpValT; idRegFpValN2 = idRegFpValN; wbRegO = exRegO; wbRegValO = exRegValO; wbRegFpO = exRegFpO; wbRegFpValO = exRegFpValO; if(idRegS == wbRegO) idRegValS2 = wbRegValO; if(idRegT == wbRegO) idRegValT2 = wbRegValO; if(idRegN == wbRegO) idRegValN2 = wbRegValO; if(idRegS == wbRegO) idRegFpValS2 = wbRegFpValO; if(idRegT == wbRegO) idRegFpValT2 = wbRegFpValO; if(idRegN == wbRegO) idRegFpValN2 = wbRegFpValO; exNextSr2 = exNextSr; exNextPr2 = exNextPr; exNextPc2 = exNextPc; exNextMac2 = exNextMac; exNextGbr2 = exNextGbr; exNextVbr2 = exNextVbr; exNextSSr2 = exNextSSr; exNextSPc2 = exNextSPc; exNextSGr2 = exNextSGr; regIfPcVal2 = regIfPcVal; if(exNextPc != tRegGenIdPc) begin regIfPcVal2 = 48'h0F09_0F09_0E09; end exNextFpul2 = idFpNextFpul; exNextFpScr2 = exFpNextFpScr; exNextFpScr2[11] = ntscPwm[3]; exNextSp2 = exNextSp; if(regRstTok != 8'h55) begin $display("Reset"); exNextPc2 = 32'hA000_0000; tRegExHold = 1; end $display("IF: %X %X", regIfPc, regIfPcVal); $display("ID: %X %X", regIdPc, regIdPcVal); end always @ (posedge clock) begin regRstTok <= regNextRstTok; dcfRegInAddr <= exMemAddr; dcfRegInData <= {32'h0, exMemData}; dcfRegInOE <= exMemLoad; dcfRegInWR <= exMemStore; dcfRegInOp <= exMemOpMode; idWbRegO <= wbRegO; idWbRegValO <= wbRegValO; if((exMemLoad||exMemStore) && (dcfRegOutOK==UMEM_OK_OK)) begin idWbRegO <= idRegN; idWbRegValO <= dcfRegOutData[31:0]; idWbRegFpO <= idRegN; idWbRegFpValO <= dcfRegOutData; end else begin idWbRegO <= wbRegO; idWbRegValO <= wbRegValO; idWbRegFpO <= wbRegFpO; idWbRegFpValO <= wbRegFpValO; end if(memIfPcOE) begin $display("ExUnit: memIfPcOE"); dc2RegInAddr <= memIfPcAddr; dc2RegInData <= 0; dc2RegInOE <= memIfPcOE; dc2RegInWR <= 0; dc2RegInOp <= 1; memIfPcData <= dc2RegOutData; memIfPcOK <= dc2RegOutOK; dcfMemInData <= 128'hX; if(dcfMemPcOE || dcfMemPcWR) dcfMemPcOK <= UMEM_OK_HOLD; else dcfMemPcOK <= UMEM_OK_READY; end else if(dcfMemPcOE || dcfMemPcWR) begin dc2RegInAddr <= dcfMemPcAddr; dc2RegInData <= dcfMemOutData; dc2RegInOE <= dcfMemPcOE; dc2RegInWR <= dcfMemPcWR; dc2RegInOp <= dcfMemOp; dcfMemInData <= dc2RegOutData; dcfMemPcOK <= dc2RegOutOK; memIfPcData <= 128'hX; if(memIfPcOE) memIfPcOK <= UMEM_OK_HOLD; else memIfPcOK <= UMEM_OK_READY; end else begin dc2RegInAddr <= 0; dc2RegInData <= 0; dc2RegInOE <= 0; dc2RegInWR <= 0; dc2RegInOp <= 1; end if(regRstTok != 8'h55) begin regIfPc <= 32'hA000_0000; regIfSr <= 0; regIdPc <= 32'hA000_0000; regIdSr <= 0; regIdPcVal <= 0; regExPcVal <= 0; regExCsFl <= 0; regExPc <= 32'hA000_0000; regExSr <= 0; exStepPc <= 0; exStepPc2 <= 0; end else if(!tRegExHold) begin $display("Step"); regIfPc <= exNextPc2; regIfSr <= exNextSr2; regIdPc <= regIfPc; regIdSr <= regIfSr; regIdPcVal <= regIfPcVal2; regExPcVal <= regIdPcVal; regExCsFl <= regIdCsFl; regExPc <= regIdPc; regExSr <= regIdSr; exRegN <= idRegN; exRegS <= idRegS; exRegT <= idRegT; exImm <= idImm; exStepPc <= idStepPc; exStepPc2 <= idStepPc2; exUCmd <= idUCmd2; exRegValN <= idRegValN2; exRegValS <= idRegValS2; exRegValT <= idRegValT2; exRegFpValN <= idRegFpValN2; exRegFpValS <= idRegFpValS2; exRegFpValT <= idRegFpValT2; end else begin $display("Hold"); end end endmodule

module ExUnit( clock, reset, extAddr, extData, extOE, extWR, extOK, mmioAddr, mmioData, mmioOE, mmioWR, mmioOK );

input clock; input reset; output[31:0] extAddr; inout[127:0] extData; output extOE; output extWR; input extOK; output[31:0] mmioAddr; inout[31:0] mmioData; output mmioOE; output mmioWR; input[1:0] mmioOK; assign extAddr = 32'hZ; assign extData = 128'hZ; assign extOE = 0; assign extWR = 0; assign mmioAddr = dc2MmioAddr; assign mmioData = dc2MmioWR ? dc2MmioOutData : 32'hZ; assign mmioOE = dc2MmioOE; assign mmioWR = dc2MmioWR; assign dc2MmioOK = mmioOK; wire[3:0] ntscPwm; wire[1:0] ntscMmioOK; TxtNtModW txtntmod( clock, reset, ntscPwm, mmioAddr, mmioData, mmioOE, mmioWR, ntscMmioOK ); reg[7:0] regRstTok; reg[7:0] regNextRstTok; reg[31:0] dc2RegInAddr; reg[127:0] dc2RegInData; wire[127:0] dc2RegOutData; wire[1:0] dc2RegOutOK; reg dc2RegInOE; reg dc2RegInWR; reg[4:0] dc2RegInOp; reg[127:0] dc2MemInData; wire[127:0] dc2MemOutData; wire[31:0] dc2MemAddr; wire dc2MemOE; wire dc2MemWR; reg[1:0] dc2MemOK; reg[31:0] dc2MmioInData; wire[31:0] dc2MmioOutData; wire[31:0] dc2MmioAddr; wire dc2MmioOE; wire dc2MmioWR; wire[1:0] dc2MmioOK; Dc2Tile dcl2( clock, reset, dc2RegInAddr, dc2RegInData, dc2RegOutData, dc2RegOutOK, dc2RegInOE, dc2RegInWR, dc2RegInOp, dc2MemInData, dc2MemOutData, dc2MemAddr, dc2MemOE, dc2MemWR, dc2MemOK, dc2MmioInData, dc2MmioOutData, dc2MmioAddr, dc2MmioOE, dc2MmioWR, dc2MmioOK ); reg[31:0] dcfRegInAddr; reg[63:0] dcfRegInData; wire[63:0] dcfRegOutData; wire[1:0] dcfRegOutOK; reg dcfRegInOE; reg dcfRegInWR; reg[4:0] dcfRegInOp; reg[127:0] dcfMemInData; wire[127:0] dcfMemOutData; wire[31:0] dcfMemPcAddr; wire dcfMemPcOE; wire dcfMemPcWR; reg[1:0] dcfMemPcOK; wire[4:0] dcfMemOp; DcTile3 dcf( clock, reset, dcfRegInData, dcfRegOutData, dcfRegInAddr, dcfRegOutOK, dcfRegInOE, dcfRegInWR, dcfRegInOp, dcfMemInData, dcfMemOutData, dcfMemPcAddr, dcfMemPcOK, dcfMemPcOE, dcfMemPcWR, dcfMemOp ); reg[31:0] regIfPc; reg[31:0] regIfSr; wire[47:0] regIfPcVal; wire[1:0] regIfPcOK; reg[127:0] memIfPcData; wire[31:0] memIfPcAddr; wire memIfPcOE; reg[1:0] memIfPcOK; IcTile2 icf(clock, reset, regIfPc, regIfPcVal, regIfPcOK, memIfPcData, memIfPcAddr, memIfPcOE, memIfPcOK); reg[47:0] regIfPcVal2; reg[47:0] regIdPcVal; reg[15:0] regIdCsFl; reg[31:0] regIdPc; reg[31:0] regIdSr; wire[6:0] idRegN; wire[6:0] idRegS; wire[6:0] idRegT; wire[31:0] idImm; wire[3:0] idStepPc; wire[3:0] idStepPc2; wire[7:0] idUCmd; reg[6:0] idWbRegO; reg[31:0] idWbRegValO; reg[6:0] wbRegO; reg[31:0] wbRegValO; DecOp4 dec( clock, regIdPcVal[47:0], regIdCsFl, idRegN, idRegS, idRegT, idImm, idStepPc, idStepPc2, idUCmd); wire[31:0] idRegValN; wire[31:0] idRegValS; wire[31:0] idRegValT; RegGPR2 gpr( clock, reset || (regRstTok != 8'h55), idRegS, idRegValS, idRegT, idRegValT, idRegN, idRegValN, idWbRegO, idWbRegValO, regIdSr, tRegExHold, idImm, regSr, exNextSr2, regPr, exNextPr2, regPc, exNextPc2, regMac, exNextMac2, regSp, exNextSp2, regGbr, exNextGbr2, regVbr, exNextVbr2, regSSr, exNextSSr2, regSPc, exNextSPc2, regSGr, exNextSGr2, regFpul, exNextFpul2, regFpScr, exNextFpScr2 ); wire[63:0] idRegFpValN; wire[63:0] idRegFpValS; wire[63:0] idRegFpValT; reg[1:0] idRegFpMode; reg[1:0] idRegFpStMode; wire[31:0] idFpNextFpul; reg[6:0] idWbRegFpO; reg[63:0] idWbRegFpValO; reg[6:0] wbRegFpO; reg[63:0] wbRegFpValO; reg[7:0] idUCmd2; reg[31:0] idRegValN2; reg[31:0] idRegValS2; reg[31:0] idRegValT2; reg[63:0] idRegFpValN2; reg[63:0] idRegFpValS2; reg[63:0] idRegFpValT2; reg[47:0] regExPcVal; reg[15:0] regExCsFl; reg[31:0] regExPc; reg[31:0] regExSr; reg[6:0] exRegN; reg[6:0] exRegS; reg[6:0] exRegT; reg[31:0] exImm; reg[3:0] exStepPc; reg[3:0] exStepPc2; reg[7:0] exUCmd; reg[31:0] exRegValN; reg[31:0] exRegValS; reg[31:0] exRegValT; reg[63:0] exRegFpValN; reg[63:0] exRegFpValS; reg[63:0] exRegFpValT; wire[6:0] exRegO; wire[31:0] exRegValO; wire[1:0] exRegOutOK; wire[31:0] exMemAddr; wire[31:0] exMemData; wire exMemLoad; wire exMemStore; wire[4:0] exMemOpMode; wire[7:0] exMemOpCmd2; wire[31:0] exNextSr; wire[31:0] exNextPr; wire[31:0] exNextPc; wire[63:0] exNextMac; wire[31:0] exNextGbr; wire[31:0] exNextVbr; wire[31:0] exNextSSr; wire[31:0] exNextSPc; wire[31:0] exNextSGr; wire[31:0] exNextSp; ExOp2 exOp(clock, reset, exUCmd, exStepPc, exRegS, exRegValS, exRegT, exRegValT, exRegN, exRegValN, exImm, tRegGenIdPc, exRegO, exRegValO, exRegOutOK, exMemAddr, exMemData, exMemLoad, exMemStore, exMemOpMode, exMemOpCmd2, regSr, exNextSr, regPr, exNextPr, regExPc, exNextPc, regMac, exNextMac, regSp, exNextSp, regGbr, exNextGbr, regVbr, exNextVbr, regSSr, exNextSSr, regSPc, exNextSPc, regSGr, exNextSGr ); reg[31:0] exNextSr2; reg[31:0] exNextPr2; reg[31:0] exNextPc2; reg[63:0] exNextMac2; reg[31:0] exNextGbr2; reg[31:0] exNextVbr2; reg[31:0] exNextSSr2; reg[31:0] exNextSPc2; reg[31:0] exNextSGr2; reg[31:0] exNextFpul2; reg[31:0] exNextFpScr2; reg[31:0] exNextSp2; wire[6:0] exRegFpO; wire[63:0] exRegFpValO; wire[1:0] exRegFpModeO; wire[31:0] exFpNextSr; wire[31:0] exFpNextFpul; wire[31:0] exFpNextFpScr; assign exRegFpO = UREG_ZZR; assign exRegFpValO = 0; assign exRegFpModeO = 0; assign exFpNextFpScr = regFpScr; reg[31:0] tRegGenIdPc; reg[31:0] tRegGenIdPr; reg[15:0] tRegGenIdOpw; reg[3:0] tRegGenIdStepPc; reg tRegExHold; always @* begin regIdCsFl=0; regIdCsFl[0]=1; regIdCsFl[1]=regFpScr[19]; regIdCsFl[2]=regFpScr[20]; regIdCsFl[3]=regFpScr[21]; regIdCsFl[4]=regFpScr[24]; regIdCsFl[5]=regSr[31]; regIdCsFl[6]=regSr[12]; regNextRstTok=8'h55; if(reset) regNextRstTok=8'h00; tRegGenIdStepPc=exStepPc2; tRegExHold = 0; if(regIfPcOK!=UMEM_OK_OK) tRegExHold = 1; if(exMemLoad||exMemStore) begin if(dcfRegOutOK!=UMEM_OK_OK) tRegExHold = 1; end if(exRegOutOK==UMEM_OK_HOLD) tRegExHold = 1; dc2MemInData = 0; dc2MemOK = UMEM_OK_READY; dc2MmioInData = 0; idRegFpMode = 0; idRegFpStMode = exRegFpModeO; if(regFpScr[19]) idRegFpMode = 1; if(regFpScr[20]) idRegFpMode = 1; idUCmd2 = idUCmd; case(exUCmd) UCMD_BRAN: idUCmd2 = UCMD_NONE; UCMD_BSRN: idUCmd2 = UCMD_NONE; UCMD_BT: idUCmd2 = UCMD_NONE; UCMD_BF: idUCmd2 = UCMD_NONE; UCMD_RTSN: idUCmd2 = UCMD_NONE; UCMD_RTEN: idUCmd2 = UCMD_NONE; default: begin end endcase tRegGenIdPc = regIfPc + {28'h0, tRegGenIdStepPc}; tRegGenIdPr = regIfPc + 32'h4; idRegValN2 = idRegValN; idRegValS2 = idRegValS; idRegValT2 = idRegValT; idRegFpValS2 = idRegFpValS; idRegFpValT2 = idRegFpValT; idRegFpValN2 = idRegFpValN; wbRegO = exRegO; wbRegValO = exRegValO; wbRegFpO = exRegFpO; wbRegFpValO = exRegFpValO; if(idRegS == wbRegO) idRegValS2 = wbRegValO; if(idRegT == wbRegO) idRegValT2 = wbRegValO; if(idRegN == wbRegO) idRegValN2 = wbRegValO; if(idRegS == wbRegO) idRegFpValS2 = wbRegFpValO; if(idRegT == wbRegO) idRegFpValT2 = wbRegFpValO; if(idRegN == wbRegO) idRegFpValN2 = wbRegFpValO; exNextSr2 = exNextSr; exNextPr2 = exNextPr; exNextPc2 = exNextPc; exNextMac2 = exNextMac; exNextGbr2 = exNextGbr; exNextVbr2 = exNextVbr; exNextSSr2 = exNextSSr; exNextSPc2 = exNextSPc; exNextSGr2 = exNextSGr; regIfPcVal2 = regIfPcVal; if(exNextPc != tRegGenIdPc) begin regIfPcVal2 = 48'h0F09_0F09_0E09; end exNextFpul2 = idFpNextFpul; exNextFpScr2 = exFpNextFpScr; exNextFpScr2[11] = ntscPwm[3]; exNextSp2 = exNextSp; if(regRstTok != 8'h55) begin $display("Reset"); exNextPc2 = 32'hA000_0000; tRegExHold = 1; end $display("IF: %X %X", regIfPc, regIfPcVal); $display("ID: %X %X", regIdPc, regIdPcVal); end always @ (posedge clock) begin regRstTok <= regNextRstTok; dcfRegInAddr <= exMemAddr; dcfRegInData <= {32'h0, exMemData}; dcfRegInOE <= exMemLoad; dcfRegInWR <= exMemStore; dcfRegInOp <= exMemOpMode; idWbRegO <= wbRegO; idWbRegValO <= wbRegValO; if((exMemLoad||exMemStore) && (dcfRegOutOK==UMEM_OK_OK)) begin idWbRegO <= idRegN; idWbRegValO <= dcfRegOutData[31:0]; idWbRegFpO <= idRegN; idWbRegFpValO <= dcfRegOutData; end else begin idWbRegO <= wbRegO; idWbRegValO <= wbRegValO; idWbRegFpO <= wbRegFpO; idWbRegFpValO <= wbRegFpValO; end if(memIfPcOE) begin $display("ExUnit: memIfPcOE"); dc2RegInAddr <= memIfPcAddr; dc2RegInData <= 0; dc2RegInOE <= memIfPcOE; dc2RegInWR <= 0; dc2RegInOp <= 1; memIfPcData <= dc2RegOutData; memIfPcOK <= dc2RegOutOK; dcfMemInData <= 128'hX; if(dcfMemPcOE || dcfMemPcWR) dcfMemPcOK <= UMEM_OK_HOLD; else dcfMemPcOK <= UMEM_OK_READY; end else if(dcfMemPcOE || dcfMemPcWR) begin dc2RegInAddr <= dcfMemPcAddr; dc2RegInData <= dcfMemOutData; dc2RegInOE <= dcfMemPcOE; dc2RegInWR <= dcfMemPcWR; dc2RegInOp <= dcfMemOp; dcfMemInData <= dc2RegOutData; dcfMemPcOK <= dc2RegOutOK; memIfPcData <= 128'hX; if(memIfPcOE) memIfPcOK <= UMEM_OK_HOLD; else memIfPcOK <= UMEM_OK_READY; end else begin dc2RegInAddr <= 0; dc2RegInData <= 0; dc2RegInOE <= 0; dc2RegInWR <= 0; dc2RegInOp <= 1; end if(regRstTok != 8'h55) begin regIfPc <= 32'hA000_0000; regIfSr <= 0; regIdPc <= 32'hA000_0000; regIdSr <= 0; regIdPcVal <= 0; regExPcVal <= 0; regExCsFl <= 0; regExPc <= 32'hA000_0000; regExSr <= 0; exStepPc <= 0; exStepPc2 <= 0; end else if(!tRegExHold) begin $display("Step"); regIfPc <= exNextPc2; regIfSr <= exNextSr2; regIdPc <= regIfPc; regIdSr <= regIfSr; regIdPcVal <= regIfPcVal2; regExPcVal <= regIdPcVal; regExCsFl <= regIdCsFl; regExPc <= regIdPc; regExSr <= regIdSr; exRegN <= idRegN; exRegS <= idRegS; exRegT <= idRegT; exImm <= idImm; exStepPc <= idStepPc; exStepPc2 <= idStepPc2; exUCmd <= idUCmd2; exRegValN <= idRegValN2; exRegValS <= idRegValS2; exRegValT <= idRegValT2; exRegFpValN <= idRegFpValN2; exRegFpValS <= idRegFpValS2; exRegFpValT <= idRegFpValT2; end else begin $display("Hold"); end end endmodule

data/full_repos/permissive/99182535/bjx1c32b/FpuFp64To32.v

FpuFp64To32.v

v

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[(1, 74)]

data/verilator_xmls/332f9a75-446e-4e6b-bd3c-947d9ec0f81c.xml

module

module FpuFp64To32( clk, enable, src, dst ); input clk; input enable; input[63:0] src; output[31:0] dst; reg[11:0] exa; reg[11:0] exb; reg[31:0] tDst; assign dst = tDst; always @* begin exa[11]=0; exa[10:0]=src[62:52]; casez(exa[10:7]) 4'b0111: begin tDst[31]=src[63]; tDst[30:29]=2'b01; tDst[28:23]=exa[5:0]; tDst[22:0]=src[51:29]; end 4'b1000: begin tDst[31]=src[63]; tDst[30:29]=2'b10; tDst[28:23]=exa[5:0]; tDst[22:0]=src[51:29]; end default: begin tDst[31:0]=exa[10] ? {src[63], 31'h7F80_0000} : 32'h0000_0000; end endcase end endmodule

module FpuFp64To32( clk, enable, src, dst );

input clk; input enable; input[63:0] src; output[31:0] dst; reg[11:0] exa; reg[11:0] exb; reg[31:0] tDst; assign dst = tDst; always @* begin exa[11]=0; exa[10:0]=src[62:52]; casez(exa[10:7]) 4'b0111: begin tDst[31]=src[63]; tDst[30:29]=2'b01; tDst[28:23]=exa[5:0]; tDst[22:0]=src[51:29]; end 4'b1000: begin tDst[31]=src[63]; tDst[30:29]=2'b10; tDst[28:23]=exa[5:0]; tDst[22:0]=src[51:29]; end default: begin tDst[31:0]=exa[10] ? {src[63], 31'h7F80_0000} : 32'h0000_0000; end endcase end endmodule

data/full_repos/permissive/99182535/bjx1c32b/FpuFp64ToInt.v

FpuFp64ToInt.v

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line:28: before: "&&"

data/verilator_xmls/6a805f1a-4d64-401b-ab8f-88aa7a7f9024.xml

module

module FpuFp64ToInt( clk, enable, is32, src, dst ); input clk; input enable; input is32; input[63:0] src; output[63:0] dst; reg[11:0] exa; reg[11:0] exb; reg[63:0] fra; reg[63:0] frb; reg sgn; reg[5:0] tShl; reg[63:0] tDst; reg[63:0] tDst2; assign dst = tDst2; always @ (clk && enable) begin sgn=src[63]; exa[11]=0; exa[10:0]=src[62:52]; exb=exa-1075; if(sgn) begin fra[63:52]=~(12'h1); fra[51:0]=~(src[51:0]); end else begin fra[63:52]=12'h1; fra[51:0]=src[51:0]; end if(exa>=1075) begin tShl[5:0]=exb[5:0]; tDst=fra<<tShl; end else begin tShl[5:0]=-exb[5:0]; tDst=fra>>>tShl; end if(is32) begin if(tDst[63:31]==33'h1_FFFF_FFFF) tDst2=tDst; else if(tDst[63:31]==33'h0_0000_0000) tDst2=tDst; else tDst2=64'h0000_00000_8000_0000; end else tDst2=tDst; end endmodule

module FpuFp64ToInt( clk, enable, is32, src, dst );

input clk; input enable; input is32; input[63:0] src; output[63:0] dst; reg[11:0] exa; reg[11:0] exb; reg[63:0] fra; reg[63:0] frb; reg sgn; reg[5:0] tShl; reg[63:0] tDst; reg[63:0] tDst2; assign dst = tDst2; always @ (clk && enable) begin sgn=src[63]; exa[11]=0; exa[10:0]=src[62:52]; exb=exa-1075; if(sgn) begin fra[63:52]=~(12'h1); fra[51:0]=~(src[51:0]); end else begin fra[63:52]=12'h1; fra[51:0]=src[51:0]; end if(exa>=1075) begin tShl[5:0]=exb[5:0]; tDst=fra<<tShl; end else begin tShl[5:0]=-exb[5:0]; tDst=fra>>>tShl; end if(is32) begin if(tDst[63:31]==33'h1_FFFF_FFFF) tDst2=tDst; else if(tDst[63:31]==33'h0_0000_0000) tDst2=tDst; else tDst2=64'h0000_00000_8000_0000; end else tDst2=tDst; end endmodule

data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v

FpuFpD.v

v

[]

[]

[]

line:28: before: "parameter"

1: b'%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:1: Cannot find include file: CoreDefs.v\n`include "CoreDefs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.v\n data/full_repos/permissive/99182535/bjx1c32b,data/full_repos/permissive/99182535/CoreDefs.v.sv\n CoreDefs.v\n CoreDefs.v.v\n CoreDefs.v.sv\n obj_dir/CoreDefs.v\n obj_dir/CoreDefs.v.v\n obj_dir/CoreDefs.v.sv\n%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:2: Cannot find include file: FpuFpD_Add.v\n`include "FpuFpD_Add.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:3: Cannot find include file: FpuFpD_Mul.v\n`include "FpuFpD_Mul.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:4: Cannot find include file: FpuFp64ToInt.v\n`include "FpuFp64ToInt.v" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:5: Cannot find include file: FpuFp64FromInt.v\n`include "FpuFp64FromInt.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:7: Cannot find include file: FpuFp32To64.v\n`include "FpuFp32To64.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/99182535/bjx1c32b/FpuFpD.v:8: Cannot find include file: FpuFp64To32.v\n`include "FpuFp64To32.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'

module

module FpuFpD( clock, opMode, idMode, idRegA, idValA, idRegB, idValB, idRegC, idValC, idRegD, idValD, idModeD, ctlInSr, ctlOutSr, ctlInFpul, ctlOutFpul, ctlInFpScr, ctlOutFpScr ); input clock; input[7:0] opMode; input[1:0] idMode; input[63:0] idValA; input[63:0] idValB; input[63:0] idValC; output[63:0] idValD; input[6:0] idRegA; input[6:0] idRegB; input[6:0] idRegC; output[6:0] idRegD; output[1:0] idModeD; input[31:0] ctlInSr; output[31:0] ctlOutSr; input[31:0] ctlInFpul; output[31:0] ctlOutFpul; input[31:0] ctlInFpScr; output[31:0] ctlOutFpScr; wire[63:0] fcSrcA; wire[63:0] fcSrcB; wire[63:0] fcSrcC; reg[63:0] tIdValA; reg[63:0] tIdValB; reg[63:0] tIdValC; wire fcCnvSrc; wire[63:0] fcCnvOA; wire[63:0] fcCnvOB; wire[63:0] fcCnvOC; FpuFp32To64 fpCvtRa(clock, fcCnvSrc, tIdValA[31:0], fcCnvOA); FpuFp32To64 fpCvtRb(clock, fcCnvSrc, tIdValB[31:0], fcCnvOB); FpuFp32To64 fpCvtRc(clock, fcCnvSrc, tIdValC[31:0], fcCnvOC); wire fcCnvDst; wire[63:0] fcCnvOD; FpuFp64To32 fpCvtRd(clock, fcCnvDst, tDst, fcCnvOD[31:0]); assign fcCnvOD[63:32] = 32'hXXXXXXXX; reg fpaIsEn; wire fpaIsSub; wire[63:0] fpaSrcA; wire[63:0] fpaSrcB; wire[63:0] fpaDst; FpuFpD_Add fpadd(clock, fpaIsEn, fpaIsSub, fpaSrcA, fpaSrcB, fpaDst); assign fpaSrcA = fcSrcA; assign fpaSrcB = fcSrcB; wire[63:0] fpmSrcB; wire[63:0] fpmDst; FpuFpD_Mul fpmul(clock, fpaIsEn, fcSrcA, fpmSrcB, fpmDst); assign fpaIsSub = ((opMode==UCMD_FPU_SUB) || (opMode==UCMD_FPU_MSC)); assign fpmSrcB = fcSrcB; reg fpCnvifEn; wire[63:0] fpCnvbDstI; wire[63:0] fpCnvbDstF; FpuFp64ToInt cnv2si1(clock, fpCnvifEn, 1, tIdValB, fpCnvbDstI); FpuFp64FromInt cnv2is1(clock, fpCnvifEn, 1, tIdValB, fpCnvbDstF); reg[63:0] tDst; wire[63:0] tDst2; reg[6:0] tIdRegD; reg[1:0] tIdModeD; reg[31:0] tSro; reg[31:0] tFpul; reg[31:0] tFpScr; wire isOpF32; assign isOpF32 = (idMode==0); assign fcCnvSrc = (isOpF32 || (opMode==UCMD_FPU_CNVSD)) && (opMode!=UCMD_FPU_CNVIS); assign fcCnvDst = (isOpF32 || (opMode==UCMD_FPU_CNVDS)) && (opMode!=UCMD_FPU_CNVSI); assign fcSrcA = fcCnvSrc ? fcCnvOA : tIdValA; assign fcSrcB = fcCnvSrc ? fcCnvOB : tIdValB; assign fcSrcC = fcCnvSrc ? fcCnvOC : tIdValC; assign tDst2 = fcCnvDst ? fcCnvOD : tDst; assign ctlOutFpScr = tFpScr; always @* begin fpCnvifEn = 0; fpaIsEn = 0; tSro = ctlInSr; tDst = fcSrcB; tIdRegD = UREG_ZZR; tIdModeD = idMode; tFpul = ctlInFpul; tFpScr = ctlInFpScr; case(opMode) UCMD_FPU_NONE: begin tDst = 0; end default: begin end endcase end assign idRegD = tIdRegD; assign idModeD = tIdModeD; reg[63:0] tDst_B0; reg[63:0] tDst_B1; reg[63:0] tDst_B2; reg[63:0] tDst_B3; reg[63:0] nxtDst_B0; reg[63:0] nxtDst_B1; reg[63:0] nxtDst_B2; reg[63:0] nxtDst_B3; reg[31:0] tFpul_B0; reg[31:0] tFpul_B1; reg[31:0] tFpul_B2; reg[31:0] tFpul_B3; reg[31:0] nxtFpul_B0; reg[31:0] nxtFpul_B1; reg[31:0] nxtFpul_B2; reg[31:0] nxtFpul_B3; reg[31:0] tSro_B0; reg[31:0] tSro_B1; reg[31:0] tSro_B2; reg[31:0] tSro_B3; reg[31:0] nxtSro_B0; reg[31:0] nxtSro_B1; reg[31:0] nxtSro_B2; reg[31:0] nxtSro_B3; assign idValD = tDst_B3; assign ctlOutFpul = nxtFpul_B3; assign ctlOutSr = nxtSro_B3; always @* begin nxtDst_B0 = tDst2; nxtDst_B1 = tDst_B0; nxtDst_B2 = tDst_B1; nxtDst_B3 = tDst_B2; nxtFpul_B0 = tFpul; nxtFpul_B1 = tFpul_B0; nxtFpul_B2 = tFpul_B1; nxtFpul_B3 = tFpul_B2; nxtSro_B0 = tSro; nxtSro_B1 = tSro_B0; nxtSro_B2 = tSro_B1; nxtSro_B3 = tSro_B2; end always @ (posedge clock) begin tIdValA <= idValA; tIdValB <= idValB; tIdValC <= idValC; tDst_B0 <= nxtDst_B0; tDst_B1 <= nxtDst_B1; tDst_B2 <= nxtDst_B2; tDst_B3 <= nxtDst_B3; tFpul_B0 <= nxtFpul_B0; tFpul_B1 <= nxtFpul_B1; tFpul_B2 <= nxtFpul_B2; tFpul_B3 <= nxtFpul_B3; tSro_B0 <= nxtSro_B0; tSro_B1 <= nxtSro_B1; tSro_B2 <= nxtSro_B2; tSro_B3 <= nxtSro_B3; end endmodule

module FpuFpD( clock, opMode, idMode, idRegA, idValA, idRegB, idValB, idRegC, idValC, idRegD, idValD, idModeD, ctlInSr, ctlOutSr, ctlInFpul, ctlOutFpul, ctlInFpScr, ctlOutFpScr );

input clock; input[7:0] opMode; input[1:0] idMode; input[63:0] idValA; input[63:0] idValB; input[63:0] idValC; output[63:0] idValD; input[6:0] idRegA; input[6:0] idRegB; input[6:0] idRegC; output[6:0] idRegD; output[1:0] idModeD; input[31:0] ctlInSr; output[31:0] ctlOutSr; input[31:0] ctlInFpul; output[31:0] ctlOutFpul; input[31:0] ctlInFpScr; output[31:0] ctlOutFpScr; wire[63:0] fcSrcA; wire[63:0] fcSrcB; wire[63:0] fcSrcC; reg[63:0] tIdValA; reg[63:0] tIdValB; reg[63:0] tIdValC; wire fcCnvSrc; wire[63:0] fcCnvOA; wire[63:0] fcCnvOB; wire[63:0] fcCnvOC; FpuFp32To64 fpCvtRa(clock, fcCnvSrc, tIdValA[31:0], fcCnvOA); FpuFp32To64 fpCvtRb(clock, fcCnvSrc, tIdValB[31:0], fcCnvOB); FpuFp32To64 fpCvtRc(clock, fcCnvSrc, tIdValC[31:0], fcCnvOC); wire fcCnvDst; wire[63:0] fcCnvOD; FpuFp64To32 fpCvtRd(clock, fcCnvDst, tDst, fcCnvOD[31:0]); assign fcCnvOD[63:32] = 32'hXXXXXXXX; reg fpaIsEn; wire fpaIsSub; wire[63:0] fpaSrcA; wire[63:0] fpaSrcB; wire[63:0] fpaDst; FpuFpD_Add fpadd(clock, fpaIsEn, fpaIsSub, fpaSrcA, fpaSrcB, fpaDst); assign fpaSrcA = fcSrcA; assign fpaSrcB = fcSrcB; wire[63:0] fpmSrcB; wire[63:0] fpmDst; FpuFpD_Mul fpmul(clock, fpaIsEn, fcSrcA, fpmSrcB, fpmDst); assign fpaIsSub = ((opMode==UCMD_FPU_SUB) || (opMode==UCMD_FPU_MSC)); assign fpmSrcB = fcSrcB; reg fpCnvifEn; wire[63:0] fpCnvbDstI; wire[63:0] fpCnvbDstF; FpuFp64ToInt cnv2si1(clock, fpCnvifEn, 1, tIdValB, fpCnvbDstI); FpuFp64FromInt cnv2is1(clock, fpCnvifEn, 1, tIdValB, fpCnvbDstF); reg[63:0] tDst; wire[63:0] tDst2; reg[6:0] tIdRegD; reg[1:0] tIdModeD; reg[31:0] tSro; reg[31:0] tFpul; reg[31:0] tFpScr; wire isOpF32; assign isOpF32 = (idMode==0); assign fcCnvSrc = (isOpF32 || (opMode==UCMD_FPU_CNVSD)) && (opMode!=UCMD_FPU_CNVIS); assign fcCnvDst = (isOpF32 || (opMode==UCMD_FPU_CNVDS)) && (opMode!=UCMD_FPU_CNVSI); assign fcSrcA = fcCnvSrc ? fcCnvOA : tIdValA; assign fcSrcB = fcCnvSrc ? fcCnvOB : tIdValB; assign fcSrcC = fcCnvSrc ? fcCnvOC : tIdValC; assign tDst2 = fcCnvDst ? fcCnvOD : tDst; assign ctlOutFpScr = tFpScr; always @* begin fpCnvifEn = 0; fpaIsEn = 0; tSro = ctlInSr; tDst = fcSrcB; tIdRegD = UREG_ZZR; tIdModeD = idMode; tFpul = ctlInFpul; tFpScr = ctlInFpScr; case(opMode) UCMD_FPU_NONE: begin tDst = 0; end default: begin end endcase end assign idRegD = tIdRegD; assign idModeD = tIdModeD; reg[63:0] tDst_B0; reg[63:0] tDst_B1; reg[63:0] tDst_B2; reg[63:0] tDst_B3; reg[63:0] nxtDst_B0; reg[63:0] nxtDst_B1; reg[63:0] nxtDst_B2; reg[63:0] nxtDst_B3; reg[31:0] tFpul_B0; reg[31:0] tFpul_B1; reg[31:0] tFpul_B2; reg[31:0] tFpul_B3; reg[31:0] nxtFpul_B0; reg[31:0] nxtFpul_B1; reg[31:0] nxtFpul_B2; reg[31:0] nxtFpul_B3; reg[31:0] tSro_B0; reg[31:0] tSro_B1; reg[31:0] tSro_B2; reg[31:0] tSro_B3; reg[31:0] nxtSro_B0; reg[31:0] nxtSro_B1; reg[31:0] nxtSro_B2; reg[31:0] nxtSro_B3; assign idValD = tDst_B3; assign ctlOutFpul = nxtFpul_B3; assign ctlOutSr = nxtSro_B3; always @* begin nxtDst_B0 = tDst2; nxtDst_B1 = tDst_B0; nxtDst_B2 = tDst_B1; nxtDst_B3 = tDst_B2; nxtFpul_B0 = tFpul; nxtFpul_B1 = tFpul_B0; nxtFpul_B2 = tFpul_B1; nxtFpul_B3 = tFpul_B2; nxtSro_B0 = tSro; nxtSro_B1 = tSro_B0; nxtSro_B2 = tSro_B1; nxtSro_B3 = tSro_B2; end always @ (posedge clock) begin tIdValA <= idValA; tIdValB <= idValB; tIdValC <= idValC; tDst_B0 <= nxtDst_B0; tDst_B1 <= nxtDst_B1; tDst_B2 <= nxtDst_B2; tDst_B3 <= nxtDst_B3; tFpul_B0 <= nxtFpul_B0; tFpul_B1 <= nxtFpul_B1; tFpul_B2 <= nxtFpul_B2; tFpul_B3 <= nxtFpul_B3; tSro_B0 <= nxtSro_B0; tSro_B1 <= nxtSro_B1; tSro_B2 <= nxtSro_B2; tSro_B3 <= nxtSro_B3; end endmodule