repo_name
stringlengths 6
97
| path
stringlengths 3
341
| text
stringlengths 8
1.02M
|
|---|---|---|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-dot-product/test_msa_dotp_u_w.c | /*
* Test program for MSA instruction DOTP_U.W
*
* Copyright (C) 2018 Wave Computing, Inc.
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs.h"
#include "../../../../include/test_utils.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "DOTP_U.W";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0xfffc0002fffc0002ULL, 0xfffc0002fffc0002ULL, }, /* 0 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x5552aaac5552aaacULL, 0x5552aaac5552aaacULL, },
{ 0xaaa95556aaa95556ULL, 0xaaa95556aaa95556ULL, },
{ 0x9996666899966668ULL, 0x9996666899966668ULL, },
{ 0x6665999a6665999aULL, 0x6665999a6665999aULL, },
{ 0x1c6fe38f71c48e3aULL, 0xc71a38e51c6fe38fULL, },
{ 0xe38c1c738e3771c8ULL, 0x38e1c71de38c1c73ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x5552aaac5552aaacULL, 0x5552aaac5552aaacULL, }, /* 16 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xe38c71c8e38c71c8ULL, 0xe38c71c8e38c71c8ULL, },
{ 0x71c638e471c638e4ULL, 0x71c638e471c638e4ULL, },
{ 0x110eeef0110eeef0ULL, 0x110eeef0110eeef0ULL, },
{ 0x4443bbbc4443bbbcULL, 0x4443bbbc4443bbbcULL, },
{ 0xbd9fed0af683097cULL, 0x84bc25eebd9fed0aULL, },
{ 0x97b2bda25ecfa130ULL, 0xd09684be97b2bda2ULL, },
{ 0xaaa95556aaa95556ULL, 0xaaa95556aaa95556ULL, }, /* 24 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x71c638e471c638e4ULL, 0x71c638e471c638e4ULL, },
{ 0x38e31c7238e31c72ULL, 0x38e31c7238e31c72ULL, },
{ 0x8887777888877778ULL, 0x8887777888877778ULL, },
{ 0x2221ddde2221dddeULL, 0x2221ddde2221dddeULL, },
{ 0x5ecff6857b4184beULL, 0x425e12f75ecff685ULL, },
{ 0x4bd95ed12f67d098ULL, 0x684b425f4bd95ed1ULL, },
{ 0x9996666899966668ULL, 0x9996666899966668ULL, }, /* 32 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x110eeef0110eeef0ULL, 0x110eeef0110eeef0ULL, },
{ 0x8887777888877778ULL, 0x8887777888877778ULL, },
{ 0x47ab852047ab8520ULL, 0x47ab852047ab8520ULL, },
{ 0x51eae14851eae148ULL, 0x51eae14851eae148ULL, },
{ 0xe38cb60c27d071c8ULL, 0x9f482d84e38cb60cULL, },
{ 0xb609b05c71c5f4a0ULL, 0xfa4e38e4b609b05cULL, },
{ 0x6665999a6665999aULL, 0x6665999a6665999aULL, }, /* 40 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x4443bbbc4443bbbcULL, 0x4443bbbc4443bbbcULL, },
{ 0x2221ddde2221dddeULL, 0x2221ddde2221dddeULL, },
{ 0x51eae14851eae148ULL, 0x51eae14851eae148ULL, },
{ 0x147ab852147ab852ULL, 0x147ab852147ab852ULL, },
{ 0x38e32d8349f41c72ULL, 0x27d20b6138e32d83ULL, },
{ 0x2d826c171c717d28ULL, 0x3e938e392d826c17ULL, },
{ 0x1c6fe38f71c48e3aULL, 0xc71a38e51c6fe38fULL, }, /* 48 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xbd9fed0af683097cULL, 0x84bc25eebd9fed0aULL, },
{ 0x5ecff6857b4184beULL, 0x425e12f75ecff685ULL, },
{ 0xe38cb60c27d071c8ULL, 0x9f482d84e38cb60cULL, },
{ 0x38e32d8349f41c72ULL, 0x27d20b6138e32d83ULL, },
{ 0xd6e93c0d19474f04ULL, 0x5ba64589d6e93c0dULL, },
{ 0x4586a782587d3f36ULL, 0x6b73f35c4586a782ULL, },
{ 0xe38c1c738e3771c8ULL, 0x38e1c71de38c1c73ULL, }, /* 56 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x97b2bda25ecfa130ULL, 0xd09684be97b2bda2ULL, },
{ 0x4bd95ed12f67d098ULL, 0x684b425f4bd95ed1ULL, },
{ 0xb609b05c71c5f4a0ULL, 0xfa4e38e4b609b05cULL, },
{ 0x2d826c171c717d28ULL, 0x3e938e392d826c17ULL, },
{ 0x4586a782587d3f36ULL, 0x6b73f35c4586a782ULL, },
{ 0x9e0574f135ba3292ULL, 0xcd6dd3c19e0574f1ULL, },
{ 0x18c3fe7422c25584ULL, 0x16b6b9f57608cfa9ULL, }, /* 64 */
{ 0x867e6d904e841446ULL, 0x0de4cfed4e2fdb15ULL, },
{ 0xf94f18bc4bc3d93eULL, 0x1492568ac3a66499ULL, },
{ 0x4ff36c125a383042ULL, 0x2fe23e4744196e36ULL, },
{ 0x867e6d904e841446ULL, 0x0de4cfed4e2fdb15ULL, },
{ 0xf78e474db23f32a9ULL, 0x8a26a8f51ca9cd91ULL, },
{ 0xa9bfb48aa4c2d0ddULL, 0x94641c4e1a398e45ULL, },
{ 0x6e796f69cc7c8793ULL, 0x6e879377578266beULL, },
{ 0xf94f18bc4bc3d93eULL, 0x1492568ac3a66499ULL, }, /* 72 */
{ 0xa9bfb48aa4c2d0ddULL, 0x94641c4e1a398e45ULL, },
{ 0xeb349888d2e11561ULL, 0xa0e2f84177d142c9ULL, },
{ 0x5ad3b4e8bfaf139fULL, 0x8076d98091fe5896ULL, },
{ 0x4ff36c125a383042ULL, 0x2fe23e4744196e36ULL, },
{ 0x6e796f69cc7c8793ULL, 0x6e879377578266beULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_DOTP_U_W(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_DOTP_U_W(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/target/i386/cpu.c | <filename>src/qemu/src-pmp/target/i386/cpu.c
/*
* i386 CPUID helper functions
*
* Copyright (c) 2003 <NAME>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/cutils.h"
#include "qemu/bitops.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "sysemu/hvf.h"
#include "sysemu/cpus.h"
#include "kvm_i386.h"
#include "sev_i386.h"
#include "qemu/error-report.h"
#include "qemu/option.h"
#include "qemu/config-file.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-misc.h"
#include "qapi/qapi-visit-run-state.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qerror.h"
#include "qapi/visitor.h"
#include "qom/qom-qobject.h"
#include "sysemu/arch_init.h"
#include "qapi/qapi-commands-target.h"
#include "standard-headers/asm-x86/kvm_para.h"
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "hw/i386/topology.h"
#ifndef CONFIG_USER_ONLY
#include "exec/address-spaces.h"
#include "hw/hw.h"
#include "hw/xen/xen.h"
#include "hw/i386/apic_internal.h"
#endif
#include "disas/capstone.h"
/* Helpers for building CPUID[2] descriptors: */
struct CPUID2CacheDescriptorInfo {
enum CacheType type;
int level;
int size;
int line_size;
int associativity;
};
/*
* Known CPUID 2 cache descriptors.
* From Intel SDM Volume 2A, CPUID instruction
*/
struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
[0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
.associativity = 4, .line_size = 32, },
[0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
.associativity = 4, .line_size = 32, },
[0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
.associativity = 4, .line_size = 64, },
[0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
.associativity = 2, .line_size = 32, },
[0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
.associativity = 4, .line_size = 32, },
[0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
.associativity = 4, .line_size = 64, },
[0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
.associativity = 6, .line_size = 64, },
[0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
.associativity = 2, .line_size = 64, },
[0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
.associativity = 8, .line_size = 64, },
/* lines per sector is not supported cpuid2_cache_descriptor(),
* so descriptors 0x22, 0x23 are not included
*/
[0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 16, .line_size = 64, },
/* lines per sector is not supported cpuid2_cache_descriptor(),
* so descriptors 0x25, 0x20 are not included
*/
[0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
.associativity = 8, .line_size = 64, },
[0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
.associativity = 8, .line_size = 64, },
[0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
.associativity = 4, .line_size = 32, },
[0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
.associativity = 4, .line_size = 32, },
[0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
.associativity = 4, .line_size = 32, },
[0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 4, .line_size = 32, },
[0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
.associativity = 4, .line_size = 32, },
[0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
.associativity = 4, .line_size = 64, },
[0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
.associativity = 8, .line_size = 64, },
[0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
.associativity = 12, .line_size = 64, },
/* Descriptor 0x49 depends on CPU family/model, so it is not included */
[0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
.associativity = 12, .line_size = 64, },
[0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
.associativity = 16, .line_size = 64, },
[0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
.associativity = 12, .line_size = 64, },
[0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
.associativity = 16, .line_size = 64, },
[0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
.associativity = 24, .line_size = 64, },
[0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
.associativity = 8, .line_size = 64, },
[0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
.associativity = 4, .line_size = 64, },
[0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
.associativity = 4, .line_size = 64, },
[0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
.associativity = 4, .line_size = 64, },
[0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 4, .line_size = 64, },
/* lines per sector is not supported cpuid2_cache_descriptor(),
* so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
*/
[0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
.associativity = 8, .line_size = 64, },
[0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
.associativity = 2, .line_size = 64, },
[0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
.associativity = 8, .line_size = 64, },
[0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
.associativity = 8, .line_size = 32, },
[0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
.associativity = 8, .line_size = 32, },
[0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 8, .line_size = 32, },
[0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
.associativity = 8, .line_size = 32, },
[0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
.associativity = 4, .line_size = 64, },
[0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 8, .line_size = 64, },
[0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
.associativity = 4, .line_size = 64, },
[0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 4, .line_size = 64, },
[0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
.associativity = 4, .line_size = 64, },
[0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
.associativity = 8, .line_size = 64, },
[0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
.associativity = 8, .line_size = 64, },
[0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
.associativity = 8, .line_size = 64, },
[0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
.associativity = 12, .line_size = 64, },
[0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
.associativity = 12, .line_size = 64, },
[0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
.associativity = 12, .line_size = 64, },
[0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
.associativity = 16, .line_size = 64, },
[0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
.associativity = 16, .line_size = 64, },
[0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
.associativity = 16, .line_size = 64, },
[0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
.associativity = 24, .line_size = 64, },
[0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
.associativity = 24, .line_size = 64, },
[0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
.associativity = 24, .line_size = 64, },
};
/*
* "CPUID leaf 2 does not report cache descriptor information,
* use CPUID leaf 4 to query cache parameters"
*/
#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
/*
* Return a CPUID 2 cache descriptor for a given cache.
* If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
*/
static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
{
int i;
assert(cache->size > 0);
assert(cache->level > 0);
assert(cache->line_size > 0);
assert(cache->associativity > 0);
for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
if (d->level == cache->level && d->type == cache->type &&
d->size == cache->size && d->line_size == cache->line_size &&
d->associativity == cache->associativity) {
return i;
}
}
return CACHE_DESCRIPTOR_UNAVAILABLE;
}
/* CPUID Leaf 4 constants: */
/* EAX: */
#define CACHE_TYPE_D 1
#define CACHE_TYPE_I 2
#define CACHE_TYPE_UNIFIED 3
#define CACHE_LEVEL(l) (l << 5)
#define CACHE_SELF_INIT_LEVEL (1 << 8)
/* EDX: */
#define CACHE_NO_INVD_SHARING (1 << 0)
#define CACHE_INCLUSIVE (1 << 1)
#define CACHE_COMPLEX_IDX (1 << 2)
/* Encode CacheType for CPUID[4].EAX */
#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
0 /* Invalid value */)
/* Encode cache info for CPUID[4] */
static void encode_cache_cpuid4(CPUCacheInfo *cache,
int num_apic_ids, int num_cores,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
assert(num_apic_ids > 0);
*eax = CACHE_TYPE(cache->type) |
CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
((num_cores - 1) << 26) |
((num_apic_ids - 1) << 14);
assert(cache->line_size > 0);
assert(cache->partitions > 0);
assert(cache->associativity > 0);
/* We don't implement fully-associative caches */
assert(cache->associativity < cache->sets);
*ebx = (cache->line_size - 1) |
((cache->partitions - 1) << 12) |
((cache->associativity - 1) << 22);
assert(cache->sets > 0);
*ecx = cache->sets - 1;
*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
(cache->inclusive ? CACHE_INCLUSIVE : 0) |
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
{
assert(cache->size % 1024 == 0);
assert(cache->lines_per_tag > 0);
assert(cache->associativity > 0);
assert(cache->line_size > 0);
return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
(cache->lines_per_tag << 8) | (cache->line_size);
}
#define ASSOC_FULL 0xFF
/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
a == 2 ? 0x2 : \
a == 4 ? 0x4 : \
a == 8 ? 0x6 : \
a == 16 ? 0x8 : \
a == 32 ? 0xA : \
a == 48 ? 0xB : \
a == 64 ? 0xC : \
a == 96 ? 0xD : \
a == 128 ? 0xE : \
a == ASSOC_FULL ? 0xF : \
0 /* invalid value */)
/*
* Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
* @l3 can be NULL.
*/
static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
CPUCacheInfo *l3,
uint32_t *ecx, uint32_t *edx)
{
assert(l2->size % 1024 == 0);
assert(l2->associativity > 0);
assert(l2->lines_per_tag > 0);
assert(l2->line_size > 0);
*ecx = ((l2->size / 1024) << 16) |
(AMD_ENC_ASSOC(l2->associativity) << 12) |
(l2->lines_per_tag << 8) | (l2->line_size);
if (l3) {
assert(l3->size % (512 * 1024) == 0);
assert(l3->associativity > 0);
assert(l3->lines_per_tag > 0);
assert(l3->line_size > 0);
*edx = ((l3->size / (512 * 1024)) << 18) |
(AMD_ENC_ASSOC(l3->associativity) << 12) |
(l3->lines_per_tag << 8) | (l3->line_size);
} else {
*edx = 0;
}
}
/*
* Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
* Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
* Define the constants to build the cpu topology. Right now, TOPOEXT
* feature is enabled only on EPYC. So, these constants are based on
* EPYC supported configurations. We may need to handle the cases if
* these values change in future.
*/
/* Maximum core complexes in a node */
#define MAX_CCX 2
/* Maximum cores in a core complex */
#define MAX_CORES_IN_CCX 4
/* Maximum cores in a node */
#define MAX_CORES_IN_NODE 8
/* Maximum nodes in a socket */
#define MAX_NODES_PER_SOCKET 4
/*
* Figure out the number of nodes required to build this config.
* Max cores in a node is 8
*/
static int nodes_in_socket(int nr_cores)
{
int nodes;
nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
/* Hardware does not support config with 3 nodes, return 4 in that case */
return (nodes == 3) ? 4 : nodes;
}
/*
* Decide the number of cores in a core complex with the given nr_cores using
* following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
* MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
* L3 cache is shared across all cores in a core complex. So, this will also
* tell us how many cores are sharing the L3 cache.
*/
static int cores_in_core_complex(int nr_cores)
{
int nodes;
/* Check if we can fit all the cores in one core complex */
if (nr_cores <= MAX_CORES_IN_CCX) {
return nr_cores;
}
/* Get the number of nodes required to build this config */
nodes = nodes_in_socket(nr_cores);
/*
* Divide the cores accros all the core complexes
* Return rounded up value
*/
return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
}
/* Encode cache info for CPUID[8000001D] */
static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
uint32_t l3_cores;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
/* L3 is shared among multiple cores */
if (cache->level == 3) {
l3_cores = cores_in_core_complex(cs->nr_cores);
*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
} else {
*eax |= ((cs->nr_threads - 1) << 14);
}
assert(cache->line_size > 0);
assert(cache->partitions > 0);
assert(cache->associativity > 0);
/* We don't implement fully-associative caches */
assert(cache->associativity < cache->sets);
*ebx = (cache->line_size - 1) |
((cache->partitions - 1) << 12) |
((cache->associativity - 1) << 22);
assert(cache->sets > 0);
*ecx = cache->sets - 1;
*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
(cache->inclusive ? CACHE_INCLUSIVE : 0) |
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
/* Data structure to hold the configuration info for a given core index */
struct core_topology {
/* core complex id of the current core index */
int ccx_id;
/*
* Adjusted core index for this core in the topology
* This can be 0,1,2,3 with max 4 cores in a core complex
*/
int core_id;
/* Node id for this core index */
int node_id;
/* Number of nodes in this config */
int num_nodes;
};
/*
* Build the configuration closely match the EPYC hardware. Using the EPYC
* hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
* right now. This could change in future.
* nr_cores : Total number of cores in the config
* core_id : Core index of the current CPU
* topo : Data structure to hold all the config info for this core index
*/
static void build_core_topology(int nr_cores, int core_id,
struct core_topology *topo)
{
int nodes, cores_in_ccx;
/* First get the number of nodes required */
nodes = nodes_in_socket(nr_cores);
cores_in_ccx = cores_in_core_complex(nr_cores);
topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
topo->core_id = core_id % cores_in_ccx;
topo->num_nodes = nodes;
}
/* Encode cache info for CPUID[8000001E] */
static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
struct core_topology topo = {0};
unsigned long nodes;
int shift;
build_core_topology(cs->nr_cores, cpu->core_id, &topo);
*eax = cpu->apic_id;
/*
* CPUID_Fn8000001E_EBX
* 31:16 Reserved
* 15:8 Threads per core (The number of threads per core is
* Threads per core + 1)
* 7:0 Core id (see bit decoding below)
* SMT:
* 4:3 node id
* 2 Core complex id
* 1:0 Core id
* Non SMT:
* 5:4 node id
* 3 Core complex id
* 1:0 Core id
*/
if (cs->nr_threads - 1) {
*ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
(topo.ccx_id << 2) | topo.core_id;
} else {
*ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
}
/*
* CPUID_Fn8000001E_ECX
* 31:11 Reserved
* 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
* 7:0 Node id (see bit decoding below)
* 2 Socket id
* 1:0 Node id
*/
if (topo.num_nodes <= 4) {
*ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
topo.node_id;
} else {
/*
* Node id fix up. Actual hardware supports up to 4 nodes. But with
* more than 32 cores, we may end up with more than 4 nodes.
* Node id is a combination of socket id and node id. Only requirement
* here is that this number should be unique accross the system.
* Shift the socket id to accommodate more nodes. We dont expect both
* socket id and node id to be big number at the same time. This is not
* an ideal config but we need to to support it. Max nodes we can have
* is 32 (255/8) with 8 cores per node and 255 max cores. We only need
* 5 bits for nodes. Find the left most set bit to represent the total
* number of nodes. find_last_bit returns last set bit(0 based). Left
* shift(+1) the socket id to represent all the nodes.
*/
nodes = topo.num_nodes - 1;
shift = find_last_bit(&nodes, 8);
*ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
topo.node_id;
}
*edx = 0;
}
/*
* Definitions of the hardcoded cache entries we expose:
* These are legacy cache values. If there is a need to change any
* of these values please use builtin_x86_defs
*/
/* L1 data cache: */
static CPUCacheInfo legacy_l1d_cache = {
.type = DATA_CACHE,
.level = 1,
.size = 32 * KiB,
.self_init = 1,
.line_size = 64,
.associativity = 8,
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
static CPUCacheInfo legacy_l1d_cache_amd = {
.type = DATA_CACHE,
.level = 1,
.size = 64 * KiB,
.self_init = 1,
.line_size = 64,
.associativity = 2,
.sets = 512,
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
};
/* L1 instruction cache: */
static CPUCacheInfo legacy_l1i_cache = {
.type = INSTRUCTION_CACHE,
.level = 1,
.size = 32 * KiB,
.self_init = 1,
.line_size = 64,
.associativity = 8,
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
static CPUCacheInfo legacy_l1i_cache_amd = {
.type = INSTRUCTION_CACHE,
.level = 1,
.size = 64 * KiB,
.self_init = 1,
.line_size = 64,
.associativity = 2,
.sets = 512,
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
};
/* Level 2 unified cache: */
static CPUCacheInfo legacy_l2_cache = {
.type = UNIFIED_CACHE,
.level = 2,
.size = 4 * MiB,
.self_init = 1,
.line_size = 64,
.associativity = 16,
.sets = 4096,
.partitions = 1,
.no_invd_sharing = true,
};
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
static CPUCacheInfo legacy_l2_cache_cpuid2 = {
.type = UNIFIED_CACHE,
.level = 2,
.size = 2 * MiB,
.line_size = 64,
.associativity = 8,
};
/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
static CPUCacheInfo legacy_l2_cache_amd = {
.type = UNIFIED_CACHE,
.level = 2,
.size = 512 * KiB,
.line_size = 64,
.lines_per_tag = 1,
.associativity = 16,
.sets = 512,
.partitions = 1,
};
/* Level 3 unified cache: */
static CPUCacheInfo legacy_l3_cache = {
.type = UNIFIED_CACHE,
.level = 3,
.size = 16 * MiB,
.line_size = 64,
.associativity = 16,
.sets = 16384,
.partitions = 1,
.lines_per_tag = 1,
.self_init = true,
.inclusive = true,
.complex_indexing = true,
};
/* TLB definitions: */
#define L1_DTLB_2M_ASSOC 1
#define L1_DTLB_2M_ENTRIES 255
#define L1_DTLB_4K_ASSOC 1
#define L1_DTLB_4K_ENTRIES 255
#define L1_ITLB_2M_ASSOC 1
#define L1_ITLB_2M_ENTRIES 255
#define L1_ITLB_4K_ASSOC 1
#define L1_ITLB_4K_ENTRIES 255
#define L2_DTLB_2M_ASSOC 0 /* disabled */
#define L2_DTLB_2M_ENTRIES 0 /* disabled */
#define L2_DTLB_4K_ASSOC 4
#define L2_DTLB_4K_ENTRIES 512
#define L2_ITLB_2M_ASSOC 0 /* disabled */
#define L2_ITLB_2M_ENTRIES 0 /* disabled */
#define L2_ITLB_4K_ASSOC 4
#define L2_ITLB_4K_ENTRIES 512
/* CPUID Leaf 0x14 constants: */
#define INTEL_PT_MAX_SUBLEAF 0x1
/*
* bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
* MSR can be accessed;
* bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
* bit[02]: Support IP Filtering, TraceStop filtering, and preservation
* of Intel PT MSRs across warm reset;
* bit[03]: Support MTC timing packet and suppression of COFI-based packets;
*/
#define INTEL_PT_MINIMAL_EBX 0xf
/*
* bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
* IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
* accessed;
* bit[01]: ToPA tables can hold any number of output entries, up to the
* maximum allowed by the MaskOrTableOffset field of
* IA32_RTIT_OUTPUT_MASK_PTRS;
* bit[02]: Support Single-Range Output scheme;
*/
#define INTEL_PT_MINIMAL_ECX 0x7
/* generated packets which contain IP payloads have LIP values */
#define INTEL_PT_IP_LIP (1 << 31)
#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
{
int i;
for (i = 0; i < 4; i++) {
dst[i] = vendor1 >> (8 * i);
dst[i + 4] = vendor2 >> (8 * i);
dst[i + 8] = vendor3 >> (8 * i);
}
dst[CPUID_VENDOR_SZ] = '\0';
}
#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
CPUID_PSE36 | CPUID_FXSR)
#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
CPUID_PAE | CPUID_SEP | CPUID_APIC)
#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
/* partly implemented:
CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
/* missing:
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
/* missing:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
CPUID_EXT_F16C, CPUID_EXT_RDRAND */
#ifdef TARGET_X86_64
#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
#else
#define TCG_EXT2_X86_64_FEATURES 0
#endif
#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
TCG_EXT2_X86_64_FEATURES)
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
#define TCG_EXT4_FEATURES 0
#define TCG_SVM_FEATURES CPUID_SVM_NPT
#define TCG_KVM_FEATURES 0
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
CPUID_7_0_EBX_ERMS)
/* missing:
CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
CPUID_7_0_EBX_RDSEED */
#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
/* CPUID_7_0_ECX_OSPKE is dynamic */ \
CPUID_7_0_ECX_LA57)
#define TCG_7_0_EDX_FEATURES 0
#define TCG_APM_FEATURES 0
#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
/* missing:
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
typedef enum FeatureWordType {
CPUID_FEATURE_WORD,
MSR_FEATURE_WORD,
} FeatureWordType;
typedef struct FeatureWordInfo {
FeatureWordType type;
/* feature flags names are taken from "Intel Processor Identification and
* the CPUID Instruction" and AMD's "CPUID Specification".
* In cases of disagreement between feature naming conventions,
* aliases may be added.
*/
const char *feat_names[32];
union {
/* If type==CPUID_FEATURE_WORD */
struct {
uint32_t eax; /* Input EAX for CPUID */
bool needs_ecx; /* CPUID instruction uses ECX as input */
uint32_t ecx; /* Input ECX value for CPUID */
int reg; /* output register (R_* constant) */
} cpuid;
/* If type==MSR_FEATURE_WORD */
struct {
uint32_t index;
struct { /*CPUID that enumerate this MSR*/
FeatureWord cpuid_class;
uint32_t cpuid_flag;
} cpuid_dep;
} msr;
};
uint32_t tcg_features; /* Feature flags supported by TCG */
uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
uint32_t migratable_flags; /* Feature flags known to be migratable */
/* Features that shouldn't be auto-enabled by "-cpu host" */
uint32_t no_autoenable_flags;
} FeatureWordInfo;
static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"fpu", "vme", "de", "pse",
"tsc", "msr", "pae", "mce",
"cx8", "apic", NULL, "sep",
"mtrr", "pge", "mca", "cmov",
"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
NULL, "ds" /* Intel dts */, "acpi", "mmx",
"fxsr", "sse", "sse2", "ss",
"ht" /* Intel htt */, "tm", "ia64", "pbe",
},
.cpuid = {.eax = 1, .reg = R_EDX, },
.tcg_features = TCG_FEATURES,
},
[FEAT_1_ECX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
"ds-cpl", "vmx", "smx", "est",
"tm2", "ssse3", "cid", NULL,
"fma", "cx16", "xtpr", "pdcm",
NULL, "pcid", "dca", "sse4.1",
"sse4.2", "x2apic", "movbe", "popcnt",
"tsc-deadline", "aes", "xsave", NULL /* osxsave */,
"avx", "f16c", "rdrand", "hypervisor",
},
.cpuid = { .eax = 1, .reg = R_ECX, },
.tcg_features = TCG_EXT_FEATURES,
},
/* Feature names that are already defined on feature_name[] but
* are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
* names on feat_names below. They are copied automatically
* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
*/
[FEAT_8000_0001_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
"nx", NULL, "mmxext", NULL /* mmx */,
NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
NULL, "lm", "3dnowext", "3dnow",
},
.cpuid = { .eax = 0x80000001, .reg = R_EDX, },
.tcg_features = TCG_EXT2_FEATURES,
},
[FEAT_8000_0001_ECX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"lahf-lm", "cmp-legacy", "svm", "extapic",
"cr8legacy", "abm", "sse4a", "misalignsse",
"3dnowprefetch", "osvw", "ibs", "xop",
"skinit", "wdt", NULL, "lwp",
"fma4", "tce", NULL, "nodeid-msr",
NULL, "tbm", "topoext", "perfctr-core",
"perfctr-nb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x80000001, .reg = R_ECX, },
.tcg_features = TCG_EXT3_FEATURES,
/*
* TOPOEXT is always allowed but can't be enabled blindly by
* "-cpu host", as it requires consistent cache topology info
* to be provided so it doesn't confuse guests.
*/
.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
},
[FEAT_C000_0001_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "xstore", "xstore-en",
NULL, NULL, "xcrypt", "xcrypt-en",
"ace2", "ace2-en", "phe", "phe-en",
"pmm", "pmm-en", NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
.tcg_features = TCG_EXT4_FEATURES,
},
[FEAT_KVM] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"kvmclock-stable-bit", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
.tcg_features = TCG_KVM_FEATURES,
},
[FEAT_KVM_HINTS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"kvm-hint-dedicated", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
.tcg_features = TCG_KVM_FEATURES,
/*
* KVM hints aren't auto-enabled by -cpu host, they need to be
* explicitly enabled in the command-line.
*/
.no_autoenable_flags = ~0U,
},
/*
* .feat_names are commented out for Hyper-V enlightenments because we
* don't want to have two different ways for enabling them on QEMU command
* line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
* enabling several feature bits simultaneously, exposing these bits
* individually may just confuse guests.
*/
[FEAT_HYPERV_EAX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x40000003, .reg = R_EAX, },
},
[FEAT_HYPERV_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
NULL /* hv_post_messages */, NULL /* hv_signal_events */,
NULL /* hv_create_port */, NULL /* hv_connect_port */,
NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x40000003, .reg = R_EBX, },
},
[FEAT_HYPERV_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
NULL, NULL,
NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x40000003, .reg = R_EDX, },
},
[FEAT_HV_RECOMM_EAX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_recommend_pv_as_switch */,
NULL /* hv_recommend_pv_tlbflush_local */,
NULL /* hv_recommend_pv_tlbflush_remote */,
NULL /* hv_recommend_msr_apic_access */,
NULL /* hv_recommend_msr_reset */,
NULL /* hv_recommend_relaxed_timing */,
NULL /* hv_recommend_dma_remapping */,
NULL /* hv_recommend_int_remapping */,
NULL /* hv_recommend_x2apic_msrs */,
NULL /* hv_recommend_autoeoi_deprecation */,
NULL /* hv_recommend_pv_ipi */,
NULL /* hv_recommend_ex_hypercalls */,
NULL /* hv_hypervisor_is_nested */,
NULL /* hv_recommend_int_mbec */,
NULL /* hv_recommend_evmcs */,
NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x40000004, .reg = R_EAX, },
},
[FEAT_HV_NESTED_EAX] = {
.type = CPUID_FEATURE_WORD,
.cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
},
[FEAT_SVM] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"npt", "lbrv", "svm-lock", "nrip-save",
"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
NULL, NULL, "pause-filter", NULL,
"pfthreshold", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
.tcg_features = TCG_SVM_FEATURES,
},
[FEAT_7_0_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"fsgsbase", "tsc-adjust", NULL, "bmi1",
"hle", "avx2", NULL, "smep",
"bmi2", "erms", "invpcid", "rtm",
NULL, NULL, "mpx", NULL,
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt",
"clwb", "intel-pt", "avx512pf", "avx512er",
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
},
.cpuid = {
.eax = 7,
.needs_ecx = true, .ecx = 0,
.reg = R_EBX,
},
.tcg_features = TCG_7_0_EBX_FEATURES,
},
[FEAT_7_0_ECX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
NULL /* ospke */, NULL, "avx512vbmi2", NULL,
"gfni", "vaes", "vpclmulqdq", "avx512vnni",
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
NULL, NULL, "rdpid", NULL,
NULL, "cldemote", NULL, "movdiri",
"movdir64b", NULL, NULL, NULL,
},
.cpuid = {
.eax = 7,
.needs_ecx = true, .ecx = 0,
.reg = R_ECX,
},
.tcg_features = TCG_7_0_ECX_FEATURES,
},
[FEAT_7_0_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, "spec-ctrl", "stibp",
NULL, "arch-capabilities", NULL, "ssbd",
},
.cpuid = {
.eax = 7,
.needs_ecx = true, .ecx = 0,
.reg = R_EDX,
},
.tcg_features = TCG_7_0_EDX_FEATURES,
},
[FEAT_8000_0007_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"invtsc", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x80000007, .reg = R_EDX, },
.tcg_features = TCG_APM_FEATURES,
.unmigratable_flags = CPUID_APM_INVTSC,
},
[FEAT_8000_0008_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL,
"ibpb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 0x80000008, .reg = R_EBX, },
.tcg_features = 0,
.unmigratable_flags = 0,
},
[FEAT_XSAVE] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"xsaveopt", "xsavec", "xgetbv1", "xsaves",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = {
.eax = 0xd,
.needs_ecx = true, .ecx = 1,
.reg = R_EAX,
},
.tcg_features = TCG_XSAVE_FEATURES,
},
[FEAT_6_EAX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "arat", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.cpuid = { .eax = 6, .reg = R_EAX, },
.tcg_features = TCG_6_EAX_FEATURES,
},
[FEAT_XSAVE_COMP_LO] = {
.type = CPUID_FEATURE_WORD,
.cpuid = {
.eax = 0xD,
.needs_ecx = true, .ecx = 0,
.reg = R_EAX,
},
.tcg_features = ~0U,
.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
XSTATE_PKRU_MASK,
},
[FEAT_XSAVE_COMP_HI] = {
.type = CPUID_FEATURE_WORD,
.cpuid = {
.eax = 0xD,
.needs_ecx = true, .ecx = 0,
.reg = R_EDX,
},
.tcg_features = ~0U,
},
/*Below are MSR exposed features*/
[FEAT_ARCH_CAPABILITIES] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
"rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
"ssb-no", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
.msr = {
.index = MSR_IA32_ARCH_CAPABILITIES,
.cpuid_dep = {
FEAT_7_0_EDX,
CPUID_7_0_EDX_ARCH_CAPABILITIES
}
},
},
};
typedef struct X86RegisterInfo32 {
/* Name of register */
const char *name;
/* QAPI enum value register */
X86CPURegister32 qapi_enum;
} X86RegisterInfo32;
#define REGISTER(reg) \
[R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
REGISTER(EAX),
REGISTER(ECX),
REGISTER(EDX),
REGISTER(EBX),
REGISTER(ESP),
REGISTER(EBP),
REGISTER(ESI),
REGISTER(EDI),
};
#undef REGISTER
typedef struct ExtSaveArea {
uint32_t feature, bits;
uint32_t offset, size;
} ExtSaveArea;
static const ExtSaveArea x86_ext_save_areas[] = {
[XSTATE_FP_BIT] = {
/* x87 FP state component is always enabled if XSAVE is supported */
.feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
/* x87 state is in the legacy region of the XSAVE area */
.offset = 0,
.size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
},
[XSTATE_SSE_BIT] = {
/* SSE state component is always enabled if XSAVE is supported */
.feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
/* SSE state is in the legacy region of the XSAVE area */
.offset = 0,
.size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
},
[XSTATE_YMM_BIT] =
{ .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = offsetof(X86XSaveArea, avx_state),
.size = sizeof(XSaveAVX) },
[XSTATE_BNDREGS_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.offset = offsetof(X86XSaveArea, bndreg_state),
.size = sizeof(XSaveBNDREG) },
[XSTATE_BNDCSR_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.offset = offsetof(X86XSaveArea, bndcsr_state),
.size = sizeof(XSaveBNDCSR) },
[XSTATE_OPMASK_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = offsetof(X86XSaveArea, opmask_state),
.size = sizeof(XSaveOpmask) },
[XSTATE_ZMM_Hi256_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = offsetof(X86XSaveArea, zmm_hi256_state),
.size = sizeof(XSaveZMM_Hi256) },
[XSTATE_Hi16_ZMM_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
.offset = offsetof(X86XSaveArea, hi16_zmm_state),
.size = sizeof(XSaveHi16_ZMM) },
[XSTATE_PKRU_BIT] =
{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
.offset = offsetof(X86XSaveArea, pkru_state),
.size = sizeof(XSavePKRU) },
};
static uint32_t xsave_area_size(uint64_t mask)
{
int i;
uint64_t ret = 0;
for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i];
if ((mask >> i) & 1) {
ret = MAX(ret, esa->offset + esa->size);
}
}
return ret;
}
static inline bool accel_uses_host_cpuid(void)
{
return kvm_enabled() || hvf_enabled();
}
static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
{
return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
cpu->env.features[FEAT_XSAVE_COMP_LO];
}
const char *get_register_name_32(unsigned int reg)
{
if (reg >= CPU_NB_REGS32) {
return NULL;
}
return x86_reg_info_32[reg].name;
}
/*
* Returns the set of feature flags that are supported and migratable by
* QEMU, for a given FeatureWord.
*/
static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
{
FeatureWordInfo *wi = &feature_word_info[w];
uint32_t r = 0;
int i;
for (i = 0; i < 32; i++) {
uint32_t f = 1U << i;
/* If the feature name is known, it is implicitly considered migratable,
* unless it is explicitly set in unmigratable_flags */
if ((wi->migratable_flags & f) ||
(wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
r |= f;
}
}
return r;
}
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
{
uint32_t vec[4];
#ifdef __x86_64__
asm volatile("cpuid"
: "=a"(vec[0]), "=b"(vec[1]),
"=c"(vec[2]), "=d"(vec[3])
: "0"(function), "c"(count) : "cc");
#elif defined(__i386__)
asm volatile("pusha \n\t"
"cpuid \n\t"
"mov %%eax, 0(%2) \n\t"
"mov %%ebx, 4(%2) \n\t"
"mov %%ecx, 8(%2) \n\t"
"mov %%edx, 12(%2) \n\t"
"popa"
: : "a"(function), "c"(count), "S"(vec)
: "memory", "cc");
#else
abort();
#endif
if (eax)
*eax = vec[0];
if (ebx)
*ebx = vec[1];
if (ecx)
*ecx = vec[2];
if (edx)
*edx = vec[3];
}
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
{
uint32_t eax, ebx, ecx, edx;
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
if (family) {
*family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
}
if (model) {
*model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
}
if (stepping) {
*stepping = eax & 0x0F;
}
}
/* CPU class name definitions: */
/* Return type name for a given CPU model name
* Caller is responsible for freeing the returned string.
*/
static char *x86_cpu_type_name(const char *model_name)
{
return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
}
static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
char *typename = x86_cpu_type_name(cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
return oc;
}
static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
{
const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
return g_strndup(class_name,
strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
}
struct X86CPUDefinition {
const char *name;
uint32_t level;
uint32_t xlevel;
/* vendor is zero-terminated, 12 character ASCII string */
char vendor[CPUID_VENDOR_SZ + 1];
int family;
int model;
int stepping;
FeatureWordArray features;
const char *model_id;
CPUCaches *cache_info;
};
static CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
.level = 1,
.size = 32 * KiB,
.line_size = 64,
.associativity = 8,
.partitions = 1,
.sets = 64,
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
.level = 1,
.size = 64 * KiB,
.line_size = 64,
.associativity = 4,
.partitions = 1,
.sets = 256,
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
.level = 2,
.size = 512 * KiB,
.line_size = 64,
.associativity = 8,
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
.level = 3,
.size = 8 * MiB,
.line_size = 64,
.associativity = 16,
.partitions = 1,
.sets = 8192,
.lines_per_tag = 1,
.self_init = true,
.inclusive = true,
.complex_indexing = true,
},
};
static X86CPUDefinition builtin_x86_defs[] = {
{
.name = "qemu64",
.level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 6,
.model = 6,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_CX16,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
.xlevel = 0x8000000A,
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
},
{
.name = "phenom",
.level = 5,
.vendor = CPUID_VENDOR_AMD,
.family = 16,
.model = 2,
.stepping = 3,
/* Missing: CPUID_HT */
.features[FEAT_1_EDX] =
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36 | CPUID_VME,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
CPUID_EXT_POPCNT,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
CPUID_EXT3_CR8LEG,
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
/* Missing: CPUID_SVM_LBRV */
.features[FEAT_SVM] =
CPUID_SVM_NPT,
.xlevel = 0x8000001A,
.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
},
{
.name = "core2duo",
.level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 15,
.stepping = 11,
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
.features[FEAT_1_EDX] =
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
/* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
* CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
CPUID_EXT_CX16,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
},
{
.name = "kvm64",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 15,
.model = 6,
.stepping = 1,
/* Missing: CPUID_HT */
.features[FEAT_1_EDX] =
PPRO_FEATURES | CPUID_VME |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_CX16,
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
.features[FEAT_8000_0001_ECX] =
0,
.xlevel = 0x80000008,
.model_id = "Common KVM processor"
},
{
.name = "qemu32",
.level = 4,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 6,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3,
.xlevel = 0x80000004,
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
},
{
.name = "kvm32",
.level = 5,
.vendor = CPUID_VENDOR_INTEL,
.family = 15,
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
PPRO_FEATURES | CPUID_VME |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_ECX] =
0,
.xlevel = 0x80000008,
.model_id = "Common 32-bit KVM processor"
},
{
.name = "coreduo",
.level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 14,
.stepping = 8,
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
.features[FEAT_1_EDX] =
PPRO_FEATURES | CPUID_VME |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
CPUID_SS,
/* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
* CPUID_EXT_PDCM, CPUID_EXT_VMX */
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_NX,
.xlevel = 0x80000008,
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
},
{
.name = "486",
.level = 1,
.vendor = CPUID_VENDOR_INTEL,
.family = 4,
.model = 8,
.stepping = 0,
.features[FEAT_1_EDX] =
I486_FEATURES,
.xlevel = 0,
.model_id = "",
},
{
.name = "pentium",
.level = 1,
.vendor = CPUID_VENDOR_INTEL,
.family = 5,
.model = 4,
.stepping = 3,
.features[FEAT_1_EDX] =
PENTIUM_FEATURES,
.xlevel = 0,
.model_id = "",
},
{
.name = "pentium2",
.level = 2,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 5,
.stepping = 2,
.features[FEAT_1_EDX] =
PENTIUM2_FEATURES,
.xlevel = 0,
.model_id = "",
},
{
.name = "pentium3",
.level = 3,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 7,
.stepping = 3,
.features[FEAT_1_EDX] =
PENTIUM3_FEATURES,
.xlevel = 0,
.model_id = "",
},
{
.name = "athlon",
.level = 2,
.vendor = CPUID_VENDOR_AMD,
.family = 6,
.model = 2,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
CPUID_MCA,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
.xlevel = 0x80000008,
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
},
{
.name = "n270",
.level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 28,
.stepping = 2,
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
.features[FEAT_1_EDX] =
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
CPUID_ACPI | CPUID_SS,
/* Some CPUs got no CPUID_SEP */
/* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
* CPUID_EXT_XTPR */
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
CPUID_EXT_MOVBE,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
},
{
.name = "Conroe",
.level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 15,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
},
{
.name = "Penryn",
.level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 23,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
},
{
.name = "Nehalem",
.level = 11,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 26,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
},
{
.name = "Nehalem-IBRS",
.level = 11,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 26,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
},
{
.name = "Westmere",
.level = 11,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 44,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
},
{
.name = "Westmere-IBRS",
.level = 11,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 44,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
},
{
.name = "SandyBridge",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 42,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
},
{
.name = "SandyBridge-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 42,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
},
{
.name = "IvyBridge",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 58,
.stepping = 9,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
},
{
.name = "IvyBridge-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 58,
.stepping = 9,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
},
{
.name = "Haswell-noTSX",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 60,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX)",
},
{
.name = "Haswell-noTSX-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 60,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
},
{
.name = "Haswell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 60,
.stepping = 4,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell)",
},
{
.name = "Haswell-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 60,
.stepping = 4,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, IBRS)",
},
{
.name = "Broadwell-noTSX",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 61,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX)",
},
{
.name = "Broadwell-noTSX-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 61,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
},
{
.name = "Broadwell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 61,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell)",
},
{
.name = "Broadwell-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 61,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, IBRS)",
},
{
.name = "Skylake-Client",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 94,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake)",
},
{
.name = "Skylake-Client-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 94,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake, IBRS)",
},
{
.name = "Skylake-Server",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
.stepping = 4,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_PKU,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
},
{
.name = "Skylake-Server-IBRS",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
.stepping = 4,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_PKU,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
},
{
.name = "Cascadelake-Server",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
.stepping = 6,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_AVX512VNNI,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cascadelake)",
},
{
.name = "Icelake-Client",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 126,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_8000_0008_EBX] =
CPUID_8000_0008_EBX_WBNOINVD,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Icelake)",
},
{
.name = "Icelake-Server",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 134,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_8000_0008_EBX] =
CPUID_8000_0008_EBX_WBNOINVD,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
},
{
.name = "KnightsMill",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 133,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
CPUID_PSE | CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
CPUID_7_0_EBX_AVX512ER,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Phi Processor (Knights Mill)",
},
{
.name = "Opteron_G1",
.level = 5,
.vendor = CPUID_VENDOR_AMD,
.family = 15,
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
},
{
.name = "Opteron_G2",
.level = 5,
.vendor = CPUID_VENDOR_AMD,
.family = 15,
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_CX16 | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
},
{
.name = "Opteron_G3",
.level = 5,
.vendor = CPUID_VENDOR_AMD,
.family = 16,
.model = 2,
.stepping = 3,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
CPUID_EXT2_RDTSCP,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
},
{
.name = "Opteron_G4",
.level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 21,
.model = 1,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM,
.features[FEAT_SVM] =
CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
/* no xsaveopt! */
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 62xx class CPU",
},
{
.name = "Opteron_G5",
.level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 21,
.model = 2,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM,
.features[FEAT_SVM] =
CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
/* no xsaveopt! */
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 63xx class CPU",
},
{
.name = "EPYC",
.level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 23,
.model = 1,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
CPUID_VME | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
CPUID_EXT3_TOPOEXT,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
CPUID_7_0_EBX_SHA_NI,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.features[FEAT_SVM] =
CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
},
{
.name = "EPYC-IBPB",
.level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 23,
.model = 1,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
CPUID_VME | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
CPUID_EXT3_TOPOEXT,
.features[FEAT_8000_0008_EBX] =
CPUID_8000_0008_EBX_IBPB,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
CPUID_7_0_EBX_SHA_NI,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.features[FEAT_SVM] =
CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor (with IBPB)",
.cache_info = &epyc_cache_info,
},
};
typedef struct PropValue {
const char *prop, *value;
} PropValue;
/* KVM-specific features that are automatically added/removed
* from all CPU models when KVM is enabled.
*/
static PropValue kvm_default_props[] = {
{ "kvmclock", "on" },
{ "kvm-nopiodelay", "on" },
{ "kvm-asyncpf", "on" },
{ "kvm-steal-time", "on" },
{ "kvm-pv-eoi", "on" },
{ "kvmclock-stable-bit", "on" },
{ "x2apic", "on" },
{ "acpi", "off" },
{ "monitor", "off" },
{ "svm", "off" },
{ NULL, NULL },
};
/* TCG-specific defaults that override all CPU models when using TCG
*/
static PropValue tcg_default_props[] = {
{ "vme", "off" },
{ NULL, NULL },
};
void x86_cpu_change_kvm_default(const char *prop, const char *value)
{
PropValue *pv;
for (pv = kvm_default_props; pv->prop; pv++) {
if (!strcmp(pv->prop, prop)) {
pv->value = value;
break;
}
}
/* It is valid to call this function only for properties that
* are already present in the kvm_default_props table.
*/
assert(pv->prop);
}
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only);
static bool lmce_supported(void)
{
uint64_t mce_cap = 0;
#ifdef CONFIG_KVM
if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
return false;
}
#endif
return !!(mce_cap & MCG_LMCE_P);
}
#define CPUID_MODEL_ID_SZ 48
/**
* cpu_x86_fill_model_id:
* Get CPUID model ID string from host CPU.
*
* @str should have at least CPUID_MODEL_ID_SZ bytes
*
* The function does NOT add a null terminator to the string
* automatically.
*/
static int cpu_x86_fill_model_id(char *str)
{
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
int i;
for (i = 0; i < 3; i++) {
host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
memcpy(str + i * 16 + 0, &eax, 4);
memcpy(str + i * 16 + 4, &ebx, 4);
memcpy(str + i * 16 + 8, &ecx, 4);
memcpy(str + i * 16 + 12, &edx, 4);
}
return 0;
}
static Property max_x86_cpu_properties[] = {
DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
DEFINE_PROP_END_OF_LIST()
};
static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
X86CPUClass *xcc = X86_CPU_CLASS(oc);
xcc->ordering = 9;
xcc->model_description =
"Enables all features supported by the accelerator in the current host";
dc->props = max_x86_cpu_properties;
}
static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
static void max_x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
KVMState *s = kvm_state;
/* We can't fill the features array here because we don't know yet if
* "migratable" is true or false.
*/
cpu->max_features = true;
if (accel_uses_host_cpuid()) {
char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
int family, model, stepping;
X86CPUDefinition host_cpudef = { };
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
host_vendor_fms(vendor, &family, &model, &stepping);
cpu_x86_fill_model_id(model_id);
object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
object_property_set_int(OBJECT(cpu), stepping, "stepping",
&error_abort);
object_property_set_str(OBJECT(cpu), model_id, "model-id",
&error_abort);
if (kvm_enabled()) {
env->cpuid_min_level =
kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
env->cpuid_min_xlevel =
kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
env->cpuid_min_xlevel2 =
kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
} else {
env->cpuid_min_level =
hvf_get_supported_cpuid(0x0, 0, R_EAX);
env->cpuid_min_xlevel =
hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
env->cpuid_min_xlevel2 =
hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
}
if (lmce_supported()) {
object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
}
} else {
object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
"vendor", &error_abort);
object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
object_property_set_str(OBJECT(cpu),
"QEMU TCG CPU version " QEMU_HW_VERSION,
"model-id", &error_abort);
}
object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
}
static const TypeInfo max_x86_cpu_type_info = {
.name = X86_CPU_TYPE_NAME("max"),
.parent = TYPE_X86_CPU,
.instance_init = max_x86_cpu_initfn,
.class_init = max_x86_cpu_class_init,
};
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
xcc->host_cpuid_required = true;
xcc->ordering = 8;
#if defined(CONFIG_KVM)
xcc->model_description =
"KVM processor with all supported host features ";
#elif defined(CONFIG_HVF)
xcc->model_description =
"HVF processor with all supported host features ";
#endif
}
static const TypeInfo host_x86_cpu_type_info = {
.name = X86_CPU_TYPE_NAME("host"),
.parent = X86_CPU_TYPE_NAME("max"),
.class_init = host_x86_cpu_class_init,
};
#endif
static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
{
assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
switch (f->type) {
case CPUID_FEATURE_WORD:
{
const char *reg = get_register_name_32(f->cpuid.reg);
assert(reg);
return g_strdup_printf("CPUID.%02XH:%s",
f->cpuid.eax, reg);
}
case MSR_FEATURE_WORD:
return g_strdup_printf("MSR(%02XH)",
f->msr.index);
}
return NULL;
}
static void report_unavailable_features(FeatureWord w, uint32_t mask)
{
FeatureWordInfo *f = &feature_word_info[w];
int i;
char *feat_word_str;
for (i = 0; i < 32; ++i) {
if ((1UL << i) & mask) {
feat_word_str = feature_word_description(f, i);
warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
accel_uses_host_cpuid() ? "host" : "TCG",
feat_word_str,
f->feat_names[i] ? "." : "",
f->feat_names[i] ? f->feat_names[i] : "", i);
g_free(feat_word_str);
}
}
}
static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
int64_t value;
value = (env->cpuid_version >> 8) & 0xf;
if (value == 0xf) {
value += (env->cpuid_version >> 20) & 0xff;
}
visit_type_int(v, name, &value, errp);
}
static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xff + 0xf;
Error *local_err = NULL;
int64_t value;
visit_type_int(v, name, &value, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (value < min || value > max) {
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
return;
}
env->cpuid_version &= ~0xff00f00;
if (value > 0x0f) {
env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
} else {
env->cpuid_version |= value << 8;
}
}
static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
int64_t value;
value = (env->cpuid_version >> 4) & 0xf;
value |= ((env->cpuid_version >> 16) & 0xf) << 4;
visit_type_int(v, name, &value, errp);
}
static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xff;
Error *local_err = NULL;
int64_t value;
visit_type_int(v, name, &value, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (value < min || value > max) {
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
return;
}
env->cpuid_version &= ~0xf00f0;
env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
}
static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
int64_t value;
value = env->cpuid_version & 0xf;
visit_type_int(v, name, &value, errp);
}
static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xf;
Error *local_err = NULL;
int64_t value;
visit_type_int(v, name, &value, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (value < min || value > max) {
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
return;
}
env->cpuid_version &= ~0xf;
env->cpuid_version |= value & 0xf;
}
static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
char *value;
value = g_malloc(CPUID_VENDOR_SZ + 1);
x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
env->cpuid_vendor3);
return value;
}
static void x86_cpuid_set_vendor(Object *obj, const char *value,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
int i;
if (strlen(value) != CPUID_VENDOR_SZ) {
error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
return;
}
env->cpuid_vendor1 = 0;
env->cpuid_vendor2 = 0;
env->cpuid_vendor3 = 0;
for (i = 0; i < 4; i++) {
env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
}
}
static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
char *value;
int i;
value = g_malloc(48 + 1);
for (i = 0; i < 48; i++) {
value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
}
value[48] = '\0';
return value;
}
static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
CPUX86State *env = &cpu->env;
int c, len, i;
if (model_id == NULL) {
model_id = "";
}
len = strlen(model_id);
memset(env->cpuid_model, 0, 48);
for (i = 0; i < 48; i++) {
if (i >= len) {
c = '\0';
} else {
c = (uint8_t)model_id[i];
}
env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
}
}
static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
int64_t value;
value = cpu->env.tsc_khz * 1000;
visit_type_int(v, name, &value, errp);
}
static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
const int64_t min = 0;
const int64_t max = INT64_MAX;
Error *local_err = NULL;
int64_t value;
visit_type_int(v, name, &value, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (value < min || value > max) {
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
return;
}
cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
}
/* Generic getter for "feature-words" and "filtered-features" properties */
static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
uint32_t *array = (uint32_t *)opaque;
FeatureWord w;
X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
X86CPUFeatureWordInfoList *list = NULL;
for (w = 0; w < FEATURE_WORDS; w++) {
FeatureWordInfo *wi = &feature_word_info[w];
/*
* We didn't have MSR features when "feature-words" was
* introduced. Therefore skipped other type entries.
*/
if (wi->type != CPUID_FEATURE_WORD) {
continue;
}
X86CPUFeatureWordInfo *qwi = &word_infos[w];
qwi->cpuid_input_eax = wi->cpuid.eax;
qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
qwi->cpuid_input_ecx = wi->cpuid.ecx;
qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
qwi->features = array[w];
/* List will be in reverse order, but order shouldn't matter */
list_entries[w].next = list;
list_entries[w].value = &word_infos[w];
list = &list_entries[w];
}
visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
}
static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
int64_t value = cpu->hyperv_spinlock_attempts;
visit_type_int(v, name, &value, errp);
}
static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
const int64_t min = 0xFFF;
const int64_t max = UINT_MAX;
X86CPU *cpu = X86_CPU(obj);
Error *err = NULL;
int64_t value;
visit_type_int(v, name, &value, &err);
if (err) {
error_propagate(errp, err);
return;
}
if (value < min || value > max) {
error_setg(errp, "Property %s.%s doesn't take value %" PRId64
" (minimum: %" PRId64 ", maximum: %" PRId64 ")",
object_get_typename(obj), name ? name : "null",
value, min, max);
return;
}
cpu->hyperv_spinlock_attempts = value;
}
static const PropertyInfo qdev_prop_spinlocks = {
.name = "int",
.get = x86_get_hv_spinlocks,
.set = x86_set_hv_spinlocks,
};
/* Convert all '_' in a feature string option name to '-', to make feature
* name conform to QOM property naming rule, which uses '-' instead of '_'.
*/
static inline void feat2prop(char *s)
{
while ((s = strchr(s, '_'))) {
*s = '-';
}
}
/* Return the feature property name for a feature flag bit */
static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
{
/* XSAVE components are automatically enabled by other features,
* so return the original feature name instead
*/
if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
x86_ext_save_areas[comp].bits) {
w = x86_ext_save_areas[comp].feature;
bitnr = ctz32(x86_ext_save_areas[comp].bits);
}
}
assert(bitnr < 32);
assert(w < FEATURE_WORDS);
return feature_word_info[w].feat_names[bitnr];
}
/* Compatibily hack to maintain legacy +-feat semantic,
* where +-feat overwrites any feature set by
* feat=on|feat even if the later is parsed after +-feat
* (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
*/
static GList *plus_features, *minus_features;
static gint compare_string(gconstpointer a, gconstpointer b)
{
return g_strcmp0(a, b);
}
/* Parse "+feature,-feature,feature=foo" CPU feature string
*/
static void x86_cpu_parse_featurestr(const char *typename, char *features,
Error **errp)
{
char *featurestr; /* Single 'key=value" string being parsed */
static bool cpu_globals_initialized;
bool ambiguous = false;
if (cpu_globals_initialized) {
return;
}
cpu_globals_initialized = true;
if (!features) {
return;
}
for (featurestr = strtok(features, ",");
featurestr;
featurestr = strtok(NULL, ",")) {
const char *name;
const char *val = NULL;
char *eq = NULL;
char num[32];
GlobalProperty *prop;
/* Compatibility syntax: */
if (featurestr[0] == '+') {
plus_features = g_list_append(plus_features,
g_strdup(featurestr + 1));
continue;
} else if (featurestr[0] == '-') {
minus_features = g_list_append(minus_features,
g_strdup(featurestr + 1));
continue;
}
eq = strchr(featurestr, '=');
if (eq) {
*eq++ = 0;
val = eq;
} else {
val = "on";
}
feat2prop(featurestr);
name = featurestr;
if (g_list_find_custom(plus_features, name, compare_string)) {
warn_report("Ambiguous CPU model string. "
"Don't mix both \"+%s\" and \"%s=%s\"",
name, name, val);
ambiguous = true;
}
if (g_list_find_custom(minus_features, name, compare_string)) {
warn_report("Ambiguous CPU model string. "
"Don't mix both \"-%s\" and \"%s=%s\"",
name, name, val);
ambiguous = true;
}
/* Special case: */
if (!strcmp(name, "tsc-freq")) {
int ret;
uint64_t tsc_freq;
ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
if (ret < 0 || tsc_freq > INT64_MAX) {
error_setg(errp, "bad numerical value %s", val);
return;
}
snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
val = num;
name = "tsc-frequency";
}
prop = g_new0(typeof(*prop), 1);
prop->driver = typename;
prop->property = g_strdup(name);
prop->value = g_strdup(val);
qdev_prop_register_global(prop);
}
if (ambiguous) {
warn_report("Compatibility of ambiguous CPU model "
"strings won't be kept on future QEMU versions");
}
}
static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
static int x86_cpu_filter_features(X86CPU *cpu);
/* Check for missing features that may prevent the CPU class from
* running using the current machine and accelerator.
*/
static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
strList **missing_feats)
{
X86CPU *xc;
FeatureWord w;
Error *err = NULL;
strList **next = missing_feats;
if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
strList *new = g_new0(strList, 1);
new->value = g_strdup("kvm");
*missing_feats = new;
return;
}
xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
x86_cpu_expand_features(xc, &err);
if (err) {
/* Errors at x86_cpu_expand_features should never happen,
* but in case it does, just report the model as not
* runnable at all using the "type" property.
*/
strList *new = g_new0(strList, 1);
new->value = g_strdup("type");
*next = new;
next = &new->next;
}
x86_cpu_filter_features(xc);
for (w = 0; w < FEATURE_WORDS; w++) {
uint32_t filtered = xc->filtered_features[w];
int i;
for (i = 0; i < 32; i++) {
if (filtered & (1UL << i)) {
strList *new = g_new0(strList, 1);
new->value = g_strdup(x86_cpu_feature_name(w, i));
*next = new;
next = &new->next;
}
}
}
object_unref(OBJECT(xc));
}
/* Print all cpuid feature names in featureset
*/
static void listflags(FILE *f, fprintf_function print, GList *features)
{
size_t len = 0;
GList *tmp;
for (tmp = features; tmp; tmp = tmp->next) {
const char *name = tmp->data;
if ((len + strlen(name) + 1) >= 75) {
print(f, "\n");
len = 0;
}
print(f, "%s%s", len == 0 ? " " : " ", name);
len += strlen(name) + 1;
}
print(f, "\n");
}
/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
{
ObjectClass *class_a = (ObjectClass *)a;
ObjectClass *class_b = (ObjectClass *)b;
X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
char *name_a, *name_b;
int ret;
if (cc_a->ordering != cc_b->ordering) {
ret = cc_a->ordering - cc_b->ordering;
} else {
name_a = x86_cpu_class_get_model_name(cc_a);
name_b = x86_cpu_class_get_model_name(cc_b);
ret = strcmp(name_a, name_b);
g_free(name_a);
g_free(name_b);
}
return ret;
}
static GSList *get_sorted_cpu_model_list(void)
{
GSList *list = object_class_get_list(TYPE_X86_CPU, false);
list = g_slist_sort(list, x86_cpu_list_compare);
return list;
}
static void x86_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
X86CPUClass *cc = X86_CPU_CLASS(oc);
CPUListState *s = user_data;
char *name = x86_cpu_class_get_model_name(cc);
const char *desc = cc->model_description;
if (!desc && cc->cpu_def) {
desc = cc->cpu_def->model_id;
}
(*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
name, desc);
g_free(name);
}
/* list available CPU models and flags */
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
int i, j;
CPUListState s = {
.file = f,
.cpu_fprintf = cpu_fprintf,
};
GSList *list;
GList *names = NULL;
(*cpu_fprintf)(f, "Available CPUs:\n");
list = get_sorted_cpu_model_list();
g_slist_foreach(list, x86_cpu_list_entry, &s);
g_slist_free(list);
names = NULL;
for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
FeatureWordInfo *fw = &feature_word_info[i];
for (j = 0; j < 32; j++) {
if (fw->feat_names[j]) {
names = g_list_append(names, (gpointer)fw->feat_names[j]);
}
}
}
names = g_list_sort(names, (GCompareFunc)strcmp);
(*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
listflags(f, cpu_fprintf, names);
(*cpu_fprintf)(f, "\n");
g_list_free(names);
}
static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
X86CPUClass *cc = X86_CPU_CLASS(oc);
CpuDefinitionInfoList **cpu_list = user_data;
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
info = g_malloc0(sizeof(*info));
info->name = x86_cpu_class_get_model_name(cc);
x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
info->has_unavailable_features = true;
info->q_typename = g_strdup(object_class_get_name(oc));
info->migration_safe = cc->migration_safe;
info->has_migration_safe = true;
info->q_static = cc->static_model;
entry = g_malloc0(sizeof(*entry));
entry->value = info;
entry->next = *cpu_list;
*cpu_list = entry;
}
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
{
CpuDefinitionInfoList *cpu_list = NULL;
GSList *list = get_sorted_cpu_model_list();
g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
g_slist_free(list);
return cpu_list;
}
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only)
{
FeatureWordInfo *wi = &feature_word_info[w];
uint32_t r = 0;
if (kvm_enabled()) {
switch (wi->type) {
case CPUID_FEATURE_WORD:
r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
wi->cpuid.ecx,
wi->cpuid.reg);
break;
case MSR_FEATURE_WORD:
r = kvm_arch_get_supported_msr_feature(kvm_state,
wi->msr.index);
break;
}
} else if (hvf_enabled()) {
if (wi->type != CPUID_FEATURE_WORD) {
return 0;
}
r = hvf_get_supported_cpuid(wi->cpuid.eax,
wi->cpuid.ecx,
wi->cpuid.reg);
} else if (tcg_enabled()) {
r = wi->tcg_features;
} else {
return ~0;
}
if (migratable_only) {
r &= x86_cpu_get_migratable_flags(w);
}
return r;
}
static void x86_cpu_report_filtered_features(X86CPU *cpu)
{
FeatureWord w;
for (w = 0; w < FEATURE_WORDS; w++) {
report_unavailable_features(w, cpu->filtered_features[w]);
}
}
static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
{
PropValue *pv;
for (pv = props; pv->prop; pv++) {
if (!pv->value) {
continue;
}
object_property_parse(OBJECT(cpu), pv->value, pv->prop,
&error_abort);
}
}
/* Load data from X86CPUDefinition into a X86CPU object
*/
static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
{
CPUX86State *env = &cpu->env;
const char *vendor;
char host_vendor[CPUID_VENDOR_SZ + 1];
FeatureWord w;
/*NOTE: any property set by this function should be returned by
* x86_cpu_static_props(), so static expansion of
* query-cpu-model-expansion is always complete.
*/
/* CPU models only set _minimum_ values for level/xlevel: */
object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
object_property_set_int(OBJECT(cpu), def->family, "family", errp);
object_property_set_int(OBJECT(cpu), def->model, "model", errp);
object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
for (w = 0; w < FEATURE_WORDS; w++) {
env->features[w] = def->features[w];
}
/* legacy-cache defaults to 'off' if CPU model provides cache info */
cpu->legacy_cache = !def->cache_info;
/* Special cases not set in the X86CPUDefinition structs: */
/* TODO: in-kernel irqchip for hvf */
if (kvm_enabled()) {
if (!kvm_irqchip_in_kernel()) {
x86_cpu_change_kvm_default("x2apic", "off");
}
x86_cpu_apply_props(cpu, kvm_default_props);
} else if (tcg_enabled()) {
x86_cpu_apply_props(cpu, tcg_default_props);
}
env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
/* sysenter isn't supported in compatibility mode on AMD,
* syscall isn't supported in compatibility mode on Intel.
* Normally we advertise the actual CPU vendor, but you can
* override this using the 'vendor' property if you want to use
* KVM's sysenter/syscall emulation in compatibility mode and
* when doing cross vendor migration
*/
vendor = def->vendor;
if (accel_uses_host_cpuid()) {
uint32_t ebx = 0, ecx = 0, edx = 0;
host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
vendor = host_vendor;
}
object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
}
#ifndef CONFIG_USER_ONLY
/* Return a QDict containing keys for all properties that can be included
* in static expansion of CPU models. All properties set by x86_cpu_load_def()
* must be included in the dictionary.
*/
static QDict *x86_cpu_static_props(void)
{
FeatureWord w;
int i;
static const char *props[] = {
"min-level",
"min-xlevel",
"family",
"model",
"stepping",
"model-id",
"vendor",
"lmce",
NULL,
};
static QDict *d;
if (d) {
return d;
}
d = qdict_new();
for (i = 0; props[i]; i++) {
qdict_put_null(d, props[i]);
}
for (w = 0; w < FEATURE_WORDS; w++) {
FeatureWordInfo *fi = &feature_word_info[w];
int bit;
for (bit = 0; bit < 32; bit++) {
if (!fi->feat_names[bit]) {
continue;
}
qdict_put_null(d, fi->feat_names[bit]);
}
}
return d;
}
/* Add an entry to @props dict, with the value for property. */
static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
{
QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
&error_abort);
qdict_put_obj(props, prop, value);
}
/* Convert CPU model data from X86CPU object to a property dictionary
* that can recreate exactly the same CPU model.
*/
static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
{
QDict *sprops = x86_cpu_static_props();
const QDictEntry *e;
for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
const char *prop = qdict_entry_key(e);
x86_cpu_expand_prop(cpu, props, prop);
}
}
/* Convert CPU model data from X86CPU object to a property dictionary
* that can recreate exactly the same CPU model, including every
* writeable QOM property.
*/
static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
{
ObjectPropertyIterator iter;
ObjectProperty *prop;
object_property_iter_init(&iter, OBJECT(cpu));
while ((prop = object_property_iter_next(&iter))) {
/* skip read-only or write-only properties */
if (!prop->get || !prop->set) {
continue;
}
/* "hotplugged" is the only property that is configurable
* on the command-line but will be set differently on CPUs
* created using "-cpu ... -smp ..." and by CPUs created
* on the fly by x86_cpu_from_model() for querying. Skip it.
*/
if (!strcmp(prop->name, "hotplugged")) {
continue;
}
x86_cpu_expand_prop(cpu, props, prop->name);
}
}
static void object_apply_props(Object *obj, QDict *props, Error **errp)
{
const QDictEntry *prop;
Error *err = NULL;
for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
object_property_set_qobject(obj, qdict_entry_value(prop),
qdict_entry_key(prop), &err);
if (err) {
break;
}
}
error_propagate(errp, err);
}
/* Create X86CPU object according to model+props specification */
static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
{
X86CPU *xc = NULL;
X86CPUClass *xcc;
Error *err = NULL;
xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
if (xcc == NULL) {
error_setg(&err, "CPU model '%s' not found", model);
goto out;
}
xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
if (props) {
object_apply_props(OBJECT(xc), props, &err);
if (err) {
goto out;
}
}
x86_cpu_expand_features(xc, &err);
if (err) {
goto out;
}
out:
if (err) {
error_propagate(errp, err);
object_unref(OBJECT(xc));
xc = NULL;
}
return xc;
}
CpuModelExpansionInfo *
qmp_query_cpu_model_expansion(CpuModelExpansionType type,
CpuModelInfo *model,
Error **errp)
{
X86CPU *xc = NULL;
Error *err = NULL;
CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
QDict *props = NULL;
const char *base_name;
xc = x86_cpu_from_model(model->name,
model->has_props ?
qobject_to(QDict, model->props) :
NULL, &err);
if (err) {
goto out;
}
props = qdict_new();
ret->model = g_new0(CpuModelInfo, 1);
ret->model->props = QOBJECT(props);
ret->model->has_props = true;
switch (type) {
case CPU_MODEL_EXPANSION_TYPE_STATIC:
/* Static expansion will be based on "base" only */
base_name = "base";
x86_cpu_to_dict(xc, props);
break;
case CPU_MODEL_EXPANSION_TYPE_FULL:
/* As we don't return every single property, full expansion needs
* to keep the original model name+props, and add extra
* properties on top of that.
*/
base_name = model->name;
x86_cpu_to_dict_full(xc, props);
break;
default:
error_setg(&err, "Unsupported expansion type");
goto out;
}
x86_cpu_to_dict(xc, props);
ret->model->name = g_strdup(base_name);
out:
object_unref(OBJECT(xc));
if (err) {
error_propagate(errp, err);
qapi_free_CpuModelExpansionInfo(ret);
ret = NULL;
}
return ret;
}
#endif /* !CONFIG_USER_ONLY */
static gchar *x86_gdb_arch_name(CPUState *cs)
{
#ifdef TARGET_X86_64
return g_strdup("i386:x86-64");
#else
return g_strdup("i386");
#endif
}
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
X86CPUDefinition *cpudef = data;
X86CPUClass *xcc = X86_CPU_CLASS(oc);
xcc->cpu_def = cpudef;
xcc->migration_safe = true;
}
static void x86_register_cpudef_type(X86CPUDefinition *def)
{
char *typename = x86_cpu_type_name(def->name);
TypeInfo ti = {
.name = typename,
.parent = TYPE_X86_CPU,
.class_init = x86_cpu_cpudef_class_init,
.class_data = def,
};
/* AMD aliases are handled at runtime based on CPUID vendor, so
* they shouldn't be set on the CPU model table.
*/
assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
/* catch mistakes instead of silently truncating model_id when too long */
assert(def->model_id && strlen(def->model_id) <= 48);
type_register(&ti);
g_free(typename);
}
#if !defined(CONFIG_USER_ONLY)
void cpu_clear_apic_feature(CPUX86State *env)
{
env->features[FEAT_1_EDX] &= ~CPUID_APIC;
}
#endif /* !CONFIG_USER_ONLY */
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = x86_env_get_cpu(env);
CPUState *cs = CPU(cpu);
uint32_t pkg_offset;
uint32_t limit;
uint32_t signature[3];
/* Calculate & apply limits for different index ranges */
if (index >= 0xC0000000) {
limit = env->cpuid_xlevel2;
} else if (index >= 0x80000000) {
limit = env->cpuid_xlevel;
} else if (index >= 0x40000000) {
limit = 0x40000001;
} else {
limit = env->cpuid_level;
}
if (index > limit) {
/* Intel documentation states that invalid EAX input will
* return the same information as EAX=cpuid_level
* (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
*/
index = env->cpuid_level;
}
switch(index) {
case 0:
*eax = env->cpuid_level;
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
break;
case 1:
*eax = env->cpuid_version;
*ebx = (cpu->apic_id << 24) |
8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
*ecx = env->features[FEAT_1_ECX];
if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
*ecx |= CPUID_EXT_OSXSAVE;
}
*edx = env->features[FEAT_1_EDX];
if (cs->nr_cores * cs->nr_threads > 1) {
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
*edx |= CPUID_HT;
}
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
if (cpu->cache_info_passthrough) {
host_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = 1; /* Number of CPUID[EAX=2] calls required */
*ebx = 0;
if (!cpu->enable_l3_cache) {
*ecx = 0;
} else {
*ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
}
*edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
break;
case 4:
/* cache info: needed for Core compatibility */
if (cpu->cache_info_passthrough) {
host_cpuid(index, count, eax, ebx, ecx, edx);
/* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
*eax &= ~0xFC000000;
if ((*eax & 31) && cs->nr_cores > 1) {
*eax |= (cs->nr_cores - 1) << 26;
}
} else {
*eax = 0;
switch (count) {
case 0: /* L1 dcache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
1, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
1, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
cs->nr_threads, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
if (cpu->enable_l3_cache) {
encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
(1 << pkg_offset), cs->nr_cores,
eax, ebx, ecx, edx);
break;
}
/* fall through */
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
break;
}
}
break;
case 5:
/* MONITOR/MWAIT Leaf */
*eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
*ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
*ecx = cpu->mwait.ecx; /* flags */
*edx = cpu->mwait.edx; /* mwait substates */
break;
case 6:
/* Thermal and Power Leaf */
*eax = env->features[FEAT_6_EAX];
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 7:
/* Structured Extended Feature Flags Enumeration Leaf */
if (count == 0) {
*eax = 0; /* Maximum ECX value for sub-leaves */
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
*ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
*ecx |= CPUID_7_0_ECX_OSPKE;
}
*edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 9:
/* Direct Cache Access Information Leaf */
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0xA:
/* Architectural Performance Monitoring Leaf */
if (kvm_enabled() && cpu->enable_pmu) {
KVMState *s = cs->kvm_state;
*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
} else if (hvf_enabled() && cpu->enable_pmu) {
*eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
*ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
*ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
*edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0xB:
/* Extended Topology Enumeration Leaf */
if (!cpu->enable_cpuid_0xb) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
*ecx = count & 0xff;
*edx = cpu->apic_id;
switch (count) {
case 0:
*eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
*eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
default:
*eax = 0;
*ebx = 0;
*ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
}
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
break;
case 0xD: {
/* Processor Extended State */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
break;
}
if (count == 0) {
*ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
*eax = env->features[FEAT_XSAVE_COMP_LO];
*edx = env->features[FEAT_XSAVE_COMP_HI];
*ebx = xsave_area_size(env->xcr0);
} else if (count == 1) {
*eax = env->features[FEAT_XSAVE];
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
const ExtSaveArea *esa = &x86_ext_save_areas[count];
*eax = esa->size;
*ebx = esa->offset;
}
}
break;
}
case 0x14: {
/* Intel Processor Trace Enumeration */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
!kvm_enabled()) {
break;
}
if (count == 0) {
*eax = INTEL_PT_MAX_SUBLEAF;
*ebx = INTEL_PT_MINIMAL_EBX;
*ecx = INTEL_PT_MINIMAL_ECX;
} else if (count == 1) {
*eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
*ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
}
break;
}
case 0x40000000:
/*
* CPUID code in kvm_arch_init_vcpu() ignores stuff
* set here, but we restrict to TCG none the less.
*/
if (tcg_enabled() && cpu->expose_tcg) {
memcpy(signature, "TCGTCGTCGTCG", 12);
*eax = 0x40000001;
*ebx = signature[0];
*ecx = signature[1];
*edx = signature[2];
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0x40000001:
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0x80000000:
*eax = env->cpuid_xlevel;
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
break;
case 0x80000001:
*eax = env->cpuid_version;
*ebx = 0;
*ecx = env->features[FEAT_8000_0001_ECX];
*edx = env->features[FEAT_8000_0001_EDX];
/* The Linux kernel checks for the CMPLegacy bit and
* discards multiple thread information if it is set.
* So don't set it here for Intel to make Linux guests happy.
*/
if (cs->nr_cores * cs->nr_threads > 1) {
if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
*ecx |= 1 << 1; /* CmpLegacy bit */
}
}
break;
case 0x80000002:
case 0x80000003:
case 0x80000004:
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
break;
case 0x80000005:
/* cache info (L1 cache) */
if (cpu->cache_info_passthrough) {
host_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
*ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
*edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
break;
case 0x80000006:
/* cache info (L2 cache) */
if (cpu->cache_info_passthrough) {
host_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
(L2_DTLB_2M_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
(L2_ITLB_2M_ENTRIES);
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
(L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES);
encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
cpu->enable_l3_cache ?
env->cache_info_amd.l3_cache : NULL,
ecx, edx);
break;
case 0x80000007:
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_8000_0007_EDX];
break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
/* 64 bit processor */
*eax = cpu->phys_bits; /* configurable physical bits */
if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
*eax |= 0x00003900; /* 57 bits virtual */
} else {
*eax |= 0x00003000; /* 48 bits virtual */
}
} else {
*eax = cpu->phys_bits;
}
*ebx = env->features[FEAT_8000_0008_EBX];
*ecx = 0;
*edx = 0;
if (cs->nr_cores * cs->nr_threads > 1) {
*ecx |= (cs->nr_cores * cs->nr_threads) - 1;
}
break;
case 0x8000000A:
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
*eax = 0x00000001; /* SVM Revision */
*ebx = 0x00000010; /* nr of ASIDs */
*ecx = 0;
*edx = env->features[FEAT_SVM]; /* optional features */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0x8000001D:
*eax = 0;
switch (count) {
case 0: /* L1 dcache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
eax, ebx, ecx, edx);
break;
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
break;
}
break;
case 0x8000001E:
assert(cpu->core_id <= 255);
encode_topo_cpuid8000001e(cs, cpu,
eax, ebx, ecx, edx);
break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0xC0000001:
/* Support for VIA CPU's CPUID instruction */
*eax = env->cpuid_version;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_C000_0001_EDX];
break;
case 0xC0000002:
case 0xC0000003:
case 0xC0000004:
/* Reserved for the future, and now filled with zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0x8000001F:
*eax = sev_enabled() ? 0x2 : 0;
*ebx = sev_get_cbit_position();
*ebx |= sev_get_reduced_phys_bits() << 6;
*ecx = 0;
*edx = 0;
break;
default:
/* reserved values: zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
}
}
/* CPUClass::reset() */
static void x86_cpu_reset(CPUState *s)
{
X86CPU *cpu = X86_CPU(s);
X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
CPUX86State *env = &cpu->env;
target_ulong cr4;
uint64_t xcr0;
int i;
xcc->parent_reset(s);
memset(env, 0, offsetof(CPUX86State, end_reset_fields));
env->old_exception = -1;
/* init to reset state */
env->hflags2 |= HF2_GIF_MASK;
cpu_x86_update_cr0(env, 0x60000010);
env->a20_mask = ~0x0;
env->smbase = 0x30000;
env->msr_smi_count = 0;
env->idt.limit = 0xffff;
env->gdt.limit = 0xffff;
env->ldt.limit = 0xffff;
env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
env->tr.limit = 0xffff;
env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
DESC_R_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
env->eip = 0xfff0;
env->regs[R_EDX] = env->cpuid_version;
env->eflags = 0x2;
/* FPU init */
for (i = 0; i < 8; i++) {
env->fptags[i] = 1;
}
cpu_set_fpuc(env, 0x37f);
env->mxcsr = 0x1f80;
/* All units are in INIT state. */
env->xstate_bv = 0;
env->pat = 0x0007040600070406ULL;
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
memset(env->dr, 0, sizeof(env->dr));
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
cpu_breakpoint_remove_all(s, BP_CPU);
cpu_watchpoint_remove_all(s, BP_CPU);
cr4 = 0;
xcr0 = XSTATE_FP_MASK;
#ifdef CONFIG_USER_ONLY
/* Enable all the features for user-mode. */
if (env->features[FEAT_1_EDX] & CPUID_SSE) {
xcr0 |= XSTATE_SSE_MASK;
}
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i];
if (env->features[esa->feature] & esa->bits) {
xcr0 |= 1ull << i;
}
}
if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
}
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
cr4 |= CR4_FSGSBASE_MASK;
}
#endif
env->xcr0 = xcr0;
cpu_x86_update_cr4(env, cr4);
/*
* SDM 11.11.5 requires:
* - IA32_MTRR_DEF_TYPE MSR.E = 0
* - IA32_MTRR_PHYSMASKn.V = 0
* All other bits are undefined. For simplification, zero it all.
*/
env->mtrr_deftype = 0;
memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
env->interrupt_injected = -1;
env->exception_injected = -1;
env->nmi_injected = false;
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
s->halted = !cpu_is_bsp(cpu);
if (kvm_enabled()) {
kvm_arch_reset_vcpu(cpu);
}
else if (hvf_enabled()) {
hvf_reset_vcpu(s);
}
#endif
}
#ifndef CONFIG_USER_ONLY
bool cpu_is_bsp(X86CPU *cpu)
{
return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
}
/* TODO: remove me, when reset over QOM tree is implemented */
static void x86_cpu_machine_reset_cb(void *opaque)
{
X86CPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
#endif
static void mce_init(X86CPU *cpu)
{
CPUX86State *cenv = &cpu->env;
unsigned int bank;
if (((cenv->cpuid_version >> 8) & 0xf) >= 6
&& (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
(CPUID_MCE | CPUID_MCA)) {
cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
(cpu->enable_lmce ? MCG_LMCE_P : 0);
cenv->mcg_ctl = ~(uint64_t)0;
for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
cenv->mce_banks[bank * 4] = ~(uint64_t)0;
}
}
}
#ifndef CONFIG_USER_ONLY
APICCommonClass *apic_get_class(void)
{
const char *apic_type = "apic";
/* TODO: in-kernel irqchip for hvf */
if (kvm_apic_in_kernel()) {
apic_type = "kvm-apic";
} else if (xen_enabled()) {
apic_type = "xen-apic";
}
return APIC_COMMON_CLASS(object_class_by_name(apic_type));
}
static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
{
APICCommonState *apic;
ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
object_property_add_child(OBJECT(cpu), "lapic",
OBJECT(cpu->apic_state), &error_abort);
object_unref(OBJECT(cpu->apic_state));
qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
/* TODO: convert to link<> */
apic = APIC_COMMON(cpu->apic_state);
apic->cpu = cpu;
apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
}
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
APICCommonState *apic;
static bool apic_mmio_map_once;
if (cpu->apic_state == NULL) {
return;
}
object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
errp);
/* Map APIC MMIO area */
apic = APIC_COMMON(cpu->apic_state);
if (!apic_mmio_map_once) {
memory_region_add_subregion_overlap(get_system_memory(),
apic->apicbase &
MSR_IA32_APICBASE_BASE,
&apic->io_memory,
0x1000);
apic_mmio_map_once = true;
}
}
static void x86_cpu_machine_done(Notifier *n, void *unused)
{
X86CPU *cpu = container_of(n, X86CPU, machine_done);
MemoryRegion *smram =
(MemoryRegion *) object_resolve_path("/machine/smram", NULL);
if (smram) {
cpu->smram = g_new(MemoryRegion, 1);
memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
smram, 0, 1ull << 32);
memory_region_set_enabled(cpu->smram, true);
memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
}
}
#else
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
}
#endif
/* Note: Only safe for use on x86(-64) hosts */
static uint32_t x86_host_phys_bits(void)
{
uint32_t eax;
uint32_t host_phys_bits;
host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
if (eax >= 0x80000008) {
host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
/* Note: According to AMD doc 25481 rev 2.34 they have a field
* at 23:16 that can specify a maximum physical address bits for
* the guest that can override this value; but I've not seen
* anything with that set.
*/
host_phys_bits = eax & 0xff;
} else {
/* It's an odd 64 bit machine that doesn't have the leaf for
* physical address bits; fall back to 36 that's most older
* Intel.
*/
host_phys_bits = 36;
}
return host_phys_bits;
}
static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
{
if (*min < value) {
*min = value;
}
}
/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
{
CPUX86State *env = &cpu->env;
FeatureWordInfo *fi = &feature_word_info[w];
uint32_t eax = fi->cpuid.eax;
uint32_t region = eax & 0xF0000000;
assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
if (!env->features[w]) {
return;
}
switch (region) {
case 0x00000000:
x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
break;
case 0x80000000:
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
break;
case 0xC0000000:
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
break;
}
}
/* Calculate XSAVE components based on the configured CPU feature flags */
static void x86_cpu_enable_xsave_components(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
int i;
uint64_t mask;
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
return;
}
mask = 0;
for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i];
if (env->features[esa->feature] & esa->bits) {
mask |= (1ULL << i);
}
}
env->features[FEAT_XSAVE_COMP_LO] = mask;
env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
}
/***** Steps involved on loading and filtering CPUID data
*
* When initializing and realizing a CPU object, the steps
* involved in setting up CPUID data are:
*
* 1) Loading CPU model definition (X86CPUDefinition). This is
* implemented by x86_cpu_load_def() and should be completely
* transparent, as it is done automatically by instance_init.
* No code should need to look at X86CPUDefinition structs
* outside instance_init.
*
* 2) CPU expansion. This is done by realize before CPUID
* filtering, and will make sure host/accelerator data is
* loaded for CPU models that depend on host capabilities
* (e.g. "host"). Done by x86_cpu_expand_features().
*
* 3) CPUID filtering. This initializes extra data related to
* CPUID, and checks if the host supports all capabilities
* required by the CPU. Runnability of a CPU model is
* determined at this step. Done by x86_cpu_filter_features().
*
* Some operations don't require all steps to be performed.
* More precisely:
*
* - CPU instance creation (instance_init) will run only CPU
* model loading. CPU expansion can't run at instance_init-time
* because host/accelerator data may be not available yet.
* - CPU realization will perform both CPU model expansion and CPUID
* filtering, and return an error in case one of them fails.
* - query-cpu-definitions needs to run all 3 steps. It needs
* to run CPUID filtering, as the 'unavailable-features'
* field is set based on the filtering results.
* - The query-cpu-model-expansion QMP command only needs to run
* CPU model loading and CPU expansion. It should not filter
* any CPUID data based on host capabilities.
*/
/* Expand CPU configuration data, based on configured features
* and host/accelerator capabilities when appropriate.
*/
static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
{
CPUX86State *env = &cpu->env;
FeatureWord w;
GList *l;
Error *local_err = NULL;
/*TODO: Now cpu->max_features doesn't overwrite features
* set using QOM properties, and we can convert
* plus_features & minus_features to global properties
* inside x86_cpu_parse_featurestr() too.
*/
if (cpu->max_features) {
for (w = 0; w < FEATURE_WORDS; w++) {
/* Override only features that weren't set explicitly
* by the user.
*/
env->features[w] |=
x86_cpu_get_supported_feature_word(w, cpu->migratable) &
~env->user_features[w] & \
~feature_word_info[w].no_autoenable_flags;
}
}
for (l = plus_features; l; l = l->next) {
const char *prop = l->data;
object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
if (local_err) {
goto out;
}
}
for (l = minus_features; l; l = l->next) {
const char *prop = l->data;
object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
if (local_err) {
goto out;
}
}
if (!kvm_enabled() || !cpu->expose_kvm) {
env->features[FEAT_KVM] = 0;
}
x86_cpu_enable_xsave_components(cpu);
/* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
if (cpu->full_cpuid_auto_level) {
x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
/* Intel Processor Trace requires CPUID[0x14] */
if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
kvm_enabled() && cpu->intel_pt_auto_level) {
x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
}
/* SVM requires CPUID[0x8000000A] */
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
}
/* SEV requires CPUID[0x8000001F] */
if (sev_enabled()) {
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
}
}
/* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
if (env->cpuid_level == UINT32_MAX) {
env->cpuid_level = env->cpuid_min_level;
}
if (env->cpuid_xlevel == UINT32_MAX) {
env->cpuid_xlevel = env->cpuid_min_xlevel;
}
if (env->cpuid_xlevel2 == UINT32_MAX) {
env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
}
out:
if (local_err != NULL) {
error_propagate(errp, local_err);
}
}
/*
* Finishes initialization of CPUID data, filters CPU feature
* words based on host availability of each feature.
*
* Returns: 0 if all flags are supported by the host, non-zero otherwise.
*/
static int x86_cpu_filter_features(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
FeatureWord w;
int rv = 0;
for (w = 0; w < FEATURE_WORDS; w++) {
uint32_t host_feat =
x86_cpu_get_supported_feature_word(w, false);
uint32_t requested_features = env->features[w];
env->features[w] &= host_feat;
cpu->filtered_features[w] = requested_features & ~env->features[w];
if (cpu->filtered_features[w]) {
rv = 1;
}
}
if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
kvm_enabled()) {
KVMState *s = CPU(cpu)->kvm_state;
uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
if (!eax_0 ||
((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
INTEL_PT_ADDR_RANGES_NUM) ||
((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
(INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
(ecx_0 & INTEL_PT_IP_LIP)) {
/*
* Processor Trace capabilities aren't configurable, so if the
* host can't emulate the capabilities we report on
* cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
*/
env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
rv = 1;
}
}
return rv;
}
#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
(env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
(env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
(env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
(env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
X86CPU *cpu = X86_CPU(dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = &cpu->env;
Error *local_err = NULL;
static bool ht_warned;
if (xcc->host_cpuid_required) {
if (!accel_uses_host_cpuid()) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(&local_err, "CPU model '%s' requires KVM", name);
g_free(name);
goto out;
}
if (enable_cpu_pm) {
host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
&cpu->mwait.ecx, &cpu->mwait.edx);
env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
}
}
/* mwait extended info: needed for Core compatibility */
/* We always wake on interrupt even if host does not have the capability */
cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
error_setg(errp, "apic-id property was not initialized properly");
return;
}
x86_cpu_expand_features(cpu, &local_err);
if (local_err) {
goto out;
}
if (x86_cpu_filter_features(cpu) &&
(cpu->check_cpuid || cpu->enforce_cpuid)) {
x86_cpu_report_filtered_features(cpu);
if (cpu->enforce_cpuid) {
error_setg(&local_err,
accel_uses_host_cpuid() ?
"Host doesn't support requested features" :
"TCG doesn't support requested features");
goto out;
}
}
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
* CPUID[1].EDX.
*/
if (IS_AMD_CPU(env)) {
env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
& CPUID_EXT2_AMD_ALIASES);
}
/* For 64bit systems think about the number of physical bits to present.
* ideally this should be the same as the host; anything other than matching
* the host can cause incorrect guest behaviour.
* QEMU used to pick the magic value of 40 bits that corresponds to
* consumer AMD devices but nothing else.
*/
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
if (accel_uses_host_cpuid()) {
uint32_t host_phys_bits = x86_host_phys_bits();
static bool warned;
if (cpu->host_phys_bits) {
/* The user asked for us to use the host physical bits */
cpu->phys_bits = host_phys_bits;
if (cpu->host_phys_bits_limit &&
cpu->phys_bits > cpu->host_phys_bits_limit) {
cpu->phys_bits = cpu->host_phys_bits_limit;
}
}
/* Print a warning if the user set it to a value that's not the
* host value.
*/
if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
!warned) {
warn_report("Host physical bits (%u)"
" does not match phys-bits property (%u)",
host_phys_bits, cpu->phys_bits);
warned = true;
}
if (cpu->phys_bits &&
(cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
cpu->phys_bits < 32)) {
error_setg(errp, "phys-bits should be between 32 and %u "
" (but is %u)",
TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
return;
}
} else {
if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
error_setg(errp, "TCG only supports phys-bits=%u",
TCG_PHYS_ADDR_BITS);
return;
}
}
/* 0 means it was not explicitly set by the user (or by machine
* compat_props or by the host code above). In this case, the default
* is the value used by TCG (40).
*/
if (cpu->phys_bits == 0) {
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
}
} else {
/* For 32 bit systems don't use the user set value, but keep
* phys_bits consistent with what we tell the guest.
*/
if (cpu->phys_bits != 0) {
error_setg(errp, "phys-bits is not user-configurable in 32 bit");
return;
}
if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
cpu->phys_bits = 36;
} else {
cpu->phys_bits = 32;
}
}
/* Cache information initialization */
if (!cpu->legacy_cache) {
if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(errp,
"CPU model '%s' doesn't support legacy-cache=off", name);
g_free(name);
return;
}
env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
*xcc->cpu_def->cache_info;
} else {
/* Build legacy cache information */
env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
env->cache_info_amd.l3_cache = &legacy_l3_cache;
}
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
#ifndef CONFIG_USER_ONLY
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
x86_cpu_apic_create(cpu, &local_err);
if (local_err != NULL) {
goto out;
}
}
#endif
mce_init(cpu);
#ifndef CONFIG_USER_ONLY
if (tcg_enabled()) {
cpu->cpu_as_mem = g_new(MemoryRegion, 1);
cpu->cpu_as_root = g_new(MemoryRegion, 1);
/* Outer container... */
memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
memory_region_set_enabled(cpu->cpu_as_root, true);
/* ... with two regions inside: normal system memory with low
* priority, and...
*/
memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
get_system_memory(), 0, ~0ull);
memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
memory_region_set_enabled(cpu->cpu_as_mem, true);
cs->num_ases = 2;
cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
/* ... SMRAM with higher priority, linked from /machine/smram. */
cpu->machine_done.notify = x86_cpu_machine_done;
qemu_add_machine_init_done_notifier(&cpu->machine_done);
}
#endif
qemu_init_vcpu(cs);
/*
* Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
* fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
* based on inputs (sockets,cores,threads), it is still better to give
* users a warning.
*
* NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
* cs->nr_threads hasn't be populated yet and the checking is incorrect.
*/
if (IS_AMD_CPU(env) &&
!(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
cs->nr_threads > 1 && !ht_warned) {
warn_report("This family of AMD CPU doesn't support "
"hyperthreading(%d)",
cs->nr_threads);
error_printf("Please configure -smp options properly"
" or try enabling topoext feature.\n");
ht_warned = true;
}
x86_cpu_apic_realize(cpu, &local_err);
if (local_err != NULL) {
goto out;
}
cpu_reset(cs);
xcc->parent_realize(dev, &local_err);
out:
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
}
static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
{
X86CPU *cpu = X86_CPU(dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
Error *local_err = NULL;
#ifndef CONFIG_USER_ONLY
cpu_remove_sync(CPU(dev));
qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
#endif
if (cpu->apic_state) {
object_unparent(OBJECT(cpu->apic_state));
cpu->apic_state = NULL;
}
xcc->parent_unrealize(dev, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
}
typedef struct BitProperty {
FeatureWord w;
uint32_t mask;
} BitProperty;
static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
X86CPU *cpu = X86_CPU(obj);
BitProperty *fp = opaque;
uint32_t f = cpu->env.features[fp->w];
bool value = (f & fp->mask) == fp->mask;
visit_type_bool(v, name, &value, errp);
}
static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
DeviceState *dev = DEVICE(obj);
X86CPU *cpu = X86_CPU(obj);
BitProperty *fp = opaque;
Error *local_err = NULL;
bool value;
if (dev->realized) {
qdev_prop_set_after_realize(dev, name, errp);
return;
}
visit_type_bool(v, name, &value, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (value) {
cpu->env.features[fp->w] |= fp->mask;
} else {
cpu->env.features[fp->w] &= ~fp->mask;
}
cpu->env.user_features[fp->w] |= fp->mask;
}
static void x86_cpu_release_bit_prop(Object *obj, const char *name,
void *opaque)
{
BitProperty *prop = opaque;
g_free(prop);
}
/* Register a boolean property to get/set a single bit in a uint32_t field.
*
* The same property name can be registered multiple times to make it affect
* multiple bits in the same FeatureWord. In that case, the getter will return
* true only if all bits are set.
*/
static void x86_cpu_register_bit_prop(X86CPU *cpu,
const char *prop_name,
FeatureWord w,
int bitnr)
{
BitProperty *fp;
ObjectProperty *op;
uint32_t mask = (1UL << bitnr);
op = object_property_find(OBJECT(cpu), prop_name, NULL);
if (op) {
fp = op->opaque;
assert(fp->w == w);
fp->mask |= mask;
} else {
fp = g_new0(BitProperty, 1);
fp->w = w;
fp->mask = mask;
object_property_add(OBJECT(cpu), prop_name, "bool",
x86_cpu_get_bit_prop,
x86_cpu_set_bit_prop,
x86_cpu_release_bit_prop, fp, &error_abort);
}
}
static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
FeatureWord w,
int bitnr)
{
FeatureWordInfo *fi = &feature_word_info[w];
const char *name = fi->feat_names[bitnr];
if (!name) {
return;
}
/* Property names should use "-" instead of "_".
* Old names containing underscores are registered as aliases
* using object_property_add_alias()
*/
assert(!strchr(name, '_'));
/* aliases don't use "|" delimiters anymore, they are registered
* manually using object_property_add_alias() */
assert(!strchr(name, '|'));
x86_cpu_register_bit_prop(cpu, name, w, bitnr);
}
static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
GuestPanicInformation *panic_info = NULL;
if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
panic_info = g_malloc0(sizeof(GuestPanicInformation));
panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
assert(HV_CRASH_PARAMS >= 5);
panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
}
return panic_info;
}
static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
CPUState *cs = CPU(obj);
GuestPanicInformation *panic_info;
if (!cs->crash_occurred) {
error_setg(errp, "No crash occured");
return;
}
panic_info = x86_cpu_get_crash_info(cs);
if (panic_info == NULL) {
error_setg(errp, "No crash information");
return;
}
visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
errp);
qapi_free_GuestPanicInformation(panic_info);
}
static void x86_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
X86CPU *cpu = X86_CPU(obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
CPUX86State *env = &cpu->env;
FeatureWord w;
cs->env_ptr = env;
object_property_add(obj, "family", "int",
x86_cpuid_version_get_family,
x86_cpuid_version_set_family, NULL, NULL, NULL);
object_property_add(obj, "model", "int",
x86_cpuid_version_get_model,
x86_cpuid_version_set_model, NULL, NULL, NULL);
object_property_add(obj, "stepping", "int",
x86_cpuid_version_get_stepping,
x86_cpuid_version_set_stepping, NULL, NULL, NULL);
object_property_add_str(obj, "vendor",
x86_cpuid_get_vendor,
x86_cpuid_set_vendor, NULL);
object_property_add_str(obj, "model-id",
x86_cpuid_get_model_id,
x86_cpuid_set_model_id, NULL);
object_property_add(obj, "tsc-frequency", "int",
x86_cpuid_get_tsc_freq,
x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
x86_cpu_get_feature_words,
NULL, NULL, (void *)env->features, NULL);
object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
x86_cpu_get_feature_words,
NULL, NULL, (void *)cpu->filtered_features, NULL);
object_property_add(obj, "crash-information", "GuestPanicInformation",
x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
for (w = 0; w < FEATURE_WORDS; w++) {
int bitnr;
for (bitnr = 0; bitnr < 32; bitnr++) {
x86_cpu_register_feature_bit_props(cpu, w, bitnr);
}
}
object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
if (xcc->cpu_def) {
x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
}
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->apic_id;
}
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
X86CPU *cpu = X86_CPU(cs);
cpu->env.eip = value;
}
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = X86_CPU(cs);
cpu->env.eip = tb->pc - tb->cs_base;
}
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_POLL) {
return CPU_INTERRUPT_POLL;
}
#endif
if (interrupt_request & CPU_INTERRUPT_SIPI) {
return CPU_INTERRUPT_SIPI;
}
if (env->hflags2 & HF2_GIF_MASK) {
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
!(env->hflags & HF_SMM_MASK)) {
return CPU_INTERRUPT_SMI;
} else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
!(env->hflags2 & HF2_NMI_MASK)) {
return CPU_INTERRUPT_NMI;
} else if (interrupt_request & CPU_INTERRUPT_MCE) {
return CPU_INTERRUPT_MCE;
} else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
(((env->hflags2 & HF2_VINTR_MASK) &&
(env->hflags2 & HF2_HIF_MASK)) ||
(!(env->hflags2 & HF2_VINTR_MASK) &&
(env->eflags & IF_MASK &&
!(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
return CPU_INTERRUPT_HARD;
#if !defined(CONFIG_USER_ONLY)
} else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
(env->eflags & IF_MASK) &&
!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
return CPU_INTERRUPT_VIRQ;
#endif
}
}
return 0;
}
static bool x86_cpu_has_work(CPUState *cs)
{
return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
}
static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
: env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
: bfd_mach_i386_i8086);
info->print_insn = print_insn_i386;
info->cap_arch = CS_ARCH_X86;
info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
: env->hflags & HF_CS32_MASK ? CS_MODE_32
: CS_MODE_16);
info->cap_insn_unit = 1;
info->cap_insn_split = 8;
}
void x86_update_hflags(CPUX86State *env)
{
uint32_t hflags;
#define HFLAG_COPY_MASK \
~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
hflags = env->hflags & HFLAG_COPY_MASK;
hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
if (env->cr[4] & CR4_OSFXSR_MASK) {
hflags |= HF_OSFXSR_MASK;
}
if (env->efer & MSR_EFER_LMA) {
hflags |= HF_LMA_MASK;
}
if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
} else {
hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
(DESC_B_SHIFT - HF_CS32_SHIFT);
hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
(DESC_B_SHIFT - HF_SS32_SHIFT);
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
!(hflags & HF_CS32_MASK)) {
hflags |= HF_ADDSEG_MASK;
} else {
hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
}
}
env->hflags = hflags;
}
static Property x86_cpu_properties[] = {
#ifdef CONFIG_USER_ONLY
/* apic_id = 0 by default for *-user, see commit 9886e834 */
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
#else
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
#endif
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
{ .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
true),
/*
* lecacy_cache defaults to true unless the CPU model provides its
* own cache information (see x86_cpu_load_def()).
*/
DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
/*
* From "Requirements for Implementing the Microsoft
* Hypervisor Interface":
* https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
*
* "Starting with Windows Server 2012 and Windows 8, if
* CPUID.40000005.EAX contains a value of -1, Windows assumes that
* the hypervisor imposes no specific limit to the number of VPs.
* In this case, Windows Server 2012 guest VMs may use more than
* 64 VPs, up to the maximum supported number of processors applicable
* to the specific Windows version being used."
*/
DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
false),
DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
true),
DEFINE_PROP_END_OF_LIST()
};
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_parent_realize(dc, x86_cpu_realizefn,
&xcc->parent_realize);
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
&xcc->parent_unrealize);
dc->props = x86_cpu_properties;
xcc->parent_reset = cc->reset;
cc->reset = x86_cpu_reset;
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
#ifdef CONFIG_TCG
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
#endif
cc->dump_state = x86_cpu_dump_state;
cc->get_crash_info = x86_cpu_get_crash_info;
cc->set_pc = x86_cpu_set_pc;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifdef CONFIG_USER_ONLY
cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
#else
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
#endif
cc->gdb_arch_name = x86_gdb_arch_name;
#ifdef TARGET_X86_64
cc->gdb_core_xml_file = "i386-64bit.xml";
cc->gdb_num_core_regs = 66;
#else
cc->gdb_core_xml_file = "i386-32bit.xml";
cc->gdb_num_core_regs = 50;
#endif
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
cc->debug_excp_handler = breakpoint_handler;
#endif
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
#ifdef CONFIG_TCG
cc->tcg_initialize = tcg_x86_init;
#endif
cc->disas_set_info = x86_disas_set_info;
dc->user_creatable = true;
}
static const TypeInfo x86_cpu_type_info = {
.name = TYPE_X86_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(X86CPU),
.instance_init = x86_cpu_initfn,
.abstract = true,
.class_size = sizeof(X86CPUClass),
.class_init = x86_cpu_common_class_init,
};
/* "base" CPU model, used by query-cpu-model-expansion */
static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
xcc->static_model = true;
xcc->migration_safe = true;
xcc->model_description = "base CPU model type with no features enabled";
xcc->ordering = 8;
}
static const TypeInfo x86_base_cpu_type_info = {
.name = X86_CPU_TYPE_NAME("base"),
.parent = TYPE_X86_CPU,
.class_init = x86_cpu_base_class_init,
};
static void x86_cpu_register_types(void)
{
int i;
type_register_static(&x86_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
x86_register_cpudef_type(&builtin_x86_defs[i]);
}
type_register_static(&max_x86_cpu_type_info);
type_register_static(&x86_base_cpu_type_info);
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
type_register_static(&host_x86_cpu_type_info);
#endif
}
type_init(x86_cpu_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/roms/skiboot/hw/occ.c | /* Copyright 2013-2017 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <xscom.h>
#include <io.h>
#include <cpu.h>
#include <chip.h>
#include <mem_region.h>
#include <fsp.h>
#include <timebase.h>
#include <hostservices.h>
#include <errorlog.h>
#include <opal-api.h>
#include <opal-msg.h>
#include <timer.h>
#include <i2c.h>
#include <powercap.h>
#include <psr.h>
#include <sensor.h>
#include <occ.h>
/* OCC Communication Area for PStates */
#define P8_HOMER_OPAL_DATA_OFFSET 0x1F8000
#define P9_HOMER_OPAL_DATA_OFFSET 0x0E2000
#define OPAL_DYNAMIC_DATA_OFFSET 0x0B80
/* relative to HOMER_OPAL_DATA_OFFSET */
#define MAX_PSTATES 256
#define MAX_P8_CORES 12
#define MAX_P9_CORES 24
#define MAX_OPAL_CMD_DATA_LENGTH 4090
#define MAX_OCC_RSP_DATA_LENGTH 8698
#define P8_PIR_CORE_MASK 0xFFF8
#define P9_PIR_QUAD_MASK 0xFFF0
#define FREQ_MAX_IN_DOMAIN 0
#define FREQ_MOST_RECENTLY_SET 1
/**
* OCC-OPAL Shared Memory Region
*
* Reference document :
* https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Interfaces.pdf
*
* Supported layout versions:
* - 0x01, 0x02 : P8
* https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_pstate.h
*
* - 0x90 : P9
* https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pstate.h
* In 0x90 the data is separated into :-
* -- Static Data (struct occ_pstate_table): Data is written once by OCC
* -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime
*
* struct occ_pstate_table - Pstate table layout
* @valid: Indicates if data is valid
* @version: Layout version [Major/Minor]
* @v2.throttle: Reason for limiting the max pstate
* @v9.occ_role: OCC role (Master/Slave)
* @v#.pstate_min: Minimum pstate ever allowed
* @v#.pstate_nom: Nominal pstate
* @v#.pstate_turbo: Maximum turbo pstate
* @v#.pstate_ultra_turbo: Maximum ultra turbo pstate and the maximum
* pstate ever allowed
* @v#.pstates: Pstate-id and frequency list from Pmax to Pmin
* @v#.pstates.id: Pstate-id
* @v#.pstates.flags: Pstate-flag(reserved)
* @v2.pstates.vdd: Voltage Identifier
* @v2.pstates.vcs: Voltage Identifier
* @v#.pstates.freq_khz: Frequency in KHz
* @v#.core_max[1..N]: Max pstate with N active cores
* @spare/reserved/pad: Unused data
*/
struct occ_pstate_table {
u8 valid;
u8 version;
union __packed {
struct __packed { /* Version 0x01 and 0x02 */
u8 throttle;
s8 pstate_min;
s8 pstate_nom;
s8 pstate_turbo;
s8 pstate_ultra_turbo;
u8 spare;
u64 reserved;
struct __packed {
s8 id;
u8 flags;
u8 vdd;
u8 vcs;
u32 freq_khz;
} pstates[MAX_PSTATES];
s8 core_max[MAX_P8_CORES];
u8 pad[100];
} v2;
struct __packed { /* Version 0x90 */
u8 occ_role;
u8 pstate_min;
u8 pstate_nom;
u8 pstate_turbo;
u8 pstate_ultra_turbo;
u8 spare;
u64 reserved1;
u64 reserved2;
struct __packed {
u8 id;
u8 flags;
u16 reserved;
u32 freq_khz;
} pstates[MAX_PSTATES];
u8 core_max[MAX_P9_CORES];
u8 pad[56];
} v9;
};
} __packed;
/**
* OPAL-OCC Command Response Interface
*
* OPAL-OCC Command Buffer
*
* ---------------------------------------------------------------------
* | OPAL | Cmd | OPAL | | Cmd Data | Cmd Data | OPAL |
* | Cmd | Request | OCC | Reserved | Length | Length | Cmd |
* | Flags | ID | Cmd | | (MSB) | (LSB) | Data... |
* ---------------------------------------------------------------------
* | ….OPAL Command Data up to max of Cmd Data Length 4090 bytes |
* | |
* ---------------------------------------------------------------------
*
* OPAL Command Flag
*
* -----------------------------------------------------------------
* | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
* | (msb) | | | | | | | (lsb) |
* -----------------------------------------------------------------
* |Cmd | | | | | | | |
* |Ready | | | | | | | |
* -----------------------------------------------------------------
*
* struct opal_command_buffer - Defines the layout of OPAL command buffer
* @flag: Provides general status of the command
* @request_id: Token to identify request
* @cmd: Command sent
* @data_size: Command data length
* @data: Command specific data
* @spare: Unused byte
*/
struct opal_command_buffer {
u8 flag;
u8 request_id;
u8 cmd;
u8 spare;
u16 data_size;
u8 data[MAX_OPAL_CMD_DATA_LENGTH];
} __packed;
/**
* OPAL-OCC Response Buffer
*
* ---------------------------------------------------------------------
* | OCC | Cmd | OPAL | Response | Rsp Data | Rsp Data | OPAL |
* | Rsp | Request | OCC | Status | Length | Length | Rsp |
* | Flags | ID | Cmd | | (MSB) | (LSB) | Data... |
* ---------------------------------------------------------------------
* | ….OPAL Response Data up to max of Rsp Data Length 8698 bytes |
* | |
* ---------------------------------------------------------------------
*
* OCC Response Flag
*
* -----------------------------------------------------------------
* | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
* | (msb) | | | | | | | (lsb) |
* -----------------------------------------------------------------
* | | | | | | |OCC in | Rsp |
* | | | | | | |progress|Ready |
* -----------------------------------------------------------------
*
* struct occ_response_buffer - Defines the layout of OCC response buffer
* @flag: Provides general status of the response
* @request_id: Token to identify request
* @cmd: Command requested
* @status: Indicates success/failure status of
* the command
* @data_size: Response data length
* @data: Response specific data
*/
struct occ_response_buffer {
u8 flag;
u8 request_id;
u8 cmd;
u8 status;
u16 data_size;
u8 data[MAX_OCC_RSP_DATA_LENGTH];
} __packed;
/**
* OCC-OPAL Shared Memory Interface Dynamic Data Vx90
*
* struct occ_dynamic_data - Contains runtime attributes
* @occ_state: Current state of OCC
* @major_version: Major version number
* @minor_version: Minor version number (backwards compatible)
* Version 1 indicates GPU presence populated
* @gpus_present: Bitmask of GPUs present (on systems where GPU
* presence is detected through APSS)
* @cpu_throttle: Reason for limiting the max pstate
* @mem_throttle: Reason for throttling memory
* @quick_pwr_drop: Indicates if QPD is asserted
* @pwr_shifting_ratio: Indicates the current percentage of power to
* take away from the CPU vs GPU when shifting
* power to maintain a power cap. Value of 100
* means take all power from CPU.
* @pwr_cap_type: Indicates type of power cap in effect
* @hard_min_pwr_cap: Hard minimum system power cap in Watts.
* Guaranteed unless hardware failure
* @max_pwr_cap: Maximum allowed system power cap in Watts
* @cur_pwr_cap: Current system power cap
* @soft_min_pwr_cap: Soft powercap minimum. OCC may or may not be
* able to maintain this
* @spare/reserved: Unused data
* @cmd: Opal Command Buffer
* @rsp: OCC Response Buffer
*/
struct occ_dynamic_data {
u8 occ_state;
u8 major_version;
u8 minor_version;
u8 gpus_present;
u8 spare1;
u8 cpu_throttle;
u8 mem_throttle;
u8 quick_pwr_drop;
u8 pwr_shifting_ratio;
u8 pwr_cap_type;
u16 hard_min_pwr_cap;
u16 max_pwr_cap;
u16 cur_pwr_cap;
u16 soft_min_pwr_cap;
u8 pad[110];
struct opal_command_buffer cmd;
struct occ_response_buffer rsp;
} __packed;
static bool occ_reset;
static struct lock occ_lock = LOCK_UNLOCKED;
static unsigned long homer_opal_data_offset;
DEFINE_LOG_ENTRY(OPAL_RC_OCC_LOAD, OPAL_PLATFORM_ERR_EVT, OPAL_OCC,
OPAL_CEC_HARDWARE, OPAL_PREDICTIVE_ERR_GENERAL,
OPAL_NA);
DEFINE_LOG_ENTRY(OPAL_RC_OCC_RESET, OPAL_PLATFORM_ERR_EVT, OPAL_OCC,
OPAL_CEC_HARDWARE, OPAL_PREDICTIVE_ERR_GENERAL,
OPAL_NA);
DEFINE_LOG_ENTRY(OPAL_RC_OCC_PSTATE_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_OCC,
OPAL_CEC_HARDWARE, OPAL_INFO,
OPAL_NA);
DEFINE_LOG_ENTRY(OPAL_RC_OCC_TIMEOUT, OPAL_PLATFORM_ERR_EVT, OPAL_OCC,
OPAL_CEC_HARDWARE, OPAL_UNRECOVERABLE_ERR_GENERAL,
OPAL_NA);
/*
* POWER9 and newer platforms have pstate values which are unsigned
* positive values. They are continuous set of unsigned integers
* [0 to +N] where Pmax is 0 and Pmin is N. The linear ordering of
* pstates for P9 has changed compared to P8. Where P8 has negative
* pstate values advertised as [0 to -N] where Pmax is 0 and
* Pmin is -N. The following routine helps to abstract pstate
* comparison with pmax and perform sanity checks on pstate limits.
*/
/**
* cmp_pstates: Compares the given two pstates and determines which
* among them is associated with a higher pstate.
*
* @a,@b: The pstate ids of the pstates being compared.
*
* Returns: -1 : If pstate associated with @a is smaller than
* the pstate associated with @b.
* 0 : If pstates associated with @a and @b are equal.
* 1 : If pstate associated with @a is greater than
* the pstate associated with @b.
*/
static int cmp_pstates(int a, int b)
{
/* P8 has 0 to -N (pmax to pmin), P9 has 0 to +N (pmax to pmin) */
if (a > b)
return (proc_gen == proc_gen_p8)? 1 : -1;
else if (a < b)
return (proc_gen == proc_gen_p8)? -1 : 1;
return 0;
}
static inline
struct occ_pstate_table *get_occ_pstate_table(struct proc_chip *chip)
{
return (struct occ_pstate_table *)
(chip->homer_base + homer_opal_data_offset);
}
static inline
struct occ_dynamic_data *get_occ_dynamic_data(struct proc_chip *chip)
{
return (struct occ_dynamic_data *)
(chip->homer_base + homer_opal_data_offset +
OPAL_DYNAMIC_DATA_OFFSET);
}
/* Check each chip's HOMER/Sapphire area for PState valid bit */
static bool wait_for_all_occ_init(void)
{
struct proc_chip *chip;
struct dt_node *xn;
struct occ_pstate_table *occ_data;
int tries;
uint64_t start_time, end_time;
uint32_t timeout = 0;
if (platform.occ_timeout)
timeout = platform.occ_timeout();
start_time = mftb();
for_each_chip(chip) {
/* Check for valid homer address */
if (!chip->homer_base) {
/**
* @fwts-label OCCInvalidHomerBase
* @fwts-advice The HOMER base address for a chip
* was not valid. This means that OCC (On Chip
* Controller) will be non-functional and CPU
* frequency scaling will not be functional. CPU may
* be set to a safe, low frequency. Power savings in
* CPU idle or CPU hotplug may be impacted.
*/
prlog(PR_ERR,"OCC: Chip: %x homer_base is not valid\n",
chip->id);
return false;
}
/* Get PState table address */
occ_data = get_occ_pstate_table(chip);
/*
* Checking for occ_data->valid == 1 is ok because we clear all
* homer_base+size before passing memory to host services.
* This ensures occ_data->valid == 0 before OCC load
*/
tries = timeout * 10;
while((occ_data->valid != 1) && tries--) {
time_wait_ms(100);
}
if (occ_data->valid != 1) {
/**
* @fwts-label OCCInvalidPStateTable
* @fwts-advice The pstate table for a chip
* was not valid. This means that OCC (On Chip
* Controller) will be non-functional and CPU
* frequency scaling will not be functional. CPU may
* be set to a low, safe frequency. This means
* that CPU idle states and CPU frequency scaling
* may not be functional.
*/
prlog(PR_ERR, "OCC: Chip: %x PState table is not valid\n",
chip->id);
return false;
}
if (!chip->occ_functional)
chip->occ_functional = true;
prlog(PR_DEBUG, "OCC: Chip %02x Data (%016llx) = %016llx\n",
chip->id, (uint64_t)occ_data, *(uint64_t *)occ_data);
}
end_time = mftb();
prlog(PR_NOTICE, "OCC: All Chip Rdy after %lu ms\n",
tb_to_msecs(end_time - start_time));
dt_for_each_compatible(dt_root, xn, "ibm,xscom") {
const struct dt_property *p;
p = dt_find_property(xn, "ibm,occ-functional-state");
if (!p)
dt_add_property_cells(xn, "ibm,occ-functional-state",
0x1);
}
return true;
}
/*
* OCC provides pstate table entries in continuous descending order.
* Parse the pstate table to skip pstate_ids that are greater
* than Pmax. If a pstate_id is equal to Pmin then add it to
* the list and break from the loop as this is the last valid
* element in the pstate table.
*/
static void parse_pstates_v2(struct occ_pstate_table *data, u32 *dt_id,
u32 *dt_freq, int nr_pstates, int pmax, int pmin)
{
int i, j;
for (i = 0, j = 0; i < MAX_PSTATES && j < nr_pstates; i++) {
if (cmp_pstates(data->v2.pstates[i].id, pmax) > 0)
continue;
dt_id[j] = data->v2.pstates[i].id;
dt_freq[j] = data->v2.pstates[i].freq_khz / 1000;
j++;
if (data->v2.pstates[i].id == pmin)
break;
}
if (j != nr_pstates)
prerror("OCC: Expected pstates(%d) is not equal to parsed pstates(%d)\n",
nr_pstates, j);
}
static void parse_pstates_v9(struct occ_pstate_table *data, u32 *dt_id,
u32 *dt_freq, int nr_pstates, int pmax, int pmin)
{
int i, j;
for (i = 0, j = 0; i < MAX_PSTATES && j < nr_pstates; i++) {
if (cmp_pstates(data->v9.pstates[i].id, pmax) > 0)
continue;
dt_id[j] = data->v9.pstates[i].id;
dt_freq[j] = data->v9.pstates[i].freq_khz / 1000;
j++;
if (data->v9.pstates[i].id == pmin)
break;
}
if (j != nr_pstates)
prerror("OCC: Expected pstates(%d) is not equal to parsed pstates(%d)\n",
nr_pstates, j);
}
static void parse_vid(struct occ_pstate_table *occ_data,
struct dt_node *node, u8 nr_pstates,
int pmax, int pmin)
{
u8 *dt_vdd, *dt_vcs;
int i, j;
dt_vdd = malloc(nr_pstates);
assert(dt_vdd);
dt_vcs = malloc(nr_pstates);
assert(dt_vcs);
for (i = 0, j = 0; i < MAX_PSTATES && j < nr_pstates; i++) {
if (cmp_pstates(occ_data->v2.pstates[i].id, pmax) > 0)
continue;
dt_vdd[j] = occ_data->v2.pstates[i].vdd;
dt_vcs[j] = occ_data->v2.pstates[i].vcs;
j++;
if (occ_data->v2.pstates[i].id == pmin)
break;
}
dt_add_property(node, "ibm,pstate-vdds", dt_vdd, nr_pstates);
dt_add_property(node, "ibm,pstate-vcss", dt_vcs, nr_pstates);
free(dt_vdd);
free(dt_vcs);
}
/* Add device tree properties to describe pstates states */
/* Return nominal pstate to set in each core */
static bool add_cpu_pstate_properties(int *pstate_nom)
{
struct proc_chip *chip;
uint64_t occ_data_area;
struct occ_pstate_table *occ_data;
struct dt_node *power_mgt;
/* Arrays for device tree */
u32 *dt_id, *dt_freq;
int pmax, pmin, pnom;
u8 nr_pstates;
bool ultra_turbo_supported;
int i, major, minor;
u8 domain_runs_at;
u32 freq_domain_mask;
/* TODO Firmware plumbing required so as to have two modes to set
* PMCR based on max in domain or most recently used. As of today,
* it is always max in domain for P9.
*/
domain_runs_at = 0;
freq_domain_mask = 0;
prlog(PR_DEBUG, "OCC: CPU pstate state device tree init\n");
/* Find first chip */
chip = next_chip(NULL);
/* Extract PState information from OCC */
occ_data = get_occ_pstate_table(chip);
/* Dump first 16 bytes of PState table */
occ_data_area = (uint64_t)occ_data;
prlog(PR_DEBUG, "OCC: Data (%16llx) = %16llx %16llx\n",
occ_data_area,
*(uint64_t *)occ_data_area,
*(uint64_t *)(occ_data_area + 8));
if (!occ_data->valid) {
/**
* @fwts-label OCCInvalidPStateTableDT
* @fwts-advice The pstate table for the first chip
* was not valid. This means that OCC (On Chip
* Controller) will be non-functional. This means
* that CPU idle states and CPU frequency scaling
* will not be functional as OPAL doesn't populate
* the device tree with pstates in this case.
*/
prlog(PR_ERR, "OCC: PState table is not valid\n");
return false;
}
/*
* Workload-Optimized-Frequency(WOF) or Ultra-Turbo is supported
* from version 0x02 onwards. If WOF is disabled then, the max
* ultra_turbo pstate will be equal to max turbo pstate.
*/
ultra_turbo_supported = true;
major = occ_data->version >> 4;
minor = occ_data->version & 0xF;
/* Parse Pmax, Pmin and Pnominal */
switch (major) {
case 0:
if (proc_gen == proc_gen_p9) {
/**
* @fwts-label OCCInvalidVersion02
* @fwts-advice The PState table layout version is not
* supported in P9. So OPAL will not parse the PState
* table. CPU frequency scaling will not be functional
* as frequency and pstate-ids are not added to DT.
*/
prerror("OCC: Version %x is not supported in P9\n",
occ_data->version);
return false;
}
if (minor == 0x1)
ultra_turbo_supported = false;
pmin = occ_data->v2.pstate_min;
pnom = occ_data->v2.pstate_nom;
if (ultra_turbo_supported)
pmax = occ_data->v2.pstate_ultra_turbo;
else
pmax = occ_data->v2.pstate_turbo;
break;
case 0x9:
if (proc_gen == proc_gen_p8) {
/**
* @fwts-label OCCInvalidVersion90
* @fwts-advice The PState table layout version is not
* supported in P8. So OPAL will not parse the PState
* table. CPU frequency scaling will not be functional
* as frequency and pstate-ids are not added to DT.
*/
prerror("OCC: Version %x is not supported in P8\n",
occ_data->version);
return false;
}
pmin = occ_data->v9.pstate_min;
pnom = occ_data->v9.pstate_nom;
pmax = occ_data->v9.pstate_ultra_turbo;
break;
default:
/**
* @fwts-label OCCUnsupportedVersion
* @fwts-advice The PState table layout version is not
* supported. So OPAL will not parse the PState table.
* CPU frequency scaling will not be functional as OPAL
* doesn't populate the device tree with pstates.
*/
prerror("OCC: Unsupported pstate table layout version %d\n",
occ_data->version);
return false;
}
/* Sanity check for pstate limits */
if (cmp_pstates(pmin, pmax) > 0) {
/**
* @fwts-label OCCInvalidPStateLimits
* @fwts-advice The min pstate is greater than the
* max pstate, this could be due to corrupted/invalid
* data in OCC-OPAL shared memory region. So OPAL has
* not added pstates to device tree. This means that
* CPU Frequency management will not be functional in
* the host.
*/
prerror("OCC: Invalid pstate limits. Pmin(%d) > Pmax (%d)\n",
pmin, pmax);
return false;
}
if (cmp_pstates(pnom, pmax) > 0) {
/**
* @fwts-label OCCInvalidNominalPState
* @fwts-advice The nominal pstate is greater than the
* max pstate, this could be due to corrupted/invalid
* data in OCC-OPAL shared memory region. So OPAL has
* limited the nominal pstate to max pstate.
*/
prerror("OCC: Clipping nominal pstate(%d) to Pmax(%d)\n",
pnom, pmax);
pnom = pmax;
}
nr_pstates = labs(pmax - pmin) + 1;
prlog(PR_DEBUG, "OCC: Version %x Min %d Nom %d Max %d Nr States %d\n",
occ_data->version, pmin, pnom, pmax, nr_pstates);
if ((major == 0x9 && nr_pstates <= 1) ||
(major == 0 && (nr_pstates <= 1 || nr_pstates > 128))) {
/**
* @fwts-label OCCInvalidPStateRange
* @fwts-advice The number of pstates is outside the valid
* range (currently <=1 or > 128 on p8, >255 on P9), so OPAL
* has not added pstates to the device tree. This means that
* OCC (On Chip Controller) will be non-functional. This means
* that CPU idle states and CPU frequency scaling
* will not be functional.
*/
prerror("OCC: OCC range is not valid; No of pstates = %d\n",
nr_pstates);
return false;
}
power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt");
if (!power_mgt) {
/**
* @fwts-label OCCDTNodeNotFound
* @fwts-advice Device tree node /ibm,opal/power-mgt not
* found. OPAL didn't add pstate information to device tree.
* Probably a firmware bug.
*/
prlog(PR_ERR, "OCC: dt node /ibm,opal/power-mgt not found\n");
return false;
}
dt_id = malloc(nr_pstates * sizeof(u32));
assert(dt_id);
dt_freq = malloc(nr_pstates * sizeof(u32));
assert(dt_freq);
switch (major) {
case 0:
parse_pstates_v2(occ_data, dt_id, dt_freq, nr_pstates,
pmax, pmin);
break;
case 0x9:
parse_pstates_v9(occ_data, dt_id, dt_freq, nr_pstates,
pmax, pmin);
break;
default:
return false;
}
if (proc_gen == proc_gen_p8) {
freq_domain_mask = P8_PIR_CORE_MASK;
domain_runs_at = FREQ_MOST_RECENTLY_SET;
} else if (proc_gen == proc_gen_p9) {
freq_domain_mask = P9_PIR_QUAD_MASK;
domain_runs_at = FREQ_MAX_IN_DOMAIN;
}
/* Add the device-tree entries */
dt_add_property(power_mgt, "ibm,pstate-ids", dt_id,
nr_pstates * sizeof(u32));
dt_add_property(power_mgt, "ibm,pstate-frequencies-mhz", dt_freq,
nr_pstates * sizeof(u32));
dt_add_property_cells(power_mgt, "ibm,pstate-min", pmin);
dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom);
dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax);
dt_add_property_cells(power_mgt, "freq-domain-mask", freq_domain_mask);
dt_add_property_cells(power_mgt, "domain-runs-at", domain_runs_at);
free(dt_freq);
free(dt_id);
/*
* Parse and add WOF properties: turbo, ultra-turbo and core_max array.
* core_max[1..n] array provides the max sustainable pstate that can be
* achieved with i active cores in the chip.
*/
if (ultra_turbo_supported) {
int pturbo, pultra_turbo;
u8 nr_cores = get_available_nr_cores_in_chip(chip->id);
u32 *dt_cmax;
dt_cmax = malloc(nr_cores * sizeof(u32));
assert(dt_cmax);
switch (major) {
case 0:
pturbo = occ_data->v2.pstate_turbo;
pultra_turbo = occ_data->v2.pstate_ultra_turbo;
for (i = 0; i < nr_cores; i++)
dt_cmax[i] = occ_data->v2.core_max[i];
break;
case 0x9:
pturbo = occ_data->v9.pstate_turbo;
pultra_turbo = occ_data->v9.pstate_ultra_turbo;
for (i = 0; i < nr_cores; i++)
dt_cmax[i] = occ_data->v9.core_max[i];
break;
default:
return false;
}
if (cmp_pstates(pturbo, pmax) > 0) {
prerror("OCC: Clipping turbo pstate(%d) to Pmax(%d)\n",
pturbo, pmax);
dt_add_property_cells(power_mgt, "ibm,pstate-turbo",
pmax);
} else {
dt_add_property_cells(power_mgt, "ibm,pstate-turbo",
pturbo);
}
dt_add_property_cells(power_mgt, "ibm,pstate-ultra-turbo",
pultra_turbo);
dt_add_property(power_mgt, "ibm,pstate-core-max", dt_cmax,
nr_cores * sizeof(u32));
free(dt_cmax);
}
if (major == 0x9)
goto out;
dt_add_property_cells(power_mgt, "#address-cells", 2);
dt_add_property_cells(power_mgt, "#size-cells", 1);
/* Add chip specific pstate properties */
for_each_chip(chip) {
struct dt_node *occ_node;
occ_data = get_occ_pstate_table(chip);
occ_node = dt_new_addr(power_mgt, "occ", (uint64_t)occ_data);
if (!occ_node) {
/**
* @fwts-label OCCDTFailedNodeCreation
* @fwts-advice Failed to create
* /ibm,opal/power-mgt/occ. Per-chip pstate properties
* are not added to Device Tree.
*/
prerror("OCC: Failed to create /ibm,opal/power-mgt/occ@%llx\n",
(uint64_t)occ_data);
return false;
}
dt_add_property_cells(occ_node, "reg",
hi32((uint64_t)occ_data),
lo32((uint64_t)occ_data),
OPAL_DYNAMIC_DATA_OFFSET +
sizeof(struct occ_dynamic_data));
dt_add_property_cells(occ_node, "ibm,chip-id", chip->id);
/*
* Parse and add pstate Voltage Identifiers (VID) to DT which
* are provided by OCC in version 0x01 and 0x02
*/
parse_vid(occ_data, occ_node, nr_pstates, pmax, pmin);
}
out:
/* Return pstate to set for each core */
*pstate_nom = pnom;
return true;
}
/*
* Prepare chip for pstate transitions
*/
static bool cpu_pstates_prepare_core(struct proc_chip *chip,
struct cpu_thread *c,
int pstate_nom)
{
uint32_t core = pir_to_core_id(c->pir);
uint64_t tmp, pstate;
int rc;
/*
* Currently Fastsleep init clears EX_PM_SPR_OVERRIDE_EN.
* Need to ensure only relevant bits are inited
*/
/* Init PM GP1 for SCOM based PSTATE control to set nominal freq
*
* Use the OR SCOM to set the required bits in PM_GP1 register
* since the OCC might be mainpulating the PM_GP1 register as well.
*/
rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SET_GP1),
EX_PM_SETUP_GP1_PM_SPR_OVERRIDE_EN);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"OCC: Failed to write PM_GP1 in pstates init\n");
return false;
}
/* Set new pstate to core */
rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_PPMCR), &tmp);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"OCC: Failed to read PM_PPMCR from OCC in pstates init\n");
return false;
}
tmp = tmp & ~0xFFFF000000000000ULL;
pstate = ((uint64_t) pstate_nom) & 0xFF;
tmp = tmp | (pstate << 56) | (pstate << 48);
rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_PPMCR), tmp);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"OCC: Failed to write PM_PPMCR in pstates init\n");
return false;
}
time_wait_ms(1); /* Wait for PState to change */
/*
* Init PM GP1 for SPR based PSTATE control.
* Once OCC is active EX_PM_SETUP_GP1_DPLL_FREQ_OVERRIDE_EN will be
* cleared by OCC. Sapphire need not clear.
* However wait for DVFS state machine to become idle after min->nominal
* transition initiated above. If not switch over to SPR control could fail.
*
* Use the AND SCOM to clear the required bits in PM_GP1 register
* since the OCC might be mainpulating the PM_GP1 register as well.
*/
tmp = ~EX_PM_SETUP_GP1_PM_SPR_OVERRIDE_EN;
rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_CLEAR_GP1),
tmp);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"OCC: Failed to write PM_GP1 in pstates init\n");
return false;
}
/* Just debug */
rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_PPMSR), &tmp);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"OCC: Failed to read PM_PPMSR from OCC"
"in pstates init\n");
return false;
}
prlog(PR_DEBUG, "OCC: Chip %x Core %x PPMSR %016llx\n",
chip->id, core, tmp);
/*
* If PMSR is still in transition at this point due to PState change
* initiated above, then the switchover to SPR may not work.
* ToDo: Check for DVFS state machine idle before change.
*/
return true;
}
static bool occ_opal_msg_outstanding = false;
static void occ_msg_consumed(void *data __unused)
{
lock(&occ_lock);
occ_opal_msg_outstanding = false;
unlock(&occ_lock);
}
static inline u8 get_cpu_throttle(struct proc_chip *chip)
{
struct occ_pstate_table *pdata = get_occ_pstate_table(chip);
struct occ_dynamic_data *data;
switch (pdata->version >> 4) {
case 0:
return pdata->v2.throttle;
case 0x9:
data = get_occ_dynamic_data(chip);
return data->cpu_throttle;
default:
return 0;
};
}
static void occ_throttle_poll(void *data __unused)
{
struct proc_chip *chip;
struct occ_pstate_table *occ_data;
struct opal_occ_msg occ_msg;
int rc;
if (!try_lock(&occ_lock))
return;
if (occ_reset) {
int inactive = 0;
for_each_chip(chip) {
occ_data = get_occ_pstate_table(chip);
if (occ_data->valid != 1) {
inactive = 1;
break;
}
}
if (!inactive) {
/*
* Queue OCC_THROTTLE with throttle status as 0 to
* indicate all OCCs are active after a reset.
*/
occ_msg.type = cpu_to_be64(OCC_THROTTLE);
occ_msg.chip = 0;
occ_msg.throttle_status = 0;
rc = _opal_queue_msg(OPAL_MSG_OCC, NULL, NULL, 3,
(uint64_t *)&occ_msg);
if (!rc)
occ_reset = false;
}
} else {
if (occ_opal_msg_outstanding)
goto done;
for_each_chip(chip) {
u8 throttle;
occ_data = get_occ_pstate_table(chip);
throttle = get_cpu_throttle(chip);
if ((occ_data->valid == 1) &&
(chip->throttle != throttle) &&
(throttle <= OCC_MAX_THROTTLE_STATUS)) {
occ_msg.type = cpu_to_be64(OCC_THROTTLE);
occ_msg.chip = cpu_to_be64(chip->id);
occ_msg.throttle_status = cpu_to_be64(throttle);
rc = _opal_queue_msg(OPAL_MSG_OCC, NULL,
occ_msg_consumed,
3, (uint64_t *)&occ_msg);
if (!rc) {
chip->throttle = throttle;
occ_opal_msg_outstanding = true;
break;
}
}
}
}
done:
unlock(&occ_lock);
}
/* OPAL-OCC Command/Response Interface */
enum occ_state {
OCC_STATE_NOT_RUNNING = 0x00,
OCC_STATE_STANDBY = 0x01,
OCC_STATE_OBSERVATION = 0x02,
OCC_STATE_ACTIVE = 0x03,
OCC_STATE_SAFE = 0x04,
OCC_STATE_CHARACTERIZATION = 0x05,
};
enum occ_role {
OCC_ROLE_SLAVE = 0x0,
OCC_ROLE_MASTER = 0x1,
};
enum occ_cmd {
OCC_CMD_CLEAR_SENSOR_DATA,
OCC_CMD_SET_POWER_CAP,
OCC_CMD_SET_POWER_SHIFTING_RATIO,
OCC_CMD_SELECT_SENSOR_GROUP,
};
struct opal_occ_cmd_info {
enum occ_cmd cmd;
u8 cmd_value;
u16 cmd_size;
u16 rsp_size;
int timeout_ms;
u16 state_mask;
u8 role_mask;
};
static struct opal_occ_cmd_info occ_cmds[] = {
{ OCC_CMD_CLEAR_SENSOR_DATA,
0xD0, 4, 4, 1000,
PPC_BIT16(OCC_STATE_OBSERVATION) |
PPC_BIT16(OCC_STATE_ACTIVE) |
PPC_BIT16(OCC_STATE_CHARACTERIZATION),
PPC_BIT8(OCC_ROLE_MASTER) | PPC_BIT8(OCC_ROLE_SLAVE)
},
{ OCC_CMD_SET_POWER_CAP,
0xD1, 2, 2, 1000,
PPC_BIT16(OCC_STATE_OBSERVATION) |
PPC_BIT16(OCC_STATE_ACTIVE) |
PPC_BIT16(OCC_STATE_CHARACTERIZATION),
PPC_BIT8(OCC_ROLE_MASTER)
},
{ OCC_CMD_SET_POWER_SHIFTING_RATIO,
0xD2, 1, 1, 1000,
PPC_BIT16(OCC_STATE_OBSERVATION) |
PPC_BIT16(OCC_STATE_ACTIVE) |
PPC_BIT16(OCC_STATE_CHARACTERIZATION),
PPC_BIT8(OCC_ROLE_MASTER) | PPC_BIT8(OCC_ROLE_SLAVE)
},
{ OCC_CMD_SELECT_SENSOR_GROUP,
0xD3, 2, 2, 1000,
PPC_BIT16(OCC_STATE_OBSERVATION) |
PPC_BIT16(OCC_STATE_ACTIVE) |
PPC_BIT16(OCC_STATE_CHARACTERIZATION),
PPC_BIT8(OCC_ROLE_MASTER) | PPC_BIT8(OCC_ROLE_SLAVE)
},
};
enum occ_response_status {
OCC_RSP_SUCCESS = 0x00,
OCC_RSP_INVALID_COMMAND = 0x11,
OCC_RSP_INVALID_CMD_DATA_LENGTH = 0x12,
OCC_RSP_INVALID_DATA = 0x13,
OCC_RSP_INTERNAL_ERROR = 0x15,
};
#define OCC_FLAG_RSP_READY 0x01
#define OCC_FLAG_CMD_IN_PROGRESS 0x02
#define OPAL_FLAG_CMD_READY 0x80
struct opal_occ_cmd_data {
u8 *data;
enum occ_cmd cmd;
};
static struct cmd_interface {
struct lock queue_lock;
struct timer timeout;
struct opal_occ_cmd_data *cdata;
struct opal_command_buffer *cmd;
struct occ_response_buffer *rsp;
u8 *occ_state;
u8 *valid;
u32 chip_id;
u32 token;
u16 enabled_sensor_mask;
u8 occ_role;
u8 request_id;
bool cmd_in_progress;
bool retry;
} *chips;
static int nr_occs;
static inline struct cmd_interface *get_chip_cmd_interface(int chip_id)
{
int i;
for (i = 0; i < nr_occs; i++)
if (chips[i].chip_id == chip_id)
return &chips[i];
return NULL;
}
static inline bool occ_in_progress(struct cmd_interface *chip)
{
return (chip->rsp->flag == OCC_FLAG_CMD_IN_PROGRESS);
}
static int write_occ_cmd(struct cmd_interface *chip)
{
struct opal_command_buffer *cmd = chip->cmd;
enum occ_cmd ocmd = chip->cdata->cmd;
if (!chip->retry && occ_in_progress(chip)) {
chip->cmd_in_progress = false;
return OPAL_BUSY;
}
cmd->flag = chip->rsp->flag = 0;
cmd->cmd = occ_cmds[ocmd].cmd_value;
cmd->request_id = chip->request_id++;
cmd->data_size = occ_cmds[ocmd].cmd_size;
memcpy(&cmd->data, chip->cdata->data, cmd->data_size);
cmd->flag = OPAL_FLAG_CMD_READY;
schedule_timer(&chip->timeout,
msecs_to_tb(occ_cmds[ocmd].timeout_ms));
return OPAL_ASYNC_COMPLETION;
}
static int64_t opal_occ_command(struct cmd_interface *chip, int token,
struct opal_occ_cmd_data *cdata)
{
int rc;
if (!(*chip->valid) ||
(!(PPC_BIT16(*chip->occ_state) & occ_cmds[cdata->cmd].state_mask)))
return OPAL_HARDWARE;
if (!(PPC_BIT8(chip->occ_role) & occ_cmds[cdata->cmd].role_mask))
return OPAL_PERMISSION;
lock(&chip->queue_lock);
if (chip->cmd_in_progress) {
rc = OPAL_BUSY;
goto out;
}
chip->cdata = cdata;
chip->token = token;
chip->cmd_in_progress = true;
chip->retry = false;
rc = write_occ_cmd(chip);
out:
unlock(&chip->queue_lock);
return rc;
}
static inline bool sanity_check_opal_cmd(struct opal_command_buffer *cmd,
struct cmd_interface *chip)
{
return ((cmd->cmd == occ_cmds[chip->cdata->cmd].cmd_value) &&
(cmd->request_id == chip->request_id - 1) &&
(cmd->data_size == occ_cmds[chip->cdata->cmd].cmd_size));
}
static inline bool check_occ_rsp(struct opal_command_buffer *cmd,
struct occ_response_buffer *rsp)
{
if (cmd->cmd != rsp->cmd) {
prlog(PR_DEBUG, "OCC: Command value mismatch in OCC response"
"rsp->cmd = %d cmd->cmd = %d\n", rsp->cmd, cmd->cmd);
return false;
}
if (cmd->request_id != rsp->request_id) {
prlog(PR_DEBUG, "OCC: Request ID mismatch in OCC response"
"rsp->request_id = %d cmd->request_id = %d\n",
rsp->request_id, cmd->request_id);
return false;
}
return true;
}
static inline void queue_occ_rsp_msg(int token, int rc)
{
int ret;
ret = opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, token, rc);
if (ret)
prerror("OCC: Failed to queue OCC response status message\n");
}
static void occ_cmd_timeout_handler(struct timer *t __unused, void *data,
uint64_t now __unused)
{
struct cmd_interface *chip = data;
lock(&chip->queue_lock);
if (!chip->cmd_in_progress)
goto exit;
if (!chip->retry) {
prlog(PR_DEBUG, "OCC: Command timeout, retrying\n");
chip->retry = true;
write_occ_cmd(chip);
} else {
chip->cmd_in_progress = false;
queue_occ_rsp_msg(chip->token, OPAL_TIMEOUT);
prlog(PR_DEBUG, "OCC: Command timeout after retry\n");
}
exit:
unlock(&chip->queue_lock);
}
static int read_occ_rsp(struct occ_response_buffer *rsp)
{
switch (rsp->status) {
case OCC_RSP_SUCCESS:
return OPAL_SUCCESS;
case OCC_RSP_INVALID_COMMAND:
prlog(PR_DEBUG, "OCC: Rsp status: Invalid command\n");
break;
case OCC_RSP_INVALID_CMD_DATA_LENGTH:
prlog(PR_DEBUG, "OCC: Rsp status: Invalid command data length\n");
break;
case OCC_RSP_INVALID_DATA:
prlog(PR_DEBUG, "OCC: Rsp status: Invalid command data\n");
break;
case OCC_RSP_INTERNAL_ERROR:
prlog(PR_DEBUG, "OCC: Rsp status: OCC internal error\n");
break;
default:
break;
}
/* Clear the OCC response flag */
rsp->flag = 0;
return OPAL_INTERNAL_ERROR;
}
static void handle_occ_rsp(uint32_t chip_id)
{
struct cmd_interface *chip;
struct opal_command_buffer *cmd;
struct occ_response_buffer *rsp;
chip = get_chip_cmd_interface(chip_id);
if (!chip)
return;
cmd = chip->cmd;
rsp = chip->rsp;
/*Read rsp*/
if (rsp->flag != OCC_FLAG_RSP_READY)
return;
lock(&chip->queue_lock);
if (!chip->cmd_in_progress)
goto exit;
cancel_timer(&chip->timeout);
if (!sanity_check_opal_cmd(cmd, chip) ||
!check_occ_rsp(cmd, rsp)) {
if (!chip->retry) {
prlog(PR_DEBUG, "OCC: Command-response mismatch, retrying\n");
chip->retry = true;
write_occ_cmd(chip);
} else {
chip->cmd_in_progress = false;
queue_occ_rsp_msg(chip->token, OPAL_INTERNAL_ERROR);
prlog(PR_DEBUG, "OCC: Command-response mismatch\n");
}
goto exit;
}
if (rsp->cmd == occ_cmds[OCC_CMD_SELECT_SENSOR_GROUP].cmd_value &&
rsp->status == OCC_RSP_SUCCESS)
chip->enabled_sensor_mask = *(u16 *)chip->cdata->data;
chip->cmd_in_progress = false;
queue_occ_rsp_msg(chip->token, read_occ_rsp(chip->rsp));
exit:
unlock(&chip->queue_lock);
}
bool occ_get_gpu_presence(struct proc_chip *chip, int gpu_num)
{
struct occ_dynamic_data *ddata;
static int max_retries = 20;
static bool found = false;
assert(gpu_num <= 2);
ddata = get_occ_dynamic_data(chip);
while (!found && max_retries) {
if (ddata->major_version == 0 && ddata->minor_version >= 1) {
found = true;
break;
}
time_wait_ms(100);
max_retries--;
ddata = get_occ_dynamic_data(chip);
}
if (!found) {
prlog(PR_INFO, "OCC: No GPU slot presence, assuming GPU present\n");
return true;
}
return (bool)(ddata->gpus_present & 1 << gpu_num);
}
static void occ_add_powercap_sensors(struct dt_node *power_mgt);
static void occ_add_psr_sensors(struct dt_node *power_mgt);
static void occ_cmd_interface_init(void)
{
struct occ_dynamic_data *data;
struct occ_pstate_table *pdata;
struct dt_node *power_mgt;
struct proc_chip *chip;
int i = 0;
/* Check if the OCC data is valid */
for_each_chip(chip) {
pdata = get_occ_pstate_table(chip);
if (!pdata->valid)
return;
}
chip = next_chip(NULL);
pdata = get_occ_pstate_table(chip);
if ((pdata->version >> 4) != 0x9)
return;
for_each_chip(chip)
nr_occs++;
chips = malloc(sizeof(*chips) * nr_occs);
assert(chips);
for_each_chip(chip) {
pdata = get_occ_pstate_table(chip);
data = get_occ_dynamic_data(chip);
chips[i].chip_id = chip->id;
chips[i].occ_role = pdata->v9.occ_role;
chips[i].occ_state = &data->occ_state;
chips[i].valid = &pdata->valid;
chips[i].cmd = &data->cmd;
chips[i].rsp = &data->rsp;
init_lock(&chips[i].queue_lock);
chips[i].cmd_in_progress = false;
chips[i].request_id = 0;
chips[i].enabled_sensor_mask = OCC_ENABLED_SENSOR_MASK;
init_timer(&chips[i].timeout, occ_cmd_timeout_handler,
&chips[i]);
i++;
}
power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt");
if (!power_mgt) {
prerror("OCC: dt node /ibm,opal/power-mgt not found\n");
return;
}
/* Add powercap sensors to DT */
occ_add_powercap_sensors(power_mgt);
/* Add power-shifting-ratio CPU-GPU sensors to DT */
occ_add_psr_sensors(power_mgt);
}
/* Powercap interface */
enum sensor_powercap_occ_attr {
POWERCAP_OCC_SOFT_MIN,
POWERCAP_OCC_MAX,
POWERCAP_OCC_CUR,
POWERCAP_OCC_HARD_MIN,
};
static void occ_add_powercap_sensors(struct dt_node *power_mgt)
{
struct dt_node *pcap, *node;
u32 handle;
pcap = dt_new(power_mgt, "powercap");
if (!pcap) {
prerror("OCC: Failed to create powercap node\n");
return;
}
dt_add_property_string(pcap, "compatible", "ibm,opal-powercap");
node = dt_new(pcap, "system-powercap");
if (!node) {
prerror("OCC: Failed to create system powercap node\n");
return;
}
handle = powercap_make_handle(POWERCAP_CLASS_OCC, POWERCAP_OCC_CUR);
dt_add_property_cells(node, "powercap-current", handle);
handle = powercap_make_handle(POWERCAP_CLASS_OCC,
POWERCAP_OCC_SOFT_MIN);
dt_add_property_cells(node, "powercap-min", handle);
handle = powercap_make_handle(POWERCAP_CLASS_OCC, POWERCAP_OCC_MAX);
dt_add_property_cells(node, "powercap-max", handle);
handle = powercap_make_handle(POWERCAP_CLASS_OCC,
POWERCAP_OCC_HARD_MIN);
dt_add_property_cells(node, "powercap-hard-min", handle);
}
int occ_get_powercap(u32 handle, u32 *pcap)
{
struct occ_pstate_table *pdata;
struct occ_dynamic_data *ddata;
struct proc_chip *chip;
chip = next_chip(NULL);
pdata = get_occ_pstate_table(chip);
ddata = get_occ_dynamic_data(chip);
if (!pdata->valid)
return OPAL_HARDWARE;
switch (powercap_get_attr(handle)) {
case POWERCAP_OCC_SOFT_MIN:
*pcap = ddata->soft_min_pwr_cap;
break;
case POWERCAP_OCC_MAX:
*pcap = ddata->max_pwr_cap;
break;
case POWERCAP_OCC_CUR:
*pcap = ddata->cur_pwr_cap;
break;
case POWERCAP_OCC_HARD_MIN:
*pcap = ddata->hard_min_pwr_cap;
break;
default:
*pcap = 0;
return OPAL_UNSUPPORTED;
}
return OPAL_SUCCESS;
}
static u16 pcap_cdata;
static struct opal_occ_cmd_data pcap_data = {
.data = (u8 *)&pcap_cdata,
.cmd = OCC_CMD_SET_POWER_CAP,
};
int occ_set_powercap(u32 handle, int token, u32 pcap)
{
struct occ_dynamic_data *ddata;
struct proc_chip *chip;
int i;
if (powercap_get_attr(handle) != POWERCAP_OCC_CUR)
return OPAL_PERMISSION;
if (!chips)
return OPAL_HARDWARE;
for (i = 0; i < nr_occs; i++)
if (chips[i].occ_role == OCC_ROLE_MASTER)
break;
if (!(*chips[i].valid))
return OPAL_HARDWARE;
chip = get_chip(chips[i].chip_id);
ddata = get_occ_dynamic_data(chip);
if (pcap == ddata->cur_pwr_cap)
return OPAL_SUCCESS;
if (pcap && (pcap > ddata->max_pwr_cap ||
pcap < ddata->soft_min_pwr_cap))
return OPAL_PARAMETER;
pcap_cdata = pcap;
return opal_occ_command(&chips[i], token, &pcap_data);
};
/* Power-Shifting Ratio */
enum psr_type {
PSR_TYPE_CPU_TO_GPU, /* 0% Cap GPU first, 100% Cap CPU first */
};
int occ_get_psr(u32 handle, u32 *ratio)
{
struct occ_dynamic_data *ddata;
struct proc_chip *chip;
u8 i = psr_get_rid(handle);
if (psr_get_type(handle) != PSR_TYPE_CPU_TO_GPU)
return OPAL_UNSUPPORTED;
if (i > nr_occs)
return OPAL_UNSUPPORTED;
if (!(*chips[i].valid))
return OPAL_HARDWARE;
chip = get_chip(chips[i].chip_id);
ddata = get_occ_dynamic_data(chip);
*ratio = ddata->pwr_shifting_ratio;
return OPAL_SUCCESS;
}
static u8 psr_cdata;
static struct opal_occ_cmd_data psr_data = {
.data = &psr_cdata,
.cmd = OCC_CMD_SET_POWER_SHIFTING_RATIO,
};
int occ_set_psr(u32 handle, int token, u32 ratio)
{
struct occ_dynamic_data *ddata;
struct proc_chip *chip;
u8 i = psr_get_rid(handle);
if (psr_get_type(handle) != PSR_TYPE_CPU_TO_GPU)
return OPAL_UNSUPPORTED;
if (ratio > 100)
return OPAL_PARAMETER;
if (i > nr_occs)
return OPAL_UNSUPPORTED;
if (!(*chips[i].valid))
return OPAL_HARDWARE;
chip = get_chip(chips[i].chip_id);
ddata = get_occ_dynamic_data(chip);
if (ratio == ddata->pwr_shifting_ratio)
return OPAL_SUCCESS;
psr_cdata = ratio;
return opal_occ_command(&chips[i], token, &psr_data);
}
static void occ_add_psr_sensors(struct dt_node *power_mgt)
{
struct dt_node *node;
int i;
node = dt_new(power_mgt, "psr");
if (!node) {
prerror("OCC: Failed to create power-shifting-ratio node\n");
return;
}
dt_add_property_string(node, "compatible",
"ibm,opal-power-shift-ratio");
dt_add_property_cells(node, "#address-cells", 1);
dt_add_property_cells(node, "#size-cells", 0);
for (i = 0; i < nr_occs; i++) {
struct dt_node *cnode;
char name[20];
u32 handle = psr_make_handle(PSR_CLASS_OCC, i,
PSR_TYPE_CPU_TO_GPU);
cnode = dt_new_addr(node, "cpu-to-gpu", handle);
if (!cnode) {
prerror("OCC: Failed to create power-shifting-ratio node\n");
return;
}
snprintf(name, 20, "cpu_to_gpu_%d", chips[i].chip_id);
dt_add_property_string(cnode, "label", name);
dt_add_property_cells(cnode, "handle", handle);
dt_add_property_cells(cnode, "reg", chips[i].chip_id);
}
}
/* OCC clear sensor limits CSM/Profiler/Job-scheduler */
enum occ_sensor_limit_group {
OCC_SENSOR_LIMIT_GROUP_CSM = 0x10,
OCC_SENSOR_LIMIT_GROUP_PROFILER = 0x20,
OCC_SENSOR_LIMIT_GROUP_JOB_SCHED = 0x40,
};
static u32 sensor_limit;
static struct opal_occ_cmd_data slimit_data = {
.data = (u8 *)&sensor_limit,
.cmd = OCC_CMD_CLEAR_SENSOR_DATA,
};
int occ_sensor_group_clear(u32 group_hndl, int token)
{
u32 limit = sensor_get_rid(group_hndl);
u8 i = sensor_get_attr(group_hndl);
if (i > nr_occs)
return OPAL_UNSUPPORTED;
switch (limit) {
case OCC_SENSOR_LIMIT_GROUP_CSM:
case OCC_SENSOR_LIMIT_GROUP_PROFILER:
case OCC_SENSOR_LIMIT_GROUP_JOB_SCHED:
break;
default:
return OPAL_UNSUPPORTED;
}
if (!(*chips[i].valid))
return OPAL_HARDWARE;
sensor_limit = limit << 24;
return opal_occ_command(&chips[i], token, &slimit_data);
}
static u16 sensor_enable;
static struct opal_occ_cmd_data sensor_mask_data = {
.data = (u8 *)&sensor_enable,
.cmd = OCC_CMD_SELECT_SENSOR_GROUP,
};
int occ_sensor_group_enable(u32 group_hndl, int token, bool enable)
{
u16 type = sensor_get_rid(group_hndl);
u8 i = sensor_get_attr(group_hndl);
if (i > nr_occs)
return OPAL_UNSUPPORTED;
switch (type) {
case OCC_SENSOR_TYPE_GENERIC:
case OCC_SENSOR_TYPE_CURRENT:
case OCC_SENSOR_TYPE_VOLTAGE:
case OCC_SENSOR_TYPE_TEMPERATURE:
case OCC_SENSOR_TYPE_UTILIZATION:
case OCC_SENSOR_TYPE_TIME:
case OCC_SENSOR_TYPE_FREQUENCY:
case OCC_SENSOR_TYPE_POWER:
case OCC_SENSOR_TYPE_PERFORMANCE:
break;
default:
return OPAL_UNSUPPORTED;
}
if (!(*chips[i].valid))
return OPAL_HARDWARE;
if (enable && (type & chips[i].enabled_sensor_mask))
return OPAL_SUCCESS;
else if (!enable && !(type & chips[i].enabled_sensor_mask))
return OPAL_SUCCESS;
sensor_enable = enable ? type | chips[i].enabled_sensor_mask :
~type & chips[i].enabled_sensor_mask;
return opal_occ_command(&chips[i], token, &sensor_mask_data);
}
void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, u32 *ptype,
int nr_phandles, int chipid)
{
struct group_info {
int type;
const char *str;
u32 ops;
} groups[] = {
{ OCC_SENSOR_LIMIT_GROUP_CSM, "csm",
OPAL_SENSOR_GROUP_CLEAR
},
{ OCC_SENSOR_LIMIT_GROUP_PROFILER, "profiler",
OPAL_SENSOR_GROUP_CLEAR
},
{ OCC_SENSOR_LIMIT_GROUP_JOB_SCHED, "js",
OPAL_SENSOR_GROUP_CLEAR
},
{ OCC_SENSOR_TYPE_GENERIC, "generic",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_CURRENT, "curr",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_VOLTAGE, "in",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_TEMPERATURE, "temp",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_UTILIZATION, "utilization",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_TIME, "time",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_FREQUENCY, "frequency",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_POWER, "power",
OPAL_SENSOR_GROUP_ENABLE
},
{ OCC_SENSOR_TYPE_PERFORMANCE, "performance",
OPAL_SENSOR_GROUP_ENABLE
},
};
int i, j;
/*
* Dont add sensor groups if cmd-interface is not intialized
*/
if (!chips)
return;
for (i = 0; i < nr_occs; i++)
if (chips[i].chip_id == chipid)
break;
for (j = 0; j < ARRAY_SIZE(groups); j++) {
struct dt_node *node;
char name[20];
u32 handle;
snprintf(name, 20, "occ-%s", groups[j].str);
handle = sensor_make_handler(SENSOR_OCC, 0,
groups[j].type, i);
node = dt_new_addr(sg, name, handle);
if (!node) {
prerror("Failed to create sensor group nodes\n");
return;
}
dt_add_property_cells(node, "sensor-group-id", handle);
dt_add_property_string(node, "type", groups[j].str);
if (groups[j].type == OCC_SENSOR_TYPE_CURRENT ||
groups[j].type == OCC_SENSOR_TYPE_VOLTAGE ||
groups[j].type == OCC_SENSOR_TYPE_TEMPERATURE ||
groups[j].type == OCC_SENSOR_TYPE_POWER) {
dt_add_property_string(node, "sensor-type",
groups[j].str);
dt_add_property_string(node, "compatible",
"ibm,opal-sensor");
}
dt_add_property_cells(node, "ibm,chip-id", chipid);
dt_add_property_cells(node, "reg", handle);
if (groups[j].ops == OPAL_SENSOR_GROUP_ENABLE) {
u32 *_phandles;
int k, pcount = 0;
_phandles = malloc(sizeof(u32) * nr_phandles);
assert(_phandles);
for (k = 0; k < nr_phandles; k++)
if (ptype[k] == groups[j].type)
_phandles[pcount++] = phandles[k];
if (pcount)
dt_add_property(node, "sensors", _phandles,
pcount * sizeof(u32));
free(_phandles);
} else {
dt_add_property(node, "sensors", phandles,
nr_phandles * sizeof(u32));
}
dt_add_property_cells(node, "ops", groups[j].ops);
}
}
/* CPU-OCC PState init */
/* Called after OCC init on P8 and P9 */
void occ_pstates_init(void)
{
struct proc_chip *chip;
struct cpu_thread *c;
int pstate_nom;
static bool occ_pstates_initialized;
/* OCC is supported in P8 and P9 */
if (proc_gen < proc_gen_p8)
return;
/* Handle fast reboots */
if (occ_pstates_initialized) {
struct dt_node *power_mgt, *child;
int i;
const char *props[] = {
"ibm,pstate-core-max",
"ibm,pstate-frequencies-mhz",
"ibm,pstate-ids",
"ibm,pstate-max",
"ibm,pstate-min",
"ibm,pstate-nominal",
"ibm,pstate-turbo",
"ibm,pstate-ultra-turbo",
"#address-cells",
"#size-cells",
};
power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt");
if (power_mgt) {
for (i = 0; i < ARRAY_SIZE(props); i++)
dt_check_del_prop(power_mgt, props[i]);
dt_for_each_child(power_mgt, child)
if (!strncmp(child->name, "occ", 3))
dt_free(child);
}
}
switch (proc_gen) {
case proc_gen_p8:
homer_opal_data_offset = P8_HOMER_OPAL_DATA_OFFSET;
break;
case proc_gen_p9:
homer_opal_data_offset = P9_HOMER_OPAL_DATA_OFFSET;
break;
default:
return;
}
chip = next_chip(NULL);
if (!chip->homer_base) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"OCC: No HOMER detected, assuming no pstates\n");
return;
}
/* Wait for all OCC to boot up */
if(!wait_for_all_occ_init()) {
log_simple_error(&e_info(OPAL_RC_OCC_TIMEOUT),
"OCC: Initialization on all chips did not complete"
"(timed out)\n");
return;
}
/*
* Check boundary conditions and add device tree nodes
* and return nominal pstate to set for the core
*/
if (!add_cpu_pstate_properties(&pstate_nom)) {
log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),
"Skiping core cpufreq init due to OCC error\n");
} else if (proc_gen == proc_gen_p8) {
/*
* Setup host based pstates and set nominal frequency only in
* P8.
*/
for_each_chip(chip)
for_each_available_core_in_chip(c, chip->id)
cpu_pstates_prepare_core(chip, c, pstate_nom);
}
if (occ_pstates_initialized)
return;
/* Add opal_poller to poll OCC throttle status of each chip */
for_each_chip(chip)
chip->throttle = 0;
opal_add_poller(occ_throttle_poll, NULL);
occ_pstates_initialized = true;
/* Init OPAL-OCC command-response interface */
occ_cmd_interface_init();
}
struct occ_load_req {
u8 scope;
u32 dbob_id;
u32 seq_id;
struct list_node link;
};
static LIST_HEAD(occ_load_req_list);
int find_master_and_slave_occ(uint64_t **master, uint64_t **slave,
int *nr_masters, int *nr_slaves)
{
struct proc_chip *chip;
int nr_chips = 0, i;
uint64_t chipids[MAX_CHIPS];
for_each_chip(chip) {
chipids[nr_chips++] = chip->id;
}
chip = next_chip(NULL);
/*
* Proc0 is the master OCC for Tuleta/Alpine boxes.
* Hostboot expects the pair of chips for MURANO, so pass the sibling
* chip id along with proc0 to hostboot.
*/
*nr_masters = (chip->type == PROC_CHIP_P8_MURANO) ? 2 : 1;
*master = (uint64_t *)malloc(*nr_masters * sizeof(uint64_t));
if (!*master) {
printf("OCC: master array alloc failure\n");
return -ENOMEM;
}
if (nr_chips - *nr_masters > 0) {
*nr_slaves = nr_chips - *nr_masters;
*slave = (uint64_t *)malloc(*nr_slaves * sizeof(uint64_t));
if (!*slave) {
printf("OCC: slave array alloc failure\n");
return -ENOMEM;
}
}
for (i = 0; i < nr_chips; i++) {
if (i < *nr_masters) {
*(*master + i) = chipids[i];
continue;
}
*(*slave + i - *nr_masters) = chipids[i];
}
return 0;
}
static void occ_queue_load(u8 scope, u32 dbob_id, u32 seq_id)
{
struct occ_load_req *occ_req;
occ_req = zalloc(sizeof(struct occ_load_req));
if (!occ_req) {
/**
* @fwts-label OCCload_reqENOMEM
* @fwts-advice ENOMEM while allocating OCC load message.
* OCCs not started, consequently no power/frequency scaling
* will be functional.
*/
prlog(PR_ERR, "OCC: Could not allocate occ_load_req\n");
return;
}
occ_req->scope = scope;
occ_req->dbob_id = dbob_id;
occ_req->seq_id = seq_id;
list_add_tail(&occ_load_req_list, &occ_req->link);
}
static void __occ_do_load(u8 scope, u32 dbob_id __unused, u32 seq_id)
{
struct fsp_msg *stat;
int rc = -ENOMEM;
int status_word = 0;
struct proc_chip *chip = next_chip(NULL);
/* Call HBRT... */
rc = host_services_occ_load();
/* Handle fallback to preload */
if (rc == -ENOENT && chip->homer_base) {
prlog(PR_INFO, "OCC: Load: Fallback to preloaded image\n");
rc = 0;
} else if (!rc) {
struct opal_occ_msg occ_msg = { CPU_TO_BE64(OCC_LOAD), 0, 0 };
rc = _opal_queue_msg(OPAL_MSG_OCC, NULL, NULL, 3,
(uint64_t *)&occ_msg);
if (rc)
prlog(PR_INFO, "OCC: Failed to queue message %d\n",
OCC_LOAD);
/* Success, start OCC */
rc = host_services_occ_start();
}
if (rc) {
/* If either of hostservices call fail, send fail to FSP */
/* Find a chip ID to send failure */
for_each_chip(chip) {
if (scope == 0x01 && dbob_id != chip->dbob_id)
continue;
status_word = 0xB500 | (chip->pcid & 0xff);
break;
}
log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
"OCC: Error %d in load/start OCC\n", rc);
}
/* Send a single response for all chips */
stat = fsp_mkmsg(FSP_CMD_LOAD_OCC_STAT, 2, status_word, seq_id);
if (stat)
rc = fsp_queue_msg(stat, fsp_freemsg);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
"OCC: Error %d queueing FSP OCC LOAD STATUS msg", rc);
fsp_freemsg(stat);
}
}
void occ_poke_load_queue(void)
{
struct occ_load_req *occ_req, *next;
if (list_empty(&occ_load_req_list))
return;
list_for_each_safe(&occ_load_req_list, occ_req, next, link) {
__occ_do_load(occ_req->scope, occ_req->dbob_id,
occ_req->seq_id);
list_del(&occ_req->link);
free(occ_req);
}
}
static u32 last_seq_id;
static bool in_ipl = true;
static void occ_do_load(u8 scope, u32 dbob_id __unused, u32 seq_id)
{
struct fsp_msg *rsp;
int rc = -ENOMEM;
u8 err = 0;
if (scope != 0x01 && scope != 0x02) {
/**
* @fwts-label OCCLoadInvalidScope
* @fwts-advice Invalid request for loading OCCs. Power and
* frequency management not functional
*/
prlog(PR_ERR, "OCC: Load message with invalid scope 0x%x\n",
scope);
err = 0x22;
}
/* First queue up an OK response to the load message itself */
rsp = fsp_mkmsg(FSP_RSP_LOAD_OCC | err, 0);
if (rsp)
rc = fsp_queue_msg(rsp, fsp_freemsg);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
"OCC: Error %d queueing FSP OCC LOAD reply\n", rc);
fsp_freemsg(rsp);
return;
}
if (err)
return;
if (proc_gen == proc_gen_p9) {
if (in_ipl) {
/* OCC is pre-loaded in P9, so send SUCCESS to FSP */
rsp = fsp_mkmsg(FSP_CMD_LOAD_OCC_STAT, 2, 0, seq_id);
if (!rsp)
return;
rc = fsp_queue_msg(rsp, fsp_freemsg);
if (rc) {
log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
"OCC: Error %d queueing OCC LOAD STATUS msg",
rc);
fsp_freemsg(rsp);
}
in_ipl = false;
} else {
struct proc_chip *chip = next_chip(NULL);
last_seq_id = seq_id;
prd_fsp_occ_load_start(chip->id);
}
return;
}
/*
* Check if hostservices lid caching is complete. If not, queue
* the load request.
*/
if (!hservices_lid_preload_complete()) {
occ_queue_load(scope, dbob_id, seq_id);
return;
}
__occ_do_load(scope, dbob_id, seq_id);
}
int occ_msg_queue_occ_reset(void)
{
struct opal_occ_msg occ_msg = { OCC_RESET, 0, 0 };
struct proc_chip *chip;
int rc;
lock(&occ_lock);
rc = _opal_queue_msg(OPAL_MSG_OCC, NULL, NULL, 3,
(uint64_t *)&occ_msg);
if (rc) {
prlog(PR_INFO, "OCC: Failed to queue OCC_RESET message\n");
goto out;
}
/*
* Set 'valid' byte of occ_pstate_table to 0 since OCC
* may not clear this byte on a reset.
* OCC will set the 'valid' byte to 1 when it becomes
* active again.
*/
for_each_chip(chip) {
struct occ_pstate_table *occ_data;
occ_data = get_occ_pstate_table(chip);
occ_data->valid = 0;
chip->throttle = 0;
}
occ_reset = true;
out:
unlock(&occ_lock);
return rc;
}
int fsp_occ_reset_status(u64 chipid, s64 status)
{
struct fsp_msg *stat;
int rc = OPAL_NO_MEM;
int status_word = 0;
prlog(PR_INFO, "HBRT: OCC stop() completed with %lld\n", status);
if (status) {
struct proc_chip *chip = get_chip(chipid);
if (!chip)
return OPAL_PARAMETER;
status_word = 0xfe00 | (chip->pcid & 0xff);
log_simple_error(&e_info(OPAL_RC_OCC_RESET),
"OCC: Error %lld in OCC reset of chip %lld\n",
status, chipid);
} else {
occ_msg_queue_occ_reset();
}
stat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2, status_word, last_seq_id);
if (!stat)
return rc;
rc = fsp_queue_msg(stat, fsp_freemsg);
if (rc) {
fsp_freemsg(stat);
log_simple_error(&e_info(OPAL_RC_OCC_RESET),
"OCC: Error %d queueing FSP OCC RESET STATUS message\n",
rc);
}
return rc;
}
int fsp_occ_load_start_status(u64 chipid, s64 status)
{
struct fsp_msg *stat;
int rc = OPAL_NO_MEM;
int status_word = 0;
if (status) {
struct proc_chip *chip = get_chip(chipid);
if (!chip)
return OPAL_PARAMETER;
status_word = 0xB500 | (chip->pcid & 0xff);
log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
"OCC: Error %d in load/start OCC %lld\n", rc,
chipid);
}
stat = fsp_mkmsg(FSP_CMD_LOAD_OCC_STAT, 2, status_word, last_seq_id);
if (!stat)
return rc;
rc = fsp_queue_msg(stat, fsp_freemsg);
if (rc) {
fsp_freemsg(stat);
log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
"OCC: Error %d queueing FSP OCC LOAD STATUS msg", rc);
}
return rc;
}
static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id)
{
struct fsp_msg *rsp, *stat;
struct proc_chip *chip = next_chip(NULL);
int rc = -ENOMEM;
u8 err = 0;
/* Check arguments */
if (scope != 0x01 && scope != 0x02) {
/**
* @fwts-label OCCResetInvalidScope
* @fwts-advice Invalid request for resetting OCCs. Power and
* frequency management not functional
*/
prlog(PR_ERR, "OCC: Reset message with invalid scope 0x%x\n",
scope);
err = 0x22;
}
/* First queue up an OK response to the reset message itself */
rsp = fsp_mkmsg(FSP_RSP_RESET_OCC | err, 0);
if (rsp)
rc = fsp_queue_msg(rsp, fsp_freemsg);
if (rc) {
fsp_freemsg(rsp);
log_simple_error(&e_info(OPAL_RC_OCC_RESET),
"OCC: Error %d queueing FSP OCC RESET reply\n", rc);
return;
}
/* If we had an error, return */
if (err)
return;
/*
* Call HBRT to stop OCC and leave it stopped. FSP will send load/start
* request subsequently. Also after few runtime restarts (currently 3),
* FSP will request OCC to left in stopped state.
*/
switch (proc_gen) {
case proc_gen_p8:
rc = host_services_occ_stop();
break;
case proc_gen_p9:
last_seq_id = seq_id;
chip = next_chip(NULL);
prd_fsp_occ_reset(chip->id);
return;
default:
return;
}
/* Handle fallback to preload */
if (rc == -ENOENT && chip->homer_base) {
prlog(PR_INFO, "OCC: Reset: Fallback to preloaded image\n");
rc = 0;
}
if (!rc) {
/* Send a single success response for all chips */
stat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2, 0, seq_id);
if (stat)
rc = fsp_queue_msg(stat, fsp_freemsg);
if (rc) {
fsp_freemsg(stat);
log_simple_error(&e_info(OPAL_RC_OCC_RESET),
"OCC: Error %d queueing FSP OCC RESET"
" STATUS message\n", rc);
}
occ_msg_queue_occ_reset();
} else {
/*
* Then send a matching OCC Reset Status message with an 0xFE
* (fail) response code as well to the first matching chip
*/
for_each_chip(chip) {
if (scope == 0x01 && dbob_id != chip->dbob_id)
continue;
rc = -ENOMEM;
stat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2,
0xfe00 | (chip->pcid & 0xff), seq_id);
if (stat)
rc = fsp_queue_msg(stat, fsp_freemsg);
if (rc) {
fsp_freemsg(stat);
log_simple_error(&e_info(OPAL_RC_OCC_RESET),
"OCC: Error %d queueing FSP OCC RESET"
" STATUS message\n", rc);
}
break;
}
}
}
#define PV_OCC_GP0 0x01000000
#define PV_OCC_GP0_AND 0x01000004
#define PV_OCC_GP0_OR 0x01000005
#define PV_OCC_GP0_PNOR_OWNER PPC_BIT(18) /* 1 = OCC / Host, 0 = BMC */
static void occ_pnor_set_one_owner(uint32_t chip_id, enum pnor_owner owner)
{
uint64_t reg, mask;
if (owner == PNOR_OWNER_HOST) {
reg = PV_OCC_GP0_OR;
mask = PV_OCC_GP0_PNOR_OWNER;
} else {
reg = PV_OCC_GP0_AND;
mask = ~PV_OCC_GP0_PNOR_OWNER;
}
xscom_write(chip_id, reg, mask);
}
void occ_pnor_set_owner(enum pnor_owner owner)
{
struct proc_chip *chip;
for_each_chip(chip)
occ_pnor_set_one_owner(chip->id, owner);
}
static bool fsp_occ_msg(u32 cmd_sub_mod, struct fsp_msg *msg)
{
u32 dbob_id, seq_id;
u8 scope;
switch (cmd_sub_mod) {
case FSP_CMD_LOAD_OCC:
/*
* We get the "Load OCC" command at boot. We don't currently
* support loading it ourselves (we don't have the procedures,
* they will come with Host Services). For now HostBoot will
* have loaded a OCC firmware for us, but we still need to
* be nice and respond to OCC.
*/
scope = msg->data.bytes[3];
dbob_id = msg->data.words[1];
seq_id = msg->data.words[2];
prlog(PR_INFO, "OCC: Got OCC Load message, scope=0x%x"
" dbob=0x%x seq=0x%x\n", scope, dbob_id, seq_id);
occ_do_load(scope, dbob_id, seq_id);
return true;
case FSP_CMD_RESET_OCC:
/*
* We shouldn't be getting this one, but if we do, we have
* to reply something sensible or the FSP will get upset
*/
scope = msg->data.bytes[3];
dbob_id = msg->data.words[1];
seq_id = msg->data.words[2];
prlog(PR_INFO, "OCC: Got OCC Reset message, scope=0x%x"
" dbob=0x%x seq=0x%x\n", scope, dbob_id, seq_id);
occ_do_reset(scope, dbob_id, seq_id);
return true;
}
return false;
}
static struct fsp_client fsp_occ_client = {
.message = fsp_occ_msg,
};
#define P8_OCB_OCI_OCCMISC 0x6a020
#define P8_OCB_OCI_OCCMISC_AND 0x6a021
#define P8_OCB_OCI_OCCMISC_OR 0x6a022
#define P9_OCB_OCI_OCCMISC 0x6c080
#define P9_OCB_OCI_OCCMISC_CLEAR 0x6c081
#define P9_OCB_OCI_OCCMISC_OR 0x6c082
#define OCB_OCI_OCIMISC_IRQ PPC_BIT(0)
#define OCB_OCI_OCIMISC_IRQ_TMGT PPC_BIT(1)
#define OCB_OCI_OCIMISC_IRQ_SLW_TMR PPC_BIT(14)
#define OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY PPC_BIT(15)
#define P8_OCB_OCI_OCIMISC_MASK (OCB_OCI_OCIMISC_IRQ_TMGT | \
OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY | \
OCB_OCI_OCIMISC_IRQ_SLW_TMR)
#define OCB_OCI_OCIMISC_IRQ_I2C PPC_BIT(2)
#define OCB_OCI_OCIMISC_IRQ_SHMEM PPC_BIT(3)
#define P9_OCB_OCI_OCIMISC_MASK (OCB_OCI_OCIMISC_IRQ_TMGT | \
OCB_OCI_OCIMISC_IRQ_I2C | \
OCB_OCI_OCIMISC_IRQ_SHMEM | \
OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY)
void occ_send_dummy_interrupt(void)
{
struct psi *psi;
struct proc_chip *chip = get_chip(this_cpu()->chip_id);
/* Emulators and P7 doesn't do this */
if (proc_gen < proc_gen_p8 || chip_quirk(QUIRK_NO_OCC_IRQ))
return;
/* Find a functional PSI. This ensures an interrupt even if
* the psihb on the current chip is not configured */
if (chip->psi)
psi = chip->psi;
else
psi = psi_find_functional_chip();
if (!psi) {
prlog_once(PR_WARNING, "PSI: no functional PSI HB found, "
"no self interrupts delivered\n");
return;
}
switch (proc_gen) {
case proc_gen_p8:
xscom_write(psi->chip_id, P8_OCB_OCI_OCCMISC_OR,
OCB_OCI_OCIMISC_IRQ |
OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY);
break;
case proc_gen_p9:
xscom_write(psi->chip_id, P9_OCB_OCI_OCCMISC_OR,
OCB_OCI_OCIMISC_IRQ |
OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY);
break;
default:
break;
}
}
void occ_p8_interrupt(uint32_t chip_id)
{
uint64_t ireg;
int64_t rc;
/* The OCC interrupt is used to mux up to 15 different sources */
rc = xscom_read(chip_id, P8_OCB_OCI_OCCMISC, &ireg);
if (rc) {
prerror("OCC: Failed to read interrupt status !\n");
/* Should we mask it in the XIVR ? */
return;
}
prlog(PR_TRACE, "OCC: IRQ received: %04llx\n", ireg >> 48);
/* Clear the bits */
xscom_write(chip_id, P8_OCB_OCI_OCCMISC_AND, ~ireg);
/* Dispatch */
if (ireg & OCB_OCI_OCIMISC_IRQ_TMGT)
prd_tmgt_interrupt(chip_id);
if (ireg & OCB_OCI_OCIMISC_IRQ_SLW_TMR)
check_timers(true);
/* We may have masked-out OCB_OCI_OCIMISC_IRQ in the previous
* OCCMISC_AND write. Check if there are any new source bits set,
* and trigger another interrupt if so.
*/
rc = xscom_read(chip_id, P8_OCB_OCI_OCCMISC, &ireg);
if (!rc && (ireg & P8_OCB_OCI_OCIMISC_MASK))
xscom_write(chip_id, P8_OCB_OCI_OCCMISC_OR,
OCB_OCI_OCIMISC_IRQ);
}
void occ_p9_interrupt(uint32_t chip_id)
{
u64 ireg;
s64 rc;
/* The OCC interrupt is used to mux up to 15 different sources */
rc = xscom_read(chip_id, P9_OCB_OCI_OCCMISC, &ireg);
if (rc) {
prerror("OCC: Failed to read interrupt status !\n");
return;
}
prlog(PR_TRACE, "OCC: IRQ received: %04llx\n", ireg >> 48);
/* Clear the bits */
xscom_write(chip_id, P9_OCB_OCI_OCCMISC_CLEAR, ireg);
/* Dispatch */
if (ireg & OCB_OCI_OCIMISC_IRQ_TMGT)
prd_tmgt_interrupt(chip_id);
if (ireg & OCB_OCI_OCIMISC_IRQ_SHMEM) {
occ_throttle_poll(NULL);
handle_occ_rsp(chip_id);
}
if (ireg & OCB_OCI_OCIMISC_IRQ_I2C)
p9_i2c_bus_owner_change(chip_id);
/* We may have masked-out OCB_OCI_OCIMISC_IRQ in the previous
* OCCMISC_AND write. Check if there are any new source bits set,
* and trigger another interrupt if so.
*/
rc = xscom_read(chip_id, P9_OCB_OCI_OCCMISC, &ireg);
if (!rc && (ireg & P9_OCB_OCI_OCIMISC_MASK))
xscom_write(chip_id, P9_OCB_OCI_OCCMISC_OR,
OCB_OCI_OCIMISC_IRQ);
}
void occ_fsp_init(void)
{
/* OCC is supported in P8 and P9 */
if (proc_gen < proc_gen_p8)
return;
/* If we have an FSP, register for notifications */
if (fsp_present())
fsp_register_client(&fsp_occ_client, FSP_MCLASS_OCC);
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/ppc/ppc4xx_devs.c | /*
* QEMU PowerPC 4xx embedded processors shared devices emulation
*
* Copyright (c) 2007 <NAME>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/boards.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
/*#define DEBUG_UIC*/
#ifdef DEBUG_UIC
# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
#else
# define LOG_UIC(...) do { } while (0)
#endif
static void ppc4xx_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
/*****************************************************************************/
/* Generic PowerPC 4xx processor instantiation */
PowerPCCPU *ppc4xx_init(const char *cpu_type,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk)
{
PowerPCCPU *cpu;
CPUPPCState *env;
/* init CPUs */
cpu = POWERPC_CPU(cpu_create(cpu_type));
env = &cpu->env;
cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
cpu_clk->opaque = env;
/* Set time-base frequency to sysclk */
tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
qemu_register_reset(ppc4xx_reset, cpu);
return cpu;
}
/*****************************************************************************/
/* "Universal" Interrupt controller */
enum {
DCR_UICSR = 0x000,
DCR_UICSRS = 0x001,
DCR_UICER = 0x002,
DCR_UICCR = 0x003,
DCR_UICPR = 0x004,
DCR_UICTR = 0x005,
DCR_UICMSR = 0x006,
DCR_UICVR = 0x007,
DCR_UICVCR = 0x008,
DCR_UICMAX = 0x009,
};
#define UIC_MAX_IRQ 32
typedef struct ppcuic_t ppcuic_t;
struct ppcuic_t {
uint32_t dcr_base;
int use_vectors;
uint32_t level; /* Remembers the state of level-triggered interrupts. */
uint32_t uicsr; /* Status register */
uint32_t uicer; /* Enable register */
uint32_t uiccr; /* Critical register */
uint32_t uicpr; /* Polarity register */
uint32_t uictr; /* Triggering register */
uint32_t uicvcr; /* Vector configuration register */
uint32_t uicvr;
qemu_irq *irqs;
};
static void ppcuic_trigger_irq (ppcuic_t *uic)
{
uint32_t ir, cr;
int start, end, inc, i;
/* Trigger interrupt if any is pending */
ir = uic->uicsr & uic->uicer & (~uic->uiccr);
cr = uic->uicsr & uic->uicer & uic->uiccr;
LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
" uiccr %08" PRIx32 "\n"
" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
__func__, uic->uicsr, uic->uicer, uic->uiccr,
uic->uicsr & uic->uicer, ir, cr);
if (ir != 0x0000000) {
LOG_UIC("Raise UIC interrupt\n");
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
} else {
LOG_UIC("Lower UIC interrupt\n");
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
}
/* Trigger critical interrupt if any is pending and update vector */
if (cr != 0x0000000) {
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
if (uic->use_vectors) {
/* Compute critical IRQ vector */
if (uic->uicvcr & 1) {
start = 31;
end = 0;
inc = -1;
} else {
start = 0;
end = 31;
inc = 1;
}
uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
for (i = start; i <= end; i += inc) {
if (cr & (1 << i)) {
uic->uicvr += (i - start) * 512 * inc;
break;
}
}
}
LOG_UIC("Raise UIC critical interrupt - "
"vector %08" PRIx32 "\n", uic->uicvr);
} else {
LOG_UIC("Lower UIC critical interrupt\n");
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
uic->uicvr = 0x00000000;
}
}
static void ppcuic_set_irq (void *opaque, int irq_num, int level)
{
ppcuic_t *uic;
uint32_t mask, sr;
uic = opaque;
mask = 1U << (31-irq_num);
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
__func__, irq_num, level,
uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
if (irq_num < 0 || irq_num > 31)
return;
sr = uic->uicsr;
/* Update status register */
if (uic->uictr & mask) {
/* Edge sensitive interrupt */
if (level == 1)
uic->uicsr |= mask;
} else {
/* Level sensitive interrupt */
if (level == 1) {
uic->uicsr |= mask;
uic->level |= mask;
} else {
uic->uicsr &= ~mask;
uic->level &= ~mask;
}
}
LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
if (sr != uic->uicsr)
ppcuic_trigger_irq(uic);
}
static uint32_t dcr_read_uic (void *opaque, int dcrn)
{
ppcuic_t *uic;
uint32_t ret;
uic = opaque;
dcrn -= uic->dcr_base;
switch (dcrn) {
case DCR_UICSR:
case DCR_UICSRS:
ret = uic->uicsr;
break;
case DCR_UICER:
ret = uic->uicer;
break;
case DCR_UICCR:
ret = uic->uiccr;
break;
case DCR_UICPR:
ret = uic->uicpr;
break;
case DCR_UICTR:
ret = uic->uictr;
break;
case DCR_UICMSR:
ret = uic->uicsr & uic->uicer;
break;
case DCR_UICVR:
if (!uic->use_vectors)
goto no_read;
ret = uic->uicvr;
break;
case DCR_UICVCR:
if (!uic->use_vectors)
goto no_read;
ret = uic->uicvcr;
break;
default:
no_read:
ret = 0x00000000;
break;
}
return ret;
}
static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
{
ppcuic_t *uic;
uic = opaque;
dcrn -= uic->dcr_base;
LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
uic->uicsr |= uic->level;
ppcuic_trigger_irq(uic);
break;
case DCR_UICSRS:
uic->uicsr |= val;
ppcuic_trigger_irq(uic);
break;
case DCR_UICER:
uic->uicer = val;
ppcuic_trigger_irq(uic);
break;
case DCR_UICCR:
uic->uiccr = val;
ppcuic_trigger_irq(uic);
break;
case DCR_UICPR:
uic->uicpr = val;
break;
case DCR_UICTR:
uic->uictr = val;
ppcuic_trigger_irq(uic);
break;
case DCR_UICMSR:
break;
case DCR_UICVR:
break;
case DCR_UICVCR:
uic->uicvcr = val & 0xFFFFFFFD;
ppcuic_trigger_irq(uic);
break;
}
}
static void ppcuic_reset (void *opaque)
{
ppcuic_t *uic;
uic = opaque;
uic->uiccr = 0x00000000;
uic->uicer = 0x00000000;
uic->uicpr = 0x00000000;
uic->uicsr = 0x00000000;
uic->uictr = 0x00000000;
if (uic->use_vectors) {
uic->uicvcr = 0x00000000;
uic->uicvr = 0x0000000;
}
}
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr)
{
ppcuic_t *uic;
int i;
uic = g_malloc0(sizeof(ppcuic_t));
uic->dcr_base = dcr_base;
uic->irqs = irqs;
if (has_vr)
uic->use_vectors = 1;
for (i = 0; i < DCR_UICMAX; i++) {
ppc_dcr_register(env, dcr_base + i, uic,
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
/*****************************************************************************/
/* SDRAM controller */
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
MemoryRegion containers[4]; /* used for clipping */
MemoryRegion *ram_memories;
hwaddr ram_bases[4];
hwaddr ram_sizes[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
uint32_t cfg;
uint32_t status;
uint32_t rtr;
uint32_t pmit;
uint32_t bcr[4];
uint32_t tr;
uint32_t ecccfg;
uint32_t eccesr;
qemu_irq irq;
};
enum {
SDRAM0_CFGADDR = 0x010,
SDRAM0_CFGDATA = 0x011,
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
* there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
static uint32_t sdram_bcr (hwaddr ram_base,
hwaddr ram_size)
{
uint32_t bcr;
switch (ram_size) {
case 4 * MiB:
bcr = 0x00000000;
break;
case 8 * MiB:
bcr = 0x00020000;
break;
case 16 * MiB:
bcr = 0x00040000;
break;
case 32 * MiB:
bcr = 0x00060000;
break;
case 64 * MiB:
bcr = 0x00080000;
break;
case 128 * MiB:
bcr = 0x000A0000;
break;
case 256 * MiB:
bcr = 0x000C0000;
break;
default:
printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
ram_size);
return 0x00000000;
}
bcr |= ram_base & 0xFF800000;
bcr |= 1;
return bcr;
}
static inline hwaddr sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
static target_ulong sdram_size (uint32_t bcr)
{
target_ulong size;
int sh;
sh = (bcr >> 17) & 0x7;
if (sh == 7)
size = -1;
else
size = (4 * MiB) << sh;
return size;
}
static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bcr[i] & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
memory_region_del_subregion(get_system_memory(),
&sdram->containers[i]);
memory_region_del_subregion(&sdram->containers[i],
&sdram->ram_memories[i]);
object_unparent(OBJECT(&sdram->containers[i]));
}
sdram->bcr[i] = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
#ifdef DEBUG_SDRAM
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
sdram_size(bcr));
memory_region_add_subregion(&sdram->containers[i], 0,
&sdram->ram_memories[i]);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
&sdram->containers[i]);
}
}
static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->ram_sizes[i] != 0) {
sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
sdram->ram_sizes[i]), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
}
}
static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
#ifdef DEBUG_SDRAM
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
memory_region_del_subregion(get_system_memory(),
&sdram->ram_memories[i]);
}
}
static uint32_t dcr_read_sdram (void *opaque, int dcrn)
{
ppc4xx_sdram_t *sdram;
uint32_t ret;
sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
ret = sdram->addr;
break;
case SDRAM0_CFGDATA:
switch (sdram->addr) {
case 0x00: /* SDRAM_BESR0 */
ret = sdram->besr0;
break;
case 0x08: /* SDRAM_BESR1 */
ret = sdram->besr1;
break;
case 0x10: /* SDRAM_BEAR */
ret = sdram->bear;
break;
case 0x20: /* SDRAM_CFG */
ret = sdram->cfg;
break;
case 0x24: /* SDRAM_STATUS */
ret = sdram->status;
break;
case 0x30: /* SDRAM_RTR */
ret = sdram->rtr;
break;
case 0x34: /* SDRAM_PMIT */
ret = sdram->pmit;
break;
case 0x40: /* SDRAM_B0CR */
ret = sdram->bcr[0];
break;
case 0x44: /* SDRAM_B1CR */
ret = sdram->bcr[1];
break;
case 0x48: /* SDRAM_B2CR */
ret = sdram->bcr[2];
break;
case 0x4C: /* SDRAM_B3CR */
ret = sdram->bcr[3];
break;
case 0x80: /* SDRAM_TR */
ret = -1; /* ? */
break;
case 0x94: /* SDRAM_ECCCFG */
ret = sdram->ecccfg;
break;
case 0x98: /* SDRAM_ECCESR */
ret = sdram->eccesr;
break;
default: /* Error */
ret = -1;
break;
}
break;
default:
/* Avoid gcc warning */
ret = 0x00000000;
break;
}
return ret;
}
static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_sdram_t *sdram;
sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
sdram->addr = val;
break;
case SDRAM0_CFGDATA:
switch (sdram->addr) {
case 0x00: /* SDRAM_BESR0 */
sdram->besr0 &= ~val;
break;
case 0x08: /* SDRAM_BESR1 */
sdram->besr1 &= ~val;
break;
case 0x10: /* SDRAM_BEAR */
sdram->bear = val;
break;
case 0x20: /* SDRAM_CFG */
val &= 0xFFE00000;
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
#ifdef DEBUG_SDRAM
printf("%s: enable SDRAM controller\n", __func__);
#endif
/* validate all RAM mappings */
sdram_map_bcr(sdram);
sdram->status &= ~0x80000000;
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
#ifdef DEBUG_SDRAM
printf("%s: disable SDRAM controller\n", __func__);
#endif
/* invalidate all RAM mappings */
sdram_unmap_bcr(sdram);
sdram->status |= 0x80000000;
}
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
sdram->status |= 0x40000000;
else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
sdram->status &= ~0x40000000;
sdram->cfg = val;
break;
case 0x24: /* SDRAM_STATUS */
/* Read-only register */
break;
case 0x30: /* SDRAM_RTR */
sdram->rtr = val & 0x3FF80000;
break;
case 0x34: /* SDRAM_PMIT */
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
break;
case 0x94: /* SDRAM_ECCCFG */
sdram->ecccfg = val & 0x00F00000;
break;
case 0x98: /* SDRAM_ECCESR */
val &= 0xFFF0F000;
if (sdram->eccesr == 0 && val != 0)
qemu_irq_raise(sdram->irq);
else if (sdram->eccesr != 0 && val == 0)
qemu_irq_lower(sdram->irq);
sdram->eccesr = val;
break;
default: /* Error */
break;
}
break;
}
}
static void sdram_reset (void *opaque)
{
ppc4xx_sdram_t *sdram;
sdram = opaque;
sdram->addr = 0x00000000;
sdram->bear = 0x00000000;
sdram->besr0 = 0x00000000; /* No error */
sdram->besr1 = 0x00000000; /* No error */
sdram->cfg = 0x00000000;
sdram->ecccfg = 0x00000000; /* No ECC */
sdram->eccesr = 0x00000000; /* No error */
sdram->pmit = 0x07C00000;
sdram->rtr = 0x05F00000;
sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */
sdram->status = 0x00000000;
sdram->cfg = 0x00800000;
}
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
hwaddr *ram_bases,
hwaddr *ram_sizes,
int do_init)
{
ppc4xx_sdram_t *sdram;
sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(hwaddr));
memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
if (do_init)
sdram_map_bcr(sdram);
}
/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
*
* sdram_bank_sizes[] must be 0-terminated.
*
* The 4xx SDRAM controller supports a small number of banks, and each bank
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[],
hwaddr ram_sizes[],
const ram_addr_t sdram_bank_sizes[])
{
MemoryRegion *ram = g_malloc0(sizeof(*ram));
ram_addr_t size_left = ram_size;
ram_addr_t base = 0;
ram_addr_t bank_size;
int i;
int j;
for (i = 0; i < nr_banks; i++) {
for (j = 0; sdram_bank_sizes[j] != 0; j++) {
bank_size = sdram_bank_sizes[j];
if (bank_size <= size_left) {
size_left -= bank_size;
}
}
if (!size_left) {
/* No need to use the remaining banks. */
break;
}
}
ram_size -= size_left;
if (size_left) {
error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM"
" controller limits", ram_size / MiB);
}
memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);
size_left = ram_size;
for (i = 0; i < nr_banks && size_left; i++) {
for (j = 0; sdram_bank_sizes[j] != 0; j++) {
bank_size = sdram_bank_sizes[j];
if (bank_size <= size_left) {
char name[32];
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
memory_region_init_alias(&ram_memories[i], NULL, name, ram,
base, bank_size);
ram_bases[i] = base;
ram_sizes[i] = bank_size;
base += bank_size;
size_left -= bank_size;
break;
}
}
}
return ram_size;
}
/*****************************************************************************/
/* MAL */
enum {
MAL0_CFG = 0x180,
MAL0_ESR = 0x181,
MAL0_IER = 0x182,
MAL0_TXCASR = 0x184,
MAL0_TXCARR = 0x185,
MAL0_TXEOBISR = 0x186,
MAL0_TXDEIR = 0x187,
MAL0_RXCASR = 0x190,
MAL0_RXCARR = 0x191,
MAL0_RXEOBISR = 0x192,
MAL0_RXDEIR = 0x193,
MAL0_TXCTP0R = 0x1A0,
MAL0_RXCTP0R = 0x1C0,
MAL0_RCBS0 = 0x1E0,
MAL0_RCBS1 = 0x1E1,
};
typedef struct ppc4xx_mal_t ppc4xx_mal_t;
struct ppc4xx_mal_t {
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
uint32_t ier;
uint32_t txcasr;
uint32_t txcarr;
uint32_t txeobisr;
uint32_t txdeir;
uint32_t rxcasr;
uint32_t rxcarr;
uint32_t rxeobisr;
uint32_t rxdeir;
uint32_t *txctpr;
uint32_t *rxctpr;
uint32_t *rcbs;
uint8_t txcnum;
uint8_t rxcnum;
};
static void ppc4xx_mal_reset(void *opaque)
{
ppc4xx_mal_t *mal;
mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x00000000;
mal->ier = 0x00000000;
mal->rxcasr = 0x00000000;
mal->rxdeir = 0x00000000;
mal->rxeobisr = 0x00000000;
mal->txcasr = 0x00000000;
mal->txdeir = 0x00000000;
mal->txeobisr = 0x00000000;
}
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
ppc4xx_mal_t *mal;
uint32_t ret;
mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
break;
case MAL0_ESR:
ret = mal->esr;
break;
case MAL0_IER:
ret = mal->ier;
break;
case MAL0_TXCASR:
ret = mal->txcasr;
break;
case MAL0_TXCARR:
ret = mal->txcarr;
break;
case MAL0_TXEOBISR:
ret = mal->txeobisr;
break;
case MAL0_TXDEIR:
ret = mal->txdeir;
break;
case MAL0_RXCASR:
ret = mal->rxcasr;
break;
case MAL0_RXCARR:
ret = mal->rxcarr;
break;
case MAL0_RXEOBISR:
ret = mal->rxeobisr;
break;
case MAL0_RXDEIR:
ret = mal->rxdeir;
break;
default:
ret = 0;
break;
}
if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
}
if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
}
if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
ret = mal->rcbs[dcrn - MAL0_RCBS0];
}
return ret;
}
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
ppc4xx_mal_t *mal;
mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000) {
ppc4xx_mal_reset(mal);
}
mal->cfg = val & 0x00FFC087;
break;
case MAL0_ESR:
/* Read/clear */
mal->esr &= ~val;
break;
case MAL0_IER:
mal->ier = val & 0x0000001F;
break;
case MAL0_TXCASR:
mal->txcasr = val & 0xF0000000;
break;
case MAL0_TXCARR:
mal->txcarr = val & 0xF0000000;
break;
case MAL0_TXEOBISR:
/* Read/clear */
mal->txeobisr &= ~val;
break;
case MAL0_TXDEIR:
/* Read/clear */
mal->txdeir &= ~val;
break;
case MAL0_RXCASR:
mal->rxcasr = val & 0xC0000000;
break;
case MAL0_RXCARR:
mal->rxcarr = val & 0xC0000000;
break;
case MAL0_RXEOBISR:
/* Read/clear */
mal->rxeobisr &= ~val;
break;
case MAL0_RXDEIR:
/* Read/clear */
mal->rxdeir &= ~val;
break;
}
if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
}
if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
}
if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
}
}
void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
qemu_irq irqs[4])
{
ppc4xx_mal_t *mal;
int i;
assert(txcnum <= 32 && rxcnum <= 32);
mal = g_malloc0(sizeof(*mal));
mal->txcnum = txcnum;
mal->rxcnum = rxcnum;
mal->txctpr = g_new0(uint32_t, txcnum);
mal->rxctpr = g_new0(uint32_t, rxcnum);
mal->rcbs = g_new0(uint32_t, rxcnum);
for (i = 0; i < 4; i++) {
mal->irqs[i] = irqs[i];
}
qemu_register_reset(&ppc4xx_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_IER,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
for (i = 0; i < txcnum; i++) {
ppc_dcr_register(env, MAL0_TXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
for (i = 0; i < rxcnum; i++) {
ppc_dcr_register(env, MAL0_RXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
for (i = 0; i < rxcnum; i++) {
ppc_dcr_register(env, MAL0_RCBS0 + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/include/authz/pamacct.h | /*
* QEMU PAM authorization driver
*
* Copyright (c) 2018 Red Hat, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef QAUTHZ_PAM_H__
#define QAUTHZ_PAM_H__
#include "authz/base.h"
#define TYPE_QAUTHZ_PAM "authz-pam"
#define QAUTHZ_PAM_CLASS(klass) \
OBJECT_CLASS_CHECK(QAuthZPAMClass, (klass), \
TYPE_QAUTHZ_PAM)
#define QAUTHZ_PAM_GET_CLASS(obj) \
OBJECT_GET_CLASS(QAuthZPAMClass, (obj), \
TYPE_QAUTHZ_PAM)
#define QAUTHZ_PAM(obj) \
OBJECT_CHECK(QAuthZPAM, (obj), \
TYPE_QAUTHZ_PAM)
typedef struct QAuthZPAM QAuthZPAM;
typedef struct QAuthZPAMClass QAuthZPAMClass;
/**
* QAuthZPAM:
*
* This authorization driver provides a PAM mechanism
* for granting access by matching user names against a
* list of globs. Each match rule has an associated policy
* and a catch all policy applies if no rule matches
*
* To create an instance of this class via QMP:
*
* {
* "execute": "object-add",
* "arguments": {
* "qom-type": "authz-pam",
* "id": "authz0",
* "parameters": {
* "service": "qemu-vnc-tls"
* }
* }
* }
*
* The driver only uses the PAM "account" verification
* subsystem. The above config would require a config
* file /etc/pam.d/qemu-vnc-tls. For a simple file
* lookup it would contain
*
* account requisite pam_listfile.so item=user sense=allow \
* file=/etc/qemu/vnc.allow
*
* The external file would then contain a list of usernames.
* If x509 cert was being used as the username, a suitable
* entry would match the distinguish name:
*
* CN=laptop.berrange.com,O=Berrange Home,L=London,ST=London,C=GB
*
* On the command line it can be created using
*
* -object authz-pam,id=authz0,service=qemu-vnc-tls
*
*/
struct QAuthZPAM {
QAuthZ parent_obj;
char *service;
};
struct QAuthZPAMClass {
QAuthZClass parent_class;
};
QAuthZPAM *qauthz_pam_new(const char *id,
const char *service,
Error **errp);
#endif /* QAUTHZ_PAM_H__ */
|
pmp-tool/PMP | src/qemu/src-pmp/tests/libqos/virtio-pci.c | /*
* libqos virtio PCI driver
*
* Copyright (c) 2014 <NAME>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/virtio.h"
#include "libqos/virtio-pci.h"
#include "libqos/pci.h"
#include "libqos/pci-pc.h"
#include "libqos/malloc.h"
#include "libqos/malloc-pc.h"
#include "libqos/qgraph.h"
#include "standard-headers/linux/virtio_ring.h"
#include "standard-headers/linux/virtio_pci.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_regs.h"
/* virtio-pci is a superclass of all virtio-xxx-pci devices;
* the relation between virtio-pci and virtio-xxx-pci is implicit,
* and therefore virtio-pci does not produce virtio and is not
* reached by any edge, not even as a "contains" edge.
* In facts, every device is a QVirtioPCIDevice with
* additional fields, since every one has its own
* number of queues and various attributes.
* Virtio-pci provides default functions to start the
* hw and destroy the object, and nodes that want to
* override them should always remember to call the
* original qvirtio_pci_destructor and qvirtio_pci_start_hw.
*/
static inline bool qvirtio_pci_is_big_endian(QVirtioPCIDevice *dev)
{
QPCIBus *bus = dev->pdev->bus;
/* FIXME: virtio 1.0 is always little-endian */
return qtest_big_endian(bus->qts);
}
#define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
return qpci_io_readb(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
}
/* PCI is always read in little-endian order
* but virtio ( < 1.0) is in guest order
* so with a big-endian guest the order has been reversed,
* reverse it again
* virtio-1.0 is always little-endian, like PCI, but this
* case will be managed inside qvirtio_pci_is_big_endian()
*/
static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
uint16_t value;
value = qpci_io_readw(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
if (qvirtio_is_big_endian(d)) {
value = bswap16(value);
}
return value;
}
static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
uint32_t value;
value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
if (qvirtio_is_big_endian(d)) {
value = bswap32(value);
}
return value;
}
static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
uint64_t val;
val = qpci_io_readq(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
if (qvirtio_is_big_endian(d)) {
val = bswap64(val);
}
return val;
}
static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_HOST_FEATURES);
}
static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES, features);
}
static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES);
}
static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS);
}
static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS, status);
}
static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
uint32_t data;
if (dev->pdev->msix_enabled) {
g_assert_cmpint(vqpci->msix_entry, !=, -1);
if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
/* No ISR checking should be done if masked, but read anyway */
return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
} else {
data = readl(vqpci->msix_addr);
if (data == vqpci->msix_data) {
writel(vqpci->msix_addr, 0);
return true;
} else {
return false;
}
}
} else {
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1;
}
}
static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
uint32_t data;
if (dev->pdev->msix_enabled) {
g_assert_cmpint(dev->config_msix_entry, !=, -1);
if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
/* No ISR checking should be done if masked, but read anyway */
return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
} else {
data = readl(dev->config_msix_addr);
if (data == dev->config_msix_data) {
writel(dev->config_msix_addr, 0);
return true;
} else {
return false;
}
}
} else {
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2;
}
}
static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_SEL, index);
}
static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
return qpci_io_readw(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NUM);
}
static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn);
}
static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
QGuestAllocator *alloc, uint16_t index)
{
uint32_t feat;
uint64_t addr;
QVirtQueuePCI *vqpci;
vqpci = g_malloc0(sizeof(*vqpci));
feat = qvirtio_pci_get_guest_features(d);
qvirtio_pci_queue_select(d, index);
vqpci->vq.index = index;
vqpci->vq.size = qvirtio_pci_get_queue_size(d);
vqpci->vq.free_head = 0;
vqpci->vq.num_free = vqpci->vq.size;
vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
vqpci->vq.indirect = (feat & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
vqpci->vq.event = (feat & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;
vqpci->msix_entry = -1;
vqpci->msix_addr = 0;
vqpci->msix_data = 0x12345678;
/* Check different than 0 */
g_assert_cmpint(vqpci->vq.size, !=, 0);
/* Check power of 2 */
g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
VIRTIO_PCI_VRING_ALIGN));
qvring_init(alloc, &vqpci->vq, addr);
qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALIGN);
return &vqpci->vq;
}
static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq,
QGuestAllocator *alloc)
{
QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
guest_free(alloc, vq->desc);
g_free(vqpci);
}
static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
qpci_io_writew(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
}
const QVirtioBus qvirtio_pci = {
.config_readb = qvirtio_pci_config_readb,
.config_readw = qvirtio_pci_config_readw,
.config_readl = qvirtio_pci_config_readl,
.config_readq = qvirtio_pci_config_readq,
.get_features = qvirtio_pci_get_features,
.set_features = qvirtio_pci_set_features,
.get_guest_features = qvirtio_pci_get_guest_features,
.get_status = qvirtio_pci_get_status,
.set_status = qvirtio_pci_set_status,
.get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
.get_config_isr_status = qvirtio_pci_get_config_isr_status,
.queue_select = qvirtio_pci_queue_select,
.get_queue_size = qvirtio_pci_get_queue_size,
.set_queue_address = qvirtio_pci_set_queue_address,
.virtqueue_setup = qvirtio_pci_virtqueue_setup,
.virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup,
.virtqueue_kick = qvirtio_pci_virtqueue_kick,
};
void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
{
qpci_device_enable(d->pdev);
d->bar = qpci_iomap(d->pdev, 0, NULL);
}
void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
{
qpci_iounmap(d->pdev, d->bar);
}
void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
QGuestAllocator *alloc, uint16_t entry)
{
uint16_t vector;
uint32_t control;
uint64_t off;
g_assert(d->pdev->msix_enabled);
off = d->pdev->msix_table_off + (entry * 16);
g_assert_cmpint(entry, >=, 0);
g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
vqpci->msix_entry = entry;
vqpci->msix_addr = guest_alloc(alloc, 4);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_UPPER_ADDR,
(vqpci->msix_addr >> 32) & ~0UL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_VECTOR_CTRL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_VECTOR_CTRL,
control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR, entry);
vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR);
g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
}
void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
QGuestAllocator *alloc, uint16_t entry)
{
uint16_t vector;
uint32_t control;
uint64_t off;
g_assert(d->pdev->msix_enabled);
off = d->pdev->msix_table_off + (entry * 16);
g_assert_cmpint(entry, >=, 0);
g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
d->config_msix_entry = entry;
d->config_msix_data = 0x12345678;
d->config_msix_addr = guest_alloc(alloc, 4);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_UPPER_ADDR,
(d->config_msix_addr >> 32) & ~0UL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_VECTOR_CTRL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_VECTOR_CTRL,
control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR, entry);
vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR);
g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
}
void qvirtio_pci_destructor(QOSGraphObject *obj)
{
QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
qvirtio_pci_device_disable(dev);
g_free(dev->pdev);
}
void qvirtio_pci_start_hw(QOSGraphObject *obj)
{
QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
qvirtio_pci_device_enable(dev);
qvirtio_start_device(&dev->vdev);
}
static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice *dev, QPCIDevice *pci_dev)
{
dev->pdev = pci_dev;
dev->vdev.device_type = qpci_config_readw(pci_dev, PCI_SUBSYSTEM_ID);
dev->config_msix_entry = -1;
dev->vdev.bus = &qvirtio_pci;
dev->vdev.big_endian = qvirtio_pci_is_big_endian(dev);
/* each virtio-xxx-pci device should override at least this function */
dev->obj.get_driver = NULL;
dev->obj.start_hw = qvirtio_pci_start_hw;
dev->obj.destructor = qvirtio_pci_destructor;
}
void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * addr)
{
QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
g_assert_nonnull(pci_dev);
qvirtio_pci_init_from_pcidev(dev, pci_dev);
}
QVirtioPCIDevice *virtio_pci_new(QPCIBus *bus, QPCIAddress * addr)
{
QVirtioPCIDevice *dev;
QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
if (!pci_dev) {
return NULL;
}
dev = g_new0(QVirtioPCIDevice, 1);
qvirtio_pci_init_from_pcidev(dev, pci_dev);
dev->obj.free = g_free;
return dev;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/isa/mips64r6/shift/test_mips64r6_srav.c | <filename>src/qemu/src-pmp/tests/tcg/mips/user/isa/mips64r6/shift/test_mips64r6_srav.c
/*
* Test program for MIPS64R6 instruction SRAV
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *instruction_name = "SRAV";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0xffffffffffffffffULL, /* 0 */
0xffffffffffffffffULL,
0xffffffffffffffffULL,
0xffffffffffffffffULL,
0xffffffffffffffffULL,
0xffffffffffffffffULL,
0xffffffffffffffffULL,
0xffffffffffffffffULL,
0x0000000000000000ULL, /* 8 */
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0xffffffffffffffffULL, /* 16 */
0xffffffffaaaaaaaaULL,
0xffffffffffeaaaaaULL,
0xfffffffffffffd55ULL,
0xfffffffffffaaaaaULL,
0xfffffffffffff555ULL,
0xfffffffffffeaaaaULL,
0xffffffffffffd555ULL,
0x0000000000000000ULL, /* 24 */
0x0000000055555555ULL,
0x0000000000155555ULL,
0x00000000000002aaULL,
0x0000000000055555ULL,
0x0000000000000aaaULL,
0x0000000000015555ULL,
0x0000000000002aaaULL,
0xffffffffffffffffULL, /* 32 */
0xffffffffccccccccULL,
0xfffffffffff33333ULL,
0xfffffffffffffe66ULL,
0xfffffffffffcccccULL,
0xfffffffffffff999ULL,
0xffffffffffff3333ULL,
0xffffffffffffe666ULL,
0x0000000000000000ULL, /* 40 */
0x0000000033333333ULL,
0x00000000000cccccULL,
0x0000000000000199ULL,
0x0000000000033333ULL,
0x0000000000000666ULL,
0x000000000000ccccULL,
0x0000000000001999ULL,
0xffffffffffffffffULL, /* 48 */
0xffffffff8e38e38eULL,
0xffffffffffe38e38ULL,
0xfffffffffffffc71ULL,
0xfffffffffff8e38eULL,
0xfffffffffffff1c7ULL,
0xfffffffffffe38e3ULL,
0xffffffffffffc71cULL,
0x0000000000000000ULL, /* 56 */
0x0000000071c71c71ULL,
0x00000000001c71c7ULL,
0x000000000000038eULL,
0x0000000000071c71ULL,
0x0000000000000e38ULL,
0x000000000001c71cULL,
0x00000000000038e3ULL,
0x0000000028625540ULL, /* 64 */
0x0000000000286255ULL,
0x0000000028625540ULL,
0x000000000000a189ULL,
0x000000004d93c708ULL,
0x00000000004d93c7ULL,
0x000000004d93c708ULL,
0x000000000001364fULL,
0xffffffffb9cf8b80ULL, /* 72 */
0xffffffffffb9cf8bULL,
0xffffffffb9cf8b80ULL,
0xfffffffffffee73eULL,
0x000000005e31e24eULL,
0x00000000005e31e2ULL,
0x000000005e31e24eULL,
0x00000000000178c7ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_SRAV(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_SRAV(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
b64_result, b64_expect);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/slirp/src/debug.h | /* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 1995 <NAME>.
*/
#ifndef DEBUG_H_
#define DEBUG_H_
#define DBG_CALL (1 << 0)
#define DBG_MISC (1 << 1)
#define DBG_ERROR (1 << 2)
#define DBG_TFTP (1 << 3)
extern int slirp_debug;
#define DEBUG_CALL(fmt, ...) do { \
if (G_UNLIKELY(slirp_debug & DBG_CALL)) { \
g_debug(fmt "...", ##__VA_ARGS__); \
} \
} while (0)
#define DEBUG_ARG(fmt, ...) do { \
if (G_UNLIKELY(slirp_debug & DBG_CALL)) { \
g_debug(" " fmt, ##__VA_ARGS__); \
} \
} while (0)
#define DEBUG_MISC(fmt, ...) do { \
if (G_UNLIKELY(slirp_debug & DBG_MISC)) { \
g_debug(fmt, ##__VA_ARGS__); \
} \
} while (0)
#define DEBUG_ERROR(fmt, ...) do { \
if (G_UNLIKELY(slirp_debug & DBG_ERROR)) { \
g_debug(fmt, ##__VA_ARGS__); \
} \
} while (0)
#define DEBUG_TFTP(fmt, ...) do { \
if (G_UNLIKELY(slirp_debug & DBG_TFTP)) { \
g_debug(fmt, ##__VA_ARGS__); \
} \
} while (0)
#endif /* DEBUG_H_ */
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-subtract/test_msa_subs_s_b.c | /*
* Test program for MSA instruction SUBS_S.B
*
* Copyright (C) 2018 Wave Computing, Inc.
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs.h"
#include "../../../../include/test_utils.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "SUBS_S.B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 0 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0x1c71c71c71c71c71ULL, 0xc71c71c71c71c71cULL, },
{ 0xe38e38e38e38e38eULL, 0x38e38e38e38e38e3ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x5656565656565656ULL, 0x5656565656565656ULL, },
{ 0xababababababababULL, 0xababababababababULL, },
{ 0x3434343434343434ULL, 0x3434343434343434ULL, },
{ 0xcdcdcdcdcdcdcdcdULL, 0xcdcdcdcdcdcdcdcdULL, },
{ 0x1d72c81d72c81d72ULL, 0xc81d72c81d72c81dULL, },
{ 0xe48f39e48f39e48fULL, 0x39e48f39e48f39e4ULL, },
{ 0xababababababababULL, 0xababababababababULL, }, /* 16 */
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x8080808080808080ULL, 0x8080808080808080ULL, },
{ 0xdedededededededeULL, 0xdedededededededeULL, },
{ 0x8080808080808080ULL, 0x8080808080808080ULL, },
{ 0xc71c80c71c80c71cULL, 0x80c71c80c71c80c7ULL, },
{ 0x8e80e38e80e38e80ULL, 0xe38e80e38e80e38eULL, },
{ 0x5656565656565656ULL, 0x5656565656565656ULL, }, /* 24 */
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x2222222222222222ULL, 0x2222222222222222ULL, },
{ 0x727f1d727f1d727fULL, 0x1d727f1d727f1d72ULL, },
{ 0x39e47f39e47f39e4ULL, 0x7f39e47f39e47f39ULL, },
{ 0xcdcdcdcdcdcdcdcdULL, 0xcdcdcdcdcdcdcdcdULL, }, /* 32 */
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0x2222222222222222ULL, 0x2222222222222222ULL, },
{ 0x8080808080808080ULL, 0x8080808080808080ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x9999999999999999ULL, 0x9999999999999999ULL, },
{ 0xe93e94e93e94e93eULL, 0x94e93e94e93e94e9ULL, },
{ 0xb08005b08005b080ULL, 0x05b08005b08005b0ULL, },
{ 0x3434343434343434ULL, 0x3434343434343434ULL, }, /* 40 */
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0xdedededededededeULL, 0xdedededededededeULL, },
{ 0x6767676767676767ULL, 0x6767676767676767ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x507ffb507ffb507fULL, 0xfb507ffb507ffb50ULL, },
{ 0x17c26c17c26c17c2ULL, 0x6c17c26c17c26c17ULL, },
{ 0xe48f39e48f39e48fULL, 0x39e48f39e48f39e4ULL, }, /* 48 */
{ 0xe38e38e38e38e38eULL, 0x38e38e38e38e38e3ULL, },
{ 0x39e47f39e47f39e4ULL, 0x7f39e47f39e47f39ULL, },
{ 0x8e80e38e80e38e80ULL, 0xe38e80e38e80e38eULL, },
{ 0x17c26c17c26c17c2ULL, 0x6c17c26c17c26c17ULL, },
{ 0xb08005b08005b080ULL, 0x05b08005b08005b0ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xc78071c78071c780ULL, 0x71c78071c78071c7ULL, },
{ 0x1d72c81d72c81d72ULL, 0xc81d72c81d72c81dULL, }, /* 56 */
{ 0x1c71c71c71c71c71ULL, 0xc71c71c71c71c71cULL, },
{ 0x727f1d727f1d727fULL, 0x1d727f1d727f1d72ULL, },
{ 0xc71c80c71c80c71cULL, 0x80c71c80c71c80c7ULL, },
{ 0x507ffb507ffb507fULL, 0xfb507ffb507ffb50ULL, },
{ 0xe93e94e93e94e93eULL, 0x94e93e94e93e94e9ULL, },
{ 0x397f8f397f8f397fULL, 0x8f397f8f397f8f39ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 64 */
{ 0x8d7fe680db7f7f38ULL, 0x39705044e93c8010ULL, },
{ 0xdc1038226f7f7f7fULL, 0x247f455f53508bf8ULL, },
{ 0x801bd080ca3173f2ULL, 0x7f767f7f5539ce6cULL, },
{ 0x73801a7f258080c8ULL, 0xc790b0bc17c47ff0ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x4f80527f7fc43c7fULL, 0xeb1ff51b6a142de8ULL, },
{ 0x8b80ea16ef80e5baULL, 0x7f0633426cfd705cULL, },
{ 0x24f0c8de91808080ULL, 0xdc80bba1adb07508ULL, }, /* 72 */
{ 0xb17fae80803cc480ULL, 0x15e10be596ecd318ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x800b9880809ea980ULL, 0x7fe73e2702e94374ULL, },
{ 0x7fe5307f36cf8d0eULL, 0x808a8080abc73294ULL, },
{ 0x757f16ea117f1b46ULL, 0x80facdbe940390a4ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_SUBS_S_B(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_SUBS_S_B(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/virtio-test.c | /*
* QTest testcase for virtio
*
* Copyright (c) 2018 Red Hat, Inc.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/qgraph.h"
#include "libqos/pci.h"
/* Tests only initialization so far. TODO: Replace with functional tests */
static void nop(void *obj, void *data, QGuestAllocator *alloc)
{
}
static void register_virtio_test(void)
{
qos_add_test("nop", "virtio", nop, NULL);
}
libqos_init(register_virtio_test);
|
pmp-tool/PMP | src/qemu/src-pmp/util/vfio-helpers.c | /*
* VFIO utility
*
* Copyright 2016 - 2018 Red Hat, Inc.
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include <sys/ioctl.h>
#include <linux/vfio.h>
#include "qapi/error.h"
#include "exec/ramlist.h"
#include "exec/cpu-common.h"
#include "trace.h"
#include "qemu/queue.h"
#include "qemu/error-report.h"
#include "standard-headers/linux/pci_regs.h"
#include "qemu/event_notifier.h"
#include "qemu/vfio-helpers.h"
#include "trace.h"
#define QEMU_VFIO_DEBUG 0
#define QEMU_VFIO_IOVA_MIN 0x10000ULL
/* XXX: Once VFIO exposes the iova bit width in the IOMMU capability interface,
* we can use a runtime limit; alternatively it's also possible to do platform
* specific detection by reading sysfs entries. Until then, 39 is a safe bet.
**/
#define QEMU_VFIO_IOVA_MAX (1ULL << 39)
typedef struct {
/* Page aligned addr. */
void *host;
size_t size;
uint64_t iova;
} IOVAMapping;
struct QEMUVFIOState {
QemuMutex lock;
/* These fields are protected by BQL */
int container;
int group;
int device;
RAMBlockNotifier ram_notifier;
struct vfio_region_info config_region_info, bar_region_info[6];
/* These fields are protected by @lock */
/* VFIO's IO virtual address space is managed by splitting into a few
* sections:
*
* --------------- <= 0
* |xxxxxxxxxxxxx|
* |-------------| <= QEMU_VFIO_IOVA_MIN
* | |
* | Fixed |
* | |
* |-------------| <= low_water_mark
* | |
* | Free |
* | |
* |-------------| <= high_water_mark
* | |
* | Temp |
* | |
* |-------------| <= QEMU_VFIO_IOVA_MAX
* |xxxxxxxxxxxxx|
* |xxxxxxxxxxxxx|
* ---------------
*
* - Addresses lower than QEMU_VFIO_IOVA_MIN are reserved as invalid;
*
* - Fixed mappings of HVAs are assigned "low" IOVAs in the range of
* [QEMU_VFIO_IOVA_MIN, low_water_mark). Once allocated they will not be
* reclaimed - low_water_mark never shrinks;
*
* - IOVAs in range [low_water_mark, high_water_mark) are free;
*
* - IOVAs in range [high_water_mark, QEMU_VFIO_IOVA_MAX) are volatile
* mappings. At each qemu_vfio_dma_reset_temporary() call, the whole area
* is recycled. The caller should make sure I/O's depending on these
* mappings are completed before calling.
**/
uint64_t low_water_mark;
uint64_t high_water_mark;
IOVAMapping *mappings;
int nr_mappings;
};
/**
* Find group file by PCI device address as specified @device, and return the
* path. The returned string is owned by caller and should be g_free'ed later.
*/
static char *sysfs_find_group_file(const char *device, Error **errp)
{
char *sysfs_link;
char *sysfs_group;
char *p;
char *path = NULL;
sysfs_link = g_strdup_printf("/sys/bus/pci/devices/%s/iommu_group", device);
sysfs_group = g_malloc0(PATH_MAX);
if (readlink(sysfs_link, sysfs_group, PATH_MAX - 1) == -1) {
error_setg_errno(errp, errno, "Failed to find iommu group sysfs path");
goto out;
}
p = strrchr(sysfs_group, '/');
if (!p) {
error_setg(errp, "Failed to find iommu group number");
goto out;
}
path = g_strdup_printf("/dev/vfio/%s", p + 1);
out:
g_free(sysfs_link);
g_free(sysfs_group);
return path;
}
static inline void assert_bar_index_valid(QEMUVFIOState *s, int index)
{
assert(index >= 0 && index < ARRAY_SIZE(s->bar_region_info));
}
static int qemu_vfio_pci_init_bar(QEMUVFIOState *s, int index, Error **errp)
{
assert_bar_index_valid(s, index);
s->bar_region_info[index] = (struct vfio_region_info) {
.index = VFIO_PCI_BAR0_REGION_INDEX + index,
.argsz = sizeof(struct vfio_region_info),
};
if (ioctl(s->device, VFIO_DEVICE_GET_REGION_INFO, &s->bar_region_info[index])) {
error_setg_errno(errp, errno, "Failed to get BAR region info");
return -errno;
}
return 0;
}
/**
* Map a PCI bar area.
*/
void *qemu_vfio_pci_map_bar(QEMUVFIOState *s, int index,
uint64_t offset, uint64_t size,
Error **errp)
{
void *p;
assert_bar_index_valid(s, index);
p = mmap(NULL, MIN(size, s->bar_region_info[index].size - offset),
PROT_READ | PROT_WRITE, MAP_SHARED,
s->device, s->bar_region_info[index].offset + offset);
if (p == MAP_FAILED) {
error_setg_errno(errp, errno, "Failed to map BAR region");
p = NULL;
}
return p;
}
/**
* Unmap a PCI bar area.
*/
void qemu_vfio_pci_unmap_bar(QEMUVFIOState *s, int index, void *bar,
uint64_t offset, uint64_t size)
{
if (bar) {
munmap(bar, MIN(size, s->bar_region_info[index].size - offset));
}
}
/**
* Initialize device IRQ with @irq_type and and register an event notifier.
*/
int qemu_vfio_pci_init_irq(QEMUVFIOState *s, EventNotifier *e,
int irq_type, Error **errp)
{
int r;
struct vfio_irq_set *irq_set;
size_t irq_set_size;
struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) };
irq_info.index = irq_type;
if (ioctl(s->device, VFIO_DEVICE_GET_IRQ_INFO, &irq_info)) {
error_setg_errno(errp, errno, "Failed to get device interrupt info");
return -errno;
}
if (!(irq_info.flags & VFIO_IRQ_INFO_EVENTFD)) {
error_setg(errp, "Device interrupt doesn't support eventfd");
return -EINVAL;
}
irq_set_size = sizeof(*irq_set) + sizeof(int);
irq_set = g_malloc0(irq_set_size);
/* Get to a known IRQ state */
*irq_set = (struct vfio_irq_set) {
.argsz = irq_set_size,
.flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER,
.index = irq_info.index,
.start = 0,
.count = 1,
};
*(int *)&irq_set->data = event_notifier_get_fd(e);
r = ioctl(s->device, VFIO_DEVICE_SET_IRQS, irq_set);
g_free(irq_set);
if (r) {
error_setg_errno(errp, errno, "Failed to setup device interrupt");
return -errno;
}
return 0;
}
static int qemu_vfio_pci_read_config(QEMUVFIOState *s, void *buf,
int size, int ofs)
{
int ret;
do {
ret = pread(s->device, buf, size, s->config_region_info.offset + ofs);
} while (ret == -1 && errno == EINTR);
return ret == size ? 0 : -errno;
}
static int qemu_vfio_pci_write_config(QEMUVFIOState *s, void *buf, int size, int ofs)
{
int ret;
do {
ret = pwrite(s->device, buf, size, s->config_region_info.offset + ofs);
} while (ret == -1 && errno == EINTR);
return ret == size ? 0 : -errno;
}
static int qemu_vfio_init_pci(QEMUVFIOState *s, const char *device,
Error **errp)
{
int ret;
int i;
uint16_t pci_cmd;
struct vfio_group_status group_status = { .argsz = sizeof(group_status) };
struct vfio_iommu_type1_info iommu_info = { .argsz = sizeof(iommu_info) };
struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
char *group_file = NULL;
/* Create a new container */
s->container = open("/dev/vfio/vfio", O_RDWR);
if (s->container == -1) {
error_setg_errno(errp, errno, "Failed to open /dev/vfio/vfio");
return -errno;
}
if (ioctl(s->container, VFIO_GET_API_VERSION) != VFIO_API_VERSION) {
error_setg(errp, "Invalid VFIO version");
ret = -EINVAL;
goto fail_container;
}
if (!ioctl(s->container, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU)) {
error_setg_errno(errp, errno, "VFIO IOMMU check failed");
ret = -EINVAL;
goto fail_container;
}
/* Open the group */
group_file = sysfs_find_group_file(device, errp);
if (!group_file) {
ret = -EINVAL;
goto fail_container;
}
s->group = open(group_file, O_RDWR);
if (s->group == -1) {
error_setg_errno(errp, errno, "Failed to open VFIO group file: %s",
group_file);
g_free(group_file);
ret = -errno;
goto fail_container;
}
g_free(group_file);
/* Test the group is viable and available */
if (ioctl(s->group, VFIO_GROUP_GET_STATUS, &group_status)) {
error_setg_errno(errp, errno, "Failed to get VFIO group status");
ret = -errno;
goto fail;
}
if (!(group_status.flags & VFIO_GROUP_FLAGS_VIABLE)) {
error_setg(errp, "VFIO group is not viable");
ret = -EINVAL;
goto fail;
}
/* Add the group to the container */
if (ioctl(s->group, VFIO_GROUP_SET_CONTAINER, &s->container)) {
error_setg_errno(errp, errno, "Failed to add group to VFIO container");
ret = -errno;
goto fail;
}
/* Enable the IOMMU model we want */
if (ioctl(s->container, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU)) {
error_setg_errno(errp, errno, "Failed to set VFIO IOMMU type");
ret = -errno;
goto fail;
}
/* Get additional IOMMU info */
if (ioctl(s->container, VFIO_IOMMU_GET_INFO, &iommu_info)) {
error_setg_errno(errp, errno, "Failed to get IOMMU info");
ret = -errno;
goto fail;
}
s->device = ioctl(s->group, VFIO_GROUP_GET_DEVICE_FD, device);
if (s->device < 0) {
error_setg_errno(errp, errno, "Failed to get device fd");
ret = -errno;
goto fail;
}
/* Test and setup the device */
if (ioctl(s->device, VFIO_DEVICE_GET_INFO, &device_info)) {
error_setg_errno(errp, errno, "Failed to get device info");
ret = -errno;
goto fail;
}
if (device_info.num_regions < VFIO_PCI_CONFIG_REGION_INDEX) {
error_setg(errp, "Invalid device regions");
ret = -EINVAL;
goto fail;
}
s->config_region_info = (struct vfio_region_info) {
.index = VFIO_PCI_CONFIG_REGION_INDEX,
.argsz = sizeof(struct vfio_region_info),
};
if (ioctl(s->device, VFIO_DEVICE_GET_REGION_INFO, &s->config_region_info)) {
error_setg_errno(errp, errno, "Failed to get config region info");
ret = -errno;
goto fail;
}
for (i = 0; i < ARRAY_SIZE(s->bar_region_info); i++) {
ret = qemu_vfio_pci_init_bar(s, i, errp);
if (ret) {
goto fail;
}
}
/* Enable bus master */
ret = qemu_vfio_pci_read_config(s, &pci_cmd, sizeof(pci_cmd), PCI_COMMAND);
if (ret) {
goto fail;
}
pci_cmd |= PCI_COMMAND_MASTER;
ret = qemu_vfio_pci_write_config(s, &pci_cmd, sizeof(pci_cmd), PCI_COMMAND);
if (ret) {
goto fail;
}
return 0;
fail:
close(s->group);
fail_container:
close(s->container);
return ret;
}
static void qemu_vfio_ram_block_added(RAMBlockNotifier *n,
void *host, size_t size)
{
QEMUVFIOState *s = container_of(n, QEMUVFIOState, ram_notifier);
trace_qemu_vfio_ram_block_added(s, host, size);
qemu_vfio_dma_map(s, host, size, false, NULL);
}
static void qemu_vfio_ram_block_removed(RAMBlockNotifier *n,
void *host, size_t size)
{
QEMUVFIOState *s = container_of(n, QEMUVFIOState, ram_notifier);
if (host) {
trace_qemu_vfio_ram_block_removed(s, host, size);
qemu_vfio_dma_unmap(s, host);
}
}
static int qemu_vfio_init_ramblock(RAMBlock *rb, void *opaque)
{
void *host_addr = qemu_ram_get_host_addr(rb);
ram_addr_t length = qemu_ram_get_used_length(rb);
int ret;
QEMUVFIOState *s = opaque;
if (!host_addr) {
return 0;
}
ret = qemu_vfio_dma_map(s, host_addr, length, false, NULL);
if (ret) {
fprintf(stderr, "qemu_vfio_init_ramblock: failed %p %" PRId64 "\n",
host_addr, (uint64_t)length);
}
return 0;
}
static void qemu_vfio_open_common(QEMUVFIOState *s)
{
qemu_mutex_init(&s->lock);
s->ram_notifier.ram_block_added = qemu_vfio_ram_block_added;
s->ram_notifier.ram_block_removed = qemu_vfio_ram_block_removed;
ram_block_notifier_add(&s->ram_notifier);
s->low_water_mark = QEMU_VFIO_IOVA_MIN;
s->high_water_mark = QEMU_VFIO_IOVA_MAX;
qemu_ram_foreach_block(qemu_vfio_init_ramblock, s);
}
/**
* Open a PCI device, e.g. "0000:00:01.0".
*/
QEMUVFIOState *qemu_vfio_open_pci(const char *device, Error **errp)
{
int r;
QEMUVFIOState *s = g_new0(QEMUVFIOState, 1);
r = qemu_vfio_init_pci(s, device, errp);
if (r) {
g_free(s);
return NULL;
}
qemu_vfio_open_common(s);
return s;
}
static void qemu_vfio_dump_mapping(IOVAMapping *m)
{
if (QEMU_VFIO_DEBUG) {
printf(" vfio mapping %p %" PRIx64 " to %" PRIx64 "\n", m->host,
(uint64_t)m->size, (uint64_t)m->iova);
}
}
static void qemu_vfio_dump_mappings(QEMUVFIOState *s)
{
int i;
if (QEMU_VFIO_DEBUG) {
printf("vfio mappings\n");
for (i = 0; i < s->nr_mappings; ++i) {
qemu_vfio_dump_mapping(&s->mappings[i]);
}
}
}
/**
* Find the mapping entry that contains [host, host + size) and set @index to
* the position. If no entry contains it, @index is the position _after_ which
* to insert the new mapping. IOW, it is the index of the largest element that
* is smaller than @host, or -1 if no entry is.
*/
static IOVAMapping *qemu_vfio_find_mapping(QEMUVFIOState *s, void *host,
int *index)
{
IOVAMapping *p = s->mappings;
IOVAMapping *q = p ? p + s->nr_mappings - 1 : NULL;
IOVAMapping *mid;
trace_qemu_vfio_find_mapping(s, host);
if (!p) {
*index = -1;
return NULL;
}
while (true) {
mid = p + (q - p) / 2;
if (mid == p) {
break;
}
if (mid->host > host) {
q = mid;
} else if (mid->host < host) {
p = mid;
} else {
break;
}
}
if (mid->host > host) {
mid--;
} else if (mid < &s->mappings[s->nr_mappings - 1]
&& (mid + 1)->host <= host) {
mid++;
}
*index = mid - &s->mappings[0];
if (mid >= &s->mappings[0] &&
mid->host <= host && mid->host + mid->size > host) {
assert(mid < &s->mappings[s->nr_mappings]);
return mid;
}
/* At this point *index + 1 is the right position to insert the new
* mapping.*/
return NULL;
}
/**
* Allocate IOVA and and create a new mapping record and insert it in @s.
*/
static IOVAMapping *qemu_vfio_add_mapping(QEMUVFIOState *s,
void *host, size_t size,
int index, uint64_t iova)
{
int shift;
IOVAMapping m = {.host = host, .size = size, .iova = iova};
IOVAMapping *insert;
assert(QEMU_IS_ALIGNED(size, getpagesize()));
assert(QEMU_IS_ALIGNED(s->low_water_mark, getpagesize()));
assert(QEMU_IS_ALIGNED(s->high_water_mark, getpagesize()));
trace_qemu_vfio_new_mapping(s, host, size, index, iova);
assert(index >= 0);
s->nr_mappings++;
s->mappings = g_renew(IOVAMapping, s->mappings, s->nr_mappings);
insert = &s->mappings[index];
shift = s->nr_mappings - index - 1;
if (shift) {
memmove(insert + 1, insert, shift * sizeof(s->mappings[0]));
}
*insert = m;
return insert;
}
/* Do the DMA mapping with VFIO. */
static int qemu_vfio_do_mapping(QEMUVFIOState *s, void *host, size_t size,
uint64_t iova)
{
struct vfio_iommu_type1_dma_map dma_map = {
.argsz = sizeof(dma_map),
.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE,
.iova = iova,
.vaddr = (uintptr_t)host,
.size = size,
};
trace_qemu_vfio_do_mapping(s, host, size, iova);
if (ioctl(s->container, VFIO_IOMMU_MAP_DMA, &dma_map)) {
error_report("VFIO_MAP_DMA: %d", -errno);
return -errno;
}
return 0;
}
/**
* Undo the DMA mapping from @s with VFIO, and remove from mapping list.
*/
static void qemu_vfio_undo_mapping(QEMUVFIOState *s, IOVAMapping *mapping,
Error **errp)
{
int index;
struct vfio_iommu_type1_dma_unmap unmap = {
.argsz = sizeof(unmap),
.flags = 0,
.iova = mapping->iova,
.size = mapping->size,
};
index = mapping - s->mappings;
assert(mapping->size > 0);
assert(QEMU_IS_ALIGNED(mapping->size, getpagesize()));
assert(index >= 0 && index < s->nr_mappings);
if (ioctl(s->container, VFIO_IOMMU_UNMAP_DMA, &unmap)) {
error_setg(errp, "VFIO_UNMAP_DMA failed: %d", -errno);
}
memmove(mapping, &s->mappings[index + 1],
sizeof(s->mappings[0]) * (s->nr_mappings - index - 1));
s->nr_mappings--;
s->mappings = g_renew(IOVAMapping, s->mappings, s->nr_mappings);
}
/* Check if the mapping list is (ascending) ordered. */
static bool qemu_vfio_verify_mappings(QEMUVFIOState *s)
{
int i;
if (QEMU_VFIO_DEBUG) {
for (i = 0; i < s->nr_mappings - 1; ++i) {
if (!(s->mappings[i].host < s->mappings[i + 1].host)) {
fprintf(stderr, "item %d not sorted!\n", i);
qemu_vfio_dump_mappings(s);
return false;
}
if (!(s->mappings[i].host + s->mappings[i].size <=
s->mappings[i + 1].host)) {
fprintf(stderr, "item %d overlap with next!\n", i);
qemu_vfio_dump_mappings(s);
return false;
}
}
}
return true;
}
/* Map [host, host + size) area into a contiguous IOVA address space, and store
* the result in @iova if not NULL. The caller need to make sure the area is
* aligned to page size, and mustn't overlap with existing mapping areas (split
* mapping status within this area is not allowed).
*/
int qemu_vfio_dma_map(QEMUVFIOState *s, void *host, size_t size,
bool temporary, uint64_t *iova)
{
int ret = 0;
int index;
IOVAMapping *mapping;
uint64_t iova0;
assert(QEMU_PTR_IS_ALIGNED(host, getpagesize()));
assert(QEMU_IS_ALIGNED(size, getpagesize()));
trace_qemu_vfio_dma_map(s, host, size, temporary, iova);
qemu_mutex_lock(&s->lock);
mapping = qemu_vfio_find_mapping(s, host, &index);
if (mapping) {
iova0 = mapping->iova + ((uint8_t *)host - (uint8_t *)mapping->host);
} else {
if (s->high_water_mark - s->low_water_mark + 1 < size) {
ret = -ENOMEM;
goto out;
}
if (!temporary) {
iova0 = s->low_water_mark;
mapping = qemu_vfio_add_mapping(s, host, size, index + 1, iova0);
if (!mapping) {
ret = -ENOMEM;
goto out;
}
assert(qemu_vfio_verify_mappings(s));
ret = qemu_vfio_do_mapping(s, host, size, iova0);
if (ret) {
qemu_vfio_undo_mapping(s, mapping, NULL);
goto out;
}
s->low_water_mark += size;
qemu_vfio_dump_mappings(s);
} else {
iova0 = s->high_water_mark - size;
ret = qemu_vfio_do_mapping(s, host, size, iova0);
if (ret) {
goto out;
}
s->high_water_mark -= size;
}
}
if (iova) {
*iova = iova0;
}
out:
qemu_mutex_unlock(&s->lock);
return ret;
}
/* Reset the high watermark and free all "temporary" mappings. */
int qemu_vfio_dma_reset_temporary(QEMUVFIOState *s)
{
struct vfio_iommu_type1_dma_unmap unmap = {
.argsz = sizeof(unmap),
.flags = 0,
.iova = s->high_water_mark,
.size = QEMU_VFIO_IOVA_MAX - s->high_water_mark,
};
trace_qemu_vfio_dma_reset_temporary(s);
qemu_mutex_lock(&s->lock);
if (ioctl(s->container, VFIO_IOMMU_UNMAP_DMA, &unmap)) {
error_report("VFIO_UNMAP_DMA: %d", -errno);
qemu_mutex_unlock(&s->lock);
return -errno;
}
s->high_water_mark = QEMU_VFIO_IOVA_MAX;
qemu_mutex_unlock(&s->lock);
return 0;
}
/* Unmapping the whole area that was previously mapped with
* qemu_vfio_dma_map(). */
void qemu_vfio_dma_unmap(QEMUVFIOState *s, void *host)
{
int index = 0;
IOVAMapping *m;
if (!host) {
return;
}
trace_qemu_vfio_dma_unmap(s, host);
qemu_mutex_lock(&s->lock);
m = qemu_vfio_find_mapping(s, host, &index);
if (!m) {
goto out;
}
qemu_vfio_undo_mapping(s, m, NULL);
out:
qemu_mutex_unlock(&s->lock);
}
static void qemu_vfio_reset(QEMUVFIOState *s)
{
ioctl(s->device, VFIO_DEVICE_RESET);
}
/* Close and free the VFIO resources. */
void qemu_vfio_close(QEMUVFIOState *s)
{
int i;
if (!s) {
return;
}
for (i = 0; i < s->nr_mappings; ++i) {
qemu_vfio_undo_mapping(s, &s->mappings[i], NULL);
}
ram_block_notifier_remove(&s->ram_notifier);
qemu_vfio_reset(s);
close(s->device);
close(s->group);
close(s->container);
}
|
pmp-tool/PMP | src/qemu/src-pmp/block/qed-table.c | <filename>src/qemu/src-pmp/block/qed-table.c
/*
* QEMU Enhanced Disk Format Table I/O
*
* Copyright IBM, Corp. 2010
*
* Authors:
* <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU LGPL, version 2 or later.
* See the COPYING.LIB file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "trace.h"
#include "qemu/sockets.h" /* for EINPROGRESS on Windows */
#include "qed.h"
#include "qemu/bswap.h"
/* Called with table_lock held. */
static int qed_read_table(BDRVQEDState *s, uint64_t offset, QEDTable *table)
{
QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(
qiov, table->offsets, s->header.cluster_size * s->header.table_size);
int noffsets;
int i, ret;
trace_qed_read_table(s, offset, table);
qemu_co_mutex_unlock(&s->table_lock);
ret = bdrv_preadv(s->bs->file, offset, &qiov);
qemu_co_mutex_lock(&s->table_lock);
if (ret < 0) {
goto out;
}
/* Byteswap offsets */
noffsets = qiov.size / sizeof(uint64_t);
for (i = 0; i < noffsets; i++) {
table->offsets[i] = le64_to_cpu(table->offsets[i]);
}
ret = 0;
out:
/* Completion */
trace_qed_read_table_cb(s, table, ret);
return ret;
}
/**
* Write out an updated part or all of a table
*
* @s: QED state
* @offset: Offset of table in image file, in bytes
* @table: Table
* @index: Index of first element
* @n: Number of elements
* @flush: Whether or not to sync to disk
*
* Called with table_lock held.
*/
static int qed_write_table(BDRVQEDState *s, uint64_t offset, QEDTable *table,
unsigned int index, unsigned int n, bool flush)
{
unsigned int sector_mask = BDRV_SECTOR_SIZE / sizeof(uint64_t) - 1;
unsigned int start, end, i;
QEDTable *new_table;
QEMUIOVector qiov;
size_t len_bytes;
int ret;
trace_qed_write_table(s, offset, table, index, n);
/* Calculate indices of the first and one after last elements */
start = index & ~sector_mask;
end = (index + n + sector_mask) & ~sector_mask;
len_bytes = (end - start) * sizeof(uint64_t);
new_table = qemu_blockalign(s->bs, len_bytes);
qemu_iovec_init_buf(&qiov, new_table->offsets, len_bytes);
/* Byteswap table */
for (i = start; i < end; i++) {
uint64_t le_offset = cpu_to_le64(table->offsets[i]);
new_table->offsets[i - start] = le_offset;
}
/* Adjust for offset into table */
offset += start * sizeof(uint64_t);
qemu_co_mutex_unlock(&s->table_lock);
ret = bdrv_pwritev(s->bs->file, offset, &qiov);
qemu_co_mutex_lock(&s->table_lock);
trace_qed_write_table_cb(s, table, flush, ret);
if (ret < 0) {
goto out;
}
if (flush) {
ret = bdrv_flush(s->bs);
if (ret < 0) {
goto out;
}
}
ret = 0;
out:
qemu_vfree(new_table);
return ret;
}
int qed_read_l1_table_sync(BDRVQEDState *s)
{
return qed_read_table(s, s->header.l1_table_offset, s->l1_table);
}
/* Called with table_lock held. */
int qed_write_l1_table(BDRVQEDState *s, unsigned int index, unsigned int n)
{
BLKDBG_EVENT(s->bs->file, BLKDBG_L1_UPDATE);
return qed_write_table(s, s->header.l1_table_offset,
s->l1_table, index, n, false);
}
int qed_write_l1_table_sync(BDRVQEDState *s, unsigned int index,
unsigned int n)
{
return qed_write_l1_table(s, index, n);
}
/* Called with table_lock held. */
int qed_read_l2_table(BDRVQEDState *s, QEDRequest *request, uint64_t offset)
{
int ret;
qed_unref_l2_cache_entry(request->l2_table);
/* Check for cached L2 entry */
request->l2_table = qed_find_l2_cache_entry(&s->l2_cache, offset);
if (request->l2_table) {
return 0;
}
request->l2_table = qed_alloc_l2_cache_entry(&s->l2_cache);
request->l2_table->table = qed_alloc_table(s);
BLKDBG_EVENT(s->bs->file, BLKDBG_L2_LOAD);
ret = qed_read_table(s, offset, request->l2_table->table);
if (ret) {
/* can't trust loaded L2 table anymore */
qed_unref_l2_cache_entry(request->l2_table);
request->l2_table = NULL;
} else {
request->l2_table->offset = offset;
qed_commit_l2_cache_entry(&s->l2_cache, request->l2_table);
/* This is guaranteed to succeed because we just committed the entry
* to the cache.
*/
request->l2_table = qed_find_l2_cache_entry(&s->l2_cache, offset);
assert(request->l2_table != NULL);
}
return ret;
}
int qed_read_l2_table_sync(BDRVQEDState *s, QEDRequest *request, uint64_t offset)
{
return qed_read_l2_table(s, request, offset);
}
/* Called with table_lock held. */
int qed_write_l2_table(BDRVQEDState *s, QEDRequest *request,
unsigned int index, unsigned int n, bool flush)
{
BLKDBG_EVENT(s->bs->file, BLKDBG_L2_UPDATE);
return qed_write_table(s, request->l2_table->offset,
request->l2_table->table, index, n, flush);
}
int qed_write_l2_table_sync(BDRVQEDState *s, QEDRequest *request,
unsigned int index, unsigned int n, bool flush)
{
return qed_write_l2_table(s, request, index, n, flush);
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/virtio/vhost.c | <gh_stars>1-10
/*
* vhost support
*
* Copyright Red Hat, Inc. 2010
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/virtio/vhost.h"
#include "hw/hw.h"
#include "qemu/atomic.h"
#include "qemu/range.h"
#include "qemu/error-report.h"
#include "qemu/memfd.h"
#include "standard-headers/linux/vhost_types.h"
#include "exec/address-spaces.h"
#include "hw/virtio/virtio-bus.h"
#include "hw/virtio/virtio-access.h"
#include "migration/blocker.h"
#include "sysemu/dma.h"
#include "trace.h"
/* enabled until disconnected backend stabilizes */
#define _VHOST_DEBUG 1
#ifdef _VHOST_DEBUG
#define VHOST_OPS_DEBUG(fmt, ...) \
do { error_report(fmt ": %s (%d)", ## __VA_ARGS__, \
strerror(errno), errno); } while (0)
#else
#define VHOST_OPS_DEBUG(fmt, ...) \
do { } while (0)
#endif
static struct vhost_log *vhost_log;
static struct vhost_log *vhost_log_shm;
static unsigned int used_memslots;
static QLIST_HEAD(, vhost_dev) vhost_devices =
QLIST_HEAD_INITIALIZER(vhost_devices);
bool vhost_has_free_slot(void)
{
unsigned int slots_limit = ~0U;
struct vhost_dev *hdev;
QLIST_FOREACH(hdev, &vhost_devices, entry) {
unsigned int r = hdev->vhost_ops->vhost_backend_memslots_limit(hdev);
slots_limit = MIN(slots_limit, r);
}
return slots_limit > used_memslots;
}
static void vhost_dev_sync_region(struct vhost_dev *dev,
MemoryRegionSection *section,
uint64_t mfirst, uint64_t mlast,
uint64_t rfirst, uint64_t rlast)
{
vhost_log_chunk_t *log = dev->log->log;
uint64_t start = MAX(mfirst, rfirst);
uint64_t end = MIN(mlast, rlast);
vhost_log_chunk_t *from = log + start / VHOST_LOG_CHUNK;
vhost_log_chunk_t *to = log + end / VHOST_LOG_CHUNK + 1;
uint64_t addr = QEMU_ALIGN_DOWN(start, VHOST_LOG_CHUNK);
if (end < start) {
return;
}
assert(end / VHOST_LOG_CHUNK < dev->log_size);
assert(start / VHOST_LOG_CHUNK < dev->log_size);
for (;from < to; ++from) {
vhost_log_chunk_t log;
/* We first check with non-atomic: much cheaper,
* and we expect non-dirty to be the common case. */
if (!*from) {
addr += VHOST_LOG_CHUNK;
continue;
}
/* Data must be read atomically. We don't really need barrier semantics
* but it's easier to use atomic_* than roll our own. */
log = atomic_xchg(from, 0);
while (log) {
int bit = ctzl(log);
hwaddr page_addr;
hwaddr section_offset;
hwaddr mr_offset;
page_addr = addr + bit * VHOST_LOG_PAGE;
section_offset = page_addr - section->offset_within_address_space;
mr_offset = section_offset + section->offset_within_region;
memory_region_set_dirty(section->mr, mr_offset, VHOST_LOG_PAGE);
log &= ~(0x1ull << bit);
}
addr += VHOST_LOG_CHUNK;
}
}
static int vhost_sync_dirty_bitmap(struct vhost_dev *dev,
MemoryRegionSection *section,
hwaddr first,
hwaddr last)
{
int i;
hwaddr start_addr;
hwaddr end_addr;
if (!dev->log_enabled || !dev->started) {
return 0;
}
start_addr = section->offset_within_address_space;
end_addr = range_get_last(start_addr, int128_get64(section->size));
start_addr = MAX(first, start_addr);
end_addr = MIN(last, end_addr);
for (i = 0; i < dev->mem->nregions; ++i) {
struct vhost_memory_region *reg = dev->mem->regions + i;
vhost_dev_sync_region(dev, section, start_addr, end_addr,
reg->guest_phys_addr,
range_get_last(reg->guest_phys_addr,
reg->memory_size));
}
for (i = 0; i < dev->nvqs; ++i) {
struct vhost_virtqueue *vq = dev->vqs + i;
vhost_dev_sync_region(dev, section, start_addr, end_addr, vq->used_phys,
range_get_last(vq->used_phys, vq->used_size));
}
return 0;
}
static void vhost_log_sync(MemoryListener *listener,
MemoryRegionSection *section)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
vhost_sync_dirty_bitmap(dev, section, 0x0, ~0x0ULL);
}
static void vhost_log_sync_range(struct vhost_dev *dev,
hwaddr first, hwaddr last)
{
int i;
/* FIXME: this is N^2 in number of sections */
for (i = 0; i < dev->n_mem_sections; ++i) {
MemoryRegionSection *section = &dev->mem_sections[i];
vhost_sync_dirty_bitmap(dev, section, first, last);
}
}
static uint64_t vhost_get_log_size(struct vhost_dev *dev)
{
uint64_t log_size = 0;
int i;
for (i = 0; i < dev->mem->nregions; ++i) {
struct vhost_memory_region *reg = dev->mem->regions + i;
uint64_t last = range_get_last(reg->guest_phys_addr,
reg->memory_size);
log_size = MAX(log_size, last / VHOST_LOG_CHUNK + 1);
}
for (i = 0; i < dev->nvqs; ++i) {
struct vhost_virtqueue *vq = dev->vqs + i;
uint64_t last = vq->used_phys + vq->used_size - 1;
log_size = MAX(log_size, last / VHOST_LOG_CHUNK + 1);
}
return log_size;
}
static struct vhost_log *vhost_log_alloc(uint64_t size, bool share)
{
Error *err = NULL;
struct vhost_log *log;
uint64_t logsize = size * sizeof(*(log->log));
int fd = -1;
log = g_new0(struct vhost_log, 1);
if (share) {
log->log = qemu_memfd_alloc("vhost-log", logsize,
F_SEAL_GROW | F_SEAL_SHRINK | F_SEAL_SEAL,
&fd, &err);
if (err) {
error_report_err(err);
g_free(log);
return NULL;
}
memset(log->log, 0, logsize);
} else {
log->log = g_malloc0(logsize);
}
log->size = size;
log->refcnt = 1;
log->fd = fd;
return log;
}
static struct vhost_log *vhost_log_get(uint64_t size, bool share)
{
struct vhost_log *log = share ? vhost_log_shm : vhost_log;
if (!log || log->size != size) {
log = vhost_log_alloc(size, share);
if (share) {
vhost_log_shm = log;
} else {
vhost_log = log;
}
} else {
++log->refcnt;
}
return log;
}
static void vhost_log_put(struct vhost_dev *dev, bool sync)
{
struct vhost_log *log = dev->log;
if (!log) {
return;
}
--log->refcnt;
if (log->refcnt == 0) {
/* Sync only the range covered by the old log */
if (dev->log_size && sync) {
vhost_log_sync_range(dev, 0, dev->log_size * VHOST_LOG_CHUNK - 1);
}
if (vhost_log == log) {
g_free(log->log);
vhost_log = NULL;
} else if (vhost_log_shm == log) {
qemu_memfd_free(log->log, log->size * sizeof(*(log->log)),
log->fd);
vhost_log_shm = NULL;
}
g_free(log);
}
dev->log = NULL;
dev->log_size = 0;
}
static bool vhost_dev_log_is_shared(struct vhost_dev *dev)
{
return dev->vhost_ops->vhost_requires_shm_log &&
dev->vhost_ops->vhost_requires_shm_log(dev);
}
static inline void vhost_dev_log_resize(struct vhost_dev *dev, uint64_t size)
{
struct vhost_log *log = vhost_log_get(size, vhost_dev_log_is_shared(dev));
uint64_t log_base = (uintptr_t)log->log;
int r;
/* inform backend of log switching, this must be done before
releasing the current log, to ensure no logging is lost */
r = dev->vhost_ops->vhost_set_log_base(dev, log_base, log);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_log_base failed");
}
vhost_log_put(dev, true);
dev->log = log;
dev->log_size = size;
}
static int vhost_dev_has_iommu(struct vhost_dev *dev)
{
VirtIODevice *vdev = dev->vdev;
return virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM);
}
static void *vhost_memory_map(struct vhost_dev *dev, hwaddr addr,
hwaddr *plen, int is_write)
{
if (!vhost_dev_has_iommu(dev)) {
return cpu_physical_memory_map(addr, plen, is_write);
} else {
return (void *)(uintptr_t)addr;
}
}
static void vhost_memory_unmap(struct vhost_dev *dev, void *buffer,
hwaddr len, int is_write,
hwaddr access_len)
{
if (!vhost_dev_has_iommu(dev)) {
cpu_physical_memory_unmap(buffer, len, is_write, access_len);
}
}
static int vhost_verify_ring_part_mapping(void *ring_hva,
uint64_t ring_gpa,
uint64_t ring_size,
void *reg_hva,
uint64_t reg_gpa,
uint64_t reg_size)
{
uint64_t hva_ring_offset;
uint64_t ring_last = range_get_last(ring_gpa, ring_size);
uint64_t reg_last = range_get_last(reg_gpa, reg_size);
if (ring_last < reg_gpa || ring_gpa > reg_last) {
return 0;
}
/* check that whole ring's is mapped */
if (ring_last > reg_last) {
return -ENOMEM;
}
/* check that ring's MemoryRegion wasn't replaced */
hva_ring_offset = ring_gpa - reg_gpa;
if (ring_hva != reg_hva + hva_ring_offset) {
return -EBUSY;
}
return 0;
}
static int vhost_verify_ring_mappings(struct vhost_dev *dev,
void *reg_hva,
uint64_t reg_gpa,
uint64_t reg_size)
{
int i, j;
int r = 0;
const char *part_name[] = {
"descriptor table",
"available ring",
"used ring"
};
if (vhost_dev_has_iommu(dev)) {
return 0;
}
for (i = 0; i < dev->nvqs; ++i) {
struct vhost_virtqueue *vq = dev->vqs + i;
if (vq->desc_phys == 0) {
continue;
}
j = 0;
r = vhost_verify_ring_part_mapping(
vq->desc, vq->desc_phys, vq->desc_size,
reg_hva, reg_gpa, reg_size);
if (r) {
break;
}
j++;
r = vhost_verify_ring_part_mapping(
vq->avail, vq->avail_phys, vq->avail_size,
reg_hva, reg_gpa, reg_size);
if (r) {
break;
}
j++;
r = vhost_verify_ring_part_mapping(
vq->used, vq->used_phys, vq->used_size,
reg_hva, reg_gpa, reg_size);
if (r) {
break;
}
}
if (r == -ENOMEM) {
error_report("Unable to map %s for ring %d", part_name[j], i);
} else if (r == -EBUSY) {
error_report("%s relocated for ring %d", part_name[j], i);
}
return r;
}
static bool vhost_section(struct vhost_dev *dev, MemoryRegionSection *section)
{
bool result;
bool log_dirty = memory_region_get_dirty_log_mask(section->mr) &
~(1 << DIRTY_MEMORY_MIGRATION);
result = memory_region_is_ram(section->mr) &&
!memory_region_is_rom(section->mr);
/* Vhost doesn't handle any block which is doing dirty-tracking other
* than migration; this typically fires on VGA areas.
*/
result &= !log_dirty;
if (result && dev->vhost_ops->vhost_backend_mem_section_filter) {
result &=
dev->vhost_ops->vhost_backend_mem_section_filter(dev, section);
}
trace_vhost_section(section->mr->name, result);
return result;
}
static void vhost_begin(MemoryListener *listener)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
dev->tmp_sections = NULL;
dev->n_tmp_sections = 0;
}
static void vhost_commit(MemoryListener *listener)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
MemoryRegionSection *old_sections;
int n_old_sections;
uint64_t log_size;
size_t regions_size;
int r;
int i;
bool changed = false;
/* Note we can be called before the device is started, but then
* starting the device calls set_mem_table, so we need to have
* built the data structures.
*/
old_sections = dev->mem_sections;
n_old_sections = dev->n_mem_sections;
dev->mem_sections = dev->tmp_sections;
dev->n_mem_sections = dev->n_tmp_sections;
if (dev->n_mem_sections != n_old_sections) {
changed = true;
} else {
/* Same size, lets check the contents */
changed = n_old_sections && memcmp(dev->mem_sections, old_sections,
n_old_sections * sizeof(old_sections[0])) != 0;
}
trace_vhost_commit(dev->started, changed);
if (!changed) {
goto out;
}
/* Rebuild the regions list from the new sections list */
regions_size = offsetof(struct vhost_memory, regions) +
dev->n_mem_sections * sizeof dev->mem->regions[0];
dev->mem = g_realloc(dev->mem, regions_size);
dev->mem->nregions = dev->n_mem_sections;
used_memslots = dev->mem->nregions;
for (i = 0; i < dev->n_mem_sections; i++) {
struct vhost_memory_region *cur_vmr = dev->mem->regions + i;
struct MemoryRegionSection *mrs = dev->mem_sections + i;
cur_vmr->guest_phys_addr = mrs->offset_within_address_space;
cur_vmr->memory_size = int128_get64(mrs->size);
cur_vmr->userspace_addr =
(uintptr_t)memory_region_get_ram_ptr(mrs->mr) +
mrs->offset_within_region;
cur_vmr->flags_padding = 0;
}
if (!dev->started) {
goto out;
}
for (i = 0; i < dev->mem->nregions; i++) {
if (vhost_verify_ring_mappings(dev,
(void *)(uintptr_t)dev->mem->regions[i].userspace_addr,
dev->mem->regions[i].guest_phys_addr,
dev->mem->regions[i].memory_size)) {
error_report("Verify ring failure on region %d", i);
abort();
}
}
if (!dev->log_enabled) {
r = dev->vhost_ops->vhost_set_mem_table(dev, dev->mem);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_mem_table failed");
}
goto out;
}
log_size = vhost_get_log_size(dev);
/* We allocate an extra 4K bytes to log,
* to reduce the * number of reallocations. */
#define VHOST_LOG_BUFFER (0x1000 / sizeof *dev->log)
/* To log more, must increase log size before table update. */
if (dev->log_size < log_size) {
vhost_dev_log_resize(dev, log_size + VHOST_LOG_BUFFER);
}
r = dev->vhost_ops->vhost_set_mem_table(dev, dev->mem);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_mem_table failed");
}
/* To log less, can only decrease log size after table update. */
if (dev->log_size > log_size + VHOST_LOG_BUFFER) {
vhost_dev_log_resize(dev, log_size);
}
out:
/* Deref the old list of sections, this must happen _after_ the
* vhost_set_mem_table to ensure the client isn't still using the
* section we're about to unref.
*/
while (n_old_sections--) {
memory_region_unref(old_sections[n_old_sections].mr);
}
g_free(old_sections);
return;
}
/* Adds the section data to the tmp_section structure.
* It relies on the listener calling us in memory address order
* and for each region (via the _add and _nop methods) to
* join neighbours.
*/
static void vhost_region_add_section(struct vhost_dev *dev,
MemoryRegionSection *section)
{
bool need_add = true;
uint64_t mrs_size = int128_get64(section->size);
uint64_t mrs_gpa = section->offset_within_address_space;
uintptr_t mrs_host = (uintptr_t)memory_region_get_ram_ptr(section->mr) +
section->offset_within_region;
RAMBlock *mrs_rb = section->mr->ram_block;
size_t mrs_page = qemu_ram_pagesize(mrs_rb);
trace_vhost_region_add_section(section->mr->name, mrs_gpa, mrs_size,
mrs_host);
/* Round the section to it's page size */
/* First align the start down to a page boundary */
uint64_t alignage = mrs_host & (mrs_page - 1);
if (alignage) {
mrs_host -= alignage;
mrs_size += alignage;
mrs_gpa -= alignage;
}
/* Now align the size up to a page boundary */
alignage = mrs_size & (mrs_page - 1);
if (alignage) {
mrs_size += mrs_page - alignage;
}
trace_vhost_region_add_section_aligned(section->mr->name, mrs_gpa, mrs_size,
mrs_host);
if (dev->n_tmp_sections) {
/* Since we already have at least one section, lets see if
* this extends it; since we're scanning in order, we only
* have to look at the last one, and the FlatView that calls
* us shouldn't have overlaps.
*/
MemoryRegionSection *prev_sec = dev->tmp_sections +
(dev->n_tmp_sections - 1);
uint64_t prev_gpa_start = prev_sec->offset_within_address_space;
uint64_t prev_size = int128_get64(prev_sec->size);
uint64_t prev_gpa_end = range_get_last(prev_gpa_start, prev_size);
uint64_t prev_host_start =
(uintptr_t)memory_region_get_ram_ptr(prev_sec->mr) +
prev_sec->offset_within_region;
uint64_t prev_host_end = range_get_last(prev_host_start, prev_size);
if (mrs_gpa <= (prev_gpa_end + 1)) {
/* OK, looks like overlapping/intersecting - it's possible that
* the rounding to page sizes has made them overlap, but they should
* match up in the same RAMBlock if they do.
*/
if (mrs_gpa < prev_gpa_start) {
error_report("%s:Section rounded to %"PRIx64
" prior to previous %"PRIx64,
__func__, mrs_gpa, prev_gpa_start);
/* A way to cleanly fail here would be better */
return;
}
/* Offset from the start of the previous GPA to this GPA */
size_t offset = mrs_gpa - prev_gpa_start;
if (prev_host_start + offset == mrs_host &&
section->mr == prev_sec->mr &&
(!dev->vhost_ops->vhost_backend_can_merge ||
dev->vhost_ops->vhost_backend_can_merge(dev,
mrs_host, mrs_size,
prev_host_start, prev_size))) {
uint64_t max_end = MAX(prev_host_end, mrs_host + mrs_size);
need_add = false;
prev_sec->offset_within_address_space =
MIN(prev_gpa_start, mrs_gpa);
prev_sec->offset_within_region =
MIN(prev_host_start, mrs_host) -
(uintptr_t)memory_region_get_ram_ptr(prev_sec->mr);
prev_sec->size = int128_make64(max_end - MIN(prev_host_start,
mrs_host));
trace_vhost_region_add_section_merge(section->mr->name,
int128_get64(prev_sec->size),
prev_sec->offset_within_address_space,
prev_sec->offset_within_region);
} else {
/* adjoining regions are fine, but overlapping ones with
* different blocks/offsets shouldn't happen
*/
if (mrs_gpa != prev_gpa_end + 1) {
error_report("%s: Overlapping but not coherent sections "
"at %"PRIx64,
__func__, mrs_gpa);
return;
}
}
}
}
if (need_add) {
++dev->n_tmp_sections;
dev->tmp_sections = g_renew(MemoryRegionSection, dev->tmp_sections,
dev->n_tmp_sections);
dev->tmp_sections[dev->n_tmp_sections - 1] = *section;
/* The flatview isn't stable and we don't use it, making it NULL
* means we can memcmp the list.
*/
dev->tmp_sections[dev->n_tmp_sections - 1].fv = NULL;
memory_region_ref(section->mr);
}
}
/* Used for both add and nop callbacks */
static void vhost_region_addnop(MemoryListener *listener,
MemoryRegionSection *section)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
if (!vhost_section(dev, section)) {
return;
}
vhost_region_add_section(dev, section);
}
static void vhost_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
{
struct vhost_iommu *iommu = container_of(n, struct vhost_iommu, n);
struct vhost_dev *hdev = iommu->hdev;
hwaddr iova = iotlb->iova + iommu->iommu_offset;
if (vhost_backend_invalidate_device_iotlb(hdev, iova,
iotlb->addr_mask + 1)) {
error_report("Fail to invalidate device iotlb");
}
}
static void vhost_iommu_region_add(MemoryListener *listener,
MemoryRegionSection *section)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
iommu_listener);
struct vhost_iommu *iommu;
Int128 end;
int iommu_idx;
IOMMUMemoryRegion *iommu_mr;
if (!memory_region_is_iommu(section->mr)) {
return;
}
iommu_mr = IOMMU_MEMORY_REGION(section->mr);
iommu = g_malloc0(sizeof(*iommu));
end = int128_add(int128_make64(section->offset_within_region),
section->size);
end = int128_sub(end, int128_one());
iommu_idx = memory_region_iommu_attrs_to_index(iommu_mr,
MEMTXATTRS_UNSPECIFIED);
iommu_notifier_init(&iommu->n, vhost_iommu_unmap_notify,
IOMMU_NOTIFIER_UNMAP,
section->offset_within_region,
int128_get64(end),
iommu_idx);
iommu->mr = section->mr;
iommu->iommu_offset = section->offset_within_address_space -
section->offset_within_region;
iommu->hdev = dev;
memory_region_register_iommu_notifier(section->mr, &iommu->n);
QLIST_INSERT_HEAD(&dev->iommu_list, iommu, iommu_next);
/* TODO: can replay help performance here? */
}
static void vhost_iommu_region_del(MemoryListener *listener,
MemoryRegionSection *section)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
iommu_listener);
struct vhost_iommu *iommu;
if (!memory_region_is_iommu(section->mr)) {
return;
}
QLIST_FOREACH(iommu, &dev->iommu_list, iommu_next) {
if (iommu->mr == section->mr &&
iommu->n.start == section->offset_within_region) {
memory_region_unregister_iommu_notifier(iommu->mr,
&iommu->n);
QLIST_REMOVE(iommu, iommu_next);
g_free(iommu);
break;
}
}
}
static int vhost_virtqueue_set_addr(struct vhost_dev *dev,
struct vhost_virtqueue *vq,
unsigned idx, bool enable_log)
{
struct vhost_vring_addr addr = {
.index = idx,
.desc_user_addr = (uint64_t)(unsigned long)vq->desc,
.avail_user_addr = (uint64_t)(unsigned long)vq->avail,
.used_user_addr = (uint64_t)(unsigned long)vq->used,
.log_guest_addr = vq->used_phys,
.flags = enable_log ? (1 << VHOST_VRING_F_LOG) : 0,
};
int r = dev->vhost_ops->vhost_set_vring_addr(dev, &addr);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_vring_addr failed");
return -errno;
}
return 0;
}
static int vhost_dev_set_features(struct vhost_dev *dev,
bool enable_log)
{
uint64_t features = dev->acked_features;
int r;
if (enable_log) {
features |= 0x1ULL << VHOST_F_LOG_ALL;
}
r = dev->vhost_ops->vhost_set_features(dev, features);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_features failed");
}
return r < 0 ? -errno : 0;
}
static int vhost_dev_set_log(struct vhost_dev *dev, bool enable_log)
{
int r, i, idx;
r = vhost_dev_set_features(dev, enable_log);
if (r < 0) {
goto err_features;
}
for (i = 0; i < dev->nvqs; ++i) {
idx = dev->vhost_ops->vhost_get_vq_index(dev, dev->vq_index + i);
r = vhost_virtqueue_set_addr(dev, dev->vqs + i, idx,
enable_log);
if (r < 0) {
goto err_vq;
}
}
return 0;
err_vq:
for (; i >= 0; --i) {
idx = dev->vhost_ops->vhost_get_vq_index(dev, dev->vq_index + i);
vhost_virtqueue_set_addr(dev, dev->vqs + i, idx,
dev->log_enabled);
}
vhost_dev_set_features(dev, dev->log_enabled);
err_features:
return r;
}
static int vhost_migration_log(MemoryListener *listener, int enable)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
int r;
if (!!enable == dev->log_enabled) {
return 0;
}
if (!dev->started) {
dev->log_enabled = enable;
return 0;
}
if (!enable) {
r = vhost_dev_set_log(dev, false);
if (r < 0) {
return r;
}
vhost_log_put(dev, false);
} else {
vhost_dev_log_resize(dev, vhost_get_log_size(dev));
r = vhost_dev_set_log(dev, true);
if (r < 0) {
return r;
}
}
dev->log_enabled = enable;
return 0;
}
static void vhost_log_global_start(MemoryListener *listener)
{
int r;
r = vhost_migration_log(listener, true);
if (r < 0) {
abort();
}
}
static void vhost_log_global_stop(MemoryListener *listener)
{
int r;
r = vhost_migration_log(listener, false);
if (r < 0) {
abort();
}
}
static void vhost_log_start(MemoryListener *listener,
MemoryRegionSection *section,
int old, int new)
{
/* FIXME: implement */
}
static void vhost_log_stop(MemoryListener *listener,
MemoryRegionSection *section,
int old, int new)
{
/* FIXME: implement */
}
/* The vhost driver natively knows how to handle the vrings of non
* cross-endian legacy devices and modern devices. Only legacy devices
* exposed to a bi-endian guest may require the vhost driver to use a
* specific endianness.
*/
static inline bool vhost_needs_vring_endian(VirtIODevice *vdev)
{
if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
return false;
}
#ifdef HOST_WORDS_BIGENDIAN
return vdev->device_endian == VIRTIO_DEVICE_ENDIAN_LITTLE;
#else
return vdev->device_endian == VIRTIO_DEVICE_ENDIAN_BIG;
#endif
}
static int vhost_virtqueue_set_vring_endian_legacy(struct vhost_dev *dev,
bool is_big_endian,
int vhost_vq_index)
{
struct vhost_vring_state s = {
.index = vhost_vq_index,
.num = is_big_endian
};
if (!dev->vhost_ops->vhost_set_vring_endian(dev, &s)) {
return 0;
}
VHOST_OPS_DEBUG("vhost_set_vring_endian failed");
if (errno == ENOTTY) {
error_report("vhost does not support cross-endian");
return -ENOSYS;
}
return -errno;
}
static int vhost_memory_region_lookup(struct vhost_dev *hdev,
uint64_t gpa, uint64_t *uaddr,
uint64_t *len)
{
int i;
for (i = 0; i < hdev->mem->nregions; i++) {
struct vhost_memory_region *reg = hdev->mem->regions + i;
if (gpa >= reg->guest_phys_addr &&
reg->guest_phys_addr + reg->memory_size > gpa) {
*uaddr = reg->userspace_addr + gpa - reg->guest_phys_addr;
*len = reg->guest_phys_addr + reg->memory_size - gpa;
return 0;
}
}
return -EFAULT;
}
int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
{
IOMMUTLBEntry iotlb;
uint64_t uaddr, len;
int ret = -EFAULT;
rcu_read_lock();
trace_vhost_iotlb_miss(dev, 1);
iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
iova, write,
MEMTXATTRS_UNSPECIFIED);
if (iotlb.target_as != NULL) {
ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
&uaddr, &len);
if (ret) {
trace_vhost_iotlb_miss(dev, 3);
error_report("Fail to lookup the translated address "
"%"PRIx64, iotlb.translated_addr);
goto out;
}
len = MIN(iotlb.addr_mask + 1, len);
iova = iova & ~iotlb.addr_mask;
ret = vhost_backend_update_device_iotlb(dev, iova, uaddr,
len, iotlb.perm);
if (ret) {
trace_vhost_iotlb_miss(dev, 4);
error_report("Fail to update device iotlb");
goto out;
}
}
trace_vhost_iotlb_miss(dev, 2);
out:
rcu_read_unlock();
return ret;
}
static int vhost_virtqueue_start(struct vhost_dev *dev,
struct VirtIODevice *vdev,
struct vhost_virtqueue *vq,
unsigned idx)
{
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
VirtioBusState *vbus = VIRTIO_BUS(qbus);
VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(vbus);
hwaddr s, l, a;
int r;
int vhost_vq_index = dev->vhost_ops->vhost_get_vq_index(dev, idx);
struct vhost_vring_file file = {
.index = vhost_vq_index
};
struct vhost_vring_state state = {
.index = vhost_vq_index
};
struct VirtQueue *vvq = virtio_get_queue(vdev, idx);
a = virtio_queue_get_desc_addr(vdev, idx);
if (a == 0) {
/* Queue might not be ready for start */
return 0;
}
vq->num = state.num = virtio_queue_get_num(vdev, idx);
r = dev->vhost_ops->vhost_set_vring_num(dev, &state);
if (r) {
VHOST_OPS_DEBUG("vhost_set_vring_num failed");
return -errno;
}
state.num = virtio_queue_get_last_avail_idx(vdev, idx);
r = dev->vhost_ops->vhost_set_vring_base(dev, &state);
if (r) {
VHOST_OPS_DEBUG("vhost_set_vring_base failed");
return -errno;
}
if (vhost_needs_vring_endian(vdev)) {
r = vhost_virtqueue_set_vring_endian_legacy(dev,
virtio_is_big_endian(vdev),
vhost_vq_index);
if (r) {
return -errno;
}
}
vq->desc_size = s = l = virtio_queue_get_desc_size(vdev, idx);
vq->desc_phys = a;
vq->desc = vhost_memory_map(dev, a, &l, 0);
if (!vq->desc || l != s) {
r = -ENOMEM;
goto fail_alloc_desc;
}
vq->avail_size = s = l = virtio_queue_get_avail_size(vdev, idx);
vq->avail_phys = a = virtio_queue_get_avail_addr(vdev, idx);
vq->avail = vhost_memory_map(dev, a, &l, 0);
if (!vq->avail || l != s) {
r = -ENOMEM;
goto fail_alloc_avail;
}
vq->used_size = s = l = virtio_queue_get_used_size(vdev, idx);
vq->used_phys = a = virtio_queue_get_used_addr(vdev, idx);
vq->used = vhost_memory_map(dev, a, &l, 1);
if (!vq->used || l != s) {
r = -ENOMEM;
goto fail_alloc_used;
}
r = vhost_virtqueue_set_addr(dev, vq, vhost_vq_index, dev->log_enabled);
if (r < 0) {
r = -errno;
goto fail_alloc;
}
file.fd = event_notifier_get_fd(virtio_queue_get_host_notifier(vvq));
r = dev->vhost_ops->vhost_set_vring_kick(dev, &file);
if (r) {
VHOST_OPS_DEBUG("vhost_set_vring_kick failed");
r = -errno;
goto fail_kick;
}
/* Clear and discard previous events if any. */
event_notifier_test_and_clear(&vq->masked_notifier);
/* Init vring in unmasked state, unless guest_notifier_mask
* will do it later.
*/
if (!vdev->use_guest_notifier_mask) {
/* TODO: check and handle errors. */
vhost_virtqueue_mask(dev, vdev, idx, false);
}
if (k->query_guest_notifiers &&
k->query_guest_notifiers(qbus->parent) &&
virtio_queue_vector(vdev, idx) == VIRTIO_NO_VECTOR) {
file.fd = -1;
r = dev->vhost_ops->vhost_set_vring_call(dev, &file);
if (r) {
goto fail_vector;
}
}
return 0;
fail_vector:
fail_kick:
fail_alloc:
vhost_memory_unmap(dev, vq->used, virtio_queue_get_used_size(vdev, idx),
0, 0);
fail_alloc_used:
vhost_memory_unmap(dev, vq->avail, virtio_queue_get_avail_size(vdev, idx),
0, 0);
fail_alloc_avail:
vhost_memory_unmap(dev, vq->desc, virtio_queue_get_desc_size(vdev, idx),
0, 0);
fail_alloc_desc:
return r;
}
static void vhost_virtqueue_stop(struct vhost_dev *dev,
struct VirtIODevice *vdev,
struct vhost_virtqueue *vq,
unsigned idx)
{
int vhost_vq_index = dev->vhost_ops->vhost_get_vq_index(dev, idx);
struct vhost_vring_state state = {
.index = vhost_vq_index,
};
int r;
if (virtio_queue_get_desc_addr(vdev, idx) == 0) {
/* Don't stop the virtqueue which might have not been started */
return;
}
r = dev->vhost_ops->vhost_get_vring_base(dev, &state);
if (r < 0) {
VHOST_OPS_DEBUG("vhost VQ %d ring restore failed: %d", idx, r);
/* Connection to the backend is broken, so let's sync internal
* last avail idx to the device used idx.
*/
virtio_queue_restore_last_avail_idx(vdev, idx);
} else {
virtio_queue_set_last_avail_idx(vdev, idx, state.num);
}
virtio_queue_invalidate_signalled_used(vdev, idx);
virtio_queue_update_used_idx(vdev, idx);
/* In the cross-endian case, we need to reset the vring endianness to
* native as legacy devices expect so by default.
*/
if (vhost_needs_vring_endian(vdev)) {
vhost_virtqueue_set_vring_endian_legacy(dev,
!virtio_is_big_endian(vdev),
vhost_vq_index);
}
vhost_memory_unmap(dev, vq->used, virtio_queue_get_used_size(vdev, idx),
1, virtio_queue_get_used_size(vdev, idx));
vhost_memory_unmap(dev, vq->avail, virtio_queue_get_avail_size(vdev, idx),
0, virtio_queue_get_avail_size(vdev, idx));
vhost_memory_unmap(dev, vq->desc, virtio_queue_get_desc_size(vdev, idx),
0, virtio_queue_get_desc_size(vdev, idx));
}
static void vhost_eventfd_add(MemoryListener *listener,
MemoryRegionSection *section,
bool match_data, uint64_t data, EventNotifier *e)
{
}
static void vhost_eventfd_del(MemoryListener *listener,
MemoryRegionSection *section,
bool match_data, uint64_t data, EventNotifier *e)
{
}
static int vhost_virtqueue_set_busyloop_timeout(struct vhost_dev *dev,
int n, uint32_t timeout)
{
int vhost_vq_index = dev->vhost_ops->vhost_get_vq_index(dev, n);
struct vhost_vring_state state = {
.index = vhost_vq_index,
.num = timeout,
};
int r;
if (!dev->vhost_ops->vhost_set_vring_busyloop_timeout) {
return -EINVAL;
}
r = dev->vhost_ops->vhost_set_vring_busyloop_timeout(dev, &state);
if (r) {
VHOST_OPS_DEBUG("vhost_set_vring_busyloop_timeout failed");
return r;
}
return 0;
}
static int vhost_virtqueue_init(struct vhost_dev *dev,
struct vhost_virtqueue *vq, int n)
{
int vhost_vq_index = dev->vhost_ops->vhost_get_vq_index(dev, n);
struct vhost_vring_file file = {
.index = vhost_vq_index,
};
int r = event_notifier_init(&vq->masked_notifier, 0);
if (r < 0) {
return r;
}
file.fd = event_notifier_get_fd(&vq->masked_notifier);
r = dev->vhost_ops->vhost_set_vring_call(dev, &file);
if (r) {
VHOST_OPS_DEBUG("vhost_set_vring_call failed");
r = -errno;
goto fail_call;
}
vq->dev = dev;
return 0;
fail_call:
event_notifier_cleanup(&vq->masked_notifier);
return r;
}
static void vhost_virtqueue_cleanup(struct vhost_virtqueue *vq)
{
event_notifier_cleanup(&vq->masked_notifier);
}
int vhost_dev_init(struct vhost_dev *hdev, void *opaque,
VhostBackendType backend_type, uint32_t busyloop_timeout)
{
uint64_t features;
int i, r, n_initialized_vqs = 0;
Error *local_err = NULL;
hdev->vdev = NULL;
hdev->migration_blocker = NULL;
r = vhost_set_backend_type(hdev, backend_type);
assert(r >= 0);
r = hdev->vhost_ops->vhost_backend_init(hdev, opaque);
if (r < 0) {
goto fail;
}
r = hdev->vhost_ops->vhost_set_owner(hdev);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_owner failed");
goto fail;
}
r = hdev->vhost_ops->vhost_get_features(hdev, &features);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_get_features failed");
goto fail;
}
for (i = 0; i < hdev->nvqs; ++i, ++n_initialized_vqs) {
r = vhost_virtqueue_init(hdev, hdev->vqs + i, hdev->vq_index + i);
if (r < 0) {
goto fail;
}
}
if (busyloop_timeout) {
for (i = 0; i < hdev->nvqs; ++i) {
r = vhost_virtqueue_set_busyloop_timeout(hdev, hdev->vq_index + i,
busyloop_timeout);
if (r < 0) {
goto fail_busyloop;
}
}
}
hdev->features = features;
hdev->memory_listener = (MemoryListener) {
.begin = vhost_begin,
.commit = vhost_commit,
.region_add = vhost_region_addnop,
.region_nop = vhost_region_addnop,
.log_start = vhost_log_start,
.log_stop = vhost_log_stop,
.log_sync = vhost_log_sync,
.log_global_start = vhost_log_global_start,
.log_global_stop = vhost_log_global_stop,
.eventfd_add = vhost_eventfd_add,
.eventfd_del = vhost_eventfd_del,
.priority = 10
};
hdev->iommu_listener = (MemoryListener) {
.region_add = vhost_iommu_region_add,
.region_del = vhost_iommu_region_del,
};
if (hdev->migration_blocker == NULL) {
if (!(hdev->features & (0x1ULL << VHOST_F_LOG_ALL))) {
error_setg(&hdev->migration_blocker,
"Migration disabled: vhost lacks VHOST_F_LOG_ALL feature.");
} else if (vhost_dev_log_is_shared(hdev) && !qemu_memfd_alloc_check()) {
error_setg(&hdev->migration_blocker,
"Migration disabled: failed to allocate shared memory");
}
}
if (hdev->migration_blocker != NULL) {
r = migrate_add_blocker(hdev->migration_blocker, &local_err);
if (local_err) {
error_report_err(local_err);
error_free(hdev->migration_blocker);
goto fail_busyloop;
}
}
hdev->mem = g_malloc0(offsetof(struct vhost_memory, regions));
hdev->n_mem_sections = 0;
hdev->mem_sections = NULL;
hdev->log = NULL;
hdev->log_size = 0;
hdev->log_enabled = false;
hdev->started = false;
memory_listener_register(&hdev->memory_listener, &address_space_memory);
QLIST_INSERT_HEAD(&vhost_devices, hdev, entry);
if (used_memslots > hdev->vhost_ops->vhost_backend_memslots_limit(hdev)) {
error_report("vhost backend memory slots limit is less"
" than current number of present memory slots");
r = -1;
if (busyloop_timeout) {
goto fail_busyloop;
} else {
goto fail;
}
}
return 0;
fail_busyloop:
while (--i >= 0) {
vhost_virtqueue_set_busyloop_timeout(hdev, hdev->vq_index + i, 0);
}
fail:
hdev->nvqs = n_initialized_vqs;
vhost_dev_cleanup(hdev);
return r;
}
void vhost_dev_cleanup(struct vhost_dev *hdev)
{
int i;
for (i = 0; i < hdev->nvqs; ++i) {
vhost_virtqueue_cleanup(hdev->vqs + i);
}
if (hdev->mem) {
/* those are only safe after successful init */
memory_listener_unregister(&hdev->memory_listener);
QLIST_REMOVE(hdev, entry);
}
if (hdev->migration_blocker) {
migrate_del_blocker(hdev->migration_blocker);
error_free(hdev->migration_blocker);
}
g_free(hdev->mem);
g_free(hdev->mem_sections);
if (hdev->vhost_ops) {
hdev->vhost_ops->vhost_backend_cleanup(hdev);
}
assert(!hdev->log);
memset(hdev, 0, sizeof(struct vhost_dev));
}
/* Stop processing guest IO notifications in qemu.
* Start processing them in vhost in kernel.
*/
int vhost_dev_enable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev)
{
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
int i, r, e;
/* We will pass the notifiers to the kernel, make sure that QEMU
* doesn't interfere.
*/
r = virtio_device_grab_ioeventfd(vdev);
if (r < 0) {
error_report("binding does not support host notifiers");
goto fail;
}
for (i = 0; i < hdev->nvqs; ++i) {
r = virtio_bus_set_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + i,
true);
if (r < 0) {
error_report("vhost VQ %d notifier binding failed: %d", i, -r);
goto fail_vq;
}
}
return 0;
fail_vq:
while (--i >= 0) {
e = virtio_bus_set_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + i,
false);
if (e < 0) {
error_report("vhost VQ %d notifier cleanup error: %d", i, -r);
}
assert (e >= 0);
virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + i);
}
virtio_device_release_ioeventfd(vdev);
fail:
return r;
}
/* Stop processing guest IO notifications in vhost.
* Start processing them in qemu.
* This might actually run the qemu handlers right away,
* so virtio in qemu must be completely setup when this is called.
*/
void vhost_dev_disable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev)
{
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
int i, r;
for (i = 0; i < hdev->nvqs; ++i) {
r = virtio_bus_set_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + i,
false);
if (r < 0) {
error_report("vhost VQ %d notifier cleanup failed: %d", i, -r);
}
assert (r >= 0);
virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + i);
}
virtio_device_release_ioeventfd(vdev);
}
/* Test and clear event pending status.
* Should be called after unmask to avoid losing events.
*/
bool vhost_virtqueue_pending(struct vhost_dev *hdev, int n)
{
struct vhost_virtqueue *vq = hdev->vqs + n - hdev->vq_index;
assert(n >= hdev->vq_index && n < hdev->vq_index + hdev->nvqs);
return event_notifier_test_and_clear(&vq->masked_notifier);
}
/* Mask/unmask events from this vq. */
void vhost_virtqueue_mask(struct vhost_dev *hdev, VirtIODevice *vdev, int n,
bool mask)
{
struct VirtQueue *vvq = virtio_get_queue(vdev, n);
int r, index = n - hdev->vq_index;
struct vhost_vring_file file;
/* should only be called after backend is connected */
assert(hdev->vhost_ops);
if (mask) {
assert(vdev->use_guest_notifier_mask);
file.fd = event_notifier_get_fd(&hdev->vqs[index].masked_notifier);
} else {
file.fd = event_notifier_get_fd(virtio_queue_get_guest_notifier(vvq));
}
file.index = hdev->vhost_ops->vhost_get_vq_index(hdev, n);
r = hdev->vhost_ops->vhost_set_vring_call(hdev, &file);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_vring_call failed");
}
}
uint64_t vhost_get_features(struct vhost_dev *hdev, const int *feature_bits,
uint64_t features)
{
const int *bit = feature_bits;
while (*bit != VHOST_INVALID_FEATURE_BIT) {
uint64_t bit_mask = (1ULL << *bit);
if (!(hdev->features & bit_mask)) {
features &= ~bit_mask;
}
bit++;
}
return features;
}
void vhost_ack_features(struct vhost_dev *hdev, const int *feature_bits,
uint64_t features)
{
const int *bit = feature_bits;
while (*bit != VHOST_INVALID_FEATURE_BIT) {
uint64_t bit_mask = (1ULL << *bit);
if (features & bit_mask) {
hdev->acked_features |= bit_mask;
}
bit++;
}
}
int vhost_dev_get_config(struct vhost_dev *hdev, uint8_t *config,
uint32_t config_len)
{
assert(hdev->vhost_ops);
if (hdev->vhost_ops->vhost_get_config) {
return hdev->vhost_ops->vhost_get_config(hdev, config, config_len);
}
return -1;
}
int vhost_dev_set_config(struct vhost_dev *hdev, const uint8_t *data,
uint32_t offset, uint32_t size, uint32_t flags)
{
assert(hdev->vhost_ops);
if (hdev->vhost_ops->vhost_set_config) {
return hdev->vhost_ops->vhost_set_config(hdev, data, offset,
size, flags);
}
return -1;
}
void vhost_dev_set_config_notifier(struct vhost_dev *hdev,
const VhostDevConfigOps *ops)
{
hdev->config_ops = ops;
}
void vhost_dev_free_inflight(struct vhost_inflight *inflight)
{
if (inflight->addr) {
qemu_memfd_free(inflight->addr, inflight->size, inflight->fd);
inflight->addr = NULL;
inflight->fd = -1;
}
}
static int vhost_dev_resize_inflight(struct vhost_inflight *inflight,
uint64_t new_size)
{
Error *err = NULL;
int fd = -1;
void *addr = qemu_memfd_alloc("vhost-inflight", new_size,
F_SEAL_GROW | F_SEAL_SHRINK | F_SEAL_SEAL,
&fd, &err);
if (err) {
error_report_err(err);
return -1;
}
vhost_dev_free_inflight(inflight);
inflight->offset = 0;
inflight->addr = addr;
inflight->fd = fd;
inflight->size = new_size;
return 0;
}
void vhost_dev_save_inflight(struct vhost_inflight *inflight, QEMUFile *f)
{
if (inflight->addr) {
qemu_put_be64(f, inflight->size);
qemu_put_be16(f, inflight->queue_size);
qemu_put_buffer(f, inflight->addr, inflight->size);
} else {
qemu_put_be64(f, 0);
}
}
int vhost_dev_load_inflight(struct vhost_inflight *inflight, QEMUFile *f)
{
uint64_t size;
size = qemu_get_be64(f);
if (!size) {
return 0;
}
if (inflight->size != size) {
if (vhost_dev_resize_inflight(inflight, size)) {
return -1;
}
}
inflight->queue_size = qemu_get_be16(f);
qemu_get_buffer(f, inflight->addr, size);
return 0;
}
int vhost_dev_set_inflight(struct vhost_dev *dev,
struct vhost_inflight *inflight)
{
int r;
if (dev->vhost_ops->vhost_set_inflight_fd && inflight->addr) {
r = dev->vhost_ops->vhost_set_inflight_fd(dev, inflight);
if (r) {
VHOST_OPS_DEBUG("vhost_set_inflight_fd failed");
return -errno;
}
}
return 0;
}
int vhost_dev_get_inflight(struct vhost_dev *dev, uint16_t queue_size,
struct vhost_inflight *inflight)
{
int r;
if (dev->vhost_ops->vhost_get_inflight_fd) {
r = dev->vhost_ops->vhost_get_inflight_fd(dev, queue_size, inflight);
if (r) {
VHOST_OPS_DEBUG("vhost_get_inflight_fd failed");
return -errno;
}
}
return 0;
}
/* Host notifiers must be enabled at this point. */
int vhost_dev_start(struct vhost_dev *hdev, VirtIODevice *vdev)
{
int i, r;
/* should only be called after backend is connected */
assert(hdev->vhost_ops);
hdev->started = true;
hdev->vdev = vdev;
r = vhost_dev_set_features(hdev, hdev->log_enabled);
if (r < 0) {
goto fail_features;
}
if (vhost_dev_has_iommu(hdev)) {
memory_listener_register(&hdev->iommu_listener, vdev->dma_as);
}
r = hdev->vhost_ops->vhost_set_mem_table(hdev, hdev->mem);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_mem_table failed");
r = -errno;
goto fail_mem;
}
for (i = 0; i < hdev->nvqs; ++i) {
r = vhost_virtqueue_start(hdev,
vdev,
hdev->vqs + i,
hdev->vq_index + i);
if (r < 0) {
goto fail_vq;
}
}
if (hdev->log_enabled) {
uint64_t log_base;
hdev->log_size = vhost_get_log_size(hdev);
hdev->log = vhost_log_get(hdev->log_size,
vhost_dev_log_is_shared(hdev));
log_base = (uintptr_t)hdev->log->log;
r = hdev->vhost_ops->vhost_set_log_base(hdev,
hdev->log_size ? log_base : 0,
hdev->log);
if (r < 0) {
VHOST_OPS_DEBUG("vhost_set_log_base failed");
r = -errno;
goto fail_log;
}
}
if (vhost_dev_has_iommu(hdev)) {
hdev->vhost_ops->vhost_set_iotlb_callback(hdev, true);
/* Update used ring information for IOTLB to work correctly,
* vhost-kernel code requires for this.*/
for (i = 0; i < hdev->nvqs; ++i) {
struct vhost_virtqueue *vq = hdev->vqs + i;
vhost_device_iotlb_miss(hdev, vq->used_phys, true);
}
}
return 0;
fail_log:
vhost_log_put(hdev, false);
fail_vq:
while (--i >= 0) {
vhost_virtqueue_stop(hdev,
vdev,
hdev->vqs + i,
hdev->vq_index + i);
}
i = hdev->nvqs;
fail_mem:
fail_features:
hdev->started = false;
return r;
}
/* Host notifiers must be enabled at this point. */
void vhost_dev_stop(struct vhost_dev *hdev, VirtIODevice *vdev)
{
int i;
/* should only be called after backend is connected */
assert(hdev->vhost_ops);
for (i = 0; i < hdev->nvqs; ++i) {
vhost_virtqueue_stop(hdev,
vdev,
hdev->vqs + i,
hdev->vq_index + i);
}
if (vhost_dev_has_iommu(hdev)) {
hdev->vhost_ops->vhost_set_iotlb_callback(hdev, false);
memory_listener_unregister(&hdev->iommu_listener);
}
vhost_log_put(hdev, true);
hdev->started = false;
hdev->vdev = NULL;
}
int vhost_net_set_backend(struct vhost_dev *hdev,
struct vhost_vring_file *file)
{
if (hdev->vhost_ops->vhost_net_set_backend) {
return hdev->vhost_ops->vhost_net_set_backend(hdev, file);
}
return -1;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-add/test_msa_adds_a_b.c | <filename>src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-add/test_msa_adds_a_b.c
/*
* Test program for MSA instruction ADDS_A.B
*
* Copyright (C) 2019 RT-RK Computer Based Systems LLC
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "ADDS_A.B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x0202020202020202ULL, 0x0202020202020202ULL, }, /* 0 */
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x5757575757575757ULL, 0x5757575757575757ULL, },
{ 0x5656565656565656ULL, 0x5656565656565656ULL, },
{ 0x3535353535353535ULL, 0x3535353535353535ULL, },
{ 0x3434343434343434ULL, 0x3434343434343434ULL, },
{ 0x1e73391e73391e73ULL, 0x391e73391e73391eULL, },
{ 0x1d723a1d723a1d72ULL, 0x3a1d723a1d723a1dULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x5656565656565656ULL, 0x5656565656565656ULL, },
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0x3434343434343434ULL, 0x3434343434343434ULL, },
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0x1d72381d72381d72ULL, 0x381d72381d72381dULL, },
{ 0x1c71391c71391c71ULL, 0x391c71391c71391cULL, },
{ 0x5757575757575757ULL, 0x5757575757575757ULL, }, /* 16 */
{ 0x5656565656565656ULL, 0x5656565656565656ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x737f7f737f7f737fULL, 0x7f737f7f737f7f73ULL, },
{ 0x727f7f727f7f727fULL, 0x7f727f7f727f7f72ULL, },
{ 0x5656565656565656ULL, 0x5656565656565656ULL, }, /* 24 */
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x727f7f727f7f727fULL, 0x7f727f7f727f7f72ULL, },
{ 0x717f7f717f7f717fULL, 0x7f717f7f717f7f71ULL, },
{ 0x3535353535353535ULL, 0x3535353535353535ULL, }, /* 32 */
{ 0x3434343434343434ULL, 0x3434343434343434ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x6868686868686868ULL, 0x6868686868686868ULL, },
{ 0x6767676767676767ULL, 0x6767676767676767ULL, },
{ 0x517f6c517f6c517fULL, 0x6c517f6c517f6c51ULL, },
{ 0x507f6d507f6d507fULL, 0x6d507f6d507f6d50ULL, },
{ 0x3434343434343434ULL, 0x3434343434343434ULL, }, /* 40 */
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x6767676767676767ULL, 0x6767676767676767ULL, },
{ 0x6666666666666666ULL, 0x6666666666666666ULL, },
{ 0x507f6b507f6b507fULL, 0x6b507f6b507f6b50ULL, },
{ 0x4f7f6c4f7f6c4f7fULL, 0x6c4f7f6c4f7f6c4fULL, },
{ 0x1e73391e73391e73ULL, 0x391e73391e73391eULL, }, /* 48 */
{ 0x1d72381d72381d72ULL, 0x381d72381d72381dULL, },
{ 0x737f7f737f7f737fULL, 0x7f737f7f737f7f73ULL, },
{ 0x727f7f727f7f727fULL, 0x7f727f7f727f7f72ULL, },
{ 0x517f6c517f6c517fULL, 0x6c517f6c517f6c51ULL, },
{ 0x507f6b507f6b507fULL, 0x6b507f6b507f6b50ULL, },
{ 0x3a7f703a7f703a7fULL, 0x703a7f703a7f703aULL, },
{ 0x397f71397f71397fULL, 0x71397f71397f7139ULL, },
{ 0x1d723a1d723a1d72ULL, 0x3a1d723a1d723a1dULL, }, /* 56 */
{ 0x1c71391c71391c71ULL, 0x391c71391c71391cULL, },
{ 0x727f7f727f7f727fULL, 0x7f727f7f727f7f72ULL, },
{ 0x717f7f717f7f717fULL, 0x7f717f7f717f7f71ULL, },
{ 0x507f6d507f6d507fULL, 0x6d507f6d507f6d50ULL, },
{ 0x4f7f6c4f7f6c4f7fULL, 0x6c4f7f6c4f7f6c4fULL, },
{ 0x397f71397f71397fULL, 0x71397f71397f7139ULL, },
{ 0x387f72387f72387fULL, 0x72387f72387f7238ULL, },
{ 0x7f7f3468507f7f7fULL, 0x7f7f167f047f7f18ULL, }, /* 64 */
{ 0x7d7f1a7f757f7f48ULL, 0x5d705078177f7f10ULL, },
{ 0x7f7f6c7f6f7f7f7fULL, 0x727f455f577f7520ULL, },
{ 0x7f7f307f7f7f737fULL, 0x7f767f7f597f6e6cULL, },
{ 0x7d7f1a7f757f7f48ULL, 0x5d705078177f7f10ULL, },
{ 0x0a7f007f7f7f7210ULL, 0x24127f342a7e7f08ULL, },
{ 0x597f527f7f7f7f7fULL, 0x39317f1b6a6a7718ULL, },
{ 0x757f167f7f7f5756ULL, 0x7f187f426c7f7064ULL, },
{ 0x7f7f6c7f6f7f7f7fULL, 0x727f455f577f7520ULL, }, /* 72 */
{ 0x597f527f7f7f7f7fULL, 0x39317f1b6a6a7718ULL, },
{ 0x7f7f7f7f7f627f7fULL, 0x4e5074027f564a28ULL, },
{ 0x7f7f687f7f627f7fULL, 0x7f377f297f6d4374ULL, },
{ 0x7f7f307f7f7f737fULL, 0x7f767f7f597f6e6cULL, },
{ 0x757f167f7f7f5756ULL, 0x7f187f426c7f7064ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_ADDS_A_B(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_ADDS_A_B(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/include/hw/ppc/openpic.h | <reponame>pmp-tool/PMP
#ifndef OPENPIC_H
#define OPENPIC_H
#include "qemu-common.h"
#include "hw/sysbus.h"
#include "hw/qdev-core.h"
#include "qom/cpu.h"
#define MAX_CPU 32
#define MAX_MSI 8
#define VID 0x03 /* MPIC version ID */
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
enum {
OPENPIC_OUTPUT_INT = 0, /* IRQ */
OPENPIC_OUTPUT_CINT, /* critical IRQ */
OPENPIC_OUTPUT_MCK, /* Machine check event */
OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
OPENPIC_OUTPUT_RESET, /* Core reset event */
OPENPIC_OUTPUT_NB,
};
typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
#define OPENPIC_MODEL_RAVEN 0
#define OPENPIC_MODEL_FSL_MPIC_20 1
#define OPENPIC_MODEL_FSL_MPIC_42 2
#define OPENPIC_MODEL_KEYLARGO 3
#define OPENPIC_MAX_SRC 256
#define OPENPIC_MAX_TMR 4
#define OPENPIC_MAX_IPI 4
#define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
OPENPIC_MAX_TMR)
/* Raven */
#define RAVEN_MAX_CPU 2
#define RAVEN_MAX_EXT 48
#define RAVEN_MAX_IRQ 64
#define RAVEN_MAX_TMR OPENPIC_MAX_TMR
#define RAVEN_MAX_IPI OPENPIC_MAX_IPI
/* KeyLargo */
#define KEYLARGO_MAX_CPU 4
#define KEYLARGO_MAX_EXT 64
#define KEYLARGO_MAX_IPI 4
#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI)
#define KEYLARGO_MAX_TMR 0
#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */
/* Timers don't exist but this makes the code happy... */
#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
/* Interrupt definitions */
#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
/* First doorbell IRQ */
#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
typedef struct FslMpicInfo {
int max_ext;
} FslMpicInfo;
typedef enum IRQType {
IRQ_TYPE_NORMAL = 0,
IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
} IRQType;
/* Round up to the nearest 64 IRQs so that the queue length
* won't change when moving between 32 and 64 bit hosts.
*/
#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
typedef struct IRQQueue {
unsigned long *queue;
int32_t queue_size; /* Only used for VMSTATE_BITMAP */
int next;
int priority;
} IRQQueue;
typedef struct IRQSource {
uint32_t ivpr; /* IRQ vector/priority register */
uint32_t idr; /* IRQ destination register */
uint32_t destmask; /* bitmap of CPU destinations */
int last_cpu;
int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
int pending; /* TRUE if IRQ is pending */
IRQType type;
bool level:1; /* level-triggered */
bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
} IRQSource;
#define IVPR_MASK_SHIFT 31
#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
#define IVPR_ACTIVITY_SHIFT 30
#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
#define IVPR_MODE_SHIFT 29
#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
#define IVPR_POLARITY_SHIFT 23
#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
#define IVPR_SENSE_SHIFT 22
#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
#define IVPR_PRIORITY_MASK (0xFU << 16)
#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
#define IDR_EP 0x80000000 /* external pin */
#define IDR_CI 0x40000000 /* critical interrupt */
typedef struct OpenPICTimer {
uint32_t tccr; /* Global timer current count register */
uint32_t tbcr; /* Global timer base count register */
int n_IRQ;
bool qemu_timer_active; /* Is the qemu_timer is running? */
struct QEMUTimer *qemu_timer;
struct OpenPICState *opp; /* Device timer is part of. */
/* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
current_count written or read, only defined if qemu_timer_active. */
uint64_t origin_time;
} OpenPICTimer;
typedef struct OpenPICMSI {
uint32_t msir; /* Shared Message Signaled Interrupt Register */
} OpenPICMSI;
typedef struct IRQDest {
int32_t ctpr; /* CPU current task priority */
IRQQueue raised;
IRQQueue servicing;
qemu_irq *irqs;
/* Count of IRQ sources asserting on non-INT outputs */
uint32_t outputs_active[OPENPIC_OUTPUT_NB];
} IRQDest;
#define TYPE_OPENPIC "openpic"
#define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
typedef struct OpenPICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mem;
/* Behavior control */
FslMpicInfo *fsl;
uint32_t model;
uint32_t flags;
uint32_t nb_irqs;
uint32_t vid;
uint32_t vir; /* Vendor identification register */
uint32_t vector_mask;
uint32_t tfrr_reset;
uint32_t ivpr_reset;
uint32_t idr_reset;
uint32_t brr1;
uint32_t mpic_mode_mask;
/* Sub-regions */
MemoryRegion sub_io_mem[6];
/* Global registers */
uint32_t frr; /* Feature reporting register */
uint32_t gcr; /* Global configuration register */
uint32_t pir; /* Processor initialization register */
uint32_t spve; /* Spurious vector register */
uint32_t tfrr; /* Timer frequency reporting register */
/* Source registers */
IRQSource src[OPENPIC_MAX_IRQ];
/* Local registers per output pin */
IRQDest dst[MAX_CPU];
uint32_t nb_cpus;
/* Timer registers */
OpenPICTimer timers[OPENPIC_MAX_TMR];
uint32_t max_tmr;
/* Shared MSI registers */
OpenPICMSI msi[MAX_MSI];
uint32_t max_irq;
uint32_t irq_ipi0;
uint32_t irq_tim0;
uint32_t irq_msi;
} OpenPICState;
#endif /* OPENPIC_H */
|
pmp-tool/PMP | src/qemu/src-pmp/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c | <gh_stars>1-10
/* Xtensa configuration-specific ISA information.
Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "qemu/osdep.h"
#include "xtensa-isa.h"
#include "xtensa-isa-internal.h"
/* Sysregs. */
static xtensa_sysreg_internal sysregs[] = {
{ "LBEG", 0, 0 },
{ "LEND", 1, 0 },
{ "LCOUNT", 2, 0 },
{ "BR", 4, 0 },
{ "PTEVADDR", 83, 0 },
{ "DDR", 104, 0 },
{ "176", 176, 0 },
{ "208", 208, 0 },
{ "INTERRUPT", 226, 0 },
{ "INTCLEAR", 227, 0 },
{ "CCOUNT", 234, 0 },
{ "PRID", 235, 0 },
{ "ICOUNT", 236, 0 },
{ "CCOMPARE0", 240, 0 },
{ "CCOMPARE1", 241, 0 },
{ "VECBASE", 231, 0 },
{ "EPC1", 177, 0 },
{ "EPC2", 178, 0 },
{ "EXCSAVE1", 209, 0 },
{ "EXCSAVE2", 210, 0 },
{ "EPS2", 194, 0 },
{ "EXCCAUSE", 232, 0 },
{ "DEPC", 192, 0 },
{ "EXCVADDR", 238, 0 },
{ "WINDOWBASE", 72, 0 },
{ "WINDOWSTART", 73, 0 },
{ "SAR", 3, 0 },
{ "LITBASE", 5, 0 },
{ "PS", 230, 0 },
{ "MISC0", 244, 0 },
{ "MISC1", 245, 0 },
{ "INTENABLE", 228, 0 },
{ "ICOUNTLEVEL", 237, 0 },
{ "DEBUGCAUSE", 233, 0 },
{ "RASID", 90, 0 },
{ "ITLBCFG", 91, 0 },
{ "DTLBCFG", 92, 0 },
{ "CPENABLE", 224, 0 },
{ "SCOMPARE1", 12, 0 },
{ "ATOMCTL", 99, 0 },
{ "THREADPTR", 231, 1 },
{ "AE_OVF_SAR", 240, 1 },
{ "AE_BITHEAD", 241, 1 },
{ "AE_TS_FTS_BU_BP", 242, 1 },
{ "AE_SD_NO", 243, 1 }
};
#define NUM_SYSREGS 45
#define MAX_SPECIAL_REG 245
#define MAX_USER_REG 243
/* Processor states. */
static xtensa_state_internal states[] = {
{ "LCOUNT", 32, 0 },
{ "PC", 32, 0 },
{ "ICOUNT", 32, 0 },
{ "DDR", 32, 0 },
{ "INTERRUPT", 12, 0 },
{ "CCOUNT", 32, 0 },
{ "XTSYNC", 1, 0 },
{ "VECBASE", 22, 0 },
{ "EPC1", 32, 0 },
{ "EPC2", 32, 0 },
{ "EXCSAVE1", 32, 0 },
{ "EXCSAVE2", 32, 0 },
{ "EPS2", 15, 0 },
{ "EXCCAUSE", 6, 0 },
{ "PSINTLEVEL", 4, 0 },
{ "PSUM", 1, 0 },
{ "PSWOE", 1, 0 },
{ "PSRING", 2, 0 },
{ "PSEXCM", 1, 0 },
{ "DEPC", 32, 0 },
{ "EXCVADDR", 32, 0 },
{ "WindowBase", 3, 0 },
{ "WindowStart", 8, 0 },
{ "PSCALLINC", 2, 0 },
{ "PSOWB", 4, 0 },
{ "LBEG", 32, 0 },
{ "LEND", 32, 0 },
{ "SAR", 6, 0 },
{ "THREADPTR", 32, 0 },
{ "LITBADDR", 20, 0 },
{ "LITBEN", 1, 0 },
{ "MISC0", 32, 0 },
{ "MISC1", 32, 0 },
{ "InOCDMode", 1, 0 },
{ "INTENABLE", 12, 0 },
{ "ICOUNTLEVEL", 4, 0 },
{ "DEBUGCAUSE", 6, 0 },
{ "DBNUM", 4, 0 },
{ "CCOMPARE0", 32, 0 },
{ "CCOMPARE1", 32, 0 },
{ "ASID3", 8, 0 },
{ "ASID2", 8, 0 },
{ "ASID1", 8, 0 },
{ "INSTPGSZID4", 2, 0 },
{ "DATAPGSZID4", 2, 0 },
{ "PTBASE", 10, 0 },
{ "CPENABLE", 2, 0 },
{ "SCOMPARE1", 32, 0 },
{ "ATOMCTL", 6, 0 },
{ "CCON", 1, XTENSA_STATE_IS_EXPORTED },
{ "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED },
{ "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED },
{ "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED },
{ "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED },
{ "AE_OVERFLOW", 1, 0 },
{ "AE_SAR", 6, 0 },
{ "AE_BITHEAD", 32, 0 },
{ "AE_BITPTR", 4, 0 },
{ "AE_BITSUSED", 4, 0 },
{ "AE_TABLESIZE", 4, 0 },
{ "AE_FIRST_TS", 4, 0 },
{ "AE_NEXTOFFSET", 27, 0 },
{ "AE_SEARCHDONE", 1, 0 }
};
#define NUM_STATES 63
enum xtensa_state_id {
STATE_LCOUNT,
STATE_PC,
STATE_ICOUNT,
STATE_DDR,
STATE_INTERRUPT,
STATE_CCOUNT,
STATE_XTSYNC,
STATE_VECBASE,
STATE_EPC1,
STATE_EPC2,
STATE_EXCSAVE1,
STATE_EXCSAVE2,
STATE_EPS2,
STATE_EXCCAUSE,
STATE_PSINTLEVEL,
STATE_PSUM,
STATE_PSWOE,
STATE_PSRING,
STATE_PSEXCM,
STATE_DEPC,
STATE_EXCVADDR,
STATE_WindowBase,
STATE_WindowStart,
STATE_PSCALLINC,
STATE_PSOWB,
STATE_LBEG,
STATE_LEND,
STATE_SAR,
STATE_THREADPTR,
STATE_LITBADDR,
STATE_LITBEN,
STATE_MISC0,
STATE_MISC1,
STATE_InOCDMode,
STATE_INTENABLE,
STATE_ICOUNTLEVEL,
STATE_DEBUGCAUSE,
STATE_DBNUM,
STATE_CCOMPARE0,
STATE_CCOMPARE1,
STATE_ASID3,
STATE_ASID2,
STATE_ASID1,
STATE_INSTPGSZID4,
STATE_DATAPGSZID4,
STATE_PTBASE,
STATE_CPENABLE,
STATE_SCOMPARE1,
STATE_ATOMCTL,
STATE_CCON,
STATE_MPSCORE,
STATE_WMPINT_ADDR,
STATE_WMPINT_DATA,
STATE_WMPINT_TOGGLEEN,
STATE_AE_OVERFLOW,
STATE_AE_SAR,
STATE_AE_BITHEAD,
STATE_AE_BITPTR,
STATE_AE_BITSUSED,
STATE_AE_TABLESIZE,
STATE_AE_FIRST_TS,
STATE_AE_NEXTOFFSET,
STATE_AE_SEARCHDONE
};
/* Field definitions. */
static unsigned
Field_t_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
}
static unsigned
Field_s_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_r_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
return tie_t;
}
static void
Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
}
static unsigned
Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
return tie_t;
}
static void
Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
}
static unsigned
Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
}
static unsigned
Field_n_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_m_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
tie_t = (val << 24) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_st_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
tie_t = (val << 24) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
}
static unsigned
Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
return tie_t;
}
static void
Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
}
static unsigned
Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
return tie_t;
}
static void
Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
}
static unsigned
Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
return tie_t;
}
static void
Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
return tie_t;
}
static void
Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
}
static unsigned
Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
return tie_t;
}
static void
Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
}
static unsigned
Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
}
static unsigned
Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
}
static unsigned
Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
}
static unsigned
Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
return tie_t;
}
static void
Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
}
static unsigned
Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
tie_t = (val << 22) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
return tie_t;
}
static void
Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
}
static unsigned
Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
}
static unsigned
Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
return tie_t;
}
static void
Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
}
static unsigned
Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
return tie_t;
}
static void
Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
return tie_t;
}
static void
Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
}
static unsigned
Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
return tie_t;
}
static void
Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
return tie_t;
}
static void
Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
return tie_t;
}
static void
Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
}
static unsigned
Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
return tie_t;
}
static void
Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
tie_t = (val << 25) >> 29;
insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
}
static unsigned
Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 30) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
tie_t = (val << 23) >> 25;
insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
}
static unsigned
Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
tie_t = (val << 22) >> 25;
insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
}
static unsigned
Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
return tie_t;
}
static void
Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
}
static unsigned
Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
return tie_t;
}
static void
Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
tie_t = (val << 21) >> 25;
insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
}
static unsigned
Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
return tie_t;
}
static void
Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
tie_t = (val << 21) >> 25;
insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
}
static unsigned
Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 21) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 20) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
return tie_t;
}
static void
Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
}
static unsigned
Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 21) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 24) >> 31;
insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
tie_t = (val << 21) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
tie_t = (val << 22) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
tie_t = (val << 21) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 20) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
return tie_t;
}
static void
Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26);
return tie_t;
}
static void
Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 26) >> 26;
insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3);
}
static unsigned
Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
return tie_t;
}
static void
Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
return tie_t;
}
static void
Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
return tie_t;
}
static void
Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27);
return tie_t;
}
static void
Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0xf8) | (tie_t << 3);
}
static unsigned
Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
return tie_t;
}
static void
Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
}
static unsigned
Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
tie_t = (val << 25) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
return tie_t;
}
static void
Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
}
static unsigned
Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 23) >> 30;
insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
}
static unsigned
Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27);
return tie_t;
}
static void
Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x7c) | (tie_t << 2);
tie_t = (val << 24) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
return tie_t;
}
static void
Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
}
static unsigned
Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
return tie_t;
}
static void
Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 23) >> 23;
insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
tie_t = (val << 20) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
tie_t = (val << 26) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
tie_t = (val << 26) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
return tie_t;
}
static void
Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 23) >> 23;
insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
tie_t = (val << 20) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26);
return tie_t;
}
static void
Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 26) >> 26;
insn[0] = (insn[0] & ~0x7e) | (tie_t << 1);
tie_t = (val << 23) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
}
static unsigned
Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
return tie_t;
}
static void
Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
tie_t = (val << 22) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
return tie_t;
}
static void
Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 22) >> 23;
insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
}
static unsigned
Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
return tie_t;
}
static void
Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
return tie_t;
}
static void
Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 24) >> 25;
insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
}
static unsigned
Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
}
static unsigned
Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
return tie_t;
}
static void
Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
tie_t = (val << 28) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
}
static unsigned
Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
tie_t = (val << 26) >> 29;
insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
}
static unsigned
Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
return tie_t;
}
static void
Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
}
static unsigned
Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
return tie_t;
}
static void
Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
}
static unsigned
Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 25) >> 31;
insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
}
static unsigned
Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 26) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 26) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 23) >> 27;
insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
}
static unsigned
Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
}
static unsigned
Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
}
static unsigned
Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
return tie_t;
}
static void
Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
}
static unsigned
Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
return tie_t;
}
static void
Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
tie_t = (val << 24) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
}
static unsigned
Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25);
return tie_t;
}
static void
Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20);
}
static unsigned
Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
return tie_t;
}
static void
Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 24) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
}
static unsigned
Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
}
static unsigned
Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
}
static unsigned
Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
}
static unsigned
Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
return tie_t;
}
static void
Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
}
static unsigned
Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
return tie_t;
}
static void
Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
}
static unsigned
Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
return tie_t;
}
static void
Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
}
static unsigned
Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
return tie_t;
}
static void
Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 24) >> 24;
insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
tie_t = (val << 16) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
return tie_t;
}
static void
Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 20) >> 20;
insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
}
static unsigned
Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
return tie_t;
}
static void
Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 26) >> 26;
insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
tie_t = (val << 25) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 17) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
return tie_t;
}
static void
Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
return tie_t;
}
static void
Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 24) >> 24;
insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
tie_t = (val << 16) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29);
return tie_t;
}
static void
Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x38) | (tie_t << 3);
tie_t = (val << 21) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
tie_t = (val << 27) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28);
return tie_t;
}
static void
Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0x3c) | (tie_t << 2);
tie_t = (val << 20) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
return tie_t;
}
static void
Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27);
return tie_t;
}
static void
Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x3e) | (tie_t << 1);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
return tie_t;
}
static void
Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
tie_t = (val << 30) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
return tie_t;
}
static void
Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 20) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25);
return tie_t;
}
static void
Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 25) >> 25;
insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13);
}
static unsigned
Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
return tie_t;
}
static void
Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 19) >> 19;
insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
}
static unsigned
Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
return tie_t;
}
static void
Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
}
static unsigned
Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23);
return tie_t;
}
static void
Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 23) >> 23;
insn[0] = (insn[0] & ~0xff800) | (tie_t << 11);
}
static unsigned
Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27);
return tie_t;
}
static void
Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6);
}
static unsigned
Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
tie_t = (val << 21) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
tie_t = (val << 21) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
return tie_t;
}
static void
Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
}
static unsigned
Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
}
static unsigned
Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
return tie_t;
}
static void
Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
return tie_t;
}
static void
Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
}
static unsigned
Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27);
return tie_t;
}
static void
Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15);
}
static unsigned
Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
tie_t = (val << 27) >> 29;
insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
}
static unsigned
Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
tie_t = (val << 17) >> 20;
insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
}
static unsigned
Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
}
static unsigned
Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 20) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
return tie_t;
}
static void
Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 26) >> 26;
insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
tie_t = (val << 18) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
return tie_t;
}
static void
Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
tie_t = (val << 28) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 20) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 30) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
}
static unsigned
Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 30) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22);
return tie_t;
}
static void
Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 22) >> 22;
insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10);
}
static unsigned
Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21);
return tie_t;
}
static void
Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 21) >> 21;
insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9);
}
static unsigned
Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
}
static unsigned
Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
return tie_t;
}
static void
Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
tie_t = (val << 19) >> 20;
insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
}
static unsigned
Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
return tie_t;
}
static void
Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
tie_t = (val << 29) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
}
static unsigned
Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
return tie_t;
}
static void
Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
tie_t = (val << 18) >> 20;
insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
}
static unsigned
Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
return tie_t;
}
static void
Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
tie_t = (val << 30) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
}
static unsigned
Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 20) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 23) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
return tie_t;
}
static void
Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
tie_t = (val << 22) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
return tie_t;
}
static void
Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
}
static unsigned
Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
return tie_t;
}
static void
Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
tie_t = (val << 17) >> 20;
insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
}
static unsigned
Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 20) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
tie_t = (val << 19) >> 24;
insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
}
static unsigned
Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
}
static unsigned
Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
return tie_t;
}
static void
Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
}
static unsigned
Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
}
static unsigned
Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
return tie_t;
}
static void
Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
}
static unsigned
Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
return tie_t;
}
static void
Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 20) >> 20;
insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
}
static unsigned
Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
return tie_t;
}
static void
Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 24) >> 24;
insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
tie_t = (val << 20) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
return tie_t;
}
static void
Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 24) >> 24;
insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
}
static unsigned
Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
return tie_t;
}
static void
Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 24) >> 24;
insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
tie_t = (val << 20) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
return tie_t;
}
static void
Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 20) >> 20;
insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
}
static unsigned
Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
return tie_t;
}
static void
Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 16) >> 16;
insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
}
static unsigned
Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
return tie_t;
}
static void
Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 16) >> 16;
insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
}
static unsigned
Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
return tie_t;
}
static void
Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 14) >> 14;
insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
}
static unsigned
Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
return tie_t;
}
static void
Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 14) >> 14;
insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
}
static unsigned
Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
return tie_t;
}
static void
Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
}
static unsigned
Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
return tie_t;
}
static void
Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
}
static unsigned
Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
}
static unsigned
Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
return tie_t;
}
static void
Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
}
static unsigned
Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
}
static unsigned
Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
}
static unsigned
Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
}
static unsigned
Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
return tie_t;
}
static void
Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
}
static unsigned
Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
return tie_t;
}
static void
Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
}
static unsigned
Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
tie_t = (val << 27) >> 31;
insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
}
static unsigned
Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
return tie_t;
}
static void
Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 27) >> 27;
insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
}
static unsigned
Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
tie_t = (val << 24) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
return tie_t;
}
static void
Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
tie_t = (val << 24) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
tie_t = (val << 24) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
return tie_t;
}
static void
Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
tie_t = (val << 24) >> 28;
insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
}
static unsigned
Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
tie_t = (val << 28) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
}
static unsigned
Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
return tie_t;
}
static void
Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
}
static unsigned
Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
tie_t = (val << 25) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
return tie_t;
}
static void
Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
tie_t = (val << 25) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
}
static unsigned
Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
}
static unsigned
Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
return tie_t;
}
static void
Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
}
static unsigned
Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 29) >> 30;
insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
}
static unsigned
Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
return tie_t;
}
static void
Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
}
static unsigned
Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
return tie_t;
}
static void
Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
}
static unsigned
Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
return tie_t;
}
static void
Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
}
static unsigned
Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
return tie_t;
}
static void
Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
}
static unsigned
Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
return tie_t;
}
static void
Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
}
static unsigned
Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
return tie_t;
}
static void
Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
}
static unsigned
Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
return tie_t;
}
static void
Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
}
static unsigned
Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
return tie_t;
}
static void
Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
}
static unsigned
Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
return tie_t;
}
static void
Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
}
static unsigned
Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
return tie_t;
}
static void
Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
}
static unsigned
Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
return tie_t;
}
static void
Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
return tie_t;
}
static void
Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
return tie_t;
}
static void
Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
}
static unsigned
Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
return tie_t;
}
static void
Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
}
static unsigned
Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
return tie_t;
}
static void
Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
}
static unsigned
Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
return tie_t;
}
static void
Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
}
static unsigned
Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
return tie_t;
}
static void
Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
}
static unsigned
Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
return tie_t;
}
static void
Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
}
static unsigned
Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
return tie_t;
}
static void
Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
}
static unsigned
Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
return tie_t;
}
static void
Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
}
static unsigned
Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
return tie_t;
}
static void
Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 17) >> 17;
insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
}
static unsigned
Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
return tie_t;
}
static void
Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 14) >> 14;
insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
}
static unsigned
Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26);
return tie_t;
}
static void
Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 26) >> 26;
insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4);
}
static unsigned
Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
return tie_t;
}
static void
Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 28) >> 28;
insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
tie_t = (val << 26) >> 30;
insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
}
static unsigned
Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
return tie_t;
}
static void
Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
}
static unsigned
Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
return tie_t;
}
static void
Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
}
static unsigned
Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
return tie_t;
}
static void
Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 29) >> 29;
insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
}
static unsigned
Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
return tie_t;
}
static void
Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 30) >> 30;
insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
}
static unsigned
Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn)
{
unsigned tie_t = 0;
tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
return tie_t;
}
static void
Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
{
uint32 tie_t;
tie_t = (val << 31) >> 31;
insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
tie_t = (val << 27) >> 28;
insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
}
static void
Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
uint32 val ATTRIBUTE_UNUSED)
{
/* Do nothing. */
}
static unsigned
Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 0;
}
static unsigned
Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 4;
}
static unsigned
Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 8;
}
static unsigned
Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 12;
}
static unsigned
Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 0;
}
static unsigned
Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 0;
}
static unsigned
Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 0;
}
static unsigned
Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
{
return 0;
}
enum xtensa_field_id {
FIELD_t,
FIELD_bbi4,
FIELD_bbi,
FIELD_imm12,
FIELD_imm8,
FIELD_s,
FIELD_imm12b,
FIELD_imm16,
FIELD_m,
FIELD_n,
FIELD_offset,
FIELD_op0,
FIELD_op1,
FIELD_op2,
FIELD_r,
FIELD_sa4,
FIELD_sae4,
FIELD_sae,
FIELD_sal,
FIELD_sargt,
FIELD_sas4,
FIELD_sas,
FIELD_sr,
FIELD_st,
FIELD_thi3,
FIELD_imm4,
FIELD_mn,
FIELD_i,
FIELD_imm6lo,
FIELD_imm6hi,
FIELD_imm7lo,
FIELD_imm7hi,
FIELD_z,
FIELD_imm6,
FIELD_imm7,
FIELD_t2,
FIELD_s2,
FIELD_r2,
FIELD_t4,
FIELD_s4,
FIELD_r4,
FIELD_t8,
FIELD_s8,
FIELD_r8,
FIELD_xt_wbr15_imm,
FIELD_xt_wbr18_imm,
FIELD_ae_r3,
FIELD_ae_s_non_samt,
FIELD_ae_s3,
FIELD_ae_r32,
FIELD_ae_samt_s_t,
FIELD_ae_r20,
FIELD_ae_r10,
FIELD_ae_s20,
FIELD_op0_s3,
FIELD_ftsf12,
FIELD_ftsf13,
FIELD_ftsf14,
FIELD_ftsf21ae_slot1,
FIELD_ftsf22ae_slot1,
FIELD_ftsf23ae_slot1,
FIELD_ftsf24ae_slot1,
FIELD_ftsf25ae_slot1,
FIELD_ftsf26ae_slot1,
FIELD_ftsf27ae_slot1,
FIELD_ftsf28ae_slot1,
FIELD_ftsf29ae_slot1,
FIELD_ftsf30ae_slot1,
FIELD_ftsf31ae_slot1,
FIELD_ftsf32ae_slot1,
FIELD_ftsf33ae_slot1,
FIELD_ftsf34ae_slot1,
FIELD_ftsf35ae_slot1,
FIELD_ftsf36ae_slot1,
FIELD_ftsf37ae_slot1,
FIELD_ftsf38ae_slot1,
FIELD_ftsf39ae_slot1,
FIELD_ftsf40ae_slot1,
FIELD_ftsf41ae_slot1,
FIELD_ftsf42ae_slot1,
FIELD_ftsf43ae_slot1,
FIELD_ftsf44ae_slot1,
FIELD_ftsf45ae_slot1,
FIELD_ftsf46ae_slot1,
FIELD_ftsf47ae_slot1,
FIELD_ftsf48ae_slot1,
FIELD_ftsf49ae_slot1,
FIELD_ftsf50ae_slot1,
FIELD_ftsf51ae_slot1,
FIELD_ftsf52ae_slot1,
FIELD_ftsf53ae_slot1,
FIELD_ftsf54ae_slot1,
FIELD_ftsf55ae_slot1,
FIELD_ftsf56ae_slot1,
FIELD_ftsf57ae_slot1,
FIELD_ftsf58ae_slot1,
FIELD_ftsf59ae_slot1,
FIELD_ftsf60ae_slot1,
FIELD_ftsf61ae_slot1,
FIELD_ftsf63ae_slot1,
FIELD_ftsf64ae_slot1,
FIELD_ftsf66ae_slot1,
FIELD_ftsf67ae_slot1,
FIELD_ftsf69ae_slot1,
FIELD_ftsf71ae_slot1,
FIELD_ftsf72ae_slot1,
FIELD_ftsf73ae_slot1,
FIELD_ftsf75ae_slot1,
FIELD_ftsf76ae_slot1,
FIELD_ftsf77ae_slot1,
FIELD_ftsf78ae_slot1,
FIELD_ftsf79ae_slot1,
FIELD_ftsf80ae_slot1,
FIELD_ftsf81ae_slot1,
FIELD_ftsf82ae_slot1,
FIELD_ftsf84ae_slot1,
FIELD_ftsf86ae_slot1,
FIELD_ftsf87ae_slot1,
FIELD_ftsf88ae_slot1,
FIELD_ftsf89ae_slot1,
FIELD_ftsf90ae_slot1,
FIELD_ftsf91ae_slot1,
FIELD_ftsf92ae_slot1,
FIELD_ftsf94ae_slot1,
FIELD_ftsf96ae_slot1,
FIELD_ftsf97ae_slot1,
FIELD_ftsf98ae_slot1,
FIELD_ftsf99ae_slot1,
FIELD_ftsf100ae_slot1,
FIELD_ftsf101ae_slot1,
FIELD_ftsf103ae_slot1,
FIELD_ftsf104ae_slot1,
FIELD_ftsf105ae_slot1,
FIELD_ftsf106ae_slot1,
FIELD_ftsf107ae_slot1,
FIELD_ftsf108ae_slot1,
FIELD_ftsf109ae_slot1,
FIELD_ftsf110ae_slot1,
FIELD_ftsf111ae_slot1,
FIELD_ftsf112ae_slot1,
FIELD_ftsf113ae_slot1,
FIELD_ftsf114ae_slot1,
FIELD_ftsf115ae_slot1,
FIELD_ftsf116ae_slot1,
FIELD_ftsf118ae_slot1,
FIELD_ftsf119ae_slot1,
FIELD_ftsf120ae_slot1,
FIELD_ftsf122ae_slot1,
FIELD_ftsf124ae_slot1,
FIELD_ftsf125ae_slot1,
FIELD_ftsf126ae_slot1,
FIELD_ftsf127ae_slot1,
FIELD_ftsf128ae_slot1,
FIELD_ftsf129ae_slot1,
FIELD_ftsf130ae_slot1,
FIELD_ftsf131ae_slot1,
FIELD_ftsf132ae_slot1,
FIELD_ftsf133ae_slot1,
FIELD_ftsf134ae_slot1,
FIELD_ftsf135ae_slot1,
FIELD_ftsf136ae_slot1,
FIELD_ftsf137ae_slot1,
FIELD_ftsf138ae_slot1,
FIELD_ftsf139ae_slot1,
FIELD_ftsf140ae_slot1,
FIELD_ftsf141ae_slot1,
FIELD_ftsf142ae_slot1,
FIELD_ftsf143ae_slot1,
FIELD_ftsf144ae_slot1,
FIELD_ftsf145ae_slot1,
FIELD_ftsf146ae_slot1,
FIELD_ftsf147ae_slot1,
FIELD_ftsf148ae_slot1,
FIELD_ftsf149ae_slot1,
FIELD_ftsf150ae_slot1,
FIELD_ftsf151ae_slot1,
FIELD_ftsf152ae_slot1,
FIELD_ftsf153ae_slot1,
FIELD_ftsf154ae_slot1,
FIELD_ftsf155ae_slot1,
FIELD_ftsf156ae_slot1,
FIELD_ftsf157ae_slot1,
FIELD_ftsf158ae_slot1,
FIELD_ftsf159ae_slot1,
FIELD_ftsf160ae_slot1,
FIELD_ftsf161ae_slot1,
FIELD_ftsf162ae_slot1,
FIELD_ftsf163ae_slot1,
FIELD_ftsf164ae_slot1,
FIELD_ftsf165ae_slot1,
FIELD_ftsf166ae_slot1,
FIELD_ftsf167ae_slot1,
FIELD_ftsf168ae_slot1,
FIELD_ftsf169ae_slot1,
FIELD_ftsf170ae_slot1,
FIELD_ftsf171ae_slot1,
FIELD_ftsf172ae_slot1,
FIELD_ftsf173ae_slot1,
FIELD_ftsf174ae_slot1,
FIELD_ftsf175ae_slot1,
FIELD_ftsf176ae_slot1,
FIELD_ftsf177ae_slot1,
FIELD_ftsf178ae_slot1,
FIELD_ftsf179ae_slot1,
FIELD_ftsf180ae_slot1,
FIELD_ftsf181ae_slot1,
FIELD_ftsf182ae_slot1,
FIELD_ftsf183ae_slot1,
FIELD_ftsf184ae_slot1,
FIELD_ftsf185ae_slot1,
FIELD_ftsf186ae_slot1,
FIELD_ftsf187ae_slot1,
FIELD_ftsf188ae_slot1,
FIELD_ftsf189ae_slot1,
FIELD_ftsf190ae_slot1,
FIELD_ftsf191ae_slot1,
FIELD_ftsf192ae_slot1,
FIELD_ftsf193ae_slot1,
FIELD_ftsf194ae_slot1,
FIELD_ftsf195ae_slot1,
FIELD_ftsf196ae_slot1,
FIELD_ftsf197ae_slot1,
FIELD_ftsf198ae_slot1,
FIELD_ftsf199ae_slot1,
FIELD_ftsf200ae_slot1,
FIELD_ftsf201ae_slot1,
FIELD_ftsf202ae_slot1,
FIELD_ftsf203ae_slot1,
FIELD_ftsf204ae_slot1,
FIELD_ftsf205ae_slot1,
FIELD_ftsf206ae_slot1,
FIELD_ftsf207ae_slot1,
FIELD_ftsf208,
FIELD_ftsf209ae_slot1,
FIELD_ftsf210ae_slot1,
FIELD_ftsf211ae_slot1,
FIELD_ftsf330ae_slot1,
FIELD_ftsf332ae_slot1,
FIELD_ftsf334ae_slot1,
FIELD_ftsf336ae_slot1,
FIELD_ftsf337ae_slot1,
FIELD_ftsf338,
FIELD_ftsf339ae_slot1,
FIELD_ftsf340,
FIELD_ftsf341ae_slot1,
FIELD_ftsf342ae_slot1,
FIELD_ftsf343ae_slot1,
FIELD_ftsf344ae_slot1,
FIELD_ftsf346ae_slot1,
FIELD_ftsf347,
FIELD_ftsf348ae_slot1,
FIELD_ftsf349ae_slot1,
FIELD_ftsf350ae_slot1,
FIELD_op0_s4,
FIELD_ftsf212ae_slot0,
FIELD_ftsf213ae_slot0,
FIELD_ftsf214ae_slot0,
FIELD_ftsf215ae_slot0,
FIELD_ftsf216ae_slot0,
FIELD_ftsf217,
FIELD_ftsf218ae_slot0,
FIELD_ftsf219ae_slot0,
FIELD_ftsf220ae_slot0,
FIELD_ftsf221ae_slot0,
FIELD_ftsf222ae_slot0,
FIELD_ftsf223ae_slot0,
FIELD_ftsf224ae_slot0,
FIELD_ftsf225ae_slot0,
FIELD_ftsf226ae_slot0,
FIELD_ftsf227ae_slot0,
FIELD_ftsf228ae_slot0,
FIELD_ftsf229ae_slot0,
FIELD_ftsf230ae_slot0,
FIELD_ftsf231ae_slot0,
FIELD_ftsf232ae_slot0,
FIELD_ftsf233ae_slot0,
FIELD_ftsf234ae_slot0,
FIELD_ftsf235ae_slot0,
FIELD_ftsf236ae_slot0,
FIELD_ftsf237ae_slot0,
FIELD_ftsf238ae_slot0,
FIELD_ftsf239ae_slot0,
FIELD_ftsf240ae_slot0,
FIELD_ftsf241ae_slot0,
FIELD_ftsf242ae_slot0,
FIELD_ftsf243ae_slot0,
FIELD_ftsf244ae_slot0,
FIELD_ftsf245ae_slot0,
FIELD_ftsf246ae_slot0,
FIELD_ftsf247ae_slot0,
FIELD_ftsf248ae_slot0,
FIELD_ftsf249ae_slot0,
FIELD_ftsf250ae_slot0,
FIELD_ftsf251ae_slot0,
FIELD_ftsf252ae_slot0,
FIELD_ftsf253ae_slot0,
FIELD_ftsf254ae_slot0,
FIELD_ftsf255ae_slot0,
FIELD_ftsf256ae_slot0,
FIELD_ftsf257ae_slot0,
FIELD_ftsf258ae_slot0,
FIELD_ftsf259ae_slot0,
FIELD_ftsf260ae_slot0,
FIELD_ftsf261ae_slot0,
FIELD_ftsf262ae_slot0,
FIELD_ftsf263ae_slot0,
FIELD_ftsf264ae_slot0,
FIELD_ftsf265ae_slot0,
FIELD_ftsf266ae_slot0,
FIELD_ftsf267ae_slot0,
FIELD_ftsf268ae_slot0,
FIELD_ftsf269ae_slot0,
FIELD_ftsf270ae_slot0,
FIELD_ftsf271ae_slot0,
FIELD_ftsf272ae_slot0,
FIELD_ftsf273ae_slot0,
FIELD_ftsf274ae_slot0,
FIELD_ftsf275ae_slot0,
FIELD_ftsf276ae_slot0,
FIELD_ftsf277ae_slot0,
FIELD_ftsf278ae_slot0,
FIELD_ftsf279ae_slot0,
FIELD_ftsf281ae_slot0,
FIELD_ftsf282ae_slot0,
FIELD_ftsf283ae_slot0,
FIELD_ftsf284ae_slot0,
FIELD_ftsf286ae_slot0,
FIELD_ftsf288ae_slot0,
FIELD_ftsf290ae_slot0,
FIELD_ftsf292ae_slot0,
FIELD_ftsf293,
FIELD_ftsf294ae_slot0,
FIELD_ftsf295ae_slot0,
FIELD_ftsf296ae_slot0,
FIELD_ftsf297ae_slot0,
FIELD_ftsf298ae_slot0,
FIELD_ftsf299ae_slot0,
FIELD_ftsf300ae_slot0,
FIELD_ftsf301ae_slot0,
FIELD_ftsf302ae_slot0,
FIELD_ftsf303ae_slot0,
FIELD_ftsf304ae_slot0,
FIELD_ftsf306ae_slot0,
FIELD_ftsf308ae_slot0,
FIELD_ftsf309ae_slot0,
FIELD_ftsf310ae_slot0,
FIELD_ftsf311ae_slot0,
FIELD_ftsf312ae_slot0,
FIELD_ftsf313ae_slot0,
FIELD_ftsf314ae_slot0,
FIELD_ftsf315ae_slot0,
FIELD_ftsf316ae_slot0,
FIELD_ftsf317ae_slot0,
FIELD_ftsf318ae_slot0,
FIELD_ftsf319,
FIELD_ftsf320ae_slot0,
FIELD_ftsf321,
FIELD_ftsf322ae_slot0,
FIELD_ftsf323ae_slot0,
FIELD_ftsf324ae_slot0,
FIELD_ftsf325ae_slot0,
FIELD_ftsf326ae_slot0,
FIELD_ftsf328ae_slot0,
FIELD_ftsf329ae_slot0,
FIELD_ftsf352ae_slot0,
FIELD_ftsf353,
FIELD_ftsf354ae_slot0,
FIELD_ftsf356ae_slot0,
FIELD_ftsf357,
FIELD_ftsf358ae_slot0,
FIELD_ftsf359ae_slot0,
FIELD_ftsf360ae_slot0,
FIELD_ftsf361ae_slot0,
FIELD_ftsf362ae_slot0,
FIELD_ftsf364ae_slot0,
FIELD_ftsf365ae_slot0,
FIELD_ftsf366ae_slot0,
FIELD_ftsf368ae_slot0,
FIELD_ftsf369ae_slot0,
FIELD__ar0,
FIELD__ar4,
FIELD__ar8,
FIELD__ar12,
FIELD__bt16,
FIELD__bs16,
FIELD__br16,
FIELD__brall
};
/* Functional units. */
static xtensa_funcUnit_internal funcUnits[] = {
{ "ae_add32", 1 },
{ "ae_shift32x4", 1 },
{ "ae_shift32x5", 1 },
{ "ae_subshift", 1 }
};
enum xtensa_funcUnit_id {
FUNCUNIT_ae_add32,
FUNCUNIT_ae_shift32x4,
FUNCUNIT_ae_shift32x5,
FUNCUNIT_ae_subshift
};
/* Register files. */
enum xtensa_regfile_id {
REGFILE_AR,
REGFILE_BR,
REGFILE_AE_PR,
REGFILE_AE_QR,
REGFILE_BR2,
REGFILE_BR4,
REGFILE_BR8,
REGFILE_BR16
};
static xtensa_regfile_internal regfiles[] = {
{ "AR", "a", REGFILE_AR, 32, 32 },
{ "BR", "b", REGFILE_BR, 1, 16 },
{ "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
{ "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
{ "BR2", "b", REGFILE_BR, 2, 8 },
{ "BR4", "b", REGFILE_BR, 4, 4 },
{ "BR8", "b", REGFILE_BR, 8, 2 },
{ "BR16", "b", REGFILE_BR, 16, 1 }
};
/* Interfaces. */
static xtensa_interface_internal interfaces[] = {
{ "RMPINT_Out", 12, 0, 0, 'o' },
{ "RMPINT_In", 32, 0, 1, 'i' }
};
enum xtensa_interface_id {
INTERFACE_RMPINT_Out,
INTERFACE_RMPINT_In
};
/* Constant tables. */
/* constant table ai4c */
static const unsigned CONST_TBL_ai4c_0[] = {
0xffffffff,
0x1,
0x2,
0x3,
0x4,
0x5,
0x6,
0x7,
0x8,
0x9,
0xa,
0xb,
0xc,
0xd,
0xe,
0xf,
0
};
/* constant table b4c */
static const unsigned CONST_TBL_b4c_0[] = {
0xffffffff,
0x1,
0x2,
0x3,
0x4,
0x5,
0x6,
0x7,
0x8,
0xa,
0xc,
0x10,
0x20,
0x40,
0x80,
0x100,
0
};
/* constant table b4cu */
static const unsigned CONST_TBL_b4cu_0[] = {
0x8000,
0x10000,
0x2,
0x3,
0x4,
0x5,
0x6,
0x7,
0x8,
0xa,
0xc,
0x10,
0x20,
0x40,
0x80,
0x100,
0
};
/* Instruction operands. */
static int
Operand_soffsetx4_decode (uint32 *valp)
{
unsigned soffsetx4_0, offset_0;
offset_0 = *valp & 0x3ffff;
soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
*valp = soffsetx4_0;
return 0;
}
static int
Operand_soffsetx4_encode (uint32 *valp)
{
unsigned offset_0, soffsetx4_0;
soffsetx4_0 = *valp;
offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
*valp = offset_0;
return 0;
}
static int
Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
{
*valp -= (pc & ~0x3);
return 0;
}
static int
Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
{
*valp += (pc & ~0x3);
return 0;
}
static int
Operand_uimm12x8_decode (uint32 *valp)
{
unsigned uimm12x8_0, imm12_0;
imm12_0 = *valp & 0xfff;
uimm12x8_0 = imm12_0 << 3;
*valp = uimm12x8_0;
return 0;
}
static int
Operand_uimm12x8_encode (uint32 *valp)
{
unsigned imm12_0, uimm12x8_0;
uimm12x8_0 = *valp;
imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
*valp = imm12_0;
return 0;
}
static int
Operand_simm4_decode (uint32 *valp)
{
unsigned simm4_0, mn_0;
mn_0 = *valp & 0xf;
simm4_0 = ((int) mn_0 << 28) >> 28;
*valp = simm4_0;
return 0;
}
static int
Operand_simm4_encode (uint32 *valp)
{
unsigned mn_0, simm4_0;
simm4_0 = *valp;
mn_0 = (simm4_0 & 0xf);
*valp = mn_0;
return 0;
}
static int
Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_arr_encode (uint32 *valp)
{
int error;
error = (*valp & ~0xf) != 0;
return error;
}
static int
Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ars_encode (uint32 *valp)
{
int error;
error = (*valp & ~0xf) != 0;
return error;
}
static int
Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_art_encode (uint32 *valp)
{
int error;
error = (*valp & ~0xf) != 0;
return error;
}
static int
Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ar0_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x1f) != 0;
return error;
}
static int
Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ar4_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x1f) != 0;
return error;
}
static int
Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ar8_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x1f) != 0;
return error;
}
static int
Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ar12_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x1f) != 0;
return error;
}
static int
Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ars_entry_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x1f) != 0;
return error;
}
static int
Operand_immrx4_decode (uint32 *valp)
{
unsigned immrx4_0, r_0;
r_0 = *valp & 0xf;
immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
*valp = immrx4_0;
return 0;
}
static int
Operand_immrx4_encode (uint32 *valp)
{
unsigned r_0, immrx4_0;
immrx4_0 = *valp;
r_0 = ((immrx4_0 >> 2) & 0xf);
*valp = r_0;
return 0;
}
static int
Operand_lsi4x4_decode (uint32 *valp)
{
unsigned lsi4x4_0, r_0;
r_0 = *valp & 0xf;
lsi4x4_0 = r_0 << 2;
*valp = lsi4x4_0;
return 0;
}
static int
Operand_lsi4x4_encode (uint32 *valp)
{
unsigned r_0, lsi4x4_0;
lsi4x4_0 = *valp;
r_0 = ((lsi4x4_0 >> 2) & 0xf);
*valp = r_0;
return 0;
}
static int
Operand_simm7_decode (uint32 *valp)
{
unsigned simm7_0, imm7_0;
imm7_0 = *valp & 0x7f;
simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
*valp = simm7_0;
return 0;
}
static int
Operand_simm7_encode (uint32 *valp)
{
unsigned imm7_0, simm7_0;
simm7_0 = *valp;
imm7_0 = (simm7_0 & 0x7f);
*valp = imm7_0;
return 0;
}
static int
Operand_uimm6_decode (uint32 *valp)
{
unsigned uimm6_0, imm6_0;
imm6_0 = *valp & 0x3f;
uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
*valp = uimm6_0;
return 0;
}
static int
Operand_uimm6_encode (uint32 *valp)
{
unsigned imm6_0, uimm6_0;
uimm6_0 = *valp;
imm6_0 = (uimm6_0 - 0x4) & 0x3f;
*valp = imm6_0;
return 0;
}
static int
Operand_uimm6_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_ai4const_decode (uint32 *valp)
{
unsigned ai4const_0, t_0;
t_0 = *valp & 0xf;
ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
*valp = ai4const_0;
return 0;
}
static int
Operand_ai4const_encode (uint32 *valp)
{
unsigned t_0, ai4const_0;
ai4const_0 = *valp;
switch (ai4const_0)
{
case 0xffffffff: t_0 = 0; break;
case 0x1: t_0 = 0x1; break;
case 0x2: t_0 = 0x2; break;
case 0x3: t_0 = 0x3; break;
case 0x4: t_0 = 0x4; break;
case 0x5: t_0 = 0x5; break;
case 0x6: t_0 = 0x6; break;
case 0x7: t_0 = 0x7; break;
case 0x8: t_0 = 0x8; break;
case 0x9: t_0 = 0x9; break;
case 0xa: t_0 = 0xa; break;
case 0xb: t_0 = 0xb; break;
case 0xc: t_0 = 0xc; break;
case 0xd: t_0 = 0xd; break;
case 0xe: t_0 = 0xe; break;
default: t_0 = 0xf; break;
}
*valp = t_0;
return 0;
}
static int
Operand_b4const_decode (uint32 *valp)
{
unsigned b4const_0, r_0;
r_0 = *valp & 0xf;
b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
*valp = b4const_0;
return 0;
}
static int
Operand_b4const_encode (uint32 *valp)
{
unsigned r_0, b4const_0;
b4const_0 = *valp;
switch (b4const_0)
{
case 0xffffffff: r_0 = 0; break;
case 0x1: r_0 = 0x1; break;
case 0x2: r_0 = 0x2; break;
case 0x3: r_0 = 0x3; break;
case 0x4: r_0 = 0x4; break;
case 0x5: r_0 = 0x5; break;
case 0x6: r_0 = 0x6; break;
case 0x7: r_0 = 0x7; break;
case 0x8: r_0 = 0x8; break;
case 0xa: r_0 = 0x9; break;
case 0xc: r_0 = 0xa; break;
case 0x10: r_0 = 0xb; break;
case 0x20: r_0 = 0xc; break;
case 0x40: r_0 = 0xd; break;
case 0x80: r_0 = 0xe; break;
default: r_0 = 0xf; break;
}
*valp = r_0;
return 0;
}
static int
Operand_b4constu_decode (uint32 *valp)
{
unsigned b4constu_0, r_0;
r_0 = *valp & 0xf;
b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
*valp = b4constu_0;
return 0;
}
static int
Operand_b4constu_encode (uint32 *valp)
{
unsigned r_0, b4constu_0;
b4constu_0 = *valp;
switch (b4constu_0)
{
case 0x8000: r_0 = 0; break;
case 0x10000: r_0 = 0x1; break;
case 0x2: r_0 = 0x2; break;
case 0x3: r_0 = 0x3; break;
case 0x4: r_0 = 0x4; break;
case 0x5: r_0 = 0x5; break;
case 0x6: r_0 = 0x6; break;
case 0x7: r_0 = 0x7; break;
case 0x8: r_0 = 0x8; break;
case 0xa: r_0 = 0x9; break;
case 0xc: r_0 = 0xa; break;
case 0x10: r_0 = 0xb; break;
case 0x20: r_0 = 0xc; break;
case 0x40: r_0 = 0xd; break;
case 0x80: r_0 = 0xe; break;
default: r_0 = 0xf; break;
}
*valp = r_0;
return 0;
}
static int
Operand_uimm8_decode (uint32 *valp)
{
unsigned uimm8_0, imm8_0;
imm8_0 = *valp & 0xff;
uimm8_0 = imm8_0;
*valp = uimm8_0;
return 0;
}
static int
Operand_uimm8_encode (uint32 *valp)
{
unsigned imm8_0, uimm8_0;
uimm8_0 = *valp;
imm8_0 = (uimm8_0 & 0xff);
*valp = imm8_0;
return 0;
}
static int
Operand_uimm8x2_decode (uint32 *valp)
{
unsigned uimm8x2_0, imm8_0;
imm8_0 = *valp & 0xff;
uimm8x2_0 = imm8_0 << 1;
*valp = uimm8x2_0;
return 0;
}
static int
Operand_uimm8x2_encode (uint32 *valp)
{
unsigned imm8_0, uimm8x2_0;
uimm8x2_0 = *valp;
imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
*valp = imm8_0;
return 0;
}
static int
Operand_uimm8x4_decode (uint32 *valp)
{
unsigned uimm8x4_0, imm8_0;
imm8_0 = *valp & 0xff;
uimm8x4_0 = imm8_0 << 2;
*valp = uimm8x4_0;
return 0;
}
static int
Operand_uimm8x4_encode (uint32 *valp)
{
unsigned imm8_0, uimm8x4_0;
uimm8x4_0 = *valp;
imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
*valp = imm8_0;
return 0;
}
static int
Operand_uimm4x16_decode (uint32 *valp)
{
unsigned uimm4x16_0, op2_0;
op2_0 = *valp & 0xf;
uimm4x16_0 = op2_0 << 4;
*valp = uimm4x16_0;
return 0;
}
static int
Operand_uimm4x16_encode (uint32 *valp)
{
unsigned op2_0, uimm4x16_0;
uimm4x16_0 = *valp;
op2_0 = ((uimm4x16_0 >> 4) & 0xf);
*valp = op2_0;
return 0;
}
static int
Operand_simm8_decode (uint32 *valp)
{
unsigned simm8_0, imm8_0;
imm8_0 = *valp & 0xff;
simm8_0 = ((int) imm8_0 << 24) >> 24;
*valp = simm8_0;
return 0;
}
static int
Operand_simm8_encode (uint32 *valp)
{
unsigned imm8_0, simm8_0;
simm8_0 = *valp;
imm8_0 = (simm8_0 & 0xff);
*valp = imm8_0;
return 0;
}
static int
Operand_simm8x256_decode (uint32 *valp)
{
unsigned simm8x256_0, imm8_0;
imm8_0 = *valp & 0xff;
simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
*valp = simm8x256_0;
return 0;
}
static int
Operand_simm8x256_encode (uint32 *valp)
{
unsigned imm8_0, simm8x256_0;
simm8x256_0 = *valp;
imm8_0 = ((simm8x256_0 >> 8) & 0xff);
*valp = imm8_0;
return 0;
}
static int
Operand_simm12b_decode (uint32 *valp)
{
unsigned simm12b_0, imm12b_0;
imm12b_0 = *valp & 0xfff;
simm12b_0 = ((int) imm12b_0 << 20) >> 20;
*valp = simm12b_0;
return 0;
}
static int
Operand_simm12b_encode (uint32 *valp)
{
unsigned imm12b_0, simm12b_0;
simm12b_0 = *valp;
imm12b_0 = (simm12b_0 & 0xfff);
*valp = imm12b_0;
return 0;
}
static int
Operand_msalp32_decode (uint32 *valp)
{
unsigned msalp32_0, sal_0;
sal_0 = *valp & 0x1f;
msalp32_0 = 0x20 - sal_0;
*valp = msalp32_0;
return 0;
}
static int
Operand_msalp32_encode (uint32 *valp)
{
unsigned sal_0, msalp32_0;
msalp32_0 = *valp;
sal_0 = (0x20 - msalp32_0) & 0x1f;
*valp = sal_0;
return 0;
}
static int
Operand_op2p1_decode (uint32 *valp)
{
unsigned op2p1_0, op2_0;
op2_0 = *valp & 0xf;
op2p1_0 = op2_0 + 0x1;
*valp = op2p1_0;
return 0;
}
static int
Operand_op2p1_encode (uint32 *valp)
{
unsigned op2_0, op2p1_0;
op2p1_0 = *valp;
op2_0 = (op2p1_0 - 0x1) & 0xf;
*valp = op2_0;
return 0;
}
static int
Operand_label8_decode (uint32 *valp)
{
unsigned label8_0, imm8_0;
imm8_0 = *valp & 0xff;
label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
*valp = label8_0;
return 0;
}
static int
Operand_label8_encode (uint32 *valp)
{
unsigned imm8_0, label8_0;
label8_0 = *valp;
imm8_0 = (label8_0 - 0x4) & 0xff;
*valp = imm8_0;
return 0;
}
static int
Operand_label8_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_label8_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_ulabel8_decode (uint32 *valp)
{
unsigned ulabel8_0, imm8_0;
imm8_0 = *valp & 0xff;
ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
*valp = ulabel8_0;
return 0;
}
static int
Operand_ulabel8_encode (uint32 *valp)
{
unsigned imm8_0, ulabel8_0;
ulabel8_0 = *valp;
imm8_0 = (ulabel8_0 - 0x4) & 0xff;
*valp = imm8_0;
return 0;
}
static int
Operand_ulabel8_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_label12_decode (uint32 *valp)
{
unsigned label12_0, imm12_0;
imm12_0 = *valp & 0xfff;
label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
*valp = label12_0;
return 0;
}
static int
Operand_label12_encode (uint32 *valp)
{
unsigned imm12_0, label12_0;
label12_0 = *valp;
imm12_0 = (label12_0 - 0x4) & 0xfff;
*valp = imm12_0;
return 0;
}
static int
Operand_label12_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_label12_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_soffset_decode (uint32 *valp)
{
unsigned soffset_0, offset_0;
offset_0 = *valp & 0x3ffff;
soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
*valp = soffset_0;
return 0;
}
static int
Operand_soffset_encode (uint32 *valp)
{
unsigned offset_0, soffset_0;
soffset_0 = *valp;
offset_0 = (soffset_0 - 0x4) & 0x3ffff;
*valp = offset_0;
return 0;
}
static int
Operand_soffset_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_soffset_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_uimm16x4_decode (uint32 *valp)
{
unsigned uimm16x4_0, imm16_0;
imm16_0 = *valp & 0xffff;
uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
*valp = uimm16x4_0;
return 0;
}
static int
Operand_uimm16x4_encode (uint32 *valp)
{
unsigned imm16_0, uimm16x4_0;
uimm16x4_0 = *valp;
imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
*valp = imm16_0;
return 0;
}
static int
Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
{
*valp -= ((pc + 3) & ~0x3);
return 0;
}
static int
Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
{
*valp += ((pc + 3) & ~0x3);
return 0;
}
static int
Operand_immt_decode (uint32 *valp)
{
unsigned immt_0, t_0;
t_0 = *valp & 0xf;
immt_0 = t_0;
*valp = immt_0;
return 0;
}
static int
Operand_immt_encode (uint32 *valp)
{
unsigned t_0, immt_0;
immt_0 = *valp;
t_0 = immt_0 & 0xf;
*valp = t_0;
return 0;
}
static int
Operand_imms_decode (uint32 *valp)
{
unsigned imms_0, s_0;
s_0 = *valp & 0xf;
imms_0 = s_0;
*valp = imms_0;
return 0;
}
static int
Operand_imms_encode (uint32 *valp)
{
unsigned s_0, imms_0;
imms_0 = *valp;
s_0 = imms_0 & 0xf;
*valp = s_0;
return 0;
}
static int
Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_bt_encode (uint32 *valp)
{
int error;
error = (*valp & ~0xf) != 0;
return error;
}
static int
Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_bs_encode (uint32 *valp)
{
int error;
error = (*valp & ~0xf) != 0;
return error;
}
static int
Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_br_encode (uint32 *valp)
{
int error;
error = (*valp & ~0xf) != 0;
return error;
}
static int
Operand_bt2_decode (uint32 *valp)
{
*valp = *valp << 1;
return 0;
}
static int
Operand_bt2_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x7 << 1)) != 0;
*valp = *valp >> 1;
return error;
}
static int
Operand_bs2_decode (uint32 *valp)
{
*valp = *valp << 1;
return 0;
}
static int
Operand_bs2_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x7 << 1)) != 0;
*valp = *valp >> 1;
return error;
}
static int
Operand_br2_decode (uint32 *valp)
{
*valp = *valp << 1;
return 0;
}
static int
Operand_br2_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x7 << 1)) != 0;
*valp = *valp >> 1;
return error;
}
static int
Operand_bt4_decode (uint32 *valp)
{
*valp = *valp << 2;
return 0;
}
static int
Operand_bt4_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x3 << 2)) != 0;
*valp = *valp >> 2;
return error;
}
static int
Operand_bs4_decode (uint32 *valp)
{
*valp = *valp << 2;
return 0;
}
static int
Operand_bs4_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x3 << 2)) != 0;
*valp = *valp >> 2;
return error;
}
static int
Operand_br4_decode (uint32 *valp)
{
*valp = *valp << 2;
return 0;
}
static int
Operand_br4_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x3 << 2)) != 0;
*valp = *valp >> 2;
return error;
}
static int
Operand_bt8_decode (uint32 *valp)
{
*valp = *valp << 3;
return 0;
}
static int
Operand_bt8_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x1 << 3)) != 0;
*valp = *valp >> 3;
return error;
}
static int
Operand_bs8_decode (uint32 *valp)
{
*valp = *valp << 3;
return 0;
}
static int
Operand_bs8_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x1 << 3)) != 0;
*valp = *valp >> 3;
return error;
}
static int
Operand_br8_decode (uint32 *valp)
{
*valp = *valp << 3;
return 0;
}
static int
Operand_br8_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0x1 << 3)) != 0;
*valp = *valp >> 3;
return error;
}
static int
Operand_bt16_decode (uint32 *valp)
{
*valp = *valp << 4;
return 0;
}
static int
Operand_bt16_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0 << 4)) != 0;
*valp = *valp >> 4;
return error;
}
static int
Operand_bs16_decode (uint32 *valp)
{
*valp = *valp << 4;
return 0;
}
static int
Operand_bs16_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0 << 4)) != 0;
*valp = *valp >> 4;
return error;
}
static int
Operand_br16_decode (uint32 *valp)
{
*valp = *valp << 4;
return 0;
}
static int
Operand_br16_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0 << 4)) != 0;
*valp = *valp >> 4;
return error;
}
static int
Operand_brall_decode (uint32 *valp)
{
*valp = *valp << 4;
return 0;
}
static int
Operand_brall_encode (uint32 *valp)
{
int error;
error = (*valp & ~(0 << 4)) != 0;
*valp = *valp >> 4;
return error;
}
static int
Operand_tp7_decode (uint32 *valp)
{
unsigned tp7_0, t_0;
t_0 = *valp & 0xf;
tp7_0 = t_0 + 0x7;
*valp = tp7_0;
return 0;
}
static int
Operand_tp7_encode (uint32 *valp)
{
unsigned t_0, tp7_0;
tp7_0 = *valp;
t_0 = (tp7_0 - 0x7) & 0xf;
*valp = t_0;
return 0;
}
static int
Operand_xt_wbr15_label_decode (uint32 *valp)
{
unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
xt_wbr15_imm_0 = *valp & 0x7fff;
xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
*valp = xt_wbr15_label_0;
return 0;
}
static int
Operand_xt_wbr15_label_encode (uint32 *valp)
{
unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
xt_wbr15_label_0 = *valp;
xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
*valp = xt_wbr15_imm_0;
return 0;
}
static int
Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_xt_wbr18_label_decode (uint32 *valp)
{
unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
xt_wbr18_imm_0 = *valp & 0x3ffff;
xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
*valp = xt_wbr18_label_0;
return 0;
}
static int
Operand_xt_wbr18_label_encode (uint32 *valp)
{
unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
xt_wbr18_label_0 = *valp;
xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
*valp = xt_wbr18_imm_0;
return 0;
}
static int
Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
{
*valp -= pc;
return 0;
}
static int
Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
{
*valp += pc;
return 0;
}
static int
Operand_ae_samt32_decode (uint32 *valp)
{
unsigned ae_samt32_0, ftsf14_0;
ftsf14_0 = *valp & 0x1f;
ae_samt32_0 = (0 << 5) | ftsf14_0;
*valp = ae_samt32_0;
return 0;
}
static int
Operand_ae_samt32_encode (uint32 *valp)
{
unsigned ftsf14_0, ae_samt32_0;
ae_samt32_0 = *valp;
ftsf14_0 = (ae_samt32_0 & 0x1f);
*valp = ftsf14_0;
return 0;
}
static int
Operand_pr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_pr0_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x7) != 0;
return error;
}
static int
Operand_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_qr0_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x3) != 0;
return error;
}
static int
Operand_ae_lsimm16_decode (uint32 *valp)
{
unsigned ae_lsimm16_0, t_0;
t_0 = *valp & 0xf;
ae_lsimm16_0 = (((int) t_0 << 28) >> 28) << 1;
*valp = ae_lsimm16_0;
return 0;
}
static int
Operand_ae_lsimm16_encode (uint32 *valp)
{
unsigned t_0, ae_lsimm16_0;
ae_lsimm16_0 = *valp;
t_0 = ((ae_lsimm16_0 >> 1) & 0xf);
*valp = t_0;
return 0;
}
static int
Operand_ae_lsimm32_decode (uint32 *valp)
{
unsigned ae_lsimm32_0, t_0;
t_0 = *valp & 0xf;
ae_lsimm32_0 = (((int) t_0 << 28) >> 28) << 2;
*valp = ae_lsimm32_0;
return 0;
}
static int
Operand_ae_lsimm32_encode (uint32 *valp)
{
unsigned t_0, ae_lsimm32_0;
ae_lsimm32_0 = *valp;
t_0 = ((ae_lsimm32_0 >> 2) & 0xf);
*valp = t_0;
return 0;
}
static int
Operand_ae_lsimm64_decode (uint32 *valp)
{
unsigned ae_lsimm64_0, t_0;
t_0 = *valp & 0xf;
ae_lsimm64_0 = (((int) t_0 << 28) >> 28) << 3;
*valp = ae_lsimm64_0;
return 0;
}
static int
Operand_ae_lsimm64_encode (uint32 *valp)
{
unsigned t_0, ae_lsimm64_0;
ae_lsimm64_0 = *valp;
t_0 = ((ae_lsimm64_0 >> 3) & 0xf);
*valp = t_0;
return 0;
}
static int
Operand_ae_samt64_decode (uint32 *valp)
{
unsigned ae_samt64_0, ae_samt_s_t_0;
ae_samt_s_t_0 = *valp & 0x3f;
ae_samt64_0 = (0 << 6) | ae_samt_s_t_0;
*valp = ae_samt64_0;
return 0;
}
static int
Operand_ae_samt64_encode (uint32 *valp)
{
unsigned ae_samt_s_t_0, ae_samt64_0;
ae_samt64_0 = *valp;
ae_samt_s_t_0 = (ae_samt64_0 & 0x3f);
*valp = ae_samt_s_t_0;
return 0;
}
static int
Operand_ae_ohba_decode (uint32 *valp)
{
unsigned ae_ohba_0, op1_0;
op1_0 = *valp & 0xf;
ae_ohba_0 = (0 << 5) | (((((op1_0 & 0xf))) == 0) << 4) | ((op1_0 & 0xf));
*valp = ae_ohba_0;
return 0;
}
static int
Operand_ae_ohba_encode (uint32 *valp)
{
unsigned op1_0, ae_ohba_0;
ae_ohba_0 = *valp;
op1_0 = (ae_ohba_0 & 0xf);
*valp = op1_0;
return 0;
}
static int
Operand_pr_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_pr_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x7) != 0;
return error;
}
static int
Operand_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_qr0_rw_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x3) != 0;
return error;
}
static int
Operand_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_qr1_w_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x3) != 0;
return error;
}
static int
Operand_ps_decode (uint32 *valp ATTRIBUTE_UNUSED)
{
return 0;
}
static int
Operand_ps_encode (uint32 *valp)
{
int error;
error = (*valp & ~0x7) != 0;
return error;
}
static xtensa_operand_internal operands[] = {
{ "soffsetx4", FIELD_offset, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_soffsetx4_encode, Operand_soffsetx4_decode,
Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
{ "uimm12x8", FIELD_imm12, -1, 0,
0,
Operand_uimm12x8_encode, Operand_uimm12x8_decode,
0, 0 },
{ "simm4", FIELD_mn, -1, 0,
0,
Operand_simm4_encode, Operand_simm4_decode,
0, 0 },
{ "arr", FIELD_r, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_arr_encode, Operand_arr_decode,
0, 0 },
{ "ars", FIELD_s, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_ars_encode, Operand_ars_decode,
0, 0 },
{ "*ars_invisible", FIELD_s, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
Operand_ars_encode, Operand_ars_decode,
0, 0 },
{ "art", FIELD_t, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_art_encode, Operand_art_decode,
0, 0 },
{ "ar0", FIELD__ar0, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
Operand_ar0_encode, Operand_ar0_decode,
0, 0 },
{ "ar4", FIELD__ar4, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
Operand_ar4_encode, Operand_ar4_decode,
0, 0 },
{ "ar8", FIELD__ar8, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
Operand_ar8_encode, Operand_ar8_decode,
0, 0 },
{ "ar12", FIELD__ar12, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
Operand_ar12_encode, Operand_ar12_decode,
0, 0 },
{ "ars_entry", FIELD_s, REGFILE_AR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_ars_entry_encode, Operand_ars_entry_decode,
0, 0 },
{ "immrx4", FIELD_r, -1, 0,
0,
Operand_immrx4_encode, Operand_immrx4_decode,
0, 0 },
{ "lsi4x4", FIELD_r, -1, 0,
0,
Operand_lsi4x4_encode, Operand_lsi4x4_decode,
0, 0 },
{ "simm7", FIELD_imm7, -1, 0,
0,
Operand_simm7_encode, Operand_simm7_decode,
0, 0 },
{ "uimm6", FIELD_imm6, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_uimm6_encode, Operand_uimm6_decode,
Operand_uimm6_ator, Operand_uimm6_rtoa },
{ "ai4const", FIELD_t, -1, 0,
0,
Operand_ai4const_encode, Operand_ai4const_decode,
0, 0 },
{ "b4const", FIELD_r, -1, 0,
0,
Operand_b4const_encode, Operand_b4const_decode,
0, 0 },
{ "b4constu", FIELD_r, -1, 0,
0,
Operand_b4constu_encode, Operand_b4constu_decode,
0, 0 },
{ "uimm8", FIELD_imm8, -1, 0,
0,
Operand_uimm8_encode, Operand_uimm8_decode,
0, 0 },
{ "uimm8x2", FIELD_imm8, -1, 0,
0,
Operand_uimm8x2_encode, Operand_uimm8x2_decode,
0, 0 },
{ "uimm8x4", FIELD_imm8, -1, 0,
0,
Operand_uimm8x4_encode, Operand_uimm8x4_decode,
0, 0 },
{ "uimm4x16", FIELD_op2, -1, 0,
0,
Operand_uimm4x16_encode, Operand_uimm4x16_decode,
0, 0 },
{ "simm8", FIELD_imm8, -1, 0,
0,
Operand_simm8_encode, Operand_simm8_decode,
0, 0 },
{ "simm8x256", FIELD_imm8, -1, 0,
0,
Operand_simm8x256_encode, Operand_simm8x256_decode,
0, 0 },
{ "simm12b", FIELD_imm12b, -1, 0,
0,
Operand_simm12b_encode, Operand_simm12b_decode,
0, 0 },
{ "msalp32", FIELD_sal, -1, 0,
0,
Operand_msalp32_encode, Operand_msalp32_decode,
0, 0 },
{ "op2p1", FIELD_op2, -1, 0,
0,
Operand_op2p1_encode, Operand_op2p1_decode,
0, 0 },
{ "label8", FIELD_imm8, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_label8_encode, Operand_label8_decode,
Operand_label8_ator, Operand_label8_rtoa },
{ "ulabel8", FIELD_imm8, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_ulabel8_encode, Operand_ulabel8_decode,
Operand_ulabel8_ator, Operand_ulabel8_rtoa },
{ "label12", FIELD_imm12, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_label12_encode, Operand_label12_decode,
Operand_label12_ator, Operand_label12_rtoa },
{ "soffset", FIELD_offset, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_soffset_encode, Operand_soffset_decode,
Operand_soffset_ator, Operand_soffset_rtoa },
{ "uimm16x4", FIELD_imm16, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_uimm16x4_encode, Operand_uimm16x4_decode,
Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
{ "immt", FIELD_t, -1, 0,
0,
Operand_immt_encode, Operand_immt_decode,
0, 0 },
{ "imms", FIELD_s, -1, 0,
0,
Operand_imms_encode, Operand_imms_decode,
0, 0 },
{ "bt", FIELD_t, REGFILE_BR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_bt_encode, Operand_bt_decode,
0, 0 },
{ "bs", FIELD_s, REGFILE_BR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_bs_encode, Operand_bs_decode,
0, 0 },
{ "br", FIELD_r, REGFILE_BR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_br_encode, Operand_br_decode,
0, 0 },
{ "bt2", FIELD_t2, REGFILE_BR, 2,
XTENSA_OPERAND_IS_REGISTER,
Operand_bt2_encode, Operand_bt2_decode,
0, 0 },
{ "bs2", FIELD_s2, REGFILE_BR, 2,
XTENSA_OPERAND_IS_REGISTER,
Operand_bs2_encode, Operand_bs2_decode,
0, 0 },
{ "br2", FIELD_r2, REGFILE_BR, 2,
XTENSA_OPERAND_IS_REGISTER,
Operand_br2_encode, Operand_br2_decode,
0, 0 },
{ "bt4", FIELD_t4, REGFILE_BR, 4,
XTENSA_OPERAND_IS_REGISTER,
Operand_bt4_encode, Operand_bt4_decode,
0, 0 },
{ "bs4", FIELD_s4, REGFILE_BR, 4,
XTENSA_OPERAND_IS_REGISTER,
Operand_bs4_encode, Operand_bs4_decode,
0, 0 },
{ "br4", FIELD_r4, REGFILE_BR, 4,
XTENSA_OPERAND_IS_REGISTER,
Operand_br4_encode, Operand_br4_decode,
0, 0 },
{ "bt8", FIELD_t8, REGFILE_BR, 8,
XTENSA_OPERAND_IS_REGISTER,
Operand_bt8_encode, Operand_bt8_decode,
0, 0 },
{ "bs8", FIELD_s8, REGFILE_BR, 8,
XTENSA_OPERAND_IS_REGISTER,
Operand_bs8_encode, Operand_bs8_decode,
0, 0 },
{ "br8", FIELD_r8, REGFILE_BR, 8,
XTENSA_OPERAND_IS_REGISTER,
Operand_br8_encode, Operand_br8_decode,
0, 0 },
{ "bt16", FIELD__bt16, REGFILE_BR, 16,
XTENSA_OPERAND_IS_REGISTER,
Operand_bt16_encode, Operand_bt16_decode,
0, 0 },
{ "bs16", FIELD__bs16, REGFILE_BR, 16,
XTENSA_OPERAND_IS_REGISTER,
Operand_bs16_encode, Operand_bs16_decode,
0, 0 },
{ "br16", FIELD__br16, REGFILE_BR, 16,
XTENSA_OPERAND_IS_REGISTER,
Operand_br16_encode, Operand_br16_decode,
0, 0 },
{ "brall", FIELD__brall, REGFILE_BR, 16,
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
Operand_brall_encode, Operand_brall_decode,
0, 0 },
{ "tp7", FIELD_t, -1, 0,
0,
Operand_tp7_encode, Operand_tp7_decode,
0, 0 },
{ "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
{ "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
XTENSA_OPERAND_IS_PCRELATIVE,
Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
{ "ae_samt32", FIELD_ftsf14, -1, 0,
0,
Operand_ae_samt32_encode, Operand_ae_samt32_decode,
0, 0 },
{ "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_pr0_encode, Operand_pr0_decode,
0, 0 },
{ "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_qr0_encode, Operand_qr0_decode,
0, 0 },
{ "ae_lsimm16", FIELD_t, -1, 0,
0,
Operand_ae_lsimm16_encode, Operand_ae_lsimm16_decode,
0, 0 },
{ "ae_lsimm32", FIELD_t, -1, 0,
0,
Operand_ae_lsimm32_encode, Operand_ae_lsimm32_decode,
0, 0 },
{ "ae_lsimm64", FIELD_t, -1, 0,
0,
Operand_ae_lsimm64_encode, Operand_ae_lsimm64_decode,
0, 0 },
{ "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
0,
Operand_ae_samt64_encode, Operand_ae_samt64_decode,
0, 0 },
{ "ae_ohba", FIELD_op1, -1, 0,
0,
Operand_ae_ohba_encode, Operand_ae_ohba_decode,
0, 0 },
{ "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_pr_encode, Operand_pr_decode,
0, 0 },
{ "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_qr0_rw_encode, Operand_qr0_rw_decode,
0, 0 },
{ "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_qr1_w_encode, Operand_qr1_w_decode,
0, 0 },
{ "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
XTENSA_OPERAND_IS_REGISTER,
Operand_ps_encode, Operand_ps_decode,
0, 0 },
{ "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
{ "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
{ "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
{ "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
{ "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
{ "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
{ "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
{ "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
{ "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
{ "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
{ "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
{ "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
{ "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
{ "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
{ "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
{ "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
{ "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
{ "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
{ "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
{ "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
{ "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
{ "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
{ "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
{ "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
{ "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
{ "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
{ "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
{ "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
{ "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
{ "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
{ "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
{ "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
{ "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
{ "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
{ "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
{ "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
{ "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
{ "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
{ "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
{ "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
{ "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
{ "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
{ "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
{ "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
{ "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
{ "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
{ "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
{ "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf208", FIELD_ftsf208, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf209ae_slot1", FIELD_ftsf209ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf211ae_slot1", FIELD_ftsf211ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf330ae_slot1", FIELD_ftsf330ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf332ae_slot1", FIELD_ftsf332ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf338", FIELD_ftsf338, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf340", FIELD_ftsf340, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf346ae_slot1", FIELD_ftsf346ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf347", FIELD_ftsf347, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
{ "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf216ae_slot0", FIELD_ftsf216ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf217", FIELD_ftsf217, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
{ "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }
};
enum xtensa_operand_id {
OPERAND_soffsetx4,
OPERAND_uimm12x8,
OPERAND_simm4,
OPERAND_arr,
OPERAND_ars,
OPERAND__ars_invisible,
OPERAND_art,
OPERAND_ar0,
OPERAND_ar4,
OPERAND_ar8,
OPERAND_ar12,
OPERAND_ars_entry,
OPERAND_immrx4,
OPERAND_lsi4x4,
OPERAND_simm7,
OPERAND_uimm6,
OPERAND_ai4const,
OPERAND_b4const,
OPERAND_b4constu,
OPERAND_uimm8,
OPERAND_uimm8x2,
OPERAND_uimm8x4,
OPERAND_uimm4x16,
OPERAND_simm8,
OPERAND_simm8x256,
OPERAND_simm12b,
OPERAND_msalp32,
OPERAND_op2p1,
OPERAND_label8,
OPERAND_ulabel8,
OPERAND_label12,
OPERAND_soffset,
OPERAND_uimm16x4,
OPERAND_immt,
OPERAND_imms,
OPERAND_bt,
OPERAND_bs,
OPERAND_br,
OPERAND_bt2,
OPERAND_bs2,
OPERAND_br2,
OPERAND_bt4,
OPERAND_bs4,
OPERAND_br4,
OPERAND_bt8,
OPERAND_bs8,
OPERAND_br8,
OPERAND_bt16,
OPERAND_bs16,
OPERAND_br16,
OPERAND_brall,
OPERAND_tp7,
OPERAND_xt_wbr15_label,
OPERAND_xt_wbr18_label,
OPERAND_ae_samt32,
OPERAND_pr0,
OPERAND_qr0,
OPERAND_ae_lsimm16,
OPERAND_ae_lsimm32,
OPERAND_ae_lsimm64,
OPERAND_ae_samt64,
OPERAND_ae_ohba,
OPERAND_pr,
OPERAND_qr0_rw,
OPERAND_qr1_w,
OPERAND_ps,
OPERAND_t,
OPERAND_bbi4,
OPERAND_bbi,
OPERAND_imm12,
OPERAND_imm8,
OPERAND_s,
OPERAND_imm12b,
OPERAND_imm16,
OPERAND_m,
OPERAND_n,
OPERAND_offset,
OPERAND_op0,
OPERAND_op1,
OPERAND_op2,
OPERAND_r,
OPERAND_sa4,
OPERAND_sae4,
OPERAND_sae,
OPERAND_sal,
OPERAND_sargt,
OPERAND_sas4,
OPERAND_sas,
OPERAND_sr,
OPERAND_st,
OPERAND_thi3,
OPERAND_imm4,
OPERAND_mn,
OPERAND_i,
OPERAND_imm6lo,
OPERAND_imm6hi,
OPERAND_imm7lo,
OPERAND_imm7hi,
OPERAND_z,
OPERAND_imm6,
OPERAND_imm7,
OPERAND_t2,
OPERAND_s2,
OPERAND_r2,
OPERAND_t4,
OPERAND_s4,
OPERAND_r4,
OPERAND_t8,
OPERAND_s8,
OPERAND_r8,
OPERAND_xt_wbr15_imm,
OPERAND_xt_wbr18_imm,
OPERAND_ae_r3,
OPERAND_ae_s_non_samt,
OPERAND_ae_s3,
OPERAND_ae_r32,
OPERAND_ae_samt_s_t,
OPERAND_ae_r20,
OPERAND_ae_r10,
OPERAND_ae_s20,
OPERAND_op0_s3,
OPERAND_ftsf12,
OPERAND_ftsf13,
OPERAND_ftsf14,
OPERAND_ftsf21ae_slot1,
OPERAND_ftsf22ae_slot1,
OPERAND_ftsf23ae_slot1,
OPERAND_ftsf24ae_slot1,
OPERAND_ftsf25ae_slot1,
OPERAND_ftsf26ae_slot1,
OPERAND_ftsf27ae_slot1,
OPERAND_ftsf28ae_slot1,
OPERAND_ftsf29ae_slot1,
OPERAND_ftsf30ae_slot1,
OPERAND_ftsf31ae_slot1,
OPERAND_ftsf32ae_slot1,
OPERAND_ftsf33ae_slot1,
OPERAND_ftsf34ae_slot1,
OPERAND_ftsf35ae_slot1,
OPERAND_ftsf36ae_slot1,
OPERAND_ftsf37ae_slot1,
OPERAND_ftsf38ae_slot1,
OPERAND_ftsf39ae_slot1,
OPERAND_ftsf40ae_slot1,
OPERAND_ftsf41ae_slot1,
OPERAND_ftsf42ae_slot1,
OPERAND_ftsf43ae_slot1,
OPERAND_ftsf44ae_slot1,
OPERAND_ftsf45ae_slot1,
OPERAND_ftsf46ae_slot1,
OPERAND_ftsf47ae_slot1,
OPERAND_ftsf48ae_slot1,
OPERAND_ftsf49ae_slot1,
OPERAND_ftsf50ae_slot1,
OPERAND_ftsf51ae_slot1,
OPERAND_ftsf52ae_slot1,
OPERAND_ftsf53ae_slot1,
OPERAND_ftsf54ae_slot1,
OPERAND_ftsf55ae_slot1,
OPERAND_ftsf56ae_slot1,
OPERAND_ftsf57ae_slot1,
OPERAND_ftsf58ae_slot1,
OPERAND_ftsf59ae_slot1,
OPERAND_ftsf60ae_slot1,
OPERAND_ftsf61ae_slot1,
OPERAND_ftsf63ae_slot1,
OPERAND_ftsf64ae_slot1,
OPERAND_ftsf66ae_slot1,
OPERAND_ftsf67ae_slot1,
OPERAND_ftsf69ae_slot1,
OPERAND_ftsf71ae_slot1,
OPERAND_ftsf72ae_slot1,
OPERAND_ftsf73ae_slot1,
OPERAND_ftsf75ae_slot1,
OPERAND_ftsf76ae_slot1,
OPERAND_ftsf77ae_slot1,
OPERAND_ftsf78ae_slot1,
OPERAND_ftsf79ae_slot1,
OPERAND_ftsf80ae_slot1,
OPERAND_ftsf81ae_slot1,
OPERAND_ftsf82ae_slot1,
OPERAND_ftsf84ae_slot1,
OPERAND_ftsf86ae_slot1,
OPERAND_ftsf87ae_slot1,
OPERAND_ftsf88ae_slot1,
OPERAND_ftsf89ae_slot1,
OPERAND_ftsf90ae_slot1,
OPERAND_ftsf91ae_slot1,
OPERAND_ftsf92ae_slot1,
OPERAND_ftsf94ae_slot1,
OPERAND_ftsf96ae_slot1,
OPERAND_ftsf97ae_slot1,
OPERAND_ftsf98ae_slot1,
OPERAND_ftsf99ae_slot1,
OPERAND_ftsf100ae_slot1,
OPERAND_ftsf101ae_slot1,
OPERAND_ftsf103ae_slot1,
OPERAND_ftsf104ae_slot1,
OPERAND_ftsf105ae_slot1,
OPERAND_ftsf106ae_slot1,
OPERAND_ftsf107ae_slot1,
OPERAND_ftsf108ae_slot1,
OPERAND_ftsf109ae_slot1,
OPERAND_ftsf110ae_slot1,
OPERAND_ftsf111ae_slot1,
OPERAND_ftsf112ae_slot1,
OPERAND_ftsf113ae_slot1,
OPERAND_ftsf114ae_slot1,
OPERAND_ftsf115ae_slot1,
OPERAND_ftsf116ae_slot1,
OPERAND_ftsf118ae_slot1,
OPERAND_ftsf119ae_slot1,
OPERAND_ftsf120ae_slot1,
OPERAND_ftsf122ae_slot1,
OPERAND_ftsf124ae_slot1,
OPERAND_ftsf125ae_slot1,
OPERAND_ftsf126ae_slot1,
OPERAND_ftsf127ae_slot1,
OPERAND_ftsf128ae_slot1,
OPERAND_ftsf129ae_slot1,
OPERAND_ftsf130ae_slot1,
OPERAND_ftsf131ae_slot1,
OPERAND_ftsf132ae_slot1,
OPERAND_ftsf133ae_slot1,
OPERAND_ftsf134ae_slot1,
OPERAND_ftsf135ae_slot1,
OPERAND_ftsf136ae_slot1,
OPERAND_ftsf137ae_slot1,
OPERAND_ftsf138ae_slot1,
OPERAND_ftsf139ae_slot1,
OPERAND_ftsf140ae_slot1,
OPERAND_ftsf141ae_slot1,
OPERAND_ftsf142ae_slot1,
OPERAND_ftsf143ae_slot1,
OPERAND_ftsf144ae_slot1,
OPERAND_ftsf145ae_slot1,
OPERAND_ftsf146ae_slot1,
OPERAND_ftsf147ae_slot1,
OPERAND_ftsf148ae_slot1,
OPERAND_ftsf149ae_slot1,
OPERAND_ftsf150ae_slot1,
OPERAND_ftsf151ae_slot1,
OPERAND_ftsf152ae_slot1,
OPERAND_ftsf153ae_slot1,
OPERAND_ftsf154ae_slot1,
OPERAND_ftsf155ae_slot1,
OPERAND_ftsf156ae_slot1,
OPERAND_ftsf157ae_slot1,
OPERAND_ftsf158ae_slot1,
OPERAND_ftsf159ae_slot1,
OPERAND_ftsf160ae_slot1,
OPERAND_ftsf161ae_slot1,
OPERAND_ftsf162ae_slot1,
OPERAND_ftsf163ae_slot1,
OPERAND_ftsf164ae_slot1,
OPERAND_ftsf165ae_slot1,
OPERAND_ftsf166ae_slot1,
OPERAND_ftsf167ae_slot1,
OPERAND_ftsf168ae_slot1,
OPERAND_ftsf169ae_slot1,
OPERAND_ftsf170ae_slot1,
OPERAND_ftsf171ae_slot1,
OPERAND_ftsf172ae_slot1,
OPERAND_ftsf173ae_slot1,
OPERAND_ftsf174ae_slot1,
OPERAND_ftsf175ae_slot1,
OPERAND_ftsf176ae_slot1,
OPERAND_ftsf177ae_slot1,
OPERAND_ftsf178ae_slot1,
OPERAND_ftsf179ae_slot1,
OPERAND_ftsf180ae_slot1,
OPERAND_ftsf181ae_slot1,
OPERAND_ftsf182ae_slot1,
OPERAND_ftsf183ae_slot1,
OPERAND_ftsf184ae_slot1,
OPERAND_ftsf185ae_slot1,
OPERAND_ftsf186ae_slot1,
OPERAND_ftsf187ae_slot1,
OPERAND_ftsf188ae_slot1,
OPERAND_ftsf189ae_slot1,
OPERAND_ftsf190ae_slot1,
OPERAND_ftsf191ae_slot1,
OPERAND_ftsf192ae_slot1,
OPERAND_ftsf193ae_slot1,
OPERAND_ftsf194ae_slot1,
OPERAND_ftsf195ae_slot1,
OPERAND_ftsf196ae_slot1,
OPERAND_ftsf197ae_slot1,
OPERAND_ftsf198ae_slot1,
OPERAND_ftsf199ae_slot1,
OPERAND_ftsf200ae_slot1,
OPERAND_ftsf201ae_slot1,
OPERAND_ftsf202ae_slot1,
OPERAND_ftsf203ae_slot1,
OPERAND_ftsf204ae_slot1,
OPERAND_ftsf205ae_slot1,
OPERAND_ftsf206ae_slot1,
OPERAND_ftsf207ae_slot1,
OPERAND_ftsf208,
OPERAND_ftsf209ae_slot1,
OPERAND_ftsf210ae_slot1,
OPERAND_ftsf211ae_slot1,
OPERAND_ftsf330ae_slot1,
OPERAND_ftsf332ae_slot1,
OPERAND_ftsf334ae_slot1,
OPERAND_ftsf336ae_slot1,
OPERAND_ftsf337ae_slot1,
OPERAND_ftsf338,
OPERAND_ftsf339ae_slot1,
OPERAND_ftsf340,
OPERAND_ftsf341ae_slot1,
OPERAND_ftsf342ae_slot1,
OPERAND_ftsf343ae_slot1,
OPERAND_ftsf344ae_slot1,
OPERAND_ftsf346ae_slot1,
OPERAND_ftsf347,
OPERAND_ftsf348ae_slot1,
OPERAND_ftsf349ae_slot1,
OPERAND_ftsf350ae_slot1,
OPERAND_op0_s4,
OPERAND_ftsf212ae_slot0,
OPERAND_ftsf213ae_slot0,
OPERAND_ftsf214ae_slot0,
OPERAND_ftsf215ae_slot0,
OPERAND_ftsf216ae_slot0,
OPERAND_ftsf217,
OPERAND_ftsf218ae_slot0,
OPERAND_ftsf219ae_slot0,
OPERAND_ftsf220ae_slot0,
OPERAND_ftsf221ae_slot0,
OPERAND_ftsf222ae_slot0,
OPERAND_ftsf223ae_slot0,
OPERAND_ftsf224ae_slot0,
OPERAND_ftsf225ae_slot0,
OPERAND_ftsf226ae_slot0,
OPERAND_ftsf227ae_slot0,
OPERAND_ftsf228ae_slot0,
OPERAND_ftsf229ae_slot0,
OPERAND_ftsf230ae_slot0,
OPERAND_ftsf231ae_slot0,
OPERAND_ftsf232ae_slot0,
OPERAND_ftsf233ae_slot0,
OPERAND_ftsf234ae_slot0,
OPERAND_ftsf235ae_slot0,
OPERAND_ftsf236ae_slot0,
OPERAND_ftsf237ae_slot0,
OPERAND_ftsf238ae_slot0,
OPERAND_ftsf239ae_slot0,
OPERAND_ftsf240ae_slot0,
OPERAND_ftsf241ae_slot0,
OPERAND_ftsf242ae_slot0,
OPERAND_ftsf243ae_slot0,
OPERAND_ftsf244ae_slot0,
OPERAND_ftsf245ae_slot0,
OPERAND_ftsf246ae_slot0,
OPERAND_ftsf247ae_slot0,
OPERAND_ftsf248ae_slot0,
OPERAND_ftsf249ae_slot0,
OPERAND_ftsf250ae_slot0,
OPERAND_ftsf251ae_slot0,
OPERAND_ftsf252ae_slot0,
OPERAND_ftsf253ae_slot0,
OPERAND_ftsf254ae_slot0,
OPERAND_ftsf255ae_slot0,
OPERAND_ftsf256ae_slot0,
OPERAND_ftsf257ae_slot0,
OPERAND_ftsf258ae_slot0,
OPERAND_ftsf259ae_slot0,
OPERAND_ftsf260ae_slot0,
OPERAND_ftsf261ae_slot0,
OPERAND_ftsf262ae_slot0,
OPERAND_ftsf263ae_slot0,
OPERAND_ftsf264ae_slot0,
OPERAND_ftsf265ae_slot0,
OPERAND_ftsf266ae_slot0,
OPERAND_ftsf267ae_slot0,
OPERAND_ftsf268ae_slot0,
OPERAND_ftsf269ae_slot0,
OPERAND_ftsf270ae_slot0,
OPERAND_ftsf271ae_slot0,
OPERAND_ftsf272ae_slot0,
OPERAND_ftsf273ae_slot0,
OPERAND_ftsf274ae_slot0,
OPERAND_ftsf275ae_slot0,
OPERAND_ftsf276ae_slot0,
OPERAND_ftsf277ae_slot0,
OPERAND_ftsf278ae_slot0,
OPERAND_ftsf279ae_slot0,
OPERAND_ftsf281ae_slot0,
OPERAND_ftsf282ae_slot0,
OPERAND_ftsf283ae_slot0,
OPERAND_ftsf284ae_slot0,
OPERAND_ftsf286ae_slot0,
OPERAND_ftsf288ae_slot0,
OPERAND_ftsf290ae_slot0,
OPERAND_ftsf292ae_slot0,
OPERAND_ftsf293,
OPERAND_ftsf294ae_slot0,
OPERAND_ftsf295ae_slot0,
OPERAND_ftsf296ae_slot0,
OPERAND_ftsf297ae_slot0,
OPERAND_ftsf298ae_slot0,
OPERAND_ftsf299ae_slot0,
OPERAND_ftsf300ae_slot0,
OPERAND_ftsf301ae_slot0,
OPERAND_ftsf302ae_slot0,
OPERAND_ftsf303ae_slot0,
OPERAND_ftsf304ae_slot0,
OPERAND_ftsf306ae_slot0,
OPERAND_ftsf308ae_slot0,
OPERAND_ftsf309ae_slot0,
OPERAND_ftsf310ae_slot0,
OPERAND_ftsf311ae_slot0,
OPERAND_ftsf312ae_slot0,
OPERAND_ftsf313ae_slot0,
OPERAND_ftsf314ae_slot0,
OPERAND_ftsf315ae_slot0,
OPERAND_ftsf316ae_slot0,
OPERAND_ftsf317ae_slot0,
OPERAND_ftsf318ae_slot0,
OPERAND_ftsf319,
OPERAND_ftsf320ae_slot0,
OPERAND_ftsf321,
OPERAND_ftsf322ae_slot0,
OPERAND_ftsf323ae_slot0,
OPERAND_ftsf324ae_slot0,
OPERAND_ftsf325ae_slot0,
OPERAND_ftsf326ae_slot0,
OPERAND_ftsf328ae_slot0,
OPERAND_ftsf329ae_slot0,
OPERAND_ftsf352ae_slot0,
OPERAND_ftsf353,
OPERAND_ftsf354ae_slot0,
OPERAND_ftsf356ae_slot0,
OPERAND_ftsf357,
OPERAND_ftsf358ae_slot0,
OPERAND_ftsf359ae_slot0,
OPERAND_ftsf360ae_slot0,
OPERAND_ftsf361ae_slot0,
OPERAND_ftsf362ae_slot0,
OPERAND_ftsf364ae_slot0,
OPERAND_ftsf365ae_slot0,
OPERAND_ftsf366ae_slot0,
OPERAND_ftsf368ae_slot0,
OPERAND_ftsf369ae_slot0
};
/* Iclass table. */
static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
{ { STATE_PSRING }, 'i' },
{ { STATE_PSEXCM }, 'm' },
{ { STATE_EPC1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEPC }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
{ { OPERAND_soffsetx4 }, 'i' },
{ { OPERAND_ar12 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
{ { STATE_PSCALLINC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
{ { OPERAND_soffsetx4 }, 'i' },
{ { OPERAND_ar8 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
{ { STATE_PSCALLINC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
{ { OPERAND_soffsetx4 }, 'i' },
{ { OPERAND_ar4 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
{ { STATE_PSCALLINC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ar12 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
{ { STATE_PSCALLINC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ar8 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
{ { STATE_PSCALLINC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ar4 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
{ { STATE_PSCALLINC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
{ { OPERAND_ars_entry }, 's' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm12x8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
{ { STATE_PSCALLINC }, 'i' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSWOE }, 'i' },
{ { STATE_WindowBase }, 'm' },
{ { STATE_WindowStart }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
{ { STATE_WindowBase }, 'i' },
{ { STATE_WindowStart }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
{ { OPERAND_simm4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowBase }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
{ { OPERAND__ars_invisible }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
{ { STATE_WindowBase }, 'm' },
{ { STATE_WindowStart }, 'm' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSWOE }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
{ { STATE_EPC1 }, 'i' },
{ { STATE_PSEXCM }, 'm' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowBase }, 'm' },
{ { STATE_WindowStart }, 'm' },
{ { STATE_PSOWB }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_immrx4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_immrx4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowBase }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowBase }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowBase }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowStart }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowStart }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WindowStart }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ai4const }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm6 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_lsi4x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_simm7 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
{ { OPERAND__ars_invisible }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_lsi4x4 }, 'i' }
};
static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
{ { STATE_THREADPTR }, 'i' }
};
static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
{ { STATE_THREADPTR }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_simm8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_simm8x256 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_b4const }, 'i' },
{ { OPERAND_label8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_bbi }, 'i' },
{ { OPERAND_label8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_b4constu }, 'i' },
{ { OPERAND_label8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' },
{ { OPERAND_label8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_label12 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
{ { OPERAND_soffsetx4 }, 'i' },
{ { OPERAND_ar0 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ar0 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_art }, 'i' },
{ { OPERAND_sae }, 'i' },
{ { OPERAND_op2p1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
{ { OPERAND_soffset }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_uimm16x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
{ { STATE_LITBADDR }, 'i' },
{ { STATE_LITBEN }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ulabel8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
{ { STATE_LBEG }, 'o' },
{ { STATE_LEND }, 'o' },
{ { STATE_LCOUNT }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ulabel8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
{ { STATE_LBEG }, 'o' },
{ { STATE_LEND }, 'o' },
{ { STATE_LCOUNT }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_simm12b }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
{ { OPERAND_arr }, 'm' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
{ { OPERAND__ars_invisible }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
{ { STATE_SAR }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
{ { OPERAND_sas }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
{ { STATE_SAR }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
{ { STATE_SAR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
{ { STATE_SAR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
{ { STATE_SAR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_msalp32 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_art }, 'i' },
{ { OPERAND_sargt }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_art }, 'i' },
{ { OPERAND_s }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
{ { STATE_XTSYNC }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_s }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
{ { STATE_PSWOE }, 'i' },
{ { STATE_PSCALLINC }, 'i' },
{ { STATE_PSOWB }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_PSUM }, 'i' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSINTLEVEL }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
{ { STATE_LEND }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
{ { STATE_LEND }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
{ { STATE_LEND }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
{ { STATE_LCOUNT }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_LCOUNT }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_LCOUNT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
{ { STATE_LBEG }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
{ { STATE_LBEG }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
{ { STATE_LBEG }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
{ { STATE_SAR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
{ { STATE_SAR }, 'o' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
{ { STATE_SAR }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
{ { STATE_LITBADDR }, 'i' },
{ { STATE_LITBEN }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
{ { STATE_LITBADDR }, 'o' },
{ { STATE_LITBEN }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
{ { STATE_LITBADDR }, 'm' },
{ { STATE_LITBEN }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
{ { STATE_PSWOE }, 'i' },
{ { STATE_PSCALLINC }, 'i' },
{ { STATE_PSOWB }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_PSUM }, 'i' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSINTLEVEL }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
{ { STATE_PSWOE }, 'o' },
{ { STATE_PSCALLINC }, 'o' },
{ { STATE_PSOWB }, 'o' },
{ { STATE_PSRING }, 'm' },
{ { STATE_PSUM }, 'o' },
{ { STATE_PSEXCM }, 'm' },
{ { STATE_PSINTLEVEL }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
{ { STATE_PSWOE }, 'm' },
{ { STATE_PSCALLINC }, 'm' },
{ { STATE_PSOWB }, 'm' },
{ { STATE_PSRING }, 'm' },
{ { STATE_PSUM }, 'm' },
{ { STATE_PSEXCM }, 'm' },
{ { STATE_PSINTLEVEL }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPC1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPC1 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPC1 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCSAVE1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCSAVE1 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCSAVE1 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPC2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPC2 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPC2 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCSAVE2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCSAVE2 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCSAVE2 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPS2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPS2 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EPS2 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCVADDR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCVADDR }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCVADDR }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEPC }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEPC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEPC }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCCAUSE }, 'i' },
{ { STATE_XTSYNC }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCCAUSE }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_EXCCAUSE }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MISC0 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MISC0 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MISC0 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MISC1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MISC1 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MISC1 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_VECBASE }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_VECBASE }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_VECBASE }, 'm' }
};
static xtensa_arg_internal Iclass_xt_mul16_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_mul32_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
{ { OPERAND_s }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
{ { STATE_PSWOE }, 'o' },
{ { STATE_PSCALLINC }, 'o' },
{ { STATE_PSOWB }, 'o' },
{ { STATE_PSRING }, 'm' },
{ { STATE_PSUM }, 'o' },
{ { STATE_PSEXCM }, 'm' },
{ { STATE_PSINTLEVEL }, 'o' },
{ { STATE_EPC1 }, 'i' },
{ { STATE_EPC2 }, 'i' },
{ { STATE_EPS2 }, 'i' },
{ { STATE_InOCDMode }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
{ { OPERAND_s }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_PSINTLEVEL }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INTERRUPT }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_INTERRUPT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_INTERRUPT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INTENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INTENABLE }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INTENABLE }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
{ { OPERAND_imms }, 'i' },
{ { OPERAND_immt }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSINTLEVEL }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
{ { OPERAND_imms }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSINTLEVEL }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEBUGCAUSE }, 'i' },
{ { STATE_DBNUM }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEBUGCAUSE }, 'o' },
{ { STATE_DBNUM }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DEBUGCAUSE }, 'm' },
{ { STATE_DBNUM }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ICOUNT }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_ICOUNT }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_ICOUNT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ICOUNTLEVEL }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ICOUNTLEVEL }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ICOUNTLEVEL }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DDR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_DDR }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_DDR }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
{ { OPERAND_imms }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
{ { STATE_InOCDMode }, 'm' },
{ { STATE_EPC2 }, 'i' },
{ { STATE_PSWOE }, 'o' },
{ { STATE_PSCALLINC }, 'o' },
{ { STATE_PSOWB }, 'o' },
{ { STATE_PSRING }, 'o' },
{ { STATE_PSUM }, 'o' },
{ { STATE_PSEXCM }, 'o' },
{ { STATE_PSINTLEVEL }, 'o' },
{ { STATE_EPS2 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
{ { STATE_InOCDMode }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
{ { OPERAND_br }, 'o' },
{ { OPERAND_bs }, 'i' },
{ { OPERAND_bt }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
{ { OPERAND_bt }, 'o' },
{ { OPERAND_bs4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
{ { OPERAND_bt }, 'o' },
{ { OPERAND_bs8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
{ { OPERAND_bs }, 'i' },
{ { OPERAND_label8 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
{ { OPERAND_arr }, 'm' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_bt }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_brall }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_brall }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
{ { OPERAND_art }, 'm' },
{ { OPERAND_brall }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOUNT }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_CCOUNT }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' },
{ { STATE_CCOUNT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOMPARE0 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOMPARE0 }, 'o' },
{ { STATE_INTERRUPT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOMPARE0 }, 'm' },
{ { STATE_INTERRUPT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOMPARE1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOMPARE1 }, 'o' },
{ { STATE_INTERRUPT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CCOMPARE1 }, 'm' },
{ { STATE_INTERRUPT }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm4x16 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_PTBASE }, 'o' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_PTBASE }, 'i' },
{ { STATE_EXCVADDR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_PTBASE }, 'm' },
{ { STATE_EXCVADDR }, 'i' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ASID3 }, 'i' },
{ { STATE_ASID2 }, 'i' },
{ { STATE_ASID1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ASID3 }, 'o' },
{ { STATE_ASID2 }, 'o' },
{ { STATE_ASID1 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ASID3 }, 'm' },
{ { STATE_ASID2 }, 'm' },
{ { STATE_ASID1 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INSTPGSZID4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INSTPGSZID4 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_INSTPGSZID4 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DATAPGSZID4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DATAPGSZID4 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
{ { STATE_XTSYNC }, 'o' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_DATAPGSZID4 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
{ { STATE_PTBASE }, 'i' },
{ { STATE_EXCVADDR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
{ { STATE_EXCVADDR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
{ { STATE_EXCVADDR }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CPENABLE }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_CPENABLE }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_tp7 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_tp7 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
{ { OPERAND_art }, 'm' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_uimm8x4 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
{ { STATE_SCOMPARE1 }, 'i' },
{ { STATE_XTSYNC }, 'i' },
{ { STATE_SCOMPARE1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
{ { STATE_SCOMPARE1 }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
{ { STATE_SCOMPARE1 }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
{ { STATE_SCOMPARE1 }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
{ { OPERAND_art }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ATOMCTL }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ATOMCTL }, 'o' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
{ { OPERAND_art }, 'm' }
};
static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_ATOMCTL }, 'm' },
{ { STATE_XTSYNC }, 'o' }
};
static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
{ { STATE_CCON }, 'i' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_MPSCORE }, 'i' }
};
static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
INTERFACE_RMPINT_Out,
INTERFACE_RMPINT_In
};
static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
{ { OPERAND_art }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
{ { STATE_CCON }, 'm' },
{ { STATE_PSEXCM }, 'i' },
{ { STATE_PSRING }, 'i' },
{ { STATE_WMPINT_DATA }, 'o' },
{ { STATE_WMPINT_ADDR }, 'o' },
{ { STATE_MPSCORE }, 'm' },
{ { STATE_WMPINT_TOGGLEEN }, 'm' }
};
static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'i' },
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'o' },
{ { STATE_AE_SAR }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
{ { STATE_AE_BITHEAD }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
{ { STATE_AE_BITHEAD }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITSUSED }, 'i' },
{ { STATE_AE_TABLESIZE }, 'i' },
{ { STATE_AE_FIRST_TS }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'o' },
{ { STATE_AE_BITSUSED }, 'o' },
{ { STATE_AE_TABLESIZE }, 'o' },
{ { STATE_AE_FIRST_TS }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
{ { STATE_AE_NEXTOFFSET }, 'i' },
{ { STATE_AE_SEARCHDONE }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
{ { STATE_AE_NEXTOFFSET }, 'o' },
{ { STATE_AE_SEARCHDONE }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
{ { STATE_AE_SAR }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
{ { STATE_AE_BITSUSED }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
{ { STATE_AE_BITSUSED }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
{ { STATE_AE_TABLESIZE }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
{ { STATE_AE_TABLESIZE }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
{ { STATE_AE_FIRST_TS }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
{ { STATE_AE_FIRST_TS }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
{ { STATE_AE_NEXTOFFSET }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
{ { STATE_AE_NEXTOFFSET }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
{ { OPERAND_arr }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
{ { STATE_AE_SEARCHDONE }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
{ { STATE_AE_SEARCHDONE }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm16 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm16 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm16 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm16 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_lsimm32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
{ { OPERAND_ps }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
{ { OPERAND_pr }, 'm' },
{ { OPERAND_pr0 }, 'i' },
{ { OPERAND_bt2 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
{ { OPERAND_pr }, 'm' },
{ { OPERAND_pr0 }, 'i' },
{ { OPERAND_bt2 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
{ { OPERAND_pr }, 'm' },
{ { OPERAND_pr0 }, 'i' },
{ { OPERAND_bt }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
{ { OPERAND_pr }, 'm' },
{ { OPERAND_pr0 }, 'i' },
{ { OPERAND_bt }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
{ { OPERAND_pr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
{ { OPERAND_qr1_w }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_bs }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_bs }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' },
{ { OPERAND_bt2 }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' },
{ { OPERAND_bt2 }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
{ { OPERAND_bt2 }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
{ { OPERAND_bt2 }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
{ { OPERAND_bt2 }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_bt }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_bt }, 'o' }
};
static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ae_samt32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ae_samt32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ae_samt32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_ae_samt32 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
{ { OPERAND_ps }, 'o' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ae_samt64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ae_samt64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ae_samt64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ae_samt64 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_AE_SAR }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
{ { OPERAND_bt }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
{ { OPERAND_bt }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
{ { OPERAND_bt }, 'o' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
{ { OPERAND_ars }, 'o' },
{ { OPERAND_qr0_rw }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
{ { STATE_AE_OVERFLOW }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_qr0_rw }, 'i' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_qr0 }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'o' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
{ { OPERAND_qr1_w }, 'm' },
{ { OPERAND_pr }, 'i' },
{ { OPERAND_pr0 }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
{ { OPERAND_br }, 'o' },
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
{ { STATE_AE_TABLESIZE }, 'm' },
{ { STATE_AE_BITSUSED }, 'o' },
{ { STATE_AE_NEXTOFFSET }, 'm' },
{ { STATE_AE_SEARCHDONE }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
{ { OPERAND_br }, 'o' },
{ { OPERAND_art }, 'o' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
{ { STATE_AE_TABLESIZE }, 'm' },
{ { STATE_AE_BITSUSED }, 'o' },
{ { STATE_AE_NEXTOFFSET }, 'm' },
{ { STATE_AE_SEARCHDONE }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
{ { OPERAND_ars }, 'm' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
{ { STATE_AE_NEXTOFFSET }, 'm' },
{ { STATE_AE_TABLESIZE }, 'm' },
{ { STATE_AE_BITPTR }, 'm' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_AE_FIRST_TS }, 'i' },
{ { STATE_AE_BITSUSED }, 'i' },
{ { STATE_AE_SEARCHDONE }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITHEAD }, 'i' },
{ { STATE_AE_FIRST_TS }, 'o' },
{ { STATE_AE_NEXTOFFSET }, 'o' },
{ { STATE_AE_TABLESIZE }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITHEAD }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ae_ohba }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITHEAD }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITHEAD }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
{ { OPERAND_arr }, 'o' },
{ { OPERAND_ars }, 'i' },
{ { OPERAND_ae_ohba }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITHEAD }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'm' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
{ { OPERAND_ars }, 'm' },
{ { OPERAND_ae_ohba }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'm' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
{ { OPERAND_br }, 'o' },
{ { OPERAND_art }, 'm' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
{ { STATE_AE_BITSUSED }, 'o' },
{ { STATE_AE_NEXTOFFSET }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
{ { OPERAND_br }, 'o' },
{ { OPERAND_art }, 'm' },
{ { OPERAND_ars }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
{ { STATE_AE_BITSUSED }, 'o' },
{ { STATE_AE_NEXTOFFSET }, 'o' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
{ { STATE_AE_BITSUSED }, 'i' },
{ { STATE_AE_BITPTR }, 'm' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
{ { OPERAND_ars }, 'm' },
{ { OPERAND_art }, 'i' },
{ { OPERAND_ae_ohba }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'm' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
{ { OPERAND_ars }, 'm' }
};
static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'm' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_AE_BITSUSED }, 'i' },
{ { STATE_AE_NEXTOFFSET }, 'i' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
{ { OPERAND_ars }, 'm' }
};
static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
{ { STATE_AE_BITPTR }, 'i' },
{ { STATE_AE_BITHEAD }, 'm' },
{ { STATE_CPENABLE }, 'i' }
};
static xtensa_iclass_internal iclasses[] = {
{ 0, 0 /* xt_iclass_excw */,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_rfe */,
3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_rfde */,
3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_syscall */,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_simcall */,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_call12_args,
1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_call8_args,
1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_call4_args,
1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_callx12_args,
1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_callx8_args,
1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_callx4_args,
1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_entry_args,
5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_movsp_args,
2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rotw_args,
3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_retw_args,
4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_rfwou */,
6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_l32e_args,
2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_s32e_args,
2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_windowbase_args,
3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_windowbase_args,
3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_windowbase_args,
3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_windowstart_args,
3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_windowstart_args,
3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_windowstart_args,
3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_add_n_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_addi_n_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_bz6_args,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_ill_n */,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_loadi4_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_mov_n_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_movi_n_args,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_nopn */,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_retn_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_storei4_args,
0, 0, 0, 0 },
{ 1, Iclass_rur_threadptr_args,
1, Iclass_rur_threadptr_stateArgs, 0, 0 },
{ 1, Iclass_wur_threadptr_args,
1, Iclass_wur_threadptr_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_addi_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_addmi_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_addsub_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_bit_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_bsi8_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_bsi8b_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_bsi8u_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_bst8_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_bsz12_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_call0_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_callx0_args,
0, 0, 0, 0 },
{ 4, Iclass_xt_iclass_exti_args,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_ill */,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_jump_args,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_jumpx_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_l16ui_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_l16si_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_l32i_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_l32r_args,
2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_l8i_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_loop_args,
3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_loopz_args,
3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_movi_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_movz_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_neg_args,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_nop */,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_return_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_s16i_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_s32i_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_s8i_args,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_sar_args,
1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_sari_args,
1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_shifts_args,
1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_shiftst_args,
1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_shiftt_args,
1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_slli_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_srai_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_srli_args,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_memw */,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_extw */,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_isync */,
0, 0, 0, 0 },
{ 0, 0 /* xt_iclass_sync */,
1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_rsil_args,
7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_lend_args,
1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_lend_args,
1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_lend_args,
1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_lcount_args,
1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_lcount_args,
2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_lcount_args,
2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_lbeg_args,
1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_lbeg_args,
1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_lbeg_args,
1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_sar_args,
1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_sar_args,
2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_sar_args,
1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_litbase_args,
2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_litbase_args,
2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_litbase_args,
2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_176_args,
2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_176_args,
2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_208_args,
2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_ps_args,
7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_ps_args,
7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_ps_args,
7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_epc1_args,
3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_epc1_args,
3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_epc1_args,
3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_excsave1_args,
3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_excsave1_args,
3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_excsave1_args,
3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_epc2_args,
3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_epc2_args,
3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_epc2_args,
3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_excsave2_args,
3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_excsave2_args,
3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_excsave2_args,
3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_eps2_args,
3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_eps2_args,
3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_eps2_args,
3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_excvaddr_args,
3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_excvaddr_args,
3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_excvaddr_args,
3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_depc_args,
3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_depc_args,
3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_depc_args,
3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_exccause_args,
4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_exccause_args,
3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_exccause_args,
3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_misc0_args,
3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_misc0_args,
3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_misc0_args,
3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_misc1_args,
3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_misc1_args,
3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_misc1_args,
3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_prid_args,
2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_vecbase_args,
3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_vecbase_args,
3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_vecbase_args,
3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
{ 3, Iclass_xt_mul16_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_mul32_args,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_rfi_args,
11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wait_args,
3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_interrupt_args,
3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_intset_args,
4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_intclear_args,
4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_intenable_args,
3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_intenable_args,
3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_intenable_args,
3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_break_args,
2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_break_n_args,
2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_debugcause_args,
4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_debugcause_args,
4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_debugcause_args,
4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_icount_args,
3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_icount_args,
4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_icount_args,
4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_icountlevel_args,
3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_icountlevel_args,
3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_icountlevel_args,
3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_ddr_args,
3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_ddr_args,
4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_ddr_args,
4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rfdo_args,
10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_rfdd */,
1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_bbool1_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_bbool4_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_bbool8_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_bbranch_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_bmove_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_RSR_BR_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_WSR_BR_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_XSR_BR_args,
0, 0, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_ccount_args,
3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_ccount_args,
4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_ccount_args,
4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_ccompare0_args,
3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_ccompare0_args,
4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_ccompare0_args,
4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_ccompare1_args,
3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_ccompare1_args,
4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_ccompare1_args,
4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_icache_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_icache_inv_args,
2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_licx_args,
2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_sicx_args,
2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_dcache_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_dcache_ind_args,
2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_dcache_inv_args,
2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_dpf_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_sdct_args,
2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_ldct_args,
2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_ptevaddr_args,
4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_ptevaddr_args,
4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_ptevaddr_args,
5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_rasid_args,
5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_rasid_args,
6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_rasid_args,
6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_itlbcfg_args,
3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_itlbcfg_args,
4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_itlbcfg_args,
4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_idtlb_args,
3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_rdtlb_args,
2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_wdtlb_args,
3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_iitlb_args,
2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_ritlb_args,
2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_witlb_args,
2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_ldpte */,
2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_hwwitlba */,
1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
{ 0, 0 /* xt_iclass_hwwdtlba */,
1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_cpenable_args,
3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_cpenable_args,
3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_cpenable_args,
3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
{ 3, Iclass_xt_iclass_clamp_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_minmax_args,
0, 0, 0, 0 },
{ 2, Iclass_xt_iclass_nsa_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_sx_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_l32ai_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_s32ri_args,
0, 0, 0, 0 },
{ 3, Iclass_xt_iclass_s32c1i_args,
3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_scompare1_args,
1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_scompare1_args,
1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_scompare1_args,
1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_rsr_atomctl_args,
3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_wsr_atomctl_args,
4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
{ 1, Iclass_xt_iclass_xsr_atomctl_args,
4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
{ 2, Iclass_xt_iclass_rer_args,
4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
{ 2, Iclass_xt_iclass_wer_args,
7, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
{ 1, Iclass_rur_ae_ovf_sar_args,
3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 },
{ 1, Iclass_wur_ae_ovf_sar_args,
3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 },
{ 1, Iclass_rur_ae_bithead_args,
2, Iclass_rur_ae_bithead_stateArgs, 0, 0 },
{ 1, Iclass_wur_ae_bithead_args,
2, Iclass_wur_ae_bithead_stateArgs, 0, 0 },
{ 1, Iclass_rur_ae_ts_fts_bu_bp_args,
5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
{ 1, Iclass_wur_ae_ts_fts_bu_bp_args,
5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
{ 1, Iclass_rur_ae_sd_no_args,
3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 },
{ 1, Iclass_wur_ae_sd_no_args,
3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_overflow_args,
2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_overflow_args,
2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_sar_args,
2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_sar_args,
2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_bitptr_args,
2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_bitptr_args,
2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_bitsused_args,
2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_bitsused_args,
2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_tablesize_args,
2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_tablesize_args,
2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_first_ts_args,
2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_first_ts_args,
2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_nextoffset_args,
2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_nextoffset_args,
2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_rur_ae_searchdone_args,
2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_wur_ae_searchdone_args,
2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16f_i_args,
1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16f_iu_args,
1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16f_x_args,
1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16f_xu_args,
1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24_i_args,
1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24_iu_args,
1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24_x_args,
1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24_xu_args,
1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24f_i_args,
1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24f_iu_args,
1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24f_x_args,
1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24f_xu_args,
1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16x2f_i_args,
1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16x2f_iu_args,
1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16x2f_x_args,
1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp16x2f_xu_args,
1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2f_i_args,
1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2f_iu_args,
1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2f_x_args,
1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2f_xu_args,
1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2_i_args,
1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2_iu_args,
1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2_x_args,
1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lp24x2_xu_args,
1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16x2f_i_args,
1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16x2f_iu_args,
1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16x2f_x_args,
1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16x2f_xu_args,
1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2s_i_args,
1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2s_iu_args,
1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2s_x_args,
1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2s_xu_args,
1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2f_i_args,
1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2f_iu_args,
1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2f_x_args,
1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24x2f_xu_args,
1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16f_l_i_args,
1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16f_l_iu_args,
1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16f_l_x_args,
1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp16f_l_xu_args,
1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24s_l_i_args,
1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24s_l_iu_args,
1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24s_l_x_args,
1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24s_l_xu_args,
1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24f_l_i_args,
1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24f_l_iu_args,
1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24f_l_x_args,
1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sp24f_l_xu_args,
1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq56_i_args,
1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq56_iu_args,
1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq56_x_args,
1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq56_xu_args,
1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq32f_i_args,
1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq32f_iu_args,
1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq32f_x_args,
1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lq32f_xu_args,
1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq56s_i_args,
1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq56s_iu_args,
1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq56s_x_args,
1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq56s_xu_args,
1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq32f_i_args,
1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq32f_iu_args,
1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq32f_x_args,
1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sq32f_xu_args,
1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_zerop48_args,
1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_movp48_args,
1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_selp24_ll_args,
1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_selp24_lh_args,
1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_selp24_hl_args,
1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_selp24_hh_args,
1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movtp24x2_args,
1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movfp24x2_args,
1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movtp48_args,
1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movfp48_args,
1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movpa24x2_args,
1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_truncp24a32x2_args,
1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_cvta32p24_l_args,
1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_cvta32p24_h_args,
1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_cvtp24a16x2_ll_args,
1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_cvtp24a16x2_lh_args,
1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_cvtp24a16x2_hl_args,
1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_cvtp24a16x2_hh_args,
1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_truncp24q48x2_args,
1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_truncp16_args,
1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsp24q48sym_args,
2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsp24q48asym_args,
2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsp16q48sym_args,
2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsp16q48asym_args,
2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsp16sym_args,
2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsp16asym_args,
2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_zeroq56_args,
1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_movq56_args,
1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movtq56_args,
1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_movfq56_args,
1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_cvtq48a32s_args,
1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_cvtq48p24s_l_args,
1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_cvtq48p24s_h_args,
1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_satq48s_args,
2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_truncq32_args,
1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsq32sym_args,
2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_roundsq32asym_args,
2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_trunca32q48_args,
1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_movap24s_l_args,
1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_movap24s_h_args,
1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_trunca16p24s_l_args,
1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_trunca16p24s_h_args,
1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_addp24_args,
1, Iclass_ae_iclass_addp24_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_subp24_args,
1, Iclass_ae_iclass_subp24_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_negp24_args,
1, Iclass_ae_iclass_negp24_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_absp24_args,
1, Iclass_ae_iclass_absp24_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_maxp24s_args,
1, Iclass_ae_iclass_maxp24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_minp24s_args,
1, Iclass_ae_iclass_minp24s_stateArgs, 0, 0 },
{ 4, Iclass_ae_iclass_maxbp24s_args,
1, Iclass_ae_iclass_maxbp24s_stateArgs, 0, 0 },
{ 4, Iclass_ae_iclass_minbp24s_args,
1, Iclass_ae_iclass_minbp24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_addsp24s_args,
2, Iclass_ae_iclass_addsp24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_subsp24s_args,
2, Iclass_ae_iclass_subsp24s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_negsp24s_args,
2, Iclass_ae_iclass_negsp24s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_abssp24s_args,
2, Iclass_ae_iclass_abssp24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_andp48_args,
1, Iclass_ae_iclass_andp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_nandp48_args,
1, Iclass_ae_iclass_nandp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_orp48_args,
1, Iclass_ae_iclass_orp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_xorp48_args,
1, Iclass_ae_iclass_xorp48_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_ltp24s_args,
1, Iclass_ae_iclass_ltp24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lep24s_args,
1, Iclass_ae_iclass_lep24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_eqp24_args,
1, Iclass_ae_iclass_eqp24_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_addq56_args,
1, Iclass_ae_iclass_addq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_subq56_args,
1, Iclass_ae_iclass_subq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_negq56_args,
1, Iclass_ae_iclass_negq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_absq56_args,
1, Iclass_ae_iclass_absq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_maxq56s_args,
1, Iclass_ae_iclass_maxq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_minq56s_args,
1, Iclass_ae_iclass_minq56s_stateArgs, 0, 0 },
{ 4, Iclass_ae_iclass_maxbq56s_args,
1, Iclass_ae_iclass_maxbq56s_stateArgs, 0, 0 },
{ 4, Iclass_ae_iclass_minbq56s_args,
1, Iclass_ae_iclass_minbq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_addsq56s_args,
2, Iclass_ae_iclass_addsq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_subsq56s_args,
2, Iclass_ae_iclass_subsq56s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_negsq56s_args,
2, Iclass_ae_iclass_negsq56s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_abssq56s_args,
2, Iclass_ae_iclass_abssq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_andq56_args,
1, Iclass_ae_iclass_andq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_nandq56_args,
1, Iclass_ae_iclass_nandq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_orq56_args,
1, Iclass_ae_iclass_orq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_xorq56_args,
1, Iclass_ae_iclass_xorq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sllip24_args,
1, Iclass_ae_iclass_sllip24_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_srlip24_args,
1, Iclass_ae_iclass_srlip24_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sraip24_args,
1, Iclass_ae_iclass_sraip24_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_sllsp24_args,
2, Iclass_ae_iclass_sllsp24_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_srlsp24_args,
2, Iclass_ae_iclass_srlsp24_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_srasp24_args,
2, Iclass_ae_iclass_srasp24_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sllisp24s_args,
2, Iclass_ae_iclass_sllisp24s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_sllssp24s_args,
3, Iclass_ae_iclass_sllssp24s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_slliq56_args,
1, Iclass_ae_iclass_slliq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_srliq56_args,
1, Iclass_ae_iclass_srliq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sraiq56_args,
1, Iclass_ae_iclass_sraiq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_sllsq56_args,
2, Iclass_ae_iclass_sllsq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_srlsq56_args,
2, Iclass_ae_iclass_srlsq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_srasq56_args,
2, Iclass_ae_iclass_srasq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sllaq56_args,
1, Iclass_ae_iclass_sllaq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_srlaq56_args,
1, Iclass_ae_iclass_srlaq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sraaq56_args,
1, Iclass_ae_iclass_sraaq56_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sllisq56s_args,
2, Iclass_ae_iclass_sllisq56s_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_sllssq56s_args,
3, Iclass_ae_iclass_sllssq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sllasq56s_args,
2, Iclass_ae_iclass_sllasq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_ltq56s_args,
1, Iclass_ae_iclass_ltq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_leq56s_args,
1, Iclass_ae_iclass_leq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_eqq56_args,
1, Iclass_ae_iclass_eqq56_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_nsaq56s_args,
1, Iclass_ae_iclass_nsaq56s_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfs32p16s_ll_args,
2, Iclass_ae_iclass_mulfs32p16s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfp24s_ll_args,
1, Iclass_ae_iclass_mulfp24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulp24s_ll_args,
1, Iclass_ae_iclass_mulp24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfs32p16s_lh_args,
2, Iclass_ae_iclass_mulfs32p16s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfp24s_lh_args,
1, Iclass_ae_iclass_mulfp24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulp24s_lh_args,
1, Iclass_ae_iclass_mulp24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfs32p16s_hl_args,
2, Iclass_ae_iclass_mulfs32p16s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfp24s_hl_args,
1, Iclass_ae_iclass_mulfp24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulp24s_hl_args,
1, Iclass_ae_iclass_mulp24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfs32p16s_hh_args,
2, Iclass_ae_iclass_mulfs32p16s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfp24s_hh_args,
1, Iclass_ae_iclass_mulfp24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulp24s_hh_args,
1, Iclass_ae_iclass_mulp24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs32p16s_ll_args,
2, Iclass_ae_iclass_mulafs32p16s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafp24s_ll_args,
1, Iclass_ae_iclass_mulafp24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulap24s_ll_args,
1, Iclass_ae_iclass_mulap24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs32p16s_lh_args,
2, Iclass_ae_iclass_mulafs32p16s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafp24s_lh_args,
1, Iclass_ae_iclass_mulafp24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulap24s_lh_args,
1, Iclass_ae_iclass_mulap24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs32p16s_hl_args,
2, Iclass_ae_iclass_mulafs32p16s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafp24s_hl_args,
1, Iclass_ae_iclass_mulafp24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulap24s_hl_args,
1, Iclass_ae_iclass_mulap24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs32p16s_hh_args,
2, Iclass_ae_iclass_mulafs32p16s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafp24s_hh_args,
1, Iclass_ae_iclass_mulafp24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulap24s_hh_args,
1, Iclass_ae_iclass_mulap24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs32p16s_ll_args,
2, Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfp24s_ll_args,
1, Iclass_ae_iclass_mulsfp24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsp24s_ll_args,
1, Iclass_ae_iclass_mulsp24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs32p16s_lh_args,
2, Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfp24s_lh_args,
1, Iclass_ae_iclass_mulsfp24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsp24s_lh_args,
1, Iclass_ae_iclass_mulsp24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs32p16s_hl_args,
2, Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfp24s_hl_args,
1, Iclass_ae_iclass_mulsfp24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsp24s_hl_args,
1, Iclass_ae_iclass_mulsp24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs32p16s_hh_args,
2, Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfp24s_hh_args,
1, Iclass_ae_iclass_mulsfp24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsp24s_hh_args,
1, Iclass_ae_iclass_mulsp24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs56p24s_ll_args,
2, Iclass_ae_iclass_mulafs56p24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulas56p24s_ll_args,
2, Iclass_ae_iclass_mulas56p24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs56p24s_lh_args,
2, Iclass_ae_iclass_mulafs56p24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulas56p24s_lh_args,
2, Iclass_ae_iclass_mulas56p24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs56p24s_hl_args,
2, Iclass_ae_iclass_mulafs56p24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulas56p24s_hl_args,
2, Iclass_ae_iclass_mulas56p24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafs56p24s_hh_args,
2, Iclass_ae_iclass_mulafs56p24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulas56p24s_hh_args,
2, Iclass_ae_iclass_mulas56p24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs56p24s_ll_args,
2, Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulss56p24s_ll_args,
2, Iclass_ae_iclass_mulss56p24s_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs56p24s_lh_args,
2, Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulss56p24s_lh_args,
2, Iclass_ae_iclass_mulss56p24s_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs56p24s_hl_args,
2, Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulss56p24s_hl_args,
2, Iclass_ae_iclass_mulss56p24s_hl_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfs56p24s_hh_args,
2, Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulss56p24s_hh_args,
2, Iclass_ae_iclass_mulss56p24s_hh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfq32sp16s_l_args,
1, Iclass_ae_iclass_mulfq32sp16s_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfq32sp16s_h_args,
1, Iclass_ae_iclass_mulfq32sp16s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfq32sp16u_l_args,
1, Iclass_ae_iclass_mulfq32sp16u_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulfq32sp16u_h_args,
1, Iclass_ae_iclass_mulfq32sp16u_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulq32sp16s_l_args,
1, Iclass_ae_iclass_mulq32sp16s_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulq32sp16s_h_args,
1, Iclass_ae_iclass_mulq32sp16s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulq32sp16u_l_args,
1, Iclass_ae_iclass_mulq32sp16u_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulq32sp16u_h_args,
1, Iclass_ae_iclass_mulq32sp16u_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafq32sp16s_l_args,
1, Iclass_ae_iclass_mulafq32sp16s_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafq32sp16s_h_args,
1, Iclass_ae_iclass_mulafq32sp16s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafq32sp16u_l_args,
1, Iclass_ae_iclass_mulafq32sp16u_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulafq32sp16u_h_args,
1, Iclass_ae_iclass_mulafq32sp16u_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaq32sp16s_l_args,
1, Iclass_ae_iclass_mulaq32sp16s_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaq32sp16s_h_args,
1, Iclass_ae_iclass_mulaq32sp16s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaq32sp16u_l_args,
1, Iclass_ae_iclass_mulaq32sp16u_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaq32sp16u_h_args,
1, Iclass_ae_iclass_mulaq32sp16u_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfq32sp16s_l_args,
1, Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfq32sp16s_h_args,
1, Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfq32sp16u_l_args,
1, Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsfq32sp16u_h_args,
1, Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsq32sp16s_l_args,
1, Iclass_ae_iclass_mulsq32sp16s_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsq32sp16s_h_args,
1, Iclass_ae_iclass_mulsq32sp16s_h_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsq32sp16u_l_args,
1, Iclass_ae_iclass_mulsq32sp16u_l_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsq32sp16u_h_args,
1, Iclass_ae_iclass_mulsq32sp16u_h_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaaq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaafq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaaq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaafq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaaq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaafq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaaq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaafq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaaq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaafq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaaq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args,
1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args,
1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args,
1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args,
1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args,
1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 },
{ 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args,
1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args,
1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_sha32_args,
0, 0, 0, 0 },
{ 3, Iclass_ae_iclass_vldl32t_args,
5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_vldl16t_args,
5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_vldl16c_args,
8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_vldsht_args,
6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_lb_args,
3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_lbi_args,
3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lbk_args,
3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_lbki_args,
3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_db_args,
3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_dbi_args,
3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_vlel32t_args,
3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_vlel16t_args,
3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
{ 2, Iclass_ae_iclass_sb_args,
4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
{ 3, Iclass_ae_iclass_sbi_args,
3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_vles16c_args,
5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
{ 1, Iclass_ae_iclass_sbf_args,
3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }
};
enum xtensa_iclass_id {
ICLASS_xt_iclass_excw,
ICLASS_xt_iclass_rfe,
ICLASS_xt_iclass_rfde,
ICLASS_xt_iclass_syscall,
ICLASS_xt_iclass_simcall,
ICLASS_xt_iclass_call12,
ICLASS_xt_iclass_call8,
ICLASS_xt_iclass_call4,
ICLASS_xt_iclass_callx12,
ICLASS_xt_iclass_callx8,
ICLASS_xt_iclass_callx4,
ICLASS_xt_iclass_entry,
ICLASS_xt_iclass_movsp,
ICLASS_xt_iclass_rotw,
ICLASS_xt_iclass_retw,
ICLASS_xt_iclass_rfwou,
ICLASS_xt_iclass_l32e,
ICLASS_xt_iclass_s32e,
ICLASS_xt_iclass_rsr_windowbase,
ICLASS_xt_iclass_wsr_windowbase,
ICLASS_xt_iclass_xsr_windowbase,
ICLASS_xt_iclass_rsr_windowstart,
ICLASS_xt_iclass_wsr_windowstart,
ICLASS_xt_iclass_xsr_windowstart,
ICLASS_xt_iclass_add_n,
ICLASS_xt_iclass_addi_n,
ICLASS_xt_iclass_bz6,
ICLASS_xt_iclass_ill_n,
ICLASS_xt_iclass_loadi4,
ICLASS_xt_iclass_mov_n,
ICLASS_xt_iclass_movi_n,
ICLASS_xt_iclass_nopn,
ICLASS_xt_iclass_retn,
ICLASS_xt_iclass_storei4,
ICLASS_rur_threadptr,
ICLASS_wur_threadptr,
ICLASS_xt_iclass_addi,
ICLASS_xt_iclass_addmi,
ICLASS_xt_iclass_addsub,
ICLASS_xt_iclass_bit,
ICLASS_xt_iclass_bsi8,
ICLASS_xt_iclass_bsi8b,
ICLASS_xt_iclass_bsi8u,
ICLASS_xt_iclass_bst8,
ICLASS_xt_iclass_bsz12,
ICLASS_xt_iclass_call0,
ICLASS_xt_iclass_callx0,
ICLASS_xt_iclass_exti,
ICLASS_xt_iclass_ill,
ICLASS_xt_iclass_jump,
ICLASS_xt_iclass_jumpx,
ICLASS_xt_iclass_l16ui,
ICLASS_xt_iclass_l16si,
ICLASS_xt_iclass_l32i,
ICLASS_xt_iclass_l32r,
ICLASS_xt_iclass_l8i,
ICLASS_xt_iclass_loop,
ICLASS_xt_iclass_loopz,
ICLASS_xt_iclass_movi,
ICLASS_xt_iclass_movz,
ICLASS_xt_iclass_neg,
ICLASS_xt_iclass_nop,
ICLASS_xt_iclass_return,
ICLASS_xt_iclass_s16i,
ICLASS_xt_iclass_s32i,
ICLASS_xt_iclass_s8i,
ICLASS_xt_iclass_sar,
ICLASS_xt_iclass_sari,
ICLASS_xt_iclass_shifts,
ICLASS_xt_iclass_shiftst,
ICLASS_xt_iclass_shiftt,
ICLASS_xt_iclass_slli,
ICLASS_xt_iclass_srai,
ICLASS_xt_iclass_srli,
ICLASS_xt_iclass_memw,
ICLASS_xt_iclass_extw,
ICLASS_xt_iclass_isync,
ICLASS_xt_iclass_sync,
ICLASS_xt_iclass_rsil,
ICLASS_xt_iclass_rsr_lend,
ICLASS_xt_iclass_wsr_lend,
ICLASS_xt_iclass_xsr_lend,
ICLASS_xt_iclass_rsr_lcount,
ICLASS_xt_iclass_wsr_lcount,
ICLASS_xt_iclass_xsr_lcount,
ICLASS_xt_iclass_rsr_lbeg,
ICLASS_xt_iclass_wsr_lbeg,
ICLASS_xt_iclass_xsr_lbeg,
ICLASS_xt_iclass_rsr_sar,
ICLASS_xt_iclass_wsr_sar,
ICLASS_xt_iclass_xsr_sar,
ICLASS_xt_iclass_rsr_litbase,
ICLASS_xt_iclass_wsr_litbase,
ICLASS_xt_iclass_xsr_litbase,
ICLASS_xt_iclass_rsr_176,
ICLASS_xt_iclass_wsr_176,
ICLASS_xt_iclass_rsr_208,
ICLASS_xt_iclass_rsr_ps,
ICLASS_xt_iclass_wsr_ps,
ICLASS_xt_iclass_xsr_ps,
ICLASS_xt_iclass_rsr_epc1,
ICLASS_xt_iclass_wsr_epc1,
ICLASS_xt_iclass_xsr_epc1,
ICLASS_xt_iclass_rsr_excsave1,
ICLASS_xt_iclass_wsr_excsave1,
ICLASS_xt_iclass_xsr_excsave1,
ICLASS_xt_iclass_rsr_epc2,
ICLASS_xt_iclass_wsr_epc2,
ICLASS_xt_iclass_xsr_epc2,
ICLASS_xt_iclass_rsr_excsave2,
ICLASS_xt_iclass_wsr_excsave2,
ICLASS_xt_iclass_xsr_excsave2,
ICLASS_xt_iclass_rsr_eps2,
ICLASS_xt_iclass_wsr_eps2,
ICLASS_xt_iclass_xsr_eps2,
ICLASS_xt_iclass_rsr_excvaddr,
ICLASS_xt_iclass_wsr_excvaddr,
ICLASS_xt_iclass_xsr_excvaddr,
ICLASS_xt_iclass_rsr_depc,
ICLASS_xt_iclass_wsr_depc,
ICLASS_xt_iclass_xsr_depc,
ICLASS_xt_iclass_rsr_exccause,
ICLASS_xt_iclass_wsr_exccause,
ICLASS_xt_iclass_xsr_exccause,
ICLASS_xt_iclass_rsr_misc0,
ICLASS_xt_iclass_wsr_misc0,
ICLASS_xt_iclass_xsr_misc0,
ICLASS_xt_iclass_rsr_misc1,
ICLASS_xt_iclass_wsr_misc1,
ICLASS_xt_iclass_xsr_misc1,
ICLASS_xt_iclass_rsr_prid,
ICLASS_xt_iclass_rsr_vecbase,
ICLASS_xt_iclass_wsr_vecbase,
ICLASS_xt_iclass_xsr_vecbase,
ICLASS_xt_mul16,
ICLASS_xt_mul32,
ICLASS_xt_iclass_rfi,
ICLASS_xt_iclass_wait,
ICLASS_xt_iclass_rsr_interrupt,
ICLASS_xt_iclass_wsr_intset,
ICLASS_xt_iclass_wsr_intclear,
ICLASS_xt_iclass_rsr_intenable,
ICLASS_xt_iclass_wsr_intenable,
ICLASS_xt_iclass_xsr_intenable,
ICLASS_xt_iclass_break,
ICLASS_xt_iclass_break_n,
ICLASS_xt_iclass_rsr_debugcause,
ICLASS_xt_iclass_wsr_debugcause,
ICLASS_xt_iclass_xsr_debugcause,
ICLASS_xt_iclass_rsr_icount,
ICLASS_xt_iclass_wsr_icount,
ICLASS_xt_iclass_xsr_icount,
ICLASS_xt_iclass_rsr_icountlevel,
ICLASS_xt_iclass_wsr_icountlevel,
ICLASS_xt_iclass_xsr_icountlevel,
ICLASS_xt_iclass_rsr_ddr,
ICLASS_xt_iclass_wsr_ddr,
ICLASS_xt_iclass_xsr_ddr,
ICLASS_xt_iclass_rfdo,
ICLASS_xt_iclass_rfdd,
ICLASS_xt_iclass_bbool1,
ICLASS_xt_iclass_bbool4,
ICLASS_xt_iclass_bbool8,
ICLASS_xt_iclass_bbranch,
ICLASS_xt_iclass_bmove,
ICLASS_xt_iclass_RSR_BR,
ICLASS_xt_iclass_WSR_BR,
ICLASS_xt_iclass_XSR_BR,
ICLASS_xt_iclass_rsr_ccount,
ICLASS_xt_iclass_wsr_ccount,
ICLASS_xt_iclass_xsr_ccount,
ICLASS_xt_iclass_rsr_ccompare0,
ICLASS_xt_iclass_wsr_ccompare0,
ICLASS_xt_iclass_xsr_ccompare0,
ICLASS_xt_iclass_rsr_ccompare1,
ICLASS_xt_iclass_wsr_ccompare1,
ICLASS_xt_iclass_xsr_ccompare1,
ICLASS_xt_iclass_icache,
ICLASS_xt_iclass_icache_inv,
ICLASS_xt_iclass_licx,
ICLASS_xt_iclass_sicx,
ICLASS_xt_iclass_dcache,
ICLASS_xt_iclass_dcache_ind,
ICLASS_xt_iclass_dcache_inv,
ICLASS_xt_iclass_dpf,
ICLASS_xt_iclass_sdct,
ICLASS_xt_iclass_ldct,
ICLASS_xt_iclass_wsr_ptevaddr,
ICLASS_xt_iclass_rsr_ptevaddr,
ICLASS_xt_iclass_xsr_ptevaddr,
ICLASS_xt_iclass_rsr_rasid,
ICLASS_xt_iclass_wsr_rasid,
ICLASS_xt_iclass_xsr_rasid,
ICLASS_xt_iclass_rsr_itlbcfg,
ICLASS_xt_iclass_wsr_itlbcfg,
ICLASS_xt_iclass_xsr_itlbcfg,
ICLASS_xt_iclass_rsr_dtlbcfg,
ICLASS_xt_iclass_wsr_dtlbcfg,
ICLASS_xt_iclass_xsr_dtlbcfg,
ICLASS_xt_iclass_idtlb,
ICLASS_xt_iclass_rdtlb,
ICLASS_xt_iclass_wdtlb,
ICLASS_xt_iclass_iitlb,
ICLASS_xt_iclass_ritlb,
ICLASS_xt_iclass_witlb,
ICLASS_xt_iclass_ldpte,
ICLASS_xt_iclass_hwwitlba,
ICLASS_xt_iclass_hwwdtlba,
ICLASS_xt_iclass_rsr_cpenable,
ICLASS_xt_iclass_wsr_cpenable,
ICLASS_xt_iclass_xsr_cpenable,
ICLASS_xt_iclass_clamp,
ICLASS_xt_iclass_minmax,
ICLASS_xt_iclass_nsa,
ICLASS_xt_iclass_sx,
ICLASS_xt_iclass_l32ai,
ICLASS_xt_iclass_s32ri,
ICLASS_xt_iclass_s32c1i,
ICLASS_xt_iclass_rsr_scompare1,
ICLASS_xt_iclass_wsr_scompare1,
ICLASS_xt_iclass_xsr_scompare1,
ICLASS_xt_iclass_rsr_atomctl,
ICLASS_xt_iclass_wsr_atomctl,
ICLASS_xt_iclass_xsr_atomctl,
ICLASS_xt_iclass_rer,
ICLASS_xt_iclass_wer,
ICLASS_rur_ae_ovf_sar,
ICLASS_wur_ae_ovf_sar,
ICLASS_rur_ae_bithead,
ICLASS_wur_ae_bithead,
ICLASS_rur_ae_ts_fts_bu_bp,
ICLASS_wur_ae_ts_fts_bu_bp,
ICLASS_rur_ae_sd_no,
ICLASS_wur_ae_sd_no,
ICLASS_ae_iclass_rur_ae_overflow,
ICLASS_ae_iclass_wur_ae_overflow,
ICLASS_ae_iclass_rur_ae_sar,
ICLASS_ae_iclass_wur_ae_sar,
ICLASS_ae_iclass_rur_ae_bitptr,
ICLASS_ae_iclass_wur_ae_bitptr,
ICLASS_ae_iclass_rur_ae_bitsused,
ICLASS_ae_iclass_wur_ae_bitsused,
ICLASS_ae_iclass_rur_ae_tablesize,
ICLASS_ae_iclass_wur_ae_tablesize,
ICLASS_ae_iclass_rur_ae_first_ts,
ICLASS_ae_iclass_wur_ae_first_ts,
ICLASS_ae_iclass_rur_ae_nextoffset,
ICLASS_ae_iclass_wur_ae_nextoffset,
ICLASS_ae_iclass_rur_ae_searchdone,
ICLASS_ae_iclass_wur_ae_searchdone,
ICLASS_ae_iclass_lp16f_i,
ICLASS_ae_iclass_lp16f_iu,
ICLASS_ae_iclass_lp16f_x,
ICLASS_ae_iclass_lp16f_xu,
ICLASS_ae_iclass_lp24_i,
ICLASS_ae_iclass_lp24_iu,
ICLASS_ae_iclass_lp24_x,
ICLASS_ae_iclass_lp24_xu,
ICLASS_ae_iclass_lp24f_i,
ICLASS_ae_iclass_lp24f_iu,
ICLASS_ae_iclass_lp24f_x,
ICLASS_ae_iclass_lp24f_xu,
ICLASS_ae_iclass_lp16x2f_i,
ICLASS_ae_iclass_lp16x2f_iu,
ICLASS_ae_iclass_lp16x2f_x,
ICLASS_ae_iclass_lp16x2f_xu,
ICLASS_ae_iclass_lp24x2f_i,
ICLASS_ae_iclass_lp24x2f_iu,
ICLASS_ae_iclass_lp24x2f_x,
ICLASS_ae_iclass_lp24x2f_xu,
ICLASS_ae_iclass_lp24x2_i,
ICLASS_ae_iclass_lp24x2_iu,
ICLASS_ae_iclass_lp24x2_x,
ICLASS_ae_iclass_lp24x2_xu,
ICLASS_ae_iclass_sp16x2f_i,
ICLASS_ae_iclass_sp16x2f_iu,
ICLASS_ae_iclass_sp16x2f_x,
ICLASS_ae_iclass_sp16x2f_xu,
ICLASS_ae_iclass_sp24x2s_i,
ICLASS_ae_iclass_sp24x2s_iu,
ICLASS_ae_iclass_sp24x2s_x,
ICLASS_ae_iclass_sp24x2s_xu,
ICLASS_ae_iclass_sp24x2f_i,
ICLASS_ae_iclass_sp24x2f_iu,
ICLASS_ae_iclass_sp24x2f_x,
ICLASS_ae_iclass_sp24x2f_xu,
ICLASS_ae_iclass_sp16f_l_i,
ICLASS_ae_iclass_sp16f_l_iu,
ICLASS_ae_iclass_sp16f_l_x,
ICLASS_ae_iclass_sp16f_l_xu,
ICLASS_ae_iclass_sp24s_l_i,
ICLASS_ae_iclass_sp24s_l_iu,
ICLASS_ae_iclass_sp24s_l_x,
ICLASS_ae_iclass_sp24s_l_xu,
ICLASS_ae_iclass_sp24f_l_i,
ICLASS_ae_iclass_sp24f_l_iu,
ICLASS_ae_iclass_sp24f_l_x,
ICLASS_ae_iclass_sp24f_l_xu,
ICLASS_ae_iclass_lq56_i,
ICLASS_ae_iclass_lq56_iu,
ICLASS_ae_iclass_lq56_x,
ICLASS_ae_iclass_lq56_xu,
ICLASS_ae_iclass_lq32f_i,
ICLASS_ae_iclass_lq32f_iu,
ICLASS_ae_iclass_lq32f_x,
ICLASS_ae_iclass_lq32f_xu,
ICLASS_ae_iclass_sq56s_i,
ICLASS_ae_iclass_sq56s_iu,
ICLASS_ae_iclass_sq56s_x,
ICLASS_ae_iclass_sq56s_xu,
ICLASS_ae_iclass_sq32f_i,
ICLASS_ae_iclass_sq32f_iu,
ICLASS_ae_iclass_sq32f_x,
ICLASS_ae_iclass_sq32f_xu,
ICLASS_ae_iclass_zerop48,
ICLASS_ae_iclass_movp48,
ICLASS_ae_iclass_selp24_ll,
ICLASS_ae_iclass_selp24_lh,
ICLASS_ae_iclass_selp24_hl,
ICLASS_ae_iclass_selp24_hh,
ICLASS_ae_iclass_movtp24x2,
ICLASS_ae_iclass_movfp24x2,
ICLASS_ae_iclass_movtp48,
ICLASS_ae_iclass_movfp48,
ICLASS_ae_iclass_movpa24x2,
ICLASS_ae_iclass_truncp24a32x2,
ICLASS_ae_iclass_cvta32p24_l,
ICLASS_ae_iclass_cvta32p24_h,
ICLASS_ae_iclass_cvtp24a16x2_ll,
ICLASS_ae_iclass_cvtp24a16x2_lh,
ICLASS_ae_iclass_cvtp24a16x2_hl,
ICLASS_ae_iclass_cvtp24a16x2_hh,
ICLASS_ae_iclass_truncp24q48x2,
ICLASS_ae_iclass_truncp16,
ICLASS_ae_iclass_roundsp24q48sym,
ICLASS_ae_iclass_roundsp24q48asym,
ICLASS_ae_iclass_roundsp16q48sym,
ICLASS_ae_iclass_roundsp16q48asym,
ICLASS_ae_iclass_roundsp16sym,
ICLASS_ae_iclass_roundsp16asym,
ICLASS_ae_iclass_zeroq56,
ICLASS_ae_iclass_movq56,
ICLASS_ae_iclass_movtq56,
ICLASS_ae_iclass_movfq56,
ICLASS_ae_iclass_cvtq48a32s,
ICLASS_ae_iclass_cvtq48p24s_l,
ICLASS_ae_iclass_cvtq48p24s_h,
ICLASS_ae_iclass_satq48s,
ICLASS_ae_iclass_truncq32,
ICLASS_ae_iclass_roundsq32sym,
ICLASS_ae_iclass_roundsq32asym,
ICLASS_ae_iclass_trunca32q48,
ICLASS_ae_iclass_movap24s_l,
ICLASS_ae_iclass_movap24s_h,
ICLASS_ae_iclass_trunca16p24s_l,
ICLASS_ae_iclass_trunca16p24s_h,
ICLASS_ae_iclass_addp24,
ICLASS_ae_iclass_subp24,
ICLASS_ae_iclass_negp24,
ICLASS_ae_iclass_absp24,
ICLASS_ae_iclass_maxp24s,
ICLASS_ae_iclass_minp24s,
ICLASS_ae_iclass_maxbp24s,
ICLASS_ae_iclass_minbp24s,
ICLASS_ae_iclass_addsp24s,
ICLASS_ae_iclass_subsp24s,
ICLASS_ae_iclass_negsp24s,
ICLASS_ae_iclass_abssp24s,
ICLASS_ae_iclass_andp48,
ICLASS_ae_iclass_nandp48,
ICLASS_ae_iclass_orp48,
ICLASS_ae_iclass_xorp48,
ICLASS_ae_iclass_ltp24s,
ICLASS_ae_iclass_lep24s,
ICLASS_ae_iclass_eqp24,
ICLASS_ae_iclass_addq56,
ICLASS_ae_iclass_subq56,
ICLASS_ae_iclass_negq56,
ICLASS_ae_iclass_absq56,
ICLASS_ae_iclass_maxq56s,
ICLASS_ae_iclass_minq56s,
ICLASS_ae_iclass_maxbq56s,
ICLASS_ae_iclass_minbq56s,
ICLASS_ae_iclass_addsq56s,
ICLASS_ae_iclass_subsq56s,
ICLASS_ae_iclass_negsq56s,
ICLASS_ae_iclass_abssq56s,
ICLASS_ae_iclass_andq56,
ICLASS_ae_iclass_nandq56,
ICLASS_ae_iclass_orq56,
ICLASS_ae_iclass_xorq56,
ICLASS_ae_iclass_sllip24,
ICLASS_ae_iclass_srlip24,
ICLASS_ae_iclass_sraip24,
ICLASS_ae_iclass_sllsp24,
ICLASS_ae_iclass_srlsp24,
ICLASS_ae_iclass_srasp24,
ICLASS_ae_iclass_sllisp24s,
ICLASS_ae_iclass_sllssp24s,
ICLASS_ae_iclass_slliq56,
ICLASS_ae_iclass_srliq56,
ICLASS_ae_iclass_sraiq56,
ICLASS_ae_iclass_sllsq56,
ICLASS_ae_iclass_srlsq56,
ICLASS_ae_iclass_srasq56,
ICLASS_ae_iclass_sllaq56,
ICLASS_ae_iclass_srlaq56,
ICLASS_ae_iclass_sraaq56,
ICLASS_ae_iclass_sllisq56s,
ICLASS_ae_iclass_sllssq56s,
ICLASS_ae_iclass_sllasq56s,
ICLASS_ae_iclass_ltq56s,
ICLASS_ae_iclass_leq56s,
ICLASS_ae_iclass_eqq56,
ICLASS_ae_iclass_nsaq56s,
ICLASS_ae_iclass_mulfs32p16s_ll,
ICLASS_ae_iclass_mulfp24s_ll,
ICLASS_ae_iclass_mulp24s_ll,
ICLASS_ae_iclass_mulfs32p16s_lh,
ICLASS_ae_iclass_mulfp24s_lh,
ICLASS_ae_iclass_mulp24s_lh,
ICLASS_ae_iclass_mulfs32p16s_hl,
ICLASS_ae_iclass_mulfp24s_hl,
ICLASS_ae_iclass_mulp24s_hl,
ICLASS_ae_iclass_mulfs32p16s_hh,
ICLASS_ae_iclass_mulfp24s_hh,
ICLASS_ae_iclass_mulp24s_hh,
ICLASS_ae_iclass_mulafs32p16s_ll,
ICLASS_ae_iclass_mulafp24s_ll,
ICLASS_ae_iclass_mulap24s_ll,
ICLASS_ae_iclass_mulafs32p16s_lh,
ICLASS_ae_iclass_mulafp24s_lh,
ICLASS_ae_iclass_mulap24s_lh,
ICLASS_ae_iclass_mulafs32p16s_hl,
ICLASS_ae_iclass_mulafp24s_hl,
ICLASS_ae_iclass_mulap24s_hl,
ICLASS_ae_iclass_mulafs32p16s_hh,
ICLASS_ae_iclass_mulafp24s_hh,
ICLASS_ae_iclass_mulap24s_hh,
ICLASS_ae_iclass_mulsfs32p16s_ll,
ICLASS_ae_iclass_mulsfp24s_ll,
ICLASS_ae_iclass_mulsp24s_ll,
ICLASS_ae_iclass_mulsfs32p16s_lh,
ICLASS_ae_iclass_mulsfp24s_lh,
ICLASS_ae_iclass_mulsp24s_lh,
ICLASS_ae_iclass_mulsfs32p16s_hl,
ICLASS_ae_iclass_mulsfp24s_hl,
ICLASS_ae_iclass_mulsp24s_hl,
ICLASS_ae_iclass_mulsfs32p16s_hh,
ICLASS_ae_iclass_mulsfp24s_hh,
ICLASS_ae_iclass_mulsp24s_hh,
ICLASS_ae_iclass_mulafs56p24s_ll,
ICLASS_ae_iclass_mulas56p24s_ll,
ICLASS_ae_iclass_mulafs56p24s_lh,
ICLASS_ae_iclass_mulas56p24s_lh,
ICLASS_ae_iclass_mulafs56p24s_hl,
ICLASS_ae_iclass_mulas56p24s_hl,
ICLASS_ae_iclass_mulafs56p24s_hh,
ICLASS_ae_iclass_mulas56p24s_hh,
ICLASS_ae_iclass_mulsfs56p24s_ll,
ICLASS_ae_iclass_mulss56p24s_ll,
ICLASS_ae_iclass_mulsfs56p24s_lh,
ICLASS_ae_iclass_mulss56p24s_lh,
ICLASS_ae_iclass_mulsfs56p24s_hl,
ICLASS_ae_iclass_mulss56p24s_hl,
ICLASS_ae_iclass_mulsfs56p24s_hh,
ICLASS_ae_iclass_mulss56p24s_hh,
ICLASS_ae_iclass_mulfq32sp16s_l,
ICLASS_ae_iclass_mulfq32sp16s_h,
ICLASS_ae_iclass_mulfq32sp16u_l,
ICLASS_ae_iclass_mulfq32sp16u_h,
ICLASS_ae_iclass_mulq32sp16s_l,
ICLASS_ae_iclass_mulq32sp16s_h,
ICLASS_ae_iclass_mulq32sp16u_l,
ICLASS_ae_iclass_mulq32sp16u_h,
ICLASS_ae_iclass_mulafq32sp16s_l,
ICLASS_ae_iclass_mulafq32sp16s_h,
ICLASS_ae_iclass_mulafq32sp16u_l,
ICLASS_ae_iclass_mulafq32sp16u_h,
ICLASS_ae_iclass_mulaq32sp16s_l,
ICLASS_ae_iclass_mulaq32sp16s_h,
ICLASS_ae_iclass_mulaq32sp16u_l,
ICLASS_ae_iclass_mulaq32sp16u_h,
ICLASS_ae_iclass_mulsfq32sp16s_l,
ICLASS_ae_iclass_mulsfq32sp16s_h,
ICLASS_ae_iclass_mulsfq32sp16u_l,
ICLASS_ae_iclass_mulsfq32sp16u_h,
ICLASS_ae_iclass_mulsq32sp16s_l,
ICLASS_ae_iclass_mulsq32sp16s_h,
ICLASS_ae_iclass_mulsq32sp16u_l,
ICLASS_ae_iclass_mulsq32sp16u_h,
ICLASS_ae_iclass_mulzaaq32sp16s_ll,
ICLASS_ae_iclass_mulzaafq32sp16s_ll,
ICLASS_ae_iclass_mulzaaq32sp16u_ll,
ICLASS_ae_iclass_mulzaafq32sp16u_ll,
ICLASS_ae_iclass_mulzaaq32sp16s_hh,
ICLASS_ae_iclass_mulzaafq32sp16s_hh,
ICLASS_ae_iclass_mulzaaq32sp16u_hh,
ICLASS_ae_iclass_mulzaafq32sp16u_hh,
ICLASS_ae_iclass_mulzaaq32sp16s_lh,
ICLASS_ae_iclass_mulzaafq32sp16s_lh,
ICLASS_ae_iclass_mulzaaq32sp16u_lh,
ICLASS_ae_iclass_mulzaafq32sp16u_lh,
ICLASS_ae_iclass_mulzasq32sp16s_ll,
ICLASS_ae_iclass_mulzasfq32sp16s_ll,
ICLASS_ae_iclass_mulzasq32sp16u_ll,
ICLASS_ae_iclass_mulzasfq32sp16u_ll,
ICLASS_ae_iclass_mulzasq32sp16s_hh,
ICLASS_ae_iclass_mulzasfq32sp16s_hh,
ICLASS_ae_iclass_mulzasq32sp16u_hh,
ICLASS_ae_iclass_mulzasfq32sp16u_hh,
ICLASS_ae_iclass_mulzasq32sp16s_lh,
ICLASS_ae_iclass_mulzasfq32sp16s_lh,
ICLASS_ae_iclass_mulzasq32sp16u_lh,
ICLASS_ae_iclass_mulzasfq32sp16u_lh,
ICLASS_ae_iclass_mulzsaq32sp16s_ll,
ICLASS_ae_iclass_mulzsafq32sp16s_ll,
ICLASS_ae_iclass_mulzsaq32sp16u_ll,
ICLASS_ae_iclass_mulzsafq32sp16u_ll,
ICLASS_ae_iclass_mulzsaq32sp16s_hh,
ICLASS_ae_iclass_mulzsafq32sp16s_hh,
ICLASS_ae_iclass_mulzsaq32sp16u_hh,
ICLASS_ae_iclass_mulzsafq32sp16u_hh,
ICLASS_ae_iclass_mulzsaq32sp16s_lh,
ICLASS_ae_iclass_mulzsafq32sp16s_lh,
ICLASS_ae_iclass_mulzsaq32sp16u_lh,
ICLASS_ae_iclass_mulzsafq32sp16u_lh,
ICLASS_ae_iclass_mulzssq32sp16s_ll,
ICLASS_ae_iclass_mulzssfq32sp16s_ll,
ICLASS_ae_iclass_mulzssq32sp16u_ll,
ICLASS_ae_iclass_mulzssfq32sp16u_ll,
ICLASS_ae_iclass_mulzssq32sp16s_hh,
ICLASS_ae_iclass_mulzssfq32sp16s_hh,
ICLASS_ae_iclass_mulzssq32sp16u_hh,
ICLASS_ae_iclass_mulzssfq32sp16u_hh,
ICLASS_ae_iclass_mulzssq32sp16s_lh,
ICLASS_ae_iclass_mulzssfq32sp16s_lh,
ICLASS_ae_iclass_mulzssq32sp16u_lh,
ICLASS_ae_iclass_mulzssfq32sp16u_lh,
ICLASS_ae_iclass_mulzaafp24s_hh_ll,
ICLASS_ae_iclass_mulzaap24s_hh_ll,
ICLASS_ae_iclass_mulzaafp24s_hl_lh,
ICLASS_ae_iclass_mulzaap24s_hl_lh,
ICLASS_ae_iclass_mulzasfp24s_hh_ll,
ICLASS_ae_iclass_mulzasp24s_hh_ll,
ICLASS_ae_iclass_mulzasfp24s_hl_lh,
ICLASS_ae_iclass_mulzasp24s_hl_lh,
ICLASS_ae_iclass_mulzsafp24s_hh_ll,
ICLASS_ae_iclass_mulzsap24s_hh_ll,
ICLASS_ae_iclass_mulzsafp24s_hl_lh,
ICLASS_ae_iclass_mulzsap24s_hl_lh,
ICLASS_ae_iclass_mulzssfp24s_hh_ll,
ICLASS_ae_iclass_mulzssp24s_hh_ll,
ICLASS_ae_iclass_mulzssfp24s_hl_lh,
ICLASS_ae_iclass_mulzssp24s_hl_lh,
ICLASS_ae_iclass_mulaafp24s_hh_ll,
ICLASS_ae_iclass_mulaap24s_hh_ll,
ICLASS_ae_iclass_mulaafp24s_hl_lh,
ICLASS_ae_iclass_mulaap24s_hl_lh,
ICLASS_ae_iclass_mulasfp24s_hh_ll,
ICLASS_ae_iclass_mulasp24s_hh_ll,
ICLASS_ae_iclass_mulasfp24s_hl_lh,
ICLASS_ae_iclass_mulasp24s_hl_lh,
ICLASS_ae_iclass_mulsafp24s_hh_ll,
ICLASS_ae_iclass_mulsap24s_hh_ll,
ICLASS_ae_iclass_mulsafp24s_hl_lh,
ICLASS_ae_iclass_mulsap24s_hl_lh,
ICLASS_ae_iclass_mulssfp24s_hh_ll,
ICLASS_ae_iclass_mulssp24s_hh_ll,
ICLASS_ae_iclass_mulssfp24s_hl_lh,
ICLASS_ae_iclass_mulssp24s_hl_lh,
ICLASS_ae_iclass_sha32,
ICLASS_ae_iclass_vldl32t,
ICLASS_ae_iclass_vldl16t,
ICLASS_ae_iclass_vldl16c,
ICLASS_ae_iclass_vldsht,
ICLASS_ae_iclass_lb,
ICLASS_ae_iclass_lbi,
ICLASS_ae_iclass_lbk,
ICLASS_ae_iclass_lbki,
ICLASS_ae_iclass_db,
ICLASS_ae_iclass_dbi,
ICLASS_ae_iclass_vlel32t,
ICLASS_ae_iclass_vlel16t,
ICLASS_ae_iclass_sb,
ICLASS_ae_iclass_sbi,
ICLASS_ae_iclass_vles16c,
ICLASS_ae_iclass_sbf
};
/* Opcode encodings. */
static void
Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2080;
}
static void
Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000;
}
static void
Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3200;
}
static void
Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5000;
}
static void
Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5100;
}
static void
Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x35;
}
static void
Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x25;
}
static void
Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15;
}
static void
Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf0;
}
static void
Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe0;
}
static void
Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd0;
}
static void
Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x36;
}
static void
Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1000;
}
static void
Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x408000;
}
static void
Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x90;
}
static void
Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf01d;
}
static void
Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3400;
}
static void
Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3500;
}
static void
Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x90000;
}
static void
Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x490000;
}
static void
Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x34800;
}
static void
Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x134800;
}
static void
Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x614800;
}
static void
Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x34900;
}
static void
Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x134900;
}
static void
Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x614900;
}
static void
Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa;
}
static void
Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb;
}
static void
Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x8c;
}
static void
Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xcc;
}
static void
Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf06d;
}
static void
Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x8;
}
static void
Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd;
}
static void
Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc;
}
static void
Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf03d;
}
static void
Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf00d;
}
static void
Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x9;
}
static void
Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe30e70;
}
static void
Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf3e700;
}
static void
Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc002;
}
static void
Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200040;
}
static void
Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd002;
}
static void
Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200080;
}
static void
Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x800000;
}
static void
Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b2000;
}
static void
Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc00000;
}
static void
Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ca000;
}
static void
Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x900000;
}
static void
Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b4000;
}
static void
Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa00000;
}
static void
Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b8000;
}
static void
Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb00000;
}
static void
Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b3000;
}
static void
Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd00000;
}
static void
Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1cc000;
}
static void
Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe00000;
}
static void
Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1cb000;
}
static void
Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf00000;
}
static void
Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1cd000;
}
static void
Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x100000;
}
static void
Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b5000;
}
static void
Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200000;
}
static void
Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e0000;
}
static void
Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300000;
}
static void
Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ce000;
}
static void
Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x26;
}
static void
Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300000;
}
static void
Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x66;
}
static void
Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300003;
}
static void
Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe6;
}
static void
Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300001;
}
static void
Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa6;
}
static void
Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300004;
}
static void
Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6007;
}
static void
Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200000;
}
static void
Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe007;
}
static void
Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200020;
}
static void
Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf6;
}
static void
Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300002;
}
static void
Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb6;
}
static void
Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300008;
}
static void
Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1007;
}
static void
Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000a0;
}
static void
Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x9007;
}
static void
Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400000;
}
static void
Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa007;
}
static void
Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000c0;
}
static void
Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2007;
}
static void
Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000d0;
}
static void
Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb007;
}
static void
Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000b0;
}
static void
Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3007;
}
static void
Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000e0;
}
static void
Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x8007;
}
static void
Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200060;
}
static void
Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7;
}
static void
Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400010;
}
static void
Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4007;
}
static void
Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200050;
}
static void
Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc007;
}
static void
Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000f0;
}
static void
Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5007;
}
static void
Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200070;
}
static void
Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd007;
}
static void
Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x200090;
}
static void
Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16;
}
static void
Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x180000;
}
static void
Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x56;
}
static void
Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x190000;
}
static void
Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd6;
}
static void
Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x160000;
}
static void
Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x96;
}
static void
Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x170000;
}
static void
Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5;
}
static void
Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc0;
}
static void
Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40000;
}
static void
Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x140000;
}
static void
Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0;
}
static void
Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6;
}
static void
Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x100000;
}
static void
Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa0;
}
static void
Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee031;
}
static void
Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1002;
}
static void
Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400040;
}
static void
Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x9002;
}
static void
Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400020;
}
static void
Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2002;
}
static void
Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400080;
}
static void
Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1;
}
static void
Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x500000;
}
static void
Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2;
}
static void
Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400030;
}
static void
Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x8076;
}
static void
Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x9076;
}
static void
Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa076;
}
static void
Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa002;
}
static void
Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1a0000;
}
static void
Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x830000;
}
static void
Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1be000;
}
static void
Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x930000;
}
static void
Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c8000;
}
static void
Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa30000;
}
static void
Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c4000;
}
static void
Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb30000;
}
static void
Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c2000;
}
static void
Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x600000;
}
static void
Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1d00;
}
static void
Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x600100;
}
static void
Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1c00;
}
static void
Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20f0;
}
static void
Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16105;
}
static void
Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee0b1;
}
static void
Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x80;
}
static void
Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5002;
}
static void
Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400050;
}
static void
Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6002;
}
static void
Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400060;
}
static void
Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4002;
}
static void
Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400070;
}
static void
Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x400000;
}
static void
Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee071;
}
static void
Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x401000;
}
static void
Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee038;
}
static void
Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x402000;
}
static void
Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee034;
}
static void
Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x403000;
}
static void
Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee032;
}
static void
Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x404000;
}
static void
Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ef0a0;
}
static void
Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa10000;
}
static void
Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f5003;
}
static void
Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x810000;
}
static void
Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c7000;
}
static void
Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x910000;
}
static void
Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1f00;
}
static void
Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb10000;
}
static void
Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1e00;
}
static void
Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10000;
}
static void
Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c0000;
}
static void
Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x210000;
}
static void
Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b0000;
}
static void
Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x410000;
}
static void
Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c9000;
}
static void
Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20c0;
}
static void
Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20d0;
}
static void
Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000;
}
static void
Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2010;
}
static void
Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2020;
}
static void
Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2030;
}
static void
Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000;
}
static void
Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30100;
}
static void
Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130100;
}
static void
Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610100;
}
static void
Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30200;
}
static void
Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130200;
}
static void
Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610200;
}
static void
Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30000;
}
static void
Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130000;
}
static void
Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610000;
}
static void
Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30300;
}
static void
Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130300;
}
static void
Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610300;
}
static void
Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30500;
}
static void
Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130500;
}
static void
Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610500;
}
static void
Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3b000;
}
static void
Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13b000;
}
static void
Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3d000;
}
static void
Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e600;
}
static void
Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e600;
}
static void
Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61e600;
}
static void
Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3b100;
}
static void
Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13b100;
}
static void
Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61b100;
}
static void
Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3d100;
}
static void
Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13d100;
}
static void
Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61d100;
}
static void
Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3b200;
}
static void
Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13b200;
}
static void
Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61b200;
}
static void
Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3d200;
}
static void
Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13d200;
}
static void
Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61d200;
}
static void
Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3c200;
}
static void
Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13c200;
}
static void
Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61c200;
}
static void
Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3ee00;
}
static void
Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13ee00;
}
static void
Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61ee00;
}
static void
Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3c000;
}
static void
Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13c000;
}
static void
Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61c000;
}
static void
Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e800;
}
static void
Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e800;
}
static void
Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61e800;
}
static void
Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3f400;
}
static void
Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13f400;
}
static void
Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61f400;
}
static void
Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3f500;
}
static void
Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13f500;
}
static void
Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61f500;
}
static void
Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3eb00;
}
static void
Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e700;
}
static void
Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e700;
}
static void
Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61e700;
}
static void
Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc10000;
}
static void
Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd10000;
}
static void
Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x820000;
}
static void
Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3010;
}
static void
Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7000;
}
static void
Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e200;
}
static void
Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e200;
}
static void
Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e300;
}
static void
Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e400;
}
static void
Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e400;
}
static void
Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61e400;
}
static void
Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000;
}
static void
Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf02d;
}
static void
Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e900;
}
static void
Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e900;
}
static void
Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61e900;
}
static void
Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3ec00;
}
static void
Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13ec00;
}
static void
Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61ec00;
}
static void
Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3ed00;
}
static void
Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13ed00;
}
static void
Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61ed00;
}
static void
Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x36800;
}
static void
Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x136800;
}
static void
Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x616800;
}
static void
Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf1e000;
}
static void
Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf1e010;
}
static void
Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20000;
}
static void
Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b6000;
}
static void
Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x120000;
}
static void
Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b7000;
}
static void
Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x220000;
}
static void
Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c3000;
}
static void
Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x320000;
}
static void
Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c5000;
}
static void
Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x420000;
}
static void
Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1cf000;
}
static void
Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x8000;
}
static void
Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2480;
}
static void
Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x9000;
}
static void
Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2800;
}
static void
Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa000;
}
static void
Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ef060;
}
static void
Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb000;
}
static void
Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ef020;
}
static void
Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x76;
}
static void
Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300005;
}
static void
Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1076;
}
static void
Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x300006;
}
static void
Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc30000;
}
static void
Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1bf000;
}
static void
Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xd30000;
}
static void
Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d0000;
}
static void
Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30400;
}
static void
Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130400;
}
static void
Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610400;
}
static void
Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3ea00;
}
static void
Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13ea00;
}
static void
Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61ea00;
}
static void
Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3f000;
}
static void
Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13f000;
}
static void
Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61f000;
}
static void
Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3f100;
}
static void
Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13f100;
}
static void
Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61f100;
}
static void
Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x70c2;
}
static void
Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x70e2;
}
static void
Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x70f2;
}
static void
Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf10000;
}
static void
Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf12000;
}
static void
Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf11000;
}
static void
Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf13000;
}
static void
Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7042;
}
static void
Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7052;
}
static void
Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x47082;
}
static void
Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x57082;
}
static void
Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7062;
}
static void
Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7072;
}
static void
Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7002;
}
static void
Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7012;
}
static void
Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7022;
}
static void
Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x7032;
}
static void
Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf19000;
}
static void
Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf18000;
}
static void
Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x135300;
}
static void
Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x35300;
}
static void
Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x615300;
}
static void
Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x35a00;
}
static void
Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x135a00;
}
static void
Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x615a00;
}
static void
Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x35b00;
}
static void
Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x135b00;
}
static void
Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x615b00;
}
static void
Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x35c00;
}
static void
Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x135c00;
}
static void
Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x615c00;
}
static void
Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50c000;
}
static void
Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50d000;
}
static void
Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50b000;
}
static void
Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50f000;
}
static void
Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50e000;
}
static void
Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x504000;
}
static void
Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x505000;
}
static void
Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x503000;
}
static void
Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x507000;
}
static void
Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x506000;
}
static void
Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf1f000;
}
static void
Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x501000;
}
static void
Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x509000;
}
static void
Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3e000;
}
static void
Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x13e000;
}
static void
Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x61e000;
}
static void
Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x330000;
}
static void
Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1b9000;
}
static void
Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x430000;
}
static void
Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1bb000;
}
static void
Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x530000;
}
static void
Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ba000;
}
static void
Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x630000;
}
static void
Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1bd000;
}
static void
Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x730000;
}
static void
Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1bc000;
}
static void
Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40e000;
}
static void
Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40f000;
}
static void
Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x230000;
}
static void
Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c6000;
}
static void
Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb002;
}
static void
Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf002;
}
static void
Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe002;
}
static void
Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30c00;
}
static void
Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x130c00;
}
static void
Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x610c00;
}
static void
Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x36300;
}
static void
Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x136300;
}
static void
Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x616300;
}
static void
Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x406000;
}
static void
Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x407000;
}
static void
Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe30f00;
}
static void
Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf3f000;
}
static void
Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe30f10;
}
static void
Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf3f100;
}
static void
Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe30f20;
}
static void
Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf3f200;
}
static void
Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe30f30;
}
static void
Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf3f300;
}
static void
Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90804;
}
static void
Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca0004;
}
static void
Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90904;
}
static void
Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca1004;
}
static void
Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90a04;
}
static void
Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca2004;
}
static void
Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90b04;
}
static void
Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca3004;
}
static void
Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90c04;
}
static void
Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca4004;
}
static void
Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90d04;
}
static void
Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca5004;
}
static void
Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90e04;
}
static void
Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca6004;
}
static void
Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90f04;
}
static void
Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca7004;
}
static void
Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d1080;
}
static void
Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa50004;
}
static void
Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d2080;
}
static void
Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa90004;
}
static void
Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d3000;
}
static void
Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xac0004;
}
static void
Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d3080;
}
static void
Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xaf0004;
}
static void
Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d6080;
}
static void
Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa58004;
}
static void
Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d7000;
}
static void
Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa98004;
}
static void
Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d7080;
}
static void
Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xac8004;
}
static void
Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d8080;
}
static void
Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xaf8004;
}
static void
Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d9000;
}
static void
Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa60004;
}
static void
Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1da000;
}
static void
Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xaa0004;
}
static void
Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1dc000;
}
static void
Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xad0004;
}
static void
Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d9080;
}
static void
Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb00004;
}
static void
Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d4080;
}
static void
Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa68004;
}
static void
Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d5000;
}
static void
Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xaa8004;
}
static void
Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d6000;
}
static void
Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xad8004;
}
static void
Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d5080;
}
static void
Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb08004;
}
static void
Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1dd000;
}
static void
Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa70004;
}
static void
Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1de000;
}
static void
Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xab0004;
}
static void
Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1dd080;
}
static void
Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xae0004;
}
static void
Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1de080;
}
static void
Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb10004;
}
static void
Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1da080;
}
static void
Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa78004;
}
static void
Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1db000;
}
static void
Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xab8004;
}
static void
Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1db080;
}
static void
Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xae8004;
}
static void
Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1dc080;
}
static void
Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb18004;
}
static void
Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e8000;
}
static void
Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb20004;
}
static void
Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f0000;
}
static void
Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb50004;
}
static void
Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e1080;
}
static void
Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb80004;
}
static void
Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e2080;
}
static void
Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbb0004;
}
static void
Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ec000;
}
static void
Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb28004;
}
static void
Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e9080;
}
static void
Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb58004;
}
static void
Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ea080;
}
static void
Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb88004;
}
static void
Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1eb000;
}
static void
Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbb8004;
}
static void
Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e7080;
}
static void
Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb30004;
}
static void
Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e8080;
}
static void
Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb60004;
}
static void
Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e9000;
}
static void
Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb90004;
}
static void
Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ea000;
}
static void
Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbc0004;
}
static void
Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1df080;
}
static void
Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb38004;
}
static void
Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e1000;
}
static void
Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb68004;
}
static void
Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e2000;
}
static void
Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb98004;
}
static void
Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e4000;
}
static void
Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbc8004;
}
static void
Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e6000;
}
static void
Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb40004;
}
static void
Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e5080;
}
static void
Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb70004;
}
static void
Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e6080;
}
static void
Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xba0004;
}
static void
Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e7000;
}
static void
Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbd0004;
}
static void
Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e3000;
}
static void
Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb48004;
}
static void
Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e3080;
}
static void
Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xb78004;
}
static void
Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e4080;
}
static void
Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xba8004;
}
static void
Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1e5000;
}
static void
Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbd8004;
}
static void
Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ed030;
}
static void
Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc10004;
}
static void
Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee010;
}
static void
Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc12004;
}
static void
Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee020;
}
static void
Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc20004;
}
static void
Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ef000;
}
static void
Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc22004;
}
static void
Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ed000;
}
static void
Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc11004;
}
static void
Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee000;
}
static void
Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc13004;
}
static void
Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ed010;
}
static void
Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc21004;
}
static void
Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ed020;
}
static void
Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc23004;
}
static void
Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f0080;
}
static void
Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc30004;
}
static void
Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f00c0;
}
static void
Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc38004;
}
static void
Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3000;
}
static void
Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc40004;
}
static void
Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3040;
}
static void
Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc48004;
}
static void
Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ec080;
}
static void
Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc34004;
}
static void
Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ec0c0;
}
static void
Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc3c004;
}
static void
Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f4000;
}
static void
Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc44004;
}
static void
Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f8000;
}
static void
Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc4c004;
}
static void
Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16b88;
}
static void
Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16808;
}
static void
Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2400;
}
static void
Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90004;
}
static void
Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10780;
}
static void
Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10708;
}
static void
Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10688;
}
static void
Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10700;
}
static void
Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c200;
}
static void
Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c004;
}
static void
Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10480;
}
static void
Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10400;
}
static void
Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1df000;
}
static void
Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc00004;
}
static void
Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1eb080;
}
static void
Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc08004;
}
static void
Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3081;
}
static void
Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xcb0004;
}
static void
Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3080;
}
static void
Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xcb8004;
}
static void
Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d8000;
}
static void
Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbe0004;
}
static void
Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d4000;
}
static void
Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbe8004;
}
static void
Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d2000;
}
static void
Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbf0004;
}
static void
Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1d1000;
}
static void
Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xbf8004;
}
static void
Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x51000;
}
static void
Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16b08;
}
static void
Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16e48;
}
static void
Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16e28;
}
static void
Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16e18;
}
static void
Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16e08;
}
static void
Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16908;
}
static void
Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16888;
}
static void
Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16085;
}
static void
Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16007;
}
static void
Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2500;
}
static void
Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90414;
}
static void
Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f6000;
}
static void
Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe50014;
}
static void
Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f5000;
}
static void
Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe60014;
}
static void
Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1ee030;
}
static void
Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe72034;
}
static void
Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16006;
}
static void
Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16005;
}
static void
Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50139;
}
static void
Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16047;
}
static void
Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16027;
}
static void
Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16017;
}
static void
Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3086;
}
static void
Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe70014;
}
static void
Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3084;
}
static void
Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc70004;
}
static void
Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3082;
}
static void
Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc78004;
}
static void
Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3083;
}
static void
Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc80004;
}
static void
Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3088;
}
static void
Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc88004;
}
static void
Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10500;
}
static void
Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10788;
}
static void
Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c600;
}
static void
Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c480;
}
static void
Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10580;
}
static void
Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10588;
}
static void
Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10000;
}
static void
Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10200;
}
static void
Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10600;
}
static void
Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c400;
}
static void
Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c488;
}
static void
Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c500;
}
static void
Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10508;
}
static void
Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10608;
}
static void
Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x10680;
}
static void
Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c408;
}
static void
Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c002;
}
static void
Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c001;
}
static void
Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1c000;
}
static void
Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x52000;
}
static void
Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50035;
}
static void
Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5003c;
}
static void
Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50039;
}
static void
Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50032;
}
static void
Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50034;
}
static void
Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50000;
}
static void
Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50010;
}
static void
Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50030;
}
static void
Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50036;
}
static void
Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x500b9;
}
static void
Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x5003a;
}
static void
Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50031;
}
static void
Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50038;
}
static void
Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50033;
}
static void
Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50037;
}
static void
Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x14000;
}
static void
Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15000;
}
static void
Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x14800;
}
static void
Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16a08;
}
static void
Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16a88;
}
static void
Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16988;
}
static void
Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x18000;
}
static void
Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16c08;
}
static void
Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1000;
}
static void
Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc50004;
}
static void
Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1800;
}
static void
Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc50404;
}
static void
Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f1400;
}
static void
Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc50804;
}
static void
Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2600;
}
static void
Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90014;
}
static void
Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2504;
}
static void
Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90114;
}
static void
Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2502;
}
static void
Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90214;
}
static void
Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f5001;
}
static void
Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe10014;
}
static void
Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f5008;
}
static void
Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe20014;
}
static void
Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f5004;
}
static void
Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe30014;
}
static void
Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2000;
}
static void
Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc50c04;
}
static void
Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f2501;
}
static void
Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc90314;
}
static void
Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f5002;
}
static void
Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe40014;
}
static void
Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50800;
}
static void
Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50040;
}
static void
Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x50020;
}
static void
Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1f3085;
}
static void
Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe74014;
}
static void
Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60101;
}
static void
Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6008b;
}
static void
Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60180;
}
static void
Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6008f;
}
static void
Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6008c;
}
static void
Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60108;
}
static void
Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6008e;
}
static void
Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6008a;
}
static void
Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60104;
}
static void
Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6008d;
}
static void
Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60089;
}
static void
Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60102;
}
static void
Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60006;
}
static void
Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64000;
}
static void
Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000f;
}
static void
Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60005;
}
static void
Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60100;
}
static void
Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000e;
}
static void
Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60003;
}
static void
Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60080;
}
static void
Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000d;
}
static void
Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x68000;
}
static void
Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60008;
}
static void
Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000b;
}
static void
Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60181;
}
static void
Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6010b;
}
static void
Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60189;
}
static void
Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6010f;
}
static void
Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6010c;
}
static void
Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60187;
}
static void
Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6010e;
}
static void
Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6010a;
}
static void
Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60186;
}
static void
Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6010d;
}
static void
Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60109;
}
static void
Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60185;
}
static void
Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000c;
}
static void
Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60088;
}
static void
Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6000a;
}
static void
Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60084;
}
static void
Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60009;
}
static void
Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60082;
}
static void
Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60007;
}
static void
Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60081;
}
static void
Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60183;
}
static void
Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6018d;
}
static void
Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60188;
}
static void
Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6018b;
}
static void
Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60184;
}
static void
Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6018c;
}
static void
Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60182;
}
static void
Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6018a;
}
static void
Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15807;
}
static void
Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15806;
}
static void
Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1580a;
}
static void
Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15809;
}
static void
Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1580b;
}
static void
Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1580c;
}
static void
Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1580e;
}
static void
Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1580d;
}
static void
Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15800;
}
static void
Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16000;
}
static void
Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15802;
}
static void
Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15801;
}
static void
Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15808;
}
static void
Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15804;
}
static void
Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15805;
}
static void
Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x15803;
}
static void
Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16001;
}
static void
Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x1580f;
}
static void
Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16004;
}
static void
Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16002;
}
static void
Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16800;
}
static void
Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16008;
}
static void
Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x16003;
}
static void
Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x17000;
}
static void
Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20007;
}
static void
Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20002;
}
static void
Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000c;
}
static void
Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20003;
}
static void
Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20005;
}
static void
Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20000;
}
static void
Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20009;
}
static void
Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20004;
}
static void
Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20006;
}
static void
Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20001;
}
static void
Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000a;
}
static void
Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x20008;
}
static void
Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30008;
}
static void
Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000e;
}
static void
Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30006;
}
static void
Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30001;
}
static void
Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30002;
}
static void
Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000b;
}
static void
Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30003;
}
static void
Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000f;
}
static void
Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30004;
}
static void
Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x2000d;
}
static void
Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30005;
}
static void
Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30000;
}
static void
Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40000;
}
static void
Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000a;
}
static void
Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40004;
}
static void
Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000d;
}
static void
Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000e;
}
static void
Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30007;
}
static void
Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40001;
}
static void
Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000c;
}
static void
Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000f;
}
static void
Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x30009;
}
static void
Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40002;
}
static void
Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x3000b;
}
static void
Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000b;
}
static void
Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40005;
}
static void
Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000f;
}
static void
Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40009;
}
static void
Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000a;
}
static void
Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40008;
}
static void
Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000d;
}
static void
Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40006;
}
static void
Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000c;
}
static void
Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40003;
}
static void
Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x4000e;
}
static void
Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x40007;
}
static void
Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64004;
}
static void
Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64080;
}
static void
Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64008;
}
static void
Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64100;
}
static void
Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64003;
}
static void
Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64006;
}
static void
Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64005;
}
static void
Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64007;
}
static void
Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64009;
}
static void
Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6400c;
}
static void
Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6400a;
}
static void
Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6400b;
}
static void
Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6400d;
}
static void
Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6400f;
}
static void
Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6400e;
}
static void
Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64081;
}
static void
Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60000;
}
static void
Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60002;
}
static void
Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60001;
}
static void
Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60004;
}
static void
Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60083;
}
static void
Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60086;
}
static void
Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60085;
}
static void
Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60087;
}
static void
Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60103;
}
static void
Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60106;
}
static void
Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60105;
}
static void
Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x60107;
}
static void
Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6018e;
}
static void
Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64001;
}
static void
Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x6018f;
}
static void
Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0x64002;
}
static void
Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe00014;
}
static void
Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa00004;
}
static void
Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa10004;
}
static void
Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe7e014;
}
static void
Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xca8004;
}
static void
Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xc60004;
}
static void
Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe00024;
}
static void
Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa20004;
}
static void
Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe00004;
}
static void
Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf01004;
}
static void
Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf02004;
}
static void
Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa30004;
}
static void
Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xa40004;
}
static void
Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf11004;
}
static void
Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xf00004;
}
static void
Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe7c014;
}
static void
Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
{
slotbuf[0] = 0xe7d014;
}
static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
Opcode_break_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
};
static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
};
static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
};
/* Opcode table. */
static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
{ FUNCUNIT_ae_add32, 3 }
};
static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
{ FUNCUNIT_ae_add32, 3 }
};
static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_shift32x5, 3 },
{ FUNCUNIT_ae_add32, 3 }
};
static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_shift32x5, 3 },
{ FUNCUNIT_ae_add32, 3 }
};
static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
{ FUNCUNIT_ae_add32, 3 }
};
static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
{ FUNCUNIT_ae_add32, 3 }
};
static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
{ FUNCUNIT_ae_shift32x4, 2 },
{ FUNCUNIT_ae_subshift, 2 }
};
static xtensa_opcode_internal opcodes[] = {
{ "excw", ICLASS_xt_iclass_excw,
0,
Opcode_excw_encode_fns, 0, 0 },
{ "rfe", ICLASS_xt_iclass_rfe,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfe_encode_fns, 0, 0 },
{ "rfde", ICLASS_xt_iclass_rfde,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfde_encode_fns, 0, 0 },
{ "syscall", ICLASS_xt_iclass_syscall,
0,
Opcode_syscall_encode_fns, 0, 0 },
{ "simcall", ICLASS_xt_iclass_simcall,
0,
Opcode_simcall_encode_fns, 0, 0 },
{ "call12", ICLASS_xt_iclass_call12,
XTENSA_OPCODE_IS_CALL,
Opcode_call12_encode_fns, 0, 0 },
{ "call8", ICLASS_xt_iclass_call8,
XTENSA_OPCODE_IS_CALL,
Opcode_call8_encode_fns, 0, 0 },
{ "call4", ICLASS_xt_iclass_call4,
XTENSA_OPCODE_IS_CALL,
Opcode_call4_encode_fns, 0, 0 },
{ "callx12", ICLASS_xt_iclass_callx12,
XTENSA_OPCODE_IS_CALL,
Opcode_callx12_encode_fns, 0, 0 },
{ "callx8", ICLASS_xt_iclass_callx8,
XTENSA_OPCODE_IS_CALL,
Opcode_callx8_encode_fns, 0, 0 },
{ "callx4", ICLASS_xt_iclass_callx4,
XTENSA_OPCODE_IS_CALL,
Opcode_callx4_encode_fns, 0, 0 },
{ "entry", ICLASS_xt_iclass_entry,
0,
Opcode_entry_encode_fns, 0, 0 },
{ "movsp", ICLASS_xt_iclass_movsp,
0,
Opcode_movsp_encode_fns, 0, 0 },
{ "rotw", ICLASS_xt_iclass_rotw,
0,
Opcode_rotw_encode_fns, 0, 0 },
{ "retw", ICLASS_xt_iclass_retw,
XTENSA_OPCODE_IS_JUMP,
Opcode_retw_encode_fns, 0, 0 },
{ "retw.n", ICLASS_xt_iclass_retw,
XTENSA_OPCODE_IS_JUMP,
Opcode_retw_n_encode_fns, 0, 0 },
{ "rfwo", ICLASS_xt_iclass_rfwou,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfwo_encode_fns, 0, 0 },
{ "rfwu", ICLASS_xt_iclass_rfwou,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfwu_encode_fns, 0, 0 },
{ "l32e", ICLASS_xt_iclass_l32e,
0,
Opcode_l32e_encode_fns, 0, 0 },
{ "s32e", ICLASS_xt_iclass_s32e,
0,
Opcode_s32e_encode_fns, 0, 0 },
{ "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
0,
Opcode_rsr_windowbase_encode_fns, 0, 0 },
{ "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
0,
Opcode_wsr_windowbase_encode_fns, 0, 0 },
{ "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
0,
Opcode_xsr_windowbase_encode_fns, 0, 0 },
{ "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
0,
Opcode_rsr_windowstart_encode_fns, 0, 0 },
{ "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
0,
Opcode_wsr_windowstart_encode_fns, 0, 0 },
{ "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
0,
Opcode_xsr_windowstart_encode_fns, 0, 0 },
{ "add.n", ICLASS_xt_iclass_add_n,
0,
Opcode_add_n_encode_fns, 0, 0 },
{ "addi.n", ICLASS_xt_iclass_addi_n,
0,
Opcode_addi_n_encode_fns, 0, 0 },
{ "beqz.n", ICLASS_xt_iclass_bz6,
XTENSA_OPCODE_IS_BRANCH,
Opcode_beqz_n_encode_fns, 0, 0 },
{ "bnez.n", ICLASS_xt_iclass_bz6,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bnez_n_encode_fns, 0, 0 },
{ "ill.n", ICLASS_xt_iclass_ill_n,
0,
Opcode_ill_n_encode_fns, 0, 0 },
{ "l32i.n", ICLASS_xt_iclass_loadi4,
0,
Opcode_l32i_n_encode_fns, 0, 0 },
{ "mov.n", ICLASS_xt_iclass_mov_n,
0,
Opcode_mov_n_encode_fns, 0, 0 },
{ "movi.n", ICLASS_xt_iclass_movi_n,
0,
Opcode_movi_n_encode_fns, 0, 0 },
{ "nop.n", ICLASS_xt_iclass_nopn,
0,
Opcode_nop_n_encode_fns, 0, 0 },
{ "ret.n", ICLASS_xt_iclass_retn,
XTENSA_OPCODE_IS_JUMP,
Opcode_ret_n_encode_fns, 0, 0 },
{ "s32i.n", ICLASS_xt_iclass_storei4,
0,
Opcode_s32i_n_encode_fns, 0, 0 },
{ "rur.threadptr", ICLASS_rur_threadptr,
0,
Opcode_rur_threadptr_encode_fns, 0, 0 },
{ "wur.threadptr", ICLASS_wur_threadptr,
0,
Opcode_wur_threadptr_encode_fns, 0, 0 },
{ "addi", ICLASS_xt_iclass_addi,
0,
Opcode_addi_encode_fns, 0, 0 },
{ "addmi", ICLASS_xt_iclass_addmi,
0,
Opcode_addmi_encode_fns, 0, 0 },
{ "add", ICLASS_xt_iclass_addsub,
0,
Opcode_add_encode_fns, 0, 0 },
{ "sub", ICLASS_xt_iclass_addsub,
0,
Opcode_sub_encode_fns, 0, 0 },
{ "addx2", ICLASS_xt_iclass_addsub,
0,
Opcode_addx2_encode_fns, 0, 0 },
{ "addx4", ICLASS_xt_iclass_addsub,
0,
Opcode_addx4_encode_fns, 0, 0 },
{ "addx8", ICLASS_xt_iclass_addsub,
0,
Opcode_addx8_encode_fns, 0, 0 },
{ "subx2", ICLASS_xt_iclass_addsub,
0,
Opcode_subx2_encode_fns, 0, 0 },
{ "subx4", ICLASS_xt_iclass_addsub,
0,
Opcode_subx4_encode_fns, 0, 0 },
{ "subx8", ICLASS_xt_iclass_addsub,
0,
Opcode_subx8_encode_fns, 0, 0 },
{ "and", ICLASS_xt_iclass_bit,
0,
Opcode_and_encode_fns, 0, 0 },
{ "or", ICLASS_xt_iclass_bit,
0,
Opcode_or_encode_fns, 0, 0 },
{ "xor", ICLASS_xt_iclass_bit,
0,
Opcode_xor_encode_fns, 0, 0 },
{ "beqi", ICLASS_xt_iclass_bsi8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_beqi_encode_fns, 0, 0 },
{ "bnei", ICLASS_xt_iclass_bsi8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bnei_encode_fns, 0, 0 },
{ "bgei", ICLASS_xt_iclass_bsi8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bgei_encode_fns, 0, 0 },
{ "blti", ICLASS_xt_iclass_bsi8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_blti_encode_fns, 0, 0 },
{ "bbci", ICLASS_xt_iclass_bsi8b,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bbci_encode_fns, 0, 0 },
{ "bbsi", ICLASS_xt_iclass_bsi8b,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bbsi_encode_fns, 0, 0 },
{ "bgeui", ICLASS_xt_iclass_bsi8u,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bgeui_encode_fns, 0, 0 },
{ "bltui", ICLASS_xt_iclass_bsi8u,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bltui_encode_fns, 0, 0 },
{ "beq", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_beq_encode_fns, 0, 0 },
{ "bne", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bne_encode_fns, 0, 0 },
{ "bge", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bge_encode_fns, 0, 0 },
{ "blt", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_blt_encode_fns, 0, 0 },
{ "bgeu", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bgeu_encode_fns, 0, 0 },
{ "bltu", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bltu_encode_fns, 0, 0 },
{ "bany", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bany_encode_fns, 0, 0 },
{ "bnone", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bnone_encode_fns, 0, 0 },
{ "ball", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_ball_encode_fns, 0, 0 },
{ "bnall", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bnall_encode_fns, 0, 0 },
{ "bbc", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bbc_encode_fns, 0, 0 },
{ "bbs", ICLASS_xt_iclass_bst8,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bbs_encode_fns, 0, 0 },
{ "beqz", ICLASS_xt_iclass_bsz12,
XTENSA_OPCODE_IS_BRANCH,
Opcode_beqz_encode_fns, 0, 0 },
{ "bnez", ICLASS_xt_iclass_bsz12,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bnez_encode_fns, 0, 0 },
{ "bgez", ICLASS_xt_iclass_bsz12,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bgez_encode_fns, 0, 0 },
{ "bltz", ICLASS_xt_iclass_bsz12,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bltz_encode_fns, 0, 0 },
{ "call0", ICLASS_xt_iclass_call0,
XTENSA_OPCODE_IS_CALL,
Opcode_call0_encode_fns, 0, 0 },
{ "callx0", ICLASS_xt_iclass_callx0,
XTENSA_OPCODE_IS_CALL,
Opcode_callx0_encode_fns, 0, 0 },
{ "extui", ICLASS_xt_iclass_exti,
0,
Opcode_extui_encode_fns, 0, 0 },
{ "ill", ICLASS_xt_iclass_ill,
0,
Opcode_ill_encode_fns, 0, 0 },
{ "j", ICLASS_xt_iclass_jump,
XTENSA_OPCODE_IS_JUMP,
Opcode_j_encode_fns, 0, 0 },
{ "jx", ICLASS_xt_iclass_jumpx,
XTENSA_OPCODE_IS_JUMP,
Opcode_jx_encode_fns, 0, 0 },
{ "l16ui", ICLASS_xt_iclass_l16ui,
0,
Opcode_l16ui_encode_fns, 0, 0 },
{ "l16si", ICLASS_xt_iclass_l16si,
0,
Opcode_l16si_encode_fns, 0, 0 },
{ "l32i", ICLASS_xt_iclass_l32i,
0,
Opcode_l32i_encode_fns, 0, 0 },
{ "l32r", ICLASS_xt_iclass_l32r,
0,
Opcode_l32r_encode_fns, 0, 0 },
{ "l8ui", ICLASS_xt_iclass_l8i,
0,
Opcode_l8ui_encode_fns, 0, 0 },
{ "loop", ICLASS_xt_iclass_loop,
XTENSA_OPCODE_IS_LOOP,
Opcode_loop_encode_fns, 0, 0 },
{ "loopnez", ICLASS_xt_iclass_loopz,
XTENSA_OPCODE_IS_LOOP,
Opcode_loopnez_encode_fns, 0, 0 },
{ "loopgtz", ICLASS_xt_iclass_loopz,
XTENSA_OPCODE_IS_LOOP,
Opcode_loopgtz_encode_fns, 0, 0 },
{ "movi", ICLASS_xt_iclass_movi,
0,
Opcode_movi_encode_fns, 0, 0 },
{ "moveqz", ICLASS_xt_iclass_movz,
0,
Opcode_moveqz_encode_fns, 0, 0 },
{ "movnez", ICLASS_xt_iclass_movz,
0,
Opcode_movnez_encode_fns, 0, 0 },
{ "movltz", ICLASS_xt_iclass_movz,
0,
Opcode_movltz_encode_fns, 0, 0 },
{ "movgez", ICLASS_xt_iclass_movz,
0,
Opcode_movgez_encode_fns, 0, 0 },
{ "neg", ICLASS_xt_iclass_neg,
0,
Opcode_neg_encode_fns, 0, 0 },
{ "abs", ICLASS_xt_iclass_neg,
0,
Opcode_abs_encode_fns, 0, 0 },
{ "nop", ICLASS_xt_iclass_nop,
0,
Opcode_nop_encode_fns, 0, 0 },
{ "ret", ICLASS_xt_iclass_return,
XTENSA_OPCODE_IS_JUMP,
Opcode_ret_encode_fns, 0, 0 },
{ "s16i", ICLASS_xt_iclass_s16i,
0,
Opcode_s16i_encode_fns, 0, 0 },
{ "s32i", ICLASS_xt_iclass_s32i,
0,
Opcode_s32i_encode_fns, 0, 0 },
{ "s8i", ICLASS_xt_iclass_s8i,
0,
Opcode_s8i_encode_fns, 0, 0 },
{ "ssr", ICLASS_xt_iclass_sar,
0,
Opcode_ssr_encode_fns, 0, 0 },
{ "ssl", ICLASS_xt_iclass_sar,
0,
Opcode_ssl_encode_fns, 0, 0 },
{ "ssa8l", ICLASS_xt_iclass_sar,
0,
Opcode_ssa8l_encode_fns, 0, 0 },
{ "ssa8b", ICLASS_xt_iclass_sar,
0,
Opcode_ssa8b_encode_fns, 0, 0 },
{ "ssai", ICLASS_xt_iclass_sari,
0,
Opcode_ssai_encode_fns, 0, 0 },
{ "sll", ICLASS_xt_iclass_shifts,
0,
Opcode_sll_encode_fns, 0, 0 },
{ "src", ICLASS_xt_iclass_shiftst,
0,
Opcode_src_encode_fns, 0, 0 },
{ "srl", ICLASS_xt_iclass_shiftt,
0,
Opcode_srl_encode_fns, 0, 0 },
{ "sra", ICLASS_xt_iclass_shiftt,
0,
Opcode_sra_encode_fns, 0, 0 },
{ "slli", ICLASS_xt_iclass_slli,
0,
Opcode_slli_encode_fns, 0, 0 },
{ "srai", ICLASS_xt_iclass_srai,
0,
Opcode_srai_encode_fns, 0, 0 },
{ "srli", ICLASS_xt_iclass_srli,
0,
Opcode_srli_encode_fns, 0, 0 },
{ "memw", ICLASS_xt_iclass_memw,
0,
Opcode_memw_encode_fns, 0, 0 },
{ "extw", ICLASS_xt_iclass_extw,
0,
Opcode_extw_encode_fns, 0, 0 },
{ "isync", ICLASS_xt_iclass_isync,
0,
Opcode_isync_encode_fns, 0, 0 },
{ "rsync", ICLASS_xt_iclass_sync,
0,
Opcode_rsync_encode_fns, 0, 0 },
{ "esync", ICLASS_xt_iclass_sync,
0,
Opcode_esync_encode_fns, 0, 0 },
{ "dsync", ICLASS_xt_iclass_sync,
0,
Opcode_dsync_encode_fns, 0, 0 },
{ "rsil", ICLASS_xt_iclass_rsil,
0,
Opcode_rsil_encode_fns, 0, 0 },
{ "rsr.lend", ICLASS_xt_iclass_rsr_lend,
0,
Opcode_rsr_lend_encode_fns, 0, 0 },
{ "wsr.lend", ICLASS_xt_iclass_wsr_lend,
0,
Opcode_wsr_lend_encode_fns, 0, 0 },
{ "xsr.lend", ICLASS_xt_iclass_xsr_lend,
0,
Opcode_xsr_lend_encode_fns, 0, 0 },
{ "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
0,
Opcode_rsr_lcount_encode_fns, 0, 0 },
{ "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
0,
Opcode_wsr_lcount_encode_fns, 0, 0 },
{ "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
0,
Opcode_xsr_lcount_encode_fns, 0, 0 },
{ "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
0,
Opcode_rsr_lbeg_encode_fns, 0, 0 },
{ "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
0,
Opcode_wsr_lbeg_encode_fns, 0, 0 },
{ "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
0,
Opcode_xsr_lbeg_encode_fns, 0, 0 },
{ "rsr.sar", ICLASS_xt_iclass_rsr_sar,
0,
Opcode_rsr_sar_encode_fns, 0, 0 },
{ "wsr.sar", ICLASS_xt_iclass_wsr_sar,
0,
Opcode_wsr_sar_encode_fns, 0, 0 },
{ "xsr.sar", ICLASS_xt_iclass_xsr_sar,
0,
Opcode_xsr_sar_encode_fns, 0, 0 },
{ "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
0,
Opcode_rsr_litbase_encode_fns, 0, 0 },
{ "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
0,
Opcode_wsr_litbase_encode_fns, 0, 0 },
{ "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
0,
Opcode_xsr_litbase_encode_fns, 0, 0 },
{ "rsr.176", ICLASS_xt_iclass_rsr_176,
0,
Opcode_rsr_176_encode_fns, 0, 0 },
{ "wsr.176", ICLASS_xt_iclass_wsr_176,
0,
Opcode_wsr_176_encode_fns, 0, 0 },
{ "rsr.208", ICLASS_xt_iclass_rsr_208,
0,
Opcode_rsr_208_encode_fns, 0, 0 },
{ "rsr.ps", ICLASS_xt_iclass_rsr_ps,
0,
Opcode_rsr_ps_encode_fns, 0, 0 },
{ "wsr.ps", ICLASS_xt_iclass_wsr_ps,
0,
Opcode_wsr_ps_encode_fns, 0, 0 },
{ "xsr.ps", ICLASS_xt_iclass_xsr_ps,
0,
Opcode_xsr_ps_encode_fns, 0, 0 },
{ "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
0,
Opcode_rsr_epc1_encode_fns, 0, 0 },
{ "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
0,
Opcode_wsr_epc1_encode_fns, 0, 0 },
{ "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
0,
Opcode_xsr_epc1_encode_fns, 0, 0 },
{ "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
0,
Opcode_rsr_excsave1_encode_fns, 0, 0 },
{ "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
0,
Opcode_wsr_excsave1_encode_fns, 0, 0 },
{ "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
0,
Opcode_xsr_excsave1_encode_fns, 0, 0 },
{ "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
0,
Opcode_rsr_epc2_encode_fns, 0, 0 },
{ "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
0,
Opcode_wsr_epc2_encode_fns, 0, 0 },
{ "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
0,
Opcode_xsr_epc2_encode_fns, 0, 0 },
{ "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
0,
Opcode_rsr_excsave2_encode_fns, 0, 0 },
{ "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
0,
Opcode_wsr_excsave2_encode_fns, 0, 0 },
{ "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
0,
Opcode_xsr_excsave2_encode_fns, 0, 0 },
{ "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
0,
Opcode_rsr_eps2_encode_fns, 0, 0 },
{ "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
0,
Opcode_wsr_eps2_encode_fns, 0, 0 },
{ "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
0,
Opcode_xsr_eps2_encode_fns, 0, 0 },
{ "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
0,
Opcode_rsr_excvaddr_encode_fns, 0, 0 },
{ "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
0,
Opcode_wsr_excvaddr_encode_fns, 0, 0 },
{ "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
0,
Opcode_xsr_excvaddr_encode_fns, 0, 0 },
{ "rsr.depc", ICLASS_xt_iclass_rsr_depc,
0,
Opcode_rsr_depc_encode_fns, 0, 0 },
{ "wsr.depc", ICLASS_xt_iclass_wsr_depc,
0,
Opcode_wsr_depc_encode_fns, 0, 0 },
{ "xsr.depc", ICLASS_xt_iclass_xsr_depc,
0,
Opcode_xsr_depc_encode_fns, 0, 0 },
{ "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
0,
Opcode_rsr_exccause_encode_fns, 0, 0 },
{ "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
0,
Opcode_wsr_exccause_encode_fns, 0, 0 },
{ "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
0,
Opcode_xsr_exccause_encode_fns, 0, 0 },
{ "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
0,
Opcode_rsr_misc0_encode_fns, 0, 0 },
{ "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
0,
Opcode_wsr_misc0_encode_fns, 0, 0 },
{ "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
0,
Opcode_xsr_misc0_encode_fns, 0, 0 },
{ "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
0,
Opcode_rsr_misc1_encode_fns, 0, 0 },
{ "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
0,
Opcode_wsr_misc1_encode_fns, 0, 0 },
{ "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
0,
Opcode_xsr_misc1_encode_fns, 0, 0 },
{ "rsr.prid", ICLASS_xt_iclass_rsr_prid,
0,
Opcode_rsr_prid_encode_fns, 0, 0 },
{ "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
0,
Opcode_rsr_vecbase_encode_fns, 0, 0 },
{ "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
0,
Opcode_wsr_vecbase_encode_fns, 0, 0 },
{ "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
0,
Opcode_xsr_vecbase_encode_fns, 0, 0 },
{ "mul16u", ICLASS_xt_mul16,
0,
Opcode_mul16u_encode_fns, 0, 0 },
{ "mul16s", ICLASS_xt_mul16,
0,
Opcode_mul16s_encode_fns, 0, 0 },
{ "mull", ICLASS_xt_mul32,
0,
Opcode_mull_encode_fns, 0, 0 },
{ "rfi", ICLASS_xt_iclass_rfi,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfi_encode_fns, 0, 0 },
{ "waiti", ICLASS_xt_iclass_wait,
0,
Opcode_waiti_encode_fns, 0, 0 },
{ "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
0,
Opcode_rsr_interrupt_encode_fns, 0, 0 },
{ "wsr.intset", ICLASS_xt_iclass_wsr_intset,
0,
Opcode_wsr_intset_encode_fns, 0, 0 },
{ "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
0,
Opcode_wsr_intclear_encode_fns, 0, 0 },
{ "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
0,
Opcode_rsr_intenable_encode_fns, 0, 0 },
{ "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
0,
Opcode_wsr_intenable_encode_fns, 0, 0 },
{ "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
0,
Opcode_xsr_intenable_encode_fns, 0, 0 },
{ "break", ICLASS_xt_iclass_break,
0,
Opcode_break_encode_fns, 0, 0 },
{ "break.n", ICLASS_xt_iclass_break_n,
0,
Opcode_break_n_encode_fns, 0, 0 },
{ "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
0,
Opcode_rsr_debugcause_encode_fns, 0, 0 },
{ "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
0,
Opcode_wsr_debugcause_encode_fns, 0, 0 },
{ "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
0,
Opcode_xsr_debugcause_encode_fns, 0, 0 },
{ "rsr.icount", ICLASS_xt_iclass_rsr_icount,
0,
Opcode_rsr_icount_encode_fns, 0, 0 },
{ "wsr.icount", ICLASS_xt_iclass_wsr_icount,
0,
Opcode_wsr_icount_encode_fns, 0, 0 },
{ "xsr.icount", ICLASS_xt_iclass_xsr_icount,
0,
Opcode_xsr_icount_encode_fns, 0, 0 },
{ "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
0,
Opcode_rsr_icountlevel_encode_fns, 0, 0 },
{ "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
0,
Opcode_wsr_icountlevel_encode_fns, 0, 0 },
{ "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
0,
Opcode_xsr_icountlevel_encode_fns, 0, 0 },
{ "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
0,
Opcode_rsr_ddr_encode_fns, 0, 0 },
{ "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
0,
Opcode_wsr_ddr_encode_fns, 0, 0 },
{ "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
0,
Opcode_xsr_ddr_encode_fns, 0, 0 },
{ "rfdo", ICLASS_xt_iclass_rfdo,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfdo_encode_fns, 0, 0 },
{ "rfdd", ICLASS_xt_iclass_rfdd,
XTENSA_OPCODE_IS_JUMP,
Opcode_rfdd_encode_fns, 0, 0 },
{ "andb", ICLASS_xt_iclass_bbool1,
0,
Opcode_andb_encode_fns, 0, 0 },
{ "andbc", ICLASS_xt_iclass_bbool1,
0,
Opcode_andbc_encode_fns, 0, 0 },
{ "orb", ICLASS_xt_iclass_bbool1,
0,
Opcode_orb_encode_fns, 0, 0 },
{ "orbc", ICLASS_xt_iclass_bbool1,
0,
Opcode_orbc_encode_fns, 0, 0 },
{ "xorb", ICLASS_xt_iclass_bbool1,
0,
Opcode_xorb_encode_fns, 0, 0 },
{ "any4", ICLASS_xt_iclass_bbool4,
0,
Opcode_any4_encode_fns, 0, 0 },
{ "all4", ICLASS_xt_iclass_bbool4,
0,
Opcode_all4_encode_fns, 0, 0 },
{ "any8", ICLASS_xt_iclass_bbool8,
0,
Opcode_any8_encode_fns, 0, 0 },
{ "all8", ICLASS_xt_iclass_bbool8,
0,
Opcode_all8_encode_fns, 0, 0 },
{ "bf", ICLASS_xt_iclass_bbranch,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bf_encode_fns, 0, 0 },
{ "bt", ICLASS_xt_iclass_bbranch,
XTENSA_OPCODE_IS_BRANCH,
Opcode_bt_encode_fns, 0, 0 },
{ "movf", ICLASS_xt_iclass_bmove,
0,
Opcode_movf_encode_fns, 0, 0 },
{ "movt", ICLASS_xt_iclass_bmove,
0,
Opcode_movt_encode_fns, 0, 0 },
{ "rsr.br", ICLASS_xt_iclass_RSR_BR,
0,
Opcode_rsr_br_encode_fns, 0, 0 },
{ "wsr.br", ICLASS_xt_iclass_WSR_BR,
0,
Opcode_wsr_br_encode_fns, 0, 0 },
{ "xsr.br", ICLASS_xt_iclass_XSR_BR,
0,
Opcode_xsr_br_encode_fns, 0, 0 },
{ "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
0,
Opcode_rsr_ccount_encode_fns, 0, 0 },
{ "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
0,
Opcode_wsr_ccount_encode_fns, 0, 0 },
{ "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
0,
Opcode_xsr_ccount_encode_fns, 0, 0 },
{ "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
0,
Opcode_rsr_ccompare0_encode_fns, 0, 0 },
{ "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
0,
Opcode_wsr_ccompare0_encode_fns, 0, 0 },
{ "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
0,
Opcode_xsr_ccompare0_encode_fns, 0, 0 },
{ "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
0,
Opcode_rsr_ccompare1_encode_fns, 0, 0 },
{ "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
0,
Opcode_wsr_ccompare1_encode_fns, 0, 0 },
{ "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
0,
Opcode_xsr_ccompare1_encode_fns, 0, 0 },
{ "ipf", ICLASS_xt_iclass_icache,
0,
Opcode_ipf_encode_fns, 0, 0 },
{ "ihi", ICLASS_xt_iclass_icache,
0,
Opcode_ihi_encode_fns, 0, 0 },
{ "iii", ICLASS_xt_iclass_icache_inv,
0,
Opcode_iii_encode_fns, 0, 0 },
{ "lict", ICLASS_xt_iclass_licx,
0,
Opcode_lict_encode_fns, 0, 0 },
{ "licw", ICLASS_xt_iclass_licx,
0,
Opcode_licw_encode_fns, 0, 0 },
{ "sict", ICLASS_xt_iclass_sicx,
0,
Opcode_sict_encode_fns, 0, 0 },
{ "sicw", ICLASS_xt_iclass_sicx,
0,
Opcode_sicw_encode_fns, 0, 0 },
{ "dhwb", ICLASS_xt_iclass_dcache,
0,
Opcode_dhwb_encode_fns, 0, 0 },
{ "dhwbi", ICLASS_xt_iclass_dcache,
0,
Opcode_dhwbi_encode_fns, 0, 0 },
{ "diwb", ICLASS_xt_iclass_dcache_ind,
0,
Opcode_diwb_encode_fns, 0, 0 },
{ "diwbi", ICLASS_xt_iclass_dcache_ind,
0,
Opcode_diwbi_encode_fns, 0, 0 },
{ "dhi", ICLASS_xt_iclass_dcache_inv,
0,
Opcode_dhi_encode_fns, 0, 0 },
{ "dii", ICLASS_xt_iclass_dcache_inv,
0,
Opcode_dii_encode_fns, 0, 0 },
{ "dpfr", ICLASS_xt_iclass_dpf,
0,
Opcode_dpfr_encode_fns, 0, 0 },
{ "dpfw", ICLASS_xt_iclass_dpf,
0,
Opcode_dpfw_encode_fns, 0, 0 },
{ "dpfro", ICLASS_xt_iclass_dpf,
0,
Opcode_dpfro_encode_fns, 0, 0 },
{ "dpfwo", ICLASS_xt_iclass_dpf,
0,
Opcode_dpfwo_encode_fns, 0, 0 },
{ "sdct", ICLASS_xt_iclass_sdct,
0,
Opcode_sdct_encode_fns, 0, 0 },
{ "ldct", ICLASS_xt_iclass_ldct,
0,
Opcode_ldct_encode_fns, 0, 0 },
{ "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
0,
Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
{ "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
0,
Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
{ "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
0,
Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
{ "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
0,
Opcode_rsr_rasid_encode_fns, 0, 0 },
{ "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
0,
Opcode_wsr_rasid_encode_fns, 0, 0 },
{ "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
0,
Opcode_xsr_rasid_encode_fns, 0, 0 },
{ "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
0,
Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
{ "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
0,
Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
{ "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
0,
Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
{ "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
0,
Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
{ "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
0,
Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
{ "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
0,
Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
{ "idtlb", ICLASS_xt_iclass_idtlb,
0,
Opcode_idtlb_encode_fns, 0, 0 },
{ "pdtlb", ICLASS_xt_iclass_rdtlb,
0,
Opcode_pdtlb_encode_fns, 0, 0 },
{ "rdtlb0", ICLASS_xt_iclass_rdtlb,
0,
Opcode_rdtlb0_encode_fns, 0, 0 },
{ "rdtlb1", ICLASS_xt_iclass_rdtlb,
0,
Opcode_rdtlb1_encode_fns, 0, 0 },
{ "wdtlb", ICLASS_xt_iclass_wdtlb,
0,
Opcode_wdtlb_encode_fns, 0, 0 },
{ "iitlb", ICLASS_xt_iclass_iitlb,
0,
Opcode_iitlb_encode_fns, 0, 0 },
{ "pitlb", ICLASS_xt_iclass_ritlb,
0,
Opcode_pitlb_encode_fns, 0, 0 },
{ "ritlb0", ICLASS_xt_iclass_ritlb,
0,
Opcode_ritlb0_encode_fns, 0, 0 },
{ "ritlb1", ICLASS_xt_iclass_ritlb,
0,
Opcode_ritlb1_encode_fns, 0, 0 },
{ "witlb", ICLASS_xt_iclass_witlb,
0,
Opcode_witlb_encode_fns, 0, 0 },
{ "ldpte", ICLASS_xt_iclass_ldpte,
0,
Opcode_ldpte_encode_fns, 0, 0 },
{ "hwwitlba", ICLASS_xt_iclass_hwwitlba,
XTENSA_OPCODE_IS_BRANCH,
Opcode_hwwitlba_encode_fns, 0, 0 },
{ "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
0,
Opcode_hwwdtlba_encode_fns, 0, 0 },
{ "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
0,
Opcode_rsr_cpenable_encode_fns, 0, 0 },
{ "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
0,
Opcode_wsr_cpenable_encode_fns, 0, 0 },
{ "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
0,
Opcode_xsr_cpenable_encode_fns, 0, 0 },
{ "clamps", ICLASS_xt_iclass_clamp,
0,
Opcode_clamps_encode_fns, 0, 0 },
{ "min", ICLASS_xt_iclass_minmax,
0,
Opcode_min_encode_fns, 0, 0 },
{ "max", ICLASS_xt_iclass_minmax,
0,
Opcode_max_encode_fns, 0, 0 },
{ "minu", ICLASS_xt_iclass_minmax,
0,
Opcode_minu_encode_fns, 0, 0 },
{ "maxu", ICLASS_xt_iclass_minmax,
0,
Opcode_maxu_encode_fns, 0, 0 },
{ "nsa", ICLASS_xt_iclass_nsa,
0,
Opcode_nsa_encode_fns, 0, 0 },
{ "nsau", ICLASS_xt_iclass_nsa,
0,
Opcode_nsau_encode_fns, 0, 0 },
{ "sext", ICLASS_xt_iclass_sx,
0,
Opcode_sext_encode_fns, 0, 0 },
{ "l32ai", ICLASS_xt_iclass_l32ai,
0,
Opcode_l32ai_encode_fns, 0, 0 },
{ "s32ri", ICLASS_xt_iclass_s32ri,
0,
Opcode_s32ri_encode_fns, 0, 0 },
{ "s32c1i", ICLASS_xt_iclass_s32c1i,
0,
Opcode_s32c1i_encode_fns, 0, 0 },
{ "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
0,
Opcode_rsr_scompare1_encode_fns, 0, 0 },
{ "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
0,
Opcode_wsr_scompare1_encode_fns, 0, 0 },
{ "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
0,
Opcode_xsr_scompare1_encode_fns, 0, 0 },
{ "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
0,
Opcode_rsr_atomctl_encode_fns, 0, 0 },
{ "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
0,
Opcode_wsr_atomctl_encode_fns, 0, 0 },
{ "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
0,
Opcode_xsr_atomctl_encode_fns, 0, 0 },
{ "rer", ICLASS_xt_iclass_rer,
0,
Opcode_rer_encode_fns, 0, 0 },
{ "wer", ICLASS_xt_iclass_wer,
0,
Opcode_wer_encode_fns, 0, 0 },
{ "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
0,
Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
{ "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
0,
Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
{ "rur.ae_bithead", ICLASS_rur_ae_bithead,
0,
Opcode_rur_ae_bithead_encode_fns, 0, 0 },
{ "wur.ae_bithead", ICLASS_wur_ae_bithead,
0,
Opcode_wur_ae_bithead_encode_fns, 0, 0 },
{ "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
0,
Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
{ "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
0,
Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
{ "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
0,
Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
{ "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
0,
Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
{ "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
0,
Opcode_rur_ae_overflow_encode_fns, 0, 0 },
{ "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
0,
Opcode_wur_ae_overflow_encode_fns, 0, 0 },
{ "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
0,
Opcode_rur_ae_sar_encode_fns, 0, 0 },
{ "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
0,
Opcode_wur_ae_sar_encode_fns, 0, 0 },
{ "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
0,
Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
{ "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
0,
Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
{ "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
0,
Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
{ "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
0,
Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
{ "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
0,
Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
{ "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
0,
Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
{ "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
0,
Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
{ "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
0,
Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
{ "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
0,
Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
{ "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
0,
Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
{ "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
0,
Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
{ "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
0,
Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
{ "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
0,
Opcode_ae_lp16f_i_encode_fns, 0, 0 },
{ "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
0,
Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
{ "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
0,
Opcode_ae_lp16f_x_encode_fns, 0, 0 },
{ "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
0,
Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
{ "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
0,
Opcode_ae_lp24_i_encode_fns, 0, 0 },
{ "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
0,
Opcode_ae_lp24_iu_encode_fns, 0, 0 },
{ "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
0,
Opcode_ae_lp24_x_encode_fns, 0, 0 },
{ "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
0,
Opcode_ae_lp24_xu_encode_fns, 0, 0 },
{ "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
0,
Opcode_ae_lp24f_i_encode_fns, 0, 0 },
{ "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
0,
Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
{ "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
0,
Opcode_ae_lp24f_x_encode_fns, 0, 0 },
{ "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
0,
Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
{ "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
0,
Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
{ "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
0,
Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
{ "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
0,
Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
{ "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
0,
Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
{ "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
0,
Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
{ "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
0,
Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
{ "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
0,
Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
{ "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
0,
Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
{ "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
0,
Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
{ "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
0,
Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
{ "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
0,
Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
{ "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
0,
Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
{ "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
0,
Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
{ "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
0,
Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
{ "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
0,
Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
{ "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
0,
Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
{ "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
0,
Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
{ "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
0,
Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
{ "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
0,
Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
{ "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
0,
Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
{ "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
0,
Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
{ "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
0,
Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
{ "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
0,
Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
{ "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
0,
Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
{ "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
0,
Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
{ "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
0,
Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
{ "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
0,
Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
{ "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
0,
Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
{ "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
0,
Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
{ "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
0,
Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
{ "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
0,
Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
{ "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
0,
Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
{ "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
0,
Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
{ "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
0,
Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
{ "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
0,
Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
{ "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
0,
Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
{ "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
0,
Opcode_ae_lq56_i_encode_fns, 0, 0 },
{ "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
0,
Opcode_ae_lq56_iu_encode_fns, 0, 0 },
{ "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
0,
Opcode_ae_lq56_x_encode_fns, 0, 0 },
{ "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
0,
Opcode_ae_lq56_xu_encode_fns, 0, 0 },
{ "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
0,
Opcode_ae_lq32f_i_encode_fns, 0, 0 },
{ "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
0,
Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
{ "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
0,
Opcode_ae_lq32f_x_encode_fns, 0, 0 },
{ "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
0,
Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
{ "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
0,
Opcode_ae_sq56s_i_encode_fns, 0, 0 },
{ "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
0,
Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
{ "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
0,
Opcode_ae_sq56s_x_encode_fns, 0, 0 },
{ "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
0,
Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
{ "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
0,
Opcode_ae_sq32f_i_encode_fns, 0, 0 },
{ "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
0,
Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
{ "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
0,
Opcode_ae_sq32f_x_encode_fns, 0, 0 },
{ "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
0,
Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
{ "ae_zerop48", ICLASS_ae_iclass_zerop48,
0,
Opcode_ae_zerop48_encode_fns, 0, 0 },
{ "ae_movp48", ICLASS_ae_iclass_movp48,
0,
Opcode_ae_movp48_encode_fns, 0, 0 },
{ "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
0,
Opcode_ae_selp24_ll_encode_fns, 0, 0 },
{ "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
0,
Opcode_ae_selp24_lh_encode_fns, 0, 0 },
{ "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
0,
Opcode_ae_selp24_hl_encode_fns, 0, 0 },
{ "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
0,
Opcode_ae_selp24_hh_encode_fns, 0, 0 },
{ "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
0,
Opcode_ae_movtp24x2_encode_fns, 0, 0 },
{ "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
0,
Opcode_ae_movfp24x2_encode_fns, 0, 0 },
{ "ae_movtp48", ICLASS_ae_iclass_movtp48,
0,
Opcode_ae_movtp48_encode_fns, 0, 0 },
{ "ae_movfp48", ICLASS_ae_iclass_movfp48,
0,
Opcode_ae_movfp48_encode_fns, 0, 0 },
{ "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
0,
Opcode_ae_movpa24x2_encode_fns, 0, 0 },
{ "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
0,
Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
{ "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
0,
Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
{ "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
0,
Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
{ "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
0,
Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
{ "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
0,
Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
{ "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
0,
Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
{ "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
0,
Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
{ "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
0,
Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
{ "ae_truncp16", ICLASS_ae_iclass_truncp16,
0,
Opcode_ae_truncp16_encode_fns, 0, 0 },
{ "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
0,
Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
{ "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
0,
Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
{ "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
0,
Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
{ "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
0,
Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
{ "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
0,
Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
{ "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
0,
Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
{ "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
0,
Opcode_ae_zeroq56_encode_fns, 0, 0 },
{ "ae_movq56", ICLASS_ae_iclass_movq56,
0,
Opcode_ae_movq56_encode_fns, 0, 0 },
{ "ae_movtq56", ICLASS_ae_iclass_movtq56,
0,
Opcode_ae_movtq56_encode_fns, 0, 0 },
{ "ae_movfq56", ICLASS_ae_iclass_movfq56,
0,
Opcode_ae_movfq56_encode_fns, 0, 0 },
{ "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
0,
Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
{ "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
0,
Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
{ "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
0,
Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
{ "ae_satq48s", ICLASS_ae_iclass_satq48s,
0,
Opcode_ae_satq48s_encode_fns, 0, 0 },
{ "ae_truncq32", ICLASS_ae_iclass_truncq32,
0,
Opcode_ae_truncq32_encode_fns, 0, 0 },
{ "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
0,
Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
{ "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
0,
Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
{ "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
0,
Opcode_ae_trunca32q48_encode_fns, 0, 0 },
{ "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
0,
Opcode_ae_movap24s_l_encode_fns, 0, 0 },
{ "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
0,
Opcode_ae_movap24s_h_encode_fns, 0, 0 },
{ "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
0,
Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
{ "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
0,
Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
{ "ae_addp24", ICLASS_ae_iclass_addp24,
0,
Opcode_ae_addp24_encode_fns, 0, 0 },
{ "ae_subp24", ICLASS_ae_iclass_subp24,
0,
Opcode_ae_subp24_encode_fns, 0, 0 },
{ "ae_negp24", ICLASS_ae_iclass_negp24,
0,
Opcode_ae_negp24_encode_fns, 0, 0 },
{ "ae_absp24", ICLASS_ae_iclass_absp24,
0,
Opcode_ae_absp24_encode_fns, 0, 0 },
{ "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
0,
Opcode_ae_maxp24s_encode_fns, 0, 0 },
{ "ae_minp24s", ICLASS_ae_iclass_minp24s,
0,
Opcode_ae_minp24s_encode_fns, 0, 0 },
{ "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
0,
Opcode_ae_maxbp24s_encode_fns, 0, 0 },
{ "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
0,
Opcode_ae_minbp24s_encode_fns, 0, 0 },
{ "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
0,
Opcode_ae_addsp24s_encode_fns, 0, 0 },
{ "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
0,
Opcode_ae_subsp24s_encode_fns, 0, 0 },
{ "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
0,
Opcode_ae_negsp24s_encode_fns, 0, 0 },
{ "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
0,
Opcode_ae_abssp24s_encode_fns, 0, 0 },
{ "ae_andp48", ICLASS_ae_iclass_andp48,
0,
Opcode_ae_andp48_encode_fns, 0, 0 },
{ "ae_nandp48", ICLASS_ae_iclass_nandp48,
0,
Opcode_ae_nandp48_encode_fns, 0, 0 },
{ "ae_orp48", ICLASS_ae_iclass_orp48,
0,
Opcode_ae_orp48_encode_fns, 0, 0 },
{ "ae_xorp48", ICLASS_ae_iclass_xorp48,
0,
Opcode_ae_xorp48_encode_fns, 0, 0 },
{ "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
0,
Opcode_ae_ltp24s_encode_fns, 0, 0 },
{ "ae_lep24s", ICLASS_ae_iclass_lep24s,
0,
Opcode_ae_lep24s_encode_fns, 0, 0 },
{ "ae_eqp24", ICLASS_ae_iclass_eqp24,
0,
Opcode_ae_eqp24_encode_fns, 0, 0 },
{ "ae_addq56", ICLASS_ae_iclass_addq56,
0,
Opcode_ae_addq56_encode_fns, 0, 0 },
{ "ae_subq56", ICLASS_ae_iclass_subq56,
0,
Opcode_ae_subq56_encode_fns, 0, 0 },
{ "ae_negq56", ICLASS_ae_iclass_negq56,
0,
Opcode_ae_negq56_encode_fns, 0, 0 },
{ "ae_absq56", ICLASS_ae_iclass_absq56,
0,
Opcode_ae_absq56_encode_fns, 0, 0 },
{ "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
0,
Opcode_ae_maxq56s_encode_fns, 0, 0 },
{ "ae_minq56s", ICLASS_ae_iclass_minq56s,
0,
Opcode_ae_minq56s_encode_fns, 0, 0 },
{ "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
0,
Opcode_ae_maxbq56s_encode_fns, 0, 0 },
{ "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
0,
Opcode_ae_minbq56s_encode_fns, 0, 0 },
{ "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
0,
Opcode_ae_addsq56s_encode_fns, 0, 0 },
{ "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
0,
Opcode_ae_subsq56s_encode_fns, 0, 0 },
{ "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
0,
Opcode_ae_negsq56s_encode_fns, 0, 0 },
{ "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
0,
Opcode_ae_abssq56s_encode_fns, 0, 0 },
{ "ae_andq56", ICLASS_ae_iclass_andq56,
0,
Opcode_ae_andq56_encode_fns, 0, 0 },
{ "ae_nandq56", ICLASS_ae_iclass_nandq56,
0,
Opcode_ae_nandq56_encode_fns, 0, 0 },
{ "ae_orq56", ICLASS_ae_iclass_orq56,
0,
Opcode_ae_orq56_encode_fns, 0, 0 },
{ "ae_xorq56", ICLASS_ae_iclass_xorq56,
0,
Opcode_ae_xorq56_encode_fns, 0, 0 },
{ "ae_sllip24", ICLASS_ae_iclass_sllip24,
0,
Opcode_ae_sllip24_encode_fns, 0, 0 },
{ "ae_srlip24", ICLASS_ae_iclass_srlip24,
0,
Opcode_ae_srlip24_encode_fns, 0, 0 },
{ "ae_sraip24", ICLASS_ae_iclass_sraip24,
0,
Opcode_ae_sraip24_encode_fns, 0, 0 },
{ "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
0,
Opcode_ae_sllsp24_encode_fns, 0, 0 },
{ "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
0,
Opcode_ae_srlsp24_encode_fns, 0, 0 },
{ "ae_srasp24", ICLASS_ae_iclass_srasp24,
0,
Opcode_ae_srasp24_encode_fns, 0, 0 },
{ "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
0,
Opcode_ae_sllisp24s_encode_fns, 0, 0 },
{ "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
0,
Opcode_ae_sllssp24s_encode_fns, 0, 0 },
{ "ae_slliq56", ICLASS_ae_iclass_slliq56,
0,
Opcode_ae_slliq56_encode_fns, 0, 0 },
{ "ae_srliq56", ICLASS_ae_iclass_srliq56,
0,
Opcode_ae_srliq56_encode_fns, 0, 0 },
{ "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
0,
Opcode_ae_sraiq56_encode_fns, 0, 0 },
{ "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
0,
Opcode_ae_sllsq56_encode_fns, 0, 0 },
{ "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
0,
Opcode_ae_srlsq56_encode_fns, 0, 0 },
{ "ae_srasq56", ICLASS_ae_iclass_srasq56,
0,
Opcode_ae_srasq56_encode_fns, 0, 0 },
{ "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
0,
Opcode_ae_sllaq56_encode_fns, 0, 0 },
{ "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
0,
Opcode_ae_srlaq56_encode_fns, 0, 0 },
{ "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
0,
Opcode_ae_sraaq56_encode_fns, 0, 0 },
{ "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
0,
Opcode_ae_sllisq56s_encode_fns, 0, 0 },
{ "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
0,
Opcode_ae_sllssq56s_encode_fns, 0, 0 },
{ "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
0,
Opcode_ae_sllasq56s_encode_fns, 0, 0 },
{ "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
0,
Opcode_ae_ltq56s_encode_fns, 0, 0 },
{ "ae_leq56s", ICLASS_ae_iclass_leq56s,
0,
Opcode_ae_leq56s_encode_fns, 0, 0 },
{ "ae_eqq56", ICLASS_ae_iclass_eqq56,
0,
Opcode_ae_eqq56_encode_fns, 0, 0 },
{ "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
0,
Opcode_ae_nsaq56s_encode_fns, 0, 0 },
{ "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
0,
Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
{ "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
0,
Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
{ "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
0,
Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
{ "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
0,
Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
{ "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
0,
Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
{ "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
0,
Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
{ "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
0,
Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
{ "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
0,
Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
{ "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
0,
Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
{ "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
0,
Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
{ "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
0,
Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
{ "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
0,
Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
{ "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
0,
Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
{ "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
0,
Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
{ "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
0,
Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
{ "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
0,
Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
{ "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
0,
Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
{ "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
0,
Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
{ "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
0,
Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
{ "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
0,
Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
{ "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
0,
Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
{ "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
0,
Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
{ "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
0,
Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
{ "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
0,
Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
{ "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
0,
Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
{ "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
0,
Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
{ "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
0,
Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
{ "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
0,
Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
{ "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
0,
Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
{ "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
0,
Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
{ "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
0,
Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
{ "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
0,
Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
{ "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
0,
Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
{ "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
0,
Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
{ "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
0,
Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
{ "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
0,
Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
{ "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
0,
Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
{ "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
0,
Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
{ "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
0,
Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
{ "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
0,
Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
{ "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
0,
Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
{ "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
0,
Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
{ "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
0,
Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
{ "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
0,
Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
{ "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
0,
Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
{ "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
0,
Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
{ "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
0,
Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
{ "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
0,
Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
{ "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
0,
Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
{ "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
0,
Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
{ "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
0,
Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
{ "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
0,
Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
{ "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
0,
Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
{ "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
0,
Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
{ "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
0,
Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
{ "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
0,
Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
{ "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
0,
Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
{ "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
0,
Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
{ "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
0,
Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
{ "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
0,
Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
{ "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
0,
Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
{ "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
0,
Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
{ "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
0,
Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
{ "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
0,
Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
{ "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
0,
Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
{ "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
0,
Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
{ "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
0,
Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
{ "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
0,
Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
{ "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
0,
Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
{ "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
0,
Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
{ "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
0,
Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
{ "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
0,
Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
{ "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
0,
Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
{ "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
0,
Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
{ "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
0,
Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
{ "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
0,
Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
{ "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
0,
Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
0,
Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
0,
Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
0,
Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
0,
Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
0,
Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
0,
Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
0,
Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
0,
Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
0,
Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
0,
Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
0,
Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
0,
Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
0,
Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
0,
Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
0,
Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
0,
Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
0,
Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
0,
Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
0,
Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
0,
Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
0,
Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
0,
Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
0,
Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
0,
Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
0,
Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
0,
Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
0,
Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
0,
Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
0,
Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
0,
Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
0,
Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
0,
Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
0,
Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
0,
Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
0,
Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
0,
Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
0,
Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
{ "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
0,
Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
0,
Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
{ "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
0,
Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
0,
Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
{ "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
0,
Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
0,
Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
{ "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
0,
Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
0,
Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
{ "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
0,
Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
0,
Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
{ "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
0,
Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
0,
Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
0,
Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
0,
Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
0,
Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
0,
Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
0,
Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
0,
Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
0,
Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
0,
Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
0,
Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
0,
Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
0,
Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
0,
Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
0,
Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
0,
Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
0,
Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
0,
Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
0,
Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
0,
Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
0,
Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
0,
Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
0,
Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
0,
Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
0,
Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
0,
Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
0,
Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
0,
Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
0,
Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
0,
Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
{ "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
0,
Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
0,
Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
{ "ae_sha32", ICLASS_ae_iclass_sha32,
0,
Opcode_ae_sha32_encode_fns, 0, 0 },
{ "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
0,
Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
{ "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
0,
Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
{ "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
0,
Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
{ "ae_vldsht", ICLASS_ae_iclass_vldsht,
0,
Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
{ "ae_lb", ICLASS_ae_iclass_lb,
0,
Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
{ "ae_lbi", ICLASS_ae_iclass_lbi,
0,
Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
{ "ae_lbk", ICLASS_ae_iclass_lbk,
0,
Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
{ "ae_lbki", ICLASS_ae_iclass_lbki,
0,
Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
{ "ae_db", ICLASS_ae_iclass_db,
0,
Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
{ "ae_dbi", ICLASS_ae_iclass_dbi,
0,
Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
{ "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
0,
Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
{ "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
0,
Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
{ "ae_sb", ICLASS_ae_iclass_sb,
0,
Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
{ "ae_sbi", ICLASS_ae_iclass_sbi,
0,
Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
{ "ae_vles16c", ICLASS_ae_iclass_vles16c,
0,
Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
{ "ae_sbf", ICLASS_ae_iclass_sbf,
0,
Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }
};
enum xtensa_opcode_id {
OPCODE_EXCW,
OPCODE_RFE,
OPCODE_RFDE,
OPCODE_SYSCALL,
OPCODE_SIMCALL,
OPCODE_CALL12,
OPCODE_CALL8,
OPCODE_CALL4,
OPCODE_CALLX12,
OPCODE_CALLX8,
OPCODE_CALLX4,
OPCODE_ENTRY,
OPCODE_MOVSP,
OPCODE_ROTW,
OPCODE_RETW,
OPCODE_RETW_N,
OPCODE_RFWO,
OPCODE_RFWU,
OPCODE_L32E,
OPCODE_S32E,
OPCODE_RSR_WINDOWBASE,
OPCODE_WSR_WINDOWBASE,
OPCODE_XSR_WINDOWBASE,
OPCODE_RSR_WINDOWSTART,
OPCODE_WSR_WINDOWSTART,
OPCODE_XSR_WINDOWSTART,
OPCODE_ADD_N,
OPCODE_ADDI_N,
OPCODE_BEQZ_N,
OPCODE_BNEZ_N,
OPCODE_ILL_N,
OPCODE_L32I_N,
OPCODE_MOV_N,
OPCODE_MOVI_N,
OPCODE_NOP_N,
OPCODE_RET_N,
OPCODE_S32I_N,
OPCODE_RUR_THREADPTR,
OPCODE_WUR_THREADPTR,
OPCODE_ADDI,
OPCODE_ADDMI,
OPCODE_ADD,
OPCODE_SUB,
OPCODE_ADDX2,
OPCODE_ADDX4,
OPCODE_ADDX8,
OPCODE_SUBX2,
OPCODE_SUBX4,
OPCODE_SUBX8,
OPCODE_AND,
OPCODE_OR,
OPCODE_XOR,
OPCODE_BEQI,
OPCODE_BNEI,
OPCODE_BGEI,
OPCODE_BLTI,
OPCODE_BBCI,
OPCODE_BBSI,
OPCODE_BGEUI,
OPCODE_BLTUI,
OPCODE_BEQ,
OPCODE_BNE,
OPCODE_BGE,
OPCODE_BLT,
OPCODE_BGEU,
OPCODE_BLTU,
OPCODE_BANY,
OPCODE_BNONE,
OPCODE_BALL,
OPCODE_BNALL,
OPCODE_BBC,
OPCODE_BBS,
OPCODE_BEQZ,
OPCODE_BNEZ,
OPCODE_BGEZ,
OPCODE_BLTZ,
OPCODE_CALL0,
OPCODE_CALLX0,
OPCODE_EXTUI,
OPCODE_ILL,
OPCODE_J,
OPCODE_JX,
OPCODE_L16UI,
OPCODE_L16SI,
OPCODE_L32I,
OPCODE_L32R,
OPCODE_L8UI,
OPCODE_LOOP,
OPCODE_LOOPNEZ,
OPCODE_LOOPGTZ,
OPCODE_MOVI,
OPCODE_MOVEQZ,
OPCODE_MOVNEZ,
OPCODE_MOVLTZ,
OPCODE_MOVGEZ,
OPCODE_NEG,
OPCODE_ABS,
OPCODE_NOP,
OPCODE_RET,
OPCODE_S16I,
OPCODE_S32I,
OPCODE_S8I,
OPCODE_SSR,
OPCODE_SSL,
OPCODE_SSA8L,
OPCODE_SSA8B,
OPCODE_SSAI,
OPCODE_SLL,
OPCODE_SRC,
OPCODE_SRL,
OPCODE_SRA,
OPCODE_SLLI,
OPCODE_SRAI,
OPCODE_SRLI,
OPCODE_MEMW,
OPCODE_EXTW,
OPCODE_ISYNC,
OPCODE_RSYNC,
OPCODE_ESYNC,
OPCODE_DSYNC,
OPCODE_RSIL,
OPCODE_RSR_LEND,
OPCODE_WSR_LEND,
OPCODE_XSR_LEND,
OPCODE_RSR_LCOUNT,
OPCODE_WSR_LCOUNT,
OPCODE_XSR_LCOUNT,
OPCODE_RSR_LBEG,
OPCODE_WSR_LBEG,
OPCODE_XSR_LBEG,
OPCODE_RSR_SAR,
OPCODE_WSR_SAR,
OPCODE_XSR_SAR,
OPCODE_RSR_LITBASE,
OPCODE_WSR_LITBASE,
OPCODE_XSR_LITBASE,
OPCODE_RSR_176,
OPCODE_WSR_176,
OPCODE_RSR_208,
OPCODE_RSR_PS,
OPCODE_WSR_PS,
OPCODE_XSR_PS,
OPCODE_RSR_EPC1,
OPCODE_WSR_EPC1,
OPCODE_XSR_EPC1,
OPCODE_RSR_EXCSAVE1,
OPCODE_WSR_EXCSAVE1,
OPCODE_XSR_EXCSAVE1,
OPCODE_RSR_EPC2,
OPCODE_WSR_EPC2,
OPCODE_XSR_EPC2,
OPCODE_RSR_EXCSAVE2,
OPCODE_WSR_EXCSAVE2,
OPCODE_XSR_EXCSAVE2,
OPCODE_RSR_EPS2,
OPCODE_WSR_EPS2,
OPCODE_XSR_EPS2,
OPCODE_RSR_EXCVADDR,
OPCODE_WSR_EXCVADDR,
OPCODE_XSR_EXCVADDR,
OPCODE_RSR_DEPC,
OPCODE_WSR_DEPC,
OPCODE_XSR_DEPC,
OPCODE_RSR_EXCCAUSE,
OPCODE_WSR_EXCCAUSE,
OPCODE_XSR_EXCCAUSE,
OPCODE_RSR_MISC0,
OPCODE_WSR_MISC0,
OPCODE_XSR_MISC0,
OPCODE_RSR_MISC1,
OPCODE_WSR_MISC1,
OPCODE_XSR_MISC1,
OPCODE_RSR_PRID,
OPCODE_RSR_VECBASE,
OPCODE_WSR_VECBASE,
OPCODE_XSR_VECBASE,
OPCODE_MUL16U,
OPCODE_MUL16S,
OPCODE_MULL,
OPCODE_RFI,
OPCODE_WAITI,
OPCODE_RSR_INTERRUPT,
OPCODE_WSR_INTSET,
OPCODE_WSR_INTCLEAR,
OPCODE_RSR_INTENABLE,
OPCODE_WSR_INTENABLE,
OPCODE_XSR_INTENABLE,
OPCODE_BREAK,
OPCODE_BREAK_N,
OPCODE_RSR_DEBUGCAUSE,
OPCODE_WSR_DEBUGCAUSE,
OPCODE_XSR_DEBUGCAUSE,
OPCODE_RSR_ICOUNT,
OPCODE_WSR_ICOUNT,
OPCODE_XSR_ICOUNT,
OPCODE_RSR_ICOUNTLEVEL,
OPCODE_WSR_ICOUNTLEVEL,
OPCODE_XSR_ICOUNTLEVEL,
OPCODE_RSR_DDR,
OPCODE_WSR_DDR,
OPCODE_XSR_DDR,
OPCODE_RFDO,
OPCODE_RFDD,
OPCODE_ANDB,
OPCODE_ANDBC,
OPCODE_ORB,
OPCODE_ORBC,
OPCODE_XORB,
OPCODE_ANY4,
OPCODE_ALL4,
OPCODE_ANY8,
OPCODE_ALL8,
OPCODE_BF,
OPCODE_BT,
OPCODE_MOVF,
OPCODE_MOVT,
OPCODE_RSR_BR,
OPCODE_WSR_BR,
OPCODE_XSR_BR,
OPCODE_RSR_CCOUNT,
OPCODE_WSR_CCOUNT,
OPCODE_XSR_CCOUNT,
OPCODE_RSR_CCOMPARE0,
OPCODE_WSR_CCOMPARE0,
OPCODE_XSR_CCOMPARE0,
OPCODE_RSR_CCOMPARE1,
OPCODE_WSR_CCOMPARE1,
OPCODE_XSR_CCOMPARE1,
OPCODE_IPF,
OPCODE_IHI,
OPCODE_III,
OPCODE_LICT,
OPCODE_LICW,
OPCODE_SICT,
OPCODE_SICW,
OPCODE_DHWB,
OPCODE_DHWBI,
OPCODE_DIWB,
OPCODE_DIWBI,
OPCODE_DHI,
OPCODE_DII,
OPCODE_DPFR,
OPCODE_DPFW,
OPCODE_DPFRO,
OPCODE_DPFWO,
OPCODE_SDCT,
OPCODE_LDCT,
OPCODE_WSR_PTEVADDR,
OPCODE_RSR_PTEVADDR,
OPCODE_XSR_PTEVADDR,
OPCODE_RSR_RASID,
OPCODE_WSR_RASID,
OPCODE_XSR_RASID,
OPCODE_RSR_ITLBCFG,
OPCODE_WSR_ITLBCFG,
OPCODE_XSR_ITLBCFG,
OPCODE_RSR_DTLBCFG,
OPCODE_WSR_DTLBCFG,
OPCODE_XSR_DTLBCFG,
OPCODE_IDTLB,
OPCODE_PDTLB,
OPCODE_RDTLB0,
OPCODE_RDTLB1,
OPCODE_WDTLB,
OPCODE_IITLB,
OPCODE_PITLB,
OPCODE_RITLB0,
OPCODE_RITLB1,
OPCODE_WITLB,
OPCODE_LDPTE,
OPCODE_HWWITLBA,
OPCODE_HWWDTLBA,
OPCODE_RSR_CPENABLE,
OPCODE_WSR_CPENABLE,
OPCODE_XSR_CPENABLE,
OPCODE_CLAMPS,
OPCODE_MIN,
OPCODE_MAX,
OPCODE_MINU,
OPCODE_MAXU,
OPCODE_NSA,
OPCODE_NSAU,
OPCODE_SEXT,
OPCODE_L32AI,
OPCODE_S32RI,
OPCODE_S32C1I,
OPCODE_RSR_SCOMPARE1,
OPCODE_WSR_SCOMPARE1,
OPCODE_XSR_SCOMPARE1,
OPCODE_RSR_ATOMCTL,
OPCODE_WSR_ATOMCTL,
OPCODE_XSR_ATOMCTL,
OPCODE_RER,
OPCODE_WER,
OPCODE_RUR_AE_OVF_SAR,
OPCODE_WUR_AE_OVF_SAR,
OPCODE_RUR_AE_BITHEAD,
OPCODE_WUR_AE_BITHEAD,
OPCODE_RUR_AE_TS_FTS_BU_BP,
OPCODE_WUR_AE_TS_FTS_BU_BP,
OPCODE_RUR_AE_SD_NO,
OPCODE_WUR_AE_SD_NO,
OPCODE_RUR_AE_OVERFLOW,
OPCODE_WUR_AE_OVERFLOW,
OPCODE_RUR_AE_SAR,
OPCODE_WUR_AE_SAR,
OPCODE_RUR_AE_BITPTR,
OPCODE_WUR_AE_BITPTR,
OPCODE_RUR_AE_BITSUSED,
OPCODE_WUR_AE_BITSUSED,
OPCODE_RUR_AE_TABLESIZE,
OPCODE_WUR_AE_TABLESIZE,
OPCODE_RUR_AE_FIRST_TS,
OPCODE_WUR_AE_FIRST_TS,
OPCODE_RUR_AE_NEXTOFFSET,
OPCODE_WUR_AE_NEXTOFFSET,
OPCODE_RUR_AE_SEARCHDONE,
OPCODE_WUR_AE_SEARCHDONE,
OPCODE_AE_LP16F_I,
OPCODE_AE_LP16F_IU,
OPCODE_AE_LP16F_X,
OPCODE_AE_LP16F_XU,
OPCODE_AE_LP24_I,
OPCODE_AE_LP24_IU,
OPCODE_AE_LP24_X,
OPCODE_AE_LP24_XU,
OPCODE_AE_LP24F_I,
OPCODE_AE_LP24F_IU,
OPCODE_AE_LP24F_X,
OPCODE_AE_LP24F_XU,
OPCODE_AE_LP16X2F_I,
OPCODE_AE_LP16X2F_IU,
OPCODE_AE_LP16X2F_X,
OPCODE_AE_LP16X2F_XU,
OPCODE_AE_LP24X2F_I,
OPCODE_AE_LP24X2F_IU,
OPCODE_AE_LP24X2F_X,
OPCODE_AE_LP24X2F_XU,
OPCODE_AE_LP24X2_I,
OPCODE_AE_LP24X2_IU,
OPCODE_AE_LP24X2_X,
OPCODE_AE_LP24X2_XU,
OPCODE_AE_SP16X2F_I,
OPCODE_AE_SP16X2F_IU,
OPCODE_AE_SP16X2F_X,
OPCODE_AE_SP16X2F_XU,
OPCODE_AE_SP24X2S_I,
OPCODE_AE_SP24X2S_IU,
OPCODE_AE_SP24X2S_X,
OPCODE_AE_SP24X2S_XU,
OPCODE_AE_SP24X2F_I,
OPCODE_AE_SP24X2F_IU,
OPCODE_AE_SP24X2F_X,
OPCODE_AE_SP24X2F_XU,
OPCODE_AE_SP16F_L_I,
OPCODE_AE_SP16F_L_IU,
OPCODE_AE_SP16F_L_X,
OPCODE_AE_SP16F_L_XU,
OPCODE_AE_SP24S_L_I,
OPCODE_AE_SP24S_L_IU,
OPCODE_AE_SP24S_L_X,
OPCODE_AE_SP24S_L_XU,
OPCODE_AE_SP24F_L_I,
OPCODE_AE_SP24F_L_IU,
OPCODE_AE_SP24F_L_X,
OPCODE_AE_SP24F_L_XU,
OPCODE_AE_LQ56_I,
OPCODE_AE_LQ56_IU,
OPCODE_AE_LQ56_X,
OPCODE_AE_LQ56_XU,
OPCODE_AE_LQ32F_I,
OPCODE_AE_LQ32F_IU,
OPCODE_AE_LQ32F_X,
OPCODE_AE_LQ32F_XU,
OPCODE_AE_SQ56S_I,
OPCODE_AE_SQ56S_IU,
OPCODE_AE_SQ56S_X,
OPCODE_AE_SQ56S_XU,
OPCODE_AE_SQ32F_I,
OPCODE_AE_SQ32F_IU,
OPCODE_AE_SQ32F_X,
OPCODE_AE_SQ32F_XU,
OPCODE_AE_ZEROP48,
OPCODE_AE_MOVP48,
OPCODE_AE_SELP24_LL,
OPCODE_AE_SELP24_LH,
OPCODE_AE_SELP24_HL,
OPCODE_AE_SELP24_HH,
OPCODE_AE_MOVTP24X2,
OPCODE_AE_MOVFP24X2,
OPCODE_AE_MOVTP48,
OPCODE_AE_MOVFP48,
OPCODE_AE_MOVPA24X2,
OPCODE_AE_TRUNCP24A32X2,
OPCODE_AE_CVTA32P24_L,
OPCODE_AE_CVTA32P24_H,
OPCODE_AE_CVTP24A16X2_LL,
OPCODE_AE_CVTP24A16X2_LH,
OPCODE_AE_CVTP24A16X2_HL,
OPCODE_AE_CVTP24A16X2_HH,
OPCODE_AE_TRUNCP24Q48X2,
OPCODE_AE_TRUNCP16,
OPCODE_AE_ROUNDSP24Q48SYM,
OPCODE_AE_ROUNDSP24Q48ASYM,
OPCODE_AE_ROUNDSP16Q48SYM,
OPCODE_AE_ROUNDSP16Q48ASYM,
OPCODE_AE_ROUNDSP16SYM,
OPCODE_AE_ROUNDSP16ASYM,
OPCODE_AE_ZEROQ56,
OPCODE_AE_MOVQ56,
OPCODE_AE_MOVTQ56,
OPCODE_AE_MOVFQ56,
OPCODE_AE_CVTQ48A32S,
OPCODE_AE_CVTQ48P24S_L,
OPCODE_AE_CVTQ48P24S_H,
OPCODE_AE_SATQ48S,
OPCODE_AE_TRUNCQ32,
OPCODE_AE_ROUNDSQ32SYM,
OPCODE_AE_ROUNDSQ32ASYM,
OPCODE_AE_TRUNCA32Q48,
OPCODE_AE_MOVAP24S_L,
OPCODE_AE_MOVAP24S_H,
OPCODE_AE_TRUNCA16P24S_L,
OPCODE_AE_TRUNCA16P24S_H,
OPCODE_AE_ADDP24,
OPCODE_AE_SUBP24,
OPCODE_AE_NEGP24,
OPCODE_AE_ABSP24,
OPCODE_AE_MAXP24S,
OPCODE_AE_MINP24S,
OPCODE_AE_MAXBP24S,
OPCODE_AE_MINBP24S,
OPCODE_AE_ADDSP24S,
OPCODE_AE_SUBSP24S,
OPCODE_AE_NEGSP24S,
OPCODE_AE_ABSSP24S,
OPCODE_AE_ANDP48,
OPCODE_AE_NANDP48,
OPCODE_AE_ORP48,
OPCODE_AE_XORP48,
OPCODE_AE_LTP24S,
OPCODE_AE_LEP24S,
OPCODE_AE_EQP24,
OPCODE_AE_ADDQ56,
OPCODE_AE_SUBQ56,
OPCODE_AE_NEGQ56,
OPCODE_AE_ABSQ56,
OPCODE_AE_MAXQ56S,
OPCODE_AE_MINQ56S,
OPCODE_AE_MAXBQ56S,
OPCODE_AE_MINBQ56S,
OPCODE_AE_ADDSQ56S,
OPCODE_AE_SUBSQ56S,
OPCODE_AE_NEGSQ56S,
OPCODE_AE_ABSSQ56S,
OPCODE_AE_ANDQ56,
OPCODE_AE_NANDQ56,
OPCODE_AE_ORQ56,
OPCODE_AE_XORQ56,
OPCODE_AE_SLLIP24,
OPCODE_AE_SRLIP24,
OPCODE_AE_SRAIP24,
OPCODE_AE_SLLSP24,
OPCODE_AE_SRLSP24,
OPCODE_AE_SRASP24,
OPCODE_AE_SLLISP24S,
OPCODE_AE_SLLSSP24S,
OPCODE_AE_SLLIQ56,
OPCODE_AE_SRLIQ56,
OPCODE_AE_SRAIQ56,
OPCODE_AE_SLLSQ56,
OPCODE_AE_SRLSQ56,
OPCODE_AE_SRASQ56,
OPCODE_AE_SLLAQ56,
OPCODE_AE_SRLAQ56,
OPCODE_AE_SRAAQ56,
OPCODE_AE_SLLISQ56S,
OPCODE_AE_SLLSSQ56S,
OPCODE_AE_SLLASQ56S,
OPCODE_AE_LTQ56S,
OPCODE_AE_LEQ56S,
OPCODE_AE_EQQ56,
OPCODE_AE_NSAQ56S,
OPCODE_AE_MULFS32P16S_LL,
OPCODE_AE_MULFP24S_LL,
OPCODE_AE_MULP24S_LL,
OPCODE_AE_MULFS32P16S_LH,
OPCODE_AE_MULFP24S_LH,
OPCODE_AE_MULP24S_LH,
OPCODE_AE_MULFS32P16S_HL,
OPCODE_AE_MULFP24S_HL,
OPCODE_AE_MULP24S_HL,
OPCODE_AE_MULFS32P16S_HH,
OPCODE_AE_MULFP24S_HH,
OPCODE_AE_MULP24S_HH,
OPCODE_AE_MULAFS32P16S_LL,
OPCODE_AE_MULAFP24S_LL,
OPCODE_AE_MULAP24S_LL,
OPCODE_AE_MULAFS32P16S_LH,
OPCODE_AE_MULAFP24S_LH,
OPCODE_AE_MULAP24S_LH,
OPCODE_AE_MULAFS32P16S_HL,
OPCODE_AE_MULAFP24S_HL,
OPCODE_AE_MULAP24S_HL,
OPCODE_AE_MULAFS32P16S_HH,
OPCODE_AE_MULAFP24S_HH,
OPCODE_AE_MULAP24S_HH,
OPCODE_AE_MULSFS32P16S_LL,
OPCODE_AE_MULSFP24S_LL,
OPCODE_AE_MULSP24S_LL,
OPCODE_AE_MULSFS32P16S_LH,
OPCODE_AE_MULSFP24S_LH,
OPCODE_AE_MULSP24S_LH,
OPCODE_AE_MULSFS32P16S_HL,
OPCODE_AE_MULSFP24S_HL,
OPCODE_AE_MULSP24S_HL,
OPCODE_AE_MULSFS32P16S_HH,
OPCODE_AE_MULSFP24S_HH,
OPCODE_AE_MULSP24S_HH,
OPCODE_AE_MULAFS56P24S_LL,
OPCODE_AE_MULAS56P24S_LL,
OPCODE_AE_MULAFS56P24S_LH,
OPCODE_AE_MULAS56P24S_LH,
OPCODE_AE_MULAFS56P24S_HL,
OPCODE_AE_MULAS56P24S_HL,
OPCODE_AE_MULAFS56P24S_HH,
OPCODE_AE_MULAS56P24S_HH,
OPCODE_AE_MULSFS56P24S_LL,
OPCODE_AE_MULSS56P24S_LL,
OPCODE_AE_MULSFS56P24S_LH,
OPCODE_AE_MULSS56P24S_LH,
OPCODE_AE_MULSFS56P24S_HL,
OPCODE_AE_MULSS56P24S_HL,
OPCODE_AE_MULSFS56P24S_HH,
OPCODE_AE_MULSS56P24S_HH,
OPCODE_AE_MULFQ32SP16S_L,
OPCODE_AE_MULFQ32SP16S_H,
OPCODE_AE_MULFQ32SP16U_L,
OPCODE_AE_MULFQ32SP16U_H,
OPCODE_AE_MULQ32SP16S_L,
OPCODE_AE_MULQ32SP16S_H,
OPCODE_AE_MULQ32SP16U_L,
OPCODE_AE_MULQ32SP16U_H,
OPCODE_AE_MULAFQ32SP16S_L,
OPCODE_AE_MULAFQ32SP16S_H,
OPCODE_AE_MULAFQ32SP16U_L,
OPCODE_AE_MULAFQ32SP16U_H,
OPCODE_AE_MULAQ32SP16S_L,
OPCODE_AE_MULAQ32SP16S_H,
OPCODE_AE_MULAQ32SP16U_L,
OPCODE_AE_MULAQ32SP16U_H,
OPCODE_AE_MULSFQ32SP16S_L,
OPCODE_AE_MULSFQ32SP16S_H,
OPCODE_AE_MULSFQ32SP16U_L,
OPCODE_AE_MULSFQ32SP16U_H,
OPCODE_AE_MULSQ32SP16S_L,
OPCODE_AE_MULSQ32SP16S_H,
OPCODE_AE_MULSQ32SP16U_L,
OPCODE_AE_MULSQ32SP16U_H,
OPCODE_AE_MULZAAQ32SP16S_LL,
OPCODE_AE_MULZAAFQ32SP16S_LL,
OPCODE_AE_MULZAAQ32SP16U_LL,
OPCODE_AE_MULZAAFQ32SP16U_LL,
OPCODE_AE_MULZAAQ32SP16S_HH,
OPCODE_AE_MULZAAFQ32SP16S_HH,
OPCODE_AE_MULZAAQ32SP16U_HH,
OPCODE_AE_MULZAAFQ32SP16U_HH,
OPCODE_AE_MULZAAQ32SP16S_LH,
OPCODE_AE_MULZAAFQ32SP16S_LH,
OPCODE_AE_MULZAAQ32SP16U_LH,
OPCODE_AE_MULZAAFQ32SP16U_LH,
OPCODE_AE_MULZASQ32SP16S_LL,
OPCODE_AE_MULZASFQ32SP16S_LL,
OPCODE_AE_MULZASQ32SP16U_LL,
OPCODE_AE_MULZASFQ32SP16U_LL,
OPCODE_AE_MULZASQ32SP16S_HH,
OPCODE_AE_MULZASFQ32SP16S_HH,
OPCODE_AE_MULZASQ32SP16U_HH,
OPCODE_AE_MULZASFQ32SP16U_HH,
OPCODE_AE_MULZASQ32SP16S_LH,
OPCODE_AE_MULZASFQ32SP16S_LH,
OPCODE_AE_MULZASQ32SP16U_LH,
OPCODE_AE_MULZASFQ32SP16U_LH,
OPCODE_AE_MULZSAQ32SP16S_LL,
OPCODE_AE_MULZSAFQ32SP16S_LL,
OPCODE_AE_MULZSAQ32SP16U_LL,
OPCODE_AE_MULZSAFQ32SP16U_LL,
OPCODE_AE_MULZSAQ32SP16S_HH,
OPCODE_AE_MULZSAFQ32SP16S_HH,
OPCODE_AE_MULZSAQ32SP16U_HH,
OPCODE_AE_MULZSAFQ32SP16U_HH,
OPCODE_AE_MULZSAQ32SP16S_LH,
OPCODE_AE_MULZSAFQ32SP16S_LH,
OPCODE_AE_MULZSAQ32SP16U_LH,
OPCODE_AE_MULZSAFQ32SP16U_LH,
OPCODE_AE_MULZSSQ32SP16S_LL,
OPCODE_AE_MULZSSFQ32SP16S_LL,
OPCODE_AE_MULZSSQ32SP16U_LL,
OPCODE_AE_MULZSSFQ32SP16U_LL,
OPCODE_AE_MULZSSQ32SP16S_HH,
OPCODE_AE_MULZSSFQ32SP16S_HH,
OPCODE_AE_MULZSSQ32SP16U_HH,
OPCODE_AE_MULZSSFQ32SP16U_HH,
OPCODE_AE_MULZSSQ32SP16S_LH,
OPCODE_AE_MULZSSFQ32SP16S_LH,
OPCODE_AE_MULZSSQ32SP16U_LH,
OPCODE_AE_MULZSSFQ32SP16U_LH,
OPCODE_AE_MULZAAFP24S_HH_LL,
OPCODE_AE_MULZAAP24S_HH_LL,
OPCODE_AE_MULZAAFP24S_HL_LH,
OPCODE_AE_MULZAAP24S_HL_LH,
OPCODE_AE_MULZASFP24S_HH_LL,
OPCODE_AE_MULZASP24S_HH_LL,
OPCODE_AE_MULZASFP24S_HL_LH,
OPCODE_AE_MULZASP24S_HL_LH,
OPCODE_AE_MULZSAFP24S_HH_LL,
OPCODE_AE_MULZSAP24S_HH_LL,
OPCODE_AE_MULZSAFP24S_HL_LH,
OPCODE_AE_MULZSAP24S_HL_LH,
OPCODE_AE_MULZSSFP24S_HH_LL,
OPCODE_AE_MULZSSP24S_HH_LL,
OPCODE_AE_MULZSSFP24S_HL_LH,
OPCODE_AE_MULZSSP24S_HL_LH,
OPCODE_AE_MULAAFP24S_HH_LL,
OPCODE_AE_MULAAP24S_HH_LL,
OPCODE_AE_MULAAFP24S_HL_LH,
OPCODE_AE_MULAAP24S_HL_LH,
OPCODE_AE_MULASFP24S_HH_LL,
OPCODE_AE_MULASP24S_HH_LL,
OPCODE_AE_MULASFP24S_HL_LH,
OPCODE_AE_MULASP24S_HL_LH,
OPCODE_AE_MULSAFP24S_HH_LL,
OPCODE_AE_MULSAP24S_HH_LL,
OPCODE_AE_MULSAFP24S_HL_LH,
OPCODE_AE_MULSAP24S_HL_LH,
OPCODE_AE_MULSSFP24S_HH_LL,
OPCODE_AE_MULSSP24S_HH_LL,
OPCODE_AE_MULSSFP24S_HL_LH,
OPCODE_AE_MULSSP24S_HL_LH,
OPCODE_AE_SHA32,
OPCODE_AE_VLDL32T,
OPCODE_AE_VLDL16T,
OPCODE_AE_VLDL16C,
OPCODE_AE_VLDSHT,
OPCODE_AE_LB,
OPCODE_AE_LBI,
OPCODE_AE_LBK,
OPCODE_AE_LBKI,
OPCODE_AE_DB,
OPCODE_AE_DBI,
OPCODE_AE_VLEL32T,
OPCODE_AE_VLEL16T,
OPCODE_AE_SB,
OPCODE_AE_SBI,
OPCODE_AE_VLES16C,
OPCODE_AE_SBF
};
/* Slot-specific opcode decode functions. */
static int
Slot_inst_decode (const xtensa_insnbuf insn)
{
switch (Field_op0_Slot_inst_get (insn))
{
case 0:
switch (Field_op1_Slot_inst_get (insn))
{
case 0:
switch (Field_op2_Slot_inst_get (insn))
{
case 0:
switch (Field_r_Slot_inst_get (insn))
{
case 0:
switch (Field_m_Slot_inst_get (insn))
{
case 0:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_n_Slot_inst_get (insn) == 0)
return OPCODE_ILL;
break;
case 2:
switch (Field_n_Slot_inst_get (insn))
{
case 0:
return OPCODE_RET;
case 1:
return OPCODE_RETW;
case 2:
return OPCODE_JX;
}
break;
case 3:
switch (Field_n_Slot_inst_get (insn))
{
case 0:
return OPCODE_CALLX0;
case 1:
return OPCODE_CALLX4;
case 2:
return OPCODE_CALLX8;
case 3:
return OPCODE_CALLX12;
}
break;
}
break;
case 1:
return OPCODE_MOVSP;
case 2:
if (Field_s_Slot_inst_get (insn) == 0)
{
switch (Field_t_Slot_inst_get (insn))
{
case 0:
return OPCODE_ISYNC;
case 1:
return OPCODE_RSYNC;
case 2:
return OPCODE_ESYNC;
case 3:
return OPCODE_DSYNC;
case 8:
return OPCODE_EXCW;
case 12:
return OPCODE_MEMW;
case 13:
return OPCODE_EXTW;
case 15:
return OPCODE_NOP;
}
}
break;
case 3:
switch (Field_t_Slot_inst_get (insn))
{
case 0:
switch (Field_s_Slot_inst_get (insn))
{
case 0:
return OPCODE_RFE;
case 2:
return OPCODE_RFDE;
case 4:
return OPCODE_RFWO;
case 5:
return OPCODE_RFWU;
}
break;
case 1:
return OPCODE_RFI;
}
break;
case 4:
return OPCODE_BREAK;
case 5:
switch (Field_s_Slot_inst_get (insn))
{
case 0:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SYSCALL;
break;
case 1:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SIMCALL;
break;
}
break;
case 6:
return OPCODE_RSIL;
case 7:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_WAITI;
break;
case 8:
return OPCODE_ANY4;
case 9:
return OPCODE_ALL4;
case 10:
return OPCODE_ANY8;
case 11:
return OPCODE_ALL8;
}
break;
case 1:
return OPCODE_AND;
case 2:
return OPCODE_OR;
case 3:
return OPCODE_XOR;
case 4:
switch (Field_r_Slot_inst_get (insn))
{
case 0:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SSR;
break;
case 1:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SSL;
break;
case 2:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SSA8L;
break;
case 3:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SSA8B;
break;
case 4:
if (Field_thi3_Slot_inst_get (insn) == 0)
return OPCODE_SSAI;
break;
case 6:
return OPCODE_RER;
case 7:
return OPCODE_WER;
case 8:
if (Field_s_Slot_inst_get (insn) == 0)
return OPCODE_ROTW;
break;
case 14:
return OPCODE_NSA;
case 15:
return OPCODE_NSAU;
}
break;
case 5:
switch (Field_r_Slot_inst_get (insn))
{
case 1:
return OPCODE_HWWITLBA;
case 3:
return OPCODE_RITLB0;
case 4:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_IITLB;
break;
case 5:
return OPCODE_PITLB;
case 6:
return OPCODE_WITLB;
case 7:
return OPCODE_RITLB1;
case 9:
return OPCODE_HWWDTLBA;
case 11:
return OPCODE_RDTLB0;
case 12:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_IDTLB;
break;
case 13:
return OPCODE_PDTLB;
case 14:
return OPCODE_WDTLB;
case 15:
return OPCODE_RDTLB1;
}
break;
case 6:
switch (Field_s_Slot_inst_get (insn))
{
case 0:
return OPCODE_NEG;
case 1:
return OPCODE_ABS;
}
break;
case 8:
return OPCODE_ADD;
case 9:
return OPCODE_ADDX2;
case 10:
return OPCODE_ADDX4;
case 11:
return OPCODE_ADDX8;
case 12:
return OPCODE_SUB;
case 13:
return OPCODE_SUBX2;
case 14:
return OPCODE_SUBX4;
case 15:
return OPCODE_SUBX8;
}
break;
case 1:
switch (Field_op2_Slot_inst_get (insn))
{
case 0:
case 1:
return OPCODE_SLLI;
case 2:
case 3:
return OPCODE_SRAI;
case 4:
return OPCODE_SRLI;
case 6:
switch (Field_sr_Slot_inst_get (insn))
{
case 0:
return OPCODE_XSR_LBEG;
case 1:
return OPCODE_XSR_LEND;
case 2:
return OPCODE_XSR_LCOUNT;
case 3:
return OPCODE_XSR_SAR;
case 4:
return OPCODE_XSR_BR;
case 5:
return OPCODE_XSR_LITBASE;
case 12:
return OPCODE_XSR_SCOMPARE1;
case 72:
return OPCODE_XSR_WINDOWBASE;
case 73:
return OPCODE_XSR_WINDOWSTART;
case 83:
return OPCODE_XSR_PTEVADDR;
case 90:
return OPCODE_XSR_RASID;
case 91:
return OPCODE_XSR_ITLBCFG;
case 92:
return OPCODE_XSR_DTLBCFG;
case 99:
return OPCODE_XSR_ATOMCTL;
case 104:
return OPCODE_XSR_DDR;
case 177:
return OPCODE_XSR_EPC1;
case 178:
return OPCODE_XSR_EPC2;
case 192:
return OPCODE_XSR_DEPC;
case 194:
return OPCODE_XSR_EPS2;
case 209:
return OPCODE_XSR_EXCSAVE1;
case 210:
return OPCODE_XSR_EXCSAVE2;
case 224:
return OPCODE_XSR_CPENABLE;
case 228:
return OPCODE_XSR_INTENABLE;
case 230:
return OPCODE_XSR_PS;
case 231:
return OPCODE_XSR_VECBASE;
case 232:
return OPCODE_XSR_EXCCAUSE;
case 233:
return OPCODE_XSR_DEBUGCAUSE;
case 234:
return OPCODE_XSR_CCOUNT;
case 236:
return OPCODE_XSR_ICOUNT;
case 237:
return OPCODE_XSR_ICOUNTLEVEL;
case 238:
return OPCODE_XSR_EXCVADDR;
case 240:
return OPCODE_XSR_CCOMPARE0;
case 241:
return OPCODE_XSR_CCOMPARE1;
case 244:
return OPCODE_XSR_MISC0;
case 245:
return OPCODE_XSR_MISC1;
}
break;
case 8:
return OPCODE_SRC;
case 9:
if (Field_s_Slot_inst_get (insn) == 0)
return OPCODE_SRL;
break;
case 10:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_SLL;
break;
case 11:
if (Field_s_Slot_inst_get (insn) == 0)
return OPCODE_SRA;
break;
case 12:
return OPCODE_MUL16U;
case 13:
return OPCODE_MUL16S;
case 15:
switch (Field_r_Slot_inst_get (insn))
{
case 0:
return OPCODE_LICT;
case 1:
return OPCODE_SICT;
case 2:
return OPCODE_LICW;
case 3:
return OPCODE_SICW;
case 8:
return OPCODE_LDCT;
case 9:
return OPCODE_SDCT;
case 14:
if (Field_t_Slot_inst_get (insn) == 0)
return OPCODE_RFDO;
if (Field_t_Slot_inst_get (insn) == 1)
return OPCODE_RFDD;
break;
case 15:
return OPCODE_LDPTE;
}
break;
}
break;
case 2:
switch (Field_op2_Slot_inst_get (insn))
{
case 0:
return OPCODE_ANDB;
case 1:
return OPCODE_ANDBC;
case 2:
return OPCODE_ORB;
case 3:
return OPCODE_ORBC;
case 4:
return OPCODE_XORB;
case 8:
return OPCODE_MULL;
}
break;
case 3:
switch (Field_op2_Slot_inst_get (insn))
{
case 0:
switch (Field_sr_Slot_inst_get (insn))
{
case 0:
return OPCODE_RSR_LBEG;
case 1:
return OPCODE_RSR_LEND;
case 2:
return OPCODE_RSR_LCOUNT;
case 3:
return OPCODE_RSR_SAR;
case 4:
return OPCODE_RSR_BR;
case 5:
return OPCODE_RSR_LITBASE;
case 12:
return OPCODE_RSR_SCOMPARE1;
case 72:
return OPCODE_RSR_WINDOWBASE;
case 73:
return OPCODE_RSR_WINDOWSTART;
case 83:
return OPCODE_RSR_PTEVADDR;
case 90:
return OPCODE_RSR_RASID;
case 91:
return OPCODE_RSR_ITLBCFG;
case 92:
return OPCODE_RSR_DTLBCFG;
case 99:
return OPCODE_RSR_ATOMCTL;
case 104:
return OPCODE_RSR_DDR;
case 176:
return OPCODE_RSR_176;
case 177:
return OPCODE_RSR_EPC1;
case 178:
return OPCODE_RSR_EPC2;
case 192:
return OPCODE_RSR_DEPC;
case 194:
return OPCODE_RSR_EPS2;
case 208:
return OPCODE_RSR_208;
case 209:
return OPCODE_RSR_EXCSAVE1;
case 210:
return OPCODE_RSR_EXCSAVE2;
case 224:
return OPCODE_RSR_CPENABLE;
case 226:
return OPCODE_RSR_INTERRUPT;
case 228:
return OPCODE_RSR_INTENABLE;
case 230:
return OPCODE_RSR_PS;
case 231:
return OPCODE_RSR_VECBASE;
case 232:
return OPCODE_RSR_EXCCAUSE;
case 233:
return OPCODE_RSR_DEBUGCAUSE;
case 234:
return OPCODE_RSR_CCOUNT;
case 235:
return OPCODE_RSR_PRID;
case 236:
return OPCODE_RSR_ICOUNT;
case 237:
return OPCODE_RSR_ICOUNTLEVEL;
case 238:
return OPCODE_RSR_EXCVADDR;
case 240:
return OPCODE_RSR_CCOMPARE0;
case 241:
return OPCODE_RSR_CCOMPARE1;
case 244:
return OPCODE_RSR_MISC0;
case 245:
return OPCODE_RSR_MISC1;
}
break;
case 1:
switch (Field_sr_Slot_inst_get (insn))
{
case 0:
return OPCODE_WSR_LBEG;
case 1:
return OPCODE_WSR_LEND;
case 2:
return OPCODE_WSR_LCOUNT;
case 3:
return OPCODE_WSR_SAR;
case 4:
return OPCODE_WSR_BR;
case 5:
return OPCODE_WSR_LITBASE;
case 12:
return OPCODE_WSR_SCOMPARE1;
case 72:
return OPCODE_WSR_WINDOWBASE;
case 73:
return OPCODE_WSR_WINDOWSTART;
case 83:
return OPCODE_WSR_PTEVADDR;
case 90:
return OPCODE_WSR_RASID;
case 91:
return OPCODE_WSR_ITLBCFG;
case 92:
return OPCODE_WSR_DTLBCFG;
case 99:
return OPCODE_WSR_ATOMCTL;
case 104:
return OPCODE_WSR_DDR;
case 176:
return OPCODE_WSR_176;
case 177:
return OPCODE_WSR_EPC1;
case 178:
return OPCODE_WSR_EPC2;
case 192:
return OPCODE_WSR_DEPC;
case 194:
return OPCODE_WSR_EPS2;
case 209:
return OPCODE_WSR_EXCSAVE1;
case 210:
return OPCODE_WSR_EXCSAVE2;
case 224:
return OPCODE_WSR_CPENABLE;
case 226:
return OPCODE_WSR_INTSET;
case 227:
return OPCODE_WSR_INTCLEAR;
case 228:
return OPCODE_WSR_INTENABLE;
case 230:
return OPCODE_WSR_PS;
case 231:
return OPCODE_WSR_VECBASE;
case 232:
return OPCODE_WSR_EXCCAUSE;
case 233:
return OPCODE_WSR_DEBUGCAUSE;
case 234:
return OPCODE_WSR_CCOUNT;
case 236:
return OPCODE_WSR_ICOUNT;
case 237:
return OPCODE_WSR_ICOUNTLEVEL;
case 238:
return OPCODE_WSR_EXCVADDR;
case 240:
return OPCODE_WSR_CCOMPARE0;
case 241:
return OPCODE_WSR_CCOMPARE1;
case 244:
return OPCODE_WSR_MISC0;
case 245:
return OPCODE_WSR_MISC1;
}
break;
case 2:
return OPCODE_SEXT;
case 3:
return OPCODE_CLAMPS;
case 4:
return OPCODE_MIN;
case 5:
return OPCODE_MAX;
case 6:
return OPCODE_MINU;
case 7:
return OPCODE_MAXU;
case 8:
return OPCODE_MOVEQZ;
case 9:
return OPCODE_MOVNEZ;
case 10:
return OPCODE_MOVLTZ;
case 11:
return OPCODE_MOVGEZ;
case 12:
return OPCODE_MOVF;
case 13:
return OPCODE_MOVT;
case 14:
switch (Field_st_Slot_inst_get (insn))
{
case 231:
return OPCODE_RUR_THREADPTR;
case 240:
return OPCODE_RUR_AE_OVF_SAR;
case 241:
return OPCODE_RUR_AE_BITHEAD;
case 242:
return OPCODE_RUR_AE_TS_FTS_BU_BP;
case 243:
return OPCODE_RUR_AE_SD_NO;
}
break;
case 15:
switch (Field_sr_Slot_inst_get (insn))
{
case 231:
return OPCODE_WUR_THREADPTR;
case 240:
return OPCODE_WUR_AE_OVF_SAR;
case 241:
return OPCODE_WUR_AE_BITHEAD;
case 242:
return OPCODE_WUR_AE_TS_FTS_BU_BP;
case 243:
return OPCODE_WUR_AE_SD_NO;
}
break;
}
break;
case 4:
case 5:
return OPCODE_EXTUI;
case 9:
switch (Field_op2_Slot_inst_get (insn))
{
case 0:
return OPCODE_L32E;
case 4:
return OPCODE_S32E;
}
break;
}
break;
case 1:
return OPCODE_L32R;
case 2:
switch (Field_r_Slot_inst_get (insn))
{
case 0:
return OPCODE_L8UI;
case 1:
return OPCODE_L16UI;
case 2:
return OPCODE_L32I;
case 4:
return OPCODE_S8I;
case 5:
return OPCODE_S16I;
case 6:
return OPCODE_S32I;
case 7:
switch (Field_t_Slot_inst_get (insn))
{
case 0:
return OPCODE_DPFR;
case 1:
return OPCODE_DPFW;
case 2:
return OPCODE_DPFRO;
case 3:
return OPCODE_DPFWO;
case 4:
return OPCODE_DHWB;
case 5:
return OPCODE_DHWBI;
case 6:
return OPCODE_DHI;
case 7:
return OPCODE_DII;
case 8:
switch (Field_op1_Slot_inst_get (insn))
{
case 4:
return OPCODE_DIWB;
case 5:
return OPCODE_DIWBI;
}
break;
case 12:
return OPCODE_IPF;
case 14:
return OPCODE_IHI;
case 15:
return OPCODE_III;
}
break;
case 9:
return OPCODE_L16SI;
case 10:
return OPCODE_MOVI;
case 11:
return OPCODE_L32AI;
case 12:
return OPCODE_ADDI;
case 13:
return OPCODE_ADDMI;
case 14:
return OPCODE_S32C1I;
case 15:
return OPCODE_S32RI;
}
break;
case 4:
switch (Field_ae_r10_Slot_inst_get (insn))
{
case 0:
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ56_I;
if (Field_op1_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ56_X;
break;
case 1:
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ32F_I;
if (Field_op1_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ32F_X;
break;
case 2:
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ56_IU;
if (Field_op1_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ56_XU;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_t_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_CVTQ48A32S;
break;
case 3:
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ32F_IU;
if (Field_op1_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LQ32F_XU;
break;
}
switch (Field_ae_r3_Slot_inst_get (insn))
{
case 0:
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16F_I;
if (Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16F_IU;
if (Field_op1_Slot_inst_get (insn) == 12 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16F_X;
if (Field_op1_Slot_inst_get (insn) == 15 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16F_XU;
if (Field_op1_Slot_inst_get (insn) == 6 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24F_I;
if (Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24F_IU;
if (Field_op1_Slot_inst_get (insn) == 13 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24F_X;
if (Field_op1_Slot_inst_get (insn) == 0 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_LP24F_XU;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24X2F_I;
if (Field_op1_Slot_inst_get (insn) == 11 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24X2F_IU;
if (Field_op1_Slot_inst_get (insn) == 14 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24X2F_X;
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_LP24X2F_XU;
if (Field_op1_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16X2F_I;
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16X2F_IU;
if (Field_op1_Slot_inst_get (insn) == 8 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16X2F_X;
if (Field_op1_Slot_inst_get (insn) == 11 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16X2F_XU;
if (Field_op1_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2F_I;
if (Field_op1_Slot_inst_get (insn) == 6 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2F_IU;
if (Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2F_X;
if (Field_op1_Slot_inst_get (insn) == 12 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2F_XU;
if (Field_op1_Slot_inst_get (insn) == 4 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24S_L_I;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24S_L_IU;
if (Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24S_L_X;
if (Field_op1_Slot_inst_get (insn) == 13 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24S_L_XU;
if (Field_ae_s3_Slot_inst_get (insn) == 0 &&
Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_MOVP48;
if (Field_op1_Slot_inst_get (insn) == 0 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_MOVPA24X2;
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 11 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_CVTA32P24_L;
if (Field_op1_Slot_inst_get (insn) == 14 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_CVTP24A16X2_LL;
if (Field_op1_Slot_inst_get (insn) == 15 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_CVTP24A16X2_HL;
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 7 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_MOVAP24S_L;
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 8 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_TRUNCA16P24S_L;
break;
case 1:
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24_I;
if (Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24_IU;
if (Field_op1_Slot_inst_get (insn) == 12 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24_X;
if (Field_op1_Slot_inst_get (insn) == 15 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24_XU;
if (Field_op1_Slot_inst_get (insn) == 6 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16X2F_I;
if (Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16X2F_IU;
if (Field_op1_Slot_inst_get (insn) == 13 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP16X2F_X;
if (Field_op1_Slot_inst_get (insn) == 0 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_LP16X2F_XU;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24X2_I;
if (Field_op1_Slot_inst_get (insn) == 11 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24X2_IU;
if (Field_op1_Slot_inst_get (insn) == 14 &&
Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LP24X2_X;
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_LP24X2_XU;
if (Field_op1_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2S_I;
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2S_IU;
if (Field_op1_Slot_inst_get (insn) == 8 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2S_X;
if (Field_op1_Slot_inst_get (insn) == 11 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24X2S_XU;
if (Field_op1_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16F_L_I;
if (Field_op1_Slot_inst_get (insn) == 6 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16F_L_IU;
if (Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16F_L_X;
if (Field_op1_Slot_inst_get (insn) == 12 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP16F_L_XU;
if (Field_op1_Slot_inst_get (insn) == 4 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24F_L_I;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24F_L_IU;
if (Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24F_L_X;
if (Field_op1_Slot_inst_get (insn) == 13 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_SP24F_L_XU;
if (Field_op1_Slot_inst_get (insn) == 0 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_TRUNCP24A32X2;
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 11 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_CVTA32P24_H;
if (Field_op1_Slot_inst_get (insn) == 14 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_CVTP24A16X2_LH;
if (Field_op1_Slot_inst_get (insn) == 15 &&
Field_op2_Slot_inst_get (insn) == 11)
return OPCODE_AE_CVTP24A16X2_HH;
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 7 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_MOVAP24S_H;
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 8 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_TRUNCA16P24S_H;
break;
}
switch (Field_ae_r32_Slot_inst_get (insn))
{
case 0:
if (Field_op1_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ56S_I;
if (Field_op1_Slot_inst_get (insn) == 4 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ56S_X;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_TRUNCA32Q48;
break;
case 1:
if (Field_op1_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ32F_I;
if (Field_op1_Slot_inst_get (insn) == 4 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ32F_X;
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_NSAQ56S;
break;
case 2:
if (Field_op1_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ56S_IU;
if (Field_op1_Slot_inst_get (insn) == 4 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ56S_XU;
break;
case 3:
if (Field_op1_Slot_inst_get (insn) == 3 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ32F_IU;
if (Field_op1_Slot_inst_get (insn) == 4 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SQ32F_XU;
break;
}
switch (Field_ae_s_non_samt_Slot_inst_get (insn))
{
case 0:
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SLLIQ56;
break;
case 1:
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SRLIQ56;
break;
case 2:
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SRAIQ56;
break;
case 3:
if (Field_op1_Slot_inst_get (insn) == 5 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SLLISQ56S;
break;
}
switch (Field_op1_Slot_inst_get (insn))
{
case 0:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_SHA32;
if (Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_VLDL32T;
break;
case 1:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_SLLAQ56;
if (Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_VLDL16T;
break;
case 2:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_SRLAQ56;
if (Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_LBK;
break;
case 3:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_SRAAQ56;
if (Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_VLEL32T;
break;
case 4:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_SLLASQ56S;
if (Field_op2_Slot_inst_get (insn) == 10)
return OPCODE_AE_VLEL16T;
break;
case 5:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_MOVTQ56;
break;
case 6:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_MOVFQ56;
break;
}
switch (Field_r_Slot_inst_get (insn))
{
case 0:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_OVERFLOW;
if (Field_op2_Slot_inst_get (insn) == 15)
return OPCODE_AE_SBI;
break;
case 1:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_SAR;
if (Field_op1_Slot_inst_get (insn) == 0 &&
Field_op2_Slot_inst_get (insn) == 15)
return OPCODE_AE_DB;
if (Field_op1_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 15)
return OPCODE_AE_SB;
break;
case 2:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_BITPTR;
break;
case 3:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_BITSUSED;
break;
case 4:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_TABLESIZE;
break;
case 5:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_FIRST_TS;
break;
case 6:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_NEXTOFFSET;
break;
case 7:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_WUR_AE_SEARCHDONE;
break;
case 8:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 10 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_VLDSHT;
break;
case 12:
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_VLES16C;
break;
case 13:
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_SBF;
break;
case 14:
if (Field_op1_Slot_inst_get (insn) == 7 &&
Field_t_Slot_inst_get (insn) == 1 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_VLDL16C;
break;
}
switch (Field_s_Slot_inst_get (insn))
{
case 0:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SLLSQ56;
if (Field_op1_Slot_inst_get (insn) == 6 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_LB;
break;
case 1:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SRLSQ56;
break;
case 2:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SRASQ56;
break;
case 3:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_SLLSSQ56S;
break;
case 4:
if (Field_t_Slot_inst_get (insn) == 1 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_AE_MOVQ56;
break;
case 8:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_OVERFLOW;
break;
case 9:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_SAR;
break;
case 10:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_BITPTR;
break;
case 11:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_BITSUSED;
break;
case 12:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_TABLESIZE;
break;
case 13:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_FIRST_TS;
break;
case 14:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_NEXTOFFSET;
break;
case 15:
if (Field_t_Slot_inst_get (insn) == 0 &&
Field_op1_Slot_inst_get (insn) == 9 &&
Field_op2_Slot_inst_get (insn) == 12)
return OPCODE_RUR_AE_SEARCHDONE;
break;
}
switch (Field_t_Slot_inst_get (insn))
{
case 0:
if (Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_LBKI;
if (Field_r_Slot_inst_get (insn) == 2 &&
Field_op2_Slot_inst_get (insn) == 15)
return OPCODE_AE_DBI;
break;
case 2:
if (Field_s_Slot_inst_get (insn) == 0 &&
Field_op2_Slot_inst_get (insn) == 14)
return OPCODE_AE_LBI;
break;
}
break;
case 5:
switch (Field_n_Slot_inst_get (insn))
{
case 0:
return OPCODE_CALL0;
case 1:
return OPCODE_CALL4;
case 2:
return OPCODE_CALL8;
case 3:
return OPCODE_CALL12;
}
break;
case 6:
switch (Field_n_Slot_inst_get (insn))
{
case 0:
return OPCODE_J;
case 1:
switch (Field_m_Slot_inst_get (insn))
{
case 0:
return OPCODE_BEQZ;
case 1:
return OPCODE_BNEZ;
case 2:
return OPCODE_BLTZ;
case 3:
return OPCODE_BGEZ;
}
break;
case 2:
switch (Field_m_Slot_inst_get (insn))
{
case 0:
return OPCODE_BEQI;
case 1:
return OPCODE_BNEI;
case 2:
return OPCODE_BLTI;
case 3:
return OPCODE_BGEI;
}
break;
case 3:
switch (Field_m_Slot_inst_get (insn))
{
case 0:
return OPCODE_ENTRY;
case 1:
switch (Field_r_Slot_inst_get (insn))
{
case 0:
return OPCODE_BF;
case 1:
return OPCODE_BT;
case 8:
return OPCODE_LOOP;
case 9:
return OPCODE_LOOPNEZ;
case 10:
return OPCODE_LOOPGTZ;
}
break;
case 2:
return OPCODE_BLTUI;
case 3:
return OPCODE_BGEUI;
}
break;
}
break;
case 7:
switch (Field_r_Slot_inst_get (insn))
{
case 0:
return OPCODE_BNONE;
case 1:
return OPCODE_BEQ;
case 2:
return OPCODE_BLT;
case 3:
return OPCODE_BLTU;
case 4:
return OPCODE_BALL;
case 5:
return OPCODE_BBC;
case 6:
case 7:
return OPCODE_BBCI;
case 8:
return OPCODE_BANY;
case 9:
return OPCODE_BNE;
case 10:
return OPCODE_BGE;
case 11:
return OPCODE_BGEU;
case 12:
return OPCODE_BNALL;
case 13:
return OPCODE_BBS;
case 14:
case 15:
return OPCODE_BBSI;
}
break;
}
return XTENSA_UNDEFINED;
}
static int
Slot_inst16b_decode (const xtensa_insnbuf insn)
{
switch (Field_op0_Slot_inst16b_get (insn))
{
case 12:
switch (Field_i_Slot_inst16b_get (insn))
{
case 0:
return OPCODE_MOVI_N;
case 1:
switch (Field_z_Slot_inst16b_get (insn))
{
case 0:
return OPCODE_BEQZ_N;
case 1:
return OPCODE_BNEZ_N;
}
break;
}
break;
case 13:
switch (Field_r_Slot_inst16b_get (insn))
{
case 0:
return OPCODE_MOV_N;
case 15:
switch (Field_t_Slot_inst16b_get (insn))
{
case 0:
return OPCODE_RET_N;
case 1:
return OPCODE_RETW_N;
case 2:
return OPCODE_BREAK_N;
case 3:
if (Field_s_Slot_inst16b_get (insn) == 0)
return OPCODE_NOP_N;
break;
case 6:
if (Field_s_Slot_inst16b_get (insn) == 0)
return OPCODE_ILL_N;
break;
}
break;
}
break;
}
return XTENSA_UNDEFINED;
}
static int
Slot_inst16a_decode (const xtensa_insnbuf insn)
{
switch (Field_op0_Slot_inst16a_get (insn))
{
case 8:
return OPCODE_L32I_N;
case 9:
return OPCODE_S32I_N;
case 10:
return OPCODE_ADD_N;
case 11:
return OPCODE_ADDI_N;
}
return XTENSA_UNDEFINED;
}
static int
Slot_ae_slot0_decode (const xtensa_insnbuf insn)
{
if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_J;
if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_EXTUI;
switch (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn))
{
case 6:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_BGEZ;
break;
case 7:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_BLTZ;
break;
case 8:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_BEQZ;
break;
case 9:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_BNEZ;
break;
case 10:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVI;
break;
}
switch (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn))
{
case 88:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SRAI;
break;
case 96:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SLLI;
break;
case 123:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_MOVTQ56;
break;
}
if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTP24A16X2_HH;
if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
Field_ae_r20_Slot_ae_slot0_get (insn) == 0)
return OPCODE_L32I;
if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16F_I;
if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTP24A16X2_HL;
if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16F_IU;
if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16F_X;
if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16F_XU;
if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTP24A16X2_LH;
if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16X2F_I;
if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16X2F_IU;
if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16X2F_XU;
if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP16X2F_X;
if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24_I;
if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24_IU;
if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24_X;
if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTP24A16X2_LL;
if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24_XU;
if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24F_I;
if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24F_XU;
if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24F_IU;
if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2_I;
if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2_IU;
if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2_X;
if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24F_X;
if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2_XU;
if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2F_I;
if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2F_X;
if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2F_IU;
if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LP24X2F_XU;
if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_MOVPA24X2;
if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16F_L_I;
if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16F_L_IU;
if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16X2F_X;
if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16F_L_X;
if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16X2F_XU;
if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24F_L_I;
if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24F_L_IU;
if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16F_L_XU;
if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24F_L_X;
if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24F_L_XU;
if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24S_L_IU;
if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24S_L_I;
if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24S_L_X;
if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24S_L_XU;
if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2F_I;
if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16X2F_I;
if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2F_IU;
if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2F_X;
if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2S_IU;
if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2F_XU;
if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2S_X;
if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2S_XU;
if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_TRUNCP24A32X2;
if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP24X2S_I;
if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SQ32F_I;
if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SQ32F_IU;
if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ32F_I;
if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ32F_X;
if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ32F_XU;
if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ56_I;
if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ32F_IU;
if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ56_IU;
if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_LQ56_X;
if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTQ48A32S;
if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_JX;
if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SSR;
if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_NOP;
if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_SSA8B;
if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_SSA8L;
if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_SSL;
if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_s8_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_LQ56_XU;
if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_s_Slot_ae_slot0_get (insn) == 0)
return OPCODE_ALL8;
switch (Field_ftsf293_Slot_ae_slot0_get (insn))
{
case 0:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BBCI;
break;
case 1:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BBSI;
break;
}
if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_s_Slot_ae_slot0_get (insn) == 0)
return OPCODE_ANY8;
if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_SSAI;
if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SP16X2F_IU;
if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SQ56S_I;
if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SQ56S_IU;
switch (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn))
{
case 964:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SLLIQ56;
break;
case 965:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SRAIQ56;
break;
case 966:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SRLIQ56;
break;
case 968:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SLLISQ56S;
break;
}
switch (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn))
{
case 3868:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ABS;
break;
case 3869:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_NEG;
break;
case 3870:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SRA;
break;
case 3871:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SRL;
break;
}
switch (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn))
{
case 7752:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_MOVP48;
break;
case 7753:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
return OPCODE_ANY4;
break;
}
if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_MOVQ56;
if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SLLSSQ56S;
if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SRASQ56;
if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SRLSQ56;
if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SLLSQ56;
if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_ALL4;
if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SQ56S_X;
if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SQ56S_XU;
if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTA32P24_H;
if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_CVTA32P24_L;
if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_MOVAP24S_H;
if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_TRUNCA16P24S_L;
if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_MOVAP24S_L;
if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_NSAQ56S;
if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_TRUNCA32Q48;
if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_BT;
if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_TRUNCA16P24S_H;
if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
return OPCODE_BLTUI;
if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_MOVFQ56;
if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SLLAQ56;
if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AE_SLLASQ56S;
if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SLL;
if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf357_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SRAAQ56;
if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SRLAQ56;
if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SQ32F_XU;
switch (Field_imm8_Slot_ae_slot0_get (insn))
{
case 178:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ADD;
break;
case 179:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ADDX8;
break;
case 180:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ADDX2;
break;
case 181:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_AND;
break;
case 182:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ANDB;
break;
case 183:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ANDBC;
break;
case 184:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ADDX4;
break;
case 185:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_CLAMPS;
break;
case 186:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MAX;
break;
case 187:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MIN;
break;
case 188:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MAXU;
break;
case 189:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MINU;
break;
case 190:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVEQZ;
break;
case 191:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVF;
break;
case 194:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVGEZ;
break;
case 195:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ORB;
break;
case 196:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVLTZ;
break;
case 197:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_ORBC;
break;
case 198:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SEXT;
break;
case 199:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SRC;
break;
case 200:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVNEZ;
break;
case 201:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SRLI;
break;
case 202:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SUB;
break;
case 203:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SUBX4;
break;
case 204:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SUBX2;
break;
case 205:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_SUBX8;
break;
case 206:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_XOR;
break;
case 207:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_XORB;
break;
case 208:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_MOVT;
break;
case 224:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
return OPCODE_OR;
break;
case 244:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
return OPCODE_AE_SQ32F_X;
break;
}
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
return OPCODE_L32R;
switch (Field_r_Slot_ae_slot0_get (insn))
{
case 0:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_BNE;
break;
case 1:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_BNONE;
break;
case 2:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_L16SI;
break;
case 3:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_L8UI;
break;
case 4:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_ADDI;
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_L16UI;
break;
case 5:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BALL;
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_S16I;
break;
case 6:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BANY;
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_S32I;
break;
case 7:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BBC;
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
return OPCODE_S8I;
break;
case 8:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_ADDMI;
break;
case 9:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BBS;
break;
case 10:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BEQ;
break;
case 11:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BGEU;
break;
case 12:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BGE;
break;
case 13:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BLT;
break;
case 14:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BLTU;
break;
case 15:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
return OPCODE_BNALL;
break;
}
switch (Field_t_Slot_ae_slot0_get (insn))
{
case 0:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
return OPCODE_BEQI;
break;
case 1:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
return OPCODE_BGEI;
break;
case 2:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
return OPCODE_BGEUI;
break;
case 3:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
return OPCODE_BNEI;
break;
case 4:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
return OPCODE_BLTI;
break;
case 5:
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
Field_r_Slot_ae_slot0_get (insn) == 0)
return OPCODE_BF;
break;
}
return XTENSA_UNDEFINED;
}
static int
Slot_ae_slot1_decode (const xtensa_insnbuf insn)
{
if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_NEGSP24S;
if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ABSSP24S;
if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_NEGP24;
if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_MAXBQ56S;
if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_MINBQ56S;
if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_EQQ56;
if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_ADDSQ56S;
if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_ANDQ56;
if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_MAXQ56S;
if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_ORQ56;
if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_MINQ56S;
if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_SUBQ56;
if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_SUBSQ56S;
if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_XORQ56;
if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_NANDQ56;
if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_ABSQ56;
if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
return OPCODE_AE_NEGSQ56S;
if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf338_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_SATQ48S;
if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_LTQ56S;
if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ABSSQ56S;
if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_NEGQ56;
if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_LEQ56S;
if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_TRUNCP24Q48X2;
if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ADDQ56;
if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAAFP24S_HH_LL;
if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAAFP24S_HL_LH;
if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAAP24S_HH_LL;
if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf12_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_SLLISP24S;
if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS32P16S_HL;
if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAAP24S_HL_LH;
if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS32P16S_LH;
if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS32P16S_LL;
if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS56P24S_HH;
if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFP24S_HH;
if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS56P24S_HL;
if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS56P24S_LH;
if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAP24S_HH;
if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFS56P24S_LL;
if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAP24S_HL;
if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAP24S_LH;
if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAP24S_LL;
if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFP24S_HL;
if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAS56P24S_HH;
if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAS56P24S_HL;
if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULASFP24S_HH_LL;
if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAS56P24S_LH;
if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULASFP24S_HL_LH;
if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULASP24S_HH_LL;
if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULASP24S_HL_LH;
if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAS56P24S_LL;
if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFP24S_HH;
if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFP24S_HL;
if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFP24S_LL;
if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFP24S_LH;
if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFS32P16S_HH;
if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFS32P16S_HL;
if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFS32P16S_LH;
if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFP24S_LH;
if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULFS32P16S_LL;
if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULP24S_HH;
if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSAFP24S_HH_LL;
if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULP24S_HL;
if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSAFP24S_HL_LH;
if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSAP24S_HH_LL;
if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSAP24S_HL_LH;
if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULP24S_LH;
if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFP24S_HH;
if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFP24S_HL;
if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFP24S_LL;
if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFP24S_LH;
if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS32P16S_HH;
if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS32P16S_HL;
if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS32P16S_LH;
if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULP24S_LL;
if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS32P16S_LL;
if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS56P24S_HH;
if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS56P24S_LL;
if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS56P24S_HL;
if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSP24S_HH;
if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSP24S_HL;
if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSP24S_LH;
if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSFS56P24S_LH;
if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSP24S_LL;
if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSS56P24S_HH;
if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSS56P24S_LH;
if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSS56P24S_HL;
if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSS56P24S_LL;
if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSSFP24S_HH_LL;
if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSSFP24S_HL_LH;
if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULAFP24S_LL;
if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSSP24S_HH_LL;
if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULSSP24S_HL_LH;
if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZASFP24S_HH_LL;
if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZAAFP24S_HH_LL;
if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZASFP24S_HL_LH;
if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZASP24S_HH_LL;
if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZASP24S_HL_LH;
if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZAAFP24S_HL_LH;
if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSAFP24S_HH_LL;
if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSAFP24S_HL_LH;
if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSAP24S_HL_LH;
if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSAP24S_HH_LL;
if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSSFP24S_HH_LL;
if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSSFP24S_HL_LH;
if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
return OPCODE_AE_MULZSSP24S_HH_LL;
if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULZAAP24S_HH_LL;
if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULZSSP24S_HL_LH;
if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULZAAP24S_HL_LH;
if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULAFS32P16S_HH;
if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MAXBP24S;
if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MINBP24S;
if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MOVFP48;
if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MOVTP48;
if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ADDP24;
if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ANDP48;
if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MAXP24S;
if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MINP24S;
if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ADDSP24S;
if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_NANDP48;
if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ORP48;
if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SELP24_HL;
if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SELP24_HH;
if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SELP24_LH;
if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SELP24_LL;
if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SUBP24;
switch (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn))
{
case 8:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SLLIP24;
break;
case 9:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SRAIP24;
break;
case 10:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SRLIP24;
break;
}
if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAFQ32SP16S_L;
if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAFQ32SP16U_H;
if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAFQ32SP16U_L;
if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAQ32SP16U_H;
if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAQ32SP16S_H;
if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAQ32SP16U_L;
if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULFQ32SP16S_H;
if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULFQ32SP16S_L;
if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAQ32SP16S_L;
if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULFQ32SP16U_H;
if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULFQ32SP16U_L;
if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULQ32SP16S_L;
if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULQ32SP16S_H;
if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULQ32SP16U_H;
if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULQ32SP16U_L;
if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULSFQ32SP16S_H;
if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULAFQ32SP16S_H;
if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULSFQ32SP16S_L;
if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULSFQ32SP16U_H;
if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULSQ32SP16U_L;
if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MULSFQ32SP16U_L;
if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_CVTQ48P24S_H;
if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ZEROQ56;
if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_NOP;
if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_CVTQ48P24S_L;
if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MOVQ56;
if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ROUNDSQ32ASYM;
if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ROUNDSQ32SYM;
if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_TRUNCQ32;
if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULSQ32SP16S_H;
if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULSQ32SP16S_L;
if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_MOVP48;
if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ROUNDSP16ASYM;
if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ROUNDSP16SYM;
if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SRASP24;
if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SLLSP24;
if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SRLSP24;
if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_TRUNCP16;
if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ZEROP48;
if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_SLLSSP24S;
if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ROUNDSP16Q48ASYM;
if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_ROUNDSP16Q48SYM;
if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ROUNDSP24Q48ASYM;
if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ROUNDSP24Q48SYM;
if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MULSQ32SP16U_H;
if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_EQP24;
if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_LEP24S;
if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf208_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_LTP24S;
if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ftsf347_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MOVFP24X2;
if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_MOVTP24X2;
if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_SUBSP24S;
if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
return OPCODE_AE_XORP48;
if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 &&
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
return OPCODE_AE_ABSP24;
switch (Field_t_Slot_ae_slot1_get (insn))
{
case 0:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAFQ32SP16S_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASFQ32SP16U_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSAQ32SP16S_LL;
break;
case 1:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAFQ32SP16S_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASFQ32SP16U_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSAQ32SP16U_HH;
break;
case 2:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAFQ32SP16S_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASQ32SP16S_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSAQ32SP16U_LH;
break;
case 3:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAFQ32SP16U_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASQ32SP16U_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSFQ32SP16S_LH;
break;
case 4:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAFQ32SP16U_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASQ32SP16S_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSAQ32SP16U_LL;
break;
case 5:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAQ32SP16S_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASQ32SP16U_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSFQ32SP16S_LL;
break;
case 6:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAQ32SP16S_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASQ32SP16U_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSFQ32SP16U_HH;
break;
case 7:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAQ32SP16S_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAFQ32SP16S_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSFQ32SP16U_LH;
break;
case 8:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAFQ32SP16U_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZASQ32SP16S_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSFQ32SP16S_HH;
break;
case 9:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAQ32SP16U_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAFQ32SP16S_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSFQ32SP16U_LL;
break;
case 10:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAQ32SP16U_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAFQ32SP16S_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSQ32SP16S_HH;
break;
case 11:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZASFQ32SP16S_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAFQ32SP16U_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSQ32SP16S_LL;
break;
case 12:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZAAQ32SP16U_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAFQ32SP16U_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSQ32SP16S_LH;
break;
case 13:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZASFQ32SP16S_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAFQ32SP16U_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSQ32SP16U_HH;
break;
case 14:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZASFQ32SP16S_LL;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAQ32SP16S_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSQ32SP16U_LH;
break;
case 15:
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
return OPCODE_AE_MULZASFQ32SP16U_HH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
return OPCODE_AE_MULZSAQ32SP16S_LH;
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
return OPCODE_AE_MULZSSQ32SP16U_LL;
break;
}
return XTENSA_UNDEFINED;
}
/* Instruction slots. */
static void
Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
xtensa_insnbuf slotbuf)
{
slotbuf[1] = 0;
slotbuf[0] = (insn[0] & 0xffffff);
}
static void
Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
const xtensa_insnbuf slotbuf)
{
insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
}
static void
Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
xtensa_insnbuf slotbuf)
{
slotbuf[1] = 0;
slotbuf[0] = (insn[0] & 0xffff);
}
static void
Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
const xtensa_insnbuf slotbuf)
{
insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
}
static void
Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
xtensa_insnbuf slotbuf)
{
slotbuf[1] = 0;
slotbuf[0] = (insn[0] & 0xffff);
}
static void
Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
const xtensa_insnbuf slotbuf)
{
insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
}
static void
Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn,
xtensa_insnbuf slotbuf)
{
slotbuf[1] = 0;
slotbuf[0] = ((insn[0] & 0x80000000) >> 31);
slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1);
}
static void
Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn,
const xtensa_insnbuf slotbuf)
{
insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31);
insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1);
}
static void
Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn,
xtensa_insnbuf slotbuf)
{
slotbuf[1] = 0;
slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4);
}
static void
Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn,
const xtensa_insnbuf slotbuf)
{
insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4);
}
static xtensa_get_field_fn
Slot_inst_get_field_fns[] = {
Field_t_Slot_inst_get,
Field_bbi4_Slot_inst_get,
Field_bbi_Slot_inst_get,
Field_imm12_Slot_inst_get,
Field_imm8_Slot_inst_get,
Field_s_Slot_inst_get,
Field_imm12b_Slot_inst_get,
Field_imm16_Slot_inst_get,
Field_m_Slot_inst_get,
Field_n_Slot_inst_get,
Field_offset_Slot_inst_get,
Field_op0_Slot_inst_get,
Field_op1_Slot_inst_get,
Field_op2_Slot_inst_get,
Field_r_Slot_inst_get,
Field_sa4_Slot_inst_get,
Field_sae4_Slot_inst_get,
Field_sae_Slot_inst_get,
Field_sal_Slot_inst_get,
Field_sargt_Slot_inst_get,
Field_sas4_Slot_inst_get,
Field_sas_Slot_inst_get,
Field_sr_Slot_inst_get,
Field_st_Slot_inst_get,
Field_thi3_Slot_inst_get,
Field_imm4_Slot_inst_get,
Field_mn_Slot_inst_get,
0,
0,
0,
0,
0,
0,
0,
0,
Field_t2_Slot_inst_get,
Field_s2_Slot_inst_get,
Field_r2_Slot_inst_get,
Field_t4_Slot_inst_get,
Field_s4_Slot_inst_get,
Field_r4_Slot_inst_get,
Field_t8_Slot_inst_get,
Field_s8_Slot_inst_get,
Field_r8_Slot_inst_get,
Field_xt_wbr15_imm_Slot_inst_get,
Field_xt_wbr18_imm_Slot_inst_get,
Field_ae_r3_Slot_inst_get,
Field_ae_s_non_samt_Slot_inst_get,
Field_ae_s3_Slot_inst_get,
Field_ae_r32_Slot_inst_get,
Field_ae_samt_s_t_Slot_inst_get,
Field_ae_r20_Slot_inst_get,
Field_ae_r10_Slot_inst_get,
Field_ae_s20_Slot_inst_get,
0,
Field_ftsf12_Slot_inst_get,
Field_ftsf13_Slot_inst_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_ar0_get,
Implicit_Field_ar4_get,
Implicit_Field_ar8_get,
Implicit_Field_ar12_get,
Implicit_Field_bt16_get,
Implicit_Field_bs16_get,
Implicit_Field_br16_get,
Implicit_Field_brall_get
};
static xtensa_set_field_fn
Slot_inst_set_field_fns[] = {
Field_t_Slot_inst_set,
Field_bbi4_Slot_inst_set,
Field_bbi_Slot_inst_set,
Field_imm12_Slot_inst_set,
Field_imm8_Slot_inst_set,
Field_s_Slot_inst_set,
Field_imm12b_Slot_inst_set,
Field_imm16_Slot_inst_set,
Field_m_Slot_inst_set,
Field_n_Slot_inst_set,
Field_offset_Slot_inst_set,
Field_op0_Slot_inst_set,
Field_op1_Slot_inst_set,
Field_op2_Slot_inst_set,
Field_r_Slot_inst_set,
Field_sa4_Slot_inst_set,
Field_sae4_Slot_inst_set,
Field_sae_Slot_inst_set,
Field_sal_Slot_inst_set,
Field_sargt_Slot_inst_set,
Field_sas4_Slot_inst_set,
Field_sas_Slot_inst_set,
Field_sr_Slot_inst_set,
Field_st_Slot_inst_set,
Field_thi3_Slot_inst_set,
Field_imm4_Slot_inst_set,
Field_mn_Slot_inst_set,
0,
0,
0,
0,
0,
0,
0,
0,
Field_t2_Slot_inst_set,
Field_s2_Slot_inst_set,
Field_r2_Slot_inst_set,
Field_t4_Slot_inst_set,
Field_s4_Slot_inst_set,
Field_r4_Slot_inst_set,
Field_t8_Slot_inst_set,
Field_s8_Slot_inst_set,
Field_r8_Slot_inst_set,
Field_xt_wbr15_imm_Slot_inst_set,
Field_xt_wbr18_imm_Slot_inst_set,
Field_ae_r3_Slot_inst_set,
Field_ae_s_non_samt_Slot_inst_set,
Field_ae_s3_Slot_inst_set,
Field_ae_r32_Slot_inst_set,
Field_ae_samt_s_t_Slot_inst_set,
Field_ae_r20_Slot_inst_set,
Field_ae_r10_Slot_inst_set,
Field_ae_s20_Slot_inst_set,
0,
Field_ftsf12_Slot_inst_set,
Field_ftsf13_Slot_inst_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set
};
static xtensa_get_field_fn
Slot_inst16a_get_field_fns[] = {
Field_t_Slot_inst16a_get,
0,
0,
0,
0,
Field_s_Slot_inst16a_get,
0,
0,
0,
0,
0,
Field_op0_Slot_inst16a_get,
0,
0,
Field_r_Slot_inst16a_get,
0,
0,
0,
0,
0,
0,
0,
Field_sr_Slot_inst16a_get,
Field_st_Slot_inst16a_get,
0,
Field_imm4_Slot_inst16a_get,
0,
Field_i_Slot_inst16a_get,
Field_imm6lo_Slot_inst16a_get,
Field_imm6hi_Slot_inst16a_get,
Field_imm7lo_Slot_inst16a_get,
Field_imm7hi_Slot_inst16a_get,
Field_z_Slot_inst16a_get,
Field_imm6_Slot_inst16a_get,
Field_imm7_Slot_inst16a_get,
Field_t2_Slot_inst16a_get,
Field_s2_Slot_inst16a_get,
Field_r2_Slot_inst16a_get,
Field_t4_Slot_inst16a_get,
Field_s4_Slot_inst16a_get,
Field_r4_Slot_inst16a_get,
Field_t8_Slot_inst16a_get,
Field_s8_Slot_inst16a_get,
Field_r8_Slot_inst16a_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_ar0_get,
Implicit_Field_ar4_get,
Implicit_Field_ar8_get,
Implicit_Field_ar12_get,
Implicit_Field_bt16_get,
Implicit_Field_bs16_get,
Implicit_Field_br16_get,
Implicit_Field_brall_get
};
static xtensa_set_field_fn
Slot_inst16a_set_field_fns[] = {
Field_t_Slot_inst16a_set,
0,
0,
0,
0,
Field_s_Slot_inst16a_set,
0,
0,
0,
0,
0,
Field_op0_Slot_inst16a_set,
0,
0,
Field_r_Slot_inst16a_set,
0,
0,
0,
0,
0,
0,
0,
Field_sr_Slot_inst16a_set,
Field_st_Slot_inst16a_set,
0,
Field_imm4_Slot_inst16a_set,
0,
Field_i_Slot_inst16a_set,
Field_imm6lo_Slot_inst16a_set,
Field_imm6hi_Slot_inst16a_set,
Field_imm7lo_Slot_inst16a_set,
Field_imm7hi_Slot_inst16a_set,
Field_z_Slot_inst16a_set,
Field_imm6_Slot_inst16a_set,
Field_imm7_Slot_inst16a_set,
Field_t2_Slot_inst16a_set,
Field_s2_Slot_inst16a_set,
Field_r2_Slot_inst16a_set,
Field_t4_Slot_inst16a_set,
Field_s4_Slot_inst16a_set,
Field_r4_Slot_inst16a_set,
Field_t8_Slot_inst16a_set,
Field_s8_Slot_inst16a_set,
Field_r8_Slot_inst16a_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set
};
static xtensa_get_field_fn
Slot_inst16b_get_field_fns[] = {
Field_t_Slot_inst16b_get,
0,
0,
0,
0,
Field_s_Slot_inst16b_get,
0,
0,
0,
0,
0,
Field_op0_Slot_inst16b_get,
0,
0,
Field_r_Slot_inst16b_get,
0,
0,
0,
0,
0,
0,
0,
Field_sr_Slot_inst16b_get,
Field_st_Slot_inst16b_get,
0,
Field_imm4_Slot_inst16b_get,
0,
Field_i_Slot_inst16b_get,
Field_imm6lo_Slot_inst16b_get,
Field_imm6hi_Slot_inst16b_get,
Field_imm7lo_Slot_inst16b_get,
Field_imm7hi_Slot_inst16b_get,
Field_z_Slot_inst16b_get,
Field_imm6_Slot_inst16b_get,
Field_imm7_Slot_inst16b_get,
Field_t2_Slot_inst16b_get,
Field_s2_Slot_inst16b_get,
Field_r2_Slot_inst16b_get,
Field_t4_Slot_inst16b_get,
Field_s4_Slot_inst16b_get,
Field_r4_Slot_inst16b_get,
Field_t8_Slot_inst16b_get,
Field_s8_Slot_inst16b_get,
Field_r8_Slot_inst16b_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_ar0_get,
Implicit_Field_ar4_get,
Implicit_Field_ar8_get,
Implicit_Field_ar12_get,
Implicit_Field_bt16_get,
Implicit_Field_bs16_get,
Implicit_Field_br16_get,
Implicit_Field_brall_get
};
static xtensa_set_field_fn
Slot_inst16b_set_field_fns[] = {
Field_t_Slot_inst16b_set,
0,
0,
0,
0,
Field_s_Slot_inst16b_set,
0,
0,
0,
0,
0,
Field_op0_Slot_inst16b_set,
0,
0,
Field_r_Slot_inst16b_set,
0,
0,
0,
0,
0,
0,
0,
Field_sr_Slot_inst16b_set,
Field_st_Slot_inst16b_set,
0,
Field_imm4_Slot_inst16b_set,
0,
Field_i_Slot_inst16b_set,
Field_imm6lo_Slot_inst16b_set,
Field_imm6hi_Slot_inst16b_set,
Field_imm7lo_Slot_inst16b_set,
Field_imm7hi_Slot_inst16b_set,
Field_z_Slot_inst16b_set,
Field_imm6_Slot_inst16b_set,
Field_imm7_Slot_inst16b_set,
Field_t2_Slot_inst16b_set,
Field_s2_Slot_inst16b_set,
Field_r2_Slot_inst16b_set,
Field_t4_Slot_inst16b_set,
Field_s4_Slot_inst16b_set,
Field_r4_Slot_inst16b_set,
Field_t8_Slot_inst16b_set,
Field_s8_Slot_inst16b_set,
Field_r8_Slot_inst16b_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set
};
static xtensa_get_field_fn
Slot_ae_slot1_get_field_fns[] = {
Field_t_Slot_ae_slot1_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_t2_Slot_ae_slot1_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_ae_r32_Slot_ae_slot1_get,
0,
Field_ae_r20_Slot_ae_slot1_get,
Field_ae_r10_Slot_ae_slot1_get,
Field_ae_s20_Slot_ae_slot1_get,
Field_op0_s3_Slot_ae_slot1_get,
Field_ftsf12_Slot_ae_slot1_get,
Field_ftsf13_Slot_ae_slot1_get,
Field_ftsf14_Slot_ae_slot1_get,
Field_ftsf21ae_slot1_Slot_ae_slot1_get,
Field_ftsf22ae_slot1_Slot_ae_slot1_get,
Field_ftsf23ae_slot1_Slot_ae_slot1_get,
Field_ftsf24ae_slot1_Slot_ae_slot1_get,
Field_ftsf25ae_slot1_Slot_ae_slot1_get,
Field_ftsf26ae_slot1_Slot_ae_slot1_get,
Field_ftsf27ae_slot1_Slot_ae_slot1_get,
Field_ftsf28ae_slot1_Slot_ae_slot1_get,
Field_ftsf29ae_slot1_Slot_ae_slot1_get,
Field_ftsf30ae_slot1_Slot_ae_slot1_get,
Field_ftsf31ae_slot1_Slot_ae_slot1_get,
Field_ftsf32ae_slot1_Slot_ae_slot1_get,
Field_ftsf33ae_slot1_Slot_ae_slot1_get,
Field_ftsf34ae_slot1_Slot_ae_slot1_get,
Field_ftsf35ae_slot1_Slot_ae_slot1_get,
Field_ftsf36ae_slot1_Slot_ae_slot1_get,
Field_ftsf37ae_slot1_Slot_ae_slot1_get,
Field_ftsf38ae_slot1_Slot_ae_slot1_get,
Field_ftsf39ae_slot1_Slot_ae_slot1_get,
Field_ftsf40ae_slot1_Slot_ae_slot1_get,
Field_ftsf41ae_slot1_Slot_ae_slot1_get,
Field_ftsf42ae_slot1_Slot_ae_slot1_get,
Field_ftsf43ae_slot1_Slot_ae_slot1_get,
Field_ftsf44ae_slot1_Slot_ae_slot1_get,
Field_ftsf45ae_slot1_Slot_ae_slot1_get,
Field_ftsf46ae_slot1_Slot_ae_slot1_get,
Field_ftsf47ae_slot1_Slot_ae_slot1_get,
Field_ftsf48ae_slot1_Slot_ae_slot1_get,
Field_ftsf49ae_slot1_Slot_ae_slot1_get,
Field_ftsf50ae_slot1_Slot_ae_slot1_get,
Field_ftsf51ae_slot1_Slot_ae_slot1_get,
Field_ftsf52ae_slot1_Slot_ae_slot1_get,
Field_ftsf53ae_slot1_Slot_ae_slot1_get,
Field_ftsf54ae_slot1_Slot_ae_slot1_get,
Field_ftsf55ae_slot1_Slot_ae_slot1_get,
Field_ftsf56ae_slot1_Slot_ae_slot1_get,
Field_ftsf57ae_slot1_Slot_ae_slot1_get,
Field_ftsf58ae_slot1_Slot_ae_slot1_get,
Field_ftsf59ae_slot1_Slot_ae_slot1_get,
Field_ftsf60ae_slot1_Slot_ae_slot1_get,
Field_ftsf61ae_slot1_Slot_ae_slot1_get,
Field_ftsf63ae_slot1_Slot_ae_slot1_get,
Field_ftsf64ae_slot1_Slot_ae_slot1_get,
Field_ftsf66ae_slot1_Slot_ae_slot1_get,
Field_ftsf67ae_slot1_Slot_ae_slot1_get,
Field_ftsf69ae_slot1_Slot_ae_slot1_get,
Field_ftsf71ae_slot1_Slot_ae_slot1_get,
Field_ftsf72ae_slot1_Slot_ae_slot1_get,
Field_ftsf73ae_slot1_Slot_ae_slot1_get,
Field_ftsf75ae_slot1_Slot_ae_slot1_get,
Field_ftsf76ae_slot1_Slot_ae_slot1_get,
Field_ftsf77ae_slot1_Slot_ae_slot1_get,
Field_ftsf78ae_slot1_Slot_ae_slot1_get,
Field_ftsf79ae_slot1_Slot_ae_slot1_get,
Field_ftsf80ae_slot1_Slot_ae_slot1_get,
Field_ftsf81ae_slot1_Slot_ae_slot1_get,
Field_ftsf82ae_slot1_Slot_ae_slot1_get,
Field_ftsf84ae_slot1_Slot_ae_slot1_get,
Field_ftsf86ae_slot1_Slot_ae_slot1_get,
Field_ftsf87ae_slot1_Slot_ae_slot1_get,
Field_ftsf88ae_slot1_Slot_ae_slot1_get,
Field_ftsf89ae_slot1_Slot_ae_slot1_get,
Field_ftsf90ae_slot1_Slot_ae_slot1_get,
Field_ftsf91ae_slot1_Slot_ae_slot1_get,
Field_ftsf92ae_slot1_Slot_ae_slot1_get,
Field_ftsf94ae_slot1_Slot_ae_slot1_get,
Field_ftsf96ae_slot1_Slot_ae_slot1_get,
Field_ftsf97ae_slot1_Slot_ae_slot1_get,
Field_ftsf98ae_slot1_Slot_ae_slot1_get,
Field_ftsf99ae_slot1_Slot_ae_slot1_get,
Field_ftsf100ae_slot1_Slot_ae_slot1_get,
Field_ftsf101ae_slot1_Slot_ae_slot1_get,
Field_ftsf103ae_slot1_Slot_ae_slot1_get,
Field_ftsf104ae_slot1_Slot_ae_slot1_get,
Field_ftsf105ae_slot1_Slot_ae_slot1_get,
Field_ftsf106ae_slot1_Slot_ae_slot1_get,
Field_ftsf107ae_slot1_Slot_ae_slot1_get,
Field_ftsf108ae_slot1_Slot_ae_slot1_get,
Field_ftsf109ae_slot1_Slot_ae_slot1_get,
Field_ftsf110ae_slot1_Slot_ae_slot1_get,
Field_ftsf111ae_slot1_Slot_ae_slot1_get,
Field_ftsf112ae_slot1_Slot_ae_slot1_get,
Field_ftsf113ae_slot1_Slot_ae_slot1_get,
Field_ftsf114ae_slot1_Slot_ae_slot1_get,
Field_ftsf115ae_slot1_Slot_ae_slot1_get,
Field_ftsf116ae_slot1_Slot_ae_slot1_get,
Field_ftsf118ae_slot1_Slot_ae_slot1_get,
Field_ftsf119ae_slot1_Slot_ae_slot1_get,
Field_ftsf120ae_slot1_Slot_ae_slot1_get,
Field_ftsf122ae_slot1_Slot_ae_slot1_get,
Field_ftsf124ae_slot1_Slot_ae_slot1_get,
Field_ftsf125ae_slot1_Slot_ae_slot1_get,
Field_ftsf126ae_slot1_Slot_ae_slot1_get,
Field_ftsf127ae_slot1_Slot_ae_slot1_get,
Field_ftsf128ae_slot1_Slot_ae_slot1_get,
Field_ftsf129ae_slot1_Slot_ae_slot1_get,
Field_ftsf130ae_slot1_Slot_ae_slot1_get,
Field_ftsf131ae_slot1_Slot_ae_slot1_get,
Field_ftsf132ae_slot1_Slot_ae_slot1_get,
Field_ftsf133ae_slot1_Slot_ae_slot1_get,
Field_ftsf134ae_slot1_Slot_ae_slot1_get,
Field_ftsf135ae_slot1_Slot_ae_slot1_get,
Field_ftsf136ae_slot1_Slot_ae_slot1_get,
Field_ftsf137ae_slot1_Slot_ae_slot1_get,
Field_ftsf138ae_slot1_Slot_ae_slot1_get,
Field_ftsf139ae_slot1_Slot_ae_slot1_get,
Field_ftsf140ae_slot1_Slot_ae_slot1_get,
Field_ftsf141ae_slot1_Slot_ae_slot1_get,
Field_ftsf142ae_slot1_Slot_ae_slot1_get,
Field_ftsf143ae_slot1_Slot_ae_slot1_get,
Field_ftsf144ae_slot1_Slot_ae_slot1_get,
Field_ftsf145ae_slot1_Slot_ae_slot1_get,
Field_ftsf146ae_slot1_Slot_ae_slot1_get,
Field_ftsf147ae_slot1_Slot_ae_slot1_get,
Field_ftsf148ae_slot1_Slot_ae_slot1_get,
Field_ftsf149ae_slot1_Slot_ae_slot1_get,
Field_ftsf150ae_slot1_Slot_ae_slot1_get,
Field_ftsf151ae_slot1_Slot_ae_slot1_get,
Field_ftsf152ae_slot1_Slot_ae_slot1_get,
Field_ftsf153ae_slot1_Slot_ae_slot1_get,
Field_ftsf154ae_slot1_Slot_ae_slot1_get,
Field_ftsf155ae_slot1_Slot_ae_slot1_get,
Field_ftsf156ae_slot1_Slot_ae_slot1_get,
Field_ftsf157ae_slot1_Slot_ae_slot1_get,
Field_ftsf158ae_slot1_Slot_ae_slot1_get,
Field_ftsf159ae_slot1_Slot_ae_slot1_get,
Field_ftsf160ae_slot1_Slot_ae_slot1_get,
Field_ftsf161ae_slot1_Slot_ae_slot1_get,
Field_ftsf162ae_slot1_Slot_ae_slot1_get,
Field_ftsf163ae_slot1_Slot_ae_slot1_get,
Field_ftsf164ae_slot1_Slot_ae_slot1_get,
Field_ftsf165ae_slot1_Slot_ae_slot1_get,
Field_ftsf166ae_slot1_Slot_ae_slot1_get,
Field_ftsf167ae_slot1_Slot_ae_slot1_get,
Field_ftsf168ae_slot1_Slot_ae_slot1_get,
Field_ftsf169ae_slot1_Slot_ae_slot1_get,
Field_ftsf170ae_slot1_Slot_ae_slot1_get,
Field_ftsf171ae_slot1_Slot_ae_slot1_get,
Field_ftsf172ae_slot1_Slot_ae_slot1_get,
Field_ftsf173ae_slot1_Slot_ae_slot1_get,
Field_ftsf174ae_slot1_Slot_ae_slot1_get,
Field_ftsf175ae_slot1_Slot_ae_slot1_get,
Field_ftsf176ae_slot1_Slot_ae_slot1_get,
Field_ftsf177ae_slot1_Slot_ae_slot1_get,
Field_ftsf178ae_slot1_Slot_ae_slot1_get,
Field_ftsf179ae_slot1_Slot_ae_slot1_get,
Field_ftsf180ae_slot1_Slot_ae_slot1_get,
Field_ftsf181ae_slot1_Slot_ae_slot1_get,
Field_ftsf182ae_slot1_Slot_ae_slot1_get,
Field_ftsf183ae_slot1_Slot_ae_slot1_get,
Field_ftsf184ae_slot1_Slot_ae_slot1_get,
Field_ftsf185ae_slot1_Slot_ae_slot1_get,
Field_ftsf186ae_slot1_Slot_ae_slot1_get,
Field_ftsf187ae_slot1_Slot_ae_slot1_get,
Field_ftsf188ae_slot1_Slot_ae_slot1_get,
Field_ftsf189ae_slot1_Slot_ae_slot1_get,
Field_ftsf190ae_slot1_Slot_ae_slot1_get,
Field_ftsf191ae_slot1_Slot_ae_slot1_get,
Field_ftsf192ae_slot1_Slot_ae_slot1_get,
Field_ftsf193ae_slot1_Slot_ae_slot1_get,
Field_ftsf194ae_slot1_Slot_ae_slot1_get,
Field_ftsf195ae_slot1_Slot_ae_slot1_get,
Field_ftsf196ae_slot1_Slot_ae_slot1_get,
Field_ftsf197ae_slot1_Slot_ae_slot1_get,
Field_ftsf198ae_slot1_Slot_ae_slot1_get,
Field_ftsf199ae_slot1_Slot_ae_slot1_get,
Field_ftsf200ae_slot1_Slot_ae_slot1_get,
Field_ftsf201ae_slot1_Slot_ae_slot1_get,
Field_ftsf202ae_slot1_Slot_ae_slot1_get,
Field_ftsf203ae_slot1_Slot_ae_slot1_get,
Field_ftsf204ae_slot1_Slot_ae_slot1_get,
Field_ftsf205ae_slot1_Slot_ae_slot1_get,
Field_ftsf206ae_slot1_Slot_ae_slot1_get,
Field_ftsf207ae_slot1_Slot_ae_slot1_get,
Field_ftsf208_Slot_ae_slot1_get,
Field_ftsf209ae_slot1_Slot_ae_slot1_get,
Field_ftsf210ae_slot1_Slot_ae_slot1_get,
Field_ftsf211ae_slot1_Slot_ae_slot1_get,
Field_ftsf330ae_slot1_Slot_ae_slot1_get,
Field_ftsf332ae_slot1_Slot_ae_slot1_get,
Field_ftsf334ae_slot1_Slot_ae_slot1_get,
Field_ftsf336ae_slot1_Slot_ae_slot1_get,
Field_ftsf337ae_slot1_Slot_ae_slot1_get,
Field_ftsf338_Slot_ae_slot1_get,
Field_ftsf339ae_slot1_Slot_ae_slot1_get,
Field_ftsf340_Slot_ae_slot1_get,
Field_ftsf341ae_slot1_Slot_ae_slot1_get,
Field_ftsf342ae_slot1_Slot_ae_slot1_get,
Field_ftsf343ae_slot1_Slot_ae_slot1_get,
Field_ftsf344ae_slot1_Slot_ae_slot1_get,
Field_ftsf346ae_slot1_Slot_ae_slot1_get,
Field_ftsf347_Slot_ae_slot1_get,
Field_ftsf348ae_slot1_Slot_ae_slot1_get,
Field_ftsf349ae_slot1_Slot_ae_slot1_get,
Field_ftsf350ae_slot1_Slot_ae_slot1_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_ar0_get,
Implicit_Field_ar4_get,
Implicit_Field_ar8_get,
Implicit_Field_ar12_get,
Implicit_Field_bt16_get,
Implicit_Field_bs16_get,
Implicit_Field_br16_get,
Implicit_Field_brall_get
};
static xtensa_set_field_fn
Slot_ae_slot1_set_field_fns[] = {
Field_t_Slot_ae_slot1_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_t2_Slot_ae_slot1_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_ae_r32_Slot_ae_slot1_set,
0,
Field_ae_r20_Slot_ae_slot1_set,
Field_ae_r10_Slot_ae_slot1_set,
Field_ae_s20_Slot_ae_slot1_set,
Field_op0_s3_Slot_ae_slot1_set,
Field_ftsf12_Slot_ae_slot1_set,
Field_ftsf13_Slot_ae_slot1_set,
Field_ftsf14_Slot_ae_slot1_set,
Field_ftsf21ae_slot1_Slot_ae_slot1_set,
Field_ftsf22ae_slot1_Slot_ae_slot1_set,
Field_ftsf23ae_slot1_Slot_ae_slot1_set,
Field_ftsf24ae_slot1_Slot_ae_slot1_set,
Field_ftsf25ae_slot1_Slot_ae_slot1_set,
Field_ftsf26ae_slot1_Slot_ae_slot1_set,
Field_ftsf27ae_slot1_Slot_ae_slot1_set,
Field_ftsf28ae_slot1_Slot_ae_slot1_set,
Field_ftsf29ae_slot1_Slot_ae_slot1_set,
Field_ftsf30ae_slot1_Slot_ae_slot1_set,
Field_ftsf31ae_slot1_Slot_ae_slot1_set,
Field_ftsf32ae_slot1_Slot_ae_slot1_set,
Field_ftsf33ae_slot1_Slot_ae_slot1_set,
Field_ftsf34ae_slot1_Slot_ae_slot1_set,
Field_ftsf35ae_slot1_Slot_ae_slot1_set,
Field_ftsf36ae_slot1_Slot_ae_slot1_set,
Field_ftsf37ae_slot1_Slot_ae_slot1_set,
Field_ftsf38ae_slot1_Slot_ae_slot1_set,
Field_ftsf39ae_slot1_Slot_ae_slot1_set,
Field_ftsf40ae_slot1_Slot_ae_slot1_set,
Field_ftsf41ae_slot1_Slot_ae_slot1_set,
Field_ftsf42ae_slot1_Slot_ae_slot1_set,
Field_ftsf43ae_slot1_Slot_ae_slot1_set,
Field_ftsf44ae_slot1_Slot_ae_slot1_set,
Field_ftsf45ae_slot1_Slot_ae_slot1_set,
Field_ftsf46ae_slot1_Slot_ae_slot1_set,
Field_ftsf47ae_slot1_Slot_ae_slot1_set,
Field_ftsf48ae_slot1_Slot_ae_slot1_set,
Field_ftsf49ae_slot1_Slot_ae_slot1_set,
Field_ftsf50ae_slot1_Slot_ae_slot1_set,
Field_ftsf51ae_slot1_Slot_ae_slot1_set,
Field_ftsf52ae_slot1_Slot_ae_slot1_set,
Field_ftsf53ae_slot1_Slot_ae_slot1_set,
Field_ftsf54ae_slot1_Slot_ae_slot1_set,
Field_ftsf55ae_slot1_Slot_ae_slot1_set,
Field_ftsf56ae_slot1_Slot_ae_slot1_set,
Field_ftsf57ae_slot1_Slot_ae_slot1_set,
Field_ftsf58ae_slot1_Slot_ae_slot1_set,
Field_ftsf59ae_slot1_Slot_ae_slot1_set,
Field_ftsf60ae_slot1_Slot_ae_slot1_set,
Field_ftsf61ae_slot1_Slot_ae_slot1_set,
Field_ftsf63ae_slot1_Slot_ae_slot1_set,
Field_ftsf64ae_slot1_Slot_ae_slot1_set,
Field_ftsf66ae_slot1_Slot_ae_slot1_set,
Field_ftsf67ae_slot1_Slot_ae_slot1_set,
Field_ftsf69ae_slot1_Slot_ae_slot1_set,
Field_ftsf71ae_slot1_Slot_ae_slot1_set,
Field_ftsf72ae_slot1_Slot_ae_slot1_set,
Field_ftsf73ae_slot1_Slot_ae_slot1_set,
Field_ftsf75ae_slot1_Slot_ae_slot1_set,
Field_ftsf76ae_slot1_Slot_ae_slot1_set,
Field_ftsf77ae_slot1_Slot_ae_slot1_set,
Field_ftsf78ae_slot1_Slot_ae_slot1_set,
Field_ftsf79ae_slot1_Slot_ae_slot1_set,
Field_ftsf80ae_slot1_Slot_ae_slot1_set,
Field_ftsf81ae_slot1_Slot_ae_slot1_set,
Field_ftsf82ae_slot1_Slot_ae_slot1_set,
Field_ftsf84ae_slot1_Slot_ae_slot1_set,
Field_ftsf86ae_slot1_Slot_ae_slot1_set,
Field_ftsf87ae_slot1_Slot_ae_slot1_set,
Field_ftsf88ae_slot1_Slot_ae_slot1_set,
Field_ftsf89ae_slot1_Slot_ae_slot1_set,
Field_ftsf90ae_slot1_Slot_ae_slot1_set,
Field_ftsf91ae_slot1_Slot_ae_slot1_set,
Field_ftsf92ae_slot1_Slot_ae_slot1_set,
Field_ftsf94ae_slot1_Slot_ae_slot1_set,
Field_ftsf96ae_slot1_Slot_ae_slot1_set,
Field_ftsf97ae_slot1_Slot_ae_slot1_set,
Field_ftsf98ae_slot1_Slot_ae_slot1_set,
Field_ftsf99ae_slot1_Slot_ae_slot1_set,
Field_ftsf100ae_slot1_Slot_ae_slot1_set,
Field_ftsf101ae_slot1_Slot_ae_slot1_set,
Field_ftsf103ae_slot1_Slot_ae_slot1_set,
Field_ftsf104ae_slot1_Slot_ae_slot1_set,
Field_ftsf105ae_slot1_Slot_ae_slot1_set,
Field_ftsf106ae_slot1_Slot_ae_slot1_set,
Field_ftsf107ae_slot1_Slot_ae_slot1_set,
Field_ftsf108ae_slot1_Slot_ae_slot1_set,
Field_ftsf109ae_slot1_Slot_ae_slot1_set,
Field_ftsf110ae_slot1_Slot_ae_slot1_set,
Field_ftsf111ae_slot1_Slot_ae_slot1_set,
Field_ftsf112ae_slot1_Slot_ae_slot1_set,
Field_ftsf113ae_slot1_Slot_ae_slot1_set,
Field_ftsf114ae_slot1_Slot_ae_slot1_set,
Field_ftsf115ae_slot1_Slot_ae_slot1_set,
Field_ftsf116ae_slot1_Slot_ae_slot1_set,
Field_ftsf118ae_slot1_Slot_ae_slot1_set,
Field_ftsf119ae_slot1_Slot_ae_slot1_set,
Field_ftsf120ae_slot1_Slot_ae_slot1_set,
Field_ftsf122ae_slot1_Slot_ae_slot1_set,
Field_ftsf124ae_slot1_Slot_ae_slot1_set,
Field_ftsf125ae_slot1_Slot_ae_slot1_set,
Field_ftsf126ae_slot1_Slot_ae_slot1_set,
Field_ftsf127ae_slot1_Slot_ae_slot1_set,
Field_ftsf128ae_slot1_Slot_ae_slot1_set,
Field_ftsf129ae_slot1_Slot_ae_slot1_set,
Field_ftsf130ae_slot1_Slot_ae_slot1_set,
Field_ftsf131ae_slot1_Slot_ae_slot1_set,
Field_ftsf132ae_slot1_Slot_ae_slot1_set,
Field_ftsf133ae_slot1_Slot_ae_slot1_set,
Field_ftsf134ae_slot1_Slot_ae_slot1_set,
Field_ftsf135ae_slot1_Slot_ae_slot1_set,
Field_ftsf136ae_slot1_Slot_ae_slot1_set,
Field_ftsf137ae_slot1_Slot_ae_slot1_set,
Field_ftsf138ae_slot1_Slot_ae_slot1_set,
Field_ftsf139ae_slot1_Slot_ae_slot1_set,
Field_ftsf140ae_slot1_Slot_ae_slot1_set,
Field_ftsf141ae_slot1_Slot_ae_slot1_set,
Field_ftsf142ae_slot1_Slot_ae_slot1_set,
Field_ftsf143ae_slot1_Slot_ae_slot1_set,
Field_ftsf144ae_slot1_Slot_ae_slot1_set,
Field_ftsf145ae_slot1_Slot_ae_slot1_set,
Field_ftsf146ae_slot1_Slot_ae_slot1_set,
Field_ftsf147ae_slot1_Slot_ae_slot1_set,
Field_ftsf148ae_slot1_Slot_ae_slot1_set,
Field_ftsf149ae_slot1_Slot_ae_slot1_set,
Field_ftsf150ae_slot1_Slot_ae_slot1_set,
Field_ftsf151ae_slot1_Slot_ae_slot1_set,
Field_ftsf152ae_slot1_Slot_ae_slot1_set,
Field_ftsf153ae_slot1_Slot_ae_slot1_set,
Field_ftsf154ae_slot1_Slot_ae_slot1_set,
Field_ftsf155ae_slot1_Slot_ae_slot1_set,
Field_ftsf156ae_slot1_Slot_ae_slot1_set,
Field_ftsf157ae_slot1_Slot_ae_slot1_set,
Field_ftsf158ae_slot1_Slot_ae_slot1_set,
Field_ftsf159ae_slot1_Slot_ae_slot1_set,
Field_ftsf160ae_slot1_Slot_ae_slot1_set,
Field_ftsf161ae_slot1_Slot_ae_slot1_set,
Field_ftsf162ae_slot1_Slot_ae_slot1_set,
Field_ftsf163ae_slot1_Slot_ae_slot1_set,
Field_ftsf164ae_slot1_Slot_ae_slot1_set,
Field_ftsf165ae_slot1_Slot_ae_slot1_set,
Field_ftsf166ae_slot1_Slot_ae_slot1_set,
Field_ftsf167ae_slot1_Slot_ae_slot1_set,
Field_ftsf168ae_slot1_Slot_ae_slot1_set,
Field_ftsf169ae_slot1_Slot_ae_slot1_set,
Field_ftsf170ae_slot1_Slot_ae_slot1_set,
Field_ftsf171ae_slot1_Slot_ae_slot1_set,
Field_ftsf172ae_slot1_Slot_ae_slot1_set,
Field_ftsf173ae_slot1_Slot_ae_slot1_set,
Field_ftsf174ae_slot1_Slot_ae_slot1_set,
Field_ftsf175ae_slot1_Slot_ae_slot1_set,
Field_ftsf176ae_slot1_Slot_ae_slot1_set,
Field_ftsf177ae_slot1_Slot_ae_slot1_set,
Field_ftsf178ae_slot1_Slot_ae_slot1_set,
Field_ftsf179ae_slot1_Slot_ae_slot1_set,
Field_ftsf180ae_slot1_Slot_ae_slot1_set,
Field_ftsf181ae_slot1_Slot_ae_slot1_set,
Field_ftsf182ae_slot1_Slot_ae_slot1_set,
Field_ftsf183ae_slot1_Slot_ae_slot1_set,
Field_ftsf184ae_slot1_Slot_ae_slot1_set,
Field_ftsf185ae_slot1_Slot_ae_slot1_set,
Field_ftsf186ae_slot1_Slot_ae_slot1_set,
Field_ftsf187ae_slot1_Slot_ae_slot1_set,
Field_ftsf188ae_slot1_Slot_ae_slot1_set,
Field_ftsf189ae_slot1_Slot_ae_slot1_set,
Field_ftsf190ae_slot1_Slot_ae_slot1_set,
Field_ftsf191ae_slot1_Slot_ae_slot1_set,
Field_ftsf192ae_slot1_Slot_ae_slot1_set,
Field_ftsf193ae_slot1_Slot_ae_slot1_set,
Field_ftsf194ae_slot1_Slot_ae_slot1_set,
Field_ftsf195ae_slot1_Slot_ae_slot1_set,
Field_ftsf196ae_slot1_Slot_ae_slot1_set,
Field_ftsf197ae_slot1_Slot_ae_slot1_set,
Field_ftsf198ae_slot1_Slot_ae_slot1_set,
Field_ftsf199ae_slot1_Slot_ae_slot1_set,
Field_ftsf200ae_slot1_Slot_ae_slot1_set,
Field_ftsf201ae_slot1_Slot_ae_slot1_set,
Field_ftsf202ae_slot1_Slot_ae_slot1_set,
Field_ftsf203ae_slot1_Slot_ae_slot1_set,
Field_ftsf204ae_slot1_Slot_ae_slot1_set,
Field_ftsf205ae_slot1_Slot_ae_slot1_set,
Field_ftsf206ae_slot1_Slot_ae_slot1_set,
Field_ftsf207ae_slot1_Slot_ae_slot1_set,
Field_ftsf208_Slot_ae_slot1_set,
Field_ftsf209ae_slot1_Slot_ae_slot1_set,
Field_ftsf210ae_slot1_Slot_ae_slot1_set,
Field_ftsf211ae_slot1_Slot_ae_slot1_set,
Field_ftsf330ae_slot1_Slot_ae_slot1_set,
Field_ftsf332ae_slot1_Slot_ae_slot1_set,
Field_ftsf334ae_slot1_Slot_ae_slot1_set,
Field_ftsf336ae_slot1_Slot_ae_slot1_set,
Field_ftsf337ae_slot1_Slot_ae_slot1_set,
Field_ftsf338_Slot_ae_slot1_set,
Field_ftsf339ae_slot1_Slot_ae_slot1_set,
Field_ftsf340_Slot_ae_slot1_set,
Field_ftsf341ae_slot1_Slot_ae_slot1_set,
Field_ftsf342ae_slot1_Slot_ae_slot1_set,
Field_ftsf343ae_slot1_Slot_ae_slot1_set,
Field_ftsf344ae_slot1_Slot_ae_slot1_set,
Field_ftsf346ae_slot1_Slot_ae_slot1_set,
Field_ftsf347_Slot_ae_slot1_set,
Field_ftsf348ae_slot1_Slot_ae_slot1_set,
Field_ftsf349ae_slot1_Slot_ae_slot1_set,
Field_ftsf350ae_slot1_Slot_ae_slot1_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set
};
static xtensa_get_field_fn
Slot_ae_slot0_get_field_fns[] = {
Field_t_Slot_ae_slot0_get,
0,
Field_bbi_Slot_ae_slot0_get,
Field_imm12_Slot_ae_slot0_get,
Field_imm8_Slot_ae_slot0_get,
Field_s_Slot_ae_slot0_get,
Field_imm12b_Slot_ae_slot0_get,
Field_imm16_Slot_ae_slot0_get,
0,
0,
Field_offset_Slot_ae_slot0_get,
0,
0,
Field_op2_Slot_ae_slot0_get,
Field_r_Slot_ae_slot0_get,
0,
0,
Field_sae_Slot_ae_slot0_get,
Field_sal_Slot_ae_slot0_get,
Field_sargt_Slot_ae_slot0_get,
0,
Field_sas_Slot_ae_slot0_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_s4_Slot_ae_slot0_get,
0,
0,
Field_s8_Slot_ae_slot0_get,
0,
0,
0,
0,
0,
0,
Field_ae_r32_Slot_ae_slot0_get,
Field_ae_samt_s_t_Slot_ae_slot0_get,
Field_ae_r20_Slot_ae_slot0_get,
Field_ae_r10_Slot_ae_slot0_get,
Field_ae_s20_Slot_ae_slot0_get,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_op0_s4_Slot_ae_slot0_get,
Field_ftsf212ae_slot0_Slot_ae_slot0_get,
Field_ftsf213ae_slot0_Slot_ae_slot0_get,
Field_ftsf214ae_slot0_Slot_ae_slot0_get,
Field_ftsf215ae_slot0_Slot_ae_slot0_get,
Field_ftsf216ae_slot0_Slot_ae_slot0_get,
Field_ftsf217_Slot_ae_slot0_get,
Field_ftsf218ae_slot0_Slot_ae_slot0_get,
Field_ftsf219ae_slot0_Slot_ae_slot0_get,
Field_ftsf220ae_slot0_Slot_ae_slot0_get,
Field_ftsf221ae_slot0_Slot_ae_slot0_get,
Field_ftsf222ae_slot0_Slot_ae_slot0_get,
Field_ftsf223ae_slot0_Slot_ae_slot0_get,
Field_ftsf224ae_slot0_Slot_ae_slot0_get,
Field_ftsf225ae_slot0_Slot_ae_slot0_get,
Field_ftsf226ae_slot0_Slot_ae_slot0_get,
Field_ftsf227ae_slot0_Slot_ae_slot0_get,
Field_ftsf228ae_slot0_Slot_ae_slot0_get,
Field_ftsf229ae_slot0_Slot_ae_slot0_get,
Field_ftsf230ae_slot0_Slot_ae_slot0_get,
Field_ftsf231ae_slot0_Slot_ae_slot0_get,
Field_ftsf232ae_slot0_Slot_ae_slot0_get,
Field_ftsf233ae_slot0_Slot_ae_slot0_get,
Field_ftsf234ae_slot0_Slot_ae_slot0_get,
Field_ftsf235ae_slot0_Slot_ae_slot0_get,
Field_ftsf236ae_slot0_Slot_ae_slot0_get,
Field_ftsf237ae_slot0_Slot_ae_slot0_get,
Field_ftsf238ae_slot0_Slot_ae_slot0_get,
Field_ftsf239ae_slot0_Slot_ae_slot0_get,
Field_ftsf240ae_slot0_Slot_ae_slot0_get,
Field_ftsf241ae_slot0_Slot_ae_slot0_get,
Field_ftsf242ae_slot0_Slot_ae_slot0_get,
Field_ftsf243ae_slot0_Slot_ae_slot0_get,
Field_ftsf244ae_slot0_Slot_ae_slot0_get,
Field_ftsf245ae_slot0_Slot_ae_slot0_get,
Field_ftsf246ae_slot0_Slot_ae_slot0_get,
Field_ftsf247ae_slot0_Slot_ae_slot0_get,
Field_ftsf248ae_slot0_Slot_ae_slot0_get,
Field_ftsf249ae_slot0_Slot_ae_slot0_get,
Field_ftsf250ae_slot0_Slot_ae_slot0_get,
Field_ftsf251ae_slot0_Slot_ae_slot0_get,
Field_ftsf252ae_slot0_Slot_ae_slot0_get,
Field_ftsf253ae_slot0_Slot_ae_slot0_get,
Field_ftsf254ae_slot0_Slot_ae_slot0_get,
Field_ftsf255ae_slot0_Slot_ae_slot0_get,
Field_ftsf256ae_slot0_Slot_ae_slot0_get,
Field_ftsf257ae_slot0_Slot_ae_slot0_get,
Field_ftsf258ae_slot0_Slot_ae_slot0_get,
Field_ftsf259ae_slot0_Slot_ae_slot0_get,
Field_ftsf260ae_slot0_Slot_ae_slot0_get,
Field_ftsf261ae_slot0_Slot_ae_slot0_get,
Field_ftsf262ae_slot0_Slot_ae_slot0_get,
Field_ftsf263ae_slot0_Slot_ae_slot0_get,
Field_ftsf264ae_slot0_Slot_ae_slot0_get,
Field_ftsf265ae_slot0_Slot_ae_slot0_get,
Field_ftsf266ae_slot0_Slot_ae_slot0_get,
Field_ftsf267ae_slot0_Slot_ae_slot0_get,
Field_ftsf268ae_slot0_Slot_ae_slot0_get,
Field_ftsf269ae_slot0_Slot_ae_slot0_get,
Field_ftsf270ae_slot0_Slot_ae_slot0_get,
Field_ftsf271ae_slot0_Slot_ae_slot0_get,
Field_ftsf272ae_slot0_Slot_ae_slot0_get,
Field_ftsf273ae_slot0_Slot_ae_slot0_get,
Field_ftsf274ae_slot0_Slot_ae_slot0_get,
Field_ftsf275ae_slot0_Slot_ae_slot0_get,
Field_ftsf276ae_slot0_Slot_ae_slot0_get,
Field_ftsf277ae_slot0_Slot_ae_slot0_get,
Field_ftsf278ae_slot0_Slot_ae_slot0_get,
Field_ftsf279ae_slot0_Slot_ae_slot0_get,
Field_ftsf281ae_slot0_Slot_ae_slot0_get,
Field_ftsf282ae_slot0_Slot_ae_slot0_get,
Field_ftsf283ae_slot0_Slot_ae_slot0_get,
Field_ftsf284ae_slot0_Slot_ae_slot0_get,
Field_ftsf286ae_slot0_Slot_ae_slot0_get,
Field_ftsf288ae_slot0_Slot_ae_slot0_get,
Field_ftsf290ae_slot0_Slot_ae_slot0_get,
Field_ftsf292ae_slot0_Slot_ae_slot0_get,
Field_ftsf293_Slot_ae_slot0_get,
Field_ftsf294ae_slot0_Slot_ae_slot0_get,
Field_ftsf295ae_slot0_Slot_ae_slot0_get,
Field_ftsf296ae_slot0_Slot_ae_slot0_get,
Field_ftsf297ae_slot0_Slot_ae_slot0_get,
Field_ftsf298ae_slot0_Slot_ae_slot0_get,
Field_ftsf299ae_slot0_Slot_ae_slot0_get,
Field_ftsf300ae_slot0_Slot_ae_slot0_get,
Field_ftsf301ae_slot0_Slot_ae_slot0_get,
Field_ftsf302ae_slot0_Slot_ae_slot0_get,
Field_ftsf303ae_slot0_Slot_ae_slot0_get,
Field_ftsf304ae_slot0_Slot_ae_slot0_get,
Field_ftsf306ae_slot0_Slot_ae_slot0_get,
Field_ftsf308ae_slot0_Slot_ae_slot0_get,
Field_ftsf309ae_slot0_Slot_ae_slot0_get,
Field_ftsf310ae_slot0_Slot_ae_slot0_get,
Field_ftsf311ae_slot0_Slot_ae_slot0_get,
Field_ftsf312ae_slot0_Slot_ae_slot0_get,
Field_ftsf313ae_slot0_Slot_ae_slot0_get,
Field_ftsf314ae_slot0_Slot_ae_slot0_get,
Field_ftsf315ae_slot0_Slot_ae_slot0_get,
Field_ftsf316ae_slot0_Slot_ae_slot0_get,
Field_ftsf317ae_slot0_Slot_ae_slot0_get,
Field_ftsf318ae_slot0_Slot_ae_slot0_get,
Field_ftsf319_Slot_ae_slot0_get,
Field_ftsf320ae_slot0_Slot_ae_slot0_get,
Field_ftsf321_Slot_ae_slot0_get,
Field_ftsf322ae_slot0_Slot_ae_slot0_get,
Field_ftsf323ae_slot0_Slot_ae_slot0_get,
Field_ftsf324ae_slot0_Slot_ae_slot0_get,
Field_ftsf325ae_slot0_Slot_ae_slot0_get,
Field_ftsf326ae_slot0_Slot_ae_slot0_get,
Field_ftsf328ae_slot0_Slot_ae_slot0_get,
Field_ftsf329ae_slot0_Slot_ae_slot0_get,
Field_ftsf352ae_slot0_Slot_ae_slot0_get,
Field_ftsf353_Slot_ae_slot0_get,
Field_ftsf354ae_slot0_Slot_ae_slot0_get,
Field_ftsf356ae_slot0_Slot_ae_slot0_get,
Field_ftsf357_Slot_ae_slot0_get,
Field_ftsf358ae_slot0_Slot_ae_slot0_get,
Field_ftsf359ae_slot0_Slot_ae_slot0_get,
Field_ftsf360ae_slot0_Slot_ae_slot0_get,
Field_ftsf361ae_slot0_Slot_ae_slot0_get,
Field_ftsf362ae_slot0_Slot_ae_slot0_get,
Field_ftsf364ae_slot0_Slot_ae_slot0_get,
Field_ftsf365ae_slot0_Slot_ae_slot0_get,
Field_ftsf366ae_slot0_Slot_ae_slot0_get,
Field_ftsf368ae_slot0_Slot_ae_slot0_get,
Field_ftsf369ae_slot0_Slot_ae_slot0_get,
Implicit_Field_ar0_get,
Implicit_Field_ar4_get,
Implicit_Field_ar8_get,
Implicit_Field_ar12_get,
Implicit_Field_bt16_get,
Implicit_Field_bs16_get,
Implicit_Field_br16_get,
Implicit_Field_brall_get
};
static xtensa_set_field_fn
Slot_ae_slot0_set_field_fns[] = {
Field_t_Slot_ae_slot0_set,
0,
Field_bbi_Slot_ae_slot0_set,
Field_imm12_Slot_ae_slot0_set,
Field_imm8_Slot_ae_slot0_set,
Field_s_Slot_ae_slot0_set,
Field_imm12b_Slot_ae_slot0_set,
Field_imm16_Slot_ae_slot0_set,
0,
0,
Field_offset_Slot_ae_slot0_set,
0,
0,
Field_op2_Slot_ae_slot0_set,
Field_r_Slot_ae_slot0_set,
0,
0,
Field_sae_Slot_ae_slot0_set,
Field_sal_Slot_ae_slot0_set,
Field_sargt_Slot_ae_slot0_set,
0,
Field_sas_Slot_ae_slot0_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_s4_Slot_ae_slot0_set,
0,
0,
Field_s8_Slot_ae_slot0_set,
0,
0,
0,
0,
0,
0,
Field_ae_r32_Slot_ae_slot0_set,
Field_ae_samt_s_t_Slot_ae_slot0_set,
Field_ae_r20_Slot_ae_slot0_set,
Field_ae_r10_Slot_ae_slot0_set,
Field_ae_s20_Slot_ae_slot0_set,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Field_op0_s4_Slot_ae_slot0_set,
Field_ftsf212ae_slot0_Slot_ae_slot0_set,
Field_ftsf213ae_slot0_Slot_ae_slot0_set,
Field_ftsf214ae_slot0_Slot_ae_slot0_set,
Field_ftsf215ae_slot0_Slot_ae_slot0_set,
Field_ftsf216ae_slot0_Slot_ae_slot0_set,
Field_ftsf217_Slot_ae_slot0_set,
Field_ftsf218ae_slot0_Slot_ae_slot0_set,
Field_ftsf219ae_slot0_Slot_ae_slot0_set,
Field_ftsf220ae_slot0_Slot_ae_slot0_set,
Field_ftsf221ae_slot0_Slot_ae_slot0_set,
Field_ftsf222ae_slot0_Slot_ae_slot0_set,
Field_ftsf223ae_slot0_Slot_ae_slot0_set,
Field_ftsf224ae_slot0_Slot_ae_slot0_set,
Field_ftsf225ae_slot0_Slot_ae_slot0_set,
Field_ftsf226ae_slot0_Slot_ae_slot0_set,
Field_ftsf227ae_slot0_Slot_ae_slot0_set,
Field_ftsf228ae_slot0_Slot_ae_slot0_set,
Field_ftsf229ae_slot0_Slot_ae_slot0_set,
Field_ftsf230ae_slot0_Slot_ae_slot0_set,
Field_ftsf231ae_slot0_Slot_ae_slot0_set,
Field_ftsf232ae_slot0_Slot_ae_slot0_set,
Field_ftsf233ae_slot0_Slot_ae_slot0_set,
Field_ftsf234ae_slot0_Slot_ae_slot0_set,
Field_ftsf235ae_slot0_Slot_ae_slot0_set,
Field_ftsf236ae_slot0_Slot_ae_slot0_set,
Field_ftsf237ae_slot0_Slot_ae_slot0_set,
Field_ftsf238ae_slot0_Slot_ae_slot0_set,
Field_ftsf239ae_slot0_Slot_ae_slot0_set,
Field_ftsf240ae_slot0_Slot_ae_slot0_set,
Field_ftsf241ae_slot0_Slot_ae_slot0_set,
Field_ftsf242ae_slot0_Slot_ae_slot0_set,
Field_ftsf243ae_slot0_Slot_ae_slot0_set,
Field_ftsf244ae_slot0_Slot_ae_slot0_set,
Field_ftsf245ae_slot0_Slot_ae_slot0_set,
Field_ftsf246ae_slot0_Slot_ae_slot0_set,
Field_ftsf247ae_slot0_Slot_ae_slot0_set,
Field_ftsf248ae_slot0_Slot_ae_slot0_set,
Field_ftsf249ae_slot0_Slot_ae_slot0_set,
Field_ftsf250ae_slot0_Slot_ae_slot0_set,
Field_ftsf251ae_slot0_Slot_ae_slot0_set,
Field_ftsf252ae_slot0_Slot_ae_slot0_set,
Field_ftsf253ae_slot0_Slot_ae_slot0_set,
Field_ftsf254ae_slot0_Slot_ae_slot0_set,
Field_ftsf255ae_slot0_Slot_ae_slot0_set,
Field_ftsf256ae_slot0_Slot_ae_slot0_set,
Field_ftsf257ae_slot0_Slot_ae_slot0_set,
Field_ftsf258ae_slot0_Slot_ae_slot0_set,
Field_ftsf259ae_slot0_Slot_ae_slot0_set,
Field_ftsf260ae_slot0_Slot_ae_slot0_set,
Field_ftsf261ae_slot0_Slot_ae_slot0_set,
Field_ftsf262ae_slot0_Slot_ae_slot0_set,
Field_ftsf263ae_slot0_Slot_ae_slot0_set,
Field_ftsf264ae_slot0_Slot_ae_slot0_set,
Field_ftsf265ae_slot0_Slot_ae_slot0_set,
Field_ftsf266ae_slot0_Slot_ae_slot0_set,
Field_ftsf267ae_slot0_Slot_ae_slot0_set,
Field_ftsf268ae_slot0_Slot_ae_slot0_set,
Field_ftsf269ae_slot0_Slot_ae_slot0_set,
Field_ftsf270ae_slot0_Slot_ae_slot0_set,
Field_ftsf271ae_slot0_Slot_ae_slot0_set,
Field_ftsf272ae_slot0_Slot_ae_slot0_set,
Field_ftsf273ae_slot0_Slot_ae_slot0_set,
Field_ftsf274ae_slot0_Slot_ae_slot0_set,
Field_ftsf275ae_slot0_Slot_ae_slot0_set,
Field_ftsf276ae_slot0_Slot_ae_slot0_set,
Field_ftsf277ae_slot0_Slot_ae_slot0_set,
Field_ftsf278ae_slot0_Slot_ae_slot0_set,
Field_ftsf279ae_slot0_Slot_ae_slot0_set,
Field_ftsf281ae_slot0_Slot_ae_slot0_set,
Field_ftsf282ae_slot0_Slot_ae_slot0_set,
Field_ftsf283ae_slot0_Slot_ae_slot0_set,
Field_ftsf284ae_slot0_Slot_ae_slot0_set,
Field_ftsf286ae_slot0_Slot_ae_slot0_set,
Field_ftsf288ae_slot0_Slot_ae_slot0_set,
Field_ftsf290ae_slot0_Slot_ae_slot0_set,
Field_ftsf292ae_slot0_Slot_ae_slot0_set,
Field_ftsf293_Slot_ae_slot0_set,
Field_ftsf294ae_slot0_Slot_ae_slot0_set,
Field_ftsf295ae_slot0_Slot_ae_slot0_set,
Field_ftsf296ae_slot0_Slot_ae_slot0_set,
Field_ftsf297ae_slot0_Slot_ae_slot0_set,
Field_ftsf298ae_slot0_Slot_ae_slot0_set,
Field_ftsf299ae_slot0_Slot_ae_slot0_set,
Field_ftsf300ae_slot0_Slot_ae_slot0_set,
Field_ftsf301ae_slot0_Slot_ae_slot0_set,
Field_ftsf302ae_slot0_Slot_ae_slot0_set,
Field_ftsf303ae_slot0_Slot_ae_slot0_set,
Field_ftsf304ae_slot0_Slot_ae_slot0_set,
Field_ftsf306ae_slot0_Slot_ae_slot0_set,
Field_ftsf308ae_slot0_Slot_ae_slot0_set,
Field_ftsf309ae_slot0_Slot_ae_slot0_set,
Field_ftsf310ae_slot0_Slot_ae_slot0_set,
Field_ftsf311ae_slot0_Slot_ae_slot0_set,
Field_ftsf312ae_slot0_Slot_ae_slot0_set,
Field_ftsf313ae_slot0_Slot_ae_slot0_set,
Field_ftsf314ae_slot0_Slot_ae_slot0_set,
Field_ftsf315ae_slot0_Slot_ae_slot0_set,
Field_ftsf316ae_slot0_Slot_ae_slot0_set,
Field_ftsf317ae_slot0_Slot_ae_slot0_set,
Field_ftsf318ae_slot0_Slot_ae_slot0_set,
Field_ftsf319_Slot_ae_slot0_set,
Field_ftsf320ae_slot0_Slot_ae_slot0_set,
Field_ftsf321_Slot_ae_slot0_set,
Field_ftsf322ae_slot0_Slot_ae_slot0_set,
Field_ftsf323ae_slot0_Slot_ae_slot0_set,
Field_ftsf324ae_slot0_Slot_ae_slot0_set,
Field_ftsf325ae_slot0_Slot_ae_slot0_set,
Field_ftsf326ae_slot0_Slot_ae_slot0_set,
Field_ftsf328ae_slot0_Slot_ae_slot0_set,
Field_ftsf329ae_slot0_Slot_ae_slot0_set,
Field_ftsf352ae_slot0_Slot_ae_slot0_set,
Field_ftsf353_Slot_ae_slot0_set,
Field_ftsf354ae_slot0_Slot_ae_slot0_set,
Field_ftsf356ae_slot0_Slot_ae_slot0_set,
Field_ftsf357_Slot_ae_slot0_set,
Field_ftsf358ae_slot0_Slot_ae_slot0_set,
Field_ftsf359ae_slot0_Slot_ae_slot0_set,
Field_ftsf360ae_slot0_Slot_ae_slot0_set,
Field_ftsf361ae_slot0_Slot_ae_slot0_set,
Field_ftsf362ae_slot0_Slot_ae_slot0_set,
Field_ftsf364ae_slot0_Slot_ae_slot0_set,
Field_ftsf365ae_slot0_Slot_ae_slot0_set,
Field_ftsf366ae_slot0_Slot_ae_slot0_set,
Field_ftsf368ae_slot0_Slot_ae_slot0_set,
Field_ftsf369ae_slot0_Slot_ae_slot0_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set,
Implicit_Field_set
};
static xtensa_slot_internal slots[] = {
{ "Inst", "x24", 0,
Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
Slot_inst_get_field_fns, Slot_inst_set_field_fns,
Slot_inst_decode, "nop" },
{ "Inst16a", "x16a", 0,
Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
Slot_inst16a_decode, "" },
{ "Inst16b", "x16b", 0,
Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
Slot_inst16b_decode, "nop.n" },
{ "ae_slot1", "ae_format", 1,
Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set,
Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
Slot_ae_slot1_decode, "nop" },
{ "ae_slot0", "ae_format", 0,
Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set,
Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
Slot_ae_slot0_decode, "nop" }
};
/* Instruction formats. */
static void
Format_x24_encode (xtensa_insnbuf insn)
{
insn[0] = 0;
insn[1] = 0;
}
static void
Format_x16a_encode (xtensa_insnbuf insn)
{
insn[0] = 0x8;
insn[1] = 0;
}
static void
Format_x16b_encode (xtensa_insnbuf insn)
{
insn[0] = 0xc;
insn[1] = 0;
}
static void
Format_ae_format_encode (xtensa_insnbuf insn)
{
insn[0] = 0xf;
insn[1] = 0;
}
static int Format_x24_slots[] = { 0 };
static int Format_x16a_slots[] = { 1 };
static int Format_x16b_slots[] = { 2 };
static int Format_ae_format_slots[] = { 4, 3 };
static xtensa_format_internal formats[] = {
{ "x24", 3, Format_x24_encode, 1, Format_x24_slots },
{ "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
{ "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
{ "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
};
static int
format_decoder (const xtensa_insnbuf insn)
{
if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
return 0; /* x24 */
if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
return 1; /* x16a */
if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
return 2; /* x16b */
if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0)
return 3; /* ae_format */
return -1;
}
static int length_table[16] = {
3,
3,
3,
3,
3,
3,
3,
3,
2,
2,
2,
2,
2,
2,
-1,
8
};
static int
length_decoder (const unsigned char *insn)
{
int op0 = insn[0] & 0xf;
return length_table[op0];
}
/* Top-level ISA structure. */
xtensa_isa_internal xtensa_modules = {
0 /* little-endian */,
8 /* insn_size */, 0,
4, formats, format_decoder, length_decoder,
5, slots,
387 /* num_fields */,
445, operands,
588, iclasses,
656, opcodes, 0,
8, regfiles,
NUM_STATES, states, 0,
NUM_SYSREGS, sysregs, 0,
{ MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
2, interfaces, 0,
4, funcUnits, 0
};
|
pmp-tool/PMP | src/qemu/src-pmp/target/ppc/translate/vmx-impl.inc.c | /*
* translate/vmx-impl.c
*
* Altivec/VMX translation
*/
/*** Altivec vector extension ***/
/* Altivec registers moves */
static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
return r;
}
#define GEN_VR_LDX(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_i64 avr; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
avr = tcg_temp_new_i64(); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
tcg_gen_andi_tl(EA, EA, ~0xf); \
/* We only need to swap high and low halves. gen_qemu_ld64_i64 does \
necessary 64-bit byteswap already. */ \
if (ctx->le_mode) { \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, false); \
tcg_gen_addi_tl(EA, EA, 8); \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, true); \
} else { \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, true); \
tcg_gen_addi_tl(EA, EA, 8); \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, false); \
} \
tcg_temp_free(EA); \
tcg_temp_free_i64(avr); \
}
#define GEN_VR_STX(name, opc2, opc3) \
static void gen_st##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_i64 avr; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
avr = tcg_temp_new_i64(); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
tcg_gen_andi_tl(EA, EA, ~0xf); \
/* We only need to swap high and low halves. gen_qemu_st64_i64 does \
necessary 64-bit byteswap already. */ \
if (ctx->le_mode) { \
get_avr64(avr, rD(ctx->opcode), false); \
gen_qemu_st64_i64(ctx, avr, EA); \
tcg_gen_addi_tl(EA, EA, 8); \
get_avr64(avr, rD(ctx->opcode), true); \
gen_qemu_st64_i64(ctx, avr, EA); \
} else { \
get_avr64(avr, rD(ctx->opcode), true); \
gen_qemu_st64_i64(ctx, avr, EA); \
tcg_gen_addi_tl(EA, EA, 8); \
get_avr64(avr, rD(ctx->opcode), false); \
gen_qemu_st64_i64(ctx, avr, EA); \
} \
tcg_temp_free(EA); \
tcg_temp_free_i64(avr); \
}
#define GEN_VR_LVE(name, opc2, opc3, size) \
static void gen_lve##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_ptr rs; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
if (size > 1) { \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_lve##name(cpu_env, rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
#define GEN_VR_STVE(name, opc2, opc3, size) \
static void gen_stve##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_ptr rs; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
if (size > 1) { \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_stve##name(cpu_env, rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
GEN_VR_LVE(bx, 0x07, 0x00, 1);
GEN_VR_LVE(hx, 0x07, 0x01, 2);
GEN_VR_LVE(wx, 0x07, 0x02, 4);
GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
GEN_VR_STVE(bx, 0x07, 0x04, 1);
GEN_VR_STVE(hx, 0x07, 0x05, 2);
GEN_VR_STVE(wx, 0x07, 0x06, 4);
static void gen_lvsl(DisasContext *ctx)
{
TCGv_ptr rd;
TCGv EA;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
rd = gen_avr_ptr(rD(ctx->opcode));
gen_helper_lvsl(rd, EA);
tcg_temp_free(EA);
tcg_temp_free_ptr(rd);
}
static void gen_lvsr(DisasContext *ctx)
{
TCGv_ptr rd;
TCGv EA;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
rd = gen_avr_ptr(rD(ctx->opcode));
gen_helper_lvsr(rd, EA);
tcg_temp_free(EA);
tcg_temp_free_ptr(rd);
}
static void gen_mfvscr(DisasContext *ctx)
{
TCGv_i32 t;
TCGv_i64 avr;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
avr = tcg_temp_new_i64();
tcg_gen_movi_i64(avr, 0);
set_avr64(rD(ctx->opcode), avr, true);
t = tcg_temp_new_i32();
gen_helper_mfvscr(t, cpu_env);
tcg_gen_extu_i32_i64(avr, t);
set_avr64(rD(ctx->opcode), avr, false);
tcg_temp_free_i32(t);
tcg_temp_free_i64(avr);
}
static void gen_mtvscr(DisasContext *ctx)
{
TCGv_i32 val;
int bofs;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
val = tcg_temp_new_i32();
bofs = avr_full_offset(rB(ctx->opcode));
#ifdef HOST_WORDS_BIGENDIAN
bofs += 3 * 4;
#endif
tcg_gen_ld_i32(val, cpu_env, bofs);
gen_helper_mtvscr(cpu_env, val);
tcg_temp_free_i32(val);
}
#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
TCGv_i64 t1; \
TCGv_i64 t2; \
TCGv_i64 avr; \
TCGv_i64 ten, z; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
t2 = tcg_temp_new_i64(); \
avr = tcg_temp_new_i64(); \
ten = tcg_const_i64(10); \
z = tcg_const_i64(0); \
\
if (add_cin) { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
get_avr64(avr, rB(ctx->opcode), false); \
tcg_gen_andi_i64(t2, avr, 0xF); \
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
} else { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(avr, t2, avr, ten); \
set_avr64(rD(ctx->opcode), avr, false); \
} \
\
if (ret_carry) { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
set_avr64(rD(ctx->opcode), z, true); \
} else { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mul_i64(t0, avr, ten); \
tcg_gen_add_i64(avr, t0, t2); \
set_avr64(rD(ctx->opcode), avr, true); \
} \
\
tcg_temp_free_i64(t0); \
tcg_temp_free_i64(t1); \
tcg_temp_free_i64(t2); \
tcg_temp_free_i64(avr); \
tcg_temp_free_i64(ten); \
tcg_temp_free_i64(z); \
} \
GEN_VX_VMUL10(vmul10uq, 0, 0);
GEN_VX_VMUL10(vmul10euq, 1, 0);
GEN_VX_VMUL10(vmul10cuq, 0, 1);
GEN_VX_VMUL10(vmul10ecuq, 1, 1);
#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
tcg_op(vece, \
avr_full_offset(rD(ctx->opcode)), \
avr_full_offset(rA(ctx->opcode)), \
avr_full_offset(rB(ctx->opcode)), \
16, 16); \
}
/* Logical operations */
GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
#define GEN_VXFORM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name (rd, ra, rb); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM_ENV(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, ra, rb); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM3(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rc, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rc = gen_avr_ptr(rC(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(rd, ra, rb, rc); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rc); \
tcg_temp_free_ptr(rd); \
}
/*
* Support for Altivec instruction pairs that use bit 31 (Rc) as
* an opcode bit. In general, these pairs come from different
* versions of the ISA, so we must also support a pair of flags for
* each instruction.
*/
#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
if ((Rc(ctx->opcode) == 0) && \
((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
gen_##name0(ctx); \
} else if ((Rc(ctx->opcode) == 1) && \
((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
gen_##name1(ctx); \
} else { \
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
} \
}
/* Adds support to provide invalid mask */
#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
name1, flg1, flg2_1, inval1) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
if ((Rc(ctx->opcode) == 0) && \
((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
!(ctx->opcode & inval0)) { \
gen_##name0(ctx); \
} else if ((Rc(ctx->opcode) == 1) && \
((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
!(ctx->opcode & inval1)) { \
gen_##name1(ctx); \
} else { \
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
} \
}
#define GEN_VXFORM_HETRO(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
tcg_temp_free_ptr(rb); \
}
GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
vmul10ecuq, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
GEN_VXFORM(vavgub, 1, 16);
GEN_VXFORM(vabsdub, 1, 16);
GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
vabsdub, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavguh, 1, 17);
GEN_VXFORM(vabsduh, 1, 17);
GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
vabsduh, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavguw, 1, 18);
GEN_VXFORM(vabsduw, 1, 18);
GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
vabsduw, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavgsb, 1, 20);
GEN_VXFORM(vavgsh, 1, 21);
GEN_VXFORM(vavgsw, 1, 22);
GEN_VXFORM(vmrghb, 6, 0);
GEN_VXFORM(vmrghh, 6, 1);
GEN_VXFORM(vmrghw, 6, 2);
GEN_VXFORM(vmrglb, 6, 4);
GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
static void gen_vmrgew(DisasContext *ctx)
{
TCGv_i64 tmp;
TCGv_i64 avr;
int VT, VA, VB;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
VT = rD(ctx->opcode);
VA = rA(ctx->opcode);
VB = rB(ctx->opcode);
tmp = tcg_temp_new_i64();
avr = tcg_temp_new_i64();
get_avr64(avr, VB, true);
tcg_gen_shri_i64(tmp, avr, 32);
get_avr64(avr, VA, true);
tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
set_avr64(VT, avr, true);
get_avr64(avr, VB, false);
tcg_gen_shri_i64(tmp, avr, 32);
get_avr64(avr, VA, false);
tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
set_avr64(VT, avr, false);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(avr);
}
static void gen_vmrgow(DisasContext *ctx)
{
TCGv_i64 t0, t1;
TCGv_i64 avr;
int VT, VA, VB;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
VT = rD(ctx->opcode);
VA = rA(ctx->opcode);
VB = rB(ctx->opcode);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
avr = tcg_temp_new_i64();
get_avr64(t0, VB, true);
get_avr64(t1, VA, true);
tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
set_avr64(VT, avr, true);
get_avr64(t0, VB, false);
get_avr64(t1, VA, false);
tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
set_avr64(VT, avr, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(avr);
}
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
GEN_VXFORM(vmulouw, 4, 2);
GEN_VXFORM(vmuluwm, 4, 2);
GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
GEN_VXFORM(vmulosw, 4, 6);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vslb, 2, 4);
GEN_VXFORM(vslh, 2, 5);
GEN_VXFORM(vslw, 2, 6);
GEN_VXFORM(vrlwnm, 2, 6);
GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
vrlwnm, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsld, 2, 23);
GEN_VXFORM(vsrb, 2, 8);
GEN_VXFORM(vsrh, 2, 9);
GEN_VXFORM(vsrw, 2, 10);
GEN_VXFORM(vsrd, 2, 27);
GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
TCGv_vec b) \
{ \
TCGv_vec x = tcg_temp_new_vec_matching(t); \
glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
tcg_gen_or_vec(VECE, sat, sat, x); \
tcg_temp_free_vec(x); \
} \
static void glue(gen_, NAME)(DisasContext *ctx) \
{ \
static const GVecGen4 g = { \
.fniv = glue(glue(gen_, NAME), _vec), \
.fno = glue(gen_helper_, NAME), \
.opc = glue(glue(INDEX_op_, SAT), _vec), \
.write_aofs = true, \
.vece = VECE, \
}; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
offsetof(CPUPPCState, vscr_sat), \
avr_full_offset(rA(ctx->opcode)), \
avr_full_offset(rB(ctx->opcode)), \
16, 16, &g); \
}
GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
vmul10euq, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
GEN_VXFORM(vadduqm, 0, 4);
GEN_VXFORM(vaddcuq, 0, 5);
GEN_VXFORM3(vaddeuqm, 30, 0);
GEN_VXFORM3(vaddecuq, 30, 0);
GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM(vsubuqm, 0, 20);
GEN_VXFORM(vsubcuq, 0, 21);
GEN_VXFORM3(vsubeuqm, 31, 0);
GEN_VXFORM3(vsubecuq, 31, 0);
GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
GEN_VXFORM(vrlwmi, 2, 2);
GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
vrlwmi, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vrld, 2, 3);
GEN_VXFORM(vrldmi, 2, 3);
GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
vrldmi, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vrldnm, 2, 7);
GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
vrldnm, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vsr, 2, 11);
GEN_VXFORM_ENV(vpkuhum, 7, 0);
GEN_VXFORM_ENV(vpkuwum, 7, 1);
GEN_VXFORM_ENV(vpkudum, 7, 17);
GEN_VXFORM_ENV(vpkuhus, 7, 2);
GEN_VXFORM_ENV(vpkuwus, 7, 3);
GEN_VXFORM_ENV(vpkudus, 7, 19);
GEN_VXFORM_ENV(vpkshus, 7, 4);
GEN_VXFORM_ENV(vpkswus, 7, 5);
GEN_VXFORM_ENV(vpksdus, 7, 21);
GEN_VXFORM_ENV(vpkshss, 7, 6);
GEN_VXFORM_ENV(vpkswss, 7, 7);
GEN_VXFORM_ENV(vpksdss, 7, 23);
GEN_VXFORM(vpkpx, 7, 12);
GEN_VXFORM_ENV(vsum4ubs, 4, 24);
GEN_VXFORM_ENV(vsum4sbs, 4, 28);
GEN_VXFORM_ENV(vsum4shs, 4, 25);
GEN_VXFORM_ENV(vsum2sws, 4, 26);
GEN_VXFORM_ENV(vsumsws, 4, 30);
GEN_VXFORM_ENV(vaddfp, 5, 0);
GEN_VXFORM_ENV(vsubfp, 5, 1);
GEN_VXFORM_ENV(vmaxfp, 5, 16);
GEN_VXFORM_ENV(vminfp, 5, 17);
GEN_VXFORM_HETRO(vextublx, 6, 24)
GEN_VXFORM_HETRO(vextuhlx, 6, 25)
GEN_VXFORM_HETRO(vextuwlx, 6, 26)
GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
vextuwlx, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_HETRO(vextubrx, 6, 28)
GEN_VXFORM_HETRO(vextuhrx, 6, 29)
GEN_VXFORM_HETRO(vextuwrx, 6, 30)
GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
vextuwrx, PPC_NONE, PPC2_ISA300)
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##opname(cpu_env, rd, ra, rb); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXRFORM(name, opc2, opc3) \
GEN_VXRFORM1(name, name, #name, opc2, opc3) \
GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
/*
* Support for Altivec instructions that use bit 31 (Rc) as an opcode
* bit but also use bit 21 as an actual Rc bit. In general, thse pairs
* come from different versions of the ISA, so we must also support a
* pair of flags for each instruction.
*/
#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
if ((Rc(ctx->opcode) == 0) && \
((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
if (Rc21(ctx->opcode) == 0) { \
gen_##name0(ctx); \
} else { \
gen_##name0##_(ctx); \
} \
} else if ((Rc(ctx->opcode) == 1) && \
((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
if (Rc21(ctx->opcode) == 0) { \
gen_##name1(ctx); \
} else { \
gen_##name1##_(ctx); \
} \
} else { \
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
} \
}
GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
GEN_VXRFORM(vcmpequd, 3, 3)
GEN_VXRFORM(vcmpnezb, 3, 4)
GEN_VXRFORM(vcmpnezh, 3, 5)
GEN_VXRFORM(vcmpnezw, 3, 6)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
GEN_VXRFORM(vcmpgtsd, 3, 15)
GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
GEN_VXRFORM(vcmpgtud, 3, 11)
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
GEN_VXRFORM(vcmpbfp, 3, 15)
GEN_VXRFORM(vcmpneb, 3, 0)
GEN_VXRFORM(vcmpneh, 3, 1)
GEN_VXRFORM(vcmpnew, 3, 2)
GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
vcmpneb, PPC_NONE, PPC2_ISA300)
GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
vcmpneh, PPC_NONE, PPC2_ISA300)
GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
vcmpnew, PPC_NONE, PPC2_ISA300)
GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
int simm; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
simm = SIMM5(ctx->opcode); \
tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
}
GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
#define GEN_VXFORM_NOA(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name (rd, rb); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb, rd; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(rd, rb); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
tcg_temp_free_ptr(rb); \
}
GEN_VXFORM_NOA(vupkhsb, 7, 8);
GEN_VXFORM_NOA(vupkhsh, 7, 9);
GEN_VXFORM_NOA(vupkhsw, 7, 25);
GEN_VXFORM_NOA(vupklsb, 7, 10);
GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupklsw, 7, 27);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
GEN_VXFORM_NOA(vprtybw, 1, 24);
GEN_VXFORM_NOA(vprtybd, 1, 24);
GEN_VXFORM_NOA(vprtybq, 1, 24);
static void gen_vsplt(DisasContext *ctx, int vece)
{
int uimm, dofs, bofs;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
uimm = UIMM5(ctx->opcode);
bofs = avr_full_offset(rB(ctx->opcode));
dofs = avr_full_offset(rD(ctx->opcode));
/* Experimental testing shows that hardware masks the immediate. */
bofs += (uimm << vece) & 15;
#ifndef HOST_WORDS_BIGENDIAN
bofs ^= 15;
bofs &= ~((1 << vece) - 1);
#endif
tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
}
#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb, rd; \
TCGv_i32 uimm; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb, uimm); \
tcg_temp_free_i32(uimm); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb, rd; \
uint8_t uimm = UIMM4(ctx->opcode); \
TCGv_i32 t0; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
if (uimm > splat_max) { \
uimm = 0; \
} \
t0 = tcg_temp_new_i32(); \
tcg_gen_movi_i32(t0, uimm); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(rd, rb, t0); \
tcg_temp_free_i32(t0); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
vextractub, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
vextractuh, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
vinsertb, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
vinserth, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
vinsertw, PPC_NONE, PPC2_ISA300);
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
TCGv_i32 sh;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
sh = tcg_const_i32(VSH(ctx->opcode));
gen_helper_vsldoi (rd, ra, rb, sh);
tcg_temp_free_ptr(ra);
tcg_temp_free_ptr(rb);
tcg_temp_free_ptr(rd);
tcg_temp_free_i32(sh);
}
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rc, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rc = gen_avr_ptr(rC(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
if (Rc(ctx->opcode)) { \
gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
} else { \
gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
} \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rc); \
tcg_temp_free_ptr(rd); \
}
GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
static void gen_vmladduhm(DisasContext *ctx)
{
TCGv_ptr ra, rb, rc, rd;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rc = gen_avr_ptr(rC(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
gen_helper_vmladduhm(rd, ra, rb, rc);
tcg_temp_free_ptr(ra);
tcg_temp_free_ptr(rb);
tcg_temp_free_ptr(rc);
tcg_temp_free_ptr(rd);
}
static void gen_vpermr(DisasContext *ctx)
{
TCGv_ptr ra, rb, rc, rd;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rc = gen_avr_ptr(rC(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
tcg_temp_free_ptr(ra);
tcg_temp_free_ptr(rb);
tcg_temp_free_ptr(rc);
tcg_temp_free_ptr(rd);
}
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
GEN_VXFORM_NOA(vclzb, 1, 28)
GEN_VXFORM_NOA(vclzh, 1, 29)
GEN_VXFORM_NOA(vclzw, 1, 30)
GEN_VXFORM_NOA(vclzd, 1, 31)
GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
GEN_VXFORM_NOA(vpopcntb, 1, 28)
GEN_VXFORM_NOA(vpopcnth, 1, 29)
GEN_VXFORM_NOA(vpopcntw, 1, 30)
GEN_VXFORM_NOA(vpopcntd, 1, 31)
GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM(vbpermd, 6, 23);
GEN_VXFORM(vbpermq, 6, 21);
GEN_VXFORM_NOA(vgbbd, 6, 20);
GEN_VXFORM(vpmsumb, 4, 16)
GEN_VXFORM(vpmsumh, 4, 17)
GEN_VXFORM(vpmsumw, 4, 18)
GEN_VXFORM(vpmsumd, 4, 19)
#define GEN_BCD(op) \
static void gen_##op(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rd; \
TCGv_i32 ps; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
\
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
tcg_temp_free_i32(ps); \
}
#define GEN_BCD2(op) \
static void gen_##op(DisasContext *ctx) \
{ \
TCGv_ptr rd, rb; \
TCGv_i32 ps; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, rb, ps); \
\
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
tcg_temp_free_i32(ps); \
}
GEN_BCD(bcdadd)
GEN_BCD(bcdsub)
GEN_BCD2(bcdcfn)
GEN_BCD2(bcdctn)
GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
GEN_BCD2(bcdcfsq)
GEN_BCD2(bcdctsq)
GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
GEN_BCD(bcds);
GEN_BCD(bcdus);
GEN_BCD(bcdsr);
GEN_BCD(bcdtrunc);
GEN_BCD(bcdutrunc);
static void gen_xpnd04_1(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
case 0:
gen_bcdctsq(ctx);
break;
case 2:
gen_bcdcfsq(ctx);
break;
case 4:
gen_bcdctz(ctx);
break;
case 5:
gen_bcdctn(ctx);
break;
case 6:
gen_bcdcfz(ctx);
break;
case 7:
gen_bcdcfn(ctx);
break;
case 31:
gen_bcdsetsgn(ctx);
break;
default:
gen_invalid(ctx);
break;
}
}
static void gen_xpnd04_2(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
case 0:
gen_bcdctsq(ctx);
break;
case 2:
gen_bcdcfsq(ctx);
break;
case 4:
gen_bcdctz(ctx);
break;
case 6:
gen_bcdcfz(ctx);
break;
case 7:
gen_bcdcfn(ctx);
break;
case 31:
gen_bcdsetsgn(ctx);
break;
default:
gen_invalid(ctx);
break;
}
}
GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
xpnd04_1, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
xpnd04_2, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
bcdcpsgn, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
bcds, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
bcdus, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
bcdtrunc, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
bcdtrunc, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
bcdutrunc, PPC_NONE, PPC2_ISA300)
static void gen_vsbox(DisasContext *ctx)
{
TCGv_ptr ra, rd;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
ra = gen_avr_ptr(rA(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
gen_helper_vsbox(rd, ra);
tcg_temp_free_ptr(ra);
tcg_temp_free_ptr(rd);
}
GEN_VXFORM(vcipher, 4, 20)
GEN_VXFORM(vcipherlast, 4, 20)
GEN_VXFORM(vncipher, 4, 21)
GEN_VXFORM(vncipherlast, 4, 21)
GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
#define VSHASIGMA(op) \
static void gen_##op(DisasContext *ctx) \
{ \
TCGv_ptr ra, rd; \
TCGv_i32 st_six; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
st_six = tcg_const_i32(rB(ctx->opcode)); \
gen_helper_##op(rd, ra, st_six); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rd); \
tcg_temp_free_i32(st_six); \
}
VSHASIGMA(vshasigmaw)
VSHASIGMA(vshasigmad)
GEN_VXFORM3(vpermxor, 22, 0xFF)
GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
#undef GEN_VR_STVE
#undef GEN_VX_LOGICAL
#undef GEN_VX_LOGICAL_207
#undef GEN_VXFORM
#undef GEN_VXFORM_207
#undef GEN_VXFORM_DUAL
#undef GEN_VXRFORM_DUAL
#undef GEN_VXRFORM1
#undef GEN_VXRFORM
#undef GEN_VXFORM_DUPI
#undef GEN_VXFORM_NOA
#undef GEN_VXFORM_UIMM
#undef GEN_VAFORM_PAIRED
#undef GEN_BCD2
|
pmp-tool/PMP | src/qemu/src-pmp/include/hw/ppc/xive.h | /*
* QEMU PowerPC XIVE interrupt controller model
*
*
* The POWER9 processor comes with a new interrupt controller, called
* XIVE as "eXternal Interrupt Virtualization Engine".
*
* = Overall architecture
*
*
* XIVE Interrupt Controller
* +------------------------------------+ IPIs
* | +---------+ +---------+ +--------+ | +-------+
* | |VC | |CQ | |PC |----> | CORES |
* | | esb | | | | |----> | |
* | | eas | | Bridge | | tctx |----> | |
* | |SC end | | | | nvt | | | |
* +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
* | RAM | +------------------|-----------------+ | | |
* | | | | | |
* | | | | | |
* | | +--------------------v------------------------v-v-v--+ other
* | <--+ Power Bus +--> chips
* | esb | +---------+-----------------------+------------------+
* | eas | | |
* | end | +--|------+ |
* | nvt | +----+----+ | +----+----+
* +------+ |SC | | |SC |
* | | | | |
* | PQ-bits | | | PQ-bits |
* | local |-+ | in VC |
* +---------+ +---------+
* PCIe NX,NPU,CAPI
*
* SC: Source Controller (aka. IVSE)
* VC: Virtualization Controller (aka. IVRE)
* PC: Presentation Controller (aka. IVPE)
* CQ: Common Queue (Bridge)
*
* PQ-bits: 2 bits source state machine (P:pending Q:queued)
* esb: Event State Buffer (Array of PQ bits in an IVSE)
* eas: Event Assignment Structure
* end: Event Notification Descriptor
* nvt: Notification Virtual Target
* tctx: Thread interrupt Context
*
*
* The XIVE IC is composed of three sub-engines :
*
* - Interrupt Virtualization Source Engine (IVSE), or Source
* Controller (SC). These are found in PCI PHBs, in the PSI host
* bridge controller, but also inside the main controller for the
* core IPIs and other sub-chips (NX, CAP, NPU) of the
* chip/processor. They are configured to feed the IVRE with events.
*
* - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
* Controller (VC). Its job is to match an event source with an
* Event Notification Descriptor (END).
*
* - Interrupt Virtualization Presentation Engine (IVPE) or
* Presentation Controller (PC). It maintains the interrupt context
* state of each thread and handles the delivery of the external
* exception to the thread.
*
* In XIVE 1.0, the sub-engines used to be referred as:
*
* SC Source Controller
* VC Virtualization Controller
* PC Presentation Controller
* CQ Common Queue (PowerBUS Bridge)
*
*
* = XIVE internal tables
*
* Each of the sub-engines uses a set of tables to redirect exceptions
* from event sources to CPU threads.
*
* +-------+
* User or OS | EQ |
* or +------>|entries|
* Hypervisor | | .. |
* Memory | +-------+
* | ^
* | |
* +-------------------------------------------------+
* | |
* Hypervisor +------+ +---+--+ +---+--+ +------+
* Memory | ESB | | EAT | | ENDT | | NVTT |
* (skiboot) +----+-+ +----+-+ +----+-+ +------+
* ^ | ^ | ^ | ^
* | | | | | | |
* +-------------------------------------------------+
* | | | | | | |
* | | | | | | |
* +----|--|--------|--|--------|--|-+ +-|-----+ +------+
* | | | | | | | | | | tctx| |Thread|
* IPI or --> | + v + v + v |---| + .. |-----> |
* HW events --> | | | | | |
* IVSE | IVRE | | IVPE | +------+
* +---------------------------------+ +-------+
*
*
*
* The IVSE have a 2-bits state machine, P for pending and Q for queued,
* for each source that allows events to be triggered. They are stored in
* an Event State Buffer (ESB) array and can be controlled by MMIOs.
*
* If the event is let through, the IVRE looks up in the Event Assignment
* Structure (EAS) table for an Event Notification Descriptor (END)
* configured for the source. Each Event Notification Descriptor defines
* a notification path to a CPU and an in-memory Event Queue, in which
* will be enqueued an EQ data for the OS to pull.
*
* The IVPE determines if a Notification Virtual Target (NVT) can
* handle the event by scanning the thread contexts of the VCPUs
* dispatched on the processor HW threads. It maintains the state of
* the thread interrupt context (TCTX) of each thread in a NVT table.
*
* = Acronyms
*
* Description In XIVE 1.0, used to be referred as
*
* EAS Event Assignment Structure IVE Interrupt Virt. Entry
* EAT Event Assignment Table IVT Interrupt Virt. Table
* ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table
* EQ Event Queue same
* ESB Event State Buffer SBE State Bit Entry
* NVT Notif. Virtual Target VPD Virtual Processor Desc.
* NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table
* TCTX Thread interrupt Context
*
*
* Copyright (c) 2017-2018, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*
*/
#ifndef PPC_XIVE_H
#define PPC_XIVE_H
#include "hw/qdev-core.h"
#include "hw/sysbus.h"
#include "hw/ppc/xive_regs.h"
/*
* XIVE Notifier (Interface between Source and Router)
*/
typedef struct XiveNotifier {
Object parent;
} XiveNotifier;
#define TYPE_XIVE_NOTIFIER "xive-notifier"
#define XIVE_NOTIFIER(obj) \
OBJECT_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
#define XIVE_NOTIFIER_CLASS(klass) \
OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER)
#define XIVE_NOTIFIER_GET_CLASS(obj) \
OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER)
typedef struct XiveNotifierClass {
InterfaceClass parent;
void (*notify)(XiveNotifier *xn, uint32_t lisn);
} XiveNotifierClass;
/*
* XIVE Interrupt Source
*/
#define TYPE_XIVE_SOURCE "xive-source"
#define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE)
/*
* XIVE Interrupt Source characteristics, which define how the ESB are
* controlled.
*/
#define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
#define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
typedef struct XiveSource {
DeviceState parent;
/* IRQs */
uint32_t nr_irqs;
unsigned long *lsi_map;
/* PQ bits and LSI assertion bit */
uint8_t *status;
/* ESB memory region */
uint64_t esb_flags;
uint32_t esb_shift;
MemoryRegion esb_mmio;
XiveNotifier *xive;
} XiveSource;
/*
* ESB MMIO setting. Can be one page, for both source triggering and
* source management, or two different pages. See below for magic
* values.
*/
#define XIVE_ESB_4K 12 /* PSI HB only */
#define XIVE_ESB_4K_2PAGE 13
#define XIVE_ESB_64K 16
#define XIVE_ESB_64K_2PAGE 17
static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
{
return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
}
/* The trigger page is always the first/even page */
static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
{
assert(srcno < xsrc->nr_irqs);
return (1ull << xsrc->esb_shift) * srcno;
}
/* In a two pages ESB MMIO setting, the odd page is for management */
static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
{
hwaddr addr = xive_source_esb_page(xsrc, srcno);
if (xive_source_esb_has_2page(xsrc)) {
addr += (1 << (xsrc->esb_shift - 1));
}
return addr;
}
/*
* Each interrupt source has a 2-bit state machine which can be
* controlled by MMIO. P indicates that an interrupt is pending (has
* been sent to a queue and is waiting for an EOI). Q indicates that
* the interrupt has been triggered while pending.
*
* This acts as a coalescing mechanism in order to guarantee that a
* given interrupt only occurs at most once in a queue.
*
* When doing an EOI, the Q bit will indicate if the interrupt
* needs to be re-triggered.
*/
#define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */
#define XIVE_ESB_VAL_P 0x2
#define XIVE_ESB_VAL_Q 0x1
#define XIVE_ESB_RESET 0x0
#define XIVE_ESB_PENDING XIVE_ESB_VAL_P
#define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
#define XIVE_ESB_OFF XIVE_ESB_VAL_Q
/*
* "magic" Event State Buffer (ESB) MMIO offsets.
*
* The following offsets into the ESB MMIO allow to read or manipulate
* the PQ bits. They must be used with an 8-byte load instruction.
* They all return the previous state of the interrupt (atomically).
*
* Additionally, some ESB pages support doing an EOI via a store and
* some ESBs support doing a trigger via a separate trigger page.
*/
#define XIVE_ESB_STORE_EOI 0x400 /* Store */
#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
#define XIVE_ESB_GET 0x800 /* Load */
#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
Monitor *mon);
static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
{
assert(srcno < xsrc->nr_irqs);
return test_bit(srcno, xsrc->lsi_map);
}
static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno)
{
assert(srcno < xsrc->nr_irqs);
bitmap_set(xsrc->lsi_map, srcno, 1);
}
void xive_source_set_irq(void *opaque, int srcno, int val);
/*
* XIVE Thread interrupt Management (TM) context
*/
#define TYPE_XIVE_TCTX "xive-tctx"
#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
/*
* XIVE Thread interrupt Management register rings :
*
* QW-0 User event-based exception state
* QW-1 O/S OS context for priority management, interrupt acks
* QW-2 Pool hypervisor pool context for virtual processors dispatched
* QW-3 Physical physical thread context and security context
*/
#define XIVE_TM_RING_COUNT 4
#define XIVE_TM_RING_SIZE 0x10
typedef struct XiveTCTX {
DeviceState parent_obj;
CPUState *cs;
qemu_irq output;
uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
} XiveTCTX;
/*
* XIVE Router
*/
typedef struct XiveRouter {
SysBusDevice parent;
} XiveRouter;
#define TYPE_XIVE_ROUTER "xive-router"
#define XIVE_ROUTER(obj) \
OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER)
#define XIVE_ROUTER_CLASS(klass) \
OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER)
#define XIVE_ROUTER_GET_CLASS(obj) \
OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER)
typedef struct XiveRouterClass {
SysBusDeviceClass parent;
/* XIVE table accessors */
int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
XiveEAS *eas);
int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
XiveEND *end);
int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
XiveEND *end, uint8_t word_number);
int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
} XiveRouterClass;
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
XiveEAS *eas);
int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
XiveEND *end);
int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
XiveEND *end, uint8_t word_number);
int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
/*
* XIVE END ESBs
*/
#define TYPE_XIVE_END_SOURCE "xive-end-source"
#define XIVE_END_SOURCE(obj) \
OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE)
typedef struct XiveENDSource {
DeviceState parent;
uint32_t nr_ends;
uint8_t block_id;
/* ESB memory region */
uint32_t esb_shift;
MemoryRegion esb_mmio;
XiveRouter *xrtr;
} XiveENDSource;
/*
* For legacy compatibility, the exceptions define up to 256 different
* priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
* and the least favored level 0xFF.
*/
#define XIVE_PRIORITY_MAX 7
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
/*
* XIVE Thread Interrupt Management Aera (TIMA)
*
* This region gives access to the registers of the thread interrupt
* management context. It is four page wide, each page providing a
* different view of the registers. The page with the lower offset is
* the most privileged and gives access to the entire context.
*/
#define XIVE_TM_HW_PAGE 0x0
#define XIVE_TM_HV_PAGE 0x1
#define XIVE_TM_OS_PAGE 0x2
#define XIVE_TM_USER_PAGE 0x3
extern const MemoryRegionOps xive_tm_ops;
void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
unsigned size);
uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
{
return (nvt_blk << 19) | nvt_idx;
}
#endif /* PPC_XIVE_H */
|
pmp-tool/PMP | src/qemu/src-pmp/disas.c | /* General "disassemble this chunk" code. Used for debugging. */
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "disas/bfd.h"
#include "elf.h"
#include "cpu.h"
#include "disas/disas.h"
#include "disas/capstone.h"
typedef struct CPUDebug {
struct disassemble_info info;
CPUState *cpu;
} CPUDebug;
/* Filled in by elfload.c. Simplistic, but will do for now. */
struct syminfo *syminfos = NULL;
/* Get LENGTH bytes from info's buffer, at target address memaddr.
Transfer them to myaddr. */
int
buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
struct disassemble_info *info)
{
if (memaddr < info->buffer_vma
|| memaddr + length > info->buffer_vma + info->buffer_length)
/* Out of bounds. Use EIO because GDB uses it. */
return EIO;
memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
return 0;
}
/* Get LENGTH bytes from info's buffer, at target address memaddr.
Transfer them to myaddr. */
static int
target_read_memory (bfd_vma memaddr,
bfd_byte *myaddr,
int length,
struct disassemble_info *info)
{
CPUDebug *s = container_of(info, CPUDebug, info);
cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
return 0;
}
/* Print an error message. We can assume that this is in response to
an error return from buffer_read_memory. */
void
perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info)
{
if (status != EIO)
/* Can't happen. */
(*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
else
/* Actually, address between memaddr and memaddr + len was
out of bounds. */
(*info->fprintf_func) (info->stream,
"Address 0x%" PRIx64 " is out of bounds.\n", memaddr);
}
/* This could be in a separate file, to save minuscule amounts of space
in statically linked executables. */
/* Just print the address is hex. This is included for completeness even
though both GDB and objdump provide their own (to print symbolic
addresses). */
void
generic_print_address (bfd_vma addr, struct disassemble_info *info)
{
(*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
}
/* Print address in hex, truncated to the width of a host virtual address. */
static void
generic_print_host_address(bfd_vma addr, struct disassemble_info *info)
{
uint64_t mask = ~0ULL >> (64 - (sizeof(void *) * 8));
generic_print_address(addr & mask, info);
}
/* Just return the given address. */
int
generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info)
{
return 1;
}
bfd_vma bfd_getl64 (const bfd_byte *addr)
{
unsigned long long v;
v = (unsigned long long) addr[0];
v |= (unsigned long long) addr[1] << 8;
v |= (unsigned long long) addr[2] << 16;
v |= (unsigned long long) addr[3] << 24;
v |= (unsigned long long) addr[4] << 32;
v |= (unsigned long long) addr[5] << 40;
v |= (unsigned long long) addr[6] << 48;
v |= (unsigned long long) addr[7] << 56;
return (bfd_vma) v;
}
bfd_vma bfd_getl32 (const bfd_byte *addr)
{
unsigned long v;
v = (unsigned long) addr[0];
v |= (unsigned long) addr[1] << 8;
v |= (unsigned long) addr[2] << 16;
v |= (unsigned long) addr[3] << 24;
return (bfd_vma) v;
}
bfd_vma bfd_getb32 (const bfd_byte *addr)
{
unsigned long v;
v = (unsigned long) addr[0] << 24;
v |= (unsigned long) addr[1] << 16;
v |= (unsigned long) addr[2] << 8;
v |= (unsigned long) addr[3];
return (bfd_vma) v;
}
bfd_vma bfd_getl16 (const bfd_byte *addr)
{
unsigned long v;
v = (unsigned long) addr[0];
v |= (unsigned long) addr[1] << 8;
return (bfd_vma) v;
}
bfd_vma bfd_getb16 (const bfd_byte *addr)
{
unsigned long v;
v = (unsigned long) addr[0] << 24;
v |= (unsigned long) addr[1] << 16;
return (bfd_vma) v;
}
static int print_insn_objdump(bfd_vma pc, disassemble_info *info,
const char *prefix)
{
int i, n = info->buffer_length;
uint8_t *buf = g_malloc(n);
info->read_memory_func(pc, buf, n, info);
for (i = 0; i < n; ++i) {
if (i % 32 == 0) {
info->fprintf_func(info->stream, "\n%s: ", prefix);
}
info->fprintf_func(info->stream, "%02x", buf[i]);
}
g_free(buf);
return n;
}
static int print_insn_od_host(bfd_vma pc, disassemble_info *info)
{
return print_insn_objdump(pc, info, "OBJD-H");
}
static int print_insn_od_target(bfd_vma pc, disassemble_info *info)
{
return print_insn_objdump(pc, info, "OBJD-T");
}
#ifdef CONFIG_CAPSTONE
/* Temporary storage for the capstone library. This will be alloced via
malloc with a size private to the library; thus there's no reason not
to share this across calls and across host vs target disassembly. */
static __thread cs_insn *cap_insn;
/* Initialize the Capstone library. */
/* ??? It would be nice to cache this. We would need one handle for the
host and one for the target. For most targets we can reset specific
parameters via cs_option(CS_OPT_MODE, new_mode), but we cannot change
CS_ARCH_* in this way. Thus we would need to be able to close and
re-open the target handle with a different arch for the target in order
to handle AArch64 vs AArch32 mode switching. */
static cs_err cap_disas_start(disassemble_info *info, csh *handle)
{
cs_mode cap_mode = info->cap_mode;
cs_err err;
cap_mode += (info->endian == BFD_ENDIAN_BIG ? CS_MODE_BIG_ENDIAN
: CS_MODE_LITTLE_ENDIAN);
err = cs_open(info->cap_arch, cap_mode, handle);
if (err != CS_ERR_OK) {
return err;
}
/* ??? There probably ought to be a better place to put this. */
if (info->cap_arch == CS_ARCH_X86) {
/* We don't care about errors (if for some reason the library
is compiled without AT&T syntax); the user will just have
to deal with the Intel syntax. */
cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
}
/* "Disassemble" unknown insns as ".byte W,X,Y,Z". */
cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON);
/* Allocate temp space for cs_disasm_iter. */
if (cap_insn == NULL) {
cap_insn = cs_malloc(*handle);
if (cap_insn == NULL) {
cs_close(handle);
return CS_ERR_MEM;
}
}
return CS_ERR_OK;
}
static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn,
int i, int n)
{
fprintf_function print = info->fprintf_func;
FILE *stream = info->stream;
switch (info->cap_insn_unit) {
case 4:
if (info->endian == BFD_ENDIAN_BIG) {
for (; i < n; i += 4) {
print(stream, " %08x", ldl_be_p(insn->bytes + i));
}
} else {
for (; i < n; i += 4) {
print(stream, " %08x", ldl_le_p(insn->bytes + i));
}
}
break;
case 2:
if (info->endian == BFD_ENDIAN_BIG) {
for (; i < n; i += 2) {
print(stream, " %04x", lduw_be_p(insn->bytes + i));
}
} else {
for (; i < n; i += 2) {
print(stream, " %04x", lduw_le_p(insn->bytes + i));
}
}
break;
default:
for (; i < n; i++) {
print(stream, " %02x", insn->bytes[i]);
}
break;
}
}
static void cap_dump_insn(disassemble_info *info, cs_insn *insn)
{
fprintf_function print = info->fprintf_func;
int i, n, split;
print(info->stream, "0x%08" PRIx64 ": ", insn->address);
n = insn->size;
split = info->cap_insn_split;
/* Dump the first SPLIT bytes of the instruction. */
cap_dump_insn_units(info, insn, 0, MIN(n, split));
/* Add padding up to SPLIT so that mnemonics line up. */
if (n < split) {
int width = (split - n) / info->cap_insn_unit;
width *= (2 * info->cap_insn_unit + 1);
print(info->stream, "%*s", width, "");
}
/* Print the actual instruction. */
print(info->stream, " %-8s %s\n", insn->mnemonic, insn->op_str);
/* Dump any remaining part of the insn on subsequent lines. */
for (i = split; i < n; i += split) {
print(info->stream, "0x%08" PRIx64 ": ", insn->address + i);
cap_dump_insn_units(info, insn, i, MIN(n, i + split));
print(info->stream, "\n");
}
}
/* Disassemble SIZE bytes at PC for the target. */
static bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size)
{
uint8_t cap_buf[1024];
csh handle;
cs_insn *insn;
size_t csize = 0;
if (cap_disas_start(info, &handle) != CS_ERR_OK) {
return false;
}
insn = cap_insn;
while (1) {
size_t tsize = MIN(sizeof(cap_buf) - csize, size);
const uint8_t *cbuf = cap_buf;
target_read_memory(pc + csize, cap_buf + csize, tsize, info);
csize += tsize;
size -= tsize;
while (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
cap_dump_insn(info, insn);
}
/* If the target memory is not consumed, go back for more... */
if (size != 0) {
/* ... taking care to move any remaining fractional insn
to the beginning of the buffer. */
if (csize != 0) {
memmove(cap_buf, cbuf, csize);
}
continue;
}
/* Since the target memory is consumed, we should not have
a remaining fractional insn. */
if (csize != 0) {
(*info->fprintf_func)(info->stream,
"Disassembler disagrees with translator "
"over instruction decoding\n"
"Please report this to <EMAIL>\n");
}
break;
}
cs_close(&handle);
return true;
}
/* Disassemble SIZE bytes at CODE for the host. */
static bool cap_disas_host(disassemble_info *info, void *code, size_t size)
{
csh handle;
const uint8_t *cbuf;
cs_insn *insn;
uint64_t pc;
if (cap_disas_start(info, &handle) != CS_ERR_OK) {
return false;
}
insn = cap_insn;
cbuf = code;
pc = (uintptr_t)code;
while (cs_disasm_iter(handle, &cbuf, &size, &pc, insn)) {
cap_dump_insn(info, insn);
}
if (size != 0) {
(*info->fprintf_func)(info->stream,
"Disassembler disagrees with TCG over instruction encoding\n"
"Please report this to <EMAIL>\n");
}
cs_close(&handle);
return true;
}
#if !defined(CONFIG_USER_ONLY)
/* Disassemble COUNT insns at PC for the target. */
static bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
{
uint8_t cap_buf[32];
csh handle;
cs_insn *insn;
size_t csize = 0;
if (cap_disas_start(info, &handle) != CS_ERR_OK) {
return false;
}
insn = cap_insn;
while (1) {
/* We want to read memory for one insn, but generically we do not
know how much memory that is. We have a small buffer which is
known to be sufficient for all supported targets. Try to not
read beyond the page, Just In Case. For even more simplicity,
ignore the actual target page size and use a 1k boundary. If
that turns out to be insufficient, we'll come back around the
loop and read more. */
uint64_t epc = QEMU_ALIGN_UP(pc + csize + 1, 1024);
size_t tsize = MIN(sizeof(cap_buf) - csize, epc - pc);
const uint8_t *cbuf = cap_buf;
/* Make certain that we can make progress. */
assert(tsize != 0);
info->read_memory_func(pc, cap_buf + csize, tsize, info);
csize += tsize;
if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
cap_dump_insn(info, insn);
if (--count <= 0) {
break;
}
}
memmove(cap_buf, cbuf, csize);
}
cs_close(&handle);
return true;
}
#endif /* !CONFIG_USER_ONLY */
#else
# define cap_disas_target(i, p, s) false
# define cap_disas_host(i, p, s) false
# define cap_disas_monitor(i, p, c) false
#endif /* CONFIG_CAPSTONE */
/* Disassemble this for me please... (debugging). */
void target_disas(FILE *out, CPUState *cpu, target_ulong code,
target_ulong size)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
target_ulong pc;
int count;
CPUDebug s;
INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
s.cpu = cpu;
s.info.read_memory_func = target_read_memory;
s.info.buffer_vma = code;
s.info.buffer_length = size;
s.info.print_address_func = generic_print_address;
s.info.cap_arch = -1;
s.info.cap_mode = 0;
s.info.cap_insn_unit = 4;
s.info.cap_insn_split = 4;
#ifdef TARGET_WORDS_BIGENDIAN
s.info.endian = BFD_ENDIAN_BIG;
#else
s.info.endian = BFD_ENDIAN_LITTLE;
#endif
if (cc->disas_set_info) {
cc->disas_set_info(cpu, &s.info);
}
if (s.info.cap_arch >= 0 && cap_disas_target(&s.info, code, size)) {
return;
}
if (s.info.print_insn == NULL) {
s.info.print_insn = print_insn_od_target;
}
for (pc = code; size > 0; pc += count, size -= count) {
fprintf(out, "0x" TARGET_FMT_lx ": ", pc);
count = s.info.print_insn(pc, &s.info);
fprintf(out, "\n");
if (count < 0)
break;
if (size < count) {
fprintf(out,
"Disassembler disagrees with translator over instruction "
"decoding\n"
"Please report this to <EMAIL>\n");
break;
}
}
}
/* Disassemble this for me please... (debugging). */
void disas(FILE *out, void *code, unsigned long size)
{
uintptr_t pc;
int count;
CPUDebug s;
int (*print_insn)(bfd_vma pc, disassemble_info *info) = NULL;
INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
s.info.print_address_func = generic_print_host_address;
s.info.buffer = code;
s.info.buffer_vma = (uintptr_t)code;
s.info.buffer_length = size;
s.info.cap_arch = -1;
s.info.cap_mode = 0;
s.info.cap_insn_unit = 4;
s.info.cap_insn_split = 4;
#ifdef HOST_WORDS_BIGENDIAN
s.info.endian = BFD_ENDIAN_BIG;
#else
s.info.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(CONFIG_TCG_INTERPRETER)
print_insn = print_insn_tci;
#elif defined(__i386__)
s.info.mach = bfd_mach_i386_i386;
print_insn = print_insn_i386;
s.info.cap_arch = CS_ARCH_X86;
s.info.cap_mode = CS_MODE_32;
s.info.cap_insn_unit = 1;
s.info.cap_insn_split = 8;
#elif defined(__x86_64__)
s.info.mach = bfd_mach_x86_64;
print_insn = print_insn_i386;
s.info.cap_arch = CS_ARCH_X86;
s.info.cap_mode = CS_MODE_64;
s.info.cap_insn_unit = 1;
s.info.cap_insn_split = 8;
#elif defined(_ARCH_PPC)
s.info.disassembler_options = (char *)"any";
print_insn = print_insn_ppc;
s.info.cap_arch = CS_ARCH_PPC;
# ifdef _ARCH_PPC64
s.info.cap_mode = CS_MODE_64;
# endif
#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
#if defined(_ILP32) || (__riscv_xlen == 32)
print_insn = print_insn_riscv32;
#elif defined(_LP64)
print_insn = print_insn_riscv64;
#else
#error unsupported RISC-V ABI
#endif
#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
print_insn = print_insn_arm_a64;
s.info.cap_arch = CS_ARCH_ARM64;
#elif defined(__alpha__)
print_insn = print_insn_alpha;
#elif defined(__sparc__)
print_insn = print_insn_sparc;
s.info.mach = bfd_mach_sparc_v9b;
#elif defined(__arm__)
print_insn = print_insn_arm;
s.info.cap_arch = CS_ARCH_ARM;
/* TCG only generates code for arm mode. */
#elif defined(__MIPSEB__)
print_insn = print_insn_big_mips;
#elif defined(__MIPSEL__)
print_insn = print_insn_little_mips;
#elif defined(__m68k__)
print_insn = print_insn_m68k;
#elif defined(__s390__)
print_insn = print_insn_s390;
#elif defined(__hppa__)
print_insn = print_insn_hppa;
#endif
if (s.info.cap_arch >= 0 && cap_disas_host(&s.info, code, size)) {
return;
}
if (print_insn == NULL) {
print_insn = print_insn_od_host;
}
for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
fprintf(out, "0x%08" PRIxPTR ": ", pc);
count = print_insn(pc, &s.info);
fprintf(out, "\n");
if (count < 0)
break;
}
}
/* Look up symbol for debugging purpose. Returns "" if unknown. */
const char *lookup_symbol(target_ulong orig_addr)
{
const char *symbol = "";
struct syminfo *s;
for (s = syminfos; s; s = s->next) {
symbol = s->lookup_symbol(s, orig_addr);
if (symbol[0] != '\0') {
break;
}
}
return symbol;
}
#if !defined(CONFIG_USER_ONLY)
#include "monitor/monitor.h"
static int
physical_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
struct disassemble_info *info)
{
CPUDebug *s = container_of(info, CPUDebug, info);
address_space_read(s->cpu->as, memaddr, MEMTXATTRS_UNSPECIFIED,
myaddr, length);
return 0;
}
/* Disassembler for the monitor. */
void monitor_disas(Monitor *mon, CPUState *cpu,
target_ulong pc, int nb_insn, int is_physical)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
int count, i;
CPUDebug s;
INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf);
s.cpu = cpu;
s.info.read_memory_func
= (is_physical ? physical_read_memory : target_read_memory);
s.info.print_address_func = generic_print_address;
s.info.buffer_vma = pc;
s.info.cap_arch = -1;
s.info.cap_mode = 0;
s.info.cap_insn_unit = 4;
s.info.cap_insn_split = 4;
#ifdef TARGET_WORDS_BIGENDIAN
s.info.endian = BFD_ENDIAN_BIG;
#else
s.info.endian = BFD_ENDIAN_LITTLE;
#endif
if (cc->disas_set_info) {
cc->disas_set_info(cpu, &s.info);
}
if (s.info.cap_arch >= 0 && cap_disas_monitor(&s.info, pc, nb_insn)) {
return;
}
if (!s.info.print_insn) {
monitor_printf(mon, "0x" TARGET_FMT_lx
": Asm output not supported on this arch\n", pc);
return;
}
for(i = 0; i < nb_insn; i++) {
monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
count = s.info.print_insn(pc, &s.info);
monitor_printf(mon, "\n");
if (count < 0)
break;
pc += count;
}
}
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/target/ppc/monitor.c | <gh_stars>1-10
/*
* QEMU monitor
*
* Copyright (c) 2003-2004 <NAME>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
#include "hmp.h"
static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
{
CPUArchState *env = mon_get_cpu_env();
unsigned int u;
int i;
u = 0;
for (i = 0; i < 8; i++)
u |= env->crf[i] << (32 - (4 * (i + 1)));
return u;
}
static target_long monitor_get_decr (const struct MonitorDef *md, int val)
{
CPUArchState *env = mon_get_cpu_env();
return cpu_ppc_load_decr(env);
}
static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
{
CPUArchState *env = mon_get_cpu_env();
return cpu_ppc_load_tbu(env);
}
static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
{
CPUArchState *env = mon_get_cpu_env();
return cpu_ppc_load_tbl(env);
}
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env1 = mon_get_cpu_env();
if (!env1) {
monitor_printf(mon, "No CPU available\n");
return;
}
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
}
const MonitorDef monitor_defs[] = {
{ "fpscr", offsetof(CPUPPCState, fpscr) },
/* Next instruction pointer */
{ "nip|pc", offsetof(CPUPPCState, nip) },
{ "lr", offsetof(CPUPPCState, lr) },
{ "ctr", offsetof(CPUPPCState, ctr) },
{ "decr", 0, &monitor_get_decr, },
{ "ccr|cr", 0, &monitor_get_ccr, },
/* Machine state register */
{ "xer", offsetof(CPUPPCState, xer) },
{ "msr", offsetof(CPUPPCState, msr) },
{ "tbu", 0, &monitor_get_tbu, },
{ "tbl", 0, &monitor_get_tbl, },
{ NULL },
};
const MonitorDef *target_monitor_defs(void)
{
return monitor_defs;
}
static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
{
int regnum;
char *endptr = NULL;
if (!*numstr) {
return false;
}
regnum = strtoul(numstr, &endptr, 10);
if (*endptr || (regnum >= maxnum)) {
return false;
}
*pregnum = regnum;
return true;
}
int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
{
int i, regnum;
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
/* General purpose registers */
if ((qemu_tolower(name[0]) == 'r') &&
ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) {
*pval = env->gpr[regnum];
return 0;
}
/* Floating point registers */
if ((qemu_tolower(name[0]) == 'f') &&
ppc_cpu_get_reg_num(name + 1, 32, ®num)) {
*pval = *cpu_fpr_ptr(env, regnum);
return 0;
}
/* Special purpose registers */
for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
ppc_spr_t *spr = &env->spr_cb[i];
if (spr->name && (strcasecmp(name, spr->name) == 0)) {
*pval = env->spr[i];
return 0;
}
}
/* Segment registers */
#if !defined(CONFIG_USER_ONLY)
if ((strncasecmp(name, "sr", 2) == 0) &&
ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) {
*pval = env->sr[regnum];
return 0;
}
#endif
return -EINVAL;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/arm/musca.c | <reponame>pmp-tool/PMP
/*
* Arm Musca-B1 test chip board emulation
*
* Copyright (c) 2019 Linaro Limited
* Written by <NAME>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* The Musca boards are a reference implementation of a system using
* the SSE-200 subsystem for embedded:
* https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board
* https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
* We model the A and B1 variants of this board, as described in the TRMs:
* http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/index.html
* http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/index.html
*/
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/arm/arm.h"
#include "hw/arm/armsse.h"
#include "hw/boards.h"
#include "hw/char/pl011.h"
#include "hw/core/split-irq.h"
#include "hw/misc/tz-mpc.h"
#include "hw/misc/tz-ppc.h"
#include "hw/misc/unimp.h"
#include "hw/timer/pl031.h"
#define MUSCA_NUMIRQ_MAX 96
#define MUSCA_PPC_MAX 3
#define MUSCA_MPC_MAX 5
typedef struct MPCInfo MPCInfo;
typedef enum MuscaType {
MUSCA_A,
MUSCA_B1,
} MuscaType;
typedef struct {
MachineClass parent;
MuscaType type;
uint32_t init_svtor;
int sram_addr_width;
int num_irqs;
const MPCInfo *mpc_info;
int num_mpcs;
} MuscaMachineClass;
typedef struct {
MachineState parent;
ARMSSE sse;
/* RAM and flash */
MemoryRegion ram[MUSCA_MPC_MAX];
SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX];
SplitIRQ sec_resp_splitter;
TZPPC ppc[MUSCA_PPC_MAX];
MemoryRegion container;
UnimplementedDeviceState eflash[2];
UnimplementedDeviceState qspi;
TZMPC mpc[MUSCA_MPC_MAX];
UnimplementedDeviceState mhu[2];
UnimplementedDeviceState pwm[3];
UnimplementedDeviceState i2s;
PL011State uart[2];
UnimplementedDeviceState i2c[2];
UnimplementedDeviceState spi;
UnimplementedDeviceState scc;
UnimplementedDeviceState timer;
PL031State rtc;
UnimplementedDeviceState pvt;
UnimplementedDeviceState sdio;
UnimplementedDeviceState gpio;
UnimplementedDeviceState cryptoisland;
} MuscaMachineState;
#define TYPE_MUSCA_MACHINE "musca"
#define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a")
#define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1")
#define MUSCA_MACHINE(obj) \
OBJECT_CHECK(MuscaMachineState, obj, TYPE_MUSCA_MACHINE)
#define MUSCA_MACHINE_GET_CLASS(obj) \
OBJECT_GET_CLASS(MuscaMachineClass, obj, TYPE_MUSCA_MACHINE)
#define MUSCA_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(MuscaMachineClass, klass, TYPE_MUSCA_MACHINE)
/*
* Main SYSCLK frequency in Hz
* TODO this should really be different for the two cores, but we
* don't model that in our SSE-200 model yet.
*/
#define SYSCLK_FRQ 40000000
static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
{
/* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
assert(irqno < MUSCA_NUMIRQ_MAX);
return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
}
/*
* Most of the devices in the Musca board sit behind Peripheral Protection
* Controllers. These data structures define the layout of which devices
* sit behind which PPCs.
* The devfn for each port is a function which creates, configures
* and initializes the device, returning the MemoryRegion which
* needs to be plugged into the downstream end of the PPC port.
*/
typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque,
const char *name, hwaddr size);
typedef struct PPCPortInfo {
const char *name;
MakeDevFn *devfn;
void *opaque;
hwaddr addr;
hwaddr size;
} PPCPortInfo;
typedef struct PPCInfo {
const char *name;
PPCPortInfo ports[TZ_NUM_PORTS];
} PPCInfo;
static MemoryRegion *make_unimp_dev(MuscaMachineState *mms,
void *opaque, const char *name, hwaddr size)
{
/*
* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
* and return a pointer to its MemoryRegion.
*/
UnimplementedDeviceState *uds = opaque;
sysbus_init_child_obj(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
}
typedef enum MPCInfoType {
MPC_RAM,
MPC_ROM,
MPC_CRYPTOISLAND,
} MPCInfoType;
struct MPCInfo {
const char *name;
hwaddr addr;
hwaddr size;
MPCInfoType type;
};
/* Order of the MPCs here must match the order of the bits in SECMPCINTSTATUS */
static const MPCInfo a_mpc_info[] = { {
.name = "qspi",
.type = MPC_ROM,
.addr = 0x00200000,
.size = 0x00800000,
}, {
.name = "sram",
.type = MPC_RAM,
.addr = 0x00000000,
.size = 0x00200000,
}
};
static const MPCInfo b1_mpc_info[] = { {
.name = "qspi",
.type = MPC_ROM,
.addr = 0x00000000,
.size = 0x02000000,
}, {
.name = "sram",
.type = MPC_RAM,
.addr = 0x0a400000,
.size = 0x00080000,
}, {
.name = "eflash0",
.type = MPC_ROM,
.addr = 0x0a000000,
.size = 0x00200000,
}, {
.name = "eflash1",
.type = MPC_ROM,
.addr = 0x0a200000,
.size = 0x00200000,
}, {
.name = "cryptoisland",
.type = MPC_CRYPTOISLAND,
.addr = 0x0a000000,
.size = 0x00200000,
}
};
static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
/*
* Create an MPC and the RAM or flash behind it.
* MPC 0: eFlash 0
* MPC 1: eFlash 1
* MPC 2: SRAM
* MPC 3: QSPI flash
* MPC 4: CryptoIsland
* For now we implement the flash regions as ROM (ie not programmable)
* (with their control interface memory regions being unimplemented
* stubs behind the PPCs).
* The whole CryptoIsland region behind its MPC is an unimplemented stub.
*/
MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
TZMPC *mpc = opaque;
int i = mpc - &mms->mpc[0];
MemoryRegion *downstream;
MemoryRegion *upstream;
UnimplementedDeviceState *uds;
char *mpcname;
const MPCInfo *mpcinfo = mmc->mpc_info;
mpcname = g_strdup_printf("%s-mpc", mpcinfo[i].name);
switch (mpcinfo[i].type) {
case MPC_ROM:
downstream = &mms->ram[i];
memory_region_init_rom(downstream, NULL, mpcinfo[i].name,
mpcinfo[i].size, &error_fatal);
break;
case MPC_RAM:
downstream = &mms->ram[i];
memory_region_init_ram(downstream, NULL, mpcinfo[i].name,
mpcinfo[i].size, &error_fatal);
break;
case MPC_CRYPTOISLAND:
/* We don't implement the CryptoIsland yet */
uds = &mms->cryptoisland;
sysbus_init_child_obj(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name);
qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
break;
default:
g_assert_not_reached();
}
sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->mpc[0]),
TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(downstream),
"downstream", &error_fatal);
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
/* Map the upstream end of the MPC into system memory */
upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream);
/* and connect its interrupt to the SSE-200 */
qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
qdev_get_gpio_in_named(DEVICE(&mms->sse),
"mpcexp_status", i));
g_free(mpcname);
/* Return the register interface MR for our caller to map behind the PPC */
return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
}
static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
PL031State *rtc = opaque;
sysbus_init_child_obj(OBJECT(mms), name, rtc, sizeof(mms->rtc), TYPE_PL031);
object_property_set_bool(OBJECT(rtc), true, "realized", &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39));
return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0);
}
static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
PL011State *uart = opaque;
int i = uart - &mms->uart[0];
int irqbase = 7 + i * 6;
SysBusDevice *s;
sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
TYPE_PL011);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */
sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */
sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */
sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */
sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
}
static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
/*
* Create the container MemoryRegion for all the devices that live
* behind the Musca-A PPC's single port. These devices don't have a PPC
* port each, but we use the PPCPortInfo struct as a convenient way
* to describe them. Note that addresses here are relative to the base
* address of the PPC port region: 0x40100000, and devices appear both
* at the 0x4... NS region and the 0x5... S region.
*/
int i;
MemoryRegion *container = &mms->container;
const PPCPortInfo devices[] = {
{ "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 },
{ "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 },
{ "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 },
{ "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 },
{ "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 },
{ "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 },
{ "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 },
{ "rtc", make_rtc, &mms->rtc, 0x8000, 0x1000 },
{ "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 },
{ "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 },
{ "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 },
{ "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 },
{ "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 },
{ "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 },
{ "mpc0", make_mpc, &mms->mpc[0], 0x12000, 0x1000 },
{ "mpc1", make_mpc, &mms->mpc[1], 0x13000, 0x1000 },
};
memory_region_init(container, OBJECT(mms), "musca-device-container", size);
for (i = 0; i < ARRAY_SIZE(devices); i++) {
const PPCPortInfo *pinfo = &devices[i];
MemoryRegion *mr;
mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
memory_region_add_subregion(container, pinfo->addr, mr);
}
return &mms->container;
}
static void musca_init(MachineState *machine)
{
MuscaMachineState *mms = MUSCA_MACHINE(machine);
MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *system_memory = get_system_memory();
DeviceState *ssedev;
DeviceState *dev_splitter;
const PPCInfo *ppcs;
int num_ppcs;
int i;
assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX);
assert(mmc->num_mpcs <= MUSCA_MPC_MAX);
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with CPU %s",
mc->default_cpu_type);
exit(1);
}
sysbus_init_child_obj(OBJECT(machine), "sse-200", &mms->sse,
sizeof(mms->sse), TYPE_SSE200);
ssedev = DEVICE(&mms->sse);
object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory),
"memory", &error_fatal);
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ);
object_property_set_bool(OBJECT(&mms->sse), true, "realized",
&error_fatal);
/*
* We need to create splitters to feed the IRQ inputs
* for each CPU in the SSE-200 from each device in the board.
*/
for (i = 0; i < mmc->num_irqs; i++) {
char *name = g_strdup_printf("musca-irq-splitter%d", i);
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
object_initialize_child(OBJECT(machine), name,
splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_fatal, NULL);
g_free(name);
object_property_set_int(OBJECT(splitter), 2, "num-lines",
&error_fatal);
object_property_set_bool(OBJECT(splitter), true, "realized",
&error_fatal);
qdev_connect_gpio_out(DEVICE(splitter), 0,
qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i));
qdev_connect_gpio_out(DEVICE(splitter), 1,
qdev_get_gpio_in_named(ssedev,
"EXP_CPU1_IRQ", i));
}
/*
* The sec_resp_cfg output from the SSE-200 must be split into multiple
* lines, one for each of the PPCs we create here.
*/
object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
TYPE_SPLIT_IRQ);
object_property_add_child(OBJECT(machine), "sec-resp-splitter",
OBJECT(&mms->sec_resp_splitter), &error_fatal);
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal);
object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
"realized", &error_fatal);
dev_splitter = DEVICE(&mms->sec_resp_splitter);
qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
/*
* Most of the devices in the board are behind Peripheral Protection
* Controllers. The required order for initializing things is:
* + initialize the PPC
* + initialize, configure and realize downstream devices
* + connect downstream device MemoryRegions to the PPC
* + realize the PPC
* + map the PPC's MemoryRegions to the places in the address map
* where the downstream devices should appear
* + wire up the PPC's control lines to the SSE object
*
* The PPC mapping differs for the -A and -B1 variants; the -A version
* is much simpler, using only a single port of a single PPC and putting
* all the devices behind that.
*/
const PPCInfo a_ppcs[] = { {
.name = "ahb_ppcexp0",
.ports = {
{ "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100000 },
},
},
};
/*
* Devices listed with an 0x4.. address appear in both the NS 0x4.. region
* and the 0x5.. S region. Devices listed with an 0x5.. address appear
* only in the S region.
*/
const PPCInfo b1_ppcs[] = { {
.name = "apb_ppcexp0",
.ports = {
{ "eflash0", make_unimp_dev, &mms->eflash[0],
0x52400000, 0x1000 },
{ "eflash1", make_unimp_dev, &mms->eflash[1],
0x52500000, 0x1000 },
{ "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000 },
{ "mpc0", make_mpc, &mms->mpc[0], 0x52000000, 0x1000 },
{ "mpc1", make_mpc, &mms->mpc[1], 0x52100000, 0x1000 },
{ "mpc2", make_mpc, &mms->mpc[2], 0x52200000, 0x1000 },
{ "mpc3", make_mpc, &mms->mpc[3], 0x52300000, 0x1000 },
{ "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 },
{ "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 },
{ }, /* port 9: unused */
{ }, /* port 10: unused */
{ }, /* port 11: unused */
{ }, /* port 12: unused */
{ }, /* port 13: unused */
{ "mpc4", make_mpc, &mms->mpc[4], 0x52e00000, 0x1000 },
},
}, {
.name = "apb_ppcexp1",
.ports = {
{ "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 },
{ "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 },
{ "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 },
{ "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 },
{ "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 },
{ "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 },
{ "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 },
{ "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 },
{ "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 },
{ "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 },
{ "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000 },
{ "rtc", make_rtc, &mms->rtc, 0x4010d000, 0x1000 },
{ "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 },
{ "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 },
},
}, {
.name = "ahb_ppcexp0",
.ports = {
{ }, /* port 0: unused */
{ "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 },
},
},
};
switch (mmc->type) {
case MUSCA_A:
ppcs = a_ppcs;
num_ppcs = ARRAY_SIZE(a_ppcs);
break;
case MUSCA_B1:
ppcs = b1_ppcs;
num_ppcs = ARRAY_SIZE(b1_ppcs);
break;
default:
g_assert_not_reached();
}
assert(num_ppcs <= MUSCA_PPC_MAX);
for (i = 0; i < num_ppcs; i++) {
const PPCInfo *ppcinfo = &ppcs[i];
TZPPC *ppc = &mms->ppc[i];
DeviceState *ppcdev;
int port;
char *gpioname;
sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
sizeof(TZPPC), TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {
const PPCPortInfo *pinfo = &ppcinfo->ports[port];
MemoryRegion *mr;
char *portname;
if (!pinfo->devfn) {
continue;
}
mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
portname = g_strdup_printf("port[%d]", port);
object_property_set_link(OBJECT(ppc), OBJECT(mr),
portname, &error_fatal);
g_free(portname);
}
object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
for (port = 0; port < TZ_NUM_PORTS; port++) {
const PPCPortInfo *pinfo = &ppcinfo->ports[port];
if (!pinfo->devfn) {
continue;
}
sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
qdev_connect_gpio_out_named(ssedev, gpioname, port,
qdev_get_gpio_in_named(ppcdev,
"cfg_nonsec",
port));
g_free(gpioname);
gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
qdev_connect_gpio_out_named(ssedev, gpioname, port,
qdev_get_gpio_in_named(ppcdev,
"cfg_ap", port));
g_free(gpioname);
}
gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
qdev_connect_gpio_out_named(ssedev, gpioname, 0,
qdev_get_gpio_in_named(ppcdev,
"irq_enable", 0));
g_free(gpioname);
gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
qdev_connect_gpio_out_named(ssedev, gpioname, 0,
qdev_get_gpio_in_named(ppcdev,
"irq_clear", 0));
g_free(gpioname);
gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
qdev_connect_gpio_out_named(ppcdev, "irq", 0,
qdev_get_gpio_in_named(ssedev,
gpioname, 0));
g_free(gpioname);
qdev_connect_gpio_out(dev_splitter, i,
qdev_get_gpio_in_named(ppcdev,
"cfg_sec_resp", 0));
}
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x2000000);
}
static void musca_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->default_cpus = 2;
mc->min_cpus = mc->default_cpus;
mc->max_cpus = mc->default_cpus;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mc->init = musca_init;
}
static void musca_a_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
mc->desc = "ARM Musca-A board (dual Cortex-M33)";
mmc->type = MUSCA_A;
mmc->init_svtor = 0x10200000;
mmc->sram_addr_width = 15;
mmc->num_irqs = 64;
mmc->mpc_info = a_mpc_info;
mmc->num_mpcs = ARRAY_SIZE(a_mpc_info);
}
static void musca_b1_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
mc->desc = "ARM Musca-B1 board (dual Cortex-M33)";
mmc->type = MUSCA_B1;
/*
* This matches the DAPlink firmware which boots from QSPI. There
* is also a firmware blob which boots from the eFlash, which
* uses init_svtor = 0x1A000000. QEMU doesn't currently support that,
* though we could in theory expose a machine property on the command
* line to allow the user to request eFlash boot.
*/
mmc->init_svtor = 0x10000000;
mmc->sram_addr_width = 17;
mmc->num_irqs = 96;
mmc->mpc_info = b1_mpc_info;
mmc->num_mpcs = ARRAY_SIZE(b1_mpc_info);
}
static const TypeInfo musca_info = {
.name = TYPE_MUSCA_MACHINE,
.parent = TYPE_MACHINE,
.abstract = true,
.instance_size = sizeof(MuscaMachineState),
.class_size = sizeof(MuscaMachineClass),
.class_init = musca_class_init,
};
static const TypeInfo musca_a_info = {
.name = TYPE_MUSCA_A_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_a_class_init,
};
static const TypeInfo musca_b1_info = {
.name = TYPE_MUSCA_B1_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_b1_class_init,
};
static void musca_machine_init(void)
{
type_register_static(&musca_info);
type_register_static(&musca_a_info);
type_register_static(&musca_b1_info);
}
type_init(musca_machine_init);
|
pmp-tool/PMP | src/qemu/src-pmp/hw/virtio/virtio-pci.h | <reponame>pmp-tool/PMP
/*
* Virtio PCI Bindings
*
* Copyright IBM, Corp. 2007
* Copyright (c) 2009 CodeSourcery
*
* Authors:
* <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#ifndef QEMU_VIRTIO_PCI_H
#define QEMU_VIRTIO_PCI_H
#include "hw/pci/msi.h"
#include "hw/virtio/virtio-bus.h"
typedef struct VirtIOPCIProxy VirtIOPCIProxy;
/* virtio-pci-bus */
typedef struct VirtioBusState VirtioPCIBusState;
typedef struct VirtioBusClass VirtioPCIBusClass;
#define TYPE_VIRTIO_PCI_BUS "virtio-pci-bus"
#define VIRTIO_PCI_BUS(obj) \
OBJECT_CHECK(VirtioPCIBusState, (obj), TYPE_VIRTIO_PCI_BUS)
#define VIRTIO_PCI_BUS_GET_CLASS(obj) \
OBJECT_GET_CLASS(VirtioPCIBusClass, obj, TYPE_VIRTIO_PCI_BUS)
#define VIRTIO_PCI_BUS_CLASS(klass) \
OBJECT_CLASS_CHECK(VirtioPCIBusClass, klass, TYPE_VIRTIO_PCI_BUS)
enum {
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT,
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT,
VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT,
VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
VIRTIO_PCI_FLAG_ATS_BIT,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
VIRTIO_PCI_FLAG_INIT_PM_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
#define VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION \
(1 << VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT)
/* Performance improves when virtqueue kick processing is decoupled from the
* vcpu thread using ioeventfd for some devices. */
#define VIRTIO_PCI_FLAG_USE_IOEVENTFD (1 << VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT)
/* virtio version flags */
#define VIRTIO_PCI_FLAG_DISABLE_PCIE (1 << VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT)
/* migrate extra state */
#define VIRTIO_PCI_FLAG_MIGRATE_EXTRA (1 << VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT)
/* have pio notification for modern device ? */
#define VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY \
(1 << VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT)
/* page per vq flag to be used by split drivers within guests */
#define VIRTIO_PCI_FLAG_PAGE_PER_VQ \
(1 << VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT)
/* address space translation service */
#define VIRTIO_PCI_FLAG_ATS (1 << VIRTIO_PCI_FLAG_ATS_BIT)
/* Init error enabling flags */
#define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT)
/* Init Link Control register */
#define VIRTIO_PCI_FLAG_INIT_LNKCTL (1 << VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT)
/* Init Power Management */
#define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
typedef struct {
MSIMessage msg;
int virq;
unsigned int users;
} VirtIOIRQFD;
/*
* virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
*/
#define TYPE_VIRTIO_PCI "virtio-pci"
#define VIRTIO_PCI_GET_CLASS(obj) \
OBJECT_GET_CLASS(VirtioPCIClass, obj, TYPE_VIRTIO_PCI)
#define VIRTIO_PCI_CLASS(klass) \
OBJECT_CLASS_CHECK(VirtioPCIClass, klass, TYPE_VIRTIO_PCI)
#define VIRTIO_PCI(obj) \
OBJECT_CHECK(VirtIOPCIProxy, (obj), TYPE_VIRTIO_PCI)
typedef struct VirtioPCIClass {
PCIDeviceClass parent_class;
DeviceRealize parent_dc_realize;
void (*realize)(VirtIOPCIProxy *vpci_dev, Error **errp);
} VirtioPCIClass;
typedef struct VirtIOPCIRegion {
MemoryRegion mr;
uint32_t offset;
uint32_t size;
uint32_t type;
} VirtIOPCIRegion;
typedef struct VirtIOPCIQueue {
uint16_t num;
bool enabled;
uint32_t desc[2];
uint32_t avail[2];
uint32_t used[2];
} VirtIOPCIQueue;
struct VirtIOPCIProxy {
PCIDevice pci_dev;
MemoryRegion bar;
union {
struct {
VirtIOPCIRegion common;
VirtIOPCIRegion isr;
VirtIOPCIRegion device;
VirtIOPCIRegion notify;
VirtIOPCIRegion notify_pio;
};
VirtIOPCIRegion regs[5];
};
MemoryRegion modern_bar;
MemoryRegion io_bar;
uint32_t legacy_io_bar_idx;
uint32_t msix_bar_idx;
uint32_t modern_io_bar_idx;
uint32_t modern_mem_bar_idx;
int config_cap;
uint32_t flags;
bool disable_modern;
bool ignore_backend_features;
OnOffAuto disable_legacy;
uint32_t class_code;
uint32_t nvectors;
uint32_t dfselect;
uint32_t gfselect;
uint32_t guest_features[2];
VirtIOPCIQueue vqs[VIRTIO_QUEUE_MAX];
VirtIOIRQFD *vector_irqfd;
int nvqs_with_notifiers;
VirtioBusState bus;
};
static inline bool virtio_pci_modern(VirtIOPCIProxy *proxy)
{
return !proxy->disable_modern;
}
static inline bool virtio_pci_legacy(VirtIOPCIProxy *proxy)
{
return proxy->disable_legacy == ON_OFF_AUTO_OFF;
}
static inline void virtio_pci_force_virtio_1(VirtIOPCIProxy *proxy)
{
proxy->disable_modern = false;
proxy->disable_legacy = ON_OFF_AUTO_ON;
}
static inline void virtio_pci_disable_modern(VirtIOPCIProxy *proxy)
{
proxy->disable_modern = true;
}
/*
* virtio-input-pci: This extends VirtioPCIProxy.
*/
#define TYPE_VIRTIO_INPUT_PCI "virtio-input-pci"
/* Virtio ABI version, if we increment this, we break the guest driver. */
#define VIRTIO_PCI_ABI_VERSION 0
/* Input for virtio_pci_types_register() */
typedef struct VirtioPCIDeviceTypeInfo {
/*
* Common base class for the subclasses below.
*
* Required only if transitional_name or non_transitional_name is set.
*
* We need a separate base type instead of making all types
* inherit from generic_name for two reasons:
* 1) generic_name implements INTERFACE_PCIE_DEVICE, but
* transitional_name does not.
* 2) generic_name has the "disable-legacy" and "disable-modern"
* properties, transitional_name and non_transitional name don't.
*/
const char *base_name;
/*
* Generic device type. Optional.
*
* Supports both transitional and non-transitional modes,
* using the disable-legacy and disable-modern properties.
* If disable-legacy=auto, (non-)transitional mode is selected
* depending on the bus where the device is plugged.
*
* Implements both INTERFACE_PCIE_DEVICE and INTERFACE_CONVENTIONAL_PCI_DEVICE,
* but PCI Express is supported only in non-transitional mode.
*
* The only type implemented by QEMU 3.1 and older.
*/
const char *generic_name;
/*
* The transitional device type. Optional.
*
* Implements both INTERFACE_PCIE_DEVICE and INTERFACE_CONVENTIONAL_PCI_DEVICE.
*/
const char *transitional_name;
/*
* The non-transitional device type. Optional.
*
* Implements INTERFACE_CONVENTIONAL_PCI_DEVICE only.
*/
const char *non_transitional_name;
/* Parent type. If NULL, TYPE_VIRTIO_PCI is used */
const char *parent;
/* Same as TypeInfo fields: */
size_t instance_size;
size_t class_size;
void (*instance_init)(Object *obj);
void (*class_init)(ObjectClass *klass, void *data);
} VirtioPCIDeviceTypeInfo;
/* Register virtio-pci type(s). @t must be static. */
void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t);
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/target/tricore/translate.c | <reponame>pmp-tool/PMP
/*
* TriCore emulation for qemu: main translation routines.
*
* Copyright (c) 2013-2014 <NAME> C-Lab/University Paderborn
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "tricore-opcodes.h"
#include "exec/log.h"
/*
* TCG registers
*/
static TCGv cpu_PC;
static TCGv cpu_PCXI;
static TCGv cpu_PSW;
static TCGv cpu_ICR;
/* GPR registers */
static TCGv cpu_gpr_a[16];
static TCGv cpu_gpr_d[16];
/* PSW Flag cache */
static TCGv cpu_PSW_C;
static TCGv cpu_PSW_V;
static TCGv cpu_PSW_SV;
static TCGv cpu_PSW_AV;
static TCGv cpu_PSW_SAV;
#include "exec/gen-icount.h"
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
"a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
"a12" , "a13" , "a14" , "a15",
};
static const char *regnames_d[] = {
"d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
"d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
"d12" , "d13" , "d14" , "d15",
};
typedef struct DisasContext {
struct TranslationBlock *tb;
target_ulong pc, saved_pc, next_pc;
uint32_t opcode;
int singlestep_enabled;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
int bstate;
} DisasContext;
enum {
BS_NONE = 0,
BS_STOP = 1,
BS_BRANCH = 2,
BS_EXCP = 3,
};
enum {
MODE_LL = 0,
MODE_LU = 1,
MODE_UL = 2,
MODE_UU = 3,
};
void tricore_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
uint32_t psw;
int i;
psw = psw_read(env);
cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
cpu_fprintf(f, "\nGPR A%02d:", i);
}
cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
}
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
cpu_fprintf(f, "\nGPR D%02d:", i);
}
cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
}
cpu_fprintf(f, "\n");
}
/*
* Functions to generate micro-ops
*/
/* Makros for generating helpers */
#define gen_helper_1arg(name, arg) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg); \
gen_helper_##name(cpu_env, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \
} while (0)
#define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg00, arg0, 16); \
tcg_gen_ext16s_tl(arg01, arg0); \
tcg_gen_ext16s_tl(arg11, arg1); \
gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg10 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg00, arg0, 16); \
tcg_gen_ext16s_tl(arg01, arg0); \
tcg_gen_sari_tl(arg11, arg1, 16); \
tcg_gen_ext16s_tl(arg10, arg1); \
gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg10); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg10 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg00, arg0, 16); \
tcg_gen_ext16s_tl(arg01, arg0); \
tcg_gen_sari_tl(arg10, arg1, 16); \
tcg_gen_ext16s_tl(arg11, arg1); \
gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg10); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg01, arg0, 16); \
tcg_gen_ext16s_tl(arg00, arg0); \
tcg_gen_sari_tl(arg11, arg1, 16); \
gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
TCGv_i64 ret = tcg_temp_new_i64(); \
TCGv_i64 arg1 = tcg_temp_new_i64(); \
\
tcg_gen_concat_i32_i64(arg1, al1, ah1); \
gen_helper_##name(ret, arg1, arg2); \
tcg_gen_extr_i64_i32(rl, rh, ret); \
\
tcg_temp_free_i64(ret); \
tcg_temp_free_i64(arg1); \
} while (0)
#define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
TCGv_i64 ret = tcg_temp_new_i64(); \
\
gen_helper_##name(ret, cpu_env, arg1, arg2); \
tcg_gen_extr_i64_i32(rl, rh, ret); \
\
tcg_temp_free_i64(ret); \
} while (0)
#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
((offset & 0x0fffff) << 1))
/* For two 32-bit registers used a 64-bit register, the first
registernumber needs to be even. Otherwise we trap. */
static inline void generate_trap(DisasContext *ctx, int class, int tin);
#define CHECK_REG_PAIR(reg) do { \
if (reg & 0x1) { \
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
} \
} while (0)
/* Functions for load/save to/from memory */
static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
int16_t con, TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, con);
tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
tcg_temp_free(temp);
}
static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
int16_t con, TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, con);
tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
tcg_temp_free(temp);
}
static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
{
TCGv_i64 temp = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp, rl, rh);
tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
tcg_temp_free_i64(temp);
}
static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, base, con);
gen_st_2regs_64(rh, rl, temp, ctx);
tcg_temp_free(temp);
}
static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
{
TCGv_i64 temp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
/* write back to two 32 bit regs */
tcg_gen_extr_i64_i32(rl, rh, temp);
tcg_temp_free_i64(temp);
}
static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, base, con);
gen_ld_2regs_64(rh, rl, temp, ctx);
tcg_temp_free(temp);
}
static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, off);
tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
tcg_gen_mov_tl(r2, temp);
tcg_temp_free(temp);
}
static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, off);
tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
tcg_gen_mov_tl(r2, temp);
tcg_temp_free(temp);
}
/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
CHECK_REG_PAIR(ereg);
/* temp = (M(EA, word) */
tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
/* temp = temp & ~E[a][63:32]) */
tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
/* temp2 = (E[a][31:0] & E[a][63:32]); */
tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
/* temp = temp | temp2; */
tcg_gen_or_tl(temp, temp, temp2);
/* M(EA, word) = temp; */
tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
/* tmp = M(EA, word);
M(EA, word) = D[a];
D[a] = tmp[31:0];*/
static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
{
TCGv temp = tcg_temp_new();
tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
tcg_temp_free(temp);
}
static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
cpu_gpr_d[reg], temp);
tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
tcg_gen_or_tl(temp2, temp2, temp3);
tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
}
/* We generate loads and store to core special function register (csfr) through
the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
makros R, A and E, which allow read-only, all and endinit protected access.
These makros also specify in which ISA version the csfr was introduced. */
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (tricore_feature(env, FEATURE)) { \
tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
#define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
{
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
gen_helper_psw_read(ret, cpu_env);
} else {
switch (offset) {
#include "csfr.def"
}
}
}
#undef R
#undef A
#undef E
#define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
since no execption occurs */
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (tricore_feature(env, FEATURE)) { \
tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
/* Endinit protected registers
TODO: Since the endinit bit is in a register of a not yet implemented
watchdog device, we handle endinit protected registers like
all-access registers for now. */
#define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
int32_t offset)
{
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
gen_helper_psw_write(cpu_env, r1);
} else {
switch (offset) {
#include "csfr.def"
}
}
} else {
/* generate privilege trap */
}
}
/* Functions for arithmetic instructions */
static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
{
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
/* Addition and set V/SV bits */
tcg_gen_add_tl(result, r1, r2);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
tcg_gen_xor_tl(t0, r1, r2);
tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, result, result);
tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, result);
tcg_temp_free(result);
tcg_temp_free(t0);
}
static inline void
gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
{
TCGv temp = tcg_temp_new();
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 result = tcg_temp_new_i64();
tcg_gen_add_i64(result, r1, r2);
/* calc v bit */
tcg_gen_xor_i64(t1, result, r1);
tcg_gen_xor_i64(t0, r1, r2);
tcg_gen_andc_i64(t1, t1, t0);
tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* calc AV/SAV bits */
tcg_gen_extrh_i64_i32(temp, result);
tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_i64(ret, result);
tcg_temp_free(temp);
tcg_temp_free_i64(result);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
static inline void
gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
void(*op2)(TCGv, TCGv, TCGv))
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv temp4 = tcg_temp_new();
(*op1)(temp, r1_low, r2);
/* calc V0 bit */
tcg_gen_xor_tl(temp2, temp, r1_low);
tcg_gen_xor_tl(temp3, r1_low, r2);
if (op1 == tcg_gen_add_tl) {
tcg_gen_andc_tl(temp2, temp2, temp3);
} else {
tcg_gen_and_tl(temp2, temp2, temp3);
}
(*op2)(temp3, r1_high, r3);
/* calc V1 bit */
tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
tcg_gen_xor_tl(temp4, r1_high, r3);
if (op2 == tcg_gen_add_tl) {
tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
} else {
tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
}
/* combine V0/V1 bits */
tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
/* calc sv bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
tcg_gen_mov_tl(ret_low, temp);
tcg_gen_mov_tl(ret_high, temp3);
/* calc AV bit */
tcg_gen_add_tl(temp, ret_low, ret_low);
tcg_gen_xor_tl(temp, temp, ret_low);
tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free(temp4);
}
/* ret = r2 + (r1 * r3); */
static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t1, r1);
tcg_gen_ext_i32_i64(t2, r2);
tcg_gen_ext_i32_i64(t3, r3);
tcg_gen_mul_i64(t1, t1, t3);
tcg_gen_add_i64(t1, t2, t1);
tcg_gen_extrl_i64_i32(ret, t1);
/* calc V
t1 > 0x7fffffff */
tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
/* t1 < -0x80000000 */
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
tcg_gen_or_i64(t2, t2, t3);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_madd32_d(ret, r1, r2, temp);
tcg_temp_free(temp);
}
static inline void
gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
TCGv t4 = tcg_temp_new();
tcg_gen_muls2_tl(t1, t2, r1, r3);
/* only the add can overflow */
tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
tcg_gen_xor_tl(t1, r2_high, t2);
tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back the result */
tcg_gen_mov_tl(ret_low, t3);
tcg_gen_mov_tl(ret_high, t4);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
tcg_temp_free(t4);
}
static inline void
gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t1, r1);
tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
tcg_gen_extu_i32_i64(t3, r3);
tcg_gen_mul_i64(t1, t1, t3);
tcg_gen_add_i64(t2, t2, t1);
/* write back result */
tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
/* only the add overflows, if t2 < t1
calc V bit */
tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static inline void
gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void
gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void
gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
tcg_gen_add_tl, tcg_gen_add_tl);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
tcg_gen_sub_tl, tcg_gen_add_tl);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
tcg_gen_ext32s_i64(temp64, temp64); /* low */
tcg_gen_sub_i64(temp64, temp64_2, temp64);
tcg_gen_shli_i64(temp64, temp64, 16);
gen_add64_d(temp64_2, temp64_3, temp64);
/* write back result */
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
tcg_temp_free_i64(temp64_3);
}
static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
static inline void
gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_adds(ret_low, r1_low, temp);
tcg_gen_mov_tl(temp, cpu_PSW_V);
tcg_gen_mov_tl(temp3, cpu_PSW_AV);
gen_adds(ret_high, r1_high, temp2);
/* combine v bits */
tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free_i64(temp64);
}
static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
static inline void
gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_subs(ret_low, r1_low, temp);
tcg_gen_mov_tl(temp, cpu_PSW_V);
tcg_gen_mov_tl(temp3, cpu_PSW_AV);
gen_adds(ret_high, r1_high, temp2);
/* combine v bits */
tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
tcg_gen_ext32s_i64(temp64, temp64); /* low */
tcg_gen_sub_i64(temp64, temp64_2, temp64);
tcg_gen_shli_i64(temp64, temp64, 16);
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
}
static inline void
gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_add64_d(temp64_3, temp64_2, temp64);
/* write back result */
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
tcg_temp_free_i64(temp64_3);
}
static inline void
gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
}
static inline void
gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_const_i32(n);
gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
tcg_temp_free(temp);
}
static inline void
gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_const_i32(n);
gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
tcg_temp_free(temp);
}
static inline void
gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift, CPUTriCoreState *env)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t2, arg2);
tcg_gen_ext_i32_i64(t3, arg3);
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_shli_i64(t2, t2, n);
tcg_gen_ext_i32_i64(t1, arg1);
tcg_gen_sari_i64(t2, t2, up_shift);
tcg_gen_add_i64(t3, t1, t2);
tcg_gen_extrl_i64_i32(temp3, t3);
/* calc v bit */
tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
tcg_gen_or_i64(t1, t1, t2);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
tcg_gen_and_tl(temp, temp, temp2);
tcg_gen_shli_tl(temp, temp, 31);
/* negate v bit, if special condition */
tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
}
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static inline void
gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
gen_add_d(ret, arg1, temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
gen_adds(ret, arg1, temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
gen_add64_d(t3, t1, t2);
/* write back result */
tcg_gen_extr_i64_i32(rl, rh, t3);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
gen_helper_add64_ssov(t1, cpu_env, t1, t2);
tcg_gen_extr_i64_i32(rl, rh, t1);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
static inline void
gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n, CPUTriCoreState *env)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_temp_new_i64();
TCGv temp, temp2;
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
tcg_gen_ext_i32_i64(t2, arg2);
tcg_gen_ext_i32_i64(t3, arg3);
tcg_gen_mul_i64(t2, t2, t3);
if (n != 0) {
tcg_gen_shli_i64(t2, t2, 1);
}
tcg_gen_add_i64(t4, t1, t2);
/* calc v bit */
tcg_gen_xor_i64(t3, t4, t1);
tcg_gen_xor_i64(t2, t1, t2);
tcg_gen_andc_i64(t3, t3, t2);
tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
temp = tcg_temp_new();
temp2 = tcg_temp_new();
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
tcg_gen_and_tl(temp, temp, temp2);
tcg_gen_shli_tl(temp, temp, 31);
/* negate v bit, if special condition */
tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
/* write back result */
tcg_gen_extr_i64_i32(rl, rh, t4);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
tcg_temp_free_i64(t4);
}
static inline void
gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t1, arg1);
tcg_gen_ext_i32_i64(t2, arg2);
tcg_gen_ext_i32_i64(t3, arg3);
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_sari_i64(t2, t2, up_shift - n);
gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static inline void
gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv_i64 r1 = tcg_temp_new_i64();
TCGv temp = tcg_const_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
tcg_gen_extr_i64_i32(rl, rh, r1);
tcg_temp_free_i64(r1);
tcg_temp_free(temp);
}
/* ret = r2 - (r1 * r3); */
static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t1, r1);
tcg_gen_ext_i32_i64(t2, r2);
tcg_gen_ext_i32_i64(t3, r3);
tcg_gen_mul_i64(t1, t1, t3);
tcg_gen_sub_i64(t1, t2, t1);
tcg_gen_extrl_i64_i32(ret, t1);
/* calc V
t2 > 0x7fffffff */
tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
/* result < -0x80000000 */
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
tcg_gen_or_i64(t2, t2, t3);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_msub32_d(ret, r1, r2, temp);
tcg_temp_free(temp);
}
static inline void
gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
TCGv t4 = tcg_temp_new();
tcg_gen_muls2_tl(t1, t2, r1, r3);
/* only the sub can overflow */
tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
tcg_gen_xor_tl(t1, r2_high, t2);
tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back the result */
tcg_gen_mov_tl(ret_low, t3);
tcg_gen_mov_tl(ret_high, t4);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
tcg_temp_free(t4);
}
static inline void
gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void
gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t1, r1);
tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
tcg_gen_extu_i32_i64(t3, r3);
tcg_gen_mul_i64(t1, t1, t3);
tcg_gen_sub_i64(t3, t2, t1);
tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
/* calc V bit, only the sub can overflow, if t1 > t2 */
tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static inline void
gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
{
TCGv temp = tcg_const_i32(r2);
gen_add_d(ret, r1, temp);
tcg_temp_free(temp);
}
/* calculate the carry bit too */
static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
tcg_gen_movi_tl(t0, 0);
/* Addition and set C/V/SV bits */
tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
tcg_gen_xor_tl(t0, r1, r2);
tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, result, result);
tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, result);
tcg_temp_free(result);
tcg_temp_free(t0);
}
static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_add_CC(ret, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv carry = tcg_temp_new_i32();
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
tcg_gen_movi_tl(t0, 0);
tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
/* Addition, carry and set C/V/SV bits */
tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
tcg_gen_xor_tl(t0, r1, r2);
tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, result, result);
tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, result);
tcg_temp_free(result);
tcg_temp_free(t0);
tcg_temp_free(carry);
}
static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_addc_CC(ret, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
TCGv r4)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv result = tcg_temp_new();
TCGv mask = tcg_temp_new();
TCGv t0 = tcg_const_i32(0);
/* create mask for sticky bits */
tcg_gen_setcond_tl(cond, mask, r4, t0);
tcg_gen_shli_tl(mask, mask, 31);
tcg_gen_add_tl(result, r1, r2);
/* Calc PSW_V */
tcg_gen_xor_tl(temp, result, r1);
tcg_gen_xor_tl(temp2, r1, r2);
tcg_gen_andc_tl(temp, temp, temp2);
tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
/* Set PSW_SV */
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
/* calc AV bit */
tcg_gen_add_tl(temp, result, result);
tcg_gen_xor_tl(temp, temp, result);
tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
/* write back result */
tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
tcg_temp_free(t0);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(result);
tcg_temp_free(mask);
}
static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
TCGv r3, TCGv r4)
{
TCGv temp = tcg_const_i32(r2);
gen_cond_add(cond, r1, temp, r3, r4);
tcg_temp_free(temp);
}
static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
tcg_gen_sub_tl(result, r1, r2);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
tcg_gen_xor_tl(temp, r1, r2);
tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, result, result);
tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, result);
tcg_temp_free(temp);
tcg_temp_free(result);
}
static inline void
gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
{
TCGv temp = tcg_temp_new();
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 result = tcg_temp_new_i64();
tcg_gen_sub_i64(result, r1, r2);
/* calc v bit */
tcg_gen_xor_i64(t1, result, r1);
tcg_gen_xor_i64(t0, r1, r2);
tcg_gen_and_i64(t1, t1, t0);
tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* calc AV/SAV bits */
tcg_gen_extrh_i64_i32(temp, result);
tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_i64(ret, result);
tcg_temp_free(temp);
tcg_temp_free_i64(result);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv result = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_sub_tl(result, r1, r2);
/* calc C bit */
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
tcg_gen_xor_tl(temp, r1, r2);
tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, result, result);
tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, result);
tcg_temp_free(result);
tcg_temp_free(temp);
}
static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new();
tcg_gen_not_tl(temp, r2);
gen_addc_CC(ret, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
TCGv r4)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv result = tcg_temp_new();
TCGv mask = tcg_temp_new();
TCGv t0 = tcg_const_i32(0);
/* create mask for sticky bits */
tcg_gen_setcond_tl(cond, mask, r4, t0);
tcg_gen_shli_tl(mask, mask, 31);
tcg_gen_sub_tl(result, r1, r2);
/* Calc PSW_V */
tcg_gen_xor_tl(temp, result, r1);
tcg_gen_xor_tl(temp2, r1, r2);
tcg_gen_and_tl(temp, temp, temp2);
tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
/* Set PSW_SV */
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
/* calc AV bit */
tcg_gen_add_tl(temp, result, result);
tcg_gen_xor_tl(temp, temp, result);
tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
/* write back result */
tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
tcg_temp_free(t0);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(result);
tcg_temp_free(mask);
}
static inline void
gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
tcg_gen_sub_tl, tcg_gen_sub_tl);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_subs(ret_low, r1_low, temp);
tcg_gen_mov_tl(temp, cpu_PSW_V);
tcg_gen_mov_tl(temp3, cpu_PSW_AV);
gen_subs(ret_high, r1_high, temp2);
/* combine v bits */
tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_sub64_d(temp64_3, temp64_2, temp64);
/* write back result */
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
tcg_temp_free_i64(temp64_3);
}
static inline void
gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
}
static inline void
gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_const_i32(n);
gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
tcg_temp_free(temp);
}
static inline void
gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_const_i32(n);
gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
tcg_temp_free(temp);
}
static inline void
gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift, CPUTriCoreState *env)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t2, arg2);
tcg_gen_ext_i32_i64(t3, arg3);
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_ext_i32_i64(t1, arg1);
/* if we shift part of the fraction out, we need to round up */
tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
tcg_gen_sari_i64(t2, t2, up_shift - n);
tcg_gen_add_i64(t2, t2, t4);
tcg_gen_sub_i64(t3, t1, t2);
tcg_gen_extrl_i64_i32(temp3, t3);
/* calc v bit */
tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
tcg_gen_or_i64(t1, t1, t2);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
tcg_temp_free_i64(t4);
}
static inline void
gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
gen_sub_d(ret, arg1, temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
gen_subs(ret, arg1, temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
gen_sub64_d(t3, t1, t2);
/* write back result */
tcg_gen_extr_i64_i32(rl, rh, t3);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
tcg_gen_sub_tl(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
tcg_gen_extr_i64_i32(rl, rh, t1);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
static inline void
gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n, CPUTriCoreState *env)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_temp_new_i64();
TCGv temp, temp2;
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
tcg_gen_ext_i32_i64(t2, arg2);
tcg_gen_ext_i32_i64(t3, arg3);
tcg_gen_mul_i64(t2, t2, t3);
if (n != 0) {
tcg_gen_shli_i64(t2, t2, 1);
}
tcg_gen_sub_i64(t4, t1, t2);
/* calc v bit */
tcg_gen_xor_i64(t3, t4, t1);
tcg_gen_xor_i64(t2, t1, t2);
tcg_gen_and_i64(t3, t3, t2);
tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
temp = tcg_temp_new();
temp2 = tcg_temp_new();
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
tcg_gen_and_tl(temp, temp, temp2);
tcg_gen_shli_tl(temp, temp, 31);
/* negate v bit, if special condition */
tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
/* write back result */
tcg_gen_extr_i64_i32(rl, rh, t4);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
/* calc SAV */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
tcg_temp_free_i64(t4);
}
static inline void
gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t1, arg1);
tcg_gen_ext_i32_i64(t2, arg2);
tcg_gen_ext_i32_i64(t3, arg3);
tcg_gen_mul_i64(t2, t2, t3);
/* if we shift part of the fraction out, we need to round up */
tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
tcg_gen_sari_i64(t3, t2, up_shift - n);
tcg_gen_add_i64(t3, t3, t4);
gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
tcg_temp_free_i64(t4);
}
static inline void
gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
TCGv_i64 r1 = tcg_temp_new_i64();
TCGv temp = tcg_const_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
tcg_gen_extr_i64_i32(rl, rh, r1);
tcg_temp_free_i64(r1);
tcg_temp_free(temp);
}
static inline void
gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
tcg_gen_add_tl, tcg_gen_sub_tl);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
tcg_gen_ext32s_i64(temp64, temp64); /* low */
tcg_gen_sub_i64(temp64, temp64_2, temp64);
tcg_gen_shli_i64(temp64, temp64, 16);
gen_sub64_d(temp64_2, temp64_3, temp64);
/* write back result */
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
tcg_temp_free_i64(temp64_3);
}
static inline void
gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_adds(ret_low, r1_low, temp);
tcg_gen_mov_tl(temp, cpu_PSW_V);
tcg_gen_mov_tl(temp3, cpu_PSW_AV);
gen_subs(ret_high, r1_high, temp2);
/* combine v bits */
tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
tcg_gen_ext32s_i64(temp64, temp64); /* low */
tcg_gen_sub_i64(temp64, temp64_2, temp64);
tcg_gen_shli_i64(temp64, temp64, 16);
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free(temp);
tcg_temp_free_i64(temp64);
tcg_temp_free_i64(temp64_2);
}
static inline void
gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_const_i32(n);
TCGv temp2 = tcg_temp_new();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
break;
case MODE_LU:
GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
break;
case MODE_UL:
GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
break;
case MODE_UU:
GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
break;
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free_i64(temp64);
}
static inline void gen_abs(TCGv ret, TCGv r1)
{
TCGv temp = tcg_temp_new();
TCGv t0 = tcg_const_i32(0);
tcg_gen_neg_tl(temp, r1);
tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
/* overflow can only happen, if r1 = 0x80000000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(temp);
tcg_temp_free(t0);
}
static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
tcg_gen_sub_tl(result, r1, r2);
tcg_gen_sub_tl(temp, r2, r1);
tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
/* calc V bit */
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
tcg_gen_xor_tl(temp, result, r2);
tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
tcg_gen_xor_tl(temp, r1, r2);
tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, result, result);
tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_tl(ret, result);
tcg_temp_free(temp);
tcg_temp_free(result);
}
static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_absdif(ret, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
{
TCGv high = tcg_temp_new();
TCGv low = tcg_temp_new();
tcg_gen_muls2_tl(low, high, r1, r2);
tcg_gen_mov_tl(ret, low);
/* calc V bit */
tcg_gen_sari_tl(low, low, 31);
tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(high);
tcg_temp_free(low);
}
static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_mul_i32s(ret, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
{
tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
/* clear V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_mul_i64s(ret_low, ret_high, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
{
tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
/* clear V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_mul_i64u(ret_low, ret_high, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_mul_ssov(ret, cpu_env, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_mul_suov(ret, cpu_env, r1, temp);
tcg_temp_free(temp);
}
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
tcg_temp_free(temp);
}
static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
tcg_temp_free(temp);
}
static void
gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
{
TCGv temp = tcg_temp_new();
TCGv_i64 temp_64 = tcg_temp_new_i64();
TCGv_i64 temp2_64 = tcg_temp_new_i64();
if (n == 0) {
if (up_shift == 32) {
tcg_gen_muls2_tl(rh, rl, arg1, arg2);
} else if (up_shift == 16) {
tcg_gen_ext_i32_i64(temp_64, arg1);
tcg_gen_ext_i32_i64(temp2_64, arg2);
tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
tcg_gen_shri_i64(temp_64, temp_64, up_shift);
tcg_gen_extr_i64_i32(rl, rh, temp_64);
} else {
tcg_gen_muls2_tl(rl, rh, arg1, arg2);
}
/* reset v bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
} else { /* n is expected to be 1 */
tcg_gen_ext_i32_i64(temp_64, arg1);
tcg_gen_ext_i32_i64(temp2_64, arg2);
tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
if (up_shift == 0) {
tcg_gen_shli_i64(temp_64, temp_64, 1);
} else {
tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
}
tcg_gen_extr_i64_i32(rl, rh, temp_64);
/* overflow only occurs if r1 = r2 = 0x8000 */
if (up_shift == 0) {/* result is 64 bit */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
0x80000000);
} else { /* result is 32 bit */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
0x80000000);
}
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc sv overflow bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
}
/* calc av overflow bit */
if (up_shift == 0) {
tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
} else {
tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
}
/* calc sav overflow bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(temp);
tcg_temp_free_i64(temp_64);
tcg_temp_free_i64(temp2_64);
}
static void
gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
{
TCGv temp = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(ret, arg1, arg2);
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(ret, arg1, arg2);
tcg_gen_shli_tl(ret, ret, 1);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
tcg_gen_sub_tl(ret, ret, temp);
}
/* reset v bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* calc av overflow bit */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc sav overflow bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(temp);
}
static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
{
TCGv temp = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(ret, arg1, arg2);
tcg_gen_addi_tl(ret, ret, 0x8000);
} else {
tcg_gen_mul_tl(ret, arg1, arg2);
tcg_gen_shli_tl(ret, ret, 1);
tcg_gen_addi_tl(ret, ret, 0x8000);
/* catch special case r1 = r2 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
tcg_gen_muli_tl(temp, temp, 0x8001);
tcg_gen_sub_tl(ret, ret, temp);
}
/* reset v bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* calc av overflow bit */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc sav overflow bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* cut halfword off */
tcg_gen_andi_tl(ret, ret, 0xffff0000);
tcg_temp_free(temp);
}
static inline void
gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void
gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free_i64(temp64);
}
static inline void
gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
tcg_temp_free(temp);
}
static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
tcg_temp_free(temp);
}
static inline void
gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static inline void
gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
tcg_temp_free_i64(temp64);
}
static inline void
gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
tcg_temp_free(temp);
}
static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
{
TCGv sat_neg = tcg_const_i32(low);
TCGv temp = tcg_const_i32(up);
/* sat_neg = (arg < low ) ? low : arg; */
tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
/* ret = (sat_neg > up ) ? up : sat_neg; */
tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
tcg_temp_free(sat_neg);
tcg_temp_free(temp);
}
static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
{
TCGv temp = tcg_const_i32(up);
/* sat_neg = (arg > up ) ? up : arg; */
tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
tcg_temp_free(temp);
}
static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
{
if (shift_count == -32) {
tcg_gen_movi_tl(ret, 0);
} else if (shift_count >= 0) {
tcg_gen_shli_tl(ret, r1, shift_count);
} else {
tcg_gen_shri_tl(ret, r1, -shift_count);
}
}
static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
{
TCGv temp_low, temp_high;
if (shiftcount == -16) {
tcg_gen_movi_tl(ret, 0);
} else {
temp_high = tcg_temp_new();
temp_low = tcg_temp_new();
tcg_gen_andi_tl(temp_low, r1, 0xffff);
tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
gen_shi(temp_low, temp_low, shiftcount);
gen_shi(ret, temp_high, shiftcount);
tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
tcg_temp_free(temp_low);
tcg_temp_free(temp_high);
}
}
static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
{
uint32_t msk, msk_start;
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
TCGv t_0 = tcg_const_i32(0);
if (shift_count == 0) {
/* Clear PSW.C and PSW.V */
tcg_gen_movi_tl(cpu_PSW_C, 0);
tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
tcg_gen_mov_tl(ret, r1);
} else if (shift_count == -32) {
/* set PSW.C */
tcg_gen_mov_tl(cpu_PSW_C, r1);
/* fill ret completely with sign bit */
tcg_gen_sari_tl(ret, r1, 31);
/* clear PSW.V */
tcg_gen_movi_tl(cpu_PSW_V, 0);
} else if (shift_count > 0) {
TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
/* calc carry */
msk_start = 32 - shift_count;
msk = ((1 << shift_count) - 1) << msk_start;
tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
/* calc v/sv bits */
tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
/* do shift */
tcg_gen_shli_tl(ret, r1, shift_count);
tcg_temp_free(t_max);
tcg_temp_free(t_min);
} else {
/* clear PSW.V */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* calc carry */
msk = (1 << -shift_count) - 1;
tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
/* do shift */
tcg_gen_sari_tl(ret, r1, -shift_count);
}
/* calc av overflow bit */
tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc sav overflow bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(t_0);
}
static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_sha_ssov(ret, cpu_env, r1, r2);
}
static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_shas(ret, r1, temp);
tcg_temp_free(temp);
}
static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
{
TCGv low, high;
if (shift_count == 0) {
tcg_gen_mov_tl(ret, r1);
} else if (shift_count > 0) {
low = tcg_temp_new();
high = tcg_temp_new();
tcg_gen_andi_tl(high, r1, 0xffff0000);
tcg_gen_shli_tl(low, r1, shift_count);
tcg_gen_shli_tl(ret, high, shift_count);
tcg_gen_deposit_tl(ret, ret, low, 0, 16);
tcg_temp_free(low);
tcg_temp_free(high);
} else {
low = tcg_temp_new();
high = tcg_temp_new();
tcg_gen_ext16s_tl(low, r1);
tcg_gen_sari_tl(low, low, -shift_count);
tcg_gen_sari_tl(ret, r1, -shift_count);
tcg_gen_deposit_tl(ret, ret, low, 0, 16);
tcg_temp_free(low);
tcg_temp_free(high);
}
}
/* ret = {ret[30:0], (r1 cond r2)}; */
static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_shli_tl(temp, ret, 1);
tcg_gen_setcond_tl(cond, temp2, r1, r2);
tcg_gen_or_tl(ret, temp, temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_sh_cond(cond, ret, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_add_ssov(ret, cpu_env, r1, r2);
}
static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_add_ssov(ret, cpu_env, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_const_i32(con);
gen_helper_add_suov(ret, cpu_env, r1, temp);
tcg_temp_free(temp);
}
static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_sub_ssov(ret, cpu_env, r1, r2);
}
static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_sub_suov(ret, cpu_env, r1, r2);
}
static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
int pos1, int pos2,
void(*op1)(TCGv, TCGv, TCGv),
void(*op2)(TCGv, TCGv, TCGv))
{
TCGv temp1, temp2;
temp1 = tcg_temp_new();
temp2 = tcg_temp_new();
tcg_gen_shri_tl(temp2, r2, pos2);
tcg_gen_shri_tl(temp1, r1, pos1);
(*op1)(temp1, temp1, temp2);
(*op2)(temp1 , ret, temp1);
tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
tcg_temp_free(temp1);
tcg_temp_free(temp2);
}
/* ret = r1[pos1] op1 r2[pos2]; */
static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
int pos1, int pos2,
void(*op1)(TCGv, TCGv, TCGv))
{
TCGv temp1, temp2;
temp1 = tcg_temp_new();
temp2 = tcg_temp_new();
tcg_gen_shri_tl(temp2, r2, pos2);
tcg_gen_shri_tl(temp1, r1, pos1);
(*op1)(ret, temp1, temp2);
tcg_gen_andi_tl(ret, ret, 0x1);
tcg_temp_free(temp1);
tcg_temp_free(temp2);
}
static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
void(*op)(TCGv, TCGv, TCGv))
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
/* temp = (arg1 cond arg2 )*/
tcg_gen_setcond_tl(cond, temp, r1, r2);
/* temp2 = ret[0]*/
tcg_gen_andi_tl(temp2, ret, 0x1);
/* temp = temp insn temp2 */
(*op)(temp, temp, temp2);
/* ret = {ret[31:1], temp} */
tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void
gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
void(*op)(TCGv, TCGv, TCGv))
{
TCGv temp = tcg_const_i32(con);
gen_accumulating_cond(cond, ret, r1, temp, op);
tcg_temp_free(temp);
}
/* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
{
tcg_gen_setcond_tl(cond, ret, r1, r2);
tcg_gen_neg_tl(ret, ret);
}
static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
{
TCGv b0 = tcg_temp_new();
TCGv b1 = tcg_temp_new();
TCGv b2 = tcg_temp_new();
TCGv b3 = tcg_temp_new();
/* byte 0 */
tcg_gen_andi_tl(b0, r1, 0xff);
tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
/* byte 1 */
tcg_gen_andi_tl(b1, r1, 0xff00);
tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
/* byte 2 */
tcg_gen_andi_tl(b2, r1, 0xff0000);
tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
/* byte 3 */
tcg_gen_andi_tl(b3, r1, 0xff000000);
tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
/* combine them */
tcg_gen_or_tl(ret, b0, b1);
tcg_gen_or_tl(ret, ret, b2);
tcg_gen_or_tl(ret, ret, b3);
tcg_temp_free(b0);
tcg_temp_free(b1);
tcg_temp_free(b2);
tcg_temp_free(b3);
}
static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
{
TCGv h0 = tcg_temp_new();
TCGv h1 = tcg_temp_new();
/* halfword 0 */
tcg_gen_andi_tl(h0, r1, 0xffff);
tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
/* halfword 1 */
tcg_gen_andi_tl(h1, r1, 0xffff0000);
tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
/* combine them */
tcg_gen_or_tl(ret, h0, h1);
tcg_temp_free(h0);
tcg_temp_free(h1);
}
/* mask = ((1 << width) -1) << pos;
ret = (r1 & ~mask) | (r2 << pos) & mask); */
static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
{
TCGv mask = tcg_temp_new();
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
tcg_gen_movi_tl(mask, 1);
tcg_gen_shl_tl(mask, mask, width);
tcg_gen_subi_tl(mask, mask, 1);
tcg_gen_shl_tl(mask, mask, pos);
tcg_gen_shl_tl(temp, r2, pos);
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_andc_tl(temp2, r1, mask);
tcg_gen_or_tl(ret, temp, temp2);
tcg_temp_free(mask);
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
{
TCGv_i64 temp = tcg_temp_new_i64();
gen_helper_bsplit(temp, r1);
tcg_gen_extr_i64_i32(rl, rh, temp);
tcg_temp_free_i64(temp);
}
static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
{
TCGv_i64 temp = tcg_temp_new_i64();
gen_helper_unpack(temp, r1);
tcg_gen_extr_i64_i32(rl, rh, temp);
tcg_temp_free_i64(temp);
}
static inline void
gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
} else {
gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
}
tcg_gen_extr_i64_i32(rl, rh, ret);
tcg_temp_free_i64(ret);
}
static inline void
gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
} else {
gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
}
tcg_gen_extr_i64_i32(rl, rh, ret);
tcg_temp_free_i64(ret);
}
static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
{
TCGv temp = tcg_temp_new();
/* calc AV bit */
tcg_gen_add_tl(temp, arg_low, arg_low);
tcg_gen_xor_tl(temp, temp, arg_low);
tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_gen_movi_tl(cpu_PSW_V, 0);
tcg_temp_free(temp);
}
static void gen_calc_usb_mulr_h(TCGv arg)
{
TCGv temp = tcg_temp_new();
/* calc AV bit */
tcg_gen_add_tl(temp, arg, arg);
tcg_gen_xor_tl(temp, temp, arg);
tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* clear V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
tcg_temp_free(temp);
}
/* helpers for generating program flow micro-ops */
static inline void gen_save_pc(target_ulong pc)
{
tcg_gen_movi_tl(cpu_PC, pc);
}
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
if (unlikely(ctx->singlestep_enabled)) {
return false;
}
#ifndef CONFIG_USER_ONLY
return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
}
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (use_goto_tb(ctx, dest)) {
tcg_gen_goto_tb(n);
gen_save_pc(dest);
tcg_gen_exit_tb(ctx->tb, n);
} else {
gen_save_pc(dest);
if (ctx->singlestep_enabled) {
/* raise exception debug */
}
tcg_gen_exit_tb(NULL, 0);
}
}
static void generate_trap(DisasContext *ctx, int class, int tin)
{
TCGv_i32 classtemp = tcg_const_i32(class);
TCGv_i32 tintemp = tcg_const_i32(tin);
gen_save_pc(ctx->pc);
gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
ctx->bstate = BS_EXCP;
tcg_temp_free(classtemp);
tcg_temp_free(tintemp);
}
static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
TCGv r2, int16_t address)
{
TCGLabel *jumpLabel = gen_new_label();
tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
gen_goto_tb(ctx, 1, ctx->next_pc);
gen_set_label(jumpLabel);
gen_goto_tb(ctx, 0, ctx->pc + address * 2);
}
static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
int r2, int16_t address)
{
TCGv temp = tcg_const_i32(r2);
gen_branch_cond(ctx, cond, r1, temp, address);
tcg_temp_free(temp);
}
static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
{
TCGLabel *l1 = gen_new_label();
tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
gen_goto_tb(ctx, 1, ctx->pc + offset);
gen_set_label(l1);
gen_goto_tb(ctx, 0, ctx->next_pc);
}
static void gen_fcall_save_ctx(DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
tcg_gen_mov_tl(cpu_gpr_a[10], temp);
tcg_temp_free(temp);
}
static void gen_fret(DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
tcg_gen_mov_tl(cpu_PC, temp);
tcg_gen_exit_tb(NULL, 0);
ctx->bstate = BS_BRANCH;
tcg_temp_free(temp);
}
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
TCGv temp, temp2;
int n;
switch (opc) {
/* SB-format jumps */
case OPC1_16_SB_J:
case OPC1_32_B_J:
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
break;
case OPC1_32_B_CALL:
case OPC1_16_SB_CALL:
gen_helper_1arg(call, ctx->next_pc);
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
break;
case OPC1_16_SB_JZ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
break;
case OPC1_16_SB_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
break;
/* SBC-format jumps */
case OPC1_16_SBC_JEQ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
break;
case OPC1_16_SBC_JEQ2:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
offset + 16);
break;
case OPC1_16_SBC_JNE:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
break;
case OPC1_16_SBC_JNE2:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
constant, offset + 16);
break;
/* SBRN-format jumps */
case OPC1_16_SBRN_JZ_T:
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
tcg_temp_free(temp);
break;
case OPC1_16_SBRN_JNZ_T:
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
tcg_temp_free(temp);
break;
/* SBR-format jumps */
case OPC1_16_SBR_JEQ:
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
offset);
break;
case OPC1_16_SBR_JEQ2:
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
offset + 16);
break;
case OPC1_16_SBR_JNE:
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
offset);
break;
case OPC1_16_SBR_JNE2:
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
offset + 16);
break;
case OPC1_16_SBR_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JNZ_A:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
break;
case OPC1_16_SBR_JGEZ:
gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JGTZ:
gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JLEZ:
gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JLTZ:
gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JZ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JZ_A:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
break;
case OPC1_16_SBR_LOOP:
gen_loop(ctx, r1, offset * 2 - 32);
break;
/* SR-format jumps */
case OPC1_16_SR_JI:
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
tcg_gen_exit_tb(NULL, 0);
break;
case OPC2_32_SYS_RET:
case OPC2_16_SR_RET:
gen_helper_ret(cpu_env);
tcg_gen_exit_tb(NULL, 0);
break;
/* B-format */
case OPC1_32_B_CALLA:
gen_helper_1arg(call, ctx->next_pc);
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_FCALL:
gen_fcall_save_ctx(ctx);
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
break;
case OPC1_32_B_FCALLA:
gen_fcall_save_ctx(ctx);
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_JLA:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
/* fall through */
case OPC1_32_B_JA:
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_JL:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
break;
/* BOL format */
case OPCM_32_BRC_EQ_NEQ:
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
} else {
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
}
break;
case OPCM_32_BRC_GE:
if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
} else {
constant = MASK_OP_BRC_CONST4(ctx->opcode);
gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
offset);
}
break;
case OPCM_32_BRC_JLT:
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
} else {
constant = MASK_OP_BRC_CONST4(ctx->opcode);
gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
offset);
}
break;
case OPCM_32_BRC_JNE:
temp = tcg_temp_new();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* subi is unconditional */
tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
} else {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* addi is unconditional */
tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
}
tcg_temp_free(temp);
break;
/* BRN format */
case OPCM_32_BRN_JTT:
n = MASK_OP_BRN_N(ctx->opcode);
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
} else {
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
}
tcg_temp_free(temp);
break;
/* BRR Format */
case OPCM_32_BRR_EQ_NEQ:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
}
break;
case OPCM_32_BRR_ADDR_EQ_NEQ:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
offset);
}
break;
case OPCM_32_BRR_GE:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
}
break;
case OPCM_32_BRR_JLT:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
}
break;
case OPCM_32_BRR_LOOP:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
gen_loop(ctx, r2, offset * 2);
} else {
/* OPC2_32_BRR_LOOPU */
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
}
break;
case OPCM_32_BRR_JNE:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
/* subi is unconditional */
tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
} else {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
/* addi is unconditional */
tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
case OPCM_32_BRR_JNZ:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
} else {
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
}
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
ctx->bstate = BS_BRANCH;
}
/*
* Functions for decoding instructions
*/
static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
{
int r1;
int32_t const4;
TCGv temp, temp2;
r1 = MASK_OP_SRC_S1D(ctx->opcode);
const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
switch (op1) {
case OPC1_16_SRC_ADD:
gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
break;
case OPC1_16_SRC_ADD_A15:
gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
break;
case OPC1_16_SRC_ADD_15A:
gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
break;
case OPC1_16_SRC_ADD_A:
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
break;
case OPC1_16_SRC_CADD:
gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
cpu_gpr_d[15]);
break;
case OPC1_16_SRC_CADDN:
gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
cpu_gpr_d[15]);
break;
case OPC1_16_SRC_CMOV:
temp = tcg_const_tl(0);
temp2 = tcg_const_tl(const4);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
case OPC1_16_SRC_CMOVN:
temp = tcg_const_tl(0);
temp2 = tcg_const_tl(const4);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
case OPC1_16_SRC_EQ:
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
const4);
break;
case OPC1_16_SRC_LT:
tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
const4);
break;
case OPC1_16_SRC_MOV:
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
break;
case OPC1_16_SRC_MOV_A:
const4 = MASK_OP_SRC_CONST4(ctx->opcode);
tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
break;
case OPC1_16_SRC_MOV_E:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_16_SRC_SH:
gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
break;
case OPC1_16_SRC_SHA:
gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_srr_opc(DisasContext *ctx, int op1)
{
int r1, r2;
TCGv temp;
r1 = MASK_OP_SRR_S1D(ctx->opcode);
r2 = MASK_OP_SRR_S2(ctx->opcode);
switch (op1) {
case OPC1_16_SRR_ADD:
gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_ADD_A15:
gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_ADD_15A:
gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_ADD_A:
tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC1_16_SRR_ADDS:
gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_AND:
tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_CMOV:
temp = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
tcg_temp_free(temp);
break;
case OPC1_16_SRR_CMOVN:
temp = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
tcg_temp_free(temp);
break;
case OPC1_16_SRR_EQ:
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_LT:
tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_MOV:
tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_MOV_A:
tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_MOV_AA:
tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC1_16_SRR_MOV_D:
tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
break;
case OPC1_16_SRR_MUL:
gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_OR:
tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_SUB:
gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_SUB_A15B:
gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_SUB_15AB:
gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_SUBS:
gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_XOR:
tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_ssr_opc(DisasContext *ctx, int op1)
{
int r1, r2;
r1 = MASK_OP_SSR_S1(ctx->opcode);
r2 = MASK_OP_SSR_S2(ctx->opcode);
switch (op1) {
case OPC1_16_SSR_ST_A:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
break;
case OPC1_16_SSR_ST_A_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
case OPC1_16_SSR_ST_B:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
break;
case OPC1_16_SSR_ST_B_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
break;
case OPC1_16_SSR_ST_H:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
break;
case OPC1_16_SSR_ST_H_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
break;
case OPC1_16_SSR_ST_W:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
break;
case OPC1_16_SSR_ST_W_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_sc_opc(DisasContext *ctx, int op1)
{
int32_t const16;
const16 = MASK_OP_SC_CONST8(ctx->opcode);
switch (op1) {
case OPC1_16_SC_AND:
tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_BISR:
gen_helper_1arg(bisr, const16 & 0xff);
break;
case OPC1_16_SC_LD_A:
gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
break;
case OPC1_16_SC_LD_W:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
break;
case OPC1_16_SC_MOV:
tcg_gen_movi_tl(cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_OR:
tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_ST_A:
gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
break;
case OPC1_16_SC_ST_W:
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
break;
case OPC1_16_SC_SUB_A:
tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_slr_opc(DisasContext *ctx, int op1)
{
int r1, r2;
r1 = MASK_OP_SLR_D(ctx->opcode);
r2 = MASK_OP_SLR_S2(ctx->opcode);
switch (op1) {
/* SLR-format */
case OPC1_16_SLR_LD_A:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
break;
case OPC1_16_SLR_LD_A_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
case OPC1_16_SLR_LD_BU:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
break;
case OPC1_16_SLR_LD_BU_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
break;
case OPC1_16_SLR_LD_H:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
break;
case OPC1_16_SLR_LD_H_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
break;
case OPC1_16_SLR_LD_W:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
break;
case OPC1_16_SLR_LD_W_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_sro_opc(DisasContext *ctx, int op1)
{
int r2;
int32_t address;
r2 = MASK_OP_SRO_S2(ctx->opcode);
address = MASK_OP_SRO_OFF4(ctx->opcode);
/* SRO-format */
switch (op1) {
case OPC1_16_SRO_LD_A:
gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
break;
case OPC1_16_SRO_LD_BU:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
break;
case OPC1_16_SRO_LD_H:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
break;
case OPC1_16_SRO_LD_W:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
break;
case OPC1_16_SRO_ST_A:
gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
break;
case OPC1_16_SRO_ST_B:
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
break;
case OPC1_16_SRO_ST_H:
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
break;
case OPC1_16_SRO_ST_W:
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
op2 = MASK_OP_SR_OP2(ctx->opcode);
switch (op2) {
case OPC2_16_SR_NOP:
break;
case OPC2_16_SR_RET:
gen_compute_branch(ctx, op2, 0, 0, 0, 0);
break;
case OPC2_16_SR_RFE:
gen_helper_rfe(cpu_env);
tcg_gen_exit_tb(NULL, 0);
ctx->bstate = BS_BRANCH;
break;
case OPC2_16_SR_DEBUG:
/* raise EXCP_DEBUG */
break;
case OPC2_16_SR_FRET:
gen_fret(ctx);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1;
TCGv temp;
r1 = MASK_OP_SR_S1D(ctx->opcode);
op2 = MASK_OP_SR_OP2(ctx->opcode);
switch (op2) {
case OPC2_16_SR_RSUB:
/* overflow only if r1 = -0x80000000 */
temp = tcg_const_i32(-0x80000000);
/* calc V bit */
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* sub */
tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
/* calc av */
tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
/* calc sav */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
tcg_temp_free(temp);
break;
case OPC2_16_SR_SAT_B:
gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
break;
case OPC2_16_SR_SAT_BU:
gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
break;
case OPC2_16_SR_SAT_H:
gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
break;
case OPC2_16_SR_SAT_HU:
gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
{
int op1;
int r1, r2;
int32_t const16;
int32_t address;
TCGv temp;
op1 = MASK_OP_MAJOR(ctx->opcode);
/* handle ADDSC.A opcode only being 6 bit long */
if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
op1 = OPC1_16_SRRS_ADDSC_A;
}
switch (op1) {
case OPC1_16_SRC_ADD:
case OPC1_16_SRC_ADD_A15:
case OPC1_16_SRC_ADD_15A:
case OPC1_16_SRC_ADD_A:
case OPC1_16_SRC_CADD:
case OPC1_16_SRC_CADDN:
case OPC1_16_SRC_CMOV:
case OPC1_16_SRC_CMOVN:
case OPC1_16_SRC_EQ:
case OPC1_16_SRC_LT:
case OPC1_16_SRC_MOV:
case OPC1_16_SRC_MOV_A:
case OPC1_16_SRC_MOV_E:
case OPC1_16_SRC_SH:
case OPC1_16_SRC_SHA:
decode_src_opc(env, ctx, op1);
break;
/* SRR-format */
case OPC1_16_SRR_ADD:
case OPC1_16_SRR_ADD_A15:
case OPC1_16_SRR_ADD_15A:
case OPC1_16_SRR_ADD_A:
case OPC1_16_SRR_ADDS:
case OPC1_16_SRR_AND:
case OPC1_16_SRR_CMOV:
case OPC1_16_SRR_CMOVN:
case OPC1_16_SRR_EQ:
case OPC1_16_SRR_LT:
case OPC1_16_SRR_MOV:
case OPC1_16_SRR_MOV_A:
case OPC1_16_SRR_MOV_AA:
case OPC1_16_SRR_MOV_D:
case OPC1_16_SRR_MUL:
case OPC1_16_SRR_OR:
case OPC1_16_SRR_SUB:
case OPC1_16_SRR_SUB_A15B:
case OPC1_16_SRR_SUB_15AB:
case OPC1_16_SRR_SUBS:
case OPC1_16_SRR_XOR:
decode_srr_opc(ctx, op1);
break;
/* SSR-format */
case OPC1_16_SSR_ST_A:
case OPC1_16_SSR_ST_A_POSTINC:
case OPC1_16_SSR_ST_B:
case OPC1_16_SSR_ST_B_POSTINC:
case OPC1_16_SSR_ST_H:
case OPC1_16_SSR_ST_H_POSTINC:
case OPC1_16_SSR_ST_W:
case OPC1_16_SSR_ST_W_POSTINC:
decode_ssr_opc(ctx, op1);
break;
/* SRRS-format */
case OPC1_16_SRRS_ADDSC_A:
r2 = MASK_OP_SRRS_S2(ctx->opcode);
r1 = MASK_OP_SRRS_S1D(ctx->opcode);
const16 = MASK_OP_SRRS_N(ctx->opcode);
temp = tcg_temp_new();
tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
tcg_temp_free(temp);
break;
/* SLRO-format */
case OPC1_16_SLRO_LD_A:
r1 = MASK_OP_SLRO_D(ctx->opcode);
const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
break;
case OPC1_16_SLRO_LD_BU:
r1 = MASK_OP_SLRO_D(ctx->opcode);
const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
break;
case OPC1_16_SLRO_LD_H:
r1 = MASK_OP_SLRO_D(ctx->opcode);
const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
break;
case OPC1_16_SLRO_LD_W:
r1 = MASK_OP_SLRO_D(ctx->opcode);
const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
break;
/* SB-format */
case OPC1_16_SB_CALL:
case OPC1_16_SB_J:
case OPC1_16_SB_JNZ:
case OPC1_16_SB_JZ:
address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, 0, address);
break;
/* SBC-format */
case OPC1_16_SBC_JEQ:
case OPC1_16_SBC_JNE:
address = MASK_OP_SBC_DISP4(ctx->opcode);
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
case OPC1_16_SBC_JEQ2:
case OPC1_16_SBC_JNE2:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
address = MASK_OP_SBC_DISP4(ctx->opcode);
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
/* SBRN-format */
case OPC1_16_SBRN_JNZ_T:
case OPC1_16_SBRN_JZ_T:
address = MASK_OP_SBRN_DISP4(ctx->opcode);
const16 = MASK_OP_SBRN_N(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
/* SBR-format */
case OPC1_16_SBR_JEQ2:
case OPC1_16_SBR_JNE2:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
r1 = MASK_OP_SBR_S2(ctx->opcode);
address = MASK_OP_SBR_DISP4(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_16_SBR_JEQ:
case OPC1_16_SBR_JGEZ:
case OPC1_16_SBR_JGTZ:
case OPC1_16_SBR_JLEZ:
case OPC1_16_SBR_JLTZ:
case OPC1_16_SBR_JNE:
case OPC1_16_SBR_JNZ:
case OPC1_16_SBR_JNZ_A:
case OPC1_16_SBR_JZ:
case OPC1_16_SBR_JZ_A:
case OPC1_16_SBR_LOOP:
r1 = MASK_OP_SBR_S2(ctx->opcode);
address = MASK_OP_SBR_DISP4(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
break;
/* SC-format */
case OPC1_16_SC_AND:
case OPC1_16_SC_BISR:
case OPC1_16_SC_LD_A:
case OPC1_16_SC_LD_W:
case OPC1_16_SC_MOV:
case OPC1_16_SC_OR:
case OPC1_16_SC_ST_A:
case OPC1_16_SC_ST_W:
case OPC1_16_SC_SUB_A:
decode_sc_opc(ctx, op1);
break;
/* SLR-format */
case OPC1_16_SLR_LD_A:
case OPC1_16_SLR_LD_A_POSTINC:
case OPC1_16_SLR_LD_BU:
case OPC1_16_SLR_LD_BU_POSTINC:
case OPC1_16_SLR_LD_H:
case OPC1_16_SLR_LD_H_POSTINC:
case OPC1_16_SLR_LD_W:
case OPC1_16_SLR_LD_W_POSTINC:
decode_slr_opc(ctx, op1);
break;
/* SRO-format */
case OPC1_16_SRO_LD_A:
case OPC1_16_SRO_LD_BU:
case OPC1_16_SRO_LD_H:
case OPC1_16_SRO_LD_W:
case OPC1_16_SRO_ST_A:
case OPC1_16_SRO_ST_B:
case OPC1_16_SRO_ST_H:
case OPC1_16_SRO_ST_W:
decode_sro_opc(ctx, op1);
break;
/* SSRO-format */
case OPC1_16_SSRO_ST_A:
r1 = MASK_OP_SSRO_S1(ctx->opcode);
const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
break;
case OPC1_16_SSRO_ST_B:
r1 = MASK_OP_SSRO_S1(ctx->opcode);
const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
break;
case OPC1_16_SSRO_ST_H:
r1 = MASK_OP_SSRO_S1(ctx->opcode);
const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
break;
case OPC1_16_SSRO_ST_W:
r1 = MASK_OP_SSRO_S1(ctx->opcode);
const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
break;
/* SR-format */
case OPCM_16_SR_SYSTEM:
decode_sr_system(env, ctx);
break;
case OPCM_16_SR_ACCU:
decode_sr_accu(env, ctx);
break;
case OPC1_16_SR_JI:
r1 = MASK_OP_SR_S1D(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, 0);
break;
case OPC1_16_SR_NOT:
r1 = MASK_OP_SR_S1D(ctx->opcode);
tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/*
* 32 bit instructions
*/
/* ABS-format */
static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
{
int32_t op2;
int32_t r1;
uint32_t address;
TCGv temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_LD_A:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
break;
case OPC2_32_ABS_LD_D:
CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
break;
case OPC2_32_ABS_LD_DA:
CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
break;
case OPC2_32_ABS_LD_W:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
{
int32_t op2;
int32_t r1;
uint32_t address;
TCGv temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_LD_B:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
break;
case OPC2_32_ABS_LD_BU:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
break;
case OPC2_32_ABS_LD_H:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
break;
case OPC2_32_ABS_LD_HU:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
{
int32_t op2;
int32_t r1;
uint32_t address;
TCGv temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_LDMST:
gen_ldmst(ctx, r1, temp);
break;
case OPC2_32_ABS_SWAP_W:
gen_swap(ctx, r1, temp);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int32_t off18;
off18 = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_ABS_LDLCX:
gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
break;
case OPC2_32_ABS_LDUCX:
gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
break;
case OPC2_32_ABS_STLCX:
gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
break;
case OPC2_32_ABS_STUCX:
gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
{
int32_t op2;
int32_t r1;
uint32_t address;
TCGv temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_ST_A:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
break;
case OPC2_32_ABS_ST_D:
CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
break;
case OPC2_32_ABS_ST_DA:
CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
break;
case OPC2_32_ABS_ST_W:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
{
int32_t op2;
int32_t r1;
uint32_t address;
TCGv temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
op2 = MASK_OP_ABS_OP2(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
switch (op2) {
case OPC2_32_ABS_ST_B:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
break;
case OPC2_32_ABS_ST_H:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
/* Bit-format */
static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
op2 = MASK_OP_BIT_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_BIT_AND_AND_T:
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
break;
case OPC2_32_BIT_AND_ANDN_T:
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
break;
case OPC2_32_BIT_AND_NOR_T:
if (TCG_TARGET_HAS_andc_i32) {
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
} else {
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
}
break;
case OPC2_32_BIT_AND_OR_T:
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
op2 = MASK_OP_BIT_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_BIT_AND_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_and_tl);
break;
case OPC2_32_BIT_ANDN_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_andc_tl);
break;
case OPC2_32_BIT_NOR_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_nor_tl);
break;
case OPC2_32_BIT_OR_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
TCGv temp;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
temp = tcg_temp_new();
tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
if (op2 == OPC2_32_BIT_INSN_T) {
tcg_gen_not_tl(temp, temp);
}
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
tcg_temp_free(temp);
}
static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
switch (op2) {
case OPC2_32_BIT_NAND_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_nand_tl);
break;
case OPC2_32_BIT_ORN_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_orc_tl);
break;
case OPC2_32_BIT_XNOR_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_eqv_tl);
break;
case OPC2_32_BIT_XOR_T:
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_xor_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
switch (op2) {
case OPC2_32_BIT_OR_AND_T:
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
break;
case OPC2_32_BIT_OR_ANDN_T:
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
break;
case OPC2_32_BIT_OR_NOR_T:
if (TCG_TARGET_HAS_orc_i32) {
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
} else {
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
}
break;
case OPC2_32_BIT_OR_OR_T:
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
TCGv temp;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
temp = tcg_temp_new();
switch (op2) {
case OPC2_32_BIT_SH_AND_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_and_tl);
break;
case OPC2_32_BIT_SH_ANDN_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_andc_tl);
break;
case OPC2_32_BIT_SH_NOR_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_nor_tl);
break;
case OPC2_32_BIT_SH_OR_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
tcg_temp_free(temp);
}
static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
TCGv temp;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
r3 = MASK_OP_BIT_D(ctx->opcode);
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
temp = tcg_temp_new();
switch (op2) {
case OPC2_32_BIT_SH_NAND_T:
gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
pos1, pos2, &tcg_gen_nand_tl);
break;
case OPC2_32_BIT_SH_ORN_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_orc_tl);
break;
case OPC2_32_BIT_SH_XNOR_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_eqv_tl);
break;
case OPC2_32_BIT_SH_XOR_T:
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_xor_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
tcg_temp_free(temp);
}
/* BO-format */
static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
DisasContext *ctx)
{
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
TCGv temp;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_BO_CACHEA_WI_SHORTOFF:
case OPC2_32_BO_CACHEA_W_SHORTOFF:
case OPC2_32_BO_CACHEA_I_SHORTOFF:
/* instruction to access the cache */
break;
case OPC2_32_BO_CACHEA_WI_POSTINC:
case OPC2_32_BO_CACHEA_W_POSTINC:
case OPC2_32_BO_CACHEA_I_POSTINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEA_WI_PREINC:
case OPC2_32_BO_CACHEA_W_PREINC:
case OPC2_32_BO_CACHEA_I_PREINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_BO_ST_A_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
break;
case OPC2_32_BO_ST_A_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_A_PREINC:
gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
break;
case OPC2_32_BO_ST_B_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_ST_B_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_UB);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_B_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_ST_D_SHORTOFF:
CHECK_REG_PAIR(r1);
gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_ST_D_POSTINC:
CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_D_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
tcg_temp_free(temp);
break;
case OPC2_32_BO_ST_DA_SHORTOFF:
CHECK_REG_PAIR(r1);
gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_ST_DA_POSTINC:
CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_DA_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
tcg_temp_free(temp);
break;
case OPC2_32_BO_ST_H_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_H_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_H_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_Q_SHORTOFF:
temp = tcg_temp_new();
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
tcg_temp_free(temp);
break;
case OPC2_32_BO_ST_Q_POSTINC:
temp = tcg_temp_new();
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
tcg_temp_free(temp);
break;
case OPC2_32_BO_ST_Q_PREINC:
temp = tcg_temp_new();
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
tcg_temp_free(temp);
break;
case OPC2_32_BO_ST_W_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_ST_W_POSTINC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_W_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
DisasContext *ctx)
{
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
TCGv temp, temp2, temp3;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_const_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
switch (op2) {
case OPC2_32_BO_CACHEA_WI_BR:
case OPC2_32_BO_CACHEA_W_BR:
case OPC2_32_BO_CACHEA_I_BR:
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_CACHEA_WI_CIRC:
case OPC2_32_BO_CACHEA_W_CIRC:
case OPC2_32_BO_CACHEA_I_CIRC:
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_A_BR:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_A_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_B_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_B_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_D_BR:
CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_D_CIRC:
CHECK_REG_PAIR(r1);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_DA_BR:
CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_DA_CIRC:
CHECK_REG_PAIR(r1);
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_H_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_H_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_Q_BR:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_Q_CIRC:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_W_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_W_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
}
static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
DisasContext *ctx)
{
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
TCGv temp;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_BO_LD_A_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_LD_A_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_A_PREINC:
gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_LD_B_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
break;
case OPC2_32_BO_LD_B_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_SB);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_B_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
break;
case OPC2_32_BO_LD_BU_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_LD_BU_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_UB);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_BU_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
break;
case OPC2_32_BO_LD_D_SHORTOFF:
CHECK_REG_PAIR(r1);
gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_LD_D_POSTINC:
CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_D_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
tcg_temp_free(temp);
break;
case OPC2_32_BO_LD_DA_SHORTOFF:
CHECK_REG_PAIR(r1);
gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_LD_DA_POSTINC:
CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_DA_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
tcg_temp_free(temp);
break;
case OPC2_32_BO_LD_H_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
break;
case OPC2_32_BO_LD_H_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LESW);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_H_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
break;
case OPC2_32_BO_LD_HU_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_LD_HU_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_HU_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_LD_Q_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
break;
case OPC2_32_BO_LD_Q_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_Q_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
break;
case OPC2_32_BO_LD_W_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_LD_W_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_W_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
DisasContext *ctx)
{
uint32_t op2;
uint32_t off10;
int r1, r2;
TCGv temp, temp2, temp3;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_const_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
switch (op2) {
case OPC2_32_BO_LD_A_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_A_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_B_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_B_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_BU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_BU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_D_BR:
CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_D_CIRC:
CHECK_REG_PAIR(r1);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_DA_BR:
CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_DA_CIRC:
CHECK_REG_PAIR(r1);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_H_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_H_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_HU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_HU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_Q_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_Q_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_W_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_W_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
}
static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
DisasContext *ctx)
{
uint32_t op2;
uint32_t off10;
int r1, r2;
TCGv temp, temp2;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
switch (op2) {
case OPC2_32_BO_LDLCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_ldlcx(cpu_env, temp);
break;
case OPC2_32_BO_LDMST_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_ldmst(ctx, r1, temp);
break;
case OPC2_32_BO_LDMST_POSTINC:
gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LDMST_PREINC:
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
break;
case OPC2_32_BO_LDUCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_lducx(cpu_env, temp);
break;
case OPC2_32_BO_LEA_SHORTOFF:
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_STLCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_stlcx(cpu_env, temp);
break;
case OPC2_32_BO_STUCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_stucx(cpu_env, temp);
break;
case OPC2_32_BO_SWAP_W_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_swap(ctx, r1, temp);
break;
case OPC2_32_BO_SWAP_W_POSTINC:
gen_swap(ctx, r1, cpu_gpr_a[r2]);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_SWAP_W_PREINC:
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swap(ctx, r1, cpu_gpr_a[r2]);
break;
case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_cmpswap(ctx, r1, temp);
break;
case OPC2_32_BO_CMPSWAP_W_POSTINC:
gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CMPSWAP_W_PREINC:
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
break;
case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_swapmsk(ctx, r1, temp);
break;
case OPC2_32_BO_SWAPMSK_W_POSTINC:
gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_SWAPMSK_W_PREINC:
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
DisasContext *ctx)
{
uint32_t op2;
uint32_t off10;
int r1, r2;
TCGv temp, temp2, temp3;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_const_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
switch (op2) {
case OPC2_32_BO_LDMST_BR:
gen_ldmst(ctx, r1, temp2);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LDMST_CIRC:
gen_ldmst(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_SWAP_W_BR:
gen_swap(ctx, r1, temp2);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_SWAP_W_CIRC:
gen_swap(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_CMPSWAP_W_BR:
gen_cmpswap(ctx, r1, temp2);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_CMPSWAP_W_CIRC:
gen_cmpswap(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_SWAPMSK_W_BR:
gen_swapmsk(ctx, r1, temp2);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_SWAPMSK_W_CIRC:
gen_swapmsk(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
}
static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
{
int r1, r2;
int32_t address;
TCGv temp;
r1 = MASK_OP_BOL_S1D(ctx->opcode);
r2 = MASK_OP_BOL_S2(ctx->opcode);
address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
switch (op1) {
case OPC1_32_BOL_LD_A_LONGOFF:
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
break;
case OPC1_32_BOL_LD_W_LONGOFF:
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
break;
case OPC1_32_BOL_LEA_LONGOFF:
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
break;
case OPC1_32_BOL_ST_A_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_W_LONGOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
break;
case OPC1_32_BOL_LD_B_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_BU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_HU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_B_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RC format */
static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2;
int32_t const9;
TCGv temp;
r2 = MASK_OP_RC_D(ctx->opcode);
r1 = MASK_OP_RC_S1(ctx->opcode);
const9 = MASK_OP_RC_CONST9(ctx->opcode);
op2 = MASK_OP_RC_OP2(ctx->opcode);
temp = tcg_temp_new();
switch (op2) {
case OPC2_32_RC_AND:
tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ANDN:
tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
break;
case OPC2_32_RC_NAND:
tcg_gen_movi_tl(temp, const9);
tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_NOR:
tcg_gen_movi_tl(temp, const9);
tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_OR:
tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ORN:
tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
break;
case OPC2_32_RC_SH:
const9 = sextract32(const9, 0, 6);
gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SH_H:
const9 = sextract32(const9, 0, 5);
gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SHA:
const9 = sextract32(const9, 0, 6);
gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SHA_H:
const9 = sextract32(const9, 0, 5);
gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SHAS:
gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_XNOR:
tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
break;
case OPC2_32_RC_XOR:
tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2;
int16_t const9;
TCGv temp;
r2 = MASK_OP_RC_D(ctx->opcode);
r1 = MASK_OP_RC_S1(ctx->opcode);
const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
op2 = MASK_OP_RC_OP2(ctx->opcode);
temp = tcg_temp_new();
switch (op2) {
case OPC2_32_RC_ABSDIF:
gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ABSDIFS:
gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ADD:
gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ADDC:
gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ADDS:
gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ADDS_U:
gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ADDX:
gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_AND_EQ:
gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_AND_GE:
gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_AND_GE_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_AND_LT:
gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_AND_LT_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_AND_NE:
gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_EQ:
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_EQANY_B:
gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_EQANY_H:
gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_GE:
tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_GE_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_LT:
tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_LT_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MAX:
tcg_gen_movi_tl(temp, const9);
tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_MAX_U:
tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_MIN:
tcg_gen_movi_tl(temp, const9);
tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_MIN_U:
tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_NE:
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_OR_EQ:
gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_OR_GE:
gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_OR_GE_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_OR_LT:
gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_OR_LT_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_OR_NE:
gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_RSUB:
tcg_gen_movi_tl(temp, const9);
gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
break;
case OPC2_32_RC_RSUBS:
tcg_gen_movi_tl(temp, const9);
gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
break;
case OPC2_32_RC_RSUBS_U:
tcg_gen_movi_tl(temp, const9);
gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
break;
case OPC2_32_RC_SH_EQ:
gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SH_GE:
gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SH_GE_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SH_LT:
gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SH_LT_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SH_NE:
gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_XOR_EQ:
gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
case OPC2_32_RC_XOR_GE:
gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
case OPC2_32_RC_XOR_GE_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
case OPC2_32_RC_XOR_LT:
gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
case OPC2_32_RC_XOR_LT_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
case OPC2_32_RC_XOR_NE:
gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t const9;
op2 = MASK_OP_RC_OP2(ctx->opcode);
const9 = MASK_OP_RC_CONST9(ctx->opcode);
switch (op2) {
case OPC2_32_RC_BISR:
gen_helper_1arg(bisr, const9);
break;
case OPC2_32_RC_SYSCALL:
/* TODO: Add exception generation */
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2;
int16_t const9;
r2 = MASK_OP_RC_D(ctx->opcode);
r1 = MASK_OP_RC_S1(ctx->opcode);
const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
op2 = MASK_OP_RC_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_RC_MUL_32:
gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MUL_64:
CHECK_REG_PAIR(r2);
gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MULS_32:
gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MUL_U_64:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
CHECK_REG_PAIR(r2);
gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MULS_U_32:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RCPW format */
static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2;
int32_t pos, width, const4;
TCGv temp;
op2 = MASK_OP_RCPW_OP2(ctx->opcode);
r1 = MASK_OP_RCPW_S1(ctx->opcode);
r2 = MASK_OP_RCPW_D(ctx->opcode);
const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
width = MASK_OP_RCPW_WIDTH(ctx->opcode);
pos = MASK_OP_RCPW_POS(ctx->opcode);
switch (op2) {
case OPC2_32_RCPW_IMASK:
CHECK_REG_PAIR(r2);
/* if pos + width > 31 undefined result */
if (pos + width <= 31) {
tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
}
break;
case OPC2_32_RCPW_INSERT:
/* if pos + width > 32 undefined result */
if (pos + width <= 32) {
temp = tcg_const_i32(const4);
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
tcg_temp_free(temp);
}
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RCRW format */
static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r3, r4;
int32_t width, const4;
TCGv temp, temp2, temp3;
op2 = MASK_OP_RCRW_OP2(ctx->opcode);
r1 = MASK_OP_RCRW_S1(ctx->opcode);
r3 = MASK_OP_RCRW_S3(ctx->opcode);
r4 = MASK_OP_RCRW_D(ctx->opcode);
width = MASK_OP_RCRW_WIDTH(ctx->opcode);
const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
switch (op2) {
case OPC2_32_RCRW_IMASK:
tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
tcg_gen_movi_tl(temp2, (1 << width) - 1);
tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
tcg_gen_movi_tl(temp2, const4);
tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
break;
case OPC2_32_RCRW_INSERT:
temp3 = tcg_temp_new();
tcg_gen_movi_tl(temp, width);
tcg_gen_movi_tl(temp2, const4);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_temp_free(temp3);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
/* RCR format */
static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r3, r4;
int32_t const9;
TCGv temp, temp2;
op2 = MASK_OP_RCR_OP2(ctx->opcode);
r1 = MASK_OP_RCR_S1(ctx->opcode);
const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
r3 = MASK_OP_RCR_S3(ctx->opcode);
r4 = MASK_OP_RCR_D(ctx->opcode);
switch (op2) {
case OPC2_32_RCR_CADD:
gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
cpu_gpr_d[r3]);
break;
case OPC2_32_RCR_CADDN:
gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
cpu_gpr_d[r3]);
break;
case OPC2_32_RCR_SEL:
temp = tcg_const_i32(0);
temp2 = tcg_const_i32(const9);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
case OPC2_32_RCR_SELN:
temp = tcg_const_i32(0);
temp2 = tcg_const_i32(const9);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r3, r4;
int32_t const9;
op2 = MASK_OP_RCR_OP2(ctx->opcode);
r1 = MASK_OP_RCR_S1(ctx->opcode);
const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
r3 = MASK_OP_RCR_S3(ctx->opcode);
r4 = MASK_OP_RCR_D(ctx->opcode);
switch (op2) {
case OPC2_32_RCR_MADD_32:
gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MADD_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MADDS_32:
gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MADDS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MADD_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MADDS_U_32:
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MADDS_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r3, r4;
int32_t const9;
op2 = MASK_OP_RCR_OP2(ctx->opcode);
r1 = MASK_OP_RCR_S1(ctx->opcode);
const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
r3 = MASK_OP_RCR_S3(ctx->opcode);
r4 = MASK_OP_RCR_D(ctx->opcode);
switch (op2) {
case OPC2_32_RCR_MSUB_32:
gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MSUB_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MSUBS_32:
gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MSUBS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MSUB_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MSUBS_U_32:
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MSUBS_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RLC format */
static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
uint32_t op1)
{
int32_t const16;
int r1, r2;
const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
r1 = MASK_OP_RLC_S1(ctx->opcode);
r2 = MASK_OP_RLC_D(ctx->opcode);
switch (op1) {
case OPC1_32_RLC_ADDI:
gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
break;
case OPC1_32_RLC_ADDIH:
gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
break;
case OPC1_32_RLC_ADDIH_A:
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
break;
case OPC1_32_RLC_MFCR:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
gen_mfcr(env, cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV:
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV_64:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r2);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_RLC_MOV_U:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV_H:
tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
break;
case OPC1_32_RLC_MOVH_A:
tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
break;
case OPC1_32_RLC_MTCR:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RR format */
static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r3, r2, r1;
TCGv temp;
r3 = MASK_OP_RR_D(ctx->opcode);
r2 = MASK_OP_RR_S2(ctx->opcode);
r1 = MASK_OP_RR_S1(ctx->opcode);
op2 = MASK_OP_RR_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_RR_ABS:
gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABS_B:
gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABS_H:
gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIF:
gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIF_B:
gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIF_H:
gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIFS:
gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIFS_H:
gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSS:
gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSS_H:
gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADD:
gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADD_B:
gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADD_H:
gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDC:
gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS:
gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS_H:
gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS_HU:
gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS_U:
gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDX:
gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_AND_EQ:
gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_AND_GE:
gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_AND_GE_U:
gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_AND_LT:
gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_AND_LT_U:
gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_AND_NE:
gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_EQ:
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQ_B:
gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQ_H:
gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQ_W:
gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQANY_B:
gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQANY_H:
gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_GE:
tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_GE_U:
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT:
tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_U:
tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_B:
gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_BU:
gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_H:
gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_HU:
gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_W:
gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_WU:
gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX:
tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_U:
tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_B:
gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_BU:
gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_H:
gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_HU:
gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN:
tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_U:
tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_B:
gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_BU:
gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_H:
gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_HU:
gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV:
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV_64:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
temp = tcg_temp_new();
CHECK_REG_PAIR(r3);
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
tcg_temp_free(temp);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_MOVS_64:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r3);
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_NE:
tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_OR_EQ:
gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_or_tl);
break;
case OPC2_32_RR_OR_GE:
gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_or_tl);
break;
case OPC2_32_RR_OR_GE_U:
gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_or_tl);
break;
case OPC2_32_RR_OR_LT:
gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_or_tl);
break;
case OPC2_32_RR_OR_LT_U:
gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_or_tl);
break;
case OPC2_32_RR_OR_NE:
gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_or_tl);
break;
case OPC2_32_RR_SAT_B:
gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
break;
case OPC2_32_RR_SAT_BU:
gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
break;
case OPC2_32_RR_SAT_H:
gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
break;
case OPC2_32_RR_SAT_HU:
gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
break;
case OPC2_32_RR_SH_EQ:
gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH_GE:
gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH_GE_U:
gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH_LT:
gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH_LT_U:
gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH_NE:
gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUB:
gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUB_B:
gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUB_H:
gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBC:
gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBS:
gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBS_U:
gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBS_H:
gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBS_HU:
gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBX:
gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_XOR_EQ:
gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
case OPC2_32_RR_XOR_GE:
gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
case OPC2_32_RR_XOR_GE_U:
gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
case OPC2_32_RR_XOR_LT:
gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
case OPC2_32_RR_XOR_LT_U:
gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
case OPC2_32_RR_XOR_NE:
gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r3, r2, r1;
TCGv temp;
r3 = MASK_OP_RR_D(ctx->opcode);
r2 = MASK_OP_RR_S2(ctx->opcode);
r1 = MASK_OP_RR_S1(ctx->opcode);
temp = tcg_temp_new();
op2 = MASK_OP_RR_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_RR_AND:
tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ANDN:
tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_CLO:
tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
break;
case OPC2_32_RR_CLO_H:
gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLS:
tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLS_H:
gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLZ:
tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
break;
case OPC2_32_RR_CLZ_H:
gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_NAND:
tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_NOR:
tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_OR:
tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ORN:
tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH:
gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH_H:
gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SHA:
gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SHA_H:
gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SHAS:
gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_XNOR:
tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_XOR:
tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2, n;
int r1, r2, r3;
TCGv temp;
op2 = MASK_OP_RR_OP2(ctx->opcode);
r3 = MASK_OP_RR_D(ctx->opcode);
r2 = MASK_OP_RR_S2(ctx->opcode);
r1 = MASK_OP_RR_S1(ctx->opcode);
n = MASK_OP_RR_N(ctx->opcode);
switch (op2) {
case OPC2_32_RR_ADD_A:
tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_ADDSC_A:
temp = tcg_temp_new();
tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
tcg_temp_free(temp);
break;
case OPC2_32_RR_ADDSC_AT:
temp = tcg_temp_new();
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
tcg_temp_free(temp);
break;
case OPC2_32_RR_EQ_A:
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_EQZ:
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
break;
case OPC2_32_RR_GE_A:
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_LT_A:
tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_MOV_A:
tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV_AA:
tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_MOV_D:
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_NE_A:
tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_NEZ_A:
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
break;
case OPC2_32_RR_SUB_A:
tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1;
op2 = MASK_OP_RR_OP2(ctx->opcode);
r1 = MASK_OP_RR_S1(ctx->opcode);
switch (op2) {
case OPC2_32_RR_JI:
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
case OPC2_32_RR_JLI:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
case OPC2_32_RR_CALLI:
gen_helper_1arg(call, ctx->next_pc);
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
case OPC2_32_RR_FCALLI:
gen_fcall_save_ctx(ctx);
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_exit_tb(NULL, 0);
ctx->bstate = BS_BRANCH;
}
static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
TCGv temp, temp2, temp3;
op2 = MASK_OP_RR_OP2(ctx->opcode);
r3 = MASK_OP_RR_D(ctx->opcode);
r2 = MASK_OP_RR_S2(ctx->opcode);
r1 = MASK_OP_RR_S1(ctx->opcode);
switch (op2) {
case OPC2_32_RR_BMERGE:
gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_BSPLIT:
CHECK_REG_PAIR(r3);
gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_DVINIT_B:
CHECK_REG_PAIR(r3);
gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DVINIT_BU:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_temp_new();
CHECK_REG_PAIR(r3);
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
tcg_gen_neg_tl(temp, temp3);
/* use cpu_PSW_AV to compare against 0 */
tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
temp, temp3);
tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
}
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
break;
case OPC2_32_RR_DVINIT_H:
CHECK_REG_PAIR(r3);
gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DVINIT_HU:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_temp_new();
CHECK_REG_PAIR(r3);
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
tcg_gen_neg_tl(temp, temp3);
/* use cpu_PSW_AV to compare against 0 */
tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
temp, temp3);
tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
}
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
break;
case OPC2_32_RR_DVINIT:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
CHECK_REG_PAIR(r3);
/* overflow = ((D[b] == 0) ||
((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
tcg_gen_and_tl(temp, temp, temp2);
tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
/* write result */
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
/* sign extend to high reg */
tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
case OPC2_32_RR_DVINIT_U:
/* overflow = (D[b] == 0) */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
/* write result */
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
/* zero extend to high reg*/
tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
break;
case OPC2_32_RR_PARITY:
gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_UNPACK:
CHECK_REG_PAIR(r3);
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CRC32:
if (tricore_feature(env, TRICORE_FEATURE_161)) {
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_DIV:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_DIV_U:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_MUL_F:
gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DIV_F:
gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_FTOI:
gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_ITOF:
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOUZ:
gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_UPDFL:
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RR1 Format */
static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
TCGv n;
TCGv_i64 temp64;
r1 = MASK_OP_RR1_S1(ctx->opcode);
r2 = MASK_OP_RR1_S2(ctx->opcode);
r3 = MASK_OP_RR1_D(ctx->opcode);
n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
op2 = MASK_OP_RR1_OP2(ctx->opcode);
switch (op2) {
case OPC2_32_RR1_MUL_H_32_LL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MUL_H_32_LU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MUL_H_32_UL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MUL_H_32_UU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MULM_H_64_LL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* reset AV bit */
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MULM_H_64_LU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* reset AV bit */
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MULM_H_64_UL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* reset AV bit */
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MULM_H_64_UU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
/* reset AV bit */
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_temp_free_i64(temp64);
break;
case OPC2_32_RR1_MULR_H_16_LL:
GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
break;
case OPC2_32_RR1_MULR_H_16_LU:
GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
break;
case OPC2_32_RR1_MULR_H_16_UL:
GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
break;
case OPC2_32_RR1_MULR_H_16_UU:
GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(n);
}
static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
uint32_t n;
TCGv temp, temp2;
r1 = MASK_OP_RR1_S1(ctx->opcode);
r2 = MASK_OP_RR1_S2(ctx->opcode);
r3 = MASK_OP_RR1_D(ctx->opcode);
n = MASK_OP_RR1_N(ctx->opcode);
op2 = MASK_OP_RR1_OP2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
switch (op2) {
case OPC2_32_RR1_MUL_Q_32:
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
break;
case OPC2_32_RR1_MUL_Q_64:
CHECK_REG_PAIR(r3);
gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, 0);
break;
case OPC2_32_RR1_MUL_Q_32_L:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
break;
case OPC2_32_RR1_MUL_Q_64_L:
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
break;
case OPC2_32_RR1_MUL_Q_32_U:
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
break;
case OPC2_32_RR1_MUL_Q_64_U:
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
break;
case OPC2_32_RR1_MUL_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RR1_MUL_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RR1_MULR_Q_32_L:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RR1_MULR_Q_32_U:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
/* RR2 format */
static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
op2 = MASK_OP_RR2_OP2(ctx->opcode);
r1 = MASK_OP_RR2_S1(ctx->opcode);
r2 = MASK_OP_RR2_S2(ctx->opcode);
r3 = MASK_OP_RR2_D(ctx->opcode);
switch (op2) {
case OPC2_32_RR2_MUL_32:
gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MUL_64:
CHECK_REG_PAIR(r3);
gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MULS_32:
gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MUL_U_64:
CHECK_REG_PAIR(r3);
gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MULS_U_32:
gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RRPW format */
static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3;
int32_t pos, width;
op2 = MASK_OP_RRPW_OP2(ctx->opcode);
r1 = MASK_OP_RRPW_S1(ctx->opcode);
r2 = MASK_OP_RRPW_S2(ctx->opcode);
r3 = MASK_OP_RRPW_D(ctx->opcode);
pos = MASK_OP_RRPW_POS(ctx->opcode);
width = MASK_OP_RRPW_WIDTH(ctx->opcode);
switch (op2) {
case OPC2_32_RRPW_EXTR:
if (pos + width <= 31) {
/* optimize special cases */
if ((pos == 0) && (width == 8)) {
tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
} else if ((pos == 0) && (width == 16)) {
tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
} else {
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
}
}
break;
case OPC2_32_RRPW_EXTR_U:
if (width == 0) {
tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
} else {
tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
}
break;
case OPC2_32_RRPW_IMASK:
CHECK_REG_PAIR(r3);
if (pos + width <= 31) {
tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
}
break;
case OPC2_32_RRPW_INSERT:
if (pos + width <= 31) {
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
width, pos);
}
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RRR format */
static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3, r4;
TCGv temp;
op2 = MASK_OP_RRR_OP2(ctx->opcode);
r1 = MASK_OP_RRR_S1(ctx->opcode);
r2 = MASK_OP_RRR_S2(ctx->opcode);
r3 = MASK_OP_RRR_S3(ctx->opcode);
r4 = MASK_OP_RRR_D(ctx->opcode);
switch (op2) {
case OPC2_32_RRR_CADD:
gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
cpu_gpr_d[r4], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_CADDN:
gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_CSUB:
gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_CSUBN:
gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_SEL:
temp = tcg_const_i32(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
tcg_temp_free(temp);
break;
case OPC2_32_RRR_SELN:
temp = tcg_const_i32(0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
tcg_temp_free(temp);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3, r4;
op2 = MASK_OP_RRR_OP2(ctx->opcode);
r1 = MASK_OP_RRR_S1(ctx->opcode);
r2 = MASK_OP_RRR_S2(ctx->opcode);
r3 = MASK_OP_RRR_S3(ctx->opcode);
r4 = MASK_OP_RRR_D(ctx->opcode);
switch (op2) {
case OPC2_32_RRR_DVADJ:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP_U:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX_U:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN_U:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_PACK:
CHECK_REG_PAIR(r3);
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RRR_ADD_F:
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_SUB_F:
gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_MADD_F:
gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_MSUB_F:
gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r3]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RRR2 format */
static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4;
op2 = MASK_OP_RRR2_OP2(ctx->opcode);
r1 = MASK_OP_RRR2_S1(ctx->opcode);
r2 = MASK_OP_RRR2_S2(ctx->opcode);
r3 = MASK_OP_RRR2_S3(ctx->opcode);
r4 = MASK_OP_RRR2_D(ctx->opcode);
switch (op2) {
case OPC2_32_RRR2_MADD_32:
gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADD_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_32:
gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADD_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_U_32:
gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4;
op2 = MASK_OP_RRR2_OP2(ctx->opcode);
r1 = MASK_OP_RRR2_S1(ctx->opcode);
r2 = MASK_OP_RRR2_S2(ctx->opcode);
r3 = MASK_OP_RRR2_S3(ctx->opcode);
r4 = MASK_OP_RRR2_D(ctx->opcode);
switch (op2) {
case OPC2_32_RRR2_MSUB_32:
gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUB_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_32:
gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUB_U_64:
gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_U_32:
gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RRR1 format */
static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
r2 = MASK_OP_RRR1_S2(ctx->opcode);
r3 = MASK_OP_RRR1_S3(ctx->opcode);
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
switch (op2) {
case OPC2_32_RRR1_MADD_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADD_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADD_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADD_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDM_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDM_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDM_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDM_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDMS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDMS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDMS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDMS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDR_H_LL:
gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDR_H_LU:
gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDR_H_UL:
gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDR_H_UU:
gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDRS_H_LL:
gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDRS_H_LU:
gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDRS_H_UL:
gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDRS_H_UU:
gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
TCGv temp, temp2;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
r2 = MASK_OP_RRR1_S2(ctx->opcode);
r3 = MASK_OP_RRR1_S3(ctx->opcode);
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
temp = tcg_const_i32(n);
temp2 = tcg_temp_new();
switch (op2) {
case OPC2_32_RRR1_MADD_Q_32:
gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, 32, env);
break;
case OPC2_32_RRR1_MADD_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, env);
break;
case OPC2_32_RRR1_MADD_Q_32_L:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16, env);
break;
case OPC2_32_RRR1_MADD_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n, env);
break;
case OPC2_32_RRR1_MADD_Q_32_U:
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16, env);
break;
case OPC2_32_RRR1_MADD_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n, env);
break;
case OPC2_32_RRR1_MADD_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_32:
gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, 32);
break;
case OPC2_32_RRR1_MADDS_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
break;
case OPC2_32_RRR1_MADDS_Q_32_L:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MADDS_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MADDS_Q_32_U:
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MADDS_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MADDS_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDR_H_64_UL:
CHECK_REG_PAIR(r3);
gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MADDRS_H_64_UL:
CHECK_REG_PAIR(r3);
gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MADDR_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDR_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDRS_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDRS_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
r2 = MASK_OP_RRR1_S2(ctx->opcode);
r3 = MASK_OP_RRR1_S3(ctx->opcode);
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
switch (op2) {
case OPC2_32_RRR1_MADDSU_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSU_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSU_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSU_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUS_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUS_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUS_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUS_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUM_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUM_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUM_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUM_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUR_H_16_LL:
gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUR_H_16_LU:
gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUR_H_16_UL:
gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUR_H_16_UU:
gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSURS_H_16_LL:
gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSURS_H_16_LU:
gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSURS_H_16_UL:
gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSURS_H_16_UU:
gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
r2 = MASK_OP_RRR1_S2(ctx->opcode);
r3 = MASK_OP_RRR1_S3(ctx->opcode);
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
switch (op2) {
case OPC2_32_RRR1_MSUB_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUB_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUB_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUB_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBM_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBM_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBM_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBM_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBMS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBMS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBMS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBMS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBR_H_LL:
gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBR_H_LU:
gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBR_H_UL:
gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBR_H_UU:
gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBRS_H_LL:
gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBRS_H_LU:
gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBRS_H_UL:
gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBRS_H_UU:
gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
TCGv temp, temp2;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
r2 = MASK_OP_RRR1_S2(ctx->opcode);
r3 = MASK_OP_RRR1_S3(ctx->opcode);
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
temp = tcg_const_i32(n);
temp2 = tcg_temp_new();
switch (op2) {
case OPC2_32_RRR1_MSUB_Q_32:
gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, 32, env);
break;
case OPC2_32_RRR1_MSUB_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, env);
break;
case OPC2_32_RRR1_MSUB_Q_32_L:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16, env);
break;
case OPC2_32_RRR1_MSUB_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n, env);
break;
case OPC2_32_RRR1_MSUB_Q_32_U:
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16, env);
break;
case OPC2_32_RRR1_MSUB_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n, env);
break;
case OPC2_32_RRR1_MSUB_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_32:
gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, 32);
break;
case OPC2_32_RRR1_MSUBS_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_L:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MSUBS_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_U:
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MSUBS_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBR_H_64_UL:
CHECK_REG_PAIR(r3);
gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MSUBRS_H_64_UL:
CHECK_REG_PAIR(r3);
gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MSUBR_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBR_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBRS_Q_32_LL:
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBRS_Q_32_UU:
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
}
static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
r2 = MASK_OP_RRR1_S2(ctx->opcode);
r3 = MASK_OP_RRR1_S3(ctx->opcode);
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
switch (op2) {
case OPC2_32_RRR1_MSUBAD_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBAD_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBAD_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBAD_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADS_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADS_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADS_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADS_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADM_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADM_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADM_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADM_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADR_H_16_LL:
gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADR_H_16_LU:
gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADR_H_16_UL:
gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADR_H_16_UU:
gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADRS_H_16_LL:
gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADRS_H_16_LU:
gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADRS_H_16_UL:
gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADRS_H_16_UU:
gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/* RRRR format */
static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3, r4;
TCGv tmp_width, tmp_pos;
r1 = MASK_OP_RRRR_S1(ctx->opcode);
r2 = MASK_OP_RRRR_S2(ctx->opcode);
r3 = MASK_OP_RRRR_S3(ctx->opcode);
r4 = MASK_OP_RRRR_D(ctx->opcode);
op2 = MASK_OP_RRRR_OP2(ctx->opcode);
tmp_pos = tcg_temp_new();
tmp_width = tcg_temp_new();
switch (op2) {
case OPC2_32_RRRR_DEXTR:
tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
if (r1 == r2) {
tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
} else {
tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
}
break;
case OPC2_32_RRRR_EXTR:
case OPC2_32_RRRR_EXTR_U:
CHECK_REG_PAIR(r3);
tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
if (op2 == OPC2_32_RRRR_EXTR) {
tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
} else {
tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
}
break;
case OPC2_32_RRRR_INSERT:
CHECK_REG_PAIR(r3);
tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
tmp_pos);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(tmp_pos);
tcg_temp_free(tmp_width);
}
/* RRRW format */
static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3, r4;
int32_t width;
TCGv temp, temp2;
op2 = MASK_OP_RRRW_OP2(ctx->opcode);
r1 = MASK_OP_RRRW_S1(ctx->opcode);
r2 = MASK_OP_RRRW_S2(ctx->opcode);
r3 = MASK_OP_RRRW_S3(ctx->opcode);
r4 = MASK_OP_RRRW_D(ctx->opcode);
width = MASK_OP_RRRW_WIDTH(ctx->opcode);
temp = tcg_temp_new();
switch (op2) {
case OPC2_32_RRRW_EXTR:
tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_addi_tl(temp, temp, width);
tcg_gen_subfi_tl(temp, 32, temp);
tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
break;
case OPC2_32_RRRW_EXTR_U:
if (width == 0) {
tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
} else {
tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
}
break;
case OPC2_32_RRRW_IMASK:
temp2 = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_movi_tl(temp2, (1 << width) - 1);
tcg_gen_shl_tl(temp2, temp2, temp);
tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
tcg_temp_free(temp2);
break;
case OPC2_32_RRRW_INSERT:
temp2 = tcg_temp_new();
tcg_gen_movi_tl(temp, width);
tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
tcg_temp_free(temp2);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
/* SYS Format*/
static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
{
uint32_t op2;
uint32_t r1;
TCGLabel *l1;
TCGv tmp;
op2 = MASK_OP_SYS_OP2(ctx->opcode);
r1 = MASK_OP_SYS_S1D(ctx->opcode);
switch (op2) {
case OPC2_32_SYS_DEBUG:
/* raise EXCP_DEBUG */
break;
case OPC2_32_SYS_DISABLE:
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
break;
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
break;
case OPC2_32_SYS_ISYNC:
break;
case OPC2_32_SYS_NOP:
break;
case OPC2_32_SYS_RET:
gen_compute_branch(ctx, op2, 0, 0, 0, 0);
break;
case OPC2_32_SYS_FRET:
gen_fret(ctx);
break;
case OPC2_32_SYS_RFE:
gen_helper_rfe(cpu_env);
tcg_gen_exit_tb(NULL, 0);
ctx->bstate = BS_BRANCH;
break;
case OPC2_32_SYS_RFM:
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
tmp = tcg_temp_new();
l1 = gen_new_label();
tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
gen_helper_rfm(cpu_env);
gen_set_label(l1);
tcg_gen_exit_tb(NULL, 0);
ctx->bstate = BS_BRANCH;
tcg_temp_free(tmp);
} else {
/* generate privilege trap */
}
break;
case OPC2_32_SYS_RSLCX:
gen_helper_rslcx(cpu_env);
break;
case OPC2_32_SYS_SVLCX:
gen_helper_svlcx(cpu_env);
break;
case OPC2_32_SYS_RESTORE:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
} /* else raise privilege trap */
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_SYS_TRAPSV:
l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
gen_set_label(l1);
break;
case OPC2_32_SYS_TRAPV:
l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
gen_set_label(l1);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
{
int op1;
int32_t r1, r2, r3;
int32_t address, const16;
int8_t b, const4;
int32_t bpos;
TCGv temp, temp2, temp3;
op1 = MASK_OP_MAJOR(ctx->opcode);
/* handle JNZ.T opcode only being 7 bit long */
if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
op1 = OPCM_32_BRN_JTT;
}
switch (op1) {
/* ABS-format */
case OPCM_32_ABS_LDW:
decode_abs_ldw(env, ctx);
break;
case OPCM_32_ABS_LDB:
decode_abs_ldb(env, ctx);
break;
case OPCM_32_ABS_LDMST_SWAP:
decode_abs_ldst_swap(env, ctx);
break;
case OPCM_32_ABS_LDST_CONTEXT:
decode_abs_ldst_context(env, ctx);
break;
case OPCM_32_ABS_STORE:
decode_abs_store(env, ctx);
break;
case OPCM_32_ABS_STOREB_H:
decode_abs_storeb_h(env, ctx);
break;
case OPC1_32_ABS_STOREQ:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
temp2 = tcg_temp_new();
tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
tcg_temp_free(temp2);
tcg_temp_free(temp);
break;
case OPC1_32_ABS_LD_Q:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
tcg_temp_free(temp);
break;
case OPC1_32_ABS_LEA:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
break;
/* ABSB-format */
case OPC1_32_ABSB_ST_T:
address = MASK_OP_ABS_OFF18(ctx->opcode);
b = MASK_OP_ABSB_B(ctx->opcode);
bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
temp = tcg_const_i32(EA_ABS_FORMAT(address));
temp2 = tcg_temp_new();
tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
tcg_gen_ori_tl(temp2, temp2, (b << bpos));
tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
/* B-format */
case OPC1_32_B_CALL:
case OPC1_32_B_CALLA:
case OPC1_32_B_FCALL:
case OPC1_32_B_FCALLA:
case OPC1_32_B_J:
case OPC1_32_B_JA:
case OPC1_32_B_JL:
case OPC1_32_B_JLA:
address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, 0, address);
break;
/* Bit-format */
case OPCM_32_BIT_ANDACC:
decode_bit_andacc(env, ctx);
break;
case OPCM_32_BIT_LOGICAL_T1:
decode_bit_logical_t(env, ctx);
break;
case OPCM_32_BIT_INSERT:
decode_bit_insert(env, ctx);
break;
case OPCM_32_BIT_LOGICAL_T2:
decode_bit_logical_t2(env, ctx);
break;
case OPCM_32_BIT_ORAND:
decode_bit_orand(env, ctx);
break;
case OPCM_32_BIT_SH_LOGIC1:
decode_bit_sh_logic1(env, ctx);
break;
case OPCM_32_BIT_SH_LOGIC2:
decode_bit_sh_logic2(env, ctx);
break;
/* BO Format */
case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
decode_bo_addrmode_post_pre_base(env, ctx);
break;
case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
decode_bo_addrmode_bitreverse_circular(env, ctx);
break;
case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
decode_bo_addrmode_ld_post_pre_base(env, ctx);
break;
case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
break;
case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
decode_bo_addrmode_stctx_post_pre_base(env, ctx);
break;
case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
break;
/* BOL-format */
case OPC1_32_BOL_LD_A_LONGOFF:
case OPC1_32_BOL_LD_W_LONGOFF:
case OPC1_32_BOL_LEA_LONGOFF:
case OPC1_32_BOL_ST_W_LONGOFF:
case OPC1_32_BOL_ST_A_LONGOFF:
case OPC1_32_BOL_LD_B_LONGOFF:
case OPC1_32_BOL_LD_BU_LONGOFF:
case OPC1_32_BOL_LD_H_LONGOFF:
case OPC1_32_BOL_LD_HU_LONGOFF:
case OPC1_32_BOL_ST_B_LONGOFF:
case OPC1_32_BOL_ST_H_LONGOFF:
decode_bol_opc(env, ctx, op1);
break;
/* BRC Format */
case OPCM_32_BRC_EQ_NEQ:
case OPCM_32_BRC_GE:
case OPCM_32_BRC_JLT:
case OPCM_32_BRC_JNE:
const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
r1 = MASK_OP_BRC_S1(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, const4, address);
break;
/* BRN Format */
case OPCM_32_BRN_JTT:
address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
r1 = MASK_OP_BRN_S1(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
break;
/* BRR Format */
case OPCM_32_BRR_EQ_NEQ:
case OPCM_32_BRR_ADDR_EQ_NEQ:
case OPCM_32_BRR_GE:
case OPCM_32_BRR_JLT:
case OPCM_32_BRR_JNE:
case OPCM_32_BRR_JNZ:
case OPCM_32_BRR_LOOP:
address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
r2 = MASK_OP_BRR_S2(ctx->opcode);
r1 = MASK_OP_BRR_S1(ctx->opcode);
gen_compute_branch(ctx, op1, r1, r2, 0, address);
break;
/* RC Format */
case OPCM_32_RC_LOGICAL_SHIFT:
decode_rc_logical_shift(env, ctx);
break;
case OPCM_32_RC_ACCUMULATOR:
decode_rc_accumulator(env, ctx);
break;
case OPCM_32_RC_SERVICEROUTINE:
decode_rc_serviceroutine(env, ctx);
break;
case OPCM_32_RC_MUL:
decode_rc_mul(env, ctx);
break;
/* RCPW Format */
case OPCM_32_RCPW_MASK_INSERT:
decode_rcpw_insert(env, ctx);
break;
/* RCRR Format */
case OPC1_32_RCRR_INSERT:
r1 = MASK_OP_RCRR_S1(ctx->opcode);
r2 = MASK_OP_RCRR_S3(ctx->opcode);
r3 = MASK_OP_RCRR_D(ctx->opcode);
const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
temp = tcg_const_i32(const16);
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
CHECK_REG_PAIR(r3);
tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT:
decode_rcrw_insert(env, ctx);
break;
/* RCR Format */
case OPCM_32_RCR_COND_SELECT:
decode_rcr_cond_select(env, ctx);
break;
case OPCM_32_RCR_MADD:
decode_rcr_madd(env, ctx);
break;
case OPCM_32_RCR_MSUB:
decode_rcr_msub(env, ctx);
break;
/* RLC Format */
case OPC1_32_RLC_ADDI:
case OPC1_32_RLC_ADDIH:
case OPC1_32_RLC_ADDIH_A:
case OPC1_32_RLC_MFCR:
case OPC1_32_RLC_MOV:
case OPC1_32_RLC_MOV_64:
case OPC1_32_RLC_MOV_U:
case OPC1_32_RLC_MOV_H:
case OPC1_32_RLC_MOVH_A:
case OPC1_32_RLC_MTCR:
decode_rlc_opc(env, ctx, op1);
break;
/* RR Format */
case OPCM_32_RR_ACCUMULATOR:
decode_rr_accumulator(env, ctx);
break;
case OPCM_32_RR_LOGICAL_SHIFT:
decode_rr_logical_shift(env, ctx);
break;
case OPCM_32_RR_ADDRESS:
decode_rr_address(env, ctx);
break;
case OPCM_32_RR_IDIRECT:
decode_rr_idirect(env, ctx);
break;
case OPCM_32_RR_DIVIDE:
decode_rr_divide(env, ctx);
break;
/* RR1 Format */
case OPCM_32_RR1_MUL:
decode_rr1_mul(env, ctx);
break;
case OPCM_32_RR1_MULQ:
decode_rr1_mulq(env, ctx);
break;
/* RR2 format */
case OPCM_32_RR2_MUL:
decode_rr2_mul(env, ctx);
break;
/* RRPW format */
case OPCM_32_RRPW_EXTRACT_INSERT:
decode_rrpw_extract_insert(env, ctx);
break;
case OPC1_32_RRPW_DEXTR:
r1 = MASK_OP_RRPW_S1(ctx->opcode);
r2 = MASK_OP_RRPW_S2(ctx->opcode);
r3 = MASK_OP_RRPW_D(ctx->opcode);
const16 = MASK_OP_RRPW_POS(ctx->opcode);
if (r1 == r2) {
tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
} else {
temp = tcg_temp_new();
tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
tcg_temp_free(temp);
}
break;
/* RRR Format */
case OPCM_32_RRR_COND_SELECT:
decode_rrr_cond_select(env, ctx);
break;
case OPCM_32_RRR_DIVIDE:
decode_rrr_divide(env, ctx);
break;
/* RRR2 Format */
case OPCM_32_RRR2_MADD:
decode_rrr2_madd(env, ctx);
break;
case OPCM_32_RRR2_MSUB:
decode_rrr2_msub(env, ctx);
break;
/* RRR1 format */
case OPCM_32_RRR1_MADD:
decode_rrr1_madd(env, ctx);
break;
case OPCM_32_RRR1_MADDQ_H:
decode_rrr1_maddq_h(env, ctx);
break;
case OPCM_32_RRR1_MADDSU_H:
decode_rrr1_maddsu_h(env, ctx);
break;
case OPCM_32_RRR1_MSUB_H:
decode_rrr1_msub(env, ctx);
break;
case OPCM_32_RRR1_MSUB_Q:
decode_rrr1_msubq_h(env, ctx);
break;
case OPCM_32_RRR1_MSUBAD_H:
decode_rrr1_msubad_h(env, ctx);
break;
/* RRRR format */
case OPCM_32_RRRR_EXTRACT_INSERT:
decode_rrrr_extract_insert(env, ctx);
break;
/* RRRW format */
case OPCM_32_RRRW_EXTRACT_INSERT:
decode_rrrw_extract_insert(env, ctx);
break;
/* SYS format */
case OPCM_32_SYS_INTERRUPTS:
decode_sys_interrupts(env, ctx);
break;
case OPC1_32_SYS_RSTV:
tcg_gen_movi_tl(cpu_PSW_V, 0);
tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
{
/* 16-Bit Instruction */
if ((ctx->opcode & 0x1) == 0) {
ctx->next_pc = ctx->pc + 2;
decode_16Bit_opc(env, ctx);
/* 32-Bit Instruction */
} else {
ctx->next_pc = ctx->pc + 4;
decode_32Bit_opc(env, ctx);
}
}
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUTriCoreState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
num_insns = 0;
max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
if (singlestep) {
max_insns = 1;
}
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
pc_start = tb->pc;
ctx.pc = pc_start;
ctx.saved_pc = -1;
ctx.tb = tb;
ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.bstate = BS_NONE;
ctx.mem_idx = cpu_mmu_index(env, false);
tcg_clear_temp_count();
gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
tcg_gen_insn_start(ctx.pc);
num_insns++;
ctx.opcode = cpu_ldl_code(env, ctx.pc);
decode_opc(env, &ctx, 0);
if (num_insns >= max_insns || tcg_op_buf_full()) {
gen_save_pc(ctx.next_pc);
tcg_gen_exit_tb(NULL, 0);
break;
}
ctx.pc = ctx.next_pc;
}
gen_tb_end(tb, num_insns);
tb->size = ctx.pc - pc_start;
tb->icount = num_insns;
if (tcg_check_temp_count()) {
printf("LEAK at %08x\n", env->PC);
}
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(cs, pc_start, ctx.pc - pc_start);
qemu_log("\n");
qemu_log_unlock();
}
#endif
}
void
restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb,
target_ulong *data)
{
env->PC = data[0];
}
/*
*
* Initialization
*
*/
void cpu_state_reset(CPUTriCoreState *env)
{
/* Reset Regs to Default Value */
env->PSW = 0xb80;
fpu_set_state(env);
}
static void tricore_tcg_init_csfr(void)
{
cpu_PCXI = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PCXI), "PCXI");
cpu_PSW = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW), "PSW");
cpu_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PC), "PC");
cpu_ICR = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, ICR), "ICR");
}
void tricore_tcg_init(void)
{
int i;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, gpr_a[i]),
regnames_a[i]);
}
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, gpr_d[i]),
regnames_d[i]);
}
tricore_tcg_init_csfr();
/* init PSW flag cache */
cpu_PSW_C = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_C),
"PSW_C");
cpu_PSW_V = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_V),
"PSW_V");
cpu_PSW_SV = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_SV),
"PSW_SV");
cpu_PSW_AV = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_AV),
"PSW_AV");
cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_SAV),
"PSW_SAV");
}
|
pmp-tool/PMP | src/qemu/src-pmp/include/hw/arm/xlnx-versal.h | <reponame>pmp-tool/PMP
/*
* Model of the Xilinx Versal
*
* Copyright (c) 2018 Xilinx Inc.
* Written by <NAME>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
#ifndef XLNX_VERSAL_H
#define XLNX_VERSAL_H
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/intc/arm_gicv3.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
#define XLNX_VERSAL_NR_ACPUS 2
#define XLNX_VERSAL_NR_UARTS 2
#define XLNX_VERSAL_NR_GEMS 2
#define XLNX_VERSAL_NR_IRQS 192
typedef struct Versal {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
struct {
struct {
MemoryRegion mr;
ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
GICv3State gic;
} apu;
} fpd;
MemoryRegion mr_ps;
struct {
/* 4 ranges to access DDR. */
MemoryRegion mr_ddr_ranges[4];
} noc;
struct {
MemoryRegion mr_ocm;
struct {
SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
} iou;
} lpd;
struct {
MemoryRegion *mr_ddr;
uint32_t psci_conduit;
} cfg;
} Versal;
/* Memory-map and IRQ definitions. Copied a subset from
* auto-generated files. */
#define VERSAL_GIC_MAINT_IRQ 9
#define VERSAL_TIMER_VIRT_IRQ 11
#define VERSAL_TIMER_S_EL1_IRQ 13
#define VERSAL_TIMER_NS_EL1_IRQ 14
#define VERSAL_TIMER_NS_EL2_IRQ 10
#define VERSAL_UART0_IRQ_0 18
#define VERSAL_UART1_IRQ_0 19
#define VERSAL_GEM0_IRQ_0 56
#define VERSAL_GEM0_WAKE_IRQ_0 57
#define VERSAL_GEM1_IRQ_0 58
#define VERSAL_GEM1_WAKE_IRQ_0 59
/* Architecturally reserved IRQs suitable for virtualization. */
#define VERSAL_RSVD_IRQ_FIRST 111
#define VERSAL_RSVD_IRQ_LAST 118
#define MM_TOP_RSVD 0xa0000000U
#define MM_TOP_RSVD_SIZE 0x4000000
#define MM_GIC_APU_DIST_MAIN 0xf9000000U
#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
#define MM_GIC_APU_REDIST_0 0xf9080000U
#define MM_GIC_APU_REDIST_0_SIZE 0x80000
#define MM_UART0 0xff000000U
#define MM_UART0_SIZE 0x10000
#define MM_UART1 0xff010000U
#define MM_UART1_SIZE 0x10000
#define MM_GEM0 0xff0c0000U
#define MM_GEM0_SIZE 0x10000
#define MM_GEM1 0xff0d0000U
#define MM_GEM1_SIZE 0x10000
#define MM_OCM 0xfffc0000U
#define MM_OCM_SIZE 0x40000
#define MM_TOP_DDR 0x0
#define MM_TOP_DDR_SIZE 0x80000000U
#define MM_TOP_DDR_2 0x800000000ULL
#define MM_TOP_DDR_2_SIZE 0x800000000ULL
#define MM_TOP_DDR_3 0xc000000000ULL
#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
#define MM_TOP_DDR_4 0x10000000000ULL
#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
#define MM_PSM_START 0xffc80000U
#define MM_PSM_END 0xffcf0000U
#define MM_CRL 0xff5e0000U
#define MM_CRL_SIZE 0x300000
#define MM_IOU_SCNTR 0xff130000U
#define MM_IOU_SCNTR_SIZE 0x10000
#define MM_IOU_SCNTRS 0xff140000U
#define MM_IOU_SCNTRS_SIZE 0x10000
#define MM_FPD_CRF 0xfd1a0000U
#define MM_FPD_CRF_SIZE 0x140000
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/backends/cryptodev-vhost-user.c | <gh_stars>1-10
/*
* QEMU Cryptodev backend for QEMU cipher APIs
*
* Copyright (c) 2016 HUAWEI TECHNOLOGIES CO., LTD.
*
* Authors:
* Gonglei <<EMAIL>>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*/
#include "qemu/osdep.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "qemu/error-report.h"
#include "hw/virtio/vhost-user.h"
#include "standard-headers/linux/virtio_crypto.h"
#include "sysemu/cryptodev-vhost.h"
#include "chardev/char-fe.h"
#include "sysemu/cryptodev-vhost-user.h"
/**
* @TYPE_CRYPTODEV_BACKEND_VHOST_USER:
* name of backend that uses vhost user server
*/
#define TYPE_CRYPTODEV_BACKEND_VHOST_USER "cryptodev-vhost-user"
#define CRYPTODEV_BACKEND_VHOST_USER(obj) \
OBJECT_CHECK(CryptoDevBackendVhostUser, \
(obj), TYPE_CRYPTODEV_BACKEND_VHOST_USER)
typedef struct CryptoDevBackendVhostUser {
CryptoDevBackend parent_obj;
VhostUserState vhost_user;
CharBackend chr;
char *chr_name;
bool opened;
CryptoDevBackendVhost *vhost_crypto[MAX_CRYPTO_QUEUE_NUM];
} CryptoDevBackendVhostUser;
static int
cryptodev_vhost_user_running(
CryptoDevBackendVhost *crypto)
{
return crypto ? 1 : 0;
}
CryptoDevBackendVhost *
cryptodev_vhost_user_get_vhost(
CryptoDevBackendClient *cc,
CryptoDevBackend *b,
uint16_t queue)
{
CryptoDevBackendVhostUser *s =
CRYPTODEV_BACKEND_VHOST_USER(b);
assert(cc->type == CRYPTODEV_BACKEND_TYPE_VHOST_USER);
assert(queue < MAX_CRYPTO_QUEUE_NUM);
return s->vhost_crypto[queue];
}
static void cryptodev_vhost_user_stop(int queues,
CryptoDevBackendVhostUser *s)
{
size_t i;
for (i = 0; i < queues; i++) {
if (!cryptodev_vhost_user_running(s->vhost_crypto[i])) {
continue;
}
cryptodev_vhost_cleanup(s->vhost_crypto[i]);
s->vhost_crypto[i] = NULL;
}
}
static int
cryptodev_vhost_user_start(int queues,
CryptoDevBackendVhostUser *s)
{
CryptoDevBackendVhostOptions options;
CryptoDevBackend *b = CRYPTODEV_BACKEND(s);
int max_queues;
size_t i;
for (i = 0; i < queues; i++) {
if (cryptodev_vhost_user_running(s->vhost_crypto[i])) {
continue;
}
options.opaque = &s->vhost_user;
options.backend_type = VHOST_BACKEND_TYPE_USER;
options.cc = b->conf.peers.ccs[i];
s->vhost_crypto[i] = cryptodev_vhost_init(&options);
if (!s->vhost_crypto[i]) {
error_report("failed to init vhost_crypto for queue %zu", i);
goto err;
}
if (i == 0) {
max_queues =
cryptodev_vhost_get_max_queues(s->vhost_crypto[i]);
if (queues > max_queues) {
error_report("you are asking more queues than supported: %d",
max_queues);
goto err;
}
}
}
return 0;
err:
cryptodev_vhost_user_stop(i + 1, s);
return -1;
}
static Chardev *
cryptodev_vhost_claim_chardev(CryptoDevBackendVhostUser *s,
Error **errp)
{
Chardev *chr;
if (s->chr_name == NULL) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE,
"chardev", "a valid character device");
return NULL;
}
chr = qemu_chr_find(s->chr_name);
if (chr == NULL) {
error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND,
"Device '%s' not found", s->chr_name);
return NULL;
}
return chr;
}
static void cryptodev_vhost_user_event(void *opaque, int event)
{
CryptoDevBackendVhostUser *s = opaque;
CryptoDevBackend *b = CRYPTODEV_BACKEND(s);
int queues = b->conf.peers.queues;
assert(queues < MAX_CRYPTO_QUEUE_NUM);
switch (event) {
case CHR_EVENT_OPENED:
if (cryptodev_vhost_user_start(queues, s) < 0) {
exit(1);
}
b->ready = true;
break;
case CHR_EVENT_CLOSED:
b->ready = false;
cryptodev_vhost_user_stop(queues, s);
break;
}
}
static void cryptodev_vhost_user_init(
CryptoDevBackend *backend, Error **errp)
{
int queues = backend->conf.peers.queues;
size_t i;
Error *local_err = NULL;
Chardev *chr;
CryptoDevBackendClient *cc;
CryptoDevBackendVhostUser *s =
CRYPTODEV_BACKEND_VHOST_USER(backend);
chr = cryptodev_vhost_claim_chardev(s, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
s->opened = true;
for (i = 0; i < queues; i++) {
cc = cryptodev_backend_new_client(
"cryptodev-vhost-user", NULL);
cc->info_str = g_strdup_printf("cryptodev-vhost-user%zu to %s ",
i, chr->label);
cc->queue_index = i;
cc->type = CRYPTODEV_BACKEND_TYPE_VHOST_USER;
backend->conf.peers.ccs[i] = cc;
if (i == 0) {
if (!qemu_chr_fe_init(&s->chr, chr, &local_err)) {
error_propagate(errp, local_err);
return;
}
}
}
if (!vhost_user_init(&s->vhost_user, &s->chr, errp)) {
return;
}
qemu_chr_fe_set_handlers(&s->chr, NULL, NULL,
cryptodev_vhost_user_event, NULL, s, NULL, true);
backend->conf.crypto_services =
1u << VIRTIO_CRYPTO_SERVICE_CIPHER |
1u << VIRTIO_CRYPTO_SERVICE_HASH |
1u << VIRTIO_CRYPTO_SERVICE_MAC;
backend->conf.cipher_algo_l = 1u << VIRTIO_CRYPTO_CIPHER_AES_CBC;
backend->conf.hash_algo = 1u << VIRTIO_CRYPTO_HASH_SHA1;
backend->conf.max_size = UINT64_MAX;
backend->conf.max_cipher_key_len = VHOST_USER_MAX_CIPHER_KEY_LEN;
backend->conf.max_auth_key_len = VHOST_USER_MAX_AUTH_KEY_LEN;
}
static int64_t cryptodev_vhost_user_sym_create_session(
CryptoDevBackend *backend,
CryptoDevBackendSymSessionInfo *sess_info,
uint32_t queue_index, Error **errp)
{
CryptoDevBackendClient *cc =
backend->conf.peers.ccs[queue_index];
CryptoDevBackendVhost *vhost_crypto;
uint64_t session_id = 0;
int ret;
vhost_crypto = cryptodev_vhost_user_get_vhost(cc, backend, queue_index);
if (vhost_crypto) {
struct vhost_dev *dev = &(vhost_crypto->dev);
ret = dev->vhost_ops->vhost_crypto_create_session(dev,
sess_info,
&session_id);
if (ret < 0) {
return -1;
} else {
return session_id;
}
}
return -1;
}
static int cryptodev_vhost_user_sym_close_session(
CryptoDevBackend *backend,
uint64_t session_id,
uint32_t queue_index, Error **errp)
{
CryptoDevBackendClient *cc =
backend->conf.peers.ccs[queue_index];
CryptoDevBackendVhost *vhost_crypto;
int ret;
vhost_crypto = cryptodev_vhost_user_get_vhost(cc, backend, queue_index);
if (vhost_crypto) {
struct vhost_dev *dev = &(vhost_crypto->dev);
ret = dev->vhost_ops->vhost_crypto_close_session(dev,
session_id);
if (ret < 0) {
return -1;
} else {
return 0;
}
}
return -1;
}
static void cryptodev_vhost_user_cleanup(
CryptoDevBackend *backend,
Error **errp)
{
CryptoDevBackendVhostUser *s =
CRYPTODEV_BACKEND_VHOST_USER(backend);
size_t i;
int queues = backend->conf.peers.queues;
CryptoDevBackendClient *cc;
cryptodev_vhost_user_stop(queues, s);
for (i = 0; i < queues; i++) {
cc = backend->conf.peers.ccs[i];
if (cc) {
cryptodev_backend_free_client(cc);
backend->conf.peers.ccs[i] = NULL;
}
}
vhost_user_cleanup(&s->vhost_user);
}
static void cryptodev_vhost_user_set_chardev(Object *obj,
const char *value, Error **errp)
{
CryptoDevBackendVhostUser *s =
CRYPTODEV_BACKEND_VHOST_USER(obj);
if (s->opened) {
error_setg(errp, QERR_PERMISSION_DENIED);
} else {
g_free(s->chr_name);
s->chr_name = g_strdup(value);
}
}
static char *
cryptodev_vhost_user_get_chardev(Object *obj, Error **errp)
{
CryptoDevBackendVhostUser *s =
CRYPTODEV_BACKEND_VHOST_USER(obj);
Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
if (chr && chr->label) {
return g_strdup(chr->label);
}
return NULL;
}
static void cryptodev_vhost_user_instance_int(Object *obj)
{
object_property_add_str(obj, "chardev",
cryptodev_vhost_user_get_chardev,
cryptodev_vhost_user_set_chardev,
NULL);
}
static void cryptodev_vhost_user_finalize(Object *obj)
{
CryptoDevBackendVhostUser *s =
CRYPTODEV_BACKEND_VHOST_USER(obj);
qemu_chr_fe_deinit(&s->chr, false);
g_free(s->chr_name);
}
static void
cryptodev_vhost_user_class_init(ObjectClass *oc, void *data)
{
CryptoDevBackendClass *bc = CRYPTODEV_BACKEND_CLASS(oc);
bc->init = cryptodev_vhost_user_init;
bc->cleanup = cryptodev_vhost_user_cleanup;
bc->create_session = cryptodev_vhost_user_sym_create_session;
bc->close_session = cryptodev_vhost_user_sym_close_session;
bc->do_sym_op = NULL;
}
static const TypeInfo cryptodev_vhost_user_info = {
.name = TYPE_CRYPTODEV_BACKEND_VHOST_USER,
.parent = TYPE_CRYPTODEV_BACKEND,
.class_init = cryptodev_vhost_user_class_init,
.instance_init = cryptodev_vhost_user_instance_int,
.instance_finalize = cryptodev_vhost_user_finalize,
.instance_size = sizeof(CryptoDevBackendVhostUser),
};
static void
cryptodev_vhost_user_register_types(void)
{
type_register_static(&cryptodev_vhost_user_info);
}
type_init(cryptodev_vhost_user_register_types);
|
pmp-tool/PMP | src/qemu/src-pmp/target/s390x/diag.c | /*
* S390x DIAG instruction helper functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "internal.h"
#include "exec/address-spaces.h"
#include "hw/watchdog/wdt_diag288.h"
#include "sysemu/cpus.h"
#include "hw/s390x/ipl.h"
#include "hw/s390x/s390-virtio-ccw.h"
int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3)
{
uint64_t func = env->regs[r1];
uint64_t timeout = env->regs[r1 + 1];
uint64_t action = env->regs[r3];
Object *obj;
DIAG288State *diag288;
DIAG288Class *diag288_class;
if (r1 % 2 || action != 0) {
return -1;
}
/* Timeout must be more than 15 seconds except for timer deletion */
if (func != WDT_DIAG288_CANCEL && timeout < 15) {
return -1;
}
obj = object_resolve_path_type("", TYPE_WDT_DIAG288, NULL);
if (!obj) {
return -1;
}
diag288 = DIAG288(obj);
diag288_class = DIAG288_GET_CLASS(diag288);
return diag288_class->handle_timer(diag288, func, timeout);
}
#define DIAG_308_RC_OK 0x0001
#define DIAG_308_RC_NO_CONF 0x0102
#define DIAG_308_RC_INVALID 0x0402
void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
{
CPUState *cs = CPU(s390_env_get_cpu(env));
uint64_t addr = env->regs[r1];
uint64_t subcode = env->regs[r3];
IplParameterBlock *iplb;
if (env->psw.mask & PSW_MASK_PSTATE) {
s390_program_interrupt(env, PGM_PRIVILEGED, ILEN_AUTO, ra);
return;
}
if ((subcode & ~0x0ffffULL) || (subcode > 6)) {
s390_program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO, ra);
return;
}
switch (subcode) {
case 0:
s390_ipl_reset_request(cs, S390_RESET_MODIFIED_CLEAR);
break;
case 1:
s390_ipl_reset_request(cs, S390_RESET_LOAD_NORMAL);
break;
case 3:
s390_ipl_reset_request(cs, S390_RESET_REIPL);
break;
case 5:
if ((r1 & 1) || (addr & 0x0fffULL)) {
s390_program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO, ra);
return;
}
if (!address_space_access_valid(&address_space_memory, addr,
sizeof(IplParameterBlock), false,
MEMTXATTRS_UNSPECIFIED)) {
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
return;
}
iplb = g_new0(IplParameterBlock, 1);
cpu_physical_memory_read(addr, iplb, sizeof(iplb->len));
if (!iplb_valid_len(iplb)) {
env->regs[r1 + 1] = DIAG_308_RC_INVALID;
goto out;
}
cpu_physical_memory_read(addr, iplb, be32_to_cpu(iplb->len));
if (!iplb_valid_ccw(iplb) && !iplb_valid_fcp(iplb)) {
env->regs[r1 + 1] = DIAG_308_RC_INVALID;
goto out;
}
s390_ipl_update_diag308(iplb);
env->regs[r1 + 1] = DIAG_308_RC_OK;
out:
g_free(iplb);
return;
case 6:
if ((r1 & 1) || (addr & 0x0fffULL)) {
s390_program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO, ra);
return;
}
if (!address_space_access_valid(&address_space_memory, addr,
sizeof(IplParameterBlock), true,
MEMTXATTRS_UNSPECIFIED)) {
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
return;
}
iplb = s390_ipl_get_iplb();
if (iplb) {
cpu_physical_memory_write(addr, iplb, be32_to_cpu(iplb->len));
env->regs[r1 + 1] = DIAG_308_RC_OK;
} else {
env->regs[r1 + 1] = DIAG_308_RC_NO_CONF;
}
return;
default:
s390_program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO, ra);
break;
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/qapi/string-input-visitor.c | /*
* String parsing visitor
*
* Copyright Red Hat, Inc. 2012-2016
*
* Author: <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING.LIB file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qapi/string-input-visitor.h"
#include "qapi/visitor-impl.h"
#include "qapi/qmp/qerror.h"
#include "qapi/qmp/qnull.h"
#include "qemu/option.h"
#include "qemu/cutils.h"
typedef enum ListMode {
/* no list parsing active / no list expected */
LM_NONE,
/* we have an unparsed string remaining */
LM_UNPARSED,
/* we have an unfinished int64 range */
LM_INT64_RANGE,
/* we have an unfinished uint64 range */
LM_UINT64_RANGE,
/* we have parsed the string completely and no range is remaining */
LM_END,
} ListMode;
/* protect against DOS attacks, limit the amount of elements per range */
#define RANGE_MAX_ELEMENTS 65536
typedef union RangeElement {
int64_t i64;
uint64_t u64;
} RangeElement;
struct StringInputVisitor
{
Visitor visitor;
/* List parsing state */
ListMode lm;
RangeElement rangeNext;
RangeElement rangeEnd;
const char *unparsed_string;
void *list;
/* The original string to parse */
const char *string;
};
static StringInputVisitor *to_siv(Visitor *v)
{
return container_of(v, StringInputVisitor, visitor);
}
static void start_list(Visitor *v, const char *name, GenericList **list,
size_t size, Error **errp)
{
StringInputVisitor *siv = to_siv(v);
assert(siv->lm == LM_NONE);
siv->list = list;
siv->unparsed_string = siv->string;
if (!siv->string[0]) {
if (list) {
*list = NULL;
}
siv->lm = LM_END;
} else {
if (list) {
*list = g_malloc0(size);
}
siv->lm = LM_UNPARSED;
}
}
static GenericList *next_list(Visitor *v, GenericList *tail, size_t size)
{
StringInputVisitor *siv = to_siv(v);
switch (siv->lm) {
case LM_END:
return NULL;
case LM_INT64_RANGE:
case LM_UINT64_RANGE:
case LM_UNPARSED:
/* we have an unparsed string or something left in a range */
break;
default:
abort();
}
tail->next = g_malloc0(size);
return tail->next;
}
static void check_list(Visitor *v, Error **errp)
{
const StringInputVisitor *siv = to_siv(v);
switch (siv->lm) {
case LM_INT64_RANGE:
case LM_UINT64_RANGE:
case LM_UNPARSED:
error_setg(errp, "Fewer list elements expected");
return;
case LM_END:
return;
default:
abort();
}
}
static void end_list(Visitor *v, void **obj)
{
StringInputVisitor *siv = to_siv(v);
assert(siv->lm != LM_NONE);
assert(siv->list == obj);
siv->list = NULL;
siv->unparsed_string = NULL;
siv->lm = LM_NONE;
}
static int try_parse_int64_list_entry(StringInputVisitor *siv, int64_t *obj)
{
const char *endptr;
int64_t start, end;
/* parse a simple int64 or range */
if (qemu_strtoi64(siv->unparsed_string, &endptr, 0, &start)) {
return -EINVAL;
}
end = start;
switch (endptr[0]) {
case '\0':
siv->unparsed_string = endptr;
break;
case ',':
siv->unparsed_string = endptr + 1;
break;
case '-':
/* parse the end of the range */
if (qemu_strtoi64(endptr + 1, &endptr, 0, &end)) {
return -EINVAL;
}
if (start > end || end - start >= RANGE_MAX_ELEMENTS) {
return -EINVAL;
}
switch (endptr[0]) {
case '\0':
siv->unparsed_string = endptr;
break;
case ',':
siv->unparsed_string = endptr + 1;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
/* we have a proper range (with maybe only one element) */
siv->lm = LM_INT64_RANGE;
siv->rangeNext.i64 = start;
siv->rangeEnd.i64 = end;
return 0;
}
static void parse_type_int64(Visitor *v, const char *name, int64_t *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
int64_t val;
switch (siv->lm) {
case LM_NONE:
/* just parse a simple int64, bail out if not completely consumed */
if (qemu_strtoi64(siv->string, NULL, 0, &val)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE,
name ? name : "null", "int64");
return;
}
*obj = val;
return;
case LM_UNPARSED:
if (try_parse_int64_list_entry(siv, obj)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name ? name : "null",
"list of int64 values or ranges");
return;
}
assert(siv->lm == LM_INT64_RANGE);
/* fall through */
case LM_INT64_RANGE:
/* return the next element in the range */
assert(siv->rangeNext.i64 <= siv->rangeEnd.i64);
*obj = siv->rangeNext.i64++;
if (siv->rangeNext.i64 > siv->rangeEnd.i64 || *obj == INT64_MAX) {
/* end of range, check if there is more to parse */
siv->lm = siv->unparsed_string[0] ? LM_UNPARSED : LM_END;
}
return;
case LM_END:
error_setg(errp, "Fewer list elements expected");
return;
default:
abort();
}
}
static int try_parse_uint64_list_entry(StringInputVisitor *siv, uint64_t *obj)
{
const char *endptr;
uint64_t start, end;
/* parse a simple uint64 or range */
if (qemu_strtou64(siv->unparsed_string, &endptr, 0, &start)) {
return -EINVAL;
}
end = start;
switch (endptr[0]) {
case '\0':
siv->unparsed_string = endptr;
break;
case ',':
siv->unparsed_string = endptr + 1;
break;
case '-':
/* parse the end of the range */
if (qemu_strtou64(endptr + 1, &endptr, 0, &end)) {
return -EINVAL;
}
if (start > end || end - start >= RANGE_MAX_ELEMENTS) {
return -EINVAL;
}
switch (endptr[0]) {
case '\0':
siv->unparsed_string = endptr;
break;
case ',':
siv->unparsed_string = endptr + 1;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
/* we have a proper range (with maybe only one element) */
siv->lm = LM_UINT64_RANGE;
siv->rangeNext.u64 = start;
siv->rangeEnd.u64 = end;
return 0;
}
static void parse_type_uint64(Visitor *v, const char *name, uint64_t *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
uint64_t val;
switch (siv->lm) {
case LM_NONE:
/* just parse a simple uint64, bail out if not completely consumed */
if (qemu_strtou64(siv->string, NULL, 0, &val)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name ? name : "null",
"uint64");
return;
}
*obj = val;
return;
case LM_UNPARSED:
if (try_parse_uint64_list_entry(siv, obj)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name ? name : "null",
"list of uint64 values or ranges");
return;
}
assert(siv->lm == LM_UINT64_RANGE);
/* fall through */
case LM_UINT64_RANGE:
/* return the next element in the range */
assert(siv->rangeNext.u64 <= siv->rangeEnd.u64);
*obj = siv->rangeNext.u64++;
if (siv->rangeNext.u64 > siv->rangeEnd.u64 || *obj == UINT64_MAX) {
/* end of range, check if there is more to parse */
siv->lm = siv->unparsed_string[0] ? LM_UNPARSED : LM_END;
}
return;
case LM_END:
error_setg(errp, "Fewer list elements expected");
return;
default:
abort();
}
}
static void parse_type_size(Visitor *v, const char *name, uint64_t *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
Error *err = NULL;
uint64_t val;
assert(siv->lm == LM_NONE);
parse_option_size(name, siv->string, &val, &err);
if (err) {
error_propagate(errp, err);
return;
}
*obj = val;
}
static void parse_type_bool(Visitor *v, const char *name, bool *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
assert(siv->lm == LM_NONE);
if (!strcasecmp(siv->string, "on") ||
!strcasecmp(siv->string, "yes") ||
!strcasecmp(siv->string, "true")) {
*obj = true;
return;
}
if (!strcasecmp(siv->string, "off") ||
!strcasecmp(siv->string, "no") ||
!strcasecmp(siv->string, "false")) {
*obj = false;
return;
}
error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null",
"boolean");
}
static void parse_type_str(Visitor *v, const char *name, char **obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
assert(siv->lm == LM_NONE);
*obj = g_strdup(siv->string);
}
static void parse_type_number(Visitor *v, const char *name, double *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
double val;
assert(siv->lm == LM_NONE);
if (qemu_strtod_finite(siv->string, NULL, &val)) {
error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null",
"number");
return;
}
*obj = val;
}
static void parse_type_null(Visitor *v, const char *name, QNull **obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
assert(siv->lm == LM_NONE);
*obj = NULL;
if (siv->string[0]) {
error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null",
"null");
return;
}
*obj = qnull();
}
static void string_input_free(Visitor *v)
{
StringInputVisitor *siv = to_siv(v);
g_free(siv);
}
Visitor *string_input_visitor_new(const char *str)
{
StringInputVisitor *v;
assert(str);
v = g_malloc0(sizeof(*v));
v->visitor.type = VISITOR_INPUT;
v->visitor.type_int64 = parse_type_int64;
v->visitor.type_uint64 = parse_type_uint64;
v->visitor.type_size = parse_type_size;
v->visitor.type_bool = parse_type_bool;
v->visitor.type_str = parse_type_str;
v->visitor.type_number = parse_type_number;
v->visitor.type_null = parse_type_null;
v->visitor.start_list = start_list;
v->visitor.next_list = next_list;
v->visitor.check_list = check_list;
v->visitor.end_list = end_list;
v->visitor.free = string_input_free;
v->string = str;
v->lm = LM_NONE;
return &v->visitor;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-add/test_msa_hadd_u_d.c | /*
* Test program for MSA instruction HADD_U.D
*
* Copyright (C) 2019 RT-RK Computer Based Systems LLC
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "HADD_U.D";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x00000001fffffffeULL, 0x00000001fffffffeULL, }, /* 0 */
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, },
{ 0x00000001aaaaaaa9ULL, 0x00000001aaaaaaa9ULL, },
{ 0x0000000155555554ULL, 0x0000000155555554ULL, },
{ 0x00000001cccccccbULL, 0x00000001cccccccbULL, },
{ 0x0000000133333332ULL, 0x0000000133333332ULL, },
{ 0x000000018e38e38dULL, 0x00000001e38e38e2ULL, },
{ 0x0000000171c71c70ULL, 0x000000011c71c71bULL, },
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x00000000aaaaaaaaULL, 0x00000000aaaaaaaaULL, },
{ 0x0000000055555555ULL, 0x0000000055555555ULL, },
{ 0x00000000ccccccccULL, 0x00000000ccccccccULL, },
{ 0x0000000033333333ULL, 0x0000000033333333ULL, },
{ 0x000000008e38e38eULL, 0x00000000e38e38e3ULL, },
{ 0x0000000071c71c71ULL, 0x000000001c71c71cULL, },
{ 0x00000001aaaaaaa9ULL, 0x00000001aaaaaaa9ULL, }, /* 16 */
{ 0x00000000aaaaaaaaULL, 0x00000000aaaaaaaaULL, },
{ 0x0000000155555554ULL, 0x0000000155555554ULL, },
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, },
{ 0x0000000177777776ULL, 0x0000000177777776ULL, },
{ 0x00000000ddddddddULL, 0x00000000ddddddddULL, },
{ 0x0000000138e38e38ULL, 0x000000018e38e38dULL, },
{ 0x000000011c71c71bULL, 0x00000000c71c71c6ULL, },
{ 0x0000000155555554ULL, 0x0000000155555554ULL, }, /* 24 */
{ 0x0000000055555555ULL, 0x0000000055555555ULL, },
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, },
{ 0x00000000aaaaaaaaULL, 0x00000000aaaaaaaaULL, },
{ 0x0000000122222221ULL, 0x0000000122222221ULL, },
{ 0x0000000088888888ULL, 0x0000000088888888ULL, },
{ 0x00000000e38e38e3ULL, 0x0000000138e38e38ULL, },
{ 0x00000000c71c71c6ULL, 0x0000000071c71c71ULL, },
{ 0x00000001cccccccbULL, 0x00000001cccccccbULL, }, /* 32 */
{ 0x00000000ccccccccULL, 0x00000000ccccccccULL, },
{ 0x0000000177777776ULL, 0x0000000177777776ULL, },
{ 0x0000000122222221ULL, 0x0000000122222221ULL, },
{ 0x0000000199999998ULL, 0x0000000199999998ULL, },
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, },
{ 0x000000015b05b05aULL, 0x00000001b05b05afULL, },
{ 0x000000013e93e93dULL, 0x00000000e93e93e8ULL, },
{ 0x0000000133333332ULL, 0x0000000133333332ULL, }, /* 40 */
{ 0x0000000033333333ULL, 0x0000000033333333ULL, },
{ 0x00000000ddddddddULL, 0x00000000ddddddddULL, },
{ 0x0000000088888888ULL, 0x0000000088888888ULL, },
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, },
{ 0x0000000066666666ULL, 0x0000000066666666ULL, },
{ 0x00000000c16c16c1ULL, 0x0000000116c16c16ULL, },
{ 0x00000000a4fa4fa4ULL, 0x000000004fa4fa4fULL, },
{ 0x00000001e38e38e2ULL, 0x0000000138e38e37ULL, }, /* 48 */
{ 0x00000000e38e38e3ULL, 0x0000000038e38e38ULL, },
{ 0x000000018e38e38dULL, 0x00000000e38e38e2ULL, },
{ 0x0000000138e38e38ULL, 0x000000008e38e38dULL, },
{ 0x00000001b05b05afULL, 0x0000000105b05b04ULL, },
{ 0x0000000116c16c16ULL, 0x000000006c16c16bULL, },
{ 0x0000000171c71c71ULL, 0x000000011c71c71bULL, },
{ 0x0000000155555554ULL, 0x0000000055555554ULL, },
{ 0x000000011c71c71bULL, 0x00000001c71c71c6ULL, }, /* 56 */
{ 0x000000001c71c71cULL, 0x00000000c71c71c7ULL, },
{ 0x00000000c71c71c6ULL, 0x0000000171c71c71ULL, },
{ 0x0000000071c71c71ULL, 0x000000011c71c71cULL, },
{ 0x00000000e93e93e8ULL, 0x0000000193e93e93ULL, },
{ 0x000000004fa4fa4fULL, 0x00000000fa4fa4faULL, },
{ 0x00000000aaaaaaaaULL, 0x00000001aaaaaaaaULL, },
{ 0x000000008e38e38dULL, 0x00000000e38e38e3ULL, },
{ 0x00000000b0cd3c0cULL, 0x0000000149e2bb6aULL, }, /* 64 */
{ 0x00000000d5feadd4ULL, 0x0000000060a65e5aULL, },
{ 0x00000001423a724cULL, 0x00000000f6923072ULL, },
{ 0x00000000e69cc91aULL, 0x00000000f4a9edfeULL, },
{ 0x00000001242055a3ULL, 0x0000000111736b26ULL, },
{ 0x000000014951c76bULL, 0x0000000028370e16ULL, },
{ 0x00000001b58d8be3ULL, 0x00000000be22e02eULL, },
{ 0x0000000159efe2b1ULL, 0x00000000bc3a9dbaULL, },
{ 0x00000000d4bd03eaULL, 0x000000012654770bULL, }, /* 72 */
{ 0x00000000f9ee75b2ULL, 0x000000003d1819fbULL, },
{ 0x00000001662a3a2aULL, 0x00000000d303ec13ULL, },
{ 0x000000010a8c90f8ULL, 0x00000000d11ba99fULL, },
{ 0x0000000098b16b8dULL, 0x000000018c6d38e4ULL, },
{ 0x00000000bde2dd55ULL, 0x00000000a330dbd4ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_HADD_U_D(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_HADD_U_D(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/include/hw/timer/pl031.h | <filename>src/qemu/src-pmp/include/hw/timer/pl031.h
/*
* ARM AMBA PrimeCell PL031 RTC
*
* Copyright (c) 2007 CodeSourcery
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
#ifndef HW_TIMER_PL031
#define HW_TIMER_PL031
#include "hw/sysbus.h"
#define TYPE_PL031 "pl031"
#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
typedef struct PL031State {
SysBusDevice parent_obj;
MemoryRegion iomem;
QEMUTimer *timer;
qemu_irq irq;
/*
* Needed to preserve the tick_count across migration, even if the
* absolute value of the rtc_clock is different on the source and
* destination.
*/
uint32_t tick_offset_vmstate;
uint32_t tick_offset;
uint32_t mr;
uint32_t lr;
uint32_t cr;
uint32_t im;
uint32_t is;
} PL031State;
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/target/riscv/cpu.c | <gh_stars>1-10
/*
* QEMU RISC-V CPU
*
* Copyright (c) 2016-2017 <NAME>, <EMAIL>
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
#include "migration/vmstate.h"
/* RISC-V CPU definitions */
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
"zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ",
"s0 ", "s1 ", "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ",
"a6 ", "a7 ", "s2 ", "s3 ", "s4 ", "s5 ", "s6 ", "s7 ",
"s8 ", "s9 ", "s10 ", "s11 ", "t3 ", "t4 ", "t5 ", "t6 "
};
const char * const riscv_fpr_regnames[] = {
"ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ",
"fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ",
"fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ",
"fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11"
};
const char * const riscv_excp_names[] = {
"misaligned_fetch",
"fault_fetch",
"illegal_instruction",
"breakpoint",
"misaligned_load",
"fault_load",
"misaligned_store",
"fault_store",
"user_ecall",
"supervisor_ecall",
"hypervisor_ecall",
"machine_ecall",
"exec_page_fault",
"load_page_fault",
"reserved",
"store_page_fault"
};
const char * const riscv_intr_names[] = {
"u_software",
"s_software",
"h_software",
"m_software",
"u_timer",
"s_timer",
"h_timer",
"m_timer",
"u_external",
"s_external",
"h_external",
"m_external",
"reserved",
"reserved",
"reserved",
"reserved"
};
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
}
static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
{
env->user_ver = user_ver;
env->priv_ver = priv_ver;
}
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
}
static void set_resetvec(CPURISCVState *env, int resetvec)
{
#ifndef CONFIG_USER_ONLY
env->resetvec = resetvec;
#endif
}
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
}
#if defined(TARGET_RISCV32)
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
}
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
}
static void rv32imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_PMP);
}
#elif defined(TARGET_RISCV64)
static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
}
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
}
static void rv64imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_PMP);
}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
char *typename;
char **cpuname;
cpuname = g_strsplit(cpu_model, ",", 1);
typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
object_class_is_abstract(oc)) {
return NULL;
}
return oc;
}
static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
int i;
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
#ifndef CONFIG_USER_ONLY
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ",
(target_ulong)atomic_read(&env->mip));
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
#endif
for (i = 0; i < 32; i++) {
cpu_fprintf(f, " %s " TARGET_FMT_lx,
riscv_int_regnames[i], env->gpr[i]);
if ((i & 3) == 3) {
cpu_fprintf(f, "\n");
}
}
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 32; i++) {
cpu_fprintf(f, " %s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]);
if ((i & 3) == 3) {
cpu_fprintf(f, "\n");
}
}
}
}
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = value;
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = tb->pc;
}
static bool riscv_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
/*
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
*/
return (atomic_read(&env->mip) & env->mie) != 0;
#else
return true;
#endif
}
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
env->pc = data[0];
}
static void riscv_cpu_reset(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPURISCVState *env = &cpu->env;
mcc->parent_reset(cs);
#ifndef CONFIG_USER_ONLY
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause = 0;
env->pc = env->resetvec;
#endif
cs->exception_index = EXCP_NONE;
set_default_nan_mode(1, &env->fp_status);
}
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
#if defined(TARGET_RISCV32)
info->print_insn = print_insn_riscv32;
#elif defined(TARGET_RISCV64)
info->print_insn = print_insn_riscv64;
#endif
}
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
riscv_cpu_register_gdb_regs_for_features(cs);
qemu_init_vcpu(cs);
cpu_reset(cs);
mcc->parent_realize(dev, errp);
}
static void riscv_cpu_init(Object *obj)
{
CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(obj);
cs->env_ptr = &cpu->env;
}
static const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
device_class_set_parent_realize(dc, riscv_cpu_realize,
&mcc->parent_realize);
mcc->parent_reset = cc->reset;
cc->reset = riscv_cpu_reset;
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
#if defined(TARGET_RISCV32)
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
#elif defined(TARGET_RISCV64)
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
cc->handle_mmu_fault = riscv_cpu_handle_mmu_fault;
#else
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
#endif
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
#endif
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
}
char *riscv_isa_string(RISCVCPU *cpu)
{
int i;
const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
char *isa_str = g_new(char, maxlen);
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
for (i = 0; i < sizeof(riscv_exts); i++) {
if (cpu->env.misa & RV(riscv_exts[i])) {
*p++ = qemu_tolower(riscv_exts[i]);
}
}
*p = '\0';
return isa_str;
}
typedef struct RISCVCPUListState {
fprintf_function cpu_fprintf;
FILE *file;
} RISCVCPUListState;
static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
{
ObjectClass *class_a = (ObjectClass *)a;
ObjectClass *class_b = (ObjectClass *)b;
const char *name_a, *name_b;
name_a = object_class_get_name(class_a);
name_b = object_class_get_name(class_b);
return strcmp(name_a, name_b);
}
static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
{
RISCVCPUListState *s = user_data;
const char *typename = object_class_get_name(OBJECT_CLASS(data));
int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
(*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
}
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
RISCVCPUListState s = {
.cpu_fprintf = cpu_fprintf,
.file = f,
};
GSList *list;
list = object_class_get_list(TYPE_RISCV_CPU, false);
list = g_slist_sort(list, riscv_cpu_list_compare);
g_slist_foreach(list, riscv_cpu_list_entry, &s);
g_slist_free(list);
}
#define DEFINE_CPU(type_name, initfn) \
{ \
.name = type_name, \
.parent = TYPE_RISCV_CPU, \
.instance_init = initfn \
}
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(RISCVCPU),
.instance_init = riscv_cpu_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
#endif
};
DEFINE_TYPES(riscv_cpu_type_infos)
|
pmp-tool/PMP | src/qemu/src-pmp/hw/misc/tz-mpc.c | /*
* ARM AHB5 TrustZone Memory Protection Controller emulation
*
* Copyright (c) 2018 Linaro Limited
* Written by <NAME>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "trace.h"
#include "hw/sysbus.h"
#include "hw/registerfields.h"
#include "hw/misc/tz-mpc.h"
/* Our IOMMU has two IOMMU indexes, one for secure transactions and one for
* non-secure transactions.
*/
enum {
IOMMU_IDX_S,
IOMMU_IDX_NS,
IOMMU_NUM_INDEXES,
};
/* Config registers */
REG32(CTRL, 0x00)
FIELD(CTRL, SEC_RESP, 4, 1)
FIELD(CTRL, AUTOINC, 8, 1)
FIELD(CTRL, LOCKDOWN, 31, 1)
REG32(BLK_MAX, 0x10)
REG32(BLK_CFG, 0x14)
REG32(BLK_IDX, 0x18)
REG32(BLK_LUT, 0x1c)
REG32(INT_STAT, 0x20)
FIELD(INT_STAT, IRQ, 0, 1)
REG32(INT_CLEAR, 0x24)
FIELD(INT_CLEAR, IRQ, 0, 1)
REG32(INT_EN, 0x28)
FIELD(INT_EN, IRQ, 0, 1)
REG32(INT_INFO1, 0x2c)
REG32(INT_INFO2, 0x30)
FIELD(INT_INFO2, HMASTER, 0, 16)
FIELD(INT_INFO2, HNONSEC, 16, 1)
FIELD(INT_INFO2, CFG_NS, 17, 1)
REG32(INT_SET, 0x34)
FIELD(INT_SET, IRQ, 0, 1)
REG32(PIDR4, 0xfd0)
REG32(PIDR5, 0xfd4)
REG32(PIDR6, 0xfd8)
REG32(PIDR7, 0xfdc)
REG32(PIDR0, 0xfe0)
REG32(PIDR1, 0xfe4)
REG32(PIDR2, 0xfe8)
REG32(PIDR3, 0xfec)
REG32(CIDR0, 0xff0)
REG32(CIDR1, 0xff4)
REG32(CIDR2, 0xff8)
REG32(CIDR3, 0xffc)
static const uint8_t tz_mpc_idregs[] = {
0x04, 0x00, 0x00, 0x00,
0x60, 0xb8, 0x1b, 0x00,
0x0d, 0xf0, 0x05, 0xb1,
};
static void tz_mpc_irq_update(TZMPC *s)
{
qemu_set_irq(s->irq, s->int_stat && s->int_en);
}
static void tz_mpc_iommu_notify(TZMPC *s, uint32_t lutidx,
uint32_t oldlut, uint32_t newlut)
{
/* Called when the LUT word at lutidx has changed from oldlut to newlut;
* must call the IOMMU notifiers for the changed blocks.
*/
IOMMUTLBEntry entry = {
.addr_mask = s->blocksize - 1,
};
hwaddr addr = lutidx * s->blocksize * 32;
int i;
for (i = 0; i < 32; i++, addr += s->blocksize) {
bool block_is_ns;
if (!((oldlut ^ newlut) & (1 << i))) {
continue;
}
/* This changes the mappings for both the S and the NS space,
* so we need to do four notifies: an UNMAP then a MAP for each.
*/
block_is_ns = newlut & (1 << i);
trace_tz_mpc_iommu_notify(addr);
entry.iova = addr;
entry.translated_addr = addr;
entry.perm = IOMMU_NONE;
memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, entry);
memory_region_notify_iommu(&s->upstream, IOMMU_IDX_NS, entry);
entry.perm = IOMMU_RW;
if (block_is_ns) {
entry.target_as = &s->blocked_io_as;
} else {
entry.target_as = &s->downstream_as;
}
memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, entry);
if (block_is_ns) {
entry.target_as = &s->downstream_as;
} else {
entry.target_as = &s->blocked_io_as;
}
memory_region_notify_iommu(&s->upstream, IOMMU_IDX_NS, entry);
}
}
static void tz_mpc_autoinc_idx(TZMPC *s, unsigned access_size)
{
/* Auto-increment BLK_IDX if necessary */
if (access_size == 4 && (s->ctrl & R_CTRL_AUTOINC_MASK)) {
s->blk_idx++;
s->blk_idx %= s->blk_max;
}
}
static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
uint64_t *pdata,
unsigned size, MemTxAttrs attrs)
{
TZMPC *s = TZ_MPC(opaque);
uint64_t r;
uint32_t offset = addr & ~0x3;
if (!attrs.secure && offset < A_PIDR4) {
/* NS accesses can only see the ID registers */
qemu_log_mask(LOG_GUEST_ERROR,
"TZ MPC register read: NS access to offset 0x%x\n",
offset);
r = 0;
goto read_out;
}
switch (offset) {
case A_CTRL:
r = s->ctrl;
break;
case A_BLK_MAX:
r = s->blk_max - 1;
break;
case A_BLK_CFG:
/* We are never in "init in progress state", so this just indicates
* the block size. s->blocksize == (1 << BLK_CFG + 5), so
* BLK_CFG == ctz32(s->blocksize) - 5
*/
r = ctz32(s->blocksize) - 5;
break;
case A_BLK_IDX:
r = s->blk_idx;
break;
case A_BLK_LUT:
r = s->blk_lut[s->blk_idx];
tz_mpc_autoinc_idx(s, size);
break;
case A_INT_STAT:
r = s->int_stat;
break;
case A_INT_EN:
r = s->int_en;
break;
case A_INT_INFO1:
r = s->int_info1;
break;
case A_INT_INFO2:
r = s->int_info2;
break;
case A_PIDR4:
case A_PIDR5:
case A_PIDR6:
case A_PIDR7:
case A_PIDR0:
case A_PIDR1:
case A_PIDR2:
case A_PIDR3:
case A_CIDR0:
case A_CIDR1:
case A_CIDR2:
case A_CIDR3:
r = tz_mpc_idregs[(offset - A_PIDR4) / 4];
break;
case A_INT_CLEAR:
case A_INT_SET:
qemu_log_mask(LOG_GUEST_ERROR,
"TZ MPC register read: write-only offset 0x%x\n",
offset);
r = 0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"TZ MPC register read: bad offset 0x%x\n", offset);
r = 0;
break;
}
if (size != 4) {
/* None of our registers are read-sensitive (except BLK_LUT,
* which can special case the "size not 4" case), so just
* pull the right bytes out of the word read result.
*/
r = extract32(r, (addr & 3) * 8, size * 8);
}
read_out:
trace_tz_mpc_reg_read(addr, r, size);
*pdata = r;
return MEMTX_OK;
}
static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
uint64_t value,
unsigned size, MemTxAttrs attrs)
{
TZMPC *s = TZ_MPC(opaque);
uint32_t offset = addr & ~0x3;
trace_tz_mpc_reg_write(addr, value, size);
if (!attrs.secure && offset < A_PIDR4) {
/* NS accesses can only see the ID registers */
qemu_log_mask(LOG_GUEST_ERROR,
"TZ MPC register write: NS access to offset 0x%x\n",
offset);
return MEMTX_OK;
}
if (size != 4) {
/* Expand the byte or halfword write to a full word size.
* In most cases we can do this with zeroes; the exceptions
* are CTRL, BLK_IDX and BLK_LUT.
*/
uint32_t oldval;
switch (offset) {
case A_CTRL:
oldval = s->ctrl;
break;
case A_BLK_IDX:
oldval = s->blk_idx;
break;
case A_BLK_LUT:
oldval = s->blk_lut[s->blk_idx];
break;
default:
oldval = 0;
break;
}
value = deposit32(oldval, (addr & 3) * 8, size * 8, value);
}
if ((s->ctrl & R_CTRL_LOCKDOWN_MASK) &&
(offset == A_CTRL || offset == A_BLK_LUT || offset == A_INT_EN)) {
/* Lockdown mode makes these three registers read-only, and
* the only way out of it is to reset the device.
*/
qemu_log_mask(LOG_GUEST_ERROR, "TZ MPC register write to offset 0x%x "
"while MPC is in lockdown mode\n", offset);
return MEMTX_OK;
}
switch (offset) {
case A_CTRL:
/* We don't implement the 'data gating' feature so all other bits
* are reserved and we make them RAZ/WI.
*/
s->ctrl = value & (R_CTRL_SEC_RESP_MASK |
R_CTRL_AUTOINC_MASK |
R_CTRL_LOCKDOWN_MASK);
break;
case A_BLK_IDX:
s->blk_idx = value % s->blk_max;
break;
case A_BLK_LUT:
tz_mpc_iommu_notify(s, s->blk_idx, s->blk_lut[s->blk_idx], value);
s->blk_lut[s->blk_idx] = value;
tz_mpc_autoinc_idx(s, size);
break;
case A_INT_CLEAR:
if (value & R_INT_CLEAR_IRQ_MASK) {
s->int_stat = 0;
tz_mpc_irq_update(s);
}
break;
case A_INT_EN:
s->int_en = value & R_INT_EN_IRQ_MASK;
tz_mpc_irq_update(s);
break;
case A_INT_SET:
if (value & R_INT_SET_IRQ_MASK) {
s->int_stat = R_INT_STAT_IRQ_MASK;
tz_mpc_irq_update(s);
}
break;
case A_PIDR4:
case A_PIDR5:
case A_PIDR6:
case A_PIDR7:
case A_PIDR0:
case A_PIDR1:
case A_PIDR2:
case A_PIDR3:
case A_CIDR0:
case A_CIDR1:
case A_CIDR2:
case A_CIDR3:
qemu_log_mask(LOG_GUEST_ERROR,
"TZ MPC register write: read-only offset 0x%x\n", offset);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"TZ MPC register write: bad offset 0x%x\n", offset);
break;
}
return MEMTX_OK;
}
static const MemoryRegionOps tz_mpc_reg_ops = {
.read_with_attrs = tz_mpc_reg_read,
.write_with_attrs = tz_mpc_reg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 4,
};
static inline bool tz_mpc_cfg_ns(TZMPC *s, hwaddr addr)
{
/* Return the cfg_ns bit from the LUT for the specified address */
hwaddr blknum = addr / s->blocksize;
hwaddr blkword = blknum / 32;
uint32_t blkbit = 1U << (blknum % 32);
/* This would imply the address was larger than the size we
* defined this memory region to be, so it can't happen.
*/
assert(blkword < s->blk_max);
return s->blk_lut[blkword] & blkbit;
}
static MemTxResult tz_mpc_handle_block(TZMPC *s, hwaddr addr, MemTxAttrs attrs)
{
/* Handle a blocked transaction: raise IRQ, capture info, etc */
if (!s->int_stat) {
/* First blocked transfer: capture information into INT_INFO1 and
* INT_INFO2. Subsequent transfers are still blocked but don't
* capture information until the guest clears the interrupt.
*/
s->int_info1 = addr;
s->int_info2 = 0;
s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, HMASTER,
attrs.requester_id & 0xffff);
s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, HNONSEC,
~attrs.secure);
s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, CFG_NS,
tz_mpc_cfg_ns(s, addr));
s->int_stat |= R_INT_STAT_IRQ_MASK;
tz_mpc_irq_update(s);
}
/* Generate bus error if desired; otherwise RAZ/WI */
return (s->ctrl & R_CTRL_SEC_RESP_MASK) ? MEMTX_ERROR : MEMTX_OK;
}
/* Accesses only reach these read and write functions if the MPC is
* blocking them; non-blocked accesses go directly to the downstream
* memory region without passing through this code.
*/
static MemTxResult tz_mpc_mem_blocked_read(void *opaque, hwaddr addr,
uint64_t *pdata,
unsigned size, MemTxAttrs attrs)
{
TZMPC *s = TZ_MPC(opaque);
trace_tz_mpc_mem_blocked_read(addr, size, attrs.secure);
*pdata = 0;
return tz_mpc_handle_block(s, addr, attrs);
}
static MemTxResult tz_mpc_mem_blocked_write(void *opaque, hwaddr addr,
uint64_t value,
unsigned size, MemTxAttrs attrs)
{
TZMPC *s = TZ_MPC(opaque);
trace_tz_mpc_mem_blocked_write(addr, value, size, attrs.secure);
return tz_mpc_handle_block(s, addr, attrs);
}
static const MemoryRegionOps tz_mpc_mem_blocked_ops = {
.read_with_attrs = tz_mpc_mem_blocked_read,
.write_with_attrs = tz_mpc_mem_blocked_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 1,
.valid.max_access_size = 8,
.impl.min_access_size = 1,
.impl.max_access_size = 8,
};
static IOMMUTLBEntry tz_mpc_translate(IOMMUMemoryRegion *iommu,
hwaddr addr, IOMMUAccessFlags flags,
int iommu_idx)
{
TZMPC *s = TZ_MPC(container_of(iommu, TZMPC, upstream));
bool ok;
IOMMUTLBEntry ret = {
.iova = addr & ~(s->blocksize - 1),
.translated_addr = addr & ~(s->blocksize - 1),
.addr_mask = s->blocksize - 1,
.perm = IOMMU_RW,
};
/* Look at the per-block configuration for this address, and
* return a TLB entry directing the transaction at either
* downstream_as or blocked_io_as, as appropriate.
* If the LUT cfg_ns bit is 1, only non-secure transactions
* may pass. If the bit is 0, only secure transactions may pass.
*/
ok = tz_mpc_cfg_ns(s, addr) == (iommu_idx == IOMMU_IDX_NS);
trace_tz_mpc_translate(addr, flags,
iommu_idx == IOMMU_IDX_S ? "S" : "NS",
ok ? "pass" : "block");
ret.target_as = ok ? &s->downstream_as : &s->blocked_io_as;
return ret;
}
static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs)
{
/* We treat unspecified attributes like secure. Transactions with
* unspecified attributes come from places like
* rom_reset() for initial image load, and we want
* those to pass through the from-reset "everything is secure" config.
* All the real during-emulation transactions from the CPU will
* specify attributes.
*/
return (attrs.unspecified || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS;
}
static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu)
{
return IOMMU_NUM_INDEXES;
}
static void tz_mpc_reset(DeviceState *dev)
{
TZMPC *s = TZ_MPC(dev);
s->ctrl = 0x00000100;
s->blk_idx = 0;
s->int_stat = 0;
s->int_en = 1;
s->int_info1 = 0;
s->int_info2 = 0;
memset(s->blk_lut, 0, s->blk_max * sizeof(uint32_t));
}
static void tz_mpc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
TZMPC *s = TZ_MPC(obj);
qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
}
static void tz_mpc_realize(DeviceState *dev, Error **errp)
{
Object *obj = OBJECT(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
TZMPC *s = TZ_MPC(dev);
uint64_t size;
/* We can't create the upstream end of the port until realize,
* as we don't know the size of the MR used as the downstream until then.
* We insist on having a downstream, to avoid complicating the code
* with handling the "don't know how big this is" case. It's easy
* enough for the user to create an unimplemented_device as downstream
* if they have nothing else to plug into this.
*/
if (!s->downstream) {
error_setg(errp, "MPC 'downstream' link not set");
return;
}
size = memory_region_size(s->downstream);
memory_region_init_iommu(&s->upstream, sizeof(s->upstream),
TYPE_TZ_MPC_IOMMU_MEMORY_REGION,
obj, "tz-mpc-upstream", size);
/* In real hardware the block size is configurable. In QEMU we could
* make it configurable but will need it to be at least as big as the
* target page size so we can execute out of the resulting MRs. Guest
* software is supposed to check the block size using the BLK_CFG
* register, so make it fixed at the page size.
*/
s->blocksize = memory_region_iommu_get_min_page_size(&s->upstream);
if (size % s->blocksize != 0) {
error_setg(errp,
"MPC 'downstream' size %" PRId64
" is not a multiple of %" HWADDR_PRIx " bytes",
size, s->blocksize);
object_unref(OBJECT(&s->upstream));
return;
}
/* BLK_MAX is the max value of BLK_IDX, which indexes an array of 32-bit
* words, each bit of which indicates one block.
*/
s->blk_max = DIV_ROUND_UP(size / s->blocksize, 32);
memory_region_init_io(&s->regmr, obj, &tz_mpc_reg_ops,
s, "tz-mpc-regs", 0x1000);
sysbus_init_mmio(sbd, &s->regmr);
sysbus_init_mmio(sbd, MEMORY_REGION(&s->upstream));
/* This memory region is not exposed to users of this device as a
* sysbus MMIO region, but is instead used internally as something
* that our IOMMU translate function might direct accesses to.
*/
memory_region_init_io(&s->blocked_io, obj, &tz_mpc_mem_blocked_ops,
s, "tz-mpc-blocked-io", size);
address_space_init(&s->downstream_as, s->downstream,
"tz-mpc-downstream");
address_space_init(&s->blocked_io_as, &s->blocked_io,
"tz-mpc-blocked-io");
s->blk_lut = g_new0(uint32_t, s->blk_max);
}
static int tz_mpc_post_load(void *opaque, int version_id)
{
TZMPC *s = TZ_MPC(opaque);
/* Check the incoming data doesn't point blk_idx off the end of blk_lut. */
if (s->blk_idx >= s->blk_max) {
return -1;
}
return 0;
}
static const VMStateDescription tz_mpc_vmstate = {
.name = "tz-mpc",
.version_id = 1,
.minimum_version_id = 1,
.post_load = tz_mpc_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, TZMPC),
VMSTATE_UINT32(blk_idx, TZMPC),
VMSTATE_UINT32(int_stat, TZMPC),
VMSTATE_UINT32(int_en, TZMPC),
VMSTATE_UINT32(int_info1, TZMPC),
VMSTATE_UINT32(int_info2, TZMPC),
VMSTATE_VARRAY_UINT32(blk_lut, TZMPC, blk_max,
0, vmstate_info_uint32, uint32_t),
VMSTATE_END_OF_LIST()
}
};
static Property tz_mpc_properties[] = {
DEFINE_PROP_LINK("downstream", TZMPC, downstream,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
static void tz_mpc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = tz_mpc_realize;
dc->vmsd = &tz_mpc_vmstate;
dc->reset = tz_mpc_reset;
dc->props = tz_mpc_properties;
}
static const TypeInfo tz_mpc_info = {
.name = TYPE_TZ_MPC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(TZMPC),
.instance_init = tz_mpc_init,
.class_init = tz_mpc_class_init,
};
static void tz_mpc_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
{
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
imrc->translate = tz_mpc_translate;
imrc->attrs_to_index = tz_mpc_attrs_to_index;
imrc->num_indexes = tz_mpc_num_indexes;
}
static const TypeInfo tz_mpc_iommu_memory_region_info = {
.name = TYPE_TZ_MPC_IOMMU_MEMORY_REGION,
.parent = TYPE_IOMMU_MEMORY_REGION,
.class_init = tz_mpc_iommu_memory_region_class_init,
};
static void tz_mpc_register_types(void)
{
type_register_static(&tz_mpc_info);
type_register_static(&tz_mpc_iommu_memory_region_info);
}
type_init(tz_mpc_register_types);
|
pmp-tool/PMP | src/qemu/src-pmp/hw/core/empty_slot.c | <gh_stars>1-10
/*
* QEMU Empty Slot
*
* The empty_slot device emulates known to a bus but not connected devices.
*
* Copyright (c) 2010 <NAME>
*
* This code is licensed under the GNU GPL v2 or (at your option) any later
* version.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/empty_slot.h"
//#define DEBUG_EMPTY_SLOT
#ifdef DEBUG_EMPTY_SLOT
#define DPRINTF(fmt, ...) \
do { printf("empty_slot: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif
#define TYPE_EMPTY_SLOT "empty_slot"
#define EMPTY_SLOT(obj) OBJECT_CHECK(EmptySlot, (obj), TYPE_EMPTY_SLOT)
typedef struct EmptySlot {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint64_t size;
} EmptySlot;
static uint64_t empty_slot_read(void *opaque, hwaddr addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
static void empty_slot_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
}
static const MemoryRegionOps empty_slot_ops = {
.read = empty_slot_read,
.write = empty_slot_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void empty_slot_init(hwaddr addr, uint64_t slot_size)
{
if (slot_size > 0) {
/* Only empty slots larger than 0 byte need handling. */
DeviceState *dev;
SysBusDevice *s;
EmptySlot *e;
dev = qdev_create(NULL, TYPE_EMPTY_SLOT);
s = SYS_BUS_DEVICE(dev);
e = EMPTY_SLOT(dev);
e->size = slot_size;
qdev_init_nofail(dev);
sysbus_mmio_map(s, 0, addr);
}
}
static void empty_slot_realize(DeviceState *dev, Error **errp)
{
EmptySlot *s = EMPTY_SLOT(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
"empty-slot", s->size);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
}
static void empty_slot_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = empty_slot_realize;
}
static const TypeInfo empty_slot_info = {
.name = TYPE_EMPTY_SLOT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(EmptySlot),
.class_init = empty_slot_class_init,
};
static void empty_slot_register_types(void)
{
type_register_static(&empty_slot_info);
}
type_init(empty_slot_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/tests/usb-hcd-ohci-test.c | <reponame>pmp-tool/PMP<gh_stars>1-10
/*
* QTest testcase for USB OHCI controller
*
* Copyright (c) 2014 HUAWEI TECHNOLOGIES CO., LTD.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/usb.h"
#include "libqos/qgraph.h"
#include "libqos/pci.h"
typedef struct QOHCI_PCI QOHCI_PCI;
struct QOHCI_PCI {
QOSGraphObject obj;
QPCIDevice dev;
};
static void test_ohci_hotplug(void *obj, void *data, QGuestAllocator *alloc)
{
usb_test_hotplug("ohci", "1", NULL);
}
static void *ohci_pci_get_driver(void *obj, const char *interface)
{
QOHCI_PCI *ohci_pci = obj;
if (!g_strcmp0(interface, "pci-device")) {
return &ohci_pci->dev;
}
fprintf(stderr, "%s not present in pci-ohci\n", interface);
g_assert_not_reached();
}
static void *ohci_pci_create(void *pci_bus, QGuestAllocator *alloc, void *addr)
{
QOHCI_PCI *ohci_pci = g_new0(QOHCI_PCI, 1);
ohci_pci->obj.get_driver = ohci_pci_get_driver;
return &ohci_pci->obj;
}
static void ohci_pci_register_nodes(void)
{
QOSGraphEdgeOptions opts = {
.extra_device_opts = "addr=04.0,id=ohci",
};
add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
qos_node_create_driver("pci-ohci", ohci_pci_create);
qos_node_consumes("pci-ohci", "pci-bus", &opts);
qos_node_produces("pci-ohci", "pci-device");
}
libqos_init(ohci_pci_register_nodes);
static void register_ohci_pci_test(void)
{
qos_add_test("ohci_pci-test-hotplug", "pci-ohci", test_ohci_hotplug, NULL);
}
libqos_init(register_ohci_pci_test);
|
pmp-tool/PMP | src/qemu/src-pmp/hw/arm/versatilepb.c | <reponame>pmp-tool/PMP<filename>src/qemu/src-pmp/hw/arm/versatilepb.c
/*
* ARM Versatile Platform/Application Baseboard System emulation.
*
* Copyright (c) 2005-2007 CodeSourcery.
* Written by <NAME>
*
* This code is licensed under the GPL.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"
#include "hw/i2c/i2c.h"
#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "hw/block/flash.h"
#include "qemu/error-report.h"
#include "hw/char/pl011.h"
#define VERSATILE_FLASH_ADDR 0x34000000
#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
/* Primary interrupt controller. */
#define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
#define VERSATILE_PB_SIC(obj) \
OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
typedef struct vpb_sic_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
qemu_irq parent[32];
int irq;
} vpb_sic_state;
static const VMStateDescription vmstate_vpb_sic = {
.name = "versatilepb_sic",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(level, vpb_sic_state),
VMSTATE_UINT32(mask, vpb_sic_state),
VMSTATE_UINT32(pic_enable, vpb_sic_state),
VMSTATE_END_OF_LIST()
}
};
static void vpb_sic_update(vpb_sic_state *s)
{
uint32_t flags;
flags = s->level & s->mask;
qemu_set_irq(s->parent[s->irq], flags != 0);
}
static void vpb_sic_update_pic(vpb_sic_state *s)
{
int i;
uint32_t mask;
for (i = 21; i <= 30; i++) {
mask = 1u << i;
if (!(s->pic_enable & mask))
continue;
qemu_set_irq(s->parent[i], (s->level & mask) != 0);
}
}
static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
if (level)
s->level |= 1u << irq;
else
s->level &= ~(1u << irq);
if (s->pic_enable & (1u << irq))
qemu_set_irq(s->parent[irq], level);
vpb_sic_update(s);
}
static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
switch (offset >> 2) {
case 0: /* STATUS */
return s->level & s->mask;
case 1: /* RAWSTAT */
return s->level;
case 2: /* ENABLE */
return s->mask;
case 4: /* SOFTINT */
return s->level & 1;
case 8: /* PICENABLE */
return s->pic_enable;
default:
printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
return 0;
}
}
static void vpb_sic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
switch (offset >> 2) {
case 2: /* ENSET */
s->mask |= value;
break;
case 3: /* ENCLR */
s->mask &= ~value;
break;
case 4: /* SOFTINTSET */
if (value)
s->mask |= 1;
break;
case 5: /* SOFTINTCLR */
if (value)
s->mask &= ~1u;
break;
case 8: /* PICENSET */
s->pic_enable |= (value & 0x7fe00000);
vpb_sic_update_pic(s);
break;
case 9: /* PICENCLR */
s->pic_enable &= ~value;
vpb_sic_update_pic(s);
break;
default:
printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
return;
}
vpb_sic_update(s);
}
static const MemoryRegionOps vpb_sic_ops = {
.read = vpb_sic_read,
.write = vpb_sic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void vpb_sic_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
vpb_sic_state *s = VERSATILE_PB_SIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int i;
qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
for (i = 0; i < 32; i++) {
sysbus_init_irq(sbd, &s->parent[i]);
}
s->irq = 31;
memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s,
"vpb-sic", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
}
/* Board init. */
/* The AB and PB boards both use the same core, just with different
peripherals and expansion busses. For now we emulate a subset of the
PB peripherals and just change the board ID. */
static struct arm_boot_info versatile_binfo;
static void versatile_init(MachineState *machine, int board_id)
{
Object *cpuobj;
ARMCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq pic[32];
qemu_irq sic[32];
DeviceState *dev, *sysctl;
SysBusDevice *busdev;
DeviceState *pl041;
PCIBus *pci_bus;
NICInfo *nd;
I2CBus *i2c;
int n;
int done_smc = 0;
DriveInfo *dinfo;
if (machine->ram_size > 0x10000000) {
/* Device starting at address 0x10000000,
* and memory cannot overlap with devices.
* Refuse to run rather than behaving very confusingly.
*/
error_report("versatilepb: memory size must not exceed 256MB");
exit(1);
}
cpuobj = object_new(machine->cpu_type);
/* By default ARM1176 CPUs have EL3 enabled. This board does not
* currently support EL3 so the CPU EL3 property is disabled before
* realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
cpu = ARM_CPU(cpuobj);
memory_region_allocate_system_memory(ram, NULL, "versatile.ram",
machine->ram_size);
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, ram);
sysctl = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
qdev_init_nofail(sysctl);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
dev = sysbus_create_varargs("pl190", 0x10140000,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
NULL);
for (n = 0; n < 32; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL);
for (n = 0; n < 32; n++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
sic[n] = qdev_get_gpio_in(dev, n);
}
sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
dev = qdev_create(NULL, "versatile_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */
sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */
sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */
sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */
sysbus_connect_irq(busdev, 0, sic[27]);
sysbus_connect_irq(busdev, 1, sic[28]);
sysbus_connect_irq(busdev, 2, sic[29]);
sysbus_connect_irq(busdev, 3, sic[30]);
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
for(n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
smc91c111_init(nd, 0x10010000, sic[25]);
done_smc = 1;
} else {
pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
}
}
if (machine_usb(machine)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
n = drive_get_max_bus(IF_SCSI);
while (n >= 0) {
dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
lsi53c8xx_handle_legacy_cmdline(dev);
n--;
}
pl011_create(0x101f1000, pic[12], serial_hd(0));
pl011_create(0x101f2000, pic[13], serial_hd(1));
pl011_create(0x101f3000, pic[14], serial_hd(2));
pl011_create(0x10009000, sic[6], serial_hd(3));
dev = qdev_create(NULL, "pl080");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0x10130000);
sysbus_connect_irq(busdev, 0, pic[17]);
sysbus_create_simple("sp804", 0x101e2000, pic[4]);
sysbus_create_simple("sp804", 0x101e3000, pic[5]);
sysbus_create_simple("pl061", 0x101e4000, pic[6]);
sysbus_create_simple("pl061", 0x101e5000, pic[7]);
sysbus_create_simple("pl061", 0x101e6000, pic[8]);
sysbus_create_simple("pl061", 0x101e7000, pic[9]);
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
/* Wire up the mux control signals from the SYS_CLCD register */
qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
/* Add PL031 Real Time Clock. */
sysbus_create_simple("pl031", 0x101e8000, pic[10]);
dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_create_slave(i2c, "ds1338", 0x68);
/* Add PL041 AACI Interface to the LM4549 codec */
pl041 = qdev_create(NULL, "pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
/* Memory map for Versatile/PB: */
/* 0x10000000 System registers. */
/* 0x10001000 PCI controller config registers. */
/* 0x10002000 Serial bus interface. */
/* 0x10003000 Secondary interrupt controller. */
/* 0x10004000 AACI (audio). */
/* 0x10005000 MMCI0. */
/* 0x10006000 KMI0 (keyboard). */
/* 0x10007000 KMI1 (mouse). */
/* 0x10008000 Character LCD Interface. */
/* 0x10009000 UART3. */
/* 0x1000a000 Smart card 1. */
/* 0x1000b000 MMCI1. */
/* 0x10010000 Ethernet. */
/* 0x10020000 USB. */
/* 0x10100000 SSMC. */
/* 0x10110000 MPMC. */
/* 0x10120000 CLCD Controller. */
/* 0x10130000 DMA Controller. */
/* 0x10140000 Vectored interrupt controller. */
/* 0x101d0000 AHB Monitor Interface. */
/* 0x101e0000 System Controller. */
/* 0x101e1000 Watchdog Interface. */
/* 0x101e2000 Timer 0/1. */
/* 0x101e3000 Timer 2/3. */
/* 0x101e4000 GPIO port 0. */
/* 0x101e5000 GPIO port 1. */
/* 0x101e6000 GPIO port 2. */
/* 0x101e7000 GPIO port 3. */
/* 0x101e8000 RTC. */
/* 0x101f0000 Smart card 0. */
/* 0x101f1000 UART0. */
/* 0x101f2000 UART1. */
/* 0x101f3000 UART2. */
/* 0x101f4000 SSPI. */
/* 0x34000000 NOR Flash */
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
VERSATILE_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
VERSATILE_FLASH_SECT_SIZE,
4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
versatile_binfo.ram_size = machine->ram_size;
versatile_binfo.kernel_filename = machine->kernel_filename;
versatile_binfo.kernel_cmdline = machine->kernel_cmdline;
versatile_binfo.initrd_filename = machine->initrd_filename;
versatile_binfo.board_id = board_id;
arm_load_kernel(cpu, &versatile_binfo);
}
static void vpb_init(MachineState *machine)
{
versatile_init(machine, 0x183);
}
static void vab_init(MachineState *machine)
{
versatile_init(machine, 0x25e);
}
static void versatilepb_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM Versatile/PB (ARM926EJ-S)";
mc->init = vpb_init;
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
static const TypeInfo versatilepb_type = {
.name = MACHINE_TYPE_NAME("versatilepb"),
.parent = TYPE_MACHINE,
.class_init = versatilepb_class_init,
};
static void versatileab_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM Versatile/AB (ARM926EJ-S)";
mc->init = vab_init;
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
}
static const TypeInfo versatileab_type = {
.name = MACHINE_TYPE_NAME("versatileab"),
.parent = TYPE_MACHINE,
.class_init = versatileab_class_init,
};
static void versatile_machine_init(void)
{
type_register_static(&versatilepb_type);
type_register_static(&versatileab_type);
}
type_init(versatile_machine_init)
static void vpb_sic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_vpb_sic;
}
static const TypeInfo vpb_sic_info = {
.name = TYPE_VERSATILE_PB_SIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(vpb_sic_state),
.instance_init = vpb_sic_init,
.class_init = vpb_sic_class_init,
};
static void versatilepb_register_types(void)
{
type_register_static(&vpb_sic_info);
}
type_init(versatilepb_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/hw/virtio/virtio-rng-pci.c | /*
* Virtio rng PCI Bindings
*
* Copyright 2012 Red Hat, Inc.
* Copyright 2012 <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or
* (at your option) any later version. See the COPYING file in the
* top-level directory.
*/
#include "qemu/osdep.h"
#include "virtio-pci.h"
#include "hw/virtio/virtio-rng.h"
#include "qapi/error.h"
typedef struct VirtIORngPCI VirtIORngPCI;
/*
* virtio-rng-pci: This extends VirtioPCIProxy.
*/
#define TYPE_VIRTIO_RNG_PCI "virtio-rng-pci-base"
#define VIRTIO_RNG_PCI(obj) \
OBJECT_CHECK(VirtIORngPCI, (obj), TYPE_VIRTIO_RNG_PCI)
struct VirtIORngPCI {
VirtIOPCIProxy parent_obj;
VirtIORNG vdev;
};
static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
{
VirtIORngPCI *vrng = VIRTIO_RNG_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&vrng->vdev);
Error *err = NULL;
qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
object_property_set_bool(OBJECT(vdev), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_link(OBJECT(vrng),
OBJECT(vrng->vdev.conf.rng), "rng",
NULL);
}
static void virtio_rng_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = virtio_rng_pci_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_RNG;
pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
pcidev_k->class_id = PCI_CLASS_OTHERS;
}
static void virtio_rng_initfn(Object *obj)
{
VirtIORngPCI *dev = VIRTIO_RNG_PCI(obj);
virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
TYPE_VIRTIO_RNG);
}
static const VirtioPCIDeviceTypeInfo virtio_rng_pci_info = {
.base_name = TYPE_VIRTIO_RNG_PCI,
.generic_name = "virtio-rng-pci",
.transitional_name = "virtio-rng-pci-transitional",
.non_transitional_name = "virtio-rng-pci-non-transitional",
.instance_size = sizeof(VirtIORngPCI),
.instance_init = virtio_rng_initfn,
.class_init = virtio_rng_pci_class_init,
};
static void virtio_rng_pci_register(void)
{
virtio_pci_types_register(&virtio_rng_pci_info);
}
type_init(virtio_rng_pci_register)
|
pmp-tool/PMP | src/qemu/src-pmp/hw/usb/combined-packet.c | <filename>src/qemu/src-pmp/hw/usb/combined-packet.c
/*
* QEMU USB packet combining code (for input pipelining)
*
* Copyright(c) 2012 Red Hat, Inc.
*
* Red Hat Authors:
* <NAME> <<EMAIL>>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "hw/usb.h"
#include "qemu/iov.h"
#include "trace.h"
static void usb_combined_packet_add(USBCombinedPacket *combined, USBPacket *p)
{
qemu_iovec_concat(&combined->iov, &p->iov, 0, p->iov.size);
QTAILQ_INSERT_TAIL(&combined->packets, p, combined_entry);
p->combined = combined;
}
/* Note will free combined when the last packet gets removed */
static void usb_combined_packet_remove(USBCombinedPacket *combined,
USBPacket *p)
{
assert(p->combined == combined);
p->combined = NULL;
QTAILQ_REMOVE(&combined->packets, p, combined_entry);
if (QTAILQ_EMPTY(&combined->packets)) {
qemu_iovec_destroy(&combined->iov);
g_free(combined);
}
}
/* Also handles completion of non combined packets for pipelined input eps */
void usb_combined_input_packet_complete(USBDevice *dev, USBPacket *p)
{
USBCombinedPacket *combined = p->combined;
USBEndpoint *ep = p->ep;
USBPacket *next;
int status, actual_length;
bool short_not_ok, done = false;
if (combined == NULL) {
usb_packet_complete_one(dev, p);
goto leave;
}
assert(combined->first == p && p == QTAILQ_FIRST(&combined->packets));
status = combined->first->status;
actual_length = combined->first->actual_length;
short_not_ok = QTAILQ_LAST(&combined->packets)->short_not_ok;
QTAILQ_FOREACH_SAFE(p, &combined->packets, combined_entry, next) {
if (!done) {
/* Distribute data over uncombined packets */
if (actual_length >= p->iov.size) {
p->actual_length = p->iov.size;
} else {
/* Send short or error packet to complete the transfer */
p->actual_length = actual_length;
done = true;
}
/* Report status on the last packet */
if (done || next == NULL) {
p->status = status;
} else {
p->status = USB_RET_SUCCESS;
}
p->short_not_ok = short_not_ok;
/* Note will free combined when the last packet gets removed! */
usb_combined_packet_remove(combined, p);
usb_packet_complete_one(dev, p);
actual_length -= p->actual_length;
} else {
/* Remove any leftover packets from the queue */
p->status = USB_RET_REMOVE_FROM_QUEUE;
/* Note will free combined on the last packet! */
dev->port->ops->complete(dev->port, p);
}
}
/* Do not use combined here, it has been freed! */
leave:
/* Check if there are packets in the queue waiting for our completion */
usb_ep_combine_input_packets(ep);
}
/* May only be called for combined packets! */
void usb_combined_packet_cancel(USBDevice *dev, USBPacket *p)
{
USBCombinedPacket *combined = p->combined;
assert(combined != NULL);
USBPacket *first = p->combined->first;
/* Note will free combined on the last packet! */
usb_combined_packet_remove(combined, p);
if (p == first) {
usb_device_cancel_packet(dev, p);
}
}
/*
* Large input transfers can get split into multiple input packets, this
* function recombines them, removing the short_not_ok checks which all but
* the last packet of such splits transfers have, thereby allowing input
* transfer pipelining (which we cannot do on short_not_ok transfers)
*/
void usb_ep_combine_input_packets(USBEndpoint *ep)
{
USBPacket *p, *u, *next, *prev = NULL, *first = NULL;
USBPort *port = ep->dev->port;
int totalsize;
assert(ep->pipeline);
assert(ep->pid == USB_TOKEN_IN);
QTAILQ_FOREACH_SAFE(p, &ep->queue, queue, next) {
/* Empty the queue on a halt */
if (ep->halted) {
p->status = USB_RET_REMOVE_FROM_QUEUE;
port->ops->complete(port, p);
continue;
}
/* Skip packets already submitted to the device */
if (p->state == USB_PACKET_ASYNC) {
prev = p;
continue;
}
usb_packet_check_state(p, USB_PACKET_QUEUED);
/*
* If the previous (combined) packet has the short_not_ok flag set
* stop, as we must not submit packets to the device after a transfer
* ending with short_not_ok packet.
*/
if (prev && prev->short_not_ok) {
break;
}
if (first) {
if (first->combined == NULL) {
USBCombinedPacket *combined = g_new0(USBCombinedPacket, 1);
combined->first = first;
QTAILQ_INIT(&combined->packets);
qemu_iovec_init(&combined->iov, 2);
usb_combined_packet_add(combined, first);
}
usb_combined_packet_add(first->combined, p);
} else {
first = p;
}
/* Is this packet the last one of a (combined) transfer? */
totalsize = (p->combined) ? p->combined->iov.size : p->iov.size;
if ((p->iov.size % ep->max_packet_size) != 0 || !p->short_not_ok ||
next == NULL ||
/* Work around for Linux usbfs bulk splitting + migration */
(totalsize == (16 * KiB - 36) && p->int_req)) {
usb_device_handle_data(ep->dev, first);
assert(first->status == USB_RET_ASYNC);
if (first->combined) {
QTAILQ_FOREACH(u, &first->combined->packets, combined_entry) {
usb_packet_set_state(u, USB_PACKET_ASYNC);
}
} else {
usb_packet_set_state(first, USB_PACKET_ASYNC);
}
first = NULL;
prev = p;
}
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/target/s390x/vec_helper.c | /*
* QEMU TCG support -- s390x vector support instructions
*
* Copyright (C) 2019 Red Hat Inc
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "internal.h"
#include "vec.h"
#include "tcg/tcg.h"
#include "tcg/tcg-gvec-desc.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes)
{
if (likely(bytes >= 16)) {
uint64_t t0, t1;
t0 = cpu_ldq_data_ra(env, addr, GETPC());
addr = wrap_address(env, addr + 8);
t1 = cpu_ldq_data_ra(env, addr, GETPC());
s390_vec_write_element64(v1, 0, t0);
s390_vec_write_element64(v1, 1, t1);
} else {
S390Vector tmp = {};
int i;
for (i = 0; i < bytes; i++) {
uint8_t byte = cpu_ldub_data_ra(env, addr, GETPC());
s390_vec_write_element8(&tmp, i, byte);
addr = wrap_address(env, addr + 1);
}
*(S390Vector *)v1 = tmp;
}
}
#define DEF_VPK_HFN(BITS, TBITS) \
typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
static int vpk##BITS##_hfn(S390Vector *v1, const S390Vector *v2, \
const S390Vector *v3, vpk##BITS##_fn fn) \
{ \
int i, saturated = 0; \
S390Vector tmp; \
\
for (i = 0; i < (128 / TBITS); i++) { \
uint##BITS##_t src; \
\
if (i < (128 / BITS)) { \
src = s390_vec_read_element##BITS(v2, i); \
} else { \
src = s390_vec_read_element##BITS(v3, i - (128 / BITS)); \
} \
s390_vec_write_element##TBITS(&tmp, i, fn(src, &saturated)); \
} \
*v1 = tmp; \
return saturated; \
}
DEF_VPK_HFN(64, 32)
DEF_VPK_HFN(32, 16)
DEF_VPK_HFN(16, 8)
#define DEF_VPK(BITS, TBITS) \
static uint##TBITS##_t vpk##BITS##e(uint##BITS##_t src, int *saturated) \
{ \
return src; \
} \
void HELPER(gvec_vpk##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
{ \
vpk##BITS##_hfn(v1, v2, v3, vpk##BITS##e); \
}
DEF_VPK(64, 32)
DEF_VPK(32, 16)
DEF_VPK(16, 8)
#define DEF_VPKS(BITS, TBITS) \
static uint##TBITS##_t vpks##BITS##e(uint##BITS##_t src, int *saturated) \
{ \
if ((int##BITS##_t)src > INT##TBITS##_MAX) { \
(*saturated)++; \
return INT##TBITS##_MAX; \
} else if ((int##BITS##_t)src < INT##TBITS##_MIN) { \
(*saturated)++; \
return INT##TBITS##_MIN; \
} \
return src; \
} \
void HELPER(gvec_vpks##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
{ \
vpk##BITS##_hfn(v1, v2, v3, vpks##BITS##e); \
} \
void HELPER(gvec_vpks_cc##BITS)(void *v1, const void *v2, const void *v3, \
CPUS390XState *env, uint32_t desc) \
{ \
int saturated = vpk##BITS##_hfn(v1, v2, v3, vpks##BITS##e); \
\
if (saturated == (128 / TBITS)) { \
env->cc_op = 3; \
} else if (saturated) { \
env->cc_op = 1; \
} else { \
env->cc_op = 0; \
} \
}
DEF_VPKS(64, 32)
DEF_VPKS(32, 16)
DEF_VPKS(16, 8)
#define DEF_VPKLS(BITS, TBITS) \
static uint##TBITS##_t vpkls##BITS##e(uint##BITS##_t src, int *saturated) \
{ \
if (src > UINT##TBITS##_MAX) { \
(*saturated)++; \
return UINT##TBITS##_MAX; \
} \
return src; \
} \
void HELPER(gvec_vpkls##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
{ \
vpk##BITS##_hfn(v1, v2, v3, vpkls##BITS##e); \
} \
void HELPER(gvec_vpkls_cc##BITS)(void *v1, const void *v2, const void *v3, \
CPUS390XState *env, uint32_t desc) \
{ \
int saturated = vpk##BITS##_hfn(v1, v2, v3, vpkls##BITS##e); \
\
if (saturated == (128 / TBITS)) { \
env->cc_op = 3; \
} else if (saturated) { \
env->cc_op = 1; \
} else { \
env->cc_op = 0; \
} \
}
DEF_VPKLS(64, 32)
DEF_VPKLS(32, 16)
DEF_VPKLS(16, 8)
void HELPER(gvec_vperm)(void *v1, const void *v2, const void *v3,
const void *v4, uint32_t desc)
{
S390Vector tmp;
int i;
for (i = 0; i < 16; i++) {
const uint8_t selector = s390_vec_read_element8(v4, i) & 0x1f;
uint8_t byte;
if (selector < 16) {
byte = s390_vec_read_element8(v2, selector);
} else {
byte = s390_vec_read_element8(v3, selector - 16);
}
s390_vec_write_element8(&tmp, i, byte);
}
*(S390Vector *)v1 = tmp;
}
void HELPER(vstl)(CPUS390XState *env, const void *v1, uint64_t addr,
uint64_t bytes)
{
/* Probe write access before actually modifying memory */
probe_write_access(env, addr, bytes, GETPC());
if (likely(bytes >= 16)) {
cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC());
addr = wrap_address(env, addr + 8);
cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC());
} else {
S390Vector tmp = {};
int i;
for (i = 0; i < bytes; i++) {
uint8_t byte = s390_vec_read_element8(v1, i);
cpu_stb_data_ra(env, addr, byte, GETPC());
addr = wrap_address(env, addr + 1);
}
*(S390Vector *)v1 = tmp;
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/target/xtensa/op_helper.c | /*
* Copyright (c) 2011, <NAME>, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
#include "qemu/timer.h"
#ifndef CONFIG_USER_ONLY
void HELPER(update_ccount)(CPUXtensaState *env)
{
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
env->ccount_time = now;
env->sregs[CCOUNT] = env->ccount_base +
(uint32_t)((now - env->time_base) *
env->config->clock_freq_khz / 1000000);
}
void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
{
int i;
HELPER(update_ccount)(env);
env->ccount_base += v - env->sregs[CCOUNT];
for (i = 0; i < env->config->nccompare; ++i) {
HELPER(update_ccompare)(env, i);
}
}
void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
{
uint64_t dcc;
atomic_and(&env->sregs[INTSET],
~(1u << env->config->timerint[i]));
HELPER(update_ccount)(env);
dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
timer_mod(env->ccompare[i].timer,
env->ccount_time + (dcc * 1000000) / env->config->clock_freq_khz);
env->yield_needed = 1;
}
/*!
* Check vaddr accessibility/cache attributes and raise an exception if
* specified by the ATOMCTL SR.
*
* Note: local memory exclusion is not implemented
*/
void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
{
uint32_t paddr, page_size, access;
uint32_t atomctl = env->sregs[ATOMCTL];
int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
xtensa_get_cring(env), &paddr, &page_size, &access);
/*
* s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
* see opcode description in the ISA
*/
if (rc == 0 &&
(access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
rc = STORE_PROHIBITED_CAUSE;
}
if (rc) {
HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
}
/*
* When data cache is not configured use ATOMCTL bypass field.
* See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
* under the Conditional Store Option.
*/
if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
access = PAGE_CACHE_BYPASS;
}
switch (access & PAGE_CACHE_MASK) {
case PAGE_CACHE_WB:
atomctl >>= 2;
/* fall through */
case PAGE_CACHE_WT:
atomctl >>= 2;
/* fall through */
case PAGE_CACHE_BYPASS:
if ((atomctl & 0x3) == 0) {
HELPER(exception_cause_vaddr)(env, pc,
LOAD_STORE_ERROR_CAUSE, vaddr);
}
break;
case PAGE_CACHE_ISOLATE:
HELPER(exception_cause_vaddr)(env, pc,
LOAD_STORE_ERROR_CAUSE, vaddr);
break;
default:
break;
}
}
void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) {
if (extract32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN) >
env->config->icache_ways) {
deposit32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN,
env->config->icache_ways);
}
}
if (xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
if (extract32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN) >
env->config->dcache_ways) {
deposit32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN,
env->config->dcache_ways);
}
if (extract32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN) >
env->config->dcache_ways) {
deposit32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN,
env->config->dcache_ways);
}
}
env->sregs[MEMCTL] = v & env->config->memctl_mask;
}
#endif
uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr)
{
#ifndef CONFIG_USER_ONLY
return address_space_ldl(env->address_space_er, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
#else
return 0;
#endif
}
void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr)
{
#ifndef CONFIG_USER_ONLY
address_space_stl(env->address_space_er, addr, data,
MEMTXATTRS_UNSPECIFIED, NULL);
#endif
}
|
pmp-tool/PMP | src/qemu/src-pmp/slirp/src/vmstate.c | /* SPDX-License-Identifier: BSD-3-Clause */
/*
* VMState interpreter
*
* Copyright (c) 2009-2018 Red Hat Inc
*
* Authors:
* <NAME> <<EMAIL>>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <errno.h>
#include <string.h>
#include <glib.h>
#include "stream.h"
#include "vmstate.h"
static int get_nullptr(SlirpIStream *f, void *pv, size_t size,
const VMStateField *field)
{
if (slirp_istream_read_u8(f) == VMS_NULLPTR_MARKER) {
return 0;
}
g_warning("vmstate: get_nullptr expected VMS_NULLPTR_MARKER");
return -EINVAL;
}
static int put_nullptr(SlirpOStream *f, void *pv, size_t size,
const VMStateField *field)
{
if (pv == NULL) {
slirp_ostream_write_u8(f, VMS_NULLPTR_MARKER);
return 0;
}
g_warning("vmstate: put_nullptr must be called with pv == NULL");
return -EINVAL;
}
const VMStateInfo slirp_vmstate_info_nullptr = {
.name = "uint64",
.get = get_nullptr,
.put = put_nullptr,
};
/* 8 bit unsigned int */
static int get_uint8(SlirpIStream *f, void *pv, size_t size, const VMStateField *field)
{
uint8_t *v = pv;
*v = slirp_istream_read_u8(f);
return 0;
}
static int put_uint8(SlirpOStream *f, void *pv, size_t size, const VMStateField *field)
{
uint8_t *v = pv;
slirp_ostream_write_u8(f, *v);
return 0;
}
const VMStateInfo slirp_vmstate_info_uint8 = {
.name = "uint8",
.get = get_uint8,
.put = put_uint8,
};
/* 16 bit unsigned int */
static int get_uint16(SlirpIStream *f, void *pv, size_t size,
const VMStateField *field)
{
uint16_t *v = pv;
*v = slirp_istream_read_u16(f);
return 0;
}
static int put_uint16(SlirpOStream *f, void *pv, size_t size,
const VMStateField *field)
{
uint16_t *v = pv;
slirp_ostream_write_u16(f, *v);
return 0;
}
const VMStateInfo slirp_vmstate_info_uint16 = {
.name = "uint16",
.get = get_uint16,
.put = put_uint16,
};
/* 32 bit unsigned int */
static int get_uint32(SlirpIStream *f, void *pv, size_t size,
const VMStateField *field)
{
uint32_t *v = pv;
*v = slirp_istream_read_u32(f);
return 0;
}
static int put_uint32(SlirpOStream *f, void *pv, size_t size,
const VMStateField *field)
{
uint32_t *v = pv;
slirp_ostream_write_u32(f, *v);
return 0;
}
const VMStateInfo slirp_vmstate_info_uint32 = {
.name = "uint32",
.get = get_uint32,
.put = put_uint32,
};
/* 16 bit int */
static int get_int16(SlirpIStream *f, void *pv, size_t size, const VMStateField *field)
{
int16_t *v = pv;
*v = slirp_istream_read_i16(f);
return 0;
}
static int put_int16(SlirpOStream *f, void *pv, size_t size, const VMStateField *field)
{
int16_t *v = pv;
slirp_ostream_write_i16(f, *v);
return 0;
}
const VMStateInfo slirp_vmstate_info_int16 = {
.name = "int16",
.get = get_int16,
.put = put_int16,
};
/* 32 bit int */
static int get_int32(SlirpIStream *f, void *pv, size_t size, const VMStateField *field)
{
int32_t *v = pv;
*v = slirp_istream_read_i32(f);
return 0;
}
static int put_int32(SlirpOStream *f, void *pv, size_t size, const VMStateField *field)
{
int32_t *v = pv;
slirp_ostream_write_i32(f, *v);
return 0;
}
const VMStateInfo slirp_vmstate_info_int32 = {
.name = "int32",
.get = get_int32,
.put = put_int32,
};
/* vmstate_info_tmp, see VMSTATE_WITH_TMP, the idea is that we allocate
* a temporary buffer and the pre_load/pre_save methods in the child vmsd
* copy stuff from the parent into the child and do calculations to fill
* in fields that don't really exist in the parent but need to be in the
* stream.
*/
static int get_tmp(SlirpIStream *f, void *pv, size_t size, const VMStateField *field)
{
int ret;
const VMStateDescription *vmsd = field->vmsd;
int version_id = field->version_id;
void *tmp = g_malloc(size);
/* Writes the parent field which is at the start of the tmp */
*(void **)tmp = pv;
ret = slirp_vmstate_load_state(f, vmsd, tmp, version_id);
g_free(tmp);
return ret;
}
static int put_tmp(SlirpOStream *f, void *pv, size_t size, const VMStateField *field)
{
const VMStateDescription *vmsd = field->vmsd;
void *tmp = g_malloc(size);
int ret;
/* Writes the parent field which is at the start of the tmp */
*(void **)tmp = pv;
ret = slirp_vmstate_save_state(f, vmsd, tmp);
g_free(tmp);
return ret;
}
const VMStateInfo slirp_vmstate_info_tmp = {
.name = "tmp",
.get = get_tmp,
.put = put_tmp,
};
/* uint8_t buffers */
static int get_buffer(SlirpIStream *f, void *pv, size_t size,
const VMStateField *field)
{
slirp_istream_read(f, pv, size);
return 0;
}
static int put_buffer(SlirpOStream *f, void *pv, size_t size,
const VMStateField *field)
{
slirp_ostream_write(f, pv, size);
return 0;
}
const VMStateInfo slirp_vmstate_info_buffer = {
.name = "buffer",
.get = get_buffer,
.put = put_buffer,
};
static int vmstate_n_elems(void *opaque, const VMStateField *field)
{
int n_elems = 1;
if (field->flags & VMS_ARRAY) {
n_elems = field->num;
} else if (field->flags & VMS_VARRAY_INT32) {
n_elems = *(int32_t *)(opaque + field->num_offset);
} else if (field->flags & VMS_VARRAY_UINT32) {
n_elems = *(uint32_t *)(opaque + field->num_offset);
} else if (field->flags & VMS_VARRAY_UINT16) {
n_elems = *(uint16_t *)(opaque + field->num_offset);
} else if (field->flags & VMS_VARRAY_UINT8) {
n_elems = *(uint8_t *)(opaque + field->num_offset);
}
if (field->flags & VMS_MULTIPLY_ELEMENTS) {
n_elems *= field->num;
}
return n_elems;
}
static int vmstate_size(void *opaque, const VMStateField *field)
{
int size = field->size;
if (field->flags & VMS_VBUFFER) {
size = *(int32_t *)(opaque + field->size_offset);
if (field->flags & VMS_MULTIPLY) {
size *= field->size;
}
}
return size;
}
static int
vmstate_save_state_v(SlirpOStream *f, const VMStateDescription *vmsd,
void *opaque, int version_id)
{
int ret = 0;
const VMStateField *field = vmsd->fields;
if (vmsd->pre_save) {
ret = vmsd->pre_save(opaque);
if (ret) {
g_warning("pre-save failed: %s", vmsd->name);
return ret;
}
}
while (field->name) {
if ((field->field_exists &&
field->field_exists(opaque, version_id)) ||
(!field->field_exists &&
field->version_id <= version_id)) {
void *first_elem = opaque + field->offset;
int i, n_elems = vmstate_n_elems(opaque, field);
int size = vmstate_size(opaque, field);
if (field->flags & VMS_POINTER) {
first_elem = *(void **)first_elem;
assert(first_elem || !n_elems || !size);
}
for (i = 0; i < n_elems; i++) {
void *curr_elem = first_elem + size * i;
ret = 0;
if (field->flags & VMS_ARRAY_OF_POINTER) {
assert(curr_elem);
curr_elem = *(void **)curr_elem;
}
if (!curr_elem && size) {
/* if null pointer write placeholder and do not follow */
assert(field->flags & VMS_ARRAY_OF_POINTER);
ret = slirp_vmstate_info_nullptr.put(f, curr_elem, size, NULL);
} else if (field->flags & VMS_STRUCT) {
ret = slirp_vmstate_save_state(f, field->vmsd, curr_elem);
} else if (field->flags & VMS_VSTRUCT) {
ret = vmstate_save_state_v(f, field->vmsd, curr_elem,
field->struct_version_id);
} else {
ret = field->info->put(f, curr_elem, size, field);
}
if (ret) {
g_warning("Save of field %s/%s failed",
vmsd->name, field->name);
return ret;
}
}
} else {
if (field->flags & VMS_MUST_EXIST) {
g_warning("Output state validation failed: %s/%s",
vmsd->name, field->name);
assert(!(field->flags & VMS_MUST_EXIST));
}
}
field++;
}
return 0;
}
int slirp_vmstate_save_state(SlirpOStream *f, const VMStateDescription *vmsd,
void *opaque)
{
return vmstate_save_state_v(f, vmsd, opaque, vmsd->version_id);
}
static void vmstate_handle_alloc(void *ptr, VMStateField *field, void *opaque)
{
if (field->flags & VMS_POINTER && field->flags & VMS_ALLOC) {
size_t size = vmstate_size(opaque, field);
size *= vmstate_n_elems(opaque, field);
if (size) {
*(void **)ptr = g_malloc(size);
}
}
}
int slirp_vmstate_load_state(SlirpIStream *f, const VMStateDescription *vmsd,
void *opaque, int version_id)
{
VMStateField *field = vmsd->fields;
int ret = 0;
if (version_id > vmsd->version_id) {
g_warning("%s: incoming version_id %d is too new "
"for local version_id %d",
vmsd->name, version_id, vmsd->version_id);
return -EINVAL;
}
if (vmsd->pre_load) {
int ret = vmsd->pre_load(opaque);
if (ret) {
return ret;
}
}
while (field->name) {
if ((field->field_exists &&
field->field_exists(opaque, version_id)) ||
(!field->field_exists &&
field->version_id <= version_id)) {
void *first_elem = opaque + field->offset;
int i, n_elems = vmstate_n_elems(opaque, field);
int size = vmstate_size(opaque, field);
vmstate_handle_alloc(first_elem, field, opaque);
if (field->flags & VMS_POINTER) {
first_elem = *(void **)first_elem;
assert(first_elem || !n_elems || !size);
}
for (i = 0; i < n_elems; i++) {
void *curr_elem = first_elem + size * i;
if (field->flags & VMS_ARRAY_OF_POINTER) {
curr_elem = *(void **)curr_elem;
}
if (!curr_elem && size) {
/* if null pointer check placeholder and do not follow */
assert(field->flags & VMS_ARRAY_OF_POINTER);
ret = slirp_vmstate_info_nullptr.get(f, curr_elem, size, NULL);
} else if (field->flags & VMS_STRUCT) {
ret = slirp_vmstate_load_state(f, field->vmsd, curr_elem,
field->vmsd->version_id);
} else if (field->flags & VMS_VSTRUCT) {
ret = slirp_vmstate_load_state(f, field->vmsd, curr_elem,
field->struct_version_id);
} else {
ret = field->info->get(f, curr_elem, size, field);
}
if (ret < 0) {
g_warning("Failed to load %s:%s", vmsd->name,
field->name);
return ret;
}
}
} else if (field->flags & VMS_MUST_EXIST) {
g_warning("Input validation failed: %s/%s",
vmsd->name, field->name);
return -1;
}
field++;
}
if (vmsd->post_load) {
ret = vmsd->post_load(opaque, version_id);
}
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/audio/wavaudio.c | /*
* QEMU WAV audio driver
*
* Copyright (c) 2004-2005 <NAME> (malc)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/timer.h"
#include "qapi/opts-visitor.h"
#include "audio.h"
#define AUDIO_CAP "wav"
#include "audio_int.h"
typedef struct WAVVoiceOut {
HWVoiceOut hw;
FILE *f;
int64_t old_ticks;
void *pcm_buf;
int total_samples;
} WAVVoiceOut;
static int wav_run_out (HWVoiceOut *hw, int live)
{
WAVVoiceOut *wav = (WAVVoiceOut *) hw;
int rpos, decr, samples;
uint8_t *dst;
struct st_sample *src;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t ticks = now - wav->old_ticks;
int64_t bytes =
muldiv64(ticks, hw->info.bytes_per_second, NANOSECONDS_PER_SECOND);
if (bytes > INT_MAX) {
samples = INT_MAX >> hw->info.shift;
}
else {
samples = bytes >> hw->info.shift;
}
wav->old_ticks = now;
decr = audio_MIN (live, samples);
samples = decr;
rpos = hw->rpos;
while (samples) {
int left_till_end_samples = hw->samples - rpos;
int convert_samples = audio_MIN (samples, left_till_end_samples);
src = hw->mix_buf + rpos;
dst = advance (wav->pcm_buf, rpos << hw->info.shift);
hw->clip (dst, src, convert_samples);
if (fwrite (dst, convert_samples << hw->info.shift, 1, wav->f) != 1) {
dolog ("wav_run_out: fwrite of %d bytes failed\nReaons: %s\n",
convert_samples << hw->info.shift, strerror (errno));
}
rpos = (rpos + convert_samples) % hw->samples;
samples -= convert_samples;
wav->total_samples += convert_samples;
}
hw->rpos = rpos;
return decr;
}
static int wav_write_out (SWVoiceOut *sw, void *buf, int len)
{
return audio_pcm_sw_write (sw, buf, len);
}
/* VICE code: Store number as little endian. */
static void le_store (uint8_t *buf, uint32_t val, int len)
{
int i;
for (i = 0; i < len; i++) {
buf[i] = (uint8_t) (val & 0xff);
val >>= 8;
}
}
static int wav_init_out(HWVoiceOut *hw, struct audsettings *as,
void *drv_opaque)
{
WAVVoiceOut *wav = (WAVVoiceOut *) hw;
int bits16 = 0, stereo = 0;
uint8_t hdr[] = {
0x52, 0x49, 0x46, 0x46, 0x00, 0x00, 0x00, 0x00, 0x57, 0x41, 0x56,
0x45, 0x66, 0x6d, 0x74, 0x20, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,
0x02, 0x00, 0x44, 0xac, 0x00, 0x00, 0x10, 0xb1, 0x02, 0x00, 0x04,
0x00, 0x10, 0x00, 0x64, 0x61, 0x74, 0x61, 0x00, 0x00, 0x00, 0x00
};
Audiodev *dev = drv_opaque;
AudiodevWavOptions *wopts = &dev->u.wav;
struct audsettings wav_as = audiodev_to_audsettings(dev->u.wav.out);
const char *wav_path = wopts->has_path ? wopts->path : "qemu.wav";
stereo = wav_as.nchannels == 2;
switch (wav_as.fmt) {
case AUDIO_FORMAT_S8:
case AUDIO_FORMAT_U8:
bits16 = 0;
break;
case AUDIO_FORMAT_S16:
case AUDIO_FORMAT_U16:
bits16 = 1;
break;
case AUDIO_FORMAT_S32:
case AUDIO_FORMAT_U32:
dolog ("WAVE files can not handle 32bit formats\n");
return -1;
default:
abort();
}
hdr[34] = bits16 ? 0x10 : 0x08;
wav_as.endianness = 0;
audio_pcm_init_info (&hw->info, &wav_as);
hw->samples = 1024;
wav->pcm_buf = audio_calloc(__func__, hw->samples, 1 << hw->info.shift);
if (!wav->pcm_buf) {
dolog ("Could not allocate buffer (%d bytes)\n",
hw->samples << hw->info.shift);
return -1;
}
le_store (hdr + 22, hw->info.nchannels, 2);
le_store (hdr + 24, hw->info.freq, 4);
le_store (hdr + 28, hw->info.freq << (bits16 + stereo), 4);
le_store (hdr + 32, 1 << (bits16 + stereo), 2);
wav->f = fopen(wav_path, "wb");
if (!wav->f) {
dolog ("Failed to open wave file `%s'\nReason: %s\n",
wav_path, strerror(errno));
g_free (wav->pcm_buf);
wav->pcm_buf = NULL;
return -1;
}
if (fwrite (hdr, sizeof (hdr), 1, wav->f) != 1) {
dolog ("wav_init_out: failed to write header\nReason: %s\n",
strerror(errno));
return -1;
}
return 0;
}
static void wav_fini_out (HWVoiceOut *hw)
{
WAVVoiceOut *wav = (WAVVoiceOut *) hw;
uint8_t rlen[4];
uint8_t dlen[4];
uint32_t datalen = wav->total_samples << hw->info.shift;
uint32_t rifflen = datalen + 36;
if (!wav->f) {
return;
}
le_store (rlen, rifflen, 4);
le_store (dlen, datalen, 4);
if (fseek (wav->f, 4, SEEK_SET)) {
dolog ("wav_fini_out: fseek to rlen failed\nReason: %s\n",
strerror(errno));
goto doclose;
}
if (fwrite (rlen, 4, 1, wav->f) != 1) {
dolog ("wav_fini_out: failed to write rlen\nReason: %s\n",
strerror (errno));
goto doclose;
}
if (fseek (wav->f, 32, SEEK_CUR)) {
dolog ("wav_fini_out: fseek to dlen failed\nReason: %s\n",
strerror (errno));
goto doclose;
}
if (fwrite (dlen, 4, 1, wav->f) != 1) {
dolog ("wav_fini_out: failed to write dlen\nReaons: %s\n",
strerror (errno));
goto doclose;
}
doclose:
if (fclose (wav->f)) {
dolog ("wav_fini_out: fclose %p failed\nReason: %s\n",
wav->f, strerror (errno));
}
wav->f = NULL;
g_free (wav->pcm_buf);
wav->pcm_buf = NULL;
}
static int wav_ctl_out (HWVoiceOut *hw, int cmd, ...)
{
(void) hw;
(void) cmd;
return 0;
}
static void *wav_audio_init(Audiodev *dev)
{
assert(dev->driver == AUDIODEV_DRIVER_WAV);
return dev;
}
static void wav_audio_fini (void *opaque)
{
ldebug ("wav_fini");
}
static struct audio_pcm_ops wav_pcm_ops = {
.init_out = wav_init_out,
.fini_out = wav_fini_out,
.run_out = wav_run_out,
.write = wav_write_out,
.ctl_out = wav_ctl_out,
};
static struct audio_driver wav_audio_driver = {
.name = "wav",
.descr = "WAV renderer http://wikipedia.org/wiki/WAV",
.init = wav_audio_init,
.fini = wav_audio_fini,
.pcm_ops = &wav_pcm_ops,
.can_be_default = 0,
.max_voices_out = 1,
.max_voices_in = 0,
.voice_size_out = sizeof (WAVVoiceOut),
.voice_size_in = 0
};
static void register_audio_wav(void)
{
audio_driver_register(&wav_audio_driver);
}
type_init(register_audio_wav);
|
pmp-tool/PMP | src/qemu/src-pmp/target/hppa/translate.c | /*
* HPPA emulation cpu translation for qemu.
*
* Copyright (c) 2016 <NAME> <<EMAIL>>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "disas/disas.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
#include "trace-tcg.h"
#include "exec/log.h"
/* Since we have a distinction between register size and address size,
we need to redefine all of these. */
#undef TCGv
#undef tcg_temp_new
#undef tcg_global_reg_new
#undef tcg_global_mem_new
#undef tcg_temp_local_new
#undef tcg_temp_free
#if TARGET_LONG_BITS == 64
#define TCGv_tl TCGv_i64
#define tcg_temp_new_tl tcg_temp_new_i64
#define tcg_temp_free_tl tcg_temp_free_i64
#if TARGET_REGISTER_BITS == 64
#define tcg_gen_extu_reg_tl tcg_gen_mov_i64
#else
#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
#endif
#else
#define TCGv_tl TCGv_i32
#define tcg_temp_new_tl tcg_temp_new_i32
#define tcg_temp_free_tl tcg_temp_free_i32
#define tcg_gen_extu_reg_tl tcg_gen_mov_i32
#endif
#if TARGET_REGISTER_BITS == 64
#define TCGv_reg TCGv_i64
#define tcg_temp_new tcg_temp_new_i64
#define tcg_global_reg_new tcg_global_reg_new_i64
#define tcg_global_mem_new tcg_global_mem_new_i64
#define tcg_temp_local_new tcg_temp_local_new_i64
#define tcg_temp_free tcg_temp_free_i64
#define tcg_gen_movi_reg tcg_gen_movi_i64
#define tcg_gen_mov_reg tcg_gen_mov_i64
#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
#define tcg_gen_ld_reg tcg_gen_ld_i64
#define tcg_gen_st8_reg tcg_gen_st8_i64
#define tcg_gen_st16_reg tcg_gen_st16_i64
#define tcg_gen_st32_reg tcg_gen_st32_i64
#define tcg_gen_st_reg tcg_gen_st_i64
#define tcg_gen_add_reg tcg_gen_add_i64
#define tcg_gen_addi_reg tcg_gen_addi_i64
#define tcg_gen_sub_reg tcg_gen_sub_i64
#define tcg_gen_neg_reg tcg_gen_neg_i64
#define tcg_gen_subfi_reg tcg_gen_subfi_i64
#define tcg_gen_subi_reg tcg_gen_subi_i64
#define tcg_gen_and_reg tcg_gen_and_i64
#define tcg_gen_andi_reg tcg_gen_andi_i64
#define tcg_gen_or_reg tcg_gen_or_i64
#define tcg_gen_ori_reg tcg_gen_ori_i64
#define tcg_gen_xor_reg tcg_gen_xor_i64
#define tcg_gen_xori_reg tcg_gen_xori_i64
#define tcg_gen_not_reg tcg_gen_not_i64
#define tcg_gen_shl_reg tcg_gen_shl_i64
#define tcg_gen_shli_reg tcg_gen_shli_i64
#define tcg_gen_shr_reg tcg_gen_shr_i64
#define tcg_gen_shri_reg tcg_gen_shri_i64
#define tcg_gen_sar_reg tcg_gen_sar_i64
#define tcg_gen_sari_reg tcg_gen_sari_i64
#define tcg_gen_brcond_reg tcg_gen_brcond_i64
#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
#define tcg_gen_setcond_reg tcg_gen_setcond_i64
#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
#define tcg_gen_mul_reg tcg_gen_mul_i64
#define tcg_gen_muli_reg tcg_gen_muli_i64
#define tcg_gen_div_reg tcg_gen_div_i64
#define tcg_gen_rem_reg tcg_gen_rem_i64
#define tcg_gen_divu_reg tcg_gen_divu_i64
#define tcg_gen_remu_reg tcg_gen_remu_i64
#define tcg_gen_discard_reg tcg_gen_discard_i64
#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
#define tcg_gen_andc_reg tcg_gen_andc_i64
#define tcg_gen_eqv_reg tcg_gen_eqv_i64
#define tcg_gen_nand_reg tcg_gen_nand_i64
#define tcg_gen_nor_reg tcg_gen_nor_i64
#define tcg_gen_orc_reg tcg_gen_orc_i64
#define tcg_gen_clz_reg tcg_gen_clz_i64
#define tcg_gen_ctz_reg tcg_gen_ctz_i64
#define tcg_gen_clzi_reg tcg_gen_clzi_i64
#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
#define tcg_gen_rotl_reg tcg_gen_rotl_i64
#define tcg_gen_rotli_reg tcg_gen_rotli_i64
#define tcg_gen_rotr_reg tcg_gen_rotr_i64
#define tcg_gen_rotri_reg tcg_gen_rotri_i64
#define tcg_gen_deposit_reg tcg_gen_deposit_i64
#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
#define tcg_gen_extract_reg tcg_gen_extract_i64
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
#define tcg_const_reg tcg_const_i64
#define tcg_const_local_reg tcg_const_local_i64
#define tcg_gen_movcond_reg tcg_gen_movcond_i64
#define tcg_gen_add2_reg tcg_gen_add2_i64
#define tcg_gen_sub2_reg tcg_gen_sub2_i64
#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
#define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
#else
#define TCGv_reg TCGv_i32
#define tcg_temp_new tcg_temp_new_i32
#define tcg_global_reg_new tcg_global_reg_new_i32
#define tcg_global_mem_new tcg_global_mem_new_i32
#define tcg_temp_local_new tcg_temp_local_new_i32
#define tcg_temp_free tcg_temp_free_i32
#define tcg_gen_movi_reg tcg_gen_movi_i32
#define tcg_gen_mov_reg tcg_gen_mov_i32
#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
#define tcg_gen_ld32u_reg tcg_gen_ld_i32
#define tcg_gen_ld32s_reg tcg_gen_ld_i32
#define tcg_gen_ld_reg tcg_gen_ld_i32
#define tcg_gen_st8_reg tcg_gen_st8_i32
#define tcg_gen_st16_reg tcg_gen_st16_i32
#define tcg_gen_st32_reg tcg_gen_st32_i32
#define tcg_gen_st_reg tcg_gen_st_i32
#define tcg_gen_add_reg tcg_gen_add_i32
#define tcg_gen_addi_reg tcg_gen_addi_i32
#define tcg_gen_sub_reg tcg_gen_sub_i32
#define tcg_gen_neg_reg tcg_gen_neg_i32
#define tcg_gen_subfi_reg tcg_gen_subfi_i32
#define tcg_gen_subi_reg tcg_gen_subi_i32
#define tcg_gen_and_reg tcg_gen_and_i32
#define tcg_gen_andi_reg tcg_gen_andi_i32
#define tcg_gen_or_reg tcg_gen_or_i32
#define tcg_gen_ori_reg tcg_gen_ori_i32
#define tcg_gen_xor_reg tcg_gen_xor_i32
#define tcg_gen_xori_reg tcg_gen_xori_i32
#define tcg_gen_not_reg tcg_gen_not_i32
#define tcg_gen_shl_reg tcg_gen_shl_i32
#define tcg_gen_shli_reg tcg_gen_shli_i32
#define tcg_gen_shr_reg tcg_gen_shr_i32
#define tcg_gen_shri_reg tcg_gen_shri_i32
#define tcg_gen_sar_reg tcg_gen_sar_i32
#define tcg_gen_sari_reg tcg_gen_sari_i32
#define tcg_gen_brcond_reg tcg_gen_brcond_i32
#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
#define tcg_gen_setcond_reg tcg_gen_setcond_i32
#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
#define tcg_gen_mul_reg tcg_gen_mul_i32
#define tcg_gen_muli_reg tcg_gen_muli_i32
#define tcg_gen_div_reg tcg_gen_div_i32
#define tcg_gen_rem_reg tcg_gen_rem_i32
#define tcg_gen_divu_reg tcg_gen_divu_i32
#define tcg_gen_remu_reg tcg_gen_remu_i32
#define tcg_gen_discard_reg tcg_gen_discard_i32
#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
#define tcg_gen_extu_i32_reg tcg_gen_mov_i32
#define tcg_gen_ext_i32_reg tcg_gen_mov_i32
#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
#define tcg_gen_ext32u_reg tcg_gen_mov_i32
#define tcg_gen_ext32s_reg tcg_gen_mov_i32
#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
#define tcg_gen_andc_reg tcg_gen_andc_i32
#define tcg_gen_eqv_reg tcg_gen_eqv_i32
#define tcg_gen_nand_reg tcg_gen_nand_i32
#define tcg_gen_nor_reg tcg_gen_nor_i32
#define tcg_gen_orc_reg tcg_gen_orc_i32
#define tcg_gen_clz_reg tcg_gen_clz_i32
#define tcg_gen_ctz_reg tcg_gen_ctz_i32
#define tcg_gen_clzi_reg tcg_gen_clzi_i32
#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
#define tcg_gen_rotl_reg tcg_gen_rotl_i32
#define tcg_gen_rotli_reg tcg_gen_rotli_i32
#define tcg_gen_rotr_reg tcg_gen_rotr_i32
#define tcg_gen_rotri_reg tcg_gen_rotri_i32
#define tcg_gen_deposit_reg tcg_gen_deposit_i32
#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
#define tcg_gen_extract_reg tcg_gen_extract_i32
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
#define tcg_const_reg tcg_const_i32
#define tcg_const_local_reg tcg_const_local_i32
#define tcg_gen_movcond_reg tcg_gen_movcond_i32
#define tcg_gen_add2_reg tcg_gen_add2_i32
#define tcg_gen_sub2_reg tcg_gen_sub2_i32
#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
#define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
#endif /* TARGET_REGISTER_BITS */
typedef struct DisasCond {
TCGCond c;
TCGv_reg a0, a1;
bool a0_is_n;
bool a1_is_0;
} DisasCond;
typedef struct DisasContext {
DisasContextBase base;
CPUState *cs;
target_ureg iaoq_f;
target_ureg iaoq_b;
target_ureg iaoq_n;
TCGv_reg iaoq_n_var;
int ntempr, ntempl;
TCGv_reg tempr[8];
TCGv_tl templ[4];
DisasCond null_cond;
TCGLabel *null_lab;
uint32_t insn;
uint32_t tb_flags;
int mmu_idx;
int privilege;
bool psw_n_nonzero;
} DisasContext;
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
static int expand_sm_imm(int val)
{
if (val & PSW_SM_E) {
val = (val & ~PSW_SM_E) | PSW_E;
}
if (val & PSW_SM_W) {
val = (val & ~PSW_SM_W) | PSW_W;
}
return val;
}
/* Inverted space register indicates 0 means sr0 not inferred from base. */
static int expand_sr3x(int val)
{
return ~val;
}
/* Convert the M:A bits within a memory insn to the tri-state value
we use for the final M. */
static int ma_to_m(int val)
{
return val & 2 ? (val & 1 ? -1 : 1) : 0;
}
/* Convert the sign of the displacement to a pre or post-modify. */
static int pos_to_m(int val)
{
return val ? 1 : -1;
}
static int neg_to_m(int val)
{
return val ? -1 : 1;
}
/* Used for branch targets and fp memory ops. */
static int expand_shl2(int val)
{
return val << 2;
}
/* Used for fp memory ops. */
static int expand_shl3(int val)
{
return val << 3;
}
/* Used for assemble_21. */
static int expand_shl11(int val)
{
return val << 11;
}
/* Include the auto-generated decoder. */
#include "decode.inc.c"
/* We are not using a goto_tb (for whatever reason), but have updated
the iaq (for whatever reason), so don't do it again on exit. */
#define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
/* We are exiting the TB, but have neither emitted a goto_tb, nor
updated the iaq for the next instruction to be executed. */
#define DISAS_IAQ_N_STALE DISAS_TARGET_1
/* Similarly, but we want to return to the main loop immediately
to recognize unmasked interrupts. */
#define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
#define DISAS_EXIT DISAS_TARGET_3
/* global register indexes */
static TCGv_reg cpu_gr[32];
static TCGv_i64 cpu_sr[4];
static TCGv_i64 cpu_srH;
static TCGv_reg cpu_iaoq_f;
static TCGv_reg cpu_iaoq_b;
static TCGv_i64 cpu_iasq_f;
static TCGv_i64 cpu_iasq_b;
static TCGv_reg cpu_sar;
static TCGv_reg cpu_psw_n;
static TCGv_reg cpu_psw_v;
static TCGv_reg cpu_psw_cb;
static TCGv_reg cpu_psw_cb_msb;
#include "exec/gen-icount.h"
void hppa_translate_init(void)
{
#define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar;
static const GlobalVar vars[] = {
{ &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) },
DEF_VAR(psw_n),
DEF_VAR(psw_v),
DEF_VAR(psw_cb),
DEF_VAR(psw_cb_msb),
DEF_VAR(iaoq_f),
DEF_VAR(iaoq_b),
};
#undef DEF_VAR
/* Use the symbolic register names that match the disassembler. */
static const char gr_names[32][4] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
};
/* SR[4-7] are not global registers so that we can index them. */
static const char sr_names[5][4] = {
"sr0", "sr1", "sr2", "sr3", "srH"
};
int i;
cpu_gr[0] = NULL;
for (i = 1; i < 32; i++) {
cpu_gr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUHPPAState, gr[i]),
gr_names[i]);
}
for (i = 0; i < 4; i++) {
cpu_sr[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUHPPAState, sr[i]),
sr_names[i]);
}
cpu_srH = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUHPPAState, sr[4]),
sr_names[4]);
for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i];
*v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name);
}
cpu_iasq_f = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUHPPAState, iasq_f),
"iasq_f");
cpu_iasq_b = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUHPPAState, iasq_b),
"iasq_b");
}
static DisasCond cond_make_f(void)
{
return (DisasCond){
.c = TCG_COND_NEVER,
.a0 = NULL,
.a1 = NULL,
};
}
static DisasCond cond_make_t(void)
{
return (DisasCond){
.c = TCG_COND_ALWAYS,
.a0 = NULL,
.a1 = NULL,
};
}
static DisasCond cond_make_n(void)
{
return (DisasCond){
.c = TCG_COND_NE,
.a0 = cpu_psw_n,
.a0_is_n = true,
.a1 = NULL,
.a1_is_0 = true
};
}
static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0)
{
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
return (DisasCond){
.c = c, .a0 = a0, .a1_is_0 = true
};
}
static DisasCond cond_make_0(TCGCond c, TCGv_reg a0)
{
TCGv_reg tmp = tcg_temp_new();
tcg_gen_mov_reg(tmp, a0);
return cond_make_0_tmp(c, tmp);
}
static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1)
{
DisasCond r = { .c = c };
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
r.a0 = tcg_temp_new();
tcg_gen_mov_reg(r.a0, a0);
r.a1 = tcg_temp_new();
tcg_gen_mov_reg(r.a1, a1);
return r;
}
static void cond_prep(DisasCond *cond)
{
if (cond->a1_is_0) {
cond->a1_is_0 = false;
cond->a1 = tcg_const_reg(0);
}
}
static void cond_free(DisasCond *cond)
{
switch (cond->c) {
default:
if (!cond->a0_is_n) {
tcg_temp_free(cond->a0);
}
if (!cond->a1_is_0) {
tcg_temp_free(cond->a1);
}
cond->a0_is_n = false;
cond->a1_is_0 = false;
cond->a0 = NULL;
cond->a1 = NULL;
/* fallthru */
case TCG_COND_ALWAYS:
cond->c = TCG_COND_NEVER;
break;
case TCG_COND_NEVER:
break;
}
}
static TCGv_reg get_temp(DisasContext *ctx)
{
unsigned i = ctx->ntempr++;
g_assert(i < ARRAY_SIZE(ctx->tempr));
return ctx->tempr[i] = tcg_temp_new();
}
#ifndef CONFIG_USER_ONLY
static TCGv_tl get_temp_tl(DisasContext *ctx)
{
unsigned i = ctx->ntempl++;
g_assert(i < ARRAY_SIZE(ctx->templ));
return ctx->templ[i] = tcg_temp_new_tl();
}
#endif
static TCGv_reg load_const(DisasContext *ctx, target_sreg v)
{
TCGv_reg t = get_temp(ctx);
tcg_gen_movi_reg(t, v);
return t;
}
static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0) {
TCGv_reg t = get_temp(ctx);
tcg_gen_movi_reg(t, 0);
return t;
} else {
return cpu_gr[reg];
}
}
static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) {
return get_temp(ctx);
} else {
return cpu_gr[reg];
}
}
static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t)
{
if (ctx->null_cond.c != TCG_COND_NEVER) {
cond_prep(&ctx->null_cond);
tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0,
ctx->null_cond.a1, dest, t);
} else {
tcg_gen_mov_reg(dest, t);
}
}
static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t)
{
if (reg != 0) {
save_or_nullify(ctx, cpu_gr[reg], t);
}
}
#ifdef HOST_WORDS_BIGENDIAN
# define HI_OFS 0
# define LO_OFS 4
#else
# define HI_OFS 4
# define LO_OFS 0
#endif
static TCGv_i32 load_frw_i32(unsigned rt)
{
TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_ld_i32(ret, cpu_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
return ret;
}
static TCGv_i32 load_frw0_i32(unsigned rt)
{
if (rt == 0) {
return tcg_const_i32(0);
} else {
return load_frw_i32(rt);
}
}
static TCGv_i64 load_frw0_i64(unsigned rt)
{
if (rt == 0) {
return tcg_const_i64(0);
} else {
TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_ld32u_i64(ret, cpu_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
return ret;
}
}
static void save_frw_i32(unsigned rt, TCGv_i32 val)
{
tcg_gen_st_i32(val, cpu_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
}
#undef HI_OFS
#undef LO_OFS
static TCGv_i64 load_frd(unsigned rt)
{
TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt]));
return ret;
}
static TCGv_i64 load_frd0(unsigned rt)
{
if (rt == 0) {
return tcg_const_i64(0);
} else {
return load_frd(rt);
}
}
static void save_frd(unsigned rt, TCGv_i64 val)
{
tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt]));
}
static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg)
{
#ifdef CONFIG_USER_ONLY
tcg_gen_movi_i64(dest, 0);
#else
if (reg < 4) {
tcg_gen_mov_i64(dest, cpu_sr[reg]);
} else if (ctx->tb_flags & TB_FLAG_SR_SAME) {
tcg_gen_mov_i64(dest, cpu_srH);
} else {
tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg]));
}
#endif
}
/* Skip over the implementation of an insn that has been nullified.
Use this when the insn is too complex for a conditional move. */
static void nullify_over(DisasContext *ctx)
{
if (ctx->null_cond.c != TCG_COND_NEVER) {
/* The always condition should have been handled in the main loop. */
assert(ctx->null_cond.c != TCG_COND_ALWAYS);
ctx->null_lab = gen_new_label();
cond_prep(&ctx->null_cond);
/* If we're using PSW[N], copy it to a temp because... */
if (ctx->null_cond.a0_is_n) {
ctx->null_cond.a0_is_n = false;
ctx->null_cond.a0 = tcg_temp_new();
tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n);
}
/* ... we clear it before branching over the implementation,
so that (1) it's clear after nullifying this insn and
(2) if this insn nullifies the next, PSW[N] is valid. */
if (ctx->psw_n_nonzero) {
ctx->psw_n_nonzero = false;
tcg_gen_movi_reg(cpu_psw_n, 0);
}
tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0,
ctx->null_cond.a1, ctx->null_lab);
cond_free(&ctx->null_cond);
}
}
/* Save the current nullification state to PSW[N]. */
static void nullify_save(DisasContext *ctx)
{
if (ctx->null_cond.c == TCG_COND_NEVER) {
if (ctx->psw_n_nonzero) {
tcg_gen_movi_reg(cpu_psw_n, 0);
}
return;
}
if (!ctx->null_cond.a0_is_n) {
cond_prep(&ctx->null_cond);
tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n,
ctx->null_cond.a0, ctx->null_cond.a1);
ctx->psw_n_nonzero = true;
}
cond_free(&ctx->null_cond);
}
/* Set a PSW[N] to X. The intention is that this is used immediately
before a goto_tb/exit_tb, so that there is no fallthru path to other
code within the TB. Therefore we do not update psw_n_nonzero. */
static void nullify_set(DisasContext *ctx, bool x)
{
if (ctx->psw_n_nonzero || x) {
tcg_gen_movi_reg(cpu_psw_n, x);
}
}
/* Mark the end of an instruction that may have been nullified.
This is the pair to nullify_over. Always returns true so that
it may be tail-called from a translate function. */
static bool nullify_end(DisasContext *ctx)
{
TCGLabel *null_lab = ctx->null_lab;
DisasJumpType status = ctx->base.is_jmp;
/* For NEXT, NORETURN, STALE, we can easily continue (or exit).
For UPDATED, we cannot update on the nullified path. */
assert(status != DISAS_IAQ_N_UPDATED);
if (likely(null_lab == NULL)) {
/* The current insn wasn't conditional or handled the condition
applied to it without a branch, so the (new) setting of
NULL_COND can be applied directly to the next insn. */
return true;
}
ctx->null_lab = NULL;
if (likely(ctx->null_cond.c == TCG_COND_NEVER)) {
/* The next instruction will be unconditional,
and NULL_COND already reflects that. */
gen_set_label(null_lab);
} else {
/* The insn that we just executed is itself nullifying the next
instruction. Store the condition in the PSW[N] global.
We asserted PSW[N] = 0 in nullify_over, so that after the
label we have the proper value in place. */
nullify_save(ctx);
gen_set_label(null_lab);
ctx->null_cond = cond_make_n();
}
if (status == DISAS_NORETURN) {
ctx->base.is_jmp = DISAS_NEXT;
}
return true;
}
static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
{
if (unlikely(ival == -1)) {
tcg_gen_mov_reg(dest, vval);
} else {
tcg_gen_movi_reg(dest, ival);
}
}
static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp)
{
return ctx->iaoq_f + disp + 8;
}
static void gen_excp_1(int exception)
{
TCGv_i32 t = tcg_const_i32(exception);
gen_helper_excp(cpu_env, t);
tcg_temp_free_i32(t);
}
static void gen_excp(DisasContext *ctx, int exception)
{
copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
gen_excp_1(exception);
ctx->base.is_jmp = DISAS_NORETURN;
}
static bool gen_excp_iir(DisasContext *ctx, int exc)
{
TCGv_reg tmp;
nullify_over(ctx);
tmp = tcg_const_reg(ctx->insn);
tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR]));
tcg_temp_free(tmp);
gen_excp(ctx, exc);
return nullify_end(ctx);
}
static bool gen_illegal(DisasContext *ctx)
{
return gen_excp_iir(ctx, EXCP_ILL);
}
#ifdef CONFIG_USER_ONLY
#define CHECK_MOST_PRIVILEGED(EXCP) \
return gen_excp_iir(ctx, EXCP)
#else
#define CHECK_MOST_PRIVILEGED(EXCP) \
do { \
if (ctx->privilege != 0) { \
return gen_excp_iir(ctx, EXCP); \
} \
} while (0)
#endif
static bool use_goto_tb(DisasContext *ctx, target_ureg dest)
{
/* Suppress goto_tb for page crossing, IO, or single-steping. */
return !(((ctx->base.pc_first ^ dest) & TARGET_PAGE_MASK)
|| (tb_cflags(ctx->base.tb) & CF_LAST_IO)
|| ctx->base.singlestep_enabled);
}
/* If the next insn is to be nullified, and it's on the same page,
and we're not attempting to set a breakpoint on it, then we can
totally skip the nullified insn. This avoids creating and
executing a TB that merely branches to the next TB. */
static bool use_nullify_skip(DisasContext *ctx)
{
return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0
&& !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY));
}
static void gen_goto_tb(DisasContext *ctx, int which,
target_ureg f, target_ureg b)
{
if (f != -1 && b != -1 && use_goto_tb(ctx, f)) {
tcg_gen_goto_tb(which);
tcg_gen_movi_reg(cpu_iaoq_f, f);
tcg_gen_movi_reg(cpu_iaoq_b, b);
tcg_gen_exit_tb(ctx->base.tb, which);
} else {
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
if (ctx->base.singlestep_enabled) {
gen_excp_1(EXCP_DEBUG);
} else {
tcg_gen_lookup_and_goto_ptr();
}
}
}
static bool cond_need_sv(int c)
{
return c == 2 || c == 3 || c == 6;
}
static bool cond_need_cb(int c)
{
return c == 4 || c == 5;
}
/*
* Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
* the Parisc 1.1 Architecture Reference Manual for details.
*/
static DisasCond do_cond(unsigned cf, TCGv_reg res,
TCGv_reg cb_msb, TCGv_reg sv)
{
DisasCond cond;
TCGv_reg tmp;
switch (cf >> 1) {
case 0: /* Never / TR (0 / 1) */
cond = cond_make_f();
break;
case 1: /* = / <> (Z / !Z) */
cond = cond_make_0(TCG_COND_EQ, res);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new();
tcg_gen_xor_reg(tmp, res, sv);
cond = cond_make_0_tmp(TCG_COND_LT, tmp);
break;
case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
/*
* Simplify:
* (N ^ V) | Z
* ((res < 0) ^ (sv < 0)) | !res
* ((res ^ sv) < 0) | !res
* (~(res ^ sv) >= 0) | !res
* !(~(res ^ sv) >> 31) | !res
* !(~(res ^ sv) >> 31 & res)
*/
tmp = tcg_temp_new();
tcg_gen_eqv_reg(tmp, res, sv);
tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
tcg_gen_and_reg(tmp, tmp, res);
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 4: /* NUV / UV (!C / C) */
cond = cond_make_0(TCG_COND_EQ, cb_msb);
break;
case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
tmp = tcg_temp_new();
tcg_gen_neg_reg(tmp, cb_msb);
tcg_gen_and_reg(tmp, tmp, res);
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 6: /* SV / NSV (V / !V) */
cond = cond_make_0(TCG_COND_LT, sv);
break;
case 7: /* OD / EV */
tmp = tcg_temp_new();
tcg_gen_andi_reg(tmp, res, 1);
cond = cond_make_0_tmp(TCG_COND_NE, tmp);
break;
default:
g_assert_not_reached();
}
if (cf & 1) {
cond.c = tcg_invert_cond(cond.c);
}
return cond;
}
/* Similar, but for the special case of subtraction without borrow, we
can use the inputs directly. This can allow other computation to be
deleted as unused. */
static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2, TCGv_reg sv)
{
DisasCond cond;
switch (cf >> 1) {
case 1: /* = / <> */
cond = cond_make(TCG_COND_EQ, in1, in2);
break;
case 2: /* < / >= */
cond = cond_make(TCG_COND_LT, in1, in2);
break;
case 3: /* <= / > */
cond = cond_make(TCG_COND_LE, in1, in2);
break;
case 4: /* << / >>= */
cond = cond_make(TCG_COND_LTU, in1, in2);
break;
case 5: /* <<= / >> */
cond = cond_make(TCG_COND_LEU, in1, in2);
break;
default:
return do_cond(cf, res, NULL, sv);
}
if (cf & 1) {
cond.c = tcg_invert_cond(cond.c);
}
return cond;
}
/*
* Similar, but for logicals, where the carry and overflow bits are not
* computed, and use of them is undefined.
*
* Undefined or not, hardware does not trap. It seems reasonable to
* assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
* how cases c={2,3} are treated.
*/
static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
{
switch (cf) {
case 0: /* never */
case 9: /* undef, C */
case 11: /* undef, C & !Z */
case 12: /* undef, V */
return cond_make_f();
case 1: /* true */
case 8: /* undef, !C */
case 10: /* undef, !C | Z */
case 13: /* undef, !V */
return cond_make_t();
case 2: /* == */
return cond_make_0(TCG_COND_EQ, res);
case 3: /* <> */
return cond_make_0(TCG_COND_NE, res);
case 4: /* < */
return cond_make_0(TCG_COND_LT, res);
case 5: /* >= */
return cond_make_0(TCG_COND_GE, res);
case 6: /* <= */
return cond_make_0(TCG_COND_LE, res);
case 7: /* > */
return cond_make_0(TCG_COND_GT, res);
case 14: /* OD */
case 15: /* EV */
return do_cond(cf, res, NULL, NULL);
default:
g_assert_not_reached();
}
}
/* Similar, but for shift/extract/deposit conditions. */
static DisasCond do_sed_cond(unsigned orig, TCGv_reg res)
{
unsigned c, f;
/* Convert the compressed condition codes to standard.
0-2 are the same as logicals (nv,<,<=), while 3 is OD.
4-7 are the reverse of 0-3. */
c = orig & 3;
if (c == 3) {
c = 7;
}
f = (orig & 4) / 4;
return do_log_cond(c * 2 + f, res);
}
/* Similar, but for unit conditions. */
static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
DisasCond cond;
TCGv_reg tmp, cb = NULL;
if (cf & 8) {
/* Since we want to test lots of carry-out bits all at once, do not
* do our normal thing and compute carry-in of bit B+1 since that
* leaves us with carry bits spread across two words.
*/
cb = tcg_temp_new();
tmp = tcg_temp_new();
tcg_gen_or_reg(cb, in1, in2);
tcg_gen_and_reg(tmp, in1, in2);
tcg_gen_andc_reg(cb, cb, res);
tcg_gen_or_reg(cb, cb, tmp);
tcg_temp_free(tmp);
}
switch (cf >> 1) {
case 0: /* never / TR */
case 1: /* undefined */
case 5: /* undefined */
cond = cond_make_f();
break;
case 2: /* SBZ / NBZ */
/* See hasless(v,1) from
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
*/
tmp = tcg_temp_new();
tcg_gen_subi_reg(tmp, res, 0x01010101u);
tcg_gen_andc_reg(tmp, tmp, res);
tcg_gen_andi_reg(tmp, tmp, 0x80808080u);
cond = cond_make_0(TCG_COND_NE, tmp);
tcg_temp_free(tmp);
break;
case 3: /* SHZ / NHZ */
tmp = tcg_temp_new();
tcg_gen_subi_reg(tmp, res, 0x00010001u);
tcg_gen_andc_reg(tmp, tmp, res);
tcg_gen_andi_reg(tmp, tmp, 0x80008000u);
cond = cond_make_0(TCG_COND_NE, tmp);
tcg_temp_free(tmp);
break;
case 4: /* SDC / NDC */
tcg_gen_andi_reg(cb, cb, 0x88888888u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 6: /* SBC / NBC */
tcg_gen_andi_reg(cb, cb, 0x80808080u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 7: /* SHC / NHC */
tcg_gen_andi_reg(cb, cb, 0x80008000u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
default:
g_assert_not_reached();
}
if (cf & 8) {
tcg_temp_free(cb);
}
if (cf & 1) {
cond.c = tcg_invert_cond(cond.c);
}
return cond;
}
/* Compute signed overflow for addition. */
static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
TCGv_reg sv = get_temp(ctx);
TCGv_reg tmp = tcg_temp_new();
tcg_gen_xor_reg(sv, res, in1);
tcg_gen_xor_reg(tmp, in1, in2);
tcg_gen_andc_reg(sv, sv, tmp);
tcg_temp_free(tmp);
return sv;
}
/* Compute signed overflow for subtraction. */
static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
TCGv_reg sv = get_temp(ctx);
TCGv_reg tmp = tcg_temp_new();
tcg_gen_xor_reg(sv, res, in1);
tcg_gen_xor_reg(tmp, in1, in2);
tcg_gen_and_reg(sv, sv, tmp);
tcg_temp_free(tmp);
return sv;
}
static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned shift, bool is_l,
bool is_tsv, bool is_tc, bool is_c, unsigned cf)
{
TCGv_reg dest, cb, cb_msb, sv, tmp;
unsigned c = cf >> 1;
DisasCond cond;
dest = tcg_temp_new();
cb = NULL;
cb_msb = NULL;
if (shift) {
tmp = get_temp(ctx);
tcg_gen_shli_reg(tmp, in1, shift);
in1 = tmp;
}
if (!is_l || cond_need_cb(c)) {
TCGv_reg zero = tcg_const_reg(0);
cb_msb = get_temp(ctx);
tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero);
if (is_c) {
tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero);
}
tcg_temp_free(zero);
if (!is_l) {
cb = get_temp(ctx);
tcg_gen_xor_reg(cb, in1, in2);
tcg_gen_xor_reg(cb, cb, dest);
}
} else {
tcg_gen_add_reg(dest, in1, in2);
if (is_c) {
tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb);
}
}
/* Compute signed overflow if required. */
sv = NULL;
if (is_tsv || cond_need_sv(c)) {
sv = do_add_sv(ctx, dest, in1, in2);
if (is_tsv) {
/* ??? Need to include overflow from shift. */
gen_helper_tsv(cpu_env, sv);
}
}
/* Emit any conditional trap before any writeback. */
cond = do_cond(cf, dest, cb_msb, sv);
if (is_tc) {
cond_prep(&cond);
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(cpu_env, tmp);
tcg_temp_free(tmp);
}
/* Write back the result. */
if (!is_l) {
save_or_nullify(ctx, cpu_psw_cb, cb);
save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb);
}
save_gpr(ctx, rt, dest);
tcg_temp_free(dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
ctx->null_cond = cond;
}
static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a,
bool is_l, bool is_tsv, bool is_tc, bool is_c)
{
TCGv_reg tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf);
return nullify_end(ctx);
}
static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
bool is_tsv, bool is_tc)
{
TCGv_reg tcg_im, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_im = load_const(ctx, a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf);
return nullify_end(ctx);
}
static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, bool is_tsv, bool is_b,
bool is_tc, unsigned cf)
{
TCGv_reg dest, sv, cb, cb_msb, zero, tmp;
unsigned c = cf >> 1;
DisasCond cond;
dest = tcg_temp_new();
cb = tcg_temp_new();
cb_msb = tcg_temp_new();
zero = tcg_const_reg(0);
if (is_b) {
/* DEST,C = IN1 + ~IN2 + C. */
tcg_gen_not_reg(cb, in2);
tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero);
tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero);
tcg_gen_xor_reg(cb, cb, in1);
tcg_gen_xor_reg(cb, cb, dest);
} else {
/* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
operations by seeding the high word with 1 and subtracting. */
tcg_gen_movi_reg(cb_msb, 1);
tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero);
tcg_gen_eqv_reg(cb, in1, in2);
tcg_gen_xor_reg(cb, cb, dest);
}
tcg_temp_free(zero);
/* Compute signed overflow if required. */
sv = NULL;
if (is_tsv || cond_need_sv(c)) {
sv = do_sub_sv(ctx, dest, in1, in2);
if (is_tsv) {
gen_helper_tsv(cpu_env, sv);
}
}
/* Compute the condition. We cannot use the special case for borrow. */
if (!is_b) {
cond = do_sub_cond(cf, dest, in1, in2, sv);
} else {
cond = do_cond(cf, dest, cb_msb, sv);
}
/* Emit any conditional trap before any writeback. */
if (is_tc) {
cond_prep(&cond);
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(cpu_env, tmp);
tcg_temp_free(tmp);
}
/* Write back the result. */
save_or_nullify(ctx, cpu_psw_cb, cb);
save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb);
save_gpr(ctx, rt, dest);
tcg_temp_free(dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
ctx->null_cond = cond;
}
static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a,
bool is_tsv, bool is_b, bool is_tc)
{
TCGv_reg tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf);
return nullify_end(ctx);
}
static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
{
TCGv_reg tcg_im, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_im = load_const(ctx, a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf);
return nullify_end(ctx);
}
static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned cf)
{
TCGv_reg dest, sv;
DisasCond cond;
dest = tcg_temp_new();
tcg_gen_sub_reg(dest, in1, in2);
/* Compute signed overflow if required. */
sv = NULL;
if (cond_need_sv(cf >> 1)) {
sv = do_sub_sv(ctx, dest, in1, in2);
}
/* Form the condition for the compare. */
cond = do_sub_cond(cf, dest, in1, in2, sv);
/* Clear. */
tcg_gen_movi_reg(dest, 0);
save_gpr(ctx, rt, dest);
tcg_temp_free(dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
ctx->null_cond = cond;
}
static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned cf,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg dest = dest_gpr(ctx, rt);
/* Perform the operation, and writeback. */
fn(dest, in1, in2);
save_gpr(ctx, rt, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (cf) {
ctx->null_cond = do_log_cond(cf, dest);
}
}
static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn);
return nullify_end(ctx);
}
static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned cf, bool is_tc,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg dest;
DisasCond cond;
if (cf == 0) {
dest = dest_gpr(ctx, rt);
fn(dest, in1, in2);
save_gpr(ctx, rt, dest);
cond_free(&ctx->null_cond);
} else {
dest = tcg_temp_new();
fn(dest, in1, in2);
cond = do_unit_cond(cf, dest, in1, in2);
if (is_tc) {
TCGv_reg tmp = tcg_temp_new();
cond_prep(&cond);
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(cpu_env, tmp);
tcg_temp_free(tmp);
}
save_gpr(ctx, rt, dest);
cond_free(&ctx->null_cond);
ctx->null_cond = cond;
}
}
#ifndef CONFIG_USER_ONLY
/* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
from the top 2 bits of the base register. There are a few system
instructions that have a 3-bit space specifier, for which SR0 is
not special. To handle this, pass ~SP. */
static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
{
TCGv_ptr ptr;
TCGv_reg tmp;
TCGv_i64 spc;
if (sp != 0) {
if (sp < 0) {
sp = ~sp;
}
spc = get_temp_tl(ctx);
load_spr(ctx, spc, sp);
return spc;
}
if (ctx->tb_flags & TB_FLAG_SR_SAME) {
return cpu_srH;
}
ptr = tcg_temp_new_ptr();
tmp = tcg_temp_new();
spc = get_temp_tl(ctx);
tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
tcg_gen_andi_reg(tmp, tmp, 030);
tcg_gen_trunc_reg_ptr(ptr, tmp);
tcg_temp_free(tmp);
tcg_gen_add_ptr(ptr, ptr, cpu_env);
tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4]));
tcg_temp_free_ptr(ptr);
return spc;
}
#endif
static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
unsigned rb, unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify, bool is_phys)
{
TCGv_reg base = load_gpr(ctx, rb);
TCGv_reg ofs;
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
ofs = get_temp(ctx);
tcg_gen_shli_reg(ofs, cpu_gr[rx], scale);
tcg_gen_add_reg(ofs, ofs, base);
} else if (disp || modify) {
ofs = get_temp(ctx);
tcg_gen_addi_reg(ofs, base, disp);
} else {
ofs = base;
}
*pofs = ofs;
#ifdef CONFIG_USER_ONLY
*pgva = (modify <= 0 ? ofs : base);
#else
TCGv_tl addr = get_temp_tl(ctx);
tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
if (ctx->tb_flags & PSW_W) {
tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull);
}
if (!is_phys) {
tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
}
*pgva = addr;
#endif
}
/* Emit a memory load. The modify parameter should be
* < 0 for pre-modify,
* > 0 for post-modify,
* = 0 for no base register update.
*/
static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify, TCGMemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
if (modify) {
save_gpr(ctx, rb, ofs);
}
}
static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify, TCGMemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
if (modify) {
save_gpr(ctx, rb, ofs);
}
}
static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify, TCGMemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
if (modify) {
save_gpr(ctx, rb, ofs);
}
}
static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify, TCGMemOp mop)
{
TCGv_reg ofs;
TCGv_tl addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop);
if (modify) {
save_gpr(ctx, rb, ofs);
}
}
#if TARGET_REGISTER_BITS == 64
#define do_load_reg do_load_64
#define do_store_reg do_store_64
#else
#define do_load_reg do_load_32
#define do_store_reg do_store_32
#endif
static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify, TCGMemOp mop)
{
TCGv_reg dest;
nullify_over(ctx);
if (modify == 0) {
/* No base register update. */
dest = dest_gpr(ctx, rt);
} else {
/* Make sure if RT == RB, we see the result of the load. */
dest = get_temp(ctx);
}
do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
save_gpr(ctx, rt, dest);
return nullify_end(ctx);
}
static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify)
{
TCGv_i32 tmp;
nullify_over(ctx);
tmp = tcg_temp_new_i32();
do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
save_frw_i32(rt, tmp);
tcg_temp_free_i32(tmp);
if (rt == 0) {
gen_helper_loaded_fr0(cpu_env);
}
return nullify_end(ctx);
}
static bool trans_fldw(DisasContext *ctx, arg_ldst *a)
{
return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0,
a->disp, a->sp, a->m);
}
static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify)
{
TCGv_i64 tmp;
nullify_over(ctx);
tmp = tcg_temp_new_i64();
do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ);
save_frd(rt, tmp);
tcg_temp_free_i64(tmp);
if (rt == 0) {
gen_helper_loaded_fr0(cpu_env);
}
return nullify_end(ctx);
}
static bool trans_fldd(DisasContext *ctx, arg_ldst *a)
{
return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0,
a->disp, a->sp, a->m);
}
static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
target_sreg disp, unsigned sp,
int modify, TCGMemOp mop)
{
nullify_over(ctx);
do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
return nullify_end(ctx);
}
static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify)
{
TCGv_i32 tmp;
nullify_over(ctx);
tmp = load_frw_i32(rt);
do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
tcg_temp_free_i32(tmp);
return nullify_end(ctx);
}
static bool trans_fstw(DisasContext *ctx, arg_ldst *a)
{
return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0,
a->disp, a->sp, a->m);
}
static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, target_sreg disp,
unsigned sp, int modify)
{
TCGv_i64 tmp;
nullify_over(ctx);
tmp = load_frd(rt);
do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ);
tcg_temp_free_i64(tmp);
return nullify_end(ctx);
}
static bool trans_fstd(DisasContext *ctx, arg_ldst *a)
{
return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0,
a->disp, a->sp, a->m);
}
static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra,
void (*func)(TCGv_i32, TCGv_env, TCGv_i32))
{
TCGv_i32 tmp;
nullify_over(ctx);
tmp = load_frw0_i32(ra);
func(tmp, cpu_env, tmp);
save_frw_i32(rt, tmp);
tcg_temp_free_i32(tmp);
return nullify_end(ctx);
}
static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra,
void (*func)(TCGv_i32, TCGv_env, TCGv_i64))
{
TCGv_i32 dst;
TCGv_i64 src;
nullify_over(ctx);
src = load_frd(ra);
dst = tcg_temp_new_i32();
func(dst, cpu_env, src);
tcg_temp_free_i64(src);
save_frw_i32(rt, dst);
tcg_temp_free_i32(dst);
return nullify_end(ctx);
}
static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra,
void (*func)(TCGv_i64, TCGv_env, TCGv_i64))
{
TCGv_i64 tmp;
nullify_over(ctx);
tmp = load_frd0(ra);
func(tmp, cpu_env, tmp);
save_frd(rt, tmp);
tcg_temp_free_i64(tmp);
return nullify_end(ctx);
}
static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra,
void (*func)(TCGv_i64, TCGv_env, TCGv_i32))
{
TCGv_i32 src;
TCGv_i64 dst;
nullify_over(ctx);
src = load_frw0_i32(ra);
dst = tcg_temp_new_i64();
func(dst, cpu_env, src);
tcg_temp_free_i32(src);
save_frd(rt, dst);
tcg_temp_free_i64(dst);
return nullify_end(ctx);
}
static bool do_fop_weww(DisasContext *ctx, unsigned rt,
unsigned ra, unsigned rb,
void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
{
TCGv_i32 a, b;
nullify_over(ctx);
a = load_frw0_i32(ra);
b = load_frw0_i32(rb);
func(a, cpu_env, a, b);
tcg_temp_free_i32(b);
save_frw_i32(rt, a);
tcg_temp_free_i32(a);
return nullify_end(ctx);
}
static bool do_fop_dedd(DisasContext *ctx, unsigned rt,
unsigned ra, unsigned rb,
void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
{
TCGv_i64 a, b;
nullify_over(ctx);
a = load_frd0(ra);
b = load_frd0(rb);
func(a, cpu_env, a, b);
tcg_temp_free_i64(b);
save_frd(rt, a);
tcg_temp_free_i64(a);
return nullify_end(ctx);
}
/* Emit an unconditional branch to a direct target, which may or may not
have already had nullification handled. */
static bool do_dbranch(DisasContext *ctx, target_ureg dest,
unsigned link, bool is_n)
{
if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) {
if (link != 0) {
copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
ctx->iaoq_n = dest;
if (is_n) {
ctx->null_cond.c = TCG_COND_ALWAYS;
}
} else {
nullify_over(ctx);
if (link != 0) {
copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
if (is_n && use_nullify_skip(ctx)) {
nullify_set(ctx, 0);
gen_goto_tb(ctx, 0, dest, dest + 4);
} else {
nullify_set(ctx, is_n);
gen_goto_tb(ctx, 0, ctx->iaoq_b, dest);
}
nullify_end(ctx);
nullify_set(ctx, 0);
gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n);
ctx->base.is_jmp = DISAS_NORETURN;
}
return true;
}
/* Emit a conditional branch to a direct target. If the branch itself
is nullified, we should have already used nullify_over. */
static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n,
DisasCond *cond)
{
target_ureg dest = iaoq_dest(ctx, disp);
TCGLabel *taken = NULL;
TCGCond c = cond->c;
bool n;
assert(ctx->null_cond.c == TCG_COND_NEVER);
/* Handle TRUE and NEVER as direct branches. */
if (c == TCG_COND_ALWAYS) {
return do_dbranch(ctx, dest, 0, is_n && disp >= 0);
}
if (c == TCG_COND_NEVER) {
return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0);
}
taken = gen_new_label();
cond_prep(cond);
tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken);
cond_free(cond);
/* Not taken: Condition not satisfied; nullify on backward branches. */
n = is_n && disp < 0;
if (n && use_nullify_skip(ctx)) {
nullify_set(ctx, 0);
gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4);
} else {
if (!n && ctx->null_lab) {
gen_set_label(ctx->null_lab);
ctx->null_lab = NULL;
}
nullify_set(ctx, n);
if (ctx->iaoq_n == -1) {
/* The temporary iaoq_n_var died at the branch above.
Regenerate it here instead of saving it. */
tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4);
}
gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n);
}
gen_set_label(taken);
/* Taken: Condition satisfied; nullify on forward branches. */
n = is_n && disp >= 0;
if (n && use_nullify_skip(ctx)) {
nullify_set(ctx, 0);
gen_goto_tb(ctx, 1, dest, dest + 4);
} else {
nullify_set(ctx, n);
gen_goto_tb(ctx, 1, ctx->iaoq_b, dest);
}
/* Not taken: the branch itself was nullified. */
if (ctx->null_lab) {
gen_set_label(ctx->null_lab);
ctx->null_lab = NULL;
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
} else {
ctx->base.is_jmp = DISAS_NORETURN;
}
return true;
}
/* Emit an unconditional branch to an indirect target. This handles
nullification of the branch itself. */
static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
unsigned link, bool is_n)
{
TCGv_reg a0, a1, next, tmp;
TCGCond c;
assert(ctx->null_lab == NULL);
if (ctx->null_cond.c == TCG_COND_NEVER) {
if (link != 0) {
copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
next = get_temp(ctx);
tcg_gen_mov_reg(next, dest);
if (is_n) {
if (use_nullify_skip(ctx)) {
tcg_gen_mov_reg(cpu_iaoq_f, next);
tcg_gen_addi_reg(cpu_iaoq_b, next, 4);
nullify_set(ctx, 0);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
return true;
}
ctx->null_cond.c = TCG_COND_ALWAYS;
}
ctx->iaoq_n = -1;
ctx->iaoq_n_var = next;
} else if (is_n && use_nullify_skip(ctx)) {
/* The (conditional) branch, B, nullifies the next insn, N,
and we're allowed to skip execution N (no single-step or
tracepoint in effect). Since the goto_ptr that we must use
for the indirect branch consumes no special resources, we
can (conditionally) skip B and continue execution. */
/* The use_nullify_skip test implies we have a known control path. */
tcg_debug_assert(ctx->iaoq_b != -1);
tcg_debug_assert(ctx->iaoq_n != -1);
/* We do have to handle the non-local temporary, DEST, before
branching. Since IOAQ_F is not really live at this point, we
can simply store DEST optimistically. Similarly with IAOQ_B. */
tcg_gen_mov_reg(cpu_iaoq_f, dest);
tcg_gen_addi_reg(cpu_iaoq_b, dest, 4);
nullify_over(ctx);
if (link != 0) {
tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n);
}
tcg_gen_lookup_and_goto_ptr();
return nullify_end(ctx);
} else {
cond_prep(&ctx->null_cond);
c = ctx->null_cond.c;
a0 = ctx->null_cond.a0;
a1 = ctx->null_cond.a1;
tmp = tcg_temp_new();
next = get_temp(ctx);
copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest);
ctx->iaoq_n = -1;
ctx->iaoq_n_var = next;
if (link != 0) {
tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp);
}
if (is_n) {
/* The branch nullifies the next insn, which means the state of N
after the branch is the inverse of the state of N that applied
to the branch. */
tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1);
cond_free(&ctx->null_cond);
ctx->null_cond = cond_make_n();
ctx->psw_n_nonzero = true;
} else {
cond_free(&ctx->null_cond);
}
}
return true;
}
/* Implement
* if (IAOQ_Front{30..31} < GR[b]{30..31})
* IAOQ_Next{30..31} ← GR[b]{30..31};
* else
* IAOQ_Next{30..31} ← IAOQ_Front{30..31};
* which keeps the privilege level from being increased.
*/
static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset)
{
TCGv_reg dest;
switch (ctx->privilege) {
case 0:
/* Privilege 0 is maximum and is allowed to decrease. */
return offset;
case 3:
/* Privilege 3 is minimum and is never allowed to increase. */
dest = get_temp(ctx);
tcg_gen_ori_reg(dest, offset, 3);
break;
default:
dest = get_temp(ctx);
tcg_gen_andi_reg(dest, offset, -4);
tcg_gen_ori_reg(dest, dest, ctx->privilege);
tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset);
break;
}
return dest;
}
#ifdef CONFIG_USER_ONLY
/* On Linux, page zero is normally marked execute only + gateway.
Therefore normal read or write is supposed to fail, but specific
offsets have kernel code mapped to raise permissions to implement
system calls. Handling this via an explicit check here, rather
in than the "be disp(sr2,r0)" instruction that probably sent us
here, is the easiest way to handle the branch delay slot on the
aforementioned BE. */
static void do_page_zero(DisasContext *ctx)
{
/* If by some means we get here with PSW[N]=1, that implies that
the B,GATE instruction would be skipped, and we'd fault on the
next insn within the privilaged page. */
switch (ctx->null_cond.c) {
case TCG_COND_NEVER:
break;
case TCG_COND_ALWAYS:
tcg_gen_movi_reg(cpu_psw_n, 0);
goto do_sigill;
default:
/* Since this is always the first (and only) insn within the
TB, we should know the state of PSW[N] from TB->FLAGS. */
g_assert_not_reached();
}
/* Check that we didn't arrive here via some means that allowed
non-sequential instruction execution. Normally the PSW[B] bit
detects this by disallowing the B,GATE instruction to execute
under such conditions. */
if (ctx->iaoq_b != ctx->iaoq_f + 4) {
goto do_sigill;
}
switch (ctx->iaoq_f & -4) {
case 0x00: /* Null pointer call */
gen_excp_1(EXCP_IMP);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0xb0: /* LWS */
gen_excp_1(EXCP_SYSCALL_LWS);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0xe0: /* SET_THREAD_POINTER */
tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27]));
tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3);
tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
break;
case 0x100: /* SYSCALL */
gen_excp_1(EXCP_SYSCALL);
ctx->base.is_jmp = DISAS_NORETURN;
break;
default:
do_sigill:
gen_excp_1(EXCP_ILL);
ctx->base.is_jmp = DISAS_NORETURN;
break;
}
}
#endif
static bool trans_nop(DisasContext *ctx, arg_nop *a)
{
cond_free(&ctx->null_cond);
return true;
}
static bool trans_break(DisasContext *ctx, arg_break *a)
{
return gen_excp_iir(ctx, EXCP_BREAK);
}
static bool trans_sync(DisasContext *ctx, arg_sync *a)
{
/* No point in nullifying the memory barrier. */
tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_mfia(DisasContext *ctx, arg_mfia *a)
{
unsigned rt = a->t;
TCGv_reg tmp = dest_gpr(ctx, rt);
tcg_gen_movi_reg(tmp, ctx->iaoq_f);
save_gpr(ctx, rt, tmp);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a)
{
unsigned rt = a->t;
unsigned rs = a->sp;
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_reg t1 = tcg_temp_new();
load_spr(ctx, t0, rs);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_trunc_i64_reg(t1, t0);
save_gpr(ctx, rt, t1);
tcg_temp_free(t1);
tcg_temp_free_i64(t0);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
{
unsigned rt = a->t;
unsigned ctl = a->r;
TCGv_reg tmp;
switch (ctl) {
case CR_SAR:
#ifdef TARGET_HPPA64
if (a->e == 0) {
/* MFSAR without ,W masks low 5 bits. */
tmp = dest_gpr(ctx, rt);
tcg_gen_andi_reg(tmp, cpu_sar, 31);
save_gpr(ctx, rt, tmp);
goto done;
}
#endif
save_gpr(ctx, rt, cpu_sar);
goto done;
case CR_IT: /* Interval Timer */
/* FIXME: Respect PSW_S bit. */
nullify_over(ctx);
tmp = dest_gpr(ctx, rt);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
gen_helper_read_interval_timer(tmp);
gen_io_end();
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
} else {
gen_helper_read_interval_timer(tmp);
}
save_gpr(ctx, rt, tmp);
return nullify_end(ctx);
case 26:
case 27:
break;
default:
/* All other control registers are privileged. */
CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG);
break;
}
tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
save_gpr(ctx, rt, tmp);
done:
cond_free(&ctx->null_cond);
return true;
}
static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a)
{
unsigned rr = a->r;
unsigned rs = a->sp;
TCGv_i64 t64;
if (rs >= 5) {
CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG);
}
nullify_over(ctx);
t64 = tcg_temp_new_i64();
tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr));
tcg_gen_shli_i64(t64, t64, 32);
if (rs >= 4) {
tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs]));
ctx->tb_flags &= ~TB_FLAG_SR_SAME;
} else {
tcg_gen_mov_i64(cpu_sr[rs], t64);
}
tcg_temp_free_i64(t64);
return nullify_end(ctx);
}
static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
{
unsigned ctl = a->t;
TCGv_reg reg = load_gpr(ctx, a->r);
TCGv_reg tmp;
if (ctl == CR_SAR) {
tmp = tcg_temp_new();
tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1);
save_or_nullify(ctx, cpu_sar, tmp);
tcg_temp_free(tmp);
cond_free(&ctx->null_cond);
return true;
}
/* All other control registers are privileged or read-only. */
CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
switch (ctl) {
case CR_IT:
gen_helper_write_interval_timer(cpu_env, reg);
break;
case CR_EIRR:
gen_helper_write_eirr(cpu_env, reg);
break;
case CR_EIEM:
gen_helper_write_eiem(cpu_env, reg);
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
break;
case CR_IIASQ:
case CR_IIAOQ:
/* FIXME: Respect PSW_Q bit */
/* The write advances the queue and stores to the back element. */
tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
tcg_gen_st_reg(reg, cpu_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
break;
case CR_PID1:
case CR_PID2:
case CR_PID3:
case CR_PID4:
tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
#ifndef CONFIG_USER_ONLY
gen_helper_change_prot_id(cpu_env);
#endif
break;
default:
tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
break;
}
return nullify_end(ctx);
#endif
}
static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
{
TCGv_reg tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, load_gpr(ctx, a->r));
tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
save_or_nullify(ctx, cpu_sar, tmp);
tcg_temp_free(tmp);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a)
{
TCGv_reg dest = dest_gpr(ctx, a->t);
#ifdef CONFIG_USER_ONLY
/* We don't implement space registers in user mode. */
tcg_gen_movi_reg(dest, 0);
#else
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b)));
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_trunc_i64_reg(dest, t0);
tcg_temp_free_i64(t0);
#endif
save_gpr(ctx, a->t, dest);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_reg tmp;
nullify_over(ctx);
tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw));
tcg_gen_andi_reg(tmp, tmp, ~a->i);
gen_helper_swap_system_mask(tmp, cpu_env, tmp);
save_gpr(ctx, a->t, tmp);
/* Exit the TB to recognize new interrupts, e.g. PSW_M. */
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
return nullify_end(ctx);
#endif
}
static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_reg tmp;
nullify_over(ctx);
tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw));
tcg_gen_ori_reg(tmp, tmp, a->i);
gen_helper_swap_system_mask(tmp, cpu_env, tmp);
save_gpr(ctx, a->t, tmp);
/* Exit the TB to recognize new interrupts, e.g. PSW_I. */
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
return nullify_end(ctx);
#endif
}
static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_reg tmp, reg;
nullify_over(ctx);
reg = load_gpr(ctx, a->r);
tmp = get_temp(ctx);
gen_helper_swap_system_mask(tmp, cpu_env, reg);
/* Exit the TB to recognize new interrupts. */
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
return nullify_end(ctx);
#endif
}
static bool do_rfi(DisasContext *ctx, bool rfi_r)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
if (rfi_r) {
gen_helper_rfi_r(cpu_env);
} else {
gen_helper_rfi(cpu_env);
}
/* Exit the TB to recognize new interrupts. */
if (ctx->base.singlestep_enabled) {
gen_excp_1(EXCP_DEBUG);
} else {
tcg_gen_exit_tb(NULL, 0);
}
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
}
static bool trans_rfi(DisasContext *ctx, arg_rfi *a)
{
return do_rfi(ctx, false);
}
static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a)
{
return do_rfi(ctx, true);
}
static bool trans_halt(DisasContext *ctx, arg_halt *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
gen_helper_halt(cpu_env);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
}
static bool trans_reset(DisasContext *ctx, arg_reset *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
gen_helper_reset(cpu_env);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
}
static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a)
{
if (a->m) {
TCGv_reg dest = dest_gpr(ctx, a->b);
TCGv_reg src1 = load_gpr(ctx, a->b);
TCGv_reg src2 = load_gpr(ctx, a->x);
/* The only thing we need to do is the base register modification. */
tcg_gen_add_reg(dest, src1, src2);
save_gpr(ctx, a->b, dest);
}
cond_free(&ctx->null_cond);
return true;
}
static bool trans_probe(DisasContext *ctx, arg_probe *a)
{
TCGv_reg dest, ofs;
TCGv_i32 level, want;
TCGv_tl addr;
nullify_over(ctx);
dest = dest_gpr(ctx, a->t);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
if (a->imm) {
level = tcg_const_i32(a->ri);
} else {
level = tcg_temp_new_i32();
tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri));
tcg_gen_andi_i32(level, level, 3);
}
want = tcg_const_i32(a->write ? PAGE_WRITE : PAGE_READ);
gen_helper_probe(dest, cpu_env, addr, level, want);
tcg_temp_free_i32(want);
tcg_temp_free_i32(level);
save_gpr(ctx, a->t, dest);
return nullify_end(ctx);
}
static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_tl addr;
TCGv_reg ofs, reg;
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
reg = load_gpr(ctx, a->r);
if (a->addr) {
gen_helper_itlba(cpu_env, addr, reg);
} else {
gen_helper_itlbp(cpu_env, addr, reg);
}
/* Exit TB for TLB change if mmu is enabled. */
if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
#endif
}
static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_tl addr;
TCGv_reg ofs;
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
if (a->m) {
save_gpr(ctx, a->b, ofs);
}
if (a->local) {
gen_helper_ptlbe(cpu_env);
} else {
gen_helper_ptlb(cpu_env, addr);
}
/* Exit TB for TLB change if mmu is enabled. */
if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
#endif
}
static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_tl vaddr;
TCGv_reg ofs, paddr;
nullify_over(ctx);
form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
paddr = tcg_temp_new();
gen_helper_lpa(paddr, cpu_env, vaddr);
/* Note that physical address result overrides base modification. */
if (a->m) {
save_gpr(ctx, a->b, ofs);
}
save_gpr(ctx, a->t, paddr);
tcg_temp_free(paddr);
return nullify_end(ctx);
#endif
}
static bool trans_lci(DisasContext *ctx, arg_lci *a)
{
TCGv_reg ci;
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
/* The Coherence Index is an implementation-defined function of the
physical address. Two addresses with the same CI have a coherent
view of the cache. Our implementation is to return 0 for all,
since the entire address space is coherent. */
ci = tcg_const_reg(0);
save_gpr(ctx, a->t, ci);
tcg_temp_free(ci);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a)
{
return do_add_reg(ctx, a, false, false, false, false);
}
static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a)
{
return do_add_reg(ctx, a, true, false, false, false);
}
static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a)
{
return do_add_reg(ctx, a, false, true, false, false);
}
static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a)
{
return do_add_reg(ctx, a, false, false, false, true);
}
static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a)
{
return do_add_reg(ctx, a, false, true, false, true);
}
static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a)
{
return do_sub_reg(ctx, a, false, false, false);
}
static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a)
{
return do_sub_reg(ctx, a, true, false, false);
}
static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a)
{
return do_sub_reg(ctx, a, false, false, true);
}
static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a)
{
return do_sub_reg(ctx, a, true, false, true);
}
static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a)
{
return do_sub_reg(ctx, a, false, true, false);
}
static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a)
{
return do_sub_reg(ctx, a, true, true, false);
}
static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a)
{
return do_log_reg(ctx, a, tcg_gen_andc_reg);
}
static bool trans_and(DisasContext *ctx, arg_rrr_cf *a)
{
return do_log_reg(ctx, a, tcg_gen_and_reg);
}
static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
{
if (a->cf == 0) {
unsigned r2 = a->r2;
unsigned r1 = a->r1;
unsigned rt = a->t;
if (rt == 0) { /* NOP */
cond_free(&ctx->null_cond);
return true;
}
if (r2 == 0) { /* COPY */
if (r1 == 0) {
TCGv_reg dest = dest_gpr(ctx, rt);
tcg_gen_movi_reg(dest, 0);
save_gpr(ctx, rt, dest);
} else {
save_gpr(ctx, rt, cpu_gr[r1]);
}
cond_free(&ctx->null_cond);
return true;
}
#ifndef CONFIG_USER_ONLY
/* These are QEMU extensions and are nops in the real architecture:
*
* or %r10,%r10,%r10 -- idle loop; wait for interrupt
* or %r31,%r31,%r31 -- death loop; offline cpu
* currently implemented as idle.
*/
if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */
TCGv_i32 tmp;
/* No need to check for supervisor, as userland can only pause
until the next timer interrupt. */
nullify_over(ctx);
/* Advance the instruction queue. */
copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */
tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) +
offsetof(CPUState, halted));
tcg_temp_free_i32(tmp);
gen_excp_1(EXCP_HALTED);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
}
#endif
}
return do_log_reg(ctx, a, tcg_gen_or_reg);
}
static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a)
{
return do_log_reg(ctx, a, tcg_gen_xor_reg);
}
static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
{
TCGv_reg tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf);
return nullify_end(ctx);
}
static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a)
{
TCGv_reg tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg);
return nullify_end(ctx);
}
static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc)
{
TCGv_reg tcg_r1, tcg_r2, tmp;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
tmp = get_temp(ctx);
tcg_gen_not_reg(tmp, tcg_r2);
do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg);
return nullify_end(ctx);
}
static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a)
{
return do_uaddcm(ctx, a, false);
}
static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a)
{
return do_uaddcm(ctx, a, true);
}
static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i)
{
TCGv_reg tmp;
nullify_over(ctx);
tmp = get_temp(ctx);
tcg_gen_shri_reg(tmp, cpu_psw_cb, 3);
if (!is_i) {
tcg_gen_not_reg(tmp, tmp);
}
tcg_gen_andi_reg(tmp, tmp, 0x11111111);
tcg_gen_muli_reg(tmp, tmp, 6);
do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false,
is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
return nullify_end(ctx);
}
static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a)
{
return do_dcor(ctx, a, false);
}
static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a)
{
return do_dcor(ctx, a, true);
}
static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
{
TCGv_reg dest, add1, add2, addc, zero, in1, in2;
nullify_over(ctx);
in1 = load_gpr(ctx, a->r1);
in2 = load_gpr(ctx, a->r2);
add1 = tcg_temp_new();
add2 = tcg_temp_new();
addc = tcg_temp_new();
dest = tcg_temp_new();
zero = tcg_const_reg(0);
/* Form R1 << 1 | PSW[CB]{8}. */
tcg_gen_add_reg(add1, in1, in1);
tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb);
/* Add or subtract R2, depending on PSW[V]. Proper computation of
carry{8} requires that we subtract via + ~R2 + 1, as described in
the manual. By extracting and masking V, we can produce the
proper inputs to the addition without movcond. */
tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1);
tcg_gen_xor_reg(add2, in2, addc);
tcg_gen_andi_reg(addc, addc, 1);
/* ??? This is only correct for 32-bit. */
tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
tcg_temp_free(addc);
tcg_temp_free(zero);
/* Write back the result register. */
save_gpr(ctx, a->t, dest);
/* Write back PSW[CB]. */
tcg_gen_xor_reg(cpu_psw_cb, add1, add2);
tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest);
/* Write back PSW[V] for the division step. */
tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb);
tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2);
/* Install the new nullification. */
if (a->cf) {
TCGv_reg sv = NULL;
if (cond_need_sv(a->cf >> 1)) {
/* ??? The lshift is supposed to contribute to overflow. */
sv = do_add_sv(ctx, dest, add1, add2);
}
ctx->null_cond = do_cond(a->cf, dest, cpu_psw_cb_msb, sv);
}
tcg_temp_free(add1);
tcg_temp_free(add2);
tcg_temp_free(dest);
return nullify_end(ctx);
}
static bool trans_addi(DisasContext *ctx, arg_rri_cf *a)
{
return do_add_imm(ctx, a, false, false);
}
static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a)
{
return do_add_imm(ctx, a, true, false);
}
static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a)
{
return do_add_imm(ctx, a, false, true);
}
static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a)
{
return do_add_imm(ctx, a, true, true);
}
static bool trans_subi(DisasContext *ctx, arg_rri_cf *a)
{
return do_sub_imm(ctx, a, false);
}
static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a)
{
return do_sub_imm(ctx, a, true);
}
static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
{
TCGv_reg tcg_im, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_im = load_const(ctx, a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf);
return nullify_end(ctx);
}
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, a->size | MO_TE);
}
static bool trans_st(DisasContext *ctx, arg_ldst *a)
{
assert(a->x == 0 && a->scale == 0);
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{
TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;
TCGv_reg zero, dest, ofs;
TCGv_tl addr;
nullify_over(ctx);
if (a->m) {
/* Base register modification. Make sure if RT == RB,
we see the result of the load. */
dest = get_temp(ctx);
} else {
dest = dest_gpr(ctx, a->t);
}
form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX);
zero = tcg_const_reg(0);
tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop);
if (a->m) {
save_gpr(ctx, a->b, ofs);
}
save_gpr(ctx, a->t, dest);
return nullify_end(ctx);
}
static bool trans_stby(DisasContext *ctx, arg_stby *a)
{
TCGv_reg ofs, val;
TCGv_tl addr;
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m,
ctx->mmu_idx == MMU_PHYS_IDX);
val = load_gpr(ctx, a->r);
if (a->a) {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
gen_helper_stby_e_parallel(cpu_env, addr, val);
} else {
gen_helper_stby_e(cpu_env, addr, val);
}
} else {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
gen_helper_stby_b_parallel(cpu_env, addr, val);
} else {
gen_helper_stby_b(cpu_env, addr, val);
}
}
if (a->m) {
tcg_gen_andi_reg(ofs, ofs, ~3);
save_gpr(ctx, a->b, ofs);
}
return nullify_end(ctx);
}
static bool trans_lda(DisasContext *ctx, arg_ldst *a)
{
int hold_mmu_idx = ctx->mmu_idx;
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
ctx->mmu_idx = MMU_PHYS_IDX;
trans_ld(ctx, a);
ctx->mmu_idx = hold_mmu_idx;
return true;
}
static bool trans_sta(DisasContext *ctx, arg_ldst *a)
{
int hold_mmu_idx = ctx->mmu_idx;
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
ctx->mmu_idx = MMU_PHYS_IDX;
trans_st(ctx, a);
ctx->mmu_idx = hold_mmu_idx;
return true;
}
static bool trans_ldil(DisasContext *ctx, arg_ldil *a)
{
TCGv_reg tcg_rt = dest_gpr(ctx, a->t);
tcg_gen_movi_reg(tcg_rt, a->i);
save_gpr(ctx, a->t, tcg_rt);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_addil(DisasContext *ctx, arg_addil *a)
{
TCGv_reg tcg_rt = load_gpr(ctx, a->r);
TCGv_reg tcg_r1 = dest_gpr(ctx, 1);
tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i);
save_gpr(ctx, 1, tcg_r1);
cond_free(&ctx->null_cond);
return true;
}
static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
{
TCGv_reg tcg_rt = dest_gpr(ctx, a->t);
/* Special case rb == 0, for the LDI pseudo-op.
The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
if (a->b == 0) {
tcg_gen_movi_reg(tcg_rt, a->i);
} else {
tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i);
}
save_gpr(ctx, a->t, tcg_rt);
cond_free(&ctx->null_cond);
return true;
}
static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
unsigned c, unsigned f, unsigned n, int disp)
{
TCGv_reg dest, in2, sv;
DisasCond cond;
in2 = load_gpr(ctx, r);
dest = get_temp(ctx);
tcg_gen_sub_reg(dest, in1, in2);
sv = NULL;
if (cond_need_sv(c)) {
sv = do_sub_sv(ctx, dest, in1, in2);
}
cond = do_sub_cond(c * 2 + f, dest, in1, in2, sv);
return do_cbranch(ctx, disp, n, &cond);
}
static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a)
{
nullify_over(ctx);
return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp);
}
static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a)
{
nullify_over(ctx);
return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp);
}
static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
unsigned c, unsigned f, unsigned n, int disp)
{
TCGv_reg dest, in2, sv, cb_msb;
DisasCond cond;
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
sv = NULL;
cb_msb = NULL;
if (cond_need_cb(c)) {
cb_msb = get_temp(ctx);
tcg_gen_movi_reg(cb_msb, 0);
tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb);
} else {
tcg_gen_add_reg(dest, in1, in2);
}
if (cond_need_sv(c)) {
sv = do_add_sv(ctx, dest, in1, in2);
}
cond = do_cond(c * 2 + f, dest, cb_msb, sv);
save_gpr(ctx, r, dest);
tcg_temp_free(dest);
return do_cbranch(ctx, disp, n, &cond);
}
static bool trans_addb(DisasContext *ctx, arg_addb *a)
{
nullify_over(ctx);
return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp);
}
static bool trans_addbi(DisasContext *ctx, arg_addbi *a)
{
nullify_over(ctx);
return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp);
}
static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
tcg_temp_free(tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
tcg_gen_shli_reg(tmp, tcg_r, a->p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
tcg_temp_free(tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
static bool trans_movb(DisasContext *ctx, arg_movb *a)
{
TCGv_reg dest;
DisasCond cond;
nullify_over(ctx);
dest = dest_gpr(ctx, a->r2);
if (a->r1 == 0) {
tcg_gen_movi_reg(dest, 0);
} else {
tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
}
cond = do_sed_cond(a->c, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
{
TCGv_reg dest;
DisasCond cond;
nullify_over(ctx);
dest = dest_gpr(ctx, a->r);
tcg_gen_movi_reg(dest, a->i);
cond = do_sed_cond(a->c, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
{
TCGv_reg dest;
if (a->c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, a->t);
if (a->r1 == 0) {
tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2));
tcg_gen_shr_reg(dest, dest, cpu_sar);
} else if (a->r1 == a->r2) {
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
tcg_gen_rotr_i32(t32, t32, cpu_sar);
tcg_gen_extu_i32_reg(dest, t32);
tcg_temp_free_i32(t32);
} else {
TCGv_i64 t = tcg_temp_new_i64();
TCGv_i64 s = tcg_temp_new_i64();
tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
tcg_gen_extu_reg_i64(s, cpu_sar);
tcg_gen_shr_i64(t, t, s);
tcg_gen_trunc_i64_reg(dest, t);
tcg_temp_free_i64(t);
tcg_temp_free_i64(s);
}
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
ctx->null_cond = do_sed_cond(a->c, dest);
}
return nullify_end(ctx);
}
static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
{
unsigned sa = 31 - a->cpos;
TCGv_reg dest, t2;
if (a->c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, a->t);
t2 = load_gpr(ctx, a->r2);
if (a->r1 == a->r2) {
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_trunc_reg_i32(t32, t2);
tcg_gen_rotri_i32(t32, t32, sa);
tcg_gen_extu_i32_reg(dest, t32);
tcg_temp_free_i32(t32);
} else if (a->r1 == 0) {
tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
} else {
TCGv_reg t0 = tcg_temp_new();
tcg_gen_extract_reg(t0, t2, sa, 32 - sa);
tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
tcg_temp_free(t0);
}
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
ctx->null_cond = do_sed_cond(a->c, dest);
}
return nullify_end(ctx);
}
static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
{
unsigned len = 32 - a->clen;
TCGv_reg dest, src, tmp;
if (a->c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, a->t);
src = load_gpr(ctx, a->r);
tmp = tcg_temp_new();
/* Recall that SAR is using big-endian bit numbering. */
tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1);
if (a->se) {
tcg_gen_sar_reg(dest, src, tmp);
tcg_gen_sextract_reg(dest, dest, 0, len);
} else {
tcg_gen_shr_reg(dest, src, tmp);
tcg_gen_extract_reg(dest, dest, 0, len);
}
tcg_temp_free(tmp);
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
ctx->null_cond = do_sed_cond(a->c, dest);
}
return nullify_end(ctx);
}
static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
{
unsigned len = 32 - a->clen;
unsigned cpos = 31 - a->pos;
TCGv_reg dest, src;
if (a->c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, a->t);
src = load_gpr(ctx, a->r);
if (a->se) {
tcg_gen_sextract_reg(dest, src, cpos, len);
} else {
tcg_gen_extract_reg(dest, src, cpos, len);
}
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
ctx->null_cond = do_sed_cond(a->c, dest);
}
return nullify_end(ctx);
}
static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
{
unsigned len = 32 - a->clen;
target_sreg mask0, mask1;
TCGv_reg dest;
if (a->c) {
nullify_over(ctx);
}
if (a->cpos + len > 32) {
len = 32 - a->cpos;
}
dest = dest_gpr(ctx, a->t);
mask0 = deposit64(0, a->cpos, len, a->i);
mask1 = deposit64(-1, a->cpos, len, a->i);
if (a->nz) {
TCGv_reg src = load_gpr(ctx, a->t);
if (mask1 != -1) {
tcg_gen_andi_reg(dest, src, mask1);
src = dest;
}
tcg_gen_ori_reg(dest, src, mask0);
} else {
tcg_gen_movi_reg(dest, mask0);
}
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
ctx->null_cond = do_sed_cond(a->c, dest);
}
return nullify_end(ctx);
}
static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a)
{
unsigned rs = a->nz ? a->t : 0;
unsigned len = 32 - a->clen;
TCGv_reg dest, val;
if (a->c) {
nullify_over(ctx);
}
if (a->cpos + len > 32) {
len = 32 - a->cpos;
}
dest = dest_gpr(ctx, a->t);
val = load_gpr(ctx, a->r);
if (rs == 0) {
tcg_gen_deposit_z_reg(dest, val, a->cpos, len);
} else {
tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len);
}
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
ctx->null_cond = do_sed_cond(a->c, dest);
}
return nullify_end(ctx);
}
static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
unsigned nz, unsigned clen, TCGv_reg val)
{
unsigned rs = nz ? rt : 0;
unsigned len = 32 - clen;
TCGv_reg mask, tmp, shift, dest;
unsigned msb = 1U << (len - 1);
if (c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, rt);
shift = tcg_temp_new();
tmp = tcg_temp_new();
/* Convert big-endian bit numbering in SAR to left-shift. */
tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1);
mask = tcg_const_reg(msb + (msb - 1));
tcg_gen_and_reg(tmp, val, mask);
if (rs) {
tcg_gen_shl_reg(mask, mask, shift);
tcg_gen_shl_reg(tmp, tmp, shift);
tcg_gen_andc_reg(dest, cpu_gr[rs], mask);
tcg_gen_or_reg(dest, dest, tmp);
} else {
tcg_gen_shl_reg(dest, tmp, shift);
}
tcg_temp_free(shift);
tcg_temp_free(mask);
tcg_temp_free(tmp);
save_gpr(ctx, rt, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
ctx->null_cond = do_sed_cond(c, dest);
}
return nullify_end(ctx);
}
static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a)
{
return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r));
}
static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a)
{
return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a->i));
}
static bool trans_be(DisasContext *ctx, arg_be *a)
{
TCGv_reg tmp;
#ifdef CONFIG_USER_ONLY
/* ??? It seems like there should be a good way of using
"be disp(sr2, r0)", the canonical gateway entry mechanism
to our advantage. But that appears to be inconvenient to
manage along side branch delay slots. Therefore we handle
entry into the gateway page via absolute address. */
/* Since we don't implement spaces, just branch. Do notice the special
case of "be disp(*,r0)" using a direct branch to disp, so that we can
goto_tb to the TB containing the syscall. */
if (a->b == 0) {
return do_dbranch(ctx, a->disp, a->l, a->n);
}
#else
nullify_over(ctx);
#endif
tmp = get_temp(ctx);
tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp);
tmp = do_ibranch_priv(ctx, tmp);
#ifdef CONFIG_USER_ONLY
return do_ibranch(ctx, tmp, a->l, a->n);
#else
TCGv_i64 new_spc = tcg_temp_new_i64();
load_spr(ctx, new_spc, a->sp);
if (a->l) {
copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f);
}
if (a->n && use_nullify_skip(ctx)) {
tcg_gen_mov_reg(cpu_iaoq_f, tmp);
tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4);
tcg_gen_mov_i64(cpu_iasq_f, new_spc);
tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f);
} else {
copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
tcg_gen_mov_reg(cpu_iaoq_b, tmp);
tcg_gen_mov_i64(cpu_iasq_b, new_spc);
nullify_set(ctx, a->n);
}
tcg_temp_free_i64(new_spc);
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
}
static bool trans_bl(DisasContext *ctx, arg_bl *a)
{
return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n);
}
static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
{
target_ureg dest = iaoq_dest(ctx, a->disp);
nullify_over(ctx);
/* Make sure the caller hasn't done something weird with the queue.
* ??? This is not quite the same as the PSW[B] bit, which would be
* expensive to track. Real hardware will trap for
* b gateway
* b gateway+4 (in delay slot of first branch)
* However, checking for a non-sequential instruction queue *will*
* diagnose the security hole
* b gateway
* b evil
* in which instructions at evil would run with increased privs.
*/
if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) {
return gen_illegal(ctx);
}
#ifndef CONFIG_USER_ONLY
if (ctx->tb_flags & PSW_C) {
CPUHPPAState *env = ctx->cs->env_ptr;
int type = hppa_artype_for_page(env, ctx->base.pc_next);
/* If we could not find a TLB entry, then we need to generate an
ITLB miss exception so the kernel will provide it.
The resulting TLB fill operation will invalidate this TB and
we will re-translate, at which point we *will* be able to find
the TLB entry and determine if this is in fact a gateway page. */
if (type < 0) {
gen_excp(ctx, EXCP_ITLB_MISS);
return true;
}
/* No change for non-gateway pages or for priv decrease. */
if (type >= 4 && type - 4 < ctx->privilege) {
dest = deposit32(dest, 0, 2, type - 4);
}
} else {
dest &= -4; /* priv = 0 */
}
#endif
if (a->l) {
TCGv_reg tmp = dest_gpr(ctx, a->l);
if (ctx->privilege < 3) {
tcg_gen_andi_reg(tmp, tmp, -4);
}
tcg_gen_ori_reg(tmp, tmp, ctx->privilege);
save_gpr(ctx, a->l, tmp);
}
return do_dbranch(ctx, dest, 0, a->n);
}
static bool trans_blr(DisasContext *ctx, arg_blr *a)
{
if (a->x) {
TCGv_reg tmp = get_temp(ctx);
tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3);
tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8);
/* The computation here never changes privilege level. */
return do_ibranch(ctx, tmp, a->l, a->n);
} else {
/* BLR R0,RX is a good way to load PC+8 into RX. */
return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n);
}
}
static bool trans_bv(DisasContext *ctx, arg_bv *a)
{
TCGv_reg dest;
if (a->x == 0) {
dest = load_gpr(ctx, a->b);
} else {
dest = get_temp(ctx);
tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3);
tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b));
}
dest = do_ibranch_priv(ctx, dest);
return do_ibranch(ctx, dest, 0, a->n);
}
static bool trans_bve(DisasContext *ctx, arg_bve *a)
{
TCGv_reg dest;
#ifdef CONFIG_USER_ONLY
dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b));
return do_ibranch(ctx, dest, a->l, a->n);
#else
nullify_over(ctx);
dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b));
copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
copy_iaoq_entry(cpu_iaoq_b, -1, dest);
tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest));
if (a->l) {
copy_iaoq_entry(cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var);
}
nullify_set(ctx, a->n);
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
}
/*
* Float class 0
*/
static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
{
tcg_gen_mov_i32(dst, src);
}
static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f);
}
static void gen_fcpy_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src)
{
tcg_gen_mov_i64(dst, src);
}
static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d);
}
static void gen_fabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
{
tcg_gen_andi_i32(dst, src, INT32_MAX);
}
static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_fabs_f);
}
static void gen_fabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src)
{
tcg_gen_andi_i64(dst, src, INT64_MAX);
}
static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_fabs_d);
}
static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s);
}
static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d);
}
static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s);
}
static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d);
}
static void gen_fneg_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
{
tcg_gen_xori_i32(dst, src, INT32_MIN);
}
static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_fneg_f);
}
static void gen_fneg_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src)
{
tcg_gen_xori_i64(dst, src, INT64_MIN);
}
static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_fneg_d);
}
static void gen_fnegabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
{
tcg_gen_ori_i32(dst, src, INT32_MIN);
}
static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f);
}
static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src)
{
tcg_gen_ori_i64(dst, src, INT64_MIN);
}
static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d);
}
/*
* Float class 1
*/
static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s);
}
static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d);
}
static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s);
}
static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s);
}
static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d);
}
static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d);
}
static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w);
}
static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w);
}
static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw);
}
static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw);
}
static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w);
}
static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w);
}
static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw);
}
static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw);
}
static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s);
}
static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s);
}
static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d);
}
static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d);
}
static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw);
}
static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw);
}
static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw);
}
static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw);
}
static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw);
}
static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw);
}
static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw);
}
static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a)
{
return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw);
}
/*
* Float class 2
*/
static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a)
{
TCGv_i32 ta, tb, tc, ty;
nullify_over(ctx);
ta = load_frw0_i32(a->r1);
tb = load_frw0_i32(a->r2);
ty = tcg_const_i32(a->y);
tc = tcg_const_i32(a->c);
gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc);
tcg_temp_free_i32(ta);
tcg_temp_free_i32(tb);
tcg_temp_free_i32(ty);
tcg_temp_free_i32(tc);
return nullify_end(ctx);
}
static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a)
{
TCGv_i64 ta, tb;
TCGv_i32 tc, ty;
nullify_over(ctx);
ta = load_frd0(a->r1);
tb = load_frd0(a->r2);
ty = tcg_const_i32(a->y);
tc = tcg_const_i32(a->c);
gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(tb);
tcg_temp_free_i32(ty);
tcg_temp_free_i32(tc);
return nullify_end(ctx);
}
static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
{
TCGv_reg t;
nullify_over(ctx);
t = get_temp(ctx);
tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) {
int mask;
bool inv = false;
switch (a->c) {
case 0: /* simple */
tcg_gen_andi_reg(t, t, 0x4000000);
ctx->null_cond = cond_make_0(TCG_COND_NE, t);
goto done;
case 2: /* rej */
inv = true;
/* fallthru */
case 1: /* acc */
mask = 0x43ff800;
break;
case 6: /* rej8 */
inv = true;
/* fallthru */
case 5: /* acc8 */
mask = 0x43f8000;
break;
case 9: /* acc6 */
mask = 0x43e0000;
break;
case 13: /* acc4 */
mask = 0x4380000;
break;
case 17: /* acc2 */
mask = 0x4200000;
break;
default:
gen_illegal(ctx);
return true;
}
if (inv) {
TCGv_reg c = load_const(ctx, mask);
tcg_gen_or_reg(t, t, c);
ctx->null_cond = cond_make(TCG_COND_EQ, t, c);
} else {
tcg_gen_andi_reg(t, t, mask);
ctx->null_cond = cond_make_0(TCG_COND_EQ, t);
}
} else {
unsigned cbit = (a->y ^ 1) - 1;
tcg_gen_extract_reg(t, t, 21 - cbit, 1);
ctx->null_cond = cond_make_0(TCG_COND_NE, t);
tcg_temp_free(t);
}
done:
return nullify_end(ctx);
}
/*
* Float class 2
*/
static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s);
}
static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d);
}
static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s);
}
static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d);
}
static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s);
}
static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d);
}
static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s);
}
static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a)
{
return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d);
}
static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a)
{
TCGv_i64 x, y;
nullify_over(ctx);
x = load_frw0_i64(a->r1);
y = load_frw0_i64(a->r2);
tcg_gen_mul_i64(x, x, y);
save_frd(a->t, x);
tcg_temp_free_i64(x);
tcg_temp_free_i64(y);
return nullify_end(ctx);
}
/* Convert the fmpyadd single-precision register encodings to standard. */
static inline int fmpyadd_s_reg(unsigned r)
{
return (r & 16) * 2 + 16 + (r & 15);
}
static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub)
{
int tm = fmpyadd_s_reg(a->tm);
int ra = fmpyadd_s_reg(a->ra);
int ta = fmpyadd_s_reg(a->ta);
int rm2 = fmpyadd_s_reg(a->rm2);
int rm1 = fmpyadd_s_reg(a->rm1);
nullify_over(ctx);
do_fop_weww(ctx, tm, rm1, rm2, gen_helper_fmpy_s);
do_fop_weww(ctx, ta, ta, ra,
is_sub ? gen_helper_fsub_s : gen_helper_fadd_s);
return nullify_end(ctx);
}
static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a)
{
return do_fmpyadd_s(ctx, a, false);
}
static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a)
{
return do_fmpyadd_s(ctx, a, true);
}
static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub)
{
nullify_over(ctx);
do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d);
do_fop_dedd(ctx, a->ta, a->ta, a->ra,
is_sub ? gen_helper_fsub_d : gen_helper_fadd_d);
return nullify_end(ctx);
}
static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a)
{
return do_fmpyadd_d(ctx, a, false);
}
static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a)
{
return do_fmpyadd_d(ctx, a, true);
}
static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a)
{
TCGv_i32 x, y, z;
nullify_over(ctx);
x = load_frw0_i32(a->rm1);
y = load_frw0_i32(a->rm2);
z = load_frw0_i32(a->ra3);
if (a->neg) {
gen_helper_fmpynfadd_s(x, cpu_env, x, y, z);
} else {
gen_helper_fmpyfadd_s(x, cpu_env, x, y, z);
}
tcg_temp_free_i32(y);
tcg_temp_free_i32(z);
save_frw_i32(a->t, x);
tcg_temp_free_i32(x);
return nullify_end(ctx);
}
static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a)
{
TCGv_i64 x, y, z;
nullify_over(ctx);
x = load_frd0(a->rm1);
y = load_frd0(a->rm2);
z = load_frd0(a->ra3);
if (a->neg) {
gen_helper_fmpynfadd_d(x, cpu_env, x, y, z);
} else {
gen_helper_fmpyfadd_d(x, cpu_env, x, y, z);
}
tcg_temp_free_i64(y);
tcg_temp_free_i64(z);
save_frd(a->t, x);
tcg_temp_free_i64(x);
return nullify_end(ctx);
}
static bool trans_diag(DisasContext *ctx, arg_diag *a)
{
qemu_log_mask(LOG_UNIMP, "DIAG opcode ignored\n");
cond_free(&ctx->null_cond);
return true;
}
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
int bound;
ctx->cs = cs;
ctx->tb_flags = ctx->base.tb->flags;
#ifdef CONFIG_USER_ONLY
ctx->privilege = MMU_USER_IDX;
ctx->mmu_idx = MMU_USER_IDX;
ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
#else
ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);
/* Recover the IAOQ values from the GVA + PRIV. */
uint64_t cs_base = ctx->base.tb->cs_base;
uint64_t iasq_f = cs_base & ~0xffffffffull;
int32_t diff = cs_base;
ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege;
ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1);
#endif
ctx->iaoq_n = -1;
ctx->iaoq_n_var = NULL;
/* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
ctx->ntempr = 0;
ctx->ntempl = 0;
memset(ctx->tempr, 0, sizeof(ctx->tempr));
memset(ctx->templ, 0, sizeof(ctx->templ));
}
static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
/* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
ctx->null_cond = cond_make_f();
ctx->psw_n_nonzero = false;
if (ctx->tb_flags & PSW_N) {
ctx->null_cond.c = TCG_COND_ALWAYS;
ctx->psw_n_nonzero = true;
}
ctx->null_lab = NULL;
}
static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b);
}
static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
const CPUBreakpoint *bp)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
gen_excp(ctx, EXCP_DEBUG);
ctx->base.pc_next += 4;
return true;
}
static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUHPPAState *env = cs->env_ptr;
DisasJumpType ret;
int i, n;
/* Execute one insn. */
#ifdef CONFIG_USER_ONLY
if (ctx->base.pc_next < TARGET_PAGE_SIZE) {
do_page_zero(ctx);
ret = ctx->base.is_jmp;
assert(ret != DISAS_NEXT);
} else
#endif
{
/* Always fetch the insn, even if nullified, so that we check
the page permissions for execute. */
uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next);
/* Set up the IA queue for the next insn.
This will be overwritten by a branch. */
if (ctx->iaoq_b == -1) {
ctx->iaoq_n = -1;
ctx->iaoq_n_var = get_temp(ctx);
tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4);
} else {
ctx->iaoq_n = ctx->iaoq_b + 4;
ctx->iaoq_n_var = NULL;
}
if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) {
ctx->null_cond.c = TCG_COND_NEVER;
ret = DISAS_NEXT;
} else {
ctx->insn = insn;
if (!decode(ctx, insn)) {
gen_illegal(ctx);
}
ret = ctx->base.is_jmp;
assert(ctx->null_lab == NULL);
}
}
/* Free any temporaries allocated. */
for (i = 0, n = ctx->ntempr; i < n; ++i) {
tcg_temp_free(ctx->tempr[i]);
ctx->tempr[i] = NULL;
}
for (i = 0, n = ctx->ntempl; i < n; ++i) {
tcg_temp_free_tl(ctx->templ[i]);
ctx->templ[i] = NULL;
}
ctx->ntempr = 0;
ctx->ntempl = 0;
/* Advance the insn queue. Note that this check also detects
a priority change within the instruction queue. */
if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) {
if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1
&& use_goto_tb(ctx, ctx->iaoq_b)
&& (ctx->null_cond.c == TCG_COND_NEVER
|| ctx->null_cond.c == TCG_COND_ALWAYS)) {
nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS);
gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n);
ctx->base.is_jmp = ret = DISAS_NORETURN;
} else {
ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE;
}
}
ctx->iaoq_f = ctx->iaoq_b;
ctx->iaoq_b = ctx->iaoq_n;
ctx->base.pc_next += 4;
switch (ret) {
case DISAS_NORETURN:
case DISAS_IAQ_N_UPDATED:
break;
case DISAS_NEXT:
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
if (ctx->iaoq_f == -1) {
tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b);
copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
#ifndef CONFIG_USER_ONLY
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
#endif
nullify_save(ctx);
ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT
? DISAS_EXIT
: DISAS_IAQ_N_UPDATED);
} else if (ctx->iaoq_b == -1) {
tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var);
}
break;
default:
g_assert_not_reached();
}
}
static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
DisasJumpType is_jmp = ctx->base.is_jmp;
switch (is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
/* FALLTHRU */
case DISAS_IAQ_N_UPDATED:
if (ctx->base.singlestep_enabled) {
gen_excp_1(EXCP_DEBUG);
} else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
tcg_gen_lookup_and_goto_ptr();
}
/* FALLTHRU */
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
{
target_ulong pc = dcbase->pc_first;
#ifdef CONFIG_USER_ONLY
switch (pc) {
case 0x00:
qemu_log("IN:\n0x00000000: (null)\n");
return;
case 0xb0:
qemu_log("IN:\n0x000000b0: light-weight-syscall\n");
return;
case 0xe0:
qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n");
return;
case 0x100:
qemu_log("IN:\n0x00000100: syscall\n");
return;
}
#endif
qemu_log("IN: %s\n", lookup_symbol(pc));
log_target_disas(cs, pc, dcbase->tb->size);
}
static const TranslatorOps hppa_tr_ops = {
.init_disas_context = hppa_tr_init_disas_context,
.tb_start = hppa_tr_tb_start,
.insn_start = hppa_tr_insn_start,
.breakpoint_check = hppa_tr_breakpoint_check,
.translate_insn = hppa_tr_translate_insn,
.tb_stop = hppa_tr_tb_stop,
.disas_log = hppa_tr_disas_log,
};
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
DisasContext ctx;
translator_loop(&hppa_tr_ops, &ctx.base, cs, tb);
}
void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
target_ulong *data)
{
env->iaoq_f = data[0];
if (data[1] != (target_ureg)-1) {
env->iaoq_b = data[1];
}
/* Since we were executing the instruction at IAOQ_F, and took some
sort of action that provoked the cpu_restore_state, we can infer
that the instruction was not nullified. */
env->psw_n = 0;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/libqos/qgraph_internal.h | <gh_stars>1-10
/*
* libqos driver framework
*
* Copyright (c) 2018 <NAME> <<EMAIL>>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License version 2 as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#ifndef QGRAPH_EXTRA_H
#define QGRAPH_EXTRA_H
/* This header is declaring additional helper functions defined in
* libqos/qgraph.c
* It should not be included in tests
*/
#include "libqos/qgraph.h"
typedef struct QOSGraphMachine QOSGraphMachine;
typedef enum QOSEdgeType QOSEdgeType;
typedef enum QOSNodeType QOSNodeType;
/* callback called when the walk path algorithm found a
* valid path
*/
typedef void (*QOSTestCallback) (QOSGraphNode *path, int len);
/* edge types*/
enum QOSEdgeType {
QEDGE_CONTAINS,
QEDGE_PRODUCES,
QEDGE_CONSUMED_BY
};
/* node types*/
enum QOSNodeType {
QNODE_MACHINE,
QNODE_DRIVER,
QNODE_INTERFACE,
QNODE_TEST
};
/* Graph Node */
struct QOSGraphNode {
QOSNodeType type;
bool available; /* set by QEMU via QMP, used during graph walk */
bool visited; /* used during graph walk */
char *name; /* used to identify the node */
char *command_line; /* used to start QEMU at test execution */
union {
struct {
QOSCreateDriverFunc constructor;
} driver;
struct {
QOSCreateMachineFunc constructor;
} machine;
struct {
QOSTestFunc function;
void *arg;
QOSBeforeTest before;
bool subprocess;
} test;
} u;
/**
* only used when traversing the path, never rely on that except in the
* qos_traverse_graph callback function
*/
QOSGraphEdge *path_edge;
};
/**
* qos_graph_get_node(): returns the node mapped to that @key.
* It performs an hash map search O(1)
*
* Returns: on success: the %QOSGraphNode
* otherwise: #NULL
*/
QOSGraphNode *qos_graph_get_node(const char *key);
/**
* qos_graph_has_node(): returns #TRUE if the node
* has map has a node mapped to that @key.
*/
bool qos_graph_has_node(const char *node);
/**
* qos_graph_get_node_type(): returns the %QOSNodeType
* of the node @node.
* It performs an hash map search O(1)
* Returns: on success: the %QOSNodeType
* otherwise: #-1
*/
QOSNodeType qos_graph_get_node_type(const char *node);
/**
* qos_graph_get_node_availability(): returns the availability (boolean)
* of the node @node.
*/
bool qos_graph_get_node_availability(const char *node);
/**
* qos_graph_get_edge(): returns the edge
* linking of the node @node with @dest.
*
* Returns: on success: the %QOSGraphEdge
* otherwise: #NULL
*/
QOSGraphEdge *qos_graph_get_edge(const char *node, const char *dest);
/**
* qos_graph_edge_get_type(): returns the edge type
* of the edge @edge.
*
* Returns: on success: the %QOSEdgeType
* otherwise: #-1
*/
QOSEdgeType qos_graph_edge_get_type(QOSGraphEdge *edge);
/**
* qos_graph_edge_get_dest(): returns the name of the node
* pointed as destination of edge @edge.
*
* Returns: on success: the destination
* otherwise: #NULL
*/
char *qos_graph_edge_get_dest(QOSGraphEdge *edge);
/**
* qos_graph_has_edge(): returns #TRUE if there
* exists an edge from @start to @dest.
*/
bool qos_graph_has_edge(const char *start, const char *dest);
/**
* qos_graph_edge_get_arg(): returns the args assigned
* to that @edge.
*
* Returns: on success: the arg
* otherwise: #NULL
*/
void *qos_graph_edge_get_arg(QOSGraphEdge *edge);
/**
* qos_graph_edge_get_after_cmd_line(): returns the edge
* command line that will be added after all the node arguments
* and all the before_cmd_line arguments.
*
* Returns: on success: the char* arg
* otherwise: #NULL
*/
char *qos_graph_edge_get_after_cmd_line(QOSGraphEdge *edge);
/**
* qos_graph_edge_get_before_cmd_line(): returns the edge
* command line that will be added before the node command
* line argument.
*
* Returns: on success: the char* arg
* otherwise: #NULL
*/
char *qos_graph_edge_get_before_cmd_line(QOSGraphEdge *edge);
/**
* qos_graph_edge_get_extra_device_opts(): returns the arg
* command line that will be added to the node command
* line argument.
*
* Returns: on success: the char* arg
* otherwise: #NULL
*/
char *qos_graph_edge_get_extra_device_opts(QOSGraphEdge *edge);
/**
* qos_graph_edge_get_name(): returns the name
* assigned to the destination node (different only)
* if there are multiple devices with the same node name
* e.g. a node has two "generic-sdhci", "emmc" and "sdcard"
* there will be two edges with edge_name ="emmc" and "sdcard"
*
* Returns always the char* edge_name
*/
char *qos_graph_edge_get_name(QOSGraphEdge *edge);
/**
* qos_graph_get_machine(): returns the machine assigned
* to that @node name.
*
* It performs a search only trough the list of machines
* (i.e. the QOS_ROOT child).
*
* Returns: on success: the %QOSGraphNode
* otherwise: #NULL
*/
QOSGraphNode *qos_graph_get_machine(const char *node);
/**
* qos_graph_has_machine(): returns #TRUE if the node
* has map has a node mapped to that @node.
*/
bool qos_graph_has_machine(const char *node);
/**
* qos_print_graph(): walks the graph and prints
* all machine-to-test paths.
*/
void qos_print_graph(void);
/**
* qos_graph_foreach_test_path(): executes the Depth First search
* algorithm and applies @fn to all discovered paths.
*
* See qos_traverse_graph() in qgraph.c for more info on
* how it works.
*/
void qos_graph_foreach_test_path(QOSTestCallback fn);
/**
* qos_get_machine_type(): return QEMU machine type for a machine node.
* This function requires every machine @name to be in the form
* <arch>/<machine_name>, like "arm/raspi2" or "x86_64/pc".
*
* The function will validate the format and return a pointer to
* @machine to <machine_name>. For example, when passed "x86_64/pc"
* it will return "pc".
*
* Note that this function *does not* allocate any new string.
*/
char *qos_get_machine_type(char *name);
/**
* qos_delete_cmd_line(): delete the
* command line present in node mapped with key @name.
*
* This function is called when the QMP query returns a node with
* { "abstract" : true } attribute.
*/
void qos_delete_cmd_line(const char *name);
/**
* qos_graph_node_set_availability(): sets the node identified
* by @node with availability @av.
*/
void qos_graph_node_set_availability(const char *node, bool av);
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_h.c | <filename>src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_h.c
/*
* Test program for MSA instruction ILVEV.H
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "*ILVEV.H";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, }, /* 0 */
{ 0xffff0000ffff0000ULL, 0xffff0000ffff0000ULL, },
{ 0xffffaaaaffffaaaaULL, 0xffffaaaaffffaaaaULL, },
{ 0xffff5555ffff5555ULL, 0xffff5555ffff5555ULL, },
{ 0xffffccccffffccccULL, 0xffffccccffffccccULL, },
{ 0xffff3333ffff3333ULL, 0xffff3333ffff3333ULL, },
{ 0xffff38e3ffffe38eULL, 0xffff8e38ffff38e3ULL, },
{ 0xffffc71cffff1c71ULL, 0xffff71c7ffffc71cULL, },
{ 0x0000ffff0000ffffULL, 0x0000ffff0000ffffULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000aaaa0000aaaaULL, 0x0000aaaa0000aaaaULL, },
{ 0x0000555500005555ULL, 0x0000555500005555ULL, },
{ 0x0000cccc0000ccccULL, 0x0000cccc0000ccccULL, },
{ 0x0000333300003333ULL, 0x0000333300003333ULL, },
{ 0x000038e30000e38eULL, 0x00008e38000038e3ULL, },
{ 0x0000c71c00001c71ULL, 0x000071c70000c71cULL, },
{ 0xaaaaffffaaaaffffULL, 0xaaaaffffaaaaffffULL, }, /* 16 */
{ 0xaaaa0000aaaa0000ULL, 0xaaaa0000aaaa0000ULL, },
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0xaaaa5555aaaa5555ULL, 0xaaaa5555aaaa5555ULL, },
{ 0xaaaaccccaaaaccccULL, 0xaaaaccccaaaaccccULL, },
{ 0xaaaa3333aaaa3333ULL, 0xaaaa3333aaaa3333ULL, },
{ 0xaaaa38e3aaaae38eULL, 0xaaaa8e38aaaa38e3ULL, },
{ 0xaaaac71caaaa1c71ULL, 0xaaaa71c7aaaac71cULL, },
{ 0x5555ffff5555ffffULL, 0x5555ffff5555ffffULL, }, /* 24 */
{ 0x5555000055550000ULL, 0x5555000055550000ULL, },
{ 0x5555aaaa5555aaaaULL, 0x5555aaaa5555aaaaULL, },
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0x5555cccc5555ccccULL, 0x5555cccc5555ccccULL, },
{ 0x5555333355553333ULL, 0x5555333355553333ULL, },
{ 0x555538e35555e38eULL, 0x55558e38555538e3ULL, },
{ 0x5555c71c55551c71ULL, 0x555571c75555c71cULL, },
{ 0xccccffffccccffffULL, 0xccccffffccccffffULL, }, /* 32 */
{ 0xcccc0000cccc0000ULL, 0xcccc0000cccc0000ULL, },
{ 0xccccaaaaccccaaaaULL, 0xccccaaaaccccaaaaULL, },
{ 0xcccc5555cccc5555ULL, 0xcccc5555cccc5555ULL, },
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0xcccc3333cccc3333ULL, 0xcccc3333cccc3333ULL, },
{ 0xcccc38e3cccce38eULL, 0xcccc8e38cccc38e3ULL, },
{ 0xccccc71ccccc1c71ULL, 0xcccc71c7ccccc71cULL, },
{ 0x3333ffff3333ffffULL, 0x3333ffff3333ffffULL, }, /* 40 */
{ 0x3333000033330000ULL, 0x3333000033330000ULL, },
{ 0x3333aaaa3333aaaaULL, 0x3333aaaa3333aaaaULL, },
{ 0x3333555533335555ULL, 0x3333555533335555ULL, },
{ 0x3333cccc3333ccccULL, 0x3333cccc3333ccccULL, },
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0x333338e33333e38eULL, 0x33338e38333338e3ULL, },
{ 0x3333c71c33331c71ULL, 0x333371c73333c71cULL, },
{ 0x38e3ffffe38effffULL, 0x8e38ffff38e3ffffULL, }, /* 48 */
{ 0x38e30000e38e0000ULL, 0x8e38000038e30000ULL, },
{ 0x38e3aaaae38eaaaaULL, 0x8e38aaaa38e3aaaaULL, },
{ 0x38e35555e38e5555ULL, 0x8e38555538e35555ULL, },
{ 0x38e3cccce38eccccULL, 0x8e38cccc38e3ccccULL, },
{ 0x38e33333e38e3333ULL, 0x8e38333338e33333ULL, },
{ 0x38e338e3e38ee38eULL, 0x8e388e3838e338e3ULL, },
{ 0x38e3c71ce38e1c71ULL, 0x8e3871c738e3c71cULL, },
{ 0xc71cffff1c71ffffULL, 0x71c7ffffc71cffffULL, }, /* 56 */
{ 0xc71c00001c710000ULL, 0x71c70000c71c0000ULL, },
{ 0xc71caaaa1c71aaaaULL, 0x71c7aaaac71caaaaULL, },
{ 0xc71c55551c715555ULL, 0x71c75555c71c5555ULL, },
{ 0xc71ccccc1c71ccccULL, 0x71c7ccccc71cccccULL, },
{ 0xc71c33331c713333ULL, 0x71c73333c71c3333ULL, },
{ 0xc71c38e31c71e38eULL, 0x71c78e38c71c38e3ULL, },
{ 0xc71cc71c1c711c71ULL, 0x71c771c7c71cc71cULL, },
{ 0xe6cce6cc55405540ULL, 0x0b5e0b5eb00cb00cULL, }, /* 64 */
{ 0xe6cc00635540c708ULL, 0x0b5ebb1ab00c52fcULL, },
{ 0xe6ccaeaa55408b80ULL, 0x0b5ec6ffb00c2514ULL, },
{ 0xe6cc164d5540e24eULL, 0x0b5e88d8b00ce2a0ULL, },
{ 0x0063e6ccc7085540ULL, 0xbb1a0b5e52fcb00cULL, },
{ 0x00630063c708c708ULL, 0xbb1abb1a52fc52fcULL, },
{ 0x0063aeaac7088b80ULL, 0xbb1ac6ff52fc2514ULL, },
{ 0x0063164dc708e24eULL, 0xbb1a88d852fce2a0ULL, },
{ 0xaeaae6cc8b805540ULL, 0xc6ff0b5e2514b00cULL, }, /* 72 */
{ 0xaeaa00638b80c708ULL, 0xc6ffbb1a251452fcULL, },
{ 0xaeaaaeaa8b808b80ULL, 0xc6ffc6ff25142514ULL, },
{ 0xaeaa164d8b80e24eULL, 0xc6ff88d82514e2a0ULL, },
{ 0x164de6cce24e5540ULL, 0x88d80b5ee2a0b00cULL, },
{ 0x164d0063e24ec708ULL, 0x88d8bb1ae2a052fcULL, },
{ 0x164daeaae24e8b80ULL, 0x88d8c6ffe2a02514ULL, },
{ 0x164d164de24ee24eULL, 0x88d888d8e2a0e2a0ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_ILVEV_H(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_ILVEV_H(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/libqos/virtio-mmio.c | /*
* libqos virtio MMIO driver
*
* Copyright (c) 2014 <NAME>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/virtio.h"
#include "libqos/virtio-mmio.h"
#include "libqos/malloc.h"
#include "libqos/qgraph.h"
#include "standard-headers/linux/virtio_ring.h"
static uint8_t qvirtio_mmio_config_readb(QVirtioDevice *d, uint64_t off)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return qtest_readb(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);
}
static uint16_t qvirtio_mmio_config_readw(QVirtioDevice *d, uint64_t off)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return qtest_readw(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);
}
static uint32_t qvirtio_mmio_config_readl(QVirtioDevice *d, uint64_t off)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);
}
static uint64_t qvirtio_mmio_config_readq(QVirtioDevice *d, uint64_t off)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return qtest_readq(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);
}
static uint32_t qvirtio_mmio_get_features(QVirtioDevice *d)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES_SEL, 0);
return qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES);
}
static void qvirtio_mmio_set_features(QVirtioDevice *d, uint32_t features)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
dev->features = features;
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES_SEL, 0);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES, features);
}
static uint32_t qvirtio_mmio_get_guest_features(QVirtioDevice *d)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return dev->features;
}
static uint8_t qvirtio_mmio_get_status(QVirtioDevice *d)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return (uint8_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS);
}
static void qvirtio_mmio_set_status(QVirtioDevice *d, uint8_t status)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS, (uint32_t)status);
}
static bool qvirtio_mmio_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
uint32_t isr;
isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1;
if (isr != 0) {
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 1);
return true;
}
return false;
}
static bool qvirtio_mmio_get_config_isr_status(QVirtioDevice *d)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
uint32_t isr;
isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2;
if (isr != 0) {
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 2);
return true;
}
return false;
}
static void qvirtio_mmio_queue_select(QVirtioDevice *d, uint16_t index)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_SEL, (uint32_t)index);
g_assert_cmphex(qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN), ==, 0);
}
static uint16_t qvirtio_mmio_get_queue_size(QVirtioDevice *d)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
return (uint16_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM_MAX);
}
static void qvirtio_mmio_set_queue_address(QVirtioDevice *d, uint32_t pfn)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN, pfn);
}
static QVirtQueue *qvirtio_mmio_virtqueue_setup(QVirtioDevice *d,
QGuestAllocator *alloc, uint16_t index)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
QVirtQueue *vq;
uint64_t addr;
vq = g_malloc0(sizeof(*vq));
qvirtio_mmio_queue_select(d, index);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_ALIGN, dev->page_size);
vq->index = index;
vq->size = qvirtio_mmio_get_queue_size(d);
vq->free_head = 0;
vq->num_free = vq->size;
vq->align = dev->page_size;
vq->indirect = (dev->features & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
vq->event = (dev->features & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM, vq->size);
/* Check different than 0 */
g_assert_cmpint(vq->size, !=, 0);
/* Check power of 2 */
g_assert_cmpint(vq->size & (vq->size - 1), ==, 0);
addr = guest_alloc(alloc, qvring_size(vq->size, dev->page_size));
qvring_init(alloc, vq, addr);
qvirtio_mmio_set_queue_address(d, vq->desc / dev->page_size);
return vq;
}
static void qvirtio_mmio_virtqueue_cleanup(QVirtQueue *vq,
QGuestAllocator *alloc)
{
guest_free(alloc, vq->desc);
g_free(vq);
}
static void qvirtio_mmio_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
{
QVirtioMMIODevice *dev = container_of(d, QVirtioMMIODevice, vdev);
qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NOTIFY, vq->index);
}
const QVirtioBus qvirtio_mmio = {
.config_readb = qvirtio_mmio_config_readb,
.config_readw = qvirtio_mmio_config_readw,
.config_readl = qvirtio_mmio_config_readl,
.config_readq = qvirtio_mmio_config_readq,
.get_features = qvirtio_mmio_get_features,
.set_features = qvirtio_mmio_set_features,
.get_guest_features = qvirtio_mmio_get_guest_features,
.get_status = qvirtio_mmio_get_status,
.set_status = qvirtio_mmio_set_status,
.get_queue_isr_status = qvirtio_mmio_get_queue_isr_status,
.get_config_isr_status = qvirtio_mmio_get_config_isr_status,
.queue_select = qvirtio_mmio_queue_select,
.get_queue_size = qvirtio_mmio_get_queue_size,
.set_queue_address = qvirtio_mmio_set_queue_address,
.virtqueue_setup = qvirtio_mmio_virtqueue_setup,
.virtqueue_cleanup = qvirtio_mmio_virtqueue_cleanup,
.virtqueue_kick = qvirtio_mmio_virtqueue_kick,
};
static void *qvirtio_mmio_get_driver(void *obj, const char *interface)
{
QVirtioMMIODevice *virtio_mmio = obj;
if (!g_strcmp0(interface, "virtio-bus")) {
return &virtio_mmio->vdev;
}
fprintf(stderr, "%s not present in virtio-mmio\n", interface);
g_assert_not_reached();
}
static void qvirtio_mmio_start_hw(QOSGraphObject *obj)
{
QVirtioMMIODevice *dev = (QVirtioMMIODevice *) obj;
qvirtio_start_device(&dev->vdev);
}
void qvirtio_mmio_init_device(QVirtioMMIODevice *dev, QTestState *qts,
uint64_t addr, uint32_t page_size)
{
uint32_t magic;
magic = qtest_readl(qts, addr + QVIRTIO_MMIO_MAGIC_VALUE);
g_assert(magic == ('v' | 'i' << 8 | 'r' << 16 | 't' << 24));
dev->qts = qts;
dev->addr = addr;
dev->page_size = page_size;
dev->vdev.device_type = qtest_readl(qts, addr + QVIRTIO_MMIO_DEVICE_ID);
dev->vdev.bus = &qvirtio_mmio;
qtest_writel(qts, addr + QVIRTIO_MMIO_GUEST_PAGE_SIZE, page_size);
dev->obj.get_driver = qvirtio_mmio_get_driver;
dev->obj.start_hw = qvirtio_mmio_start_hw;
}
static void virtio_mmio_register_nodes(void)
{
qos_node_create_driver("virtio-mmio", NULL);
qos_node_produces("virtio-mmio", "virtio-bus");
}
libqos_init(virtio_mmio_register_nodes);
|
pmp-tool/PMP | src/qemu/src-pmp/target/i386/hvf/x86_decode.c | <reponame>pmp-tool/PMP
/*
* Copyright (C) 2016 Veertu Inc,
* Copyright (C) 2017 Google Inc,
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "panic.h"
#include "x86_decode.h"
#include "vmx.h"
#include "x86_mmu.h"
#include "x86_descr.h"
#define OPCODE_ESCAPE 0xf
static void decode_invalid(CPUX86State *env, struct x86_decode *decode)
{
printf("%llx: failed to decode instruction ", env->hvf_emul->fetch_rip -
decode->len);
for (int i = 0; i < decode->opcode_len; i++) {
printf("%x ", decode->opcode[i]);
}
printf("\n");
VM_PANIC("decoder failed\n");
}
uint64_t sign(uint64_t val, int size)
{
switch (size) {
case 1:
val = (int8_t)val;
break;
case 2:
val = (int16_t)val;
break;
case 4:
val = (int32_t)val;
break;
case 8:
val = (int64_t)val;
break;
default:
VM_PANIC_EX("%s invalid size %d\n", __func__, size);
break;
}
return val;
}
static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
int size)
{
target_ulong val = 0;
switch (size) {
case 1:
case 2:
case 4:
case 8:
break;
default:
VM_PANIC_EX("%s invalid size %d\n", __func__, size);
break;
}
target_ulong va = linear_rip(ENV_GET_CPU(env), RIP(env)) + decode->len;
vmx_read_mem(ENV_GET_CPU(env), &val, va, size);
decode->len += size;
return val;
}
static inline uint8_t decode_byte(CPUX86State *env, struct x86_decode *decode)
{
return (uint8_t)decode_bytes(env, decode, 1);
}
static inline uint16_t decode_word(CPUX86State *env, struct x86_decode *decode)
{
return (uint16_t)decode_bytes(env, decode, 2);
}
static inline uint32_t decode_dword(CPUX86State *env, struct x86_decode *decode)
{
return (uint32_t)decode_bytes(env, decode, 4);
}
static inline uint64_t decode_qword(CPUX86State *env, struct x86_decode *decode)
{
return decode_bytes(env, decode, 8);
}
static void decode_modrm_rm(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_RM;
}
static void decode_modrm_reg(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = decode->modrm.reg;
op->ptr = get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.r,
decode->operand_size);
}
static void decode_rax(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = R_EAX;
op->ptr = get_reg_ref(env, op->reg, decode->rex.rex, 0,
decode->operand_size);
}
static inline void decode_immediate(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *var, int size)
{
var->type = X86_VAR_IMMEDIATE;
var->size = size;
switch (size) {
case 1:
var->val = decode_byte(env, decode);
break;
case 2:
var->val = decode_word(env, decode);
break;
case 4:
var->val = decode_dword(env, decode);
break;
case 8:
var->val = decode_qword(env, decode);
break;
default:
VM_PANIC_EX("bad size %d\n", size);
}
}
static void decode_imm8(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
decode_immediate(env, decode, op, 1);
op->type = X86_VAR_IMMEDIATE;
}
static void decode_imm8_signed(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
decode_immediate(env, decode, op, 1);
op->val = sign(op->val, 1);
op->type = X86_VAR_IMMEDIATE;
}
static void decode_imm16(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
decode_immediate(env, decode, op, 2);
op->type = X86_VAR_IMMEDIATE;
}
static void decode_imm(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
if (8 == decode->operand_size) {
decode_immediate(env, decode, op, 4);
op->val = sign(op->val, decode->operand_size);
} else {
decode_immediate(env, decode, op, decode->operand_size);
}
op->type = X86_VAR_IMMEDIATE;
}
static void decode_imm_signed(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
decode_immediate(env, decode, op, decode->operand_size);
op->val = sign(op->val, decode->operand_size);
op->type = X86_VAR_IMMEDIATE;
}
static void decode_imm_1(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_IMMEDIATE;
op->val = 1;
}
static void decode_imm_0(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_IMMEDIATE;
op->val = 0;
}
static void decode_pushseg(CPUX86State *env, struct x86_decode *decode)
{
uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
decode->op[0].type = X86_VAR_REG;
switch (op) {
case 0xe:
decode->op[0].reg = R_CS;
break;
case 0x16:
decode->op[0].reg = R_SS;
break;
case 0x1e:
decode->op[0].reg = R_DS;
break;
case 0x06:
decode->op[0].reg = R_ES;
break;
case 0xa0:
decode->op[0].reg = R_FS;
break;
case 0xa8:
decode->op[0].reg = R_GS;
break;
}
}
static void decode_popseg(CPUX86State *env, struct x86_decode *decode)
{
uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
decode->op[0].type = X86_VAR_REG;
switch (op) {
case 0xf:
decode->op[0].reg = R_CS;
break;
case 0x17:
decode->op[0].reg = R_SS;
break;
case 0x1f:
decode->op[0].reg = R_DS;
break;
case 0x07:
decode->op[0].reg = R_ES;
break;
case 0xa1:
decode->op[0].reg = R_FS;
break;
case 0xa9:
decode->op[0].reg = R_GS;
break;
}
}
static void decode_incgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x40;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
}
static void decode_decgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x48;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
}
static void decode_incgroup2(CPUX86State *env, struct x86_decode *decode)
{
if (!decode->modrm.reg) {
decode->cmd = X86_DECODE_CMD_INC;
} else if (1 == decode->modrm.reg) {
decode->cmd = X86_DECODE_CMD_DEC;
}
}
static void decode_pushgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x50;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
}
static void decode_popgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x58;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
}
static void decode_jxx(CPUX86State *env, struct x86_decode *decode)
{
decode->displacement = decode_bytes(env, decode, decode->operand_size);
decode->displacement_size = decode->operand_size;
}
static void decode_farjmp(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_IMMEDIATE;
decode->op[0].val = decode_bytes(env, decode, decode->operand_size);
decode->displacement = decode_word(env, decode);
}
static void decode_addgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_ADD,
X86_DECODE_CMD_OR,
X86_DECODE_CMD_ADC,
X86_DECODE_CMD_SBB,
X86_DECODE_CMD_AND,
X86_DECODE_CMD_SUB,
X86_DECODE_CMD_XOR,
X86_DECODE_CMD_CMP
};
decode->cmd = group[decode->modrm.reg];
}
static void decode_rotgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_ROL,
X86_DECODE_CMD_ROR,
X86_DECODE_CMD_RCL,
X86_DECODE_CMD_RCR,
X86_DECODE_CMD_SHL,
X86_DECODE_CMD_SHR,
X86_DECODE_CMD_SHL,
X86_DECODE_CMD_SAR
};
decode->cmd = group[decode->modrm.reg];
}
static void decode_f7group(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_TST,
X86_DECODE_CMD_TST,
X86_DECODE_CMD_NOT,
X86_DECODE_CMD_NEG,
X86_DECODE_CMD_MUL,
X86_DECODE_CMD_IMUL_1,
X86_DECODE_CMD_DIV,
X86_DECODE_CMD_IDIV
};
decode->cmd = group[decode->modrm.reg];
decode_modrm_rm(env, decode, &decode->op[0]);
switch (decode->modrm.reg) {
case 0:
case 1:
decode_imm(env, decode, &decode->op[1]);
break;
case 2:
break;
case 3:
decode->op[1].type = X86_VAR_IMMEDIATE;
decode->op[1].val = 0;
break;
default:
break;
}
}
static void decode_xchgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x90;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
}
static void decode_movgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0xb8;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
decode_immediate(env, decode, &decode->op[1], decode->operand_size);
}
static void fetch_moffs(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_OFFSET;
op->ptr = decode_bytes(env, decode, decode->addressing_size);
}
static void decode_movgroup8(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0xb0;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
decode_immediate(env, decode, &decode->op[1], decode->operand_size);
}
static void decode_rcx(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = R_ECX;
op->ptr = get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.b,
decode->operand_size);
}
struct decode_tbl {
uint8_t opcode;
enum x86_decode_cmd cmd;
uint8_t operand_size;
bool is_modrm;
void (*decode_op1)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op1);
void (*decode_op2)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op2);
void (*decode_op3)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op3);
void (*decode_op4)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op4);
void (*decode_postfix)(CPUX86State *env, struct x86_decode *decode);
uint32_t flags_mask;
};
struct decode_x87_tbl {
uint8_t opcode;
uint8_t modrm_reg;
uint8_t modrm_mod;
enum x86_decode_cmd cmd;
uint8_t operand_size;
bool rev;
bool pop;
void (*decode_op1)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op1);
void (*decode_op2)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op2);
void (*decode_postfix)(CPUX86State *env, struct x86_decode *decode);
uint32_t flags_mask;
};
struct decode_tbl invl_inst = {0x0, 0, 0, false, NULL, NULL, NULL, NULL,
decode_invalid};
struct decode_tbl _decode_tbl1[256];
struct decode_tbl _decode_tbl2[256];
struct decode_x87_tbl _decode_tbl3[256];
static void decode_x87_ins(CPUX86State *env, struct x86_decode *decode)
{
struct decode_x87_tbl *decoder;
decode->is_fpu = true;
int mode = decode->modrm.mod == 3 ? 1 : 0;
int index = ((decode->opcode[0] & 0xf) << 4) | (mode << 3) |
decode->modrm.reg;
decoder = &_decode_tbl3[index];
decode->cmd = decoder->cmd;
if (decoder->operand_size) {
decode->operand_size = decoder->operand_size;
}
decode->flags_mask = decoder->flags_mask;
decode->fpop_stack = decoder->pop;
decode->frev = decoder->rev;
if (decoder->decode_op1) {
decoder->decode_op1(env, decode, &decode->op[0]);
}
if (decoder->decode_op2) {
decoder->decode_op2(env, decode, &decode->op[1]);
}
if (decoder->decode_postfix) {
decoder->decode_postfix(env, decode);
}
VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n",
decode->opcode[0], decode->modrm.modrm, decoder->modrm_reg,
decoder->modrm_mod);
}
static void decode_ffgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_INC,
X86_DECODE_CMD_DEC,
X86_DECODE_CMD_CALL_NEAR_ABS_INDIRECT,
X86_DECODE_CMD_CALL_FAR_ABS_INDIRECT,
X86_DECODE_CMD_JMP_NEAR_ABS_INDIRECT,
X86_DECODE_CMD_JMP_FAR_ABS_INDIRECT,
X86_DECODE_CMD_PUSH,
X86_DECODE_CMD_INVL,
X86_DECODE_CMD_INVL
};
decode->cmd = group[decode->modrm.reg];
if (decode->modrm.reg > 2) {
decode->flags_mask = 0;
}
}
static void decode_sldtgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_SLDT,
X86_DECODE_CMD_STR,
X86_DECODE_CMD_LLDT,
X86_DECODE_CMD_LTR,
X86_DECODE_CMD_VERR,
X86_DECODE_CMD_VERW,
X86_DECODE_CMD_INVL,
X86_DECODE_CMD_INVL
};
decode->cmd = group[decode->modrm.reg];
}
static void decode_lidtgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_SGDT,
X86_DECODE_CMD_SIDT,
X86_DECODE_CMD_LGDT,
X86_DECODE_CMD_LIDT,
X86_DECODE_CMD_SMSW,
X86_DECODE_CMD_LMSW,
X86_DECODE_CMD_LMSW,
X86_DECODE_CMD_INVLPG
};
decode->cmd = group[decode->modrm.reg];
if (0xf9 == decode->modrm.modrm) {
decode->opcode[decode->len++] = decode->modrm.modrm;
decode->cmd = X86_DECODE_CMD_RDTSCP;
}
}
static void decode_btgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_INVL,
X86_DECODE_CMD_INVL,
X86_DECODE_CMD_INVL,
X86_DECODE_CMD_INVL,
X86_DECODE_CMD_BT,
X86_DECODE_CMD_BTS,
X86_DECODE_CMD_BTR,
X86_DECODE_CMD_BTC
};
decode->cmd = group[decode->modrm.reg];
}
static void decode_x87_general(CPUX86State *env, struct x86_decode *decode)
{
decode->is_fpu = true;
}
static void decode_x87_modrm_floatp(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_FLOATP;
}
static void decode_x87_modrm_intp(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_INTP;
}
static void decode_x87_modrm_bytep(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_BYTEP;
}
static void decode_x87_modrm_st0(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_REG;
op->reg = 0;
}
static void decode_decode_x87_modrm_st0(CPUX86State *env,
struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_REG;
op->reg = decode->modrm.modrm & 7;
}
static void decode_aegroup(CPUX86State *env, struct x86_decode *decode)
{
decode->is_fpu = true;
switch (decode->modrm.reg) {
case 0:
decode->cmd = X86_DECODE_CMD_FXSAVE;
decode_x87_modrm_bytep(env, decode, &decode->op[0]);
break;
case 1:
decode_x87_modrm_bytep(env, decode, &decode->op[0]);
decode->cmd = X86_DECODE_CMD_FXRSTOR;
break;
case 5:
if (decode->modrm.modrm == 0xe8) {
decode->cmd = X86_DECODE_CMD_LFENCE;
} else {
VM_PANIC("xrstor");
}
break;
case 6:
VM_PANIC_ON(decode->modrm.modrm != 0xf0);
decode->cmd = X86_DECODE_CMD_MFENCE;
break;
case 7:
if (decode->modrm.modrm == 0xf8) {
decode->cmd = X86_DECODE_CMD_SFENCE;
} else {
decode->cmd = X86_DECODE_CMD_CLFLUSH;
}
break;
default:
VM_PANIC_EX("0xae: reg %d\n", decode->modrm.reg);
break;
}
}
static void decode_bswap(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[1] - 0xc8;
decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.rex,
decode->rex.b, decode->operand_size);
}
static void decode_d9_4(CPUX86State *env, struct x86_decode *decode)
{
switch (decode->modrm.modrm) {
case 0xe0:
/* FCHS */
decode->cmd = X86_DECODE_CMD_FCHS;
break;
case 0xe1:
decode->cmd = X86_DECODE_CMD_FABS;
break;
case 0xe4:
VM_PANIC("FTST");
break;
case 0xe5:
/* FXAM */
decode->cmd = X86_DECODE_CMD_FXAM;
break;
default:
VM_PANIC("FLDENV");
break;
}
}
static void decode_db_4(CPUX86State *env, struct x86_decode *decode)
{
switch (decode->modrm.modrm) {
case 0xe0:
VM_PANIC_EX("unhandled FNENI: %x %x\n", decode->opcode[0],
decode->modrm.modrm);
break;
case 0xe1:
VM_PANIC_EX("unhandled FNDISI: %x %x\n", decode->opcode[0],
decode->modrm.modrm);
break;
case 0xe2:
VM_PANIC_EX("unhandled FCLEX: %x %x\n", decode->opcode[0],
decode->modrm.modrm);
break;
case 0xe3:
decode->cmd = X86_DECODE_CMD_FNINIT;
break;
case 0xe4:
decode->cmd = X86_DECODE_CMD_FNSETPM;
break;
default:
VM_PANIC_EX("unhandled fpu opcode: %x %x\n", decode->opcode[0],
decode->modrm.modrm);
break;
}
}
#define RFLAGS_MASK_NONE 0
#define RFLAGS_MASK_OSZAPC (RFLAGS_OF | RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | \
RFLAGS_PF | RFLAGS_CF)
#define RFLAGS_MASK_LAHF (RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | \
RFLAGS_CF)
#define RFLAGS_MASK_CF (RFLAGS_CF)
#define RFLAGS_MASK_IF (RFLAGS_IF)
#define RFLAGS_MASK_TF (RFLAGS_TF)
#define RFLAGS_MASK_DF (RFLAGS_DF)
#define RFLAGS_MASK_ZF (RFLAGS_ZF)
struct decode_tbl _1op_inst[] = {
{0x0, X86_DECODE_CMD_ADD, 1, true, decode_modrm_rm, decode_modrm_reg, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x1, X86_DECODE_CMD_ADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x2, X86_DECODE_CMD_ADD, 1, true, decode_modrm_reg, decode_modrm_rm, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x3, X86_DECODE_CMD_ADD, 0, true, decode_modrm_reg, decode_modrm_rm, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x4, X86_DECODE_CMD_ADD, 1, false, decode_rax, decode_imm8, NULL, NULL,
NULL, RFLAGS_MASK_OSZAPC},
{0x5, X86_DECODE_CMD_ADD, 0, false, decode_rax, decode_imm, NULL, NULL,
NULL, RFLAGS_MASK_OSZAPC},
{0x6, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL,
decode_pushseg, RFLAGS_MASK_NONE},
{0x7, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL,
decode_popseg, RFLAGS_MASK_NONE},
{0x8, X86_DECODE_CMD_OR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x9, X86_DECODE_CMD_OR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xa, X86_DECODE_CMD_OR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL,
NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xb, X86_DECODE_CMD_OR, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xc, X86_DECODE_CMD_OR, 1, false, decode_rax, decode_imm8,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xd, X86_DECODE_CMD_OR, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xe, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
{0xf, X86_DECODE_CMD_POP_SEG, 0, false, false,
NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
{0x10, X86_DECODE_CMD_ADC, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x11, X86_DECODE_CMD_ADC, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x12, X86_DECODE_CMD_ADC, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x13, X86_DECODE_CMD_ADC, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x14, X86_DECODE_CMD_ADC, 1, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x15, X86_DECODE_CMD_ADC, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x16, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
{0x17, X86_DECODE_CMD_POP_SEG, 0, false, false,
NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
{0x18, X86_DECODE_CMD_SBB, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x19, X86_DECODE_CMD_SBB, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x1a, X86_DECODE_CMD_SBB, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x1b, X86_DECODE_CMD_SBB, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x1c, X86_DECODE_CMD_SBB, 1, false, decode_rax, decode_imm8,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x1d, X86_DECODE_CMD_SBB, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x1e, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
{0x1f, X86_DECODE_CMD_POP_SEG, 0, false, false,
NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
{0x20, X86_DECODE_CMD_AND, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x21, X86_DECODE_CMD_AND, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x22, X86_DECODE_CMD_AND, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x23, X86_DECODE_CMD_AND, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x24, X86_DECODE_CMD_AND, 1, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x25, X86_DECODE_CMD_AND, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x28, X86_DECODE_CMD_SUB, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x29, X86_DECODE_CMD_SUB, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x2a, X86_DECODE_CMD_SUB, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x2b, X86_DECODE_CMD_SUB, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x2c, X86_DECODE_CMD_SUB, 1, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x2d, X86_DECODE_CMD_SUB, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x2f, X86_DECODE_CMD_DAS, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x30, X86_DECODE_CMD_XOR, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x31, X86_DECODE_CMD_XOR, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x32, X86_DECODE_CMD_XOR, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x33, X86_DECODE_CMD_XOR, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x34, X86_DECODE_CMD_XOR, 1, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x35, X86_DECODE_CMD_XOR, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x38, X86_DECODE_CMD_CMP, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x39, X86_DECODE_CMD_CMP, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x3a, X86_DECODE_CMD_CMP, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x3b, X86_DECODE_CMD_CMP, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x3c, X86_DECODE_CMD_CMP, 1, false, decode_rax, decode_imm8,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x3d, X86_DECODE_CMD_CMP, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x3f, X86_DECODE_CMD_AAS, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x40, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x41, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x42, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x43, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x44, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x45, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x46, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x47, X86_DECODE_CMD_INC, 0, false,
NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
{0x48, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x49, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x4a, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x4b, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x4c, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x4d, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x4e, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x4f, X86_DECODE_CMD_DEC, 0, false,
NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
{0x50, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x51, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x52, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x53, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x54, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x55, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x56, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x57, X86_DECODE_CMD_PUSH, 0, false,
NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
{0x58, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x59, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x5a, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x5b, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x5c, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x5d, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x5e, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x5f, X86_DECODE_CMD_POP, 0, false,
NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
{0x60, X86_DECODE_CMD_PUSHA, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x61, X86_DECODE_CMD_POPA, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x68, X86_DECODE_CMD_PUSH, 0, false, decode_imm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x6a, X86_DECODE_CMD_PUSH, 0, false, decode_imm8_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x69, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg,
decode_modrm_rm, decode_imm, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x6b, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm,
decode_imm8_signed, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x6c, X86_DECODE_CMD_INS, 1, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x6d, X86_DECODE_CMD_INS, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x6e, X86_DECODE_CMD_OUTS, 1, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x6f, X86_DECODE_CMD_OUTS, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x70, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x71, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x72, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x73, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x74, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x75, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x76, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x77, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x78, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x79, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x7a, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x7b, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x7c, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x7d, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x7e, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x7f, X86_DECODE_CMD_JXX, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x80, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8,
NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
{0x81, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm,
NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
{0x82, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8,
NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
{0x83, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8_signed,
NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
{0x84, X86_DECODE_CMD_TST, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x85, X86_DECODE_CMD_TST, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0x86, X86_DECODE_CMD_XCHG, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x87, X86_DECODE_CMD_XCHG, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x88, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x89, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x8a, X86_DECODE_CMD_MOV, 1, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x8b, X86_DECODE_CMD_MOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x8c, X86_DECODE_CMD_MOV_FROM_SEG, 0, true, decode_modrm_rm,
decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x8d, X86_DECODE_CMD_LEA, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x8e, X86_DECODE_CMD_MOV_TO_SEG, 0, true, decode_modrm_reg,
decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x8f, X86_DECODE_CMD_POP, 0, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x90, X86_DECODE_CMD_NOP, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x91, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x92, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x93, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x94, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x95, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x96, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x97, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
{0x98, X86_DECODE_CMD_CBW, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x99, X86_DECODE_CMD_CWD, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9a, X86_DECODE_CMD_CALL_FAR, 0, false, NULL,
NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
{0x9c, X86_DECODE_CMD_PUSHF, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
/*{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_POPF},*/
{0x9e, X86_DECODE_CMD_SAHF, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9f, X86_DECODE_CMD_LAHF, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_LAHF},
{0xa0, X86_DECODE_CMD_MOV, 1, false, decode_rax, fetch_moffs,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa1, X86_DECODE_CMD_MOV, 0, false, decode_rax, fetch_moffs,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa2, X86_DECODE_CMD_MOV, 1, false, fetch_moffs, decode_rax,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa3, X86_DECODE_CMD_MOV, 0, false, fetch_moffs, decode_rax,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa4, X86_DECODE_CMD_MOVS, 1, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa5, X86_DECODE_CMD_MOVS, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa6, X86_DECODE_CMD_CMPS, 1, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xa7, X86_DECODE_CMD_CMPS, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xaa, X86_DECODE_CMD_STOS, 1, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xab, X86_DECODE_CMD_STOS, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xac, X86_DECODE_CMD_LODS, 1, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xad, X86_DECODE_CMD_LODS, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xae, X86_DECODE_CMD_SCAS, 1, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xaf, X86_DECODE_CMD_SCAS, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xa8, X86_DECODE_CMD_TST, 1, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xa9, X86_DECODE_CMD_TST, 0, false, decode_rax, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xb0, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb1, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb2, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb3, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb4, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb5, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb6, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb7, X86_DECODE_CMD_MOV, 1, false, NULL,
NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
{0xb8, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xb9, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xba, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xbb, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xbc, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xbd, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xbe, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xbf, X86_DECODE_CMD_MOV, 0, false, NULL,
NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
{0xc0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8,
NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
{0xc1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8,
NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
{0xc2, X86_DECODE_RET_NEAR, 0, false, decode_imm16,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc3, X86_DECODE_RET_NEAR, 0, false, NULL,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc4, X86_DECODE_CMD_LES, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc5, X86_DECODE_CMD_LDS, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc6, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_imm8,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc7, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_imm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc8, X86_DECODE_CMD_ENTER, 0, false, decode_imm16, decode_imm8,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xc9, X86_DECODE_CMD_LEAVE, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xca, X86_DECODE_RET_FAR, 0, false, decode_imm16, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xcb, X86_DECODE_RET_FAR, 0, false, decode_imm_0, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xcd, X86_DECODE_CMD_INT, 0, false, decode_imm8, NULL,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
/*{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL,
NULL, NULL, NULL, RFLAGS_MASK_IRET},*/
{0xd0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm_1,
NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
{0xd1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm_1,
NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
{0xd2, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_rcx,
NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
{0xd3, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_rcx,
NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
{0xd4, X86_DECODE_CMD_AAM, 0, false, decode_imm8,
NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xd5, X86_DECODE_CMD_AAD, 0, false, decode_imm8,
NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xd7, X86_DECODE_CMD_XLAT, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xd8, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xd9, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xda, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xdb, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xdc, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xdd, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xde, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xdf, X86_DECODE_CMD_INVL, 0, true, NULL,
NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
{0xe0, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe1, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe2, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe3, X86_DECODE_CMD_JCXZ, 1, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0xe4, X86_DECODE_CMD_IN, 1, false, decode_imm8,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe5, X86_DECODE_CMD_IN, 0, false, decode_imm8,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe6, X86_DECODE_CMD_OUT, 1, false, decode_imm8,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe7, X86_DECODE_CMD_OUT, 0, false, decode_imm8,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe8, X86_DECODE_CMD_CALL_NEAR, 0, false, decode_imm_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xe9, X86_DECODE_CMD_JMP_NEAR, 0, false, decode_imm_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xea, X86_DECODE_CMD_JMP_FAR, 0, false,
NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
{0xeb, X86_DECODE_CMD_JMP_NEAR, 1, false, decode_imm8_signed,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xec, X86_DECODE_CMD_IN, 1, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xed, X86_DECODE_CMD_IN, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xee, X86_DECODE_CMD_OUT, 1, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xef, X86_DECODE_CMD_OUT, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xf4, X86_DECODE_CMD_HLT, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xf5, X86_DECODE_CMD_CMC, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
{0xf6, X86_DECODE_CMD_INVL, 1, true,
NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
{0xf7, X86_DECODE_CMD_INVL, 0, true,
NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
{0xf8, X86_DECODE_CMD_CLC, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
{0xf9, X86_DECODE_CMD_STC, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
{0xfa, X86_DECODE_CMD_CLI, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
{0xfb, X86_DECODE_CMD_STI, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
{0xfc, X86_DECODE_CMD_CLD, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
{0xfd, X86_DECODE_CMD_STD, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
{0xfe, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm,
NULL, NULL, NULL, decode_incgroup2, RFLAGS_MASK_OSZAPC},
{0xff, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
NULL, NULL, NULL, decode_ffgroup, RFLAGS_MASK_OSZAPC},
};
struct decode_tbl _2op_inst[] = {
{0x0, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
NULL, NULL, NULL, decode_sldtgroup, RFLAGS_MASK_NONE},
{0x1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
NULL, NULL, NULL, decode_lidtgroup, RFLAGS_MASK_NONE},
{0x6, X86_DECODE_CMD_CLTS, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_TF},
{0x9, X86_DECODE_CMD_WBINVD, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x18, X86_DECODE_CMD_PREFETCH, 0, true,
NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
{0x1f, X86_DECODE_CMD_NOP, 0, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x20, X86_DECODE_CMD_MOV_FROM_CR, 0, true, decode_modrm_rm,
decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x21, X86_DECODE_CMD_MOV_FROM_DR, 0, true, decode_modrm_rm,
decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x22, X86_DECODE_CMD_MOV_TO_CR, 0, true, decode_modrm_reg,
decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x23, X86_DECODE_CMD_MOV_TO_DR, 0, true, decode_modrm_reg,
decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x30, X86_DECODE_CMD_WRMSR, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x31, X86_DECODE_CMD_RDTSC, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x32, X86_DECODE_CMD_RDMSR, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x40, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x41, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x42, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x43, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x44, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x45, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x46, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x47, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x48, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x49, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x4a, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x4b, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x4c, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x4d, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x4e, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x4f, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x77, X86_DECODE_CMD_EMMS, 0, false,
NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
{0x82, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x83, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x84, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x85, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x86, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x87, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x88, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x89, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x8a, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x8b, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x8c, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x8d, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x8e, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x8f, X86_DECODE_CMD_JXX, 0, false,
NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
{0x90, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x91, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x92, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x93, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x94, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x95, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x96, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x97, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x98, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x99, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9a, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9b, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9c, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9d, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9e, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0x9f, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xb0, X86_DECODE_CMD_CMPXCHG, 1, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xb1, X86_DECODE_CMD_CMPXCHG, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xb6, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xb7, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xb8, X86_DECODE_CMD_POPCNT, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xbe, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xbf, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa0, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
{0xa1, X86_DECODE_CMD_POP_SEG, 0, false, false,
NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
{0xa2, X86_DECODE_CMD_CPUID, 0, false,
NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xa3, X86_DECODE_CMD_BT, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_CF},
{0xa4, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg,
decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xa5, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg,
decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xa8, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
{0xa9, X86_DECODE_CMD_POP_SEG, 0, false, false,
NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
{0xab, X86_DECODE_CMD_BTS, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_CF},
{0xac, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg,
decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xad, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg,
decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xae, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
NULL, NULL, NULL, decode_aegroup, RFLAGS_MASK_NONE},
{0xaf, X86_DECODE_CMD_IMUL_2, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xb2, X86_DECODE_CMD_LSS, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_NONE},
{0xb3, X86_DECODE_CMD_BTR, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xba, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8,
NULL, NULL, decode_btgroup, RFLAGS_MASK_OSZAPC},
{0xbb, X86_DECODE_CMD_BTC, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xbc, X86_DECODE_CMD_BSF, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xbd, X86_DECODE_CMD_BSR, 0, true, decode_modrm_reg, decode_modrm_rm,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xc1, X86_DECODE_CMD_XADD, 0, true, decode_modrm_rm, decode_modrm_reg,
NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
{0xc7, X86_DECODE_CMD_CMPXCHG8B, 0, true, decode_modrm_rm,
NULL, NULL, NULL, NULL, RFLAGS_MASK_ZF},
{0xc8, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xc9, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xca, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xcb, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xcc, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xcd, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xce, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
{0xcf, X86_DECODE_CMD_BSWAP, 0, false,
NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
};
struct decode_x87_tbl invl_inst_x87 = {0x0, 0, 0, 0, 0, false, false, NULL,
NULL, decode_invalid, 0};
struct decode_x87_tbl _x87_inst[] = {
{0xd8, 0, 3, X86_DECODE_CMD_FADD, 10, false, false,
decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd8, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xd8, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0,
decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd8, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xd8, 4, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd8, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xd8, 5, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd8, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0,
decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd8, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xd8, 7, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd8, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0,
decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xd9, 0, 3, X86_DECODE_CMD_FLD, 10, false, false,
decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 0, 0, X86_DECODE_CMD_FLD, 4, false, false,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xd9, 1, 0, X86_DECODE_CMD_INVL, 10, false, false,
decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 2, 3, X86_DECODE_CMD_INVL, 10, false, false,
decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 2, 0, X86_DECODE_CMD_FST, 4, false, false,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 3, 3, X86_DECODE_CMD_INVL, 10, false, false,
decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 3, 0, X86_DECODE_CMD_FST, 4, false, true,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 4, 3, X86_DECODE_CMD_INVL, 10, false, false,
decode_x87_modrm_st0, NULL, decode_d9_4, RFLAGS_MASK_NONE},
{0xd9, 4, 0, X86_DECODE_CMD_INVL, 4, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 5, 3, X86_DECODE_CMD_FLDxx, 10, false, false, NULL, NULL, NULL,
RFLAGS_MASK_NONE},
{0xd9, 5, 0, X86_DECODE_CMD_FLDCW, 2, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 7, 3, X86_DECODE_CMD_FNSTCW, 2, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xd9, 7, 0, X86_DECODE_CMD_FNSTCW, 2, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xda, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xda, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xda, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xda, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xda, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xda, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xda, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
RFLAGS_MASK_NONE},
{0xda, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xda, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0,
decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xda, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0,
decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xda, 6, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
RFLAGS_MASK_NONE},
{0xda, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0,
decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xda, 7, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
RFLAGS_MASK_NONE},
{0xda, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0,
decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xdb, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdb, 0, 0, X86_DECODE_CMD_FLD, 4, false, false,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdb, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdb, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdb, 2, 0, X86_DECODE_CMD_FST, 4, false, false,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdb, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdb, 3, 0, X86_DECODE_CMD_FST, 4, false, true,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdb, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL,
decode_db_4, RFLAGS_MASK_NONE},
{0xdb, 4, 0, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
RFLAGS_MASK_NONE},
{0xdb, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdb, 5, 0, X86_DECODE_CMD_FLD, 10, false, false,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdb, 7, 0, X86_DECODE_CMD_FST, 10, false, true,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdc, 0, 3, X86_DECODE_CMD_FADD, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdc, 0, 0, X86_DECODE_CMD_FADD, 8, false, false,
decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xdc, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdc, 1, 0, X86_DECODE_CMD_FMUL, 8, false, false,
decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xdc, 4, 3, X86_DECODE_CMD_FSUB, 10, true, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdc, 4, 0, X86_DECODE_CMD_FSUB, 8, false, false,
decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xdc, 5, 3, X86_DECODE_CMD_FSUB, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdc, 5, 0, X86_DECODE_CMD_FSUB, 8, true, false,
decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xdc, 6, 3, X86_DECODE_CMD_FDIV, 10, true, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdc, 6, 0, X86_DECODE_CMD_FDIV, 8, false, false,
decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xdc, 7, 3, X86_DECODE_CMD_FDIV, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdc, 7, 0, X86_DECODE_CMD_FDIV, 8, true, false,
decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
{0xdd, 0, 0, X86_DECODE_CMD_FLD, 8, false, false,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdd, 2, 3, X86_DECODE_CMD_FST, 10, false, false,
decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 2, 0, X86_DECODE_CMD_FST, 8, false, false,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 3, 3, X86_DECODE_CMD_FST, 10, false, true,
decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 3, 0, X86_DECODE_CMD_FST, 8, false, true,
decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 4, 3, X86_DECODE_CMD_FUCOM, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdd, 4, 0, X86_DECODE_CMD_FRSTOR, 8, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdd, 7, 0, X86_DECODE_CMD_FNSTSW, 0, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xdd, 7, 3, X86_DECODE_CMD_FNSTSW, 0, false, false,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xde, 0, 3, X86_DECODE_CMD_FADD, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xde, 0, 0, X86_DECODE_CMD_FADD, 2, false, false,
decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xde, 1, 3, X86_DECODE_CMD_FMUL, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xde, 1, 0, X86_DECODE_CMD_FMUL, 2, false, false,
decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xde, 4, 3, X86_DECODE_CMD_FSUB, 10, true, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xde, 4, 0, X86_DECODE_CMD_FSUB, 2, false, false,
decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xde, 5, 3, X86_DECODE_CMD_FSUB, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xde, 5, 0, X86_DECODE_CMD_FSUB, 2, true, false,
decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xde, 6, 3, X86_DECODE_CMD_FDIV, 10, true, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xde, 6, 0, X86_DECODE_CMD_FDIV, 2, false, false,
decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xde, 7, 3, X86_DECODE_CMD_FDIV, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xde, 7, 0, X86_DECODE_CMD_FDIV, 2, true, false,
decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
{0xdf, 0, 0, X86_DECODE_CMD_FLD, 2, false, false,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdf, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdf, 2, 3, X86_DECODE_CMD_FST, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdf, 2, 0, X86_DECODE_CMD_FST, 2, false, false,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdf, 3, 3, X86_DECODE_CMD_FST, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdf, 3, 0, X86_DECODE_CMD_FST, 2, false, true,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdf, 4, 3, X86_DECODE_CMD_FNSTSW, 2, false, true,
decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
{0xdf, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, true,
decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
{0xdf, 5, 0, X86_DECODE_CMD_FLD, 8, false, false,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
{0xdf, 7, 0, X86_DECODE_CMD_FST, 8, false, true,
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
};
void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
target_ulong ptr = 0;
X86Seg seg = R_DS;
if (!decode->modrm.mod && 6 == decode->modrm.rm) {
ptr = decode->displacement;
goto calc_addr;
}
if (decode->displacement_size) {
ptr = sign(decode->displacement, decode->displacement_size);
}
switch (decode->modrm.rm) {
case 0:
ptr += BX(env) + SI(env);
break;
case 1:
ptr += BX(env) + DI(env);
break;
case 2:
ptr += BP(env) + SI(env);
seg = R_SS;
break;
case 3:
ptr += BP(env) + DI(env);
seg = R_SS;
break;
case 4:
ptr += SI(env);
break;
case 5:
ptr += DI(env);
break;
case 6:
ptr += BP(env);
seg = R_SS;
break;
case 7:
ptr += BX(env);
break;
}
calc_addr:
if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = (uint16_t)ptr;
} else {
op->ptr = decode_linear_addr(env, decode, (uint16_t)ptr, seg);
}
}
target_ulong get_reg_ref(CPUX86State *env, int reg, int rex, int is_extended,
int size)
{
target_ulong ptr = 0;
int which = 0;
if (is_extended) {
reg |= R_R8;
}
switch (size) {
case 1:
if (is_extended || reg < 4 || rex) {
which = 1;
ptr = (target_ulong)&RL(env, reg);
} else {
which = 2;
ptr = (target_ulong)&RH(env, reg - 4);
}
break;
default:
which = 3;
ptr = (target_ulong)&RRX(env, reg);
break;
}
return ptr;
}
target_ulong get_reg_val(CPUX86State *env, int reg, int rex, int is_extended,
int size)
{
target_ulong val = 0;
memcpy(&val, (void *)get_reg_ref(env, reg, rex, is_extended, size), size);
return val;
}
static target_ulong get_sib_val(CPUX86State *env, struct x86_decode *decode,
X86Seg *sel)
{
target_ulong base = 0;
target_ulong scaled_index = 0;
int addr_size = decode->addressing_size;
int base_reg = decode->sib.base;
int index_reg = decode->sib.index;
*sel = R_DS;
if (decode->modrm.mod || base_reg != R_EBP) {
if (decode->rex.b) {
base_reg |= R_R8;
}
if (base_reg == R_ESP || base_reg == R_EBP) {
*sel = R_SS;
}
base = get_reg_val(env, decode->sib.base, decode->rex.rex,
decode->rex.b, addr_size);
}
if (decode->rex.x) {
index_reg |= R_R8;
}
if (index_reg != R_ESP) {
scaled_index = get_reg_val(env, index_reg, decode->rex.rex,
decode->rex.x, addr_size) <<
decode->sib.scale;
}
return base + scaled_index;
}
void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
X86Seg seg = R_DS;
target_ulong ptr = 0;
int addr_size = decode->addressing_size;
if (decode->displacement_size) {
ptr = sign(decode->displacement, decode->displacement_size);
}
if (4 == decode->modrm.rm) {
ptr += get_sib_val(env, decode, &seg);
} else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
if (x86_is_long_mode(ENV_GET_CPU(env))) {
ptr += RIP(env) + decode->len;
} else {
ptr = decode->displacement;
}
} else {
if (decode->modrm.rm == R_EBP || decode->modrm.rm == R_ESP) {
seg = R_SS;
}
ptr += get_reg_val(env, decode->modrm.rm, decode->rex.rex,
decode->rex.b, addr_size);
}
if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = (uint32_t)ptr;
} else {
op->ptr = decode_linear_addr(env, decode, (uint32_t)ptr, seg);
}
}
void calc_modrm_operand64(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
X86Seg seg = R_DS;
int32_t offset = 0;
int mod = decode->modrm.mod;
int rm = decode->modrm.rm;
target_ulong ptr;
int src = decode->modrm.rm;
if (decode->displacement_size) {
offset = sign(decode->displacement, decode->displacement_size);
}
if (4 == rm) {
ptr = get_sib_val(env, decode, &seg) + offset;
} else if (0 == mod && 5 == rm) {
ptr = RIP(env) + decode->len + (int32_t) offset;
} else {
ptr = get_reg_val(env, src, decode->rex.rex, decode->rex.b, 8) +
(int64_t) offset;
}
if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = ptr;
} else {
op->ptr = decode_linear_addr(env, decode, ptr, seg);
}
}
void calc_modrm_operand(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
if (3 == decode->modrm.mod) {
op->reg = decode->modrm.reg;
op->type = X86_VAR_REG;
op->ptr = get_reg_ref(env, decode->modrm.rm, decode->rex.rex,
decode->rex.b, decode->operand_size);
return;
}
switch (decode->addressing_size) {
case 2:
calc_modrm_operand16(env, decode, op);
break;
case 4:
calc_modrm_operand32(env, decode, op);
break;
case 8:
calc_modrm_operand64(env, decode, op);
break;
default:
VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
break;
}
}
static void decode_prefix(CPUX86State *env, struct x86_decode *decode)
{
while (1) {
uint8_t byte = decode_byte(env, decode);
switch (byte) {
case PREFIX_LOCK:
decode->lock = byte;
break;
case PREFIX_REPN:
case PREFIX_REP:
decode->rep = byte;
break;
case PREFIX_CS_SEG_OVEERIDE:
case PREFIX_SS_SEG_OVEERIDE:
case PREFIX_DS_SEG_OVEERIDE:
case PREFIX_ES_SEG_OVEERIDE:
case PREFIX_FS_SEG_OVEERIDE:
case PREFIX_GS_SEG_OVEERIDE:
decode->segment_override = byte;
break;
case PREFIX_OP_SIZE_OVERRIDE:
decode->op_size_override = byte;
break;
case PREFIX_ADDR_SIZE_OVERRIDE:
decode->addr_size_override = byte;
break;
case PREFIX_REX ... (PREFIX_REX + 0xf):
if (x86_is_long_mode(ENV_GET_CPU(env))) {
decode->rex.rex = byte;
break;
}
/* fall through when not in long mode */
default:
decode->len--;
return;
}
}
}
void set_addressing_size(CPUX86State *env, struct x86_decode *decode)
{
decode->addressing_size = -1;
if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) {
if (decode->addr_size_override) {
decode->addressing_size = 4;
} else {
decode->addressing_size = 2;
}
} else if (!x86_is_long_mode(ENV_GET_CPU(env))) {
/* protected */
struct vmx_segment cs;
vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS);
/* check db */
if ((cs.ar >> 14) & 1) {
if (decode->addr_size_override) {
decode->addressing_size = 2;
} else {
decode->addressing_size = 4;
}
} else {
if (decode->addr_size_override) {
decode->addressing_size = 4;
} else {
decode->addressing_size = 2;
}
}
} else {
/* long */
if (decode->addr_size_override) {
decode->addressing_size = 4;
} else {
decode->addressing_size = 8;
}
}
}
void set_operand_size(CPUX86State *env, struct x86_decode *decode)
{
decode->operand_size = -1;
if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) {
if (decode->op_size_override) {
decode->operand_size = 4;
} else {
decode->operand_size = 2;
}
} else if (!x86_is_long_mode(ENV_GET_CPU(env))) {
/* protected */
struct vmx_segment cs;
vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS);
/* check db */
if ((cs.ar >> 14) & 1) {
if (decode->op_size_override) {
decode->operand_size = 2;
} else{
decode->operand_size = 4;
}
} else {
if (decode->op_size_override) {
decode->operand_size = 4;
} else {
decode->operand_size = 2;
}
}
} else {
/* long */
if (decode->op_size_override) {
decode->operand_size = 2;
} else {
decode->operand_size = 4;
}
if (decode->rex.w) {
decode->operand_size = 8;
}
}
}
static void decode_sib(CPUX86State *env, struct x86_decode *decode)
{
if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) &&
(decode->addressing_size != 2)) {
decode->sib.sib = decode_byte(env, decode);
decode->sib_present = true;
}
}
/* 16 bit modrm */
int disp16_tbl[4][8] = {
{0, 0, 0, 0, 0, 0, 2, 0},
{1, 1, 1, 1, 1, 1, 1, 1},
{2, 2, 2, 2, 2, 2, 2, 2},
{0, 0, 0, 0, 0, 0, 0, 0}
};
/* 32/64-bit modrm */
int disp32_tbl[4][8] = {
{0, 0, 0, 0, -1, 4, 0, 0},
{1, 1, 1, 1, 1, 1, 1, 1},
{4, 4, 4, 4, 4, 4, 4, 4},
{0, 0, 0, 0, 0, 0, 0, 0}
};
static inline void decode_displacement(CPUX86State *env, struct x86_decode *decode)
{
int addressing_size = decode->addressing_size;
int mod = decode->modrm.mod;
int rm = decode->modrm.rm;
decode->displacement_size = 0;
switch (addressing_size) {
case 2:
decode->displacement_size = disp16_tbl[mod][rm];
if (decode->displacement_size) {
decode->displacement = (uint16_t)decode_bytes(env, decode,
decode->displacement_size);
}
break;
case 4:
case 8:
if (-1 == disp32_tbl[mod][rm]) {
if (5 == decode->sib.base) {
decode->displacement_size = 4;
}
} else {
decode->displacement_size = disp32_tbl[mod][rm];
}
if (decode->displacement_size) {
decode->displacement = (uint32_t)decode_bytes(env, decode,
decode->displacement_size);
}
break;
}
}
static inline void decode_modrm(CPUX86State *env, struct x86_decode *decode)
{
decode->modrm.modrm = decode_byte(env, decode);
decode->is_modrm = true;
decode_sib(env, decode);
decode_displacement(env, decode);
}
static inline void decode_opcode_general(CPUX86State *env,
struct x86_decode *decode,
uint8_t opcode,
struct decode_tbl *inst_decoder)
{
decode->cmd = inst_decoder->cmd;
if (inst_decoder->operand_size) {
decode->operand_size = inst_decoder->operand_size;
}
decode->flags_mask = inst_decoder->flags_mask;
if (inst_decoder->is_modrm) {
decode_modrm(env, decode);
}
if (inst_decoder->decode_op1) {
inst_decoder->decode_op1(env, decode, &decode->op[0]);
}
if (inst_decoder->decode_op2) {
inst_decoder->decode_op2(env, decode, &decode->op[1]);
}
if (inst_decoder->decode_op3) {
inst_decoder->decode_op3(env, decode, &decode->op[2]);
}
if (inst_decoder->decode_op4) {
inst_decoder->decode_op4(env, decode, &decode->op[3]);
}
if (inst_decoder->decode_postfix) {
inst_decoder->decode_postfix(env, decode);
}
}
static inline void decode_opcode_1(CPUX86State *env, struct x86_decode *decode,
uint8_t opcode)
{
struct decode_tbl *inst_decoder = &_decode_tbl1[opcode];
decode_opcode_general(env, decode, opcode, inst_decoder);
}
static inline void decode_opcode_2(CPUX86State *env, struct x86_decode *decode,
uint8_t opcode)
{
struct decode_tbl *inst_decoder = &_decode_tbl2[opcode];
decode_opcode_general(env, decode, opcode, inst_decoder);
}
static void decode_opcodes(CPUX86State *env, struct x86_decode *decode)
{
uint8_t opcode;
opcode = decode_byte(env, decode);
decode->opcode[decode->opcode_len++] = opcode;
if (opcode != OPCODE_ESCAPE) {
decode_opcode_1(env, decode, opcode);
} else {
opcode = decode_byte(env, decode);
decode->opcode[decode->opcode_len++] = opcode;
decode_opcode_2(env, decode, opcode);
}
}
uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode)
{
memset(decode, 0, sizeof(*decode));
decode_prefix(env, decode);
set_addressing_size(env, decode);
set_operand_size(env, decode);
decode_opcodes(env, decode);
return decode->len;
}
void init_decoder()
{
int i;
for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++) {
memcpy(_decode_tbl1, &invl_inst, sizeof(invl_inst));
}
for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++) {
memcpy(_decode_tbl2, &invl_inst, sizeof(invl_inst));
}
for (i = 0; i < ARRAY_SIZE(_decode_tbl3); i++) {
memcpy(_decode_tbl3, &invl_inst, sizeof(invl_inst_x87));
}
for (i = 0; i < ARRAY_SIZE(_1op_inst); i++) {
_decode_tbl1[_1op_inst[i].opcode] = _1op_inst[i];
}
for (i = 0; i < ARRAY_SIZE(_2op_inst); i++) {
_decode_tbl2[_2op_inst[i].opcode] = _2op_inst[i];
}
for (i = 0; i < ARRAY_SIZE(_x87_inst); i++) {
int index = ((_x87_inst[i].opcode & 0xf) << 4) |
((_x87_inst[i].modrm_mod & 1) << 3) |
_x87_inst[i].modrm_reg;
_decode_tbl3[index] = _x87_inst[i];
}
}
const char *decode_cmd_to_string(enum x86_decode_cmd cmd)
{
static const char *cmds[] = {"INVL", "PUSH", "PUSH_SEG", "POP", "POP_SEG",
"MOV", "MOVSX", "MOVZX", "CALL_NEAR", "CALL_NEAR_ABS_INDIRECT",
"CALL_FAR_ABS_INDIRECT", "CMD_CALL_FAR", "RET_NEAR", "RET_FAR", "ADD",
"OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP", "INC", "DEC", "TST",
"NOT", "NEG", "JMP_NEAR", "JMP_NEAR_ABS_INDIRECT", "JMP_FAR",
"JMP_FAR_ABS_INDIRECT", "LEA", "JXX", "JCXZ", "SETXX", "MOV_TO_SEG",
"MOV_FROM_SEG", "CLI", "STI", "CLD", "STD", "STC", "CLC", "OUT", "IN",
"INS", "OUTS", "LIDT", "SIDT", "LGDT", "SGDT", "SMSW", "LMSW",
"RDTSCP", "INVLPG", "MOV_TO_CR", "MOV_FROM_CR", "MOV_TO_DR",
"MOV_FROM_DR", "PUSHF", "POPF", "CPUID", "ROL", "ROR", "RCL", "RCR",
"SHL", "SAL", "SHR", "SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL",
"IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS", "LODS", "STOS",
"BSWAP", "XCHG", "RDTSC", "RDMSR", "WRMSR", "ENTER", "LEAVE", "BT",
"BTS", "BTC", "BTR", "BSF", "BSR", "IRET", "INT", "POPA", "PUSHA",
"CWD", "CBW", "DAS", "AAD", "AAM", "AAS", "LOOP", "SLDT", "STR", "LLDT",
"LTR", "VERR", "VERW", "SAHF", "LAHF", "WBINVD", "LDS", "LSS", "LES",
"LGS", "LFS", "CMC", "XLAT", "NOP", "CMOV", "CLTS", "XADD", "HLT",
"CMPXCHG8B", "CMPXCHG", "POPCNT", "FNINIT", "FLD", "FLDxx", "FNSTCW",
"FNSTSW", "FNSETPM", "FSAVE", "FRSTOR", "FXSAVE", "FXRSTOR", "FDIV",
"FMUL", "FSUB", "FADD", "EMMS", "MFENCE", "SFENCE", "LFENCE",
"PREFETCH", "FST", "FABS", "FUCOM", "FUCOMI", "FLDCW",
"FXCH", "FCHS", "FCMOV", "FRNDINT", "FXAM", "LAST"};
return cmds[cmd];
}
target_ulong decode_linear_addr(CPUX86State *env, struct x86_decode *decode,
target_ulong addr, X86Seg seg)
{
switch (decode->segment_override) {
case PREFIX_CS_SEG_OVEERIDE:
seg = R_CS;
break;
case PREFIX_SS_SEG_OVEERIDE:
seg = R_SS;
break;
case PREFIX_DS_SEG_OVEERIDE:
seg = R_DS;
break;
case PREFIX_ES_SEG_OVEERIDE:
seg = R_ES;
break;
case PREFIX_FS_SEG_OVEERIDE:
seg = R_FS;
break;
case PREFIX_GS_SEG_OVEERIDE:
seg = R_GS;
break;
default:
break;
}
return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_size, seg);
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/timer/twl92230.c | /*
* TI TWL92230C energy-management companion device for the OMAP24xx.
* Aka. Menelaus (N4200 MENELAUS1_V2.2)
*
* Copyright (C) 2008 Nokia Corporation
* Written by <NAME> <<EMAIL>>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "qemu/timer.h"
#include "hw/i2c/i2c.h"
#include "sysemu/sysemu.h"
#include "ui/console.h"
#include "qemu/bcd.h"
#define VERBOSE 1
#define TYPE_TWL92230 "twl92230"
#define TWL92230(obj) OBJECT_CHECK(MenelausState, (obj), TYPE_TWL92230)
typedef struct MenelausState {
I2CSlave parent_obj;
int firstbyte;
uint8_t reg;
uint8_t vcore[5];
uint8_t dcdc[3];
uint8_t ldo[8];
uint8_t sleep[2];
uint8_t osc;
uint8_t detect;
uint16_t mask;
uint16_t status;
uint8_t dir;
uint8_t inputs;
uint8_t outputs;
uint8_t bbsms;
uint8_t pull[4];
uint8_t mmc_ctrl[3];
uint8_t mmc_debounce;
struct {
uint8_t ctrl;
uint16_t comp;
QEMUTimer *hz_tm;
int64_t next;
struct tm tm;
struct tm new;
struct tm alm;
int sec_offset;
int alm_sec;
int next_comp;
} rtc;
uint16_t rtc_next_vmstate;
qemu_irq out[4];
uint8_t pwrbtn_state;
} MenelausState;
static inline void menelaus_update(MenelausState *s)
{
qemu_set_irq(s->out[3], s->status & ~s->mask);
}
static inline void menelaus_rtc_start(MenelausState *s)
{
s->rtc.next += qemu_clock_get_ms(rtc_clock);
timer_mod(s->rtc.hz_tm, s->rtc.next);
}
static inline void menelaus_rtc_stop(MenelausState *s)
{
timer_del(s->rtc.hz_tm);
s->rtc.next -= qemu_clock_get_ms(rtc_clock);
if (s->rtc.next < 1)
s->rtc.next = 1;
}
static void menelaus_rtc_update(MenelausState *s)
{
qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
}
static void menelaus_alm_update(MenelausState *s)
{
if ((s->rtc.ctrl & 3) == 3)
s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
}
static void menelaus_rtc_hz(void *opaque)
{
MenelausState *s = (MenelausState *) opaque;
s->rtc.next_comp --;
s->rtc.alm_sec --;
s->rtc.next += 1000;
timer_mod(s->rtc.hz_tm, s->rtc.next);
if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
menelaus_rtc_update(s);
if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
s->status |= 1 << 8; /* RTCTMR */
else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
s->status |= 1 << 8; /* RTCTMR */
else if (!s->rtc.tm.tm_hour)
s->status |= 1 << 8; /* RTCTMR */
} else
s->status |= 1 << 8; /* RTCTMR */
if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
if (s->rtc.alm_sec == 0)
s->status |= 1 << 9; /* RTCALM */
/* TODO: wake-up */
}
if (s->rtc.next_comp <= 0) {
s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
s->rtc.next_comp = 3600;
}
menelaus_update(s);
}
static void menelaus_reset(I2CSlave *i2c)
{
MenelausState *s = TWL92230(i2c);
s->reg = 0x00;
s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
s->vcore[1] = 0x05;
s->vcore[2] = 0x02;
s->vcore[3] = 0x0c;
s->vcore[4] = 0x03;
s->dcdc[0] = 0x33; /* Depends on wiring */
s->dcdc[1] = 0x03;
s->dcdc[2] = 0x00;
s->ldo[0] = 0x95;
s->ldo[1] = 0x7e;
s->ldo[2] = 0x00;
s->ldo[3] = 0x00; /* Depends on wiring */
s->ldo[4] = 0x03; /* Depends on wiring */
s->ldo[5] = 0x00;
s->ldo[6] = 0x00;
s->ldo[7] = 0x00;
s->sleep[0] = 0x00;
s->sleep[1] = 0x00;
s->osc = 0x01;
s->detect = 0x09;
s->mask = 0x0fff;
s->status = 0;
s->dir = 0x07;
s->outputs = 0x00;
s->bbsms = 0x00;
s->pull[0] = 0x00;
s->pull[1] = 0x00;
s->pull[2] = 0x00;
s->pull[3] = 0x00;
s->mmc_ctrl[0] = 0x03;
s->mmc_ctrl[1] = 0xc0;
s->mmc_ctrl[2] = 0x00;
s->mmc_debounce = 0x05;
if (s->rtc.ctrl & 1)
menelaus_rtc_stop(s);
s->rtc.ctrl = 0x00;
s->rtc.comp = 0x0000;
s->rtc.next = 1000;
s->rtc.sec_offset = 0;
s->rtc.next_comp = 1800;
s->rtc.alm_sec = 1800;
s->rtc.alm.tm_sec = 0x00;
s->rtc.alm.tm_min = 0x00;
s->rtc.alm.tm_hour = 0x00;
s->rtc.alm.tm_mday = 0x01;
s->rtc.alm.tm_mon = 0x00;
s->rtc.alm.tm_year = 2004;
menelaus_update(s);
}
static void menelaus_gpio_set(void *opaque, int line, int level)
{
MenelausState *s = (MenelausState *) opaque;
if (line < 3) {
/* No interrupt generated */
s->inputs &= ~(1 << line);
s->inputs |= level << line;
return;
}
if (!s->pwrbtn_state && level) {
s->status |= 1 << 11; /* PSHBTN */
menelaus_update(s);
}
s->pwrbtn_state = level;
}
#define MENELAUS_REV 0x01
#define MENELAUS_VCORE_CTRL1 0x02
#define MENELAUS_VCORE_CTRL2 0x03
#define MENELAUS_VCORE_CTRL3 0x04
#define MENELAUS_VCORE_CTRL4 0x05
#define MENELAUS_VCORE_CTRL5 0x06
#define MENELAUS_DCDC_CTRL1 0x07
#define MENELAUS_DCDC_CTRL2 0x08
#define MENELAUS_DCDC_CTRL3 0x09
#define MENELAUS_LDO_CTRL1 0x0a
#define MENELAUS_LDO_CTRL2 0x0b
#define MENELAUS_LDO_CTRL3 0x0c
#define MENELAUS_LDO_CTRL4 0x0d
#define MENELAUS_LDO_CTRL5 0x0e
#define MENELAUS_LDO_CTRL6 0x0f
#define MENELAUS_LDO_CTRL7 0x10
#define MENELAUS_LDO_CTRL8 0x11
#define MENELAUS_SLEEP_CTRL1 0x12
#define MENELAUS_SLEEP_CTRL2 0x13
#define MENELAUS_DEVICE_OFF 0x14
#define MENELAUS_OSC_CTRL 0x15
#define MENELAUS_DETECT_CTRL 0x16
#define MENELAUS_INT_MASK1 0x17
#define MENELAUS_INT_MASK2 0x18
#define MENELAUS_INT_STATUS1 0x19
#define MENELAUS_INT_STATUS2 0x1a
#define MENELAUS_INT_ACK1 0x1b
#define MENELAUS_INT_ACK2 0x1c
#define MENELAUS_GPIO_CTRL 0x1d
#define MENELAUS_GPIO_IN 0x1e
#define MENELAUS_GPIO_OUT 0x1f
#define MENELAUS_BBSMS 0x20
#define MENELAUS_RTC_CTRL 0x21
#define MENELAUS_RTC_UPDATE 0x22
#define MENELAUS_RTC_SEC 0x23
#define MENELAUS_RTC_MIN 0x24
#define MENELAUS_RTC_HR 0x25
#define MENELAUS_RTC_DAY 0x26
#define MENELAUS_RTC_MON 0x27
#define MENELAUS_RTC_YR 0x28
#define MENELAUS_RTC_WKDAY 0x29
#define MENELAUS_RTC_AL_SEC 0x2a
#define MENELAUS_RTC_AL_MIN 0x2b
#define MENELAUS_RTC_AL_HR 0x2c
#define MENELAUS_RTC_AL_DAY 0x2d
#define MENELAUS_RTC_AL_MON 0x2e
#define MENELAUS_RTC_AL_YR 0x2f
#define MENELAUS_RTC_COMP_MSB 0x30
#define MENELAUS_RTC_COMP_LSB 0x31
#define MENELAUS_S1_PULL_EN 0x32
#define MENELAUS_S1_PULL_DIR 0x33
#define MENELAUS_S2_PULL_EN 0x34
#define MENELAUS_S2_PULL_DIR 0x35
#define MENELAUS_MCT_CTRL1 0x36
#define MENELAUS_MCT_CTRL2 0x37
#define MENELAUS_MCT_CTRL3 0x38
#define MENELAUS_MCT_PIN_ST 0x39
#define MENELAUS_DEBOUNCE1 0x3a
static uint8_t menelaus_read(void *opaque, uint8_t addr)
{
MenelausState *s = (MenelausState *) opaque;
int reg = 0;
switch (addr) {
case MENELAUS_REV:
return 0x22;
case MENELAUS_VCORE_CTRL5: reg ++;
case MENELAUS_VCORE_CTRL4: reg ++;
case MENELAUS_VCORE_CTRL3: reg ++;
case MENELAUS_VCORE_CTRL2: reg ++;
case MENELAUS_VCORE_CTRL1:
return s->vcore[reg];
case MENELAUS_DCDC_CTRL3: reg ++;
case MENELAUS_DCDC_CTRL2: reg ++;
case MENELAUS_DCDC_CTRL1:
return s->dcdc[reg];
case MENELAUS_LDO_CTRL8: reg ++;
case MENELAUS_LDO_CTRL7: reg ++;
case MENELAUS_LDO_CTRL6: reg ++;
case MENELAUS_LDO_CTRL5: reg ++;
case MENELAUS_LDO_CTRL4: reg ++;
case MENELAUS_LDO_CTRL3: reg ++;
case MENELAUS_LDO_CTRL2: reg ++;
case MENELAUS_LDO_CTRL1:
return s->ldo[reg];
case MENELAUS_SLEEP_CTRL2: reg ++;
case MENELAUS_SLEEP_CTRL1:
return s->sleep[reg];
case MENELAUS_DEVICE_OFF:
return 0;
case MENELAUS_OSC_CTRL:
return s->osc | (1 << 7); /* CLK32K_GOOD */
case MENELAUS_DETECT_CTRL:
return s->detect;
case MENELAUS_INT_MASK1:
return (s->mask >> 0) & 0xff;
case MENELAUS_INT_MASK2:
return (s->mask >> 8) & 0xff;
case MENELAUS_INT_STATUS1:
return (s->status >> 0) & 0xff;
case MENELAUS_INT_STATUS2:
return (s->status >> 8) & 0xff;
case MENELAUS_INT_ACK1:
case MENELAUS_INT_ACK2:
return 0;
case MENELAUS_GPIO_CTRL:
return s->dir;
case MENELAUS_GPIO_IN:
return s->inputs | (~s->dir & s->outputs);
case MENELAUS_GPIO_OUT:
return s->outputs;
case MENELAUS_BBSMS:
return s->bbsms;
case MENELAUS_RTC_CTRL:
return s->rtc.ctrl;
case MENELAUS_RTC_UPDATE:
return 0x00;
case MENELAUS_RTC_SEC:
menelaus_rtc_update(s);
return to_bcd(s->rtc.tm.tm_sec);
case MENELAUS_RTC_MIN:
menelaus_rtc_update(s);
return to_bcd(s->rtc.tm.tm_min);
case MENELAUS_RTC_HR:
menelaus_rtc_update(s);
if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
(!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
else
return to_bcd(s->rtc.tm.tm_hour);
case MENELAUS_RTC_DAY:
menelaus_rtc_update(s);
return to_bcd(s->rtc.tm.tm_mday);
case MENELAUS_RTC_MON:
menelaus_rtc_update(s);
return to_bcd(s->rtc.tm.tm_mon + 1);
case MENELAUS_RTC_YR:
menelaus_rtc_update(s);
return to_bcd(s->rtc.tm.tm_year - 2000);
case MENELAUS_RTC_WKDAY:
menelaus_rtc_update(s);
return to_bcd(s->rtc.tm.tm_wday);
case MENELAUS_RTC_AL_SEC:
return to_bcd(s->rtc.alm.tm_sec);
case MENELAUS_RTC_AL_MIN:
return to_bcd(s->rtc.alm.tm_min);
case MENELAUS_RTC_AL_HR:
if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
(!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
else
return to_bcd(s->rtc.alm.tm_hour);
case MENELAUS_RTC_AL_DAY:
return to_bcd(s->rtc.alm.tm_mday);
case MENELAUS_RTC_AL_MON:
return to_bcd(s->rtc.alm.tm_mon + 1);
case MENELAUS_RTC_AL_YR:
return to_bcd(s->rtc.alm.tm_year - 2000);
case MENELAUS_RTC_COMP_MSB:
return (s->rtc.comp >> 8) & 0xff;
case MENELAUS_RTC_COMP_LSB:
return (s->rtc.comp >> 0) & 0xff;
case MENELAUS_S1_PULL_EN:
return s->pull[0];
case MENELAUS_S1_PULL_DIR:
return s->pull[1];
case MENELAUS_S2_PULL_EN:
return s->pull[2];
case MENELAUS_S2_PULL_DIR:
return s->pull[3];
case MENELAUS_MCT_CTRL3: reg ++;
case MENELAUS_MCT_CTRL2: reg ++;
case MENELAUS_MCT_CTRL1:
return s->mmc_ctrl[reg];
case MENELAUS_MCT_PIN_ST:
/* TODO: return the real Card Detect */
return 0;
case MENELAUS_DEBOUNCE1:
return s->mmc_debounce;
default:
#ifdef VERBOSE
printf("%s: unknown register %02x\n", __func__, addr);
#endif
break;
}
return 0;
}
static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
{
MenelausState *s = (MenelausState *) opaque;
int line;
int reg = 0;
struct tm tm;
switch (addr) {
case MENELAUS_VCORE_CTRL1:
s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
break;
case MENELAUS_VCORE_CTRL2:
s->vcore[1] = value;
break;
case MENELAUS_VCORE_CTRL3:
s->vcore[2] = MIN(value & 0x1f, 0x12);
break;
case MENELAUS_VCORE_CTRL4:
s->vcore[3] = MIN(value & 0x1f, 0x12);
break;
case MENELAUS_VCORE_CTRL5:
s->vcore[4] = value & 3;
/* XXX
* auto set to 3 on M_Active, nRESWARM
* auto set to 0 on M_WaitOn, M_Backup
*/
break;
case MENELAUS_DCDC_CTRL1:
s->dcdc[0] = value & 0x3f;
break;
case MENELAUS_DCDC_CTRL2:
s->dcdc[1] = value & 0x07;
/* XXX
* auto set to 3 on M_Active, nRESWARM
* auto set to 0 on M_WaitOn, M_Backup
*/
break;
case MENELAUS_DCDC_CTRL3:
s->dcdc[2] = value & 0x07;
break;
case MENELAUS_LDO_CTRL1:
s->ldo[0] = value;
break;
case MENELAUS_LDO_CTRL2:
s->ldo[1] = value & 0x7f;
/* XXX
* auto set to 0x7e on M_WaitOn, M_Backup
*/
break;
case MENELAUS_LDO_CTRL3:
s->ldo[2] = value & 3;
/* XXX
* auto set to 3 on M_Active, nRESWARM
* auto set to 0 on M_WaitOn, M_Backup
*/
break;
case MENELAUS_LDO_CTRL4:
s->ldo[3] = value & 3;
/* XXX
* auto set to 3 on M_Active, nRESWARM
* auto set to 0 on M_WaitOn, M_Backup
*/
break;
case MENELAUS_LDO_CTRL5:
s->ldo[4] = value & 3;
/* XXX
* auto set to 3 on M_Active, nRESWARM
* auto set to 0 on M_WaitOn, M_Backup
*/
break;
case MENELAUS_LDO_CTRL6:
s->ldo[5] = value & 3;
break;
case MENELAUS_LDO_CTRL7:
s->ldo[6] = value & 3;
break;
case MENELAUS_LDO_CTRL8:
s->ldo[7] = value & 3;
break;
case MENELAUS_SLEEP_CTRL2: reg ++;
case MENELAUS_SLEEP_CTRL1:
s->sleep[reg] = value;
break;
case MENELAUS_DEVICE_OFF:
if (value & 1) {
menelaus_reset(I2C_SLAVE(s));
}
break;
case MENELAUS_OSC_CTRL:
s->osc = value & 7;
break;
case MENELAUS_DETECT_CTRL:
s->detect = value & 0x7f;
break;
case MENELAUS_INT_MASK1:
s->mask &= 0xf00;
s->mask |= value << 0;
menelaus_update(s);
break;
case MENELAUS_INT_MASK2:
s->mask &= 0x0ff;
s->mask |= value << 8;
menelaus_update(s);
break;
case MENELAUS_INT_ACK1:
s->status &= ~(((uint16_t) value) << 0);
menelaus_update(s);
break;
case MENELAUS_INT_ACK2:
s->status &= ~(((uint16_t) value) << 8);
menelaus_update(s);
break;
case MENELAUS_GPIO_CTRL:
for (line = 0; line < 3; line ++) {
if (((s->dir ^ value) >> line) & 1) {
qemu_set_irq(s->out[line],
((s->outputs & ~s->dir) >> line) & 1);
}
}
s->dir = value & 0x67;
break;
case MENELAUS_GPIO_OUT:
for (line = 0; line < 3; line ++) {
if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
}
}
s->outputs = value & 0x07;
break;
case MENELAUS_BBSMS:
s->bbsms = 0x0d;
break;
case MENELAUS_RTC_CTRL:
if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
if (value & 1)
menelaus_rtc_start(s);
else
menelaus_rtc_stop(s);
}
s->rtc.ctrl = value & 0x1f;
menelaus_alm_update(s);
break;
case MENELAUS_RTC_UPDATE:
menelaus_rtc_update(s);
memcpy(&tm, &s->rtc.tm, sizeof(tm));
switch (value & 0xf) {
case 0:
break;
case 1:
tm.tm_sec = s->rtc.new.tm_sec;
break;
case 2:
tm.tm_min = s->rtc.new.tm_min;
break;
case 3:
if (s->rtc.new.tm_hour > 23)
goto rtc_badness;
tm.tm_hour = s->rtc.new.tm_hour;
break;
case 4:
if (s->rtc.new.tm_mday < 1)
goto rtc_badness;
/* TODO check range */
tm.tm_mday = s->rtc.new.tm_mday;
break;
case 5:
if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
goto rtc_badness;
tm.tm_mon = s->rtc.new.tm_mon;
break;
case 6:
tm.tm_year = s->rtc.new.tm_year;
break;
case 7:
/* TODO set .tm_mday instead */
tm.tm_wday = s->rtc.new.tm_wday;
break;
case 8:
if (s->rtc.new.tm_hour > 23)
goto rtc_badness;
if (s->rtc.new.tm_mday < 1)
goto rtc_badness;
if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
goto rtc_badness;
tm.tm_sec = s->rtc.new.tm_sec;
tm.tm_min = s->rtc.new.tm_min;
tm.tm_hour = s->rtc.new.tm_hour;
tm.tm_mday = s->rtc.new.tm_mday;
tm.tm_mon = s->rtc.new.tm_mon;
tm.tm_year = s->rtc.new.tm_year;
break;
rtc_badness:
default:
fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
__func__, value);
s->status |= 1 << 10; /* RTCERR */
menelaus_update(s);
}
s->rtc.sec_offset = qemu_timedate_diff(&tm);
break;
case MENELAUS_RTC_SEC:
s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
break;
case MENELAUS_RTC_MIN:
s->rtc.tm.tm_min = from_bcd(value & 0x7f);
break;
case MENELAUS_RTC_HR:
s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
from_bcd(value & 0x3f);
break;
case MENELAUS_RTC_DAY:
s->rtc.tm.tm_mday = from_bcd(value);
break;
case MENELAUS_RTC_MON:
s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
break;
case MENELAUS_RTC_YR:
s->rtc.tm.tm_year = 2000 + from_bcd(value);
break;
case MENELAUS_RTC_WKDAY:
s->rtc.tm.tm_mday = from_bcd(value);
break;
case MENELAUS_RTC_AL_SEC:
s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
menelaus_alm_update(s);
break;
case MENELAUS_RTC_AL_MIN:
s->rtc.alm.tm_min = from_bcd(value & 0x7f);
menelaus_alm_update(s);
break;
case MENELAUS_RTC_AL_HR:
s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
from_bcd(value & 0x3f);
menelaus_alm_update(s);
break;
case MENELAUS_RTC_AL_DAY:
s->rtc.alm.tm_mday = from_bcd(value);
menelaus_alm_update(s);
break;
case MENELAUS_RTC_AL_MON:
s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
menelaus_alm_update(s);
break;
case MENELAUS_RTC_AL_YR:
s->rtc.alm.tm_year = 2000 + from_bcd(value);
menelaus_alm_update(s);
break;
case MENELAUS_RTC_COMP_MSB:
s->rtc.comp &= 0xff;
s->rtc.comp |= value << 8;
break;
case MENELAUS_RTC_COMP_LSB:
s->rtc.comp &= 0xff << 8;
s->rtc.comp |= value;
break;
case MENELAUS_S1_PULL_EN:
s->pull[0] = value;
break;
case MENELAUS_S1_PULL_DIR:
s->pull[1] = value & 0x1f;
break;
case MENELAUS_S2_PULL_EN:
s->pull[2] = value;
break;
case MENELAUS_S2_PULL_DIR:
s->pull[3] = value & 0x1f;
break;
case MENELAUS_MCT_CTRL1:
s->mmc_ctrl[0] = value & 0x7f;
break;
case MENELAUS_MCT_CTRL2:
s->mmc_ctrl[1] = value;
/* TODO update Card Detect interrupts */
break;
case MENELAUS_MCT_CTRL3:
s->mmc_ctrl[2] = value & 0xf;
break;
case MENELAUS_DEBOUNCE1:
s->mmc_debounce = value & 0x3f;
break;
default:
#ifdef VERBOSE
printf("%s: unknown register %02x\n", __func__, addr);
#endif
}
}
static int menelaus_event(I2CSlave *i2c, enum i2c_event event)
{
MenelausState *s = TWL92230(i2c);
if (event == I2C_START_SEND)
s->firstbyte = 1;
return 0;
}
static int menelaus_tx(I2CSlave *i2c, uint8_t data)
{
MenelausState *s = TWL92230(i2c);
/* Interpret register address byte */
if (s->firstbyte) {
s->reg = data;
s->firstbyte = 0;
} else
menelaus_write(s, s->reg ++, data);
return 0;
}
static uint8_t menelaus_rx(I2CSlave *i2c)
{
MenelausState *s = TWL92230(i2c);
return menelaus_read(s, s->reg ++);
}
/* Save restore 32 bit int as uint16_t
This is a Big hack, but it is how the old state did it.
Or we broke compatibility in the state, or we can't use struct tm
*/
static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
int *v = pv;
*v = qemu_get_be16(f);
return 0;
}
static int put_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
const VMStateField *field, QJSON *vmdesc)
{
int *v = pv;
qemu_put_be16(f, *v);
return 0;
}
static const VMStateInfo vmstate_hack_int32_as_uint16 = {
.name = "int32_as_uint16",
.get = get_int32_as_uint16,
.put = put_int32_as_uint16,
};
#define VMSTATE_UINT16_HACK(_f, _s) \
VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
static const VMStateDescription vmstate_menelaus_tm = {
.name = "menelaus_tm",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT16_HACK(tm_sec, struct tm),
VMSTATE_UINT16_HACK(tm_min, struct tm),
VMSTATE_UINT16_HACK(tm_hour, struct tm),
VMSTATE_UINT16_HACK(tm_mday, struct tm),
VMSTATE_UINT16_HACK(tm_min, struct tm),
VMSTATE_UINT16_HACK(tm_year, struct tm),
VMSTATE_END_OF_LIST()
}
};
static int menelaus_pre_save(void *opaque)
{
MenelausState *s = opaque;
/* Should be <= 1000 */
s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
return 0;
}
static int menelaus_post_load(void *opaque, int version_id)
{
MenelausState *s = opaque;
if (s->rtc.ctrl & 1) /* RTC_EN */
menelaus_rtc_stop(s);
s->rtc.next = s->rtc_next_vmstate;
menelaus_alm_update(s);
menelaus_update(s);
if (s->rtc.ctrl & 1) /* RTC_EN */
menelaus_rtc_start(s);
return 0;
}
static const VMStateDescription vmstate_menelaus = {
.name = "menelaus",
.version_id = 0,
.minimum_version_id = 0,
.pre_save = menelaus_pre_save,
.post_load = menelaus_post_load,
.fields = (VMStateField[]) {
VMSTATE_INT32(firstbyte, MenelausState),
VMSTATE_UINT8(reg, MenelausState),
VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
VMSTATE_UINT8(osc, MenelausState),
VMSTATE_UINT8(detect, MenelausState),
VMSTATE_UINT16(mask, MenelausState),
VMSTATE_UINT16(status, MenelausState),
VMSTATE_UINT8(dir, MenelausState),
VMSTATE_UINT8(inputs, MenelausState),
VMSTATE_UINT8(outputs, MenelausState),
VMSTATE_UINT8(bbsms, MenelausState),
VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
VMSTATE_UINT8(mmc_debounce, MenelausState),
VMSTATE_UINT8(rtc.ctrl, MenelausState),
VMSTATE_UINT16(rtc.comp, MenelausState),
VMSTATE_UINT16(rtc_next_vmstate, MenelausState),
VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
struct tm),
VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
struct tm),
VMSTATE_UINT8(pwrbtn_state, MenelausState),
VMSTATE_I2C_SLAVE(parent_obj, MenelausState),
VMSTATE_END_OF_LIST()
}
};
static void twl92230_realize(DeviceState *dev, Error **errp)
{
MenelausState *s = TWL92230(dev);
s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
/* Three output pins plus one interrupt pin. */
qdev_init_gpio_out(dev, s->out, 4);
/* Three input pins plus one power-button pin. */
qdev_init_gpio_in(dev, menelaus_gpio_set, 4);
menelaus_reset(I2C_SLAVE(dev));
}
static void twl92230_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
dc->realize = twl92230_realize;
sc->event = menelaus_event;
sc->recv = menelaus_rx;
sc->send = menelaus_tx;
dc->vmsd = &vmstate_menelaus;
}
static const TypeInfo twl92230_info = {
.name = TYPE_TWL92230,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(MenelausState),
.class_init = twl92230_class_init,
};
static void twl92230_register_types(void)
{
type_register_static(&twl92230_info);
}
type_init(twl92230_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/io/task.c | /*
* QEMU I/O task
*
* Copyright (c) 2015 Red Hat, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*/
#include "qemu/osdep.h"
#include "io/task.h"
#include "qapi/error.h"
#include "qemu/thread.h"
#include "trace.h"
struct QIOTaskThreadData {
QIOTaskWorker worker;
gpointer opaque;
GDestroyNotify destroy;
GMainContext *context;
GSource *completion;
};
struct QIOTask {
Object *source;
QIOTaskFunc func;
gpointer opaque;
GDestroyNotify destroy;
Error *err;
gpointer result;
GDestroyNotify destroyResult;
QemuMutex thread_lock;
QemuCond thread_cond;
struct QIOTaskThreadData *thread;
};
QIOTask *qio_task_new(Object *source,
QIOTaskFunc func,
gpointer opaque,
GDestroyNotify destroy)
{
QIOTask *task;
task = g_new0(QIOTask, 1);
task->source = source;
object_ref(source);
task->func = func;
task->opaque = opaque;
task->destroy = destroy;
qemu_mutex_init(&task->thread_lock);
qemu_cond_init(&task->thread_cond);
trace_qio_task_new(task, source, func, opaque);
return task;
}
static void qio_task_free(QIOTask *task)
{
qemu_mutex_lock(&task->thread_lock);
if (task->thread) {
if (task->thread->destroy) {
task->thread->destroy(task->thread->opaque);
}
if (task->thread->context) {
g_main_context_unref(task->thread->context);
}
g_free(task->thread);
}
if (task->destroy) {
task->destroy(task->opaque);
}
if (task->destroyResult) {
task->destroyResult(task->result);
}
if (task->err) {
error_free(task->err);
}
object_unref(task->source);
qemu_mutex_unlock(&task->thread_lock);
qemu_mutex_destroy(&task->thread_lock);
qemu_cond_destroy(&task->thread_cond);
g_free(task);
}
static gboolean qio_task_thread_result(gpointer opaque)
{
QIOTask *task = opaque;
trace_qio_task_thread_result(task);
qio_task_complete(task);
return FALSE;
}
static gpointer qio_task_thread_worker(gpointer opaque)
{
QIOTask *task = opaque;
trace_qio_task_thread_run(task);
task->thread->worker(task, task->thread->opaque);
/* We're running in the background thread, and must only
* ever report the task results in the main event loop
* thread. So we schedule an idle callback to report
* the worker results
*/
trace_qio_task_thread_exit(task);
qemu_mutex_lock(&task->thread_lock);
task->thread->completion = g_idle_source_new();
g_source_set_callback(task->thread->completion,
qio_task_thread_result, task, NULL);
g_source_attach(task->thread->completion,
task->thread->context);
trace_qio_task_thread_source_attach(task, task->thread->completion);
qemu_cond_signal(&task->thread_cond);
qemu_mutex_unlock(&task->thread_lock);
return NULL;
}
void qio_task_run_in_thread(QIOTask *task,
QIOTaskWorker worker,
gpointer opaque,
GDestroyNotify destroy,
GMainContext *context)
{
struct QIOTaskThreadData *data = g_new0(struct QIOTaskThreadData, 1);
QemuThread thread;
if (context) {
g_main_context_ref(context);
}
data->worker = worker;
data->opaque = opaque;
data->destroy = destroy;
data->context = context;
task->thread = data;
trace_qio_task_thread_start(task, worker, opaque);
qemu_thread_create(&thread,
"io-task-worker",
qio_task_thread_worker,
task,
QEMU_THREAD_DETACHED);
}
void qio_task_wait_thread(QIOTask *task)
{
qemu_mutex_lock(&task->thread_lock);
g_assert(task->thread != NULL);
while (task->thread->completion == NULL) {
qemu_cond_wait(&task->thread_cond, &task->thread_lock);
}
trace_qio_task_thread_source_cancel(task, task->thread->completion);
g_source_destroy(task->thread->completion);
qemu_mutex_unlock(&task->thread_lock);
qio_task_thread_result(task);
}
void qio_task_complete(QIOTask *task)
{
task->func(task, task->opaque);
trace_qio_task_complete(task);
qio_task_free(task);
}
void qio_task_set_error(QIOTask *task,
Error *err)
{
error_propagate(&task->err, err);
}
bool qio_task_propagate_error(QIOTask *task,
Error **errp)
{
if (task->err) {
error_propagate(errp, task->err);
task->err = NULL;
return true;
}
return false;
}
void qio_task_set_result_pointer(QIOTask *task,
gpointer result,
GDestroyNotify destroy)
{
task->result = result;
task->destroyResult = destroy;
}
gpointer qio_task_get_result_pointer(QIOTask *task)
{
return task->result;
}
Object *qio_task_get_source(QIOTask *task)
{
return task->source;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-multiply/test_msa_mulr_q_h.c | /*
* Test program for MSA instruction MULR_Q.H
*
* Copyright (C) 2018 Wave Computing, Inc.
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs.h"
#include "../../../../include/test_utils.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "MULR_Q.H";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 0 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000010000ULL, 0x0000000100000000ULL, },
{ 0x00000000ffff0000ULL, 0x0000ffff00000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, }, /* 16 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x38e438e438e438e4ULL, 0x38e438e438e438e4ULL, },
{ 0xc71cc71cc71cc71cULL, 0xc71cc71cc71cc71cULL, },
{ 0x2223222322232223ULL, 0x2223222322232223ULL, },
{ 0xdddedddedddedddeULL, 0xdddedddedddedddeULL, },
{ 0x12f7da134bdb12f7ULL, 0xda134bdb12f7da13ULL, },
{ 0xed0a25eeb425ed0aULL, 0x25eeb425ed0a25eeULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, }, /* 24 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xc71cc71cc71cc71cULL, 0xc71cc71cc71cc71cULL, },
{ 0x38e338e338e338e3ULL, 0x38e338e338e338e3ULL, },
{ 0xddddddddddddddddULL, 0xddddddddddddddddULL, },
{ 0x2222222222222222ULL, 0x2222222222222222ULL, },
{ 0xed0925edb426ed09ULL, 0x25edb426ed0925edULL, },
{ 0x12f6da134bda12f6ULL, 0xda134bda12f6da13ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 32 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x2223222322232223ULL, 0x2223222322232223ULL, },
{ 0xddddddddddddddddULL, 0xddddddddddddddddULL, },
{ 0x147c147c147c147cULL, 0x147c147c147c147cULL, },
{ 0xeb85eb85eb85eb85ULL, 0xeb85eb85eb85eb85ULL, },
{ 0x0b61e93e2d840b61ULL, 0xe93e2d840b61e93eULL, },
{ 0xf49f16c2d27cf49fULL, 0x16c2d27cf49f16c2ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 40 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xdddedddedddedddeULL, 0xdddedddedddedddeULL, },
{ 0x2222222222222222ULL, 0x2222222222222222ULL, },
{ 0xeb85eb85eb85eb85ULL, 0xeb85eb85eb85eb85ULL, },
{ 0x147b147b147b147bULL, 0x147b147b147b147bULL, },
{ 0xf49f16c1d27df49fULL, 0x16c1d27df49f16c1ULL, },
{ 0x0b60e93e2d830b60ULL, 0xe93e2d830b60e93eULL, },
{ 0x0000000000010000ULL, 0x0000000100000000ULL, }, /* 48 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x12f7da134bdb12f7ULL, 0xda134bdb12f7da13ULL, },
{ 0xed0925edb426ed09ULL, 0x25edb426ed0925edULL, },
{ 0x0b61e93e2d840b61ULL, 0xe93e2d840b61e93eULL, },
{ 0xf49f16c1d27df49fULL, 0x16c1d27df49f16c1ULL, },
{ 0x0652194865240652ULL, 0x1948652406521948ULL, },
{ 0xf9aee6b79addf9aeULL, 0xe6b79addf9aee6b7ULL, },
{ 0x00000000ffff0000ULL, 0x0000ffff00000000ULL, }, /* 56 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xed0a25eeb425ed0aULL, 0x25eeb425ed0a25eeULL, },
{ 0x12f6da134bda12f6ULL, 0xda134bda12f6da13ULL, },
{ 0xf49f16c2d27cf49fULL, 0x16c2d27cf49f16c2ULL, },
{ 0x0b60e93e2d830b60ULL, 0xe93e2d830b60e93eULL, },
{ 0xf9aee6b79addf9aeULL, 0xe6b79addf9aee6b7ULL, },
{ 0x0652194965230652ULL, 0x1949652306521949ULL, },
{ 0x6fba04f60cbe38c7ULL, 0x2c6b0102000531f1ULL, }, /* 64 */
{ 0x03faffed1879da0fULL, 0x0b2cf9e2ffbfcc2aULL, },
{ 0x4e261004e9dbb269ULL, 0x1779faf00102e8d7ULL, },
{ 0x9713fb9c1db7ec39ULL, 0xbccff56b01081259ULL, },
{ 0x03faffed1879da0fULL, 0x0b2cf9e2ffbfcc2aULL, },
{ 0x002400002f04195bULL, 0x02cf2516038735cdULL, },
{ 0x02c8ffc1d57633daULL, 0x05e71eaff1eb180aULL, },
{ 0xfc44001139160d37ULL, 0xef1a4023f19aecf5ULL, },
{ 0x4e261004e9dbb269ULL, 0x1779faf00102e8d7ULL, }, /* 72 */
{ 0x02c8ffc1d57633daULL, 0x05e71eaff1eb180aULL, },
{ 0x36aa33af267e6a09ULL, 0x0c67196338390abeULL, },
{ 0xb69bf1d4cc591b07ULL, 0xdc7f3511397df77eULL, },
{ 0x9713fb9c1db7ec39ULL, 0xbccff56b01081259ULL, },
{ 0xfc44001139160d37ULL, 0xef1a4023f19aecf5ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_MULR_Q_H(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_MULR_Q_H(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/migration/postcopy-ram.c | <reponame>pmp-tool/PMP<gh_stars>1-10
/*
* Postcopy migration for RAM
*
* Copyright 2013-2015 Red Hat, Inc. and/or its affiliates
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
*/
/*
* Postcopy is a migration technique where the execution flips from the
* source to the destination before all the data has been copied.
*/
#include "qemu/osdep.h"
#include "exec/target_page.h"
#include "migration.h"
#include "qemu-file.h"
#include "savevm.h"
#include "postcopy-ram.h"
#include "ram.h"
#include "qapi/error.h"
#include "qemu/notify.h"
#include "sysemu/sysemu.h"
#include "sysemu/balloon.h"
#include "qemu/error-report.h"
#include "trace.h"
/* Arbitrary limit on size of each discard command,
* keeps them around ~200 bytes
*/
#define MAX_DISCARDS_PER_COMMAND 12
struct PostcopyDiscardState {
const char *ramblock_name;
uint16_t cur_entry;
/*
* Start and length of a discard range (bytes)
*/
uint64_t start_list[MAX_DISCARDS_PER_COMMAND];
uint64_t length_list[MAX_DISCARDS_PER_COMMAND];
unsigned int nsentwords;
unsigned int nsentcmds;
};
static NotifierWithReturnList postcopy_notifier_list;
void postcopy_infrastructure_init(void)
{
notifier_with_return_list_init(&postcopy_notifier_list);
}
void postcopy_add_notifier(NotifierWithReturn *nn)
{
notifier_with_return_list_add(&postcopy_notifier_list, nn);
}
void postcopy_remove_notifier(NotifierWithReturn *n)
{
notifier_with_return_remove(n);
}
int postcopy_notify(enum PostcopyNotifyReason reason, Error **errp)
{
struct PostcopyNotifyData pnd;
pnd.reason = reason;
pnd.errp = errp;
return notifier_with_return_list_notify(&postcopy_notifier_list,
&pnd);
}
/* Postcopy needs to detect accesses to pages that haven't yet been copied
* across, and efficiently map new pages in, the techniques for doing this
* are target OS specific.
*/
#if defined(__linux__)
#include <poll.h>
#include <sys/ioctl.h>
#include <sys/syscall.h>
#include <asm/types.h> /* for __u64 */
#endif
#if defined(__linux__) && defined(__NR_userfaultfd) && defined(CONFIG_EVENTFD)
#include <sys/eventfd.h>
#include <linux/userfaultfd.h>
typedef struct PostcopyBlocktimeContext {
/* time when page fault initiated per vCPU */
uint32_t *page_fault_vcpu_time;
/* page address per vCPU */
uintptr_t *vcpu_addr;
uint32_t total_blocktime;
/* blocktime per vCPU */
uint32_t *vcpu_blocktime;
/* point in time when last page fault was initiated */
uint32_t last_begin;
/* number of vCPU are suspended */
int smp_cpus_down;
uint64_t start_time;
/*
* Handler for exit event, necessary for
* releasing whole blocktime_ctx
*/
Notifier exit_notifier;
} PostcopyBlocktimeContext;
static void destroy_blocktime_context(struct PostcopyBlocktimeContext *ctx)
{
g_free(ctx->page_fault_vcpu_time);
g_free(ctx->vcpu_addr);
g_free(ctx->vcpu_blocktime);
g_free(ctx);
}
static void migration_exit_cb(Notifier *n, void *data)
{
PostcopyBlocktimeContext *ctx = container_of(n, PostcopyBlocktimeContext,
exit_notifier);
destroy_blocktime_context(ctx);
}
static struct PostcopyBlocktimeContext *blocktime_context_new(void)
{
PostcopyBlocktimeContext *ctx = g_new0(PostcopyBlocktimeContext, 1);
ctx->page_fault_vcpu_time = g_new0(uint32_t, smp_cpus);
ctx->vcpu_addr = g_new0(uintptr_t, smp_cpus);
ctx->vcpu_blocktime = g_new0(uint32_t, smp_cpus);
ctx->exit_notifier.notify = migration_exit_cb;
ctx->start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
qemu_add_exit_notifier(&ctx->exit_notifier);
return ctx;
}
static uint32List *get_vcpu_blocktime_list(PostcopyBlocktimeContext *ctx)
{
uint32List *list = NULL, *entry = NULL;
int i;
for (i = smp_cpus - 1; i >= 0; i--) {
entry = g_new0(uint32List, 1);
entry->value = ctx->vcpu_blocktime[i];
entry->next = list;
list = entry;
}
return list;
}
/*
* This function just populates MigrationInfo from postcopy's
* blocktime context. It will not populate MigrationInfo,
* unless postcopy-blocktime capability was set.
*
* @info: pointer to MigrationInfo to populate
*/
void fill_destination_postcopy_migration_info(MigrationInfo *info)
{
MigrationIncomingState *mis = migration_incoming_get_current();
PostcopyBlocktimeContext *bc = mis->blocktime_ctx;
if (!bc) {
return;
}
info->has_postcopy_blocktime = true;
info->postcopy_blocktime = bc->total_blocktime;
info->has_postcopy_vcpu_blocktime = true;
info->postcopy_vcpu_blocktime = get_vcpu_blocktime_list(bc);
}
static uint32_t get_postcopy_total_blocktime(void)
{
MigrationIncomingState *mis = migration_incoming_get_current();
PostcopyBlocktimeContext *bc = mis->blocktime_ctx;
if (!bc) {
return 0;
}
return bc->total_blocktime;
}
/**
* receive_ufd_features: check userfault fd features, to request only supported
* features in the future.
*
* Returns: true on success
*
* __NR_userfaultfd - should be checked before
* @features: out parameter will contain uffdio_api.features provided by kernel
* in case of success
*/
static bool receive_ufd_features(uint64_t *features)
{
struct uffdio_api api_struct = {0};
int ufd;
bool ret = true;
/* if we are here __NR_userfaultfd should exists */
ufd = syscall(__NR_userfaultfd, O_CLOEXEC);
if (ufd == -1) {
error_report("%s: syscall __NR_userfaultfd failed: %s", __func__,
strerror(errno));
return false;
}
/* ask features */
api_struct.api = UFFD_API;
api_struct.features = 0;
if (ioctl(ufd, UFFDIO_API, &api_struct)) {
error_report("%s: UFFDIO_API failed: %s", __func__,
strerror(errno));
ret = false;
goto release_ufd;
}
*features = api_struct.features;
release_ufd:
close(ufd);
return ret;
}
/**
* request_ufd_features: this function should be called only once on a newly
* opened ufd, subsequent calls will lead to error.
*
* Returns: true on succes
*
* @ufd: fd obtained from userfaultfd syscall
* @features: bit mask see UFFD_API_FEATURES
*/
static bool request_ufd_features(int ufd, uint64_t features)
{
struct uffdio_api api_struct = {0};
uint64_t ioctl_mask;
api_struct.api = UFFD_API;
api_struct.features = features;
if (ioctl(ufd, UFFDIO_API, &api_struct)) {
error_report("%s failed: UFFDIO_API failed: %s", __func__,
strerror(errno));
return false;
}
ioctl_mask = (__u64)1 << _UFFDIO_REGISTER |
(__u64)1 << _UFFDIO_UNREGISTER;
if ((api_struct.ioctls & ioctl_mask) != ioctl_mask) {
error_report("Missing userfault features: %" PRIx64,
(uint64_t)(~api_struct.ioctls & ioctl_mask));
return false;
}
return true;
}
static bool ufd_check_and_apply(int ufd, MigrationIncomingState *mis)
{
uint64_t asked_features = 0;
static uint64_t supported_features;
/*
* it's not possible to
* request UFFD_API twice per one fd
* userfault fd features is persistent
*/
if (!supported_features) {
if (!receive_ufd_features(&supported_features)) {
error_report("%s failed", __func__);
return false;
}
}
#ifdef UFFD_FEATURE_THREAD_ID
if (migrate_postcopy_blocktime() && mis &&
UFFD_FEATURE_THREAD_ID & supported_features) {
/* kernel supports that feature */
/* don't create blocktime_context if it exists */
if (!mis->blocktime_ctx) {
mis->blocktime_ctx = blocktime_context_new();
}
asked_features |= UFFD_FEATURE_THREAD_ID;
}
#endif
/*
* request features, even if asked_features is 0, due to
* kernel expects UFFD_API before UFFDIO_REGISTER, per
* userfault file descriptor
*/
if (!request_ufd_features(ufd, asked_features)) {
error_report("%s failed: features %" PRIu64, __func__,
asked_features);
return false;
}
if (getpagesize() != ram_pagesize_summary()) {
bool have_hp = false;
/* We've got a huge page */
#ifdef UFFD_FEATURE_MISSING_HUGETLBFS
have_hp = supported_features & UFFD_FEATURE_MISSING_HUGETLBFS;
#endif
if (!have_hp) {
error_report("Userfault on this host does not support huge pages");
return false;
}
}
return true;
}
/* Callback from postcopy_ram_supported_by_host block iterator.
*/
static int test_ramblock_postcopiable(RAMBlock *rb, void *opaque)
{
const char *block_name = qemu_ram_get_idstr(rb);
ram_addr_t length = qemu_ram_get_used_length(rb);
size_t pagesize = qemu_ram_pagesize(rb);
if (length % pagesize) {
error_report("Postcopy requires RAM blocks to be a page size multiple,"
" block %s is 0x" RAM_ADDR_FMT " bytes with a "
"page size of 0x%zx", block_name, length, pagesize);
return 1;
}
return 0;
}
/*
* Note: This has the side effect of munlock'ing all of RAM, that's
* normally fine since if the postcopy succeeds it gets turned back on at the
* end.
*/
bool postcopy_ram_supported_by_host(MigrationIncomingState *mis)
{
long pagesize = getpagesize();
int ufd = -1;
bool ret = false; /* Error unless we change it */
void *testarea = NULL;
struct uffdio_register reg_struct;
struct uffdio_range range_struct;
uint64_t feature_mask;
Error *local_err = NULL;
if (qemu_target_page_size() > pagesize) {
error_report("Target page size bigger than host page size");
goto out;
}
ufd = syscall(__NR_userfaultfd, O_CLOEXEC);
if (ufd == -1) {
error_report("%s: userfaultfd not available: %s", __func__,
strerror(errno));
goto out;
}
/* Give devices a chance to object */
if (postcopy_notify(POSTCOPY_NOTIFY_PROBE, &local_err)) {
error_report_err(local_err);
goto out;
}
/* Version and features check */
if (!ufd_check_and_apply(ufd, mis)) {
goto out;
}
/* We don't support postcopy with shared RAM yet */
if (foreach_not_ignored_block(test_ramblock_postcopiable, NULL)) {
goto out;
}
/*
* userfault and mlock don't go together; we'll put it back later if
* it was enabled.
*/
if (munlockall()) {
error_report("%s: munlockall: %s", __func__, strerror(errno));
return -1;
}
/*
* We need to check that the ops we need are supported on anon memory
* To do that we need to register a chunk and see the flags that
* are returned.
*/
testarea = mmap(NULL, pagesize, PROT_READ | PROT_WRITE, MAP_PRIVATE |
MAP_ANONYMOUS, -1, 0);
if (testarea == MAP_FAILED) {
error_report("%s: Failed to map test area: %s", __func__,
strerror(errno));
goto out;
}
g_assert(((size_t)testarea & (pagesize-1)) == 0);
reg_struct.range.start = (uintptr_t)testarea;
reg_struct.range.len = pagesize;
reg_struct.mode = UFFDIO_REGISTER_MODE_MISSING;
if (ioctl(ufd, UFFDIO_REGISTER, ®_struct)) {
error_report("%s userfault register: %s", __func__, strerror(errno));
goto out;
}
range_struct.start = (uintptr_t)testarea;
range_struct.len = pagesize;
if (ioctl(ufd, UFFDIO_UNREGISTER, &range_struct)) {
error_report("%s userfault unregister: %s", __func__, strerror(errno));
goto out;
}
feature_mask = (__u64)1 << _UFFDIO_WAKE |
(__u64)1 << _UFFDIO_COPY |
(__u64)1 << _UFFDIO_ZEROPAGE;
if ((reg_struct.ioctls & feature_mask) != feature_mask) {
error_report("Missing userfault map features: %" PRIx64,
(uint64_t)(~reg_struct.ioctls & feature_mask));
goto out;
}
/* Success! */
ret = true;
out:
if (testarea) {
munmap(testarea, pagesize);
}
if (ufd != -1) {
close(ufd);
}
return ret;
}
/*
* Setup an area of RAM so that it *can* be used for postcopy later; this
* must be done right at the start prior to pre-copy.
* opaque should be the MIS.
*/
static int init_range(RAMBlock *rb, void *opaque)
{
const char *block_name = qemu_ram_get_idstr(rb);
void *host_addr = qemu_ram_get_host_addr(rb);
ram_addr_t offset = qemu_ram_get_offset(rb);
ram_addr_t length = qemu_ram_get_used_length(rb);
trace_postcopy_init_range(block_name, host_addr, offset, length);
/*
* We need the whole of RAM to be truly empty for postcopy, so things
* like ROMs and any data tables built during init must be zero'd
* - we're going to get the copy from the source anyway.
* (Precopy will just overwrite this data, so doesn't need the discard)
*/
if (ram_discard_range(block_name, 0, length)) {
return -1;
}
return 0;
}
/*
* At the end of migration, undo the effects of init_range
* opaque should be the MIS.
*/
static int cleanup_range(RAMBlock *rb, void *opaque)
{
const char *block_name = qemu_ram_get_idstr(rb);
void *host_addr = qemu_ram_get_host_addr(rb);
ram_addr_t offset = qemu_ram_get_offset(rb);
ram_addr_t length = qemu_ram_get_used_length(rb);
MigrationIncomingState *mis = opaque;
struct uffdio_range range_struct;
trace_postcopy_cleanup_range(block_name, host_addr, offset, length);
/*
* We turned off hugepage for the precopy stage with postcopy enabled
* we can turn it back on now.
*/
qemu_madvise(host_addr, length, QEMU_MADV_HUGEPAGE);
/*
* We can also turn off userfault now since we should have all the
* pages. It can be useful to leave it on to debug postcopy
* if you're not sure it's always getting every page.
*/
range_struct.start = (uintptr_t)host_addr;
range_struct.len = length;
if (ioctl(mis->userfault_fd, UFFDIO_UNREGISTER, &range_struct)) {
error_report("%s: userfault unregister %s", __func__, strerror(errno));
return -1;
}
return 0;
}
/*
* Initialise postcopy-ram, setting the RAM to a state where we can go into
* postcopy later; must be called prior to any precopy.
* called from arch_init's similarly named ram_postcopy_incoming_init
*/
int postcopy_ram_incoming_init(MigrationIncomingState *mis)
{
if (foreach_not_ignored_block(init_range, NULL)) {
return -1;
}
return 0;
}
/*
* Manage a single vote to the QEMU balloon inhibitor for all postcopy usage,
* last caller wins.
*/
static void postcopy_balloon_inhibit(bool state)
{
static bool cur_state = false;
if (state != cur_state) {
qemu_balloon_inhibit(state);
cur_state = state;
}
}
/*
* At the end of a migration where postcopy_ram_incoming_init was called.
*/
int postcopy_ram_incoming_cleanup(MigrationIncomingState *mis)
{
trace_postcopy_ram_incoming_cleanup_entry();
if (mis->have_fault_thread) {
Error *local_err = NULL;
/* Let the fault thread quit */
atomic_set(&mis->fault_thread_quit, 1);
postcopy_fault_thread_notify(mis);
trace_postcopy_ram_incoming_cleanup_join();
qemu_thread_join(&mis->fault_thread);
if (postcopy_notify(POSTCOPY_NOTIFY_INBOUND_END, &local_err)) {
error_report_err(local_err);
return -1;
}
if (foreach_not_ignored_block(cleanup_range, mis)) {
return -1;
}
trace_postcopy_ram_incoming_cleanup_closeuf();
close(mis->userfault_fd);
close(mis->userfault_event_fd);
mis->have_fault_thread = false;
}
postcopy_balloon_inhibit(false);
if (enable_mlock) {
if (os_mlock() < 0) {
error_report("mlock: %s", strerror(errno));
/*
* It doesn't feel right to fail at this point, we have a valid
* VM state.
*/
}
}
postcopy_state_set(POSTCOPY_INCOMING_END);
if (mis->postcopy_tmp_page) {
munmap(mis->postcopy_tmp_page, mis->largest_page_size);
mis->postcopy_tmp_page = NULL;
}
if (mis->postcopy_tmp_zero_page) {
munmap(mis->postcopy_tmp_zero_page, mis->largest_page_size);
mis->postcopy_tmp_zero_page = NULL;
}
trace_postcopy_ram_incoming_cleanup_blocktime(
get_postcopy_total_blocktime());
trace_postcopy_ram_incoming_cleanup_exit();
return 0;
}
/*
* Disable huge pages on an area
*/
static int nhp_range(RAMBlock *rb, void *opaque)
{
const char *block_name = qemu_ram_get_idstr(rb);
void *host_addr = qemu_ram_get_host_addr(rb);
ram_addr_t offset = qemu_ram_get_offset(rb);
ram_addr_t length = qemu_ram_get_used_length(rb);
trace_postcopy_nhp_range(block_name, host_addr, offset, length);
/*
* Before we do discards we need to ensure those discards really
* do delete areas of the page, even if THP thinks a hugepage would
* be a good idea, so force hugepages off.
*/
qemu_madvise(host_addr, length, QEMU_MADV_NOHUGEPAGE);
return 0;
}
/*
* Userfault requires us to mark RAM as NOHUGEPAGE prior to discard
* however leaving it until after precopy means that most of the precopy
* data is still THPd
*/
int postcopy_ram_prepare_discard(MigrationIncomingState *mis)
{
if (foreach_not_ignored_block(nhp_range, mis)) {
return -1;
}
postcopy_state_set(POSTCOPY_INCOMING_DISCARD);
return 0;
}
/*
* Mark the given area of RAM as requiring notification to unwritten areas
* Used as a callback on foreach_not_ignored_block.
* host_addr: Base of area to mark
* offset: Offset in the whole ram arena
* length: Length of the section
* opaque: MigrationIncomingState pointer
* Returns 0 on success
*/
static int ram_block_enable_notify(RAMBlock *rb, void *opaque)
{
MigrationIncomingState *mis = opaque;
struct uffdio_register reg_struct;
reg_struct.range.start = (uintptr_t)qemu_ram_get_host_addr(rb);
reg_struct.range.len = qemu_ram_get_used_length(rb);
reg_struct.mode = UFFDIO_REGISTER_MODE_MISSING;
/* Now tell our userfault_fd that it's responsible for this area */
if (ioctl(mis->userfault_fd, UFFDIO_REGISTER, ®_struct)) {
error_report("%s userfault register: %s", __func__, strerror(errno));
return -1;
}
if (!(reg_struct.ioctls & ((__u64)1 << _UFFDIO_COPY))) {
error_report("%s userfault: Region doesn't support COPY", __func__);
return -1;
}
if (reg_struct.ioctls & ((__u64)1 << _UFFDIO_ZEROPAGE)) {
qemu_ram_set_uf_zeroable(rb);
}
return 0;
}
int postcopy_wake_shared(struct PostCopyFD *pcfd,
uint64_t client_addr,
RAMBlock *rb)
{
size_t pagesize = qemu_ram_pagesize(rb);
struct uffdio_range range;
int ret;
trace_postcopy_wake_shared(client_addr, qemu_ram_get_idstr(rb));
range.start = client_addr & ~(pagesize - 1);
range.len = pagesize;
ret = ioctl(pcfd->fd, UFFDIO_WAKE, &range);
if (ret) {
error_report("%s: Failed to wake: %zx in %s (%s)",
__func__, (size_t)client_addr, qemu_ram_get_idstr(rb),
strerror(errno));
}
return ret;
}
/*
* Callback from shared fault handlers to ask for a page,
* the page must be specified by a RAMBlock and an offset in that rb
* Note: Only for use by shared fault handlers (in fault thread)
*/
int postcopy_request_shared_page(struct PostCopyFD *pcfd, RAMBlock *rb,
uint64_t client_addr, uint64_t rb_offset)
{
size_t pagesize = qemu_ram_pagesize(rb);
uint64_t aligned_rbo = rb_offset & ~(pagesize - 1);
MigrationIncomingState *mis = migration_incoming_get_current();
trace_postcopy_request_shared_page(pcfd->idstr, qemu_ram_get_idstr(rb),
rb_offset);
if (ramblock_recv_bitmap_test_byte_offset(rb, aligned_rbo)) {
trace_postcopy_request_shared_page_present(pcfd->idstr,
qemu_ram_get_idstr(rb), rb_offset);
return postcopy_wake_shared(pcfd, client_addr, rb);
}
if (rb != mis->last_rb) {
mis->last_rb = rb;
migrate_send_rp_req_pages(mis, qemu_ram_get_idstr(rb),
aligned_rbo, pagesize);
} else {
/* Save some space */
migrate_send_rp_req_pages(mis, NULL, aligned_rbo, pagesize);
}
return 0;
}
static int get_mem_fault_cpu_index(uint32_t pid)
{
CPUState *cpu_iter;
CPU_FOREACH(cpu_iter) {
if (cpu_iter->thread_id == pid) {
trace_get_mem_fault_cpu_index(cpu_iter->cpu_index, pid);
return cpu_iter->cpu_index;
}
}
trace_get_mem_fault_cpu_index(-1, pid);
return -1;
}
static uint32_t get_low_time_offset(PostcopyBlocktimeContext *dc)
{
int64_t start_time_offset = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) -
dc->start_time;
return start_time_offset < 1 ? 1 : start_time_offset & UINT32_MAX;
}
/*
* This function is being called when pagefault occurs. It
* tracks down vCPU blocking time.
*
* @addr: faulted host virtual address
* @ptid: faulted process thread id
* @rb: ramblock appropriate to addr
*/
static void mark_postcopy_blocktime_begin(uintptr_t addr, uint32_t ptid,
RAMBlock *rb)
{
int cpu, already_received;
MigrationIncomingState *mis = migration_incoming_get_current();
PostcopyBlocktimeContext *dc = mis->blocktime_ctx;
uint32_t low_time_offset;
if (!dc || ptid == 0) {
return;
}
cpu = get_mem_fault_cpu_index(ptid);
if (cpu < 0) {
return;
}
low_time_offset = get_low_time_offset(dc);
if (dc->vcpu_addr[cpu] == 0) {
atomic_inc(&dc->smp_cpus_down);
}
atomic_xchg(&dc->last_begin, low_time_offset);
atomic_xchg(&dc->page_fault_vcpu_time[cpu], low_time_offset);
atomic_xchg(&dc->vcpu_addr[cpu], addr);
/* check it here, not at the begining of the function,
* due to, check could accur early than bitmap_set in
* qemu_ufd_copy_ioctl */
already_received = ramblock_recv_bitmap_test(rb, (void *)addr);
if (already_received) {
atomic_xchg(&dc->vcpu_addr[cpu], 0);
atomic_xchg(&dc->page_fault_vcpu_time[cpu], 0);
atomic_dec(&dc->smp_cpus_down);
}
trace_mark_postcopy_blocktime_begin(addr, dc, dc->page_fault_vcpu_time[cpu],
cpu, already_received);
}
/*
* This function just provide calculated blocktime per cpu and trace it.
* Total blocktime is calculated in mark_postcopy_blocktime_end.
*
*
* Assume we have 3 CPU
*
* S1 E1 S1 E1
* -----***********------------xxx***************------------------------> CPU1
*
* S2 E2
* ------------****************xxx---------------------------------------> CPU2
*
* S3 E3
* ------------------------****xxx********-------------------------------> CPU3
*
* We have sequence S1,S2,E1,S3,S1,E2,E3,E1
* S2,E1 - doesn't match condition due to sequence S1,S2,E1 doesn't include CPU3
* S3,S1,E2 - sequence includes all CPUs, in this case overlap will be S1,E2 -
* it's a part of total blocktime.
* S1 - here is last_begin
* Legend of the picture is following:
* * - means blocktime per vCPU
* x - means overlapped blocktime (total blocktime)
*
* @addr: host virtual address
*/
static void mark_postcopy_blocktime_end(uintptr_t addr)
{
MigrationIncomingState *mis = migration_incoming_get_current();
PostcopyBlocktimeContext *dc = mis->blocktime_ctx;
int i, affected_cpu = 0;
bool vcpu_total_blocktime = false;
uint32_t read_vcpu_time, low_time_offset;
if (!dc) {
return;
}
low_time_offset = get_low_time_offset(dc);
/* lookup cpu, to clear it,
* that algorithm looks straighforward, but it's not
* optimal, more optimal algorithm is keeping tree or hash
* where key is address value is a list of */
for (i = 0; i < smp_cpus; i++) {
uint32_t vcpu_blocktime = 0;
read_vcpu_time = atomic_fetch_add(&dc->page_fault_vcpu_time[i], 0);
if (atomic_fetch_add(&dc->vcpu_addr[i], 0) != addr ||
read_vcpu_time == 0) {
continue;
}
atomic_xchg(&dc->vcpu_addr[i], 0);
vcpu_blocktime = low_time_offset - read_vcpu_time;
affected_cpu += 1;
/* we need to know is that mark_postcopy_end was due to
* faulted page, another possible case it's prefetched
* page and in that case we shouldn't be here */
if (!vcpu_total_blocktime &&
atomic_fetch_add(&dc->smp_cpus_down, 0) == smp_cpus) {
vcpu_total_blocktime = true;
}
/* continue cycle, due to one page could affect several vCPUs */
dc->vcpu_blocktime[i] += vcpu_blocktime;
}
atomic_sub(&dc->smp_cpus_down, affected_cpu);
if (vcpu_total_blocktime) {
dc->total_blocktime += low_time_offset - atomic_fetch_add(
&dc->last_begin, 0);
}
trace_mark_postcopy_blocktime_end(addr, dc, dc->total_blocktime,
affected_cpu);
}
static bool postcopy_pause_fault_thread(MigrationIncomingState *mis)
{
trace_postcopy_pause_fault_thread();
qemu_sem_wait(&mis->postcopy_pause_sem_fault);
trace_postcopy_pause_fault_thread_continued();
return true;
}
/*
* Handle faults detected by the USERFAULT markings
*/
static void *postcopy_ram_fault_thread(void *opaque)
{
MigrationIncomingState *mis = opaque;
struct uffd_msg msg;
int ret;
size_t index;
RAMBlock *rb = NULL;
trace_postcopy_ram_fault_thread_entry();
rcu_register_thread();
mis->last_rb = NULL; /* last RAMBlock we sent part of */
qemu_sem_post(&mis->fault_thread_sem);
struct pollfd *pfd;
size_t pfd_len = 2 + mis->postcopy_remote_fds->len;
pfd = g_new0(struct pollfd, pfd_len);
pfd[0].fd = mis->userfault_fd;
pfd[0].events = POLLIN;
pfd[1].fd = mis->userfault_event_fd;
pfd[1].events = POLLIN; /* Waiting for eventfd to go positive */
trace_postcopy_ram_fault_thread_fds_core(pfd[0].fd, pfd[1].fd);
for (index = 0; index < mis->postcopy_remote_fds->len; index++) {
struct PostCopyFD *pcfd = &g_array_index(mis->postcopy_remote_fds,
struct PostCopyFD, index);
pfd[2 + index].fd = pcfd->fd;
pfd[2 + index].events = POLLIN;
trace_postcopy_ram_fault_thread_fds_extra(2 + index, pcfd->idstr,
pcfd->fd);
}
while (true) {
ram_addr_t rb_offset;
int poll_result;
/*
* We're mainly waiting for the kernel to give us a faulting HVA,
* however we can be told to quit via userfault_quit_fd which is
* an eventfd
*/
poll_result = poll(pfd, pfd_len, -1 /* Wait forever */);
if (poll_result == -1) {
error_report("%s: userfault poll: %s", __func__, strerror(errno));
break;
}
if (!mis->to_src_file) {
/*
* Possibly someone tells us that the return path is
* broken already using the event. We should hold until
* the channel is rebuilt.
*/
if (postcopy_pause_fault_thread(mis)) {
mis->last_rb = NULL;
/* Continue to read the userfaultfd */
} else {
error_report("%s: paused but don't allow to continue",
__func__);
break;
}
}
if (pfd[1].revents) {
uint64_t tmp64 = 0;
/* Consume the signal */
if (read(mis->userfault_event_fd, &tmp64, 8) != 8) {
/* Nothing obviously nicer than posting this error. */
error_report("%s: read() failed", __func__);
}
if (atomic_read(&mis->fault_thread_quit)) {
trace_postcopy_ram_fault_thread_quit();
break;
}
}
if (pfd[0].revents) {
poll_result--;
ret = read(mis->userfault_fd, &msg, sizeof(msg));
if (ret != sizeof(msg)) {
if (errno == EAGAIN) {
/*
* if a wake up happens on the other thread just after
* the poll, there is nothing to read.
*/
continue;
}
if (ret < 0) {
error_report("%s: Failed to read full userfault "
"message: %s",
__func__, strerror(errno));
break;
} else {
error_report("%s: Read %d bytes from userfaultfd "
"expected %zd",
__func__, ret, sizeof(msg));
break; /* Lost alignment, don't know what we'd read next */
}
}
if (msg.event != UFFD_EVENT_PAGEFAULT) {
error_report("%s: Read unexpected event %ud from userfaultfd",
__func__, msg.event);
continue; /* It's not a page fault, shouldn't happen */
}
rb = qemu_ram_block_from_host(
(void *)(uintptr_t)msg.arg.pagefault.address,
true, &rb_offset);
if (!rb) {
error_report("postcopy_ram_fault_thread: Fault outside guest: %"
PRIx64, (uint64_t)msg.arg.pagefault.address);
break;
}
rb_offset &= ~(qemu_ram_pagesize(rb) - 1);
trace_postcopy_ram_fault_thread_request(msg.arg.pagefault.address,
qemu_ram_get_idstr(rb),
rb_offset,
msg.arg.pagefault.feat.ptid);
mark_postcopy_blocktime_begin(
(uintptr_t)(msg.arg.pagefault.address),
msg.arg.pagefault.feat.ptid, rb);
retry:
/*
* Send the request to the source - we want to request one
* of our host page sizes (which is >= TPS)
*/
if (rb != mis->last_rb) {
mis->last_rb = rb;
ret = migrate_send_rp_req_pages(mis,
qemu_ram_get_idstr(rb),
rb_offset,
qemu_ram_pagesize(rb));
} else {
/* Save some space */
ret = migrate_send_rp_req_pages(mis,
NULL,
rb_offset,
qemu_ram_pagesize(rb));
}
if (ret) {
/* May be network failure, try to wait for recovery */
if (ret == -EIO && postcopy_pause_fault_thread(mis)) {
/* We got reconnected somehow, try to continue */
mis->last_rb = NULL;
goto retry;
} else {
/* This is a unavoidable fault */
error_report("%s: migrate_send_rp_req_pages() get %d",
__func__, ret);
break;
}
}
}
/* Now handle any requests from external processes on shared memory */
/* TODO: May need to handle devices deregistering during postcopy */
for (index = 2; index < pfd_len && poll_result; index++) {
if (pfd[index].revents) {
struct PostCopyFD *pcfd =
&g_array_index(mis->postcopy_remote_fds,
struct PostCopyFD, index - 2);
poll_result--;
if (pfd[index].revents & POLLERR) {
error_report("%s: POLLERR on poll %zd fd=%d",
__func__, index, pcfd->fd);
pfd[index].events = 0;
continue;
}
ret = read(pcfd->fd, &msg, sizeof(msg));
if (ret != sizeof(msg)) {
if (errno == EAGAIN) {
/*
* if a wake up happens on the other thread just after
* the poll, there is nothing to read.
*/
continue;
}
if (ret < 0) {
error_report("%s: Failed to read full userfault "
"message: %s (shared) revents=%d",
__func__, strerror(errno),
pfd[index].revents);
/*TODO: Could just disable this sharer */
break;
} else {
error_report("%s: Read %d bytes from userfaultfd "
"expected %zd (shared)",
__func__, ret, sizeof(msg));
/*TODO: Could just disable this sharer */
break; /*Lost alignment,don't know what we'd read next*/
}
}
if (msg.event != UFFD_EVENT_PAGEFAULT) {
error_report("%s: Read unexpected event %ud "
"from userfaultfd (shared)",
__func__, msg.event);
continue; /* It's not a page fault, shouldn't happen */
}
/* Call the device handler registered with us */
ret = pcfd->handler(pcfd, &msg);
if (ret) {
error_report("%s: Failed to resolve shared fault on %zd/%s",
__func__, index, pcfd->idstr);
/* TODO: Fail? Disable this sharer? */
}
}
}
}
rcu_unregister_thread();
trace_postcopy_ram_fault_thread_exit();
g_free(pfd);
return NULL;
}
int postcopy_ram_enable_notify(MigrationIncomingState *mis)
{
/* Open the fd for the kernel to give us userfaults */
mis->userfault_fd = syscall(__NR_userfaultfd, O_CLOEXEC | O_NONBLOCK);
if (mis->userfault_fd == -1) {
error_report("%s: Failed to open userfault fd: %s", __func__,
strerror(errno));
return -1;
}
/*
* Although the host check already tested the API, we need to
* do the check again as an ABI handshake on the new fd.
*/
if (!ufd_check_and_apply(mis->userfault_fd, mis)) {
return -1;
}
/* Now an eventfd we use to tell the fault-thread to quit */
mis->userfault_event_fd = eventfd(0, EFD_CLOEXEC);
if (mis->userfault_event_fd == -1) {
error_report("%s: Opening userfault_event_fd: %s", __func__,
strerror(errno));
close(mis->userfault_fd);
return -1;
}
qemu_sem_init(&mis->fault_thread_sem, 0);
qemu_thread_create(&mis->fault_thread, "postcopy/fault",
postcopy_ram_fault_thread, mis, QEMU_THREAD_JOINABLE);
qemu_sem_wait(&mis->fault_thread_sem);
qemu_sem_destroy(&mis->fault_thread_sem);
mis->have_fault_thread = true;
/* Mark so that we get notified of accesses to unwritten areas */
if (foreach_not_ignored_block(ram_block_enable_notify, mis)) {
error_report("ram_block_enable_notify failed");
return -1;
}
/*
* Ballooning can mark pages as absent while we're postcopying
* that would cause false userfaults.
*/
postcopy_balloon_inhibit(true);
trace_postcopy_ram_enable_notify();
return 0;
}
static int qemu_ufd_copy_ioctl(int userfault_fd, void *host_addr,
void *from_addr, uint64_t pagesize, RAMBlock *rb)
{
int ret;
if (from_addr) {
struct uffdio_copy copy_struct;
copy_struct.dst = (uint64_t)(uintptr_t)host_addr;
copy_struct.src = (uint64_t)(uintptr_t)from_addr;
copy_struct.len = pagesize;
copy_struct.mode = 0;
ret = ioctl(userfault_fd, UFFDIO_COPY, ©_struct);
} else {
struct uffdio_zeropage zero_struct;
zero_struct.range.start = (uint64_t)(uintptr_t)host_addr;
zero_struct.range.len = pagesize;
zero_struct.mode = 0;
ret = ioctl(userfault_fd, UFFDIO_ZEROPAGE, &zero_struct);
}
if (!ret) {
ramblock_recv_bitmap_set_range(rb, host_addr,
pagesize / qemu_target_page_size());
mark_postcopy_blocktime_end((uintptr_t)host_addr);
}
return ret;
}
int postcopy_notify_shared_wake(RAMBlock *rb, uint64_t offset)
{
int i;
MigrationIncomingState *mis = migration_incoming_get_current();
GArray *pcrfds = mis->postcopy_remote_fds;
for (i = 0; i < pcrfds->len; i++) {
struct PostCopyFD *cur = &g_array_index(pcrfds, struct PostCopyFD, i);
int ret = cur->waker(cur, rb, offset);
if (ret) {
return ret;
}
}
return 0;
}
/*
* Place a host page (from) at (host) atomically
* returns 0 on success
*/
int postcopy_place_page(MigrationIncomingState *mis, void *host, void *from,
RAMBlock *rb)
{
size_t pagesize = qemu_ram_pagesize(rb);
/* copy also acks to the kernel waking the stalled thread up
* TODO: We can inhibit that ack and only do it if it was requested
* which would be slightly cheaper, but we'd have to be careful
* of the order of updating our page state.
*/
if (qemu_ufd_copy_ioctl(mis->userfault_fd, host, from, pagesize, rb)) {
int e = errno;
error_report("%s: %s copy host: %p from: %p (size: %zd)",
__func__, strerror(e), host, from, pagesize);
return -e;
}
trace_postcopy_place_page(host);
return postcopy_notify_shared_wake(rb,
qemu_ram_block_host_offset(rb, host));
}
/*
* Place a zero page at (host) atomically
* returns 0 on success
*/
int postcopy_place_page_zero(MigrationIncomingState *mis, void *host,
RAMBlock *rb)
{
size_t pagesize = qemu_ram_pagesize(rb);
trace_postcopy_place_page_zero(host);
/* Normal RAMBlocks can zero a page using UFFDIO_ZEROPAGE
* but it's not available for everything (e.g. hugetlbpages)
*/
if (qemu_ram_is_uf_zeroable(rb)) {
if (qemu_ufd_copy_ioctl(mis->userfault_fd, host, NULL, pagesize, rb)) {
int e = errno;
error_report("%s: %s zero host: %p",
__func__, strerror(e), host);
return -e;
}
return postcopy_notify_shared_wake(rb,
qemu_ram_block_host_offset(rb,
host));
} else {
/* The kernel can't use UFFDIO_ZEROPAGE for hugepages */
if (!mis->postcopy_tmp_zero_page) {
mis->postcopy_tmp_zero_page = mmap(NULL, mis->largest_page_size,
PROT_READ | PROT_WRITE,
MAP_PRIVATE | MAP_ANONYMOUS,
-1, 0);
if (mis->postcopy_tmp_zero_page == MAP_FAILED) {
int e = errno;
mis->postcopy_tmp_zero_page = NULL;
error_report("%s: %s mapping large zero page",
__func__, strerror(e));
return -e;
}
memset(mis->postcopy_tmp_zero_page, '\0', mis->largest_page_size);
}
return postcopy_place_page(mis, host, mis->postcopy_tmp_zero_page,
rb);
}
}
/*
* Returns a target page of memory that can be mapped at a later point in time
* using postcopy_place_page
* The same address is used repeatedly, postcopy_place_page just takes the
* backing page away.
* Returns: Pointer to allocated page
*
*/
void *postcopy_get_tmp_page(MigrationIncomingState *mis)
{
if (!mis->postcopy_tmp_page) {
mis->postcopy_tmp_page = mmap(NULL, mis->largest_page_size,
PROT_READ | PROT_WRITE, MAP_PRIVATE |
MAP_ANONYMOUS, -1, 0);
if (mis->postcopy_tmp_page == MAP_FAILED) {
mis->postcopy_tmp_page = NULL;
error_report("%s: %s", __func__, strerror(errno));
return NULL;
}
}
return mis->postcopy_tmp_page;
}
#else
/* No target OS support, stubs just fail */
void fill_destination_postcopy_migration_info(MigrationInfo *info)
{
}
bool postcopy_ram_supported_by_host(MigrationIncomingState *mis)
{
error_report("%s: No OS support", __func__);
return false;
}
int postcopy_ram_incoming_init(MigrationIncomingState *mis)
{
error_report("postcopy_ram_incoming_init: No OS support");
return -1;
}
int postcopy_ram_incoming_cleanup(MigrationIncomingState *mis)
{
assert(0);
return -1;
}
int postcopy_ram_prepare_discard(MigrationIncomingState *mis)
{
assert(0);
return -1;
}
int postcopy_request_shared_page(struct PostCopyFD *pcfd, RAMBlock *rb,
uint64_t client_addr, uint64_t rb_offset)
{
assert(0);
return -1;
}
int postcopy_ram_enable_notify(MigrationIncomingState *mis)
{
assert(0);
return -1;
}
int postcopy_place_page(MigrationIncomingState *mis, void *host, void *from,
RAMBlock *rb)
{
assert(0);
return -1;
}
int postcopy_place_page_zero(MigrationIncomingState *mis, void *host,
RAMBlock *rb)
{
assert(0);
return -1;
}
void *postcopy_get_tmp_page(MigrationIncomingState *mis)
{
assert(0);
return NULL;
}
int postcopy_wake_shared(struct PostCopyFD *pcfd,
uint64_t client_addr,
RAMBlock *rb)
{
assert(0);
return -1;
}
#endif
/* ------------------------------------------------------------------------- */
void postcopy_fault_thread_notify(MigrationIncomingState *mis)
{
uint64_t tmp64 = 1;
/*
* Wakeup the fault_thread. It's an eventfd that should currently
* be at 0, we're going to increment it to 1
*/
if (write(mis->userfault_event_fd, &tmp64, 8) != 8) {
/* Not much we can do here, but may as well report it */
error_report("%s: incrementing failed: %s", __func__,
strerror(errno));
}
}
/**
* postcopy_discard_send_init: Called at the start of each RAMBlock before
* asking to discard individual ranges.
*
* @ms: The current migration state.
* @offset: the bitmap offset of the named RAMBlock in the migration
* bitmap.
* @name: RAMBlock that discards will operate on.
*
* returns: a new PDS.
*/
PostcopyDiscardState *postcopy_discard_send_init(MigrationState *ms,
const char *name)
{
PostcopyDiscardState *res = g_malloc0(sizeof(PostcopyDiscardState));
if (res) {
res->ramblock_name = name;
}
return res;
}
/**
* postcopy_discard_send_range: Called by the bitmap code for each chunk to
* discard. May send a discard message, may just leave it queued to
* be sent later.
*
* @ms: Current migration state.
* @pds: Structure initialised by postcopy_discard_send_init().
* @start,@length: a range of pages in the migration bitmap in the
* RAM block passed to postcopy_discard_send_init() (length=1 is one page)
*/
void postcopy_discard_send_range(MigrationState *ms, PostcopyDiscardState *pds,
unsigned long start, unsigned long length)
{
size_t tp_size = qemu_target_page_size();
/* Convert to byte offsets within the RAM block */
pds->start_list[pds->cur_entry] = start * tp_size;
pds->length_list[pds->cur_entry] = length * tp_size;
trace_postcopy_discard_send_range(pds->ramblock_name, start, length);
pds->cur_entry++;
pds->nsentwords++;
if (pds->cur_entry == MAX_DISCARDS_PER_COMMAND) {
/* Full set, ship it! */
qemu_savevm_send_postcopy_ram_discard(ms->to_dst_file,
pds->ramblock_name,
pds->cur_entry,
pds->start_list,
pds->length_list);
pds->nsentcmds++;
pds->cur_entry = 0;
}
}
/**
* postcopy_discard_send_finish: Called at the end of each RAMBlock by the
* bitmap code. Sends any outstanding discard messages, frees the PDS
*
* @ms: Current migration state.
* @pds: Structure initialised by postcopy_discard_send_init().
*/
void postcopy_discard_send_finish(MigrationState *ms, PostcopyDiscardState *pds)
{
/* Anything unsent? */
if (pds->cur_entry) {
qemu_savevm_send_postcopy_ram_discard(ms->to_dst_file,
pds->ramblock_name,
pds->cur_entry,
pds->start_list,
pds->length_list);
pds->nsentcmds++;
}
trace_postcopy_discard_send_finish(pds->ramblock_name, pds->nsentwords,
pds->nsentcmds);
g_free(pds);
}
/*
* Current state of incoming postcopy; note this is not part of
* MigrationIncomingState since it's state is used during cleanup
* at the end as MIS is being freed.
*/
static PostcopyState incoming_postcopy_state;
PostcopyState postcopy_state_get(void)
{
return atomic_mb_read(&incoming_postcopy_state);
}
/* Set the state and return the old state */
PostcopyState postcopy_state_set(PostcopyState new_state)
{
return atomic_xchg(&incoming_postcopy_state, new_state);
}
/* Register a handler for external shared memory postcopy
* called on the destination.
*/
void postcopy_register_shared_ufd(struct PostCopyFD *pcfd)
{
MigrationIncomingState *mis = migration_incoming_get_current();
mis->postcopy_remote_fds = g_array_append_val(mis->postcopy_remote_fds,
*pcfd);
}
/* Unregister a handler for external shared memory postcopy
*/
void postcopy_unregister_shared_ufd(struct PostCopyFD *pcfd)
{
guint i;
MigrationIncomingState *mis = migration_incoming_get_current();
GArray *pcrfds = mis->postcopy_remote_fds;
for (i = 0; i < pcrfds->len; i++) {
struct PostCopyFD *cur = &g_array_index(pcrfds, struct PostCopyFD, i);
if (cur->fd == pcfd->fd) {
mis->postcopy_remote_fds = g_array_remove_index(pcrfds, i);
return;
}
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/block/throttle-groups.c | /*
* QEMU block throttling group infrastructure
*
* Copyright (C) Nodalink, EURL. 2014
* Copyright (C) Igalia, S.L. 2015
*
* Authors:
* <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "sysemu/block-backend.h"
#include "block/throttle-groups.h"
#include "qemu/throttle-options.h"
#include "qemu/queue.h"
#include "qemu/thread.h"
#include "sysemu/qtest.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-block-core.h"
#include "qom/object.h"
#include "qom/object_interfaces.h"
static void throttle_group_obj_init(Object *obj);
static void throttle_group_obj_complete(UserCreatable *obj, Error **errp);
static void timer_cb(ThrottleGroupMember *tgm, bool is_write);
/* The ThrottleGroup structure (with its ThrottleState) is shared
* among different ThrottleGroupMembers and it's independent from
* AioContext, so in order to use it from different threads it needs
* its own locking.
*
* This locking is however handled internally in this file, so it's
* transparent to outside users.
*
* The whole ThrottleGroup structure is private and invisible to
* outside users, that only use it through its ThrottleState.
*
* In addition to the ThrottleGroup structure, ThrottleGroupMember has
* fields that need to be accessed by other members of the group and
* therefore also need to be protected by this lock. Once a
* ThrottleGroupMember is registered in a group those fields can be accessed
* by other threads any time.
*
* Again, all this is handled internally and is mostly transparent to
* the outside. The 'throttle_timers' field however has an additional
* constraint because it may be temporarily invalid (see for example
* blk_set_aio_context()). Therefore in this file a thread will
* access some other ThrottleGroupMember's timers only after verifying that
* that ThrottleGroupMember has throttled requests in the queue.
*/
typedef struct ThrottleGroup {
Object parent_obj;
/* refuse individual property change if initialization is complete */
bool is_initialized;
char *name; /* This is constant during the lifetime of the group */
QemuMutex lock; /* This lock protects the following four fields */
ThrottleState ts;
QLIST_HEAD(, ThrottleGroupMember) head;
ThrottleGroupMember *tokens[2];
bool any_timer_armed[2];
QEMUClockType clock_type;
/* This field is protected by the global QEMU mutex */
QTAILQ_ENTRY(ThrottleGroup) list;
} ThrottleGroup;
/* This is protected by the global QEMU mutex */
static QTAILQ_HEAD(, ThrottleGroup) throttle_groups =
QTAILQ_HEAD_INITIALIZER(throttle_groups);
/* This function reads throttle_groups and must be called under the global
* mutex.
*/
static ThrottleGroup *throttle_group_by_name(const char *name)
{
ThrottleGroup *iter;
/* Look for an existing group with that name */
QTAILQ_FOREACH(iter, &throttle_groups, list) {
if (!g_strcmp0(name, iter->name)) {
return iter;
}
}
return NULL;
}
/* This function reads throttle_groups and must be called under the global
* mutex.
*/
bool throttle_group_exists(const char *name)
{
return throttle_group_by_name(name) != NULL;
}
/* Increments the reference count of a ThrottleGroup given its name.
*
* If no ThrottleGroup is found with the given name a new one is
* created.
*
* This function edits throttle_groups and must be called under the global
* mutex.
*
* @name: the name of the ThrottleGroup
* @ret: the ThrottleState member of the ThrottleGroup
*/
ThrottleState *throttle_group_incref(const char *name)
{
ThrottleGroup *tg = NULL;
/* Look for an existing group with that name */
tg = throttle_group_by_name(name);
if (tg) {
object_ref(OBJECT(tg));
} else {
/* Create a new one if not found */
/* new ThrottleGroup obj will have a refcnt = 1 */
tg = THROTTLE_GROUP(object_new(TYPE_THROTTLE_GROUP));
tg->name = g_strdup(name);
throttle_group_obj_complete(USER_CREATABLE(tg), &error_abort);
}
return &tg->ts;
}
/* Decrease the reference count of a ThrottleGroup.
*
* When the reference count reaches zero the ThrottleGroup is
* destroyed.
*
* This function edits throttle_groups and must be called under the global
* mutex.
*
* @ts: The ThrottleGroup to unref, given by its ThrottleState member
*/
void throttle_group_unref(ThrottleState *ts)
{
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
object_unref(OBJECT(tg));
}
/* Get the name from a ThrottleGroupMember's group. The name (and the pointer)
* is guaranteed to remain constant during the lifetime of the group.
*
* @tgm: a ThrottleGroupMember
* @ret: the name of the group.
*/
const char *throttle_group_get_name(ThrottleGroupMember *tgm)
{
ThrottleGroup *tg = container_of(tgm->throttle_state, ThrottleGroup, ts);
return tg->name;
}
/* Return the next ThrottleGroupMember in the round-robin sequence, simulating
* a circular list.
*
* This assumes that tg->lock is held.
*
* @tgm: the current ThrottleGroupMember
* @ret: the next ThrottleGroupMember in the sequence
*/
static ThrottleGroupMember *throttle_group_next_tgm(ThrottleGroupMember *tgm)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
ThrottleGroupMember *next = QLIST_NEXT(tgm, round_robin);
if (!next) {
next = QLIST_FIRST(&tg->head);
}
return next;
}
/*
* Return whether a ThrottleGroupMember has pending requests.
*
* This assumes that tg->lock is held.
*
* @tgm: the ThrottleGroupMember
* @is_write: the type of operation (read/write)
* @ret: whether the ThrottleGroupMember has pending requests.
*/
static inline bool tgm_has_pending_reqs(ThrottleGroupMember *tgm,
bool is_write)
{
return tgm->pending_reqs[is_write];
}
/* Return the next ThrottleGroupMember in the round-robin sequence with pending
* I/O requests.
*
* This assumes that tg->lock is held.
*
* @tgm: the current ThrottleGroupMember
* @is_write: the type of operation (read/write)
* @ret: the next ThrottleGroupMember with pending requests, or tgm if
* there is none.
*/
static ThrottleGroupMember *next_throttle_token(ThrottleGroupMember *tgm,
bool is_write)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
ThrottleGroupMember *token, *start;
/* If this member has its I/O limits disabled then it means that
* it's being drained. Skip the round-robin search and return tgm
* immediately if it has pending requests. Otherwise we could be
* forcing it to wait for other member's throttled requests. */
if (tgm_has_pending_reqs(tgm, is_write) &&
atomic_read(&tgm->io_limits_disabled)) {
return tgm;
}
start = token = tg->tokens[is_write];
/* get next bs round in round robin style */
token = throttle_group_next_tgm(token);
while (token != start && !tgm_has_pending_reqs(token, is_write)) {
token = throttle_group_next_tgm(token);
}
/* If no IO are queued for scheduling on the next round robin token
* then decide the token is the current tgm because chances are
* the current tgm got the current request queued.
*/
if (token == start && !tgm_has_pending_reqs(token, is_write)) {
token = tgm;
}
/* Either we return the original TGM, or one with pending requests */
assert(token == tgm || tgm_has_pending_reqs(token, is_write));
return token;
}
/* Check if the next I/O request for a ThrottleGroupMember needs to be
* throttled or not. If there's no timer set in this group, set one and update
* the token accordingly.
*
* This assumes that tg->lock is held.
*
* @tgm: the current ThrottleGroupMember
* @is_write: the type of operation (read/write)
* @ret: whether the I/O request needs to be throttled or not
*/
static bool throttle_group_schedule_timer(ThrottleGroupMember *tgm,
bool is_write)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
ThrottleTimers *tt = &tgm->throttle_timers;
bool must_wait;
if (atomic_read(&tgm->io_limits_disabled)) {
return false;
}
/* Check if any of the timers in this group is already armed */
if (tg->any_timer_armed[is_write]) {
return true;
}
must_wait = throttle_schedule_timer(ts, tt, is_write);
/* If a timer just got armed, set tgm as the current token */
if (must_wait) {
tg->tokens[is_write] = tgm;
tg->any_timer_armed[is_write] = true;
}
return must_wait;
}
/* Start the next pending I/O request for a ThrottleGroupMember. Return whether
* any request was actually pending.
*
* @tgm: the current ThrottleGroupMember
* @is_write: the type of operation (read/write)
*/
static bool coroutine_fn throttle_group_co_restart_queue(ThrottleGroupMember *tgm,
bool is_write)
{
bool ret;
qemu_co_mutex_lock(&tgm->throttled_reqs_lock);
ret = qemu_co_queue_next(&tgm->throttled_reqs[is_write]);
qemu_co_mutex_unlock(&tgm->throttled_reqs_lock);
return ret;
}
/* Look for the next pending I/O request and schedule it.
*
* This assumes that tg->lock is held.
*
* @tgm: the current ThrottleGroupMember
* @is_write: the type of operation (read/write)
*/
static void schedule_next_request(ThrottleGroupMember *tgm, bool is_write)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
bool must_wait;
ThrottleGroupMember *token;
/* Check if there's any pending request to schedule next */
token = next_throttle_token(tgm, is_write);
if (!tgm_has_pending_reqs(token, is_write)) {
return;
}
/* Set a timer for the request if it needs to be throttled */
must_wait = throttle_group_schedule_timer(token, is_write);
/* If it doesn't have to wait, queue it for immediate execution */
if (!must_wait) {
/* Give preference to requests from the current tgm */
if (qemu_in_coroutine() &&
throttle_group_co_restart_queue(tgm, is_write)) {
token = tgm;
} else {
ThrottleTimers *tt = &token->throttle_timers;
int64_t now = qemu_clock_get_ns(tg->clock_type);
timer_mod(tt->timers[is_write], now);
tg->any_timer_armed[is_write] = true;
}
tg->tokens[is_write] = token;
}
}
/* Check if an I/O request needs to be throttled, wait and set a timer
* if necessary, and schedule the next request using a round robin
* algorithm.
*
* @tgm: the current ThrottleGroupMember
* @bytes: the number of bytes for this I/O
* @is_write: the type of operation (read/write)
*/
void coroutine_fn throttle_group_co_io_limits_intercept(ThrottleGroupMember *tgm,
unsigned int bytes,
bool is_write)
{
bool must_wait;
ThrottleGroupMember *token;
ThrottleGroup *tg = container_of(tgm->throttle_state, ThrottleGroup, ts);
qemu_mutex_lock(&tg->lock);
/* First we check if this I/O has to be throttled. */
token = next_throttle_token(tgm, is_write);
must_wait = throttle_group_schedule_timer(token, is_write);
/* Wait if there's a timer set or queued requests of this type */
if (must_wait || tgm->pending_reqs[is_write]) {
tgm->pending_reqs[is_write]++;
qemu_mutex_unlock(&tg->lock);
qemu_co_mutex_lock(&tgm->throttled_reqs_lock);
qemu_co_queue_wait(&tgm->throttled_reqs[is_write],
&tgm->throttled_reqs_lock);
qemu_co_mutex_unlock(&tgm->throttled_reqs_lock);
qemu_mutex_lock(&tg->lock);
tgm->pending_reqs[is_write]--;
}
/* The I/O will be executed, so do the accounting */
throttle_account(tgm->throttle_state, is_write, bytes);
/* Schedule the next request */
schedule_next_request(tgm, is_write);
qemu_mutex_unlock(&tg->lock);
}
typedef struct {
ThrottleGroupMember *tgm;
bool is_write;
} RestartData;
static void coroutine_fn throttle_group_restart_queue_entry(void *opaque)
{
RestartData *data = opaque;
ThrottleGroupMember *tgm = data->tgm;
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
bool is_write = data->is_write;
bool empty_queue;
empty_queue = !throttle_group_co_restart_queue(tgm, is_write);
/* If the request queue was empty then we have to take care of
* scheduling the next one */
if (empty_queue) {
qemu_mutex_lock(&tg->lock);
schedule_next_request(tgm, is_write);
qemu_mutex_unlock(&tg->lock);
}
g_free(data);
atomic_dec(&tgm->restart_pending);
aio_wait_kick();
}
static void throttle_group_restart_queue(ThrottleGroupMember *tgm, bool is_write)
{
Coroutine *co;
RestartData *rd = g_new0(RestartData, 1);
rd->tgm = tgm;
rd->is_write = is_write;
/* This function is called when a timer is fired or when
* throttle_group_restart_tgm() is called. Either way, there can
* be no timer pending on this tgm at this point */
assert(!timer_pending(tgm->throttle_timers.timers[is_write]));
atomic_inc(&tgm->restart_pending);
co = qemu_coroutine_create(throttle_group_restart_queue_entry, rd);
aio_co_enter(tgm->aio_context, co);
}
void throttle_group_restart_tgm(ThrottleGroupMember *tgm)
{
int i;
if (tgm->throttle_state) {
for (i = 0; i < 2; i++) {
QEMUTimer *t = tgm->throttle_timers.timers[i];
if (timer_pending(t)) {
/* If there's a pending timer on this tgm, fire it now */
timer_del(t);
timer_cb(tgm, i);
} else {
/* Else run the next request from the queue manually */
throttle_group_restart_queue(tgm, i);
}
}
}
}
/* Update the throttle configuration for a particular group. Similar
* to throttle_config(), but guarantees atomicity within the
* throttling group.
*
* @tgm: a ThrottleGroupMember that is a member of the group
* @cfg: the configuration to set
*/
void throttle_group_config(ThrottleGroupMember *tgm, ThrottleConfig *cfg)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
qemu_mutex_lock(&tg->lock);
throttle_config(ts, tg->clock_type, cfg);
qemu_mutex_unlock(&tg->lock);
throttle_group_restart_tgm(tgm);
}
/* Get the throttle configuration from a particular group. Similar to
* throttle_get_config(), but guarantees atomicity within the
* throttling group.
*
* @tgm: a ThrottleGroupMember that is a member of the group
* @cfg: the configuration will be written here
*/
void throttle_group_get_config(ThrottleGroupMember *tgm, ThrottleConfig *cfg)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
qemu_mutex_lock(&tg->lock);
throttle_get_config(ts, cfg);
qemu_mutex_unlock(&tg->lock);
}
/* ThrottleTimers callback. This wakes up a request that was waiting
* because it had been throttled.
*
* @tgm: the ThrottleGroupMember whose request had been throttled
* @is_write: the type of operation (read/write)
*/
static void timer_cb(ThrottleGroupMember *tgm, bool is_write)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
/* The timer has just been fired, so we can update the flag */
qemu_mutex_lock(&tg->lock);
tg->any_timer_armed[is_write] = false;
qemu_mutex_unlock(&tg->lock);
/* Run the request that was waiting for this timer */
throttle_group_restart_queue(tgm, is_write);
}
static void read_timer_cb(void *opaque)
{
timer_cb(opaque, false);
}
static void write_timer_cb(void *opaque)
{
timer_cb(opaque, true);
}
/* Register a ThrottleGroupMember from the throttling group, also initializing
* its timers and updating its throttle_state pointer to point to it. If a
* throttling group with that name does not exist yet, it will be created.
*
* This function edits throttle_groups and must be called under the global
* mutex.
*
* @tgm: the ThrottleGroupMember to insert
* @groupname: the name of the group
* @ctx: the AioContext to use
*/
void throttle_group_register_tgm(ThrottleGroupMember *tgm,
const char *groupname,
AioContext *ctx)
{
int i;
ThrottleState *ts = throttle_group_incref(groupname);
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
tgm->throttle_state = ts;
tgm->aio_context = ctx;
atomic_set(&tgm->restart_pending, 0);
qemu_mutex_lock(&tg->lock);
/* If the ThrottleGroup is new set this ThrottleGroupMember as the token */
for (i = 0; i < 2; i++) {
if (!tg->tokens[i]) {
tg->tokens[i] = tgm;
}
}
QLIST_INSERT_HEAD(&tg->head, tgm, round_robin);
throttle_timers_init(&tgm->throttle_timers,
tgm->aio_context,
tg->clock_type,
read_timer_cb,
write_timer_cb,
tgm);
qemu_co_mutex_init(&tgm->throttled_reqs_lock);
qemu_co_queue_init(&tgm->throttled_reqs[0]);
qemu_co_queue_init(&tgm->throttled_reqs[1]);
qemu_mutex_unlock(&tg->lock);
}
/* Unregister a ThrottleGroupMember from its group, removing it from the list,
* destroying the timers and setting the throttle_state pointer to NULL.
*
* The ThrottleGroupMember must not have pending throttled requests, so the
* caller has to drain them first.
*
* The group will be destroyed if it's empty after this operation.
*
* @tgm the ThrottleGroupMember to remove
*/
void throttle_group_unregister_tgm(ThrottleGroupMember *tgm)
{
ThrottleState *ts = tgm->throttle_state;
ThrottleGroup *tg = container_of(ts, ThrottleGroup, ts);
ThrottleGroupMember *token;
int i;
if (!ts) {
/* Discard already unregistered tgm */
return;
}
/* Wait for throttle_group_restart_queue_entry() coroutines to finish */
AIO_WAIT_WHILE(tgm->aio_context, atomic_read(&tgm->restart_pending) > 0);
qemu_mutex_lock(&tg->lock);
for (i = 0; i < 2; i++) {
assert(tgm->pending_reqs[i] == 0);
assert(qemu_co_queue_empty(&tgm->throttled_reqs[i]));
assert(!timer_pending(tgm->throttle_timers.timers[i]));
if (tg->tokens[i] == tgm) {
token = throttle_group_next_tgm(tgm);
/* Take care of the case where this is the last tgm in the group */
if (token == tgm) {
token = NULL;
}
tg->tokens[i] = token;
}
}
/* remove the current tgm from the list */
QLIST_REMOVE(tgm, round_robin);
throttle_timers_destroy(&tgm->throttle_timers);
qemu_mutex_unlock(&tg->lock);
throttle_group_unref(&tg->ts);
tgm->throttle_state = NULL;
}
void throttle_group_attach_aio_context(ThrottleGroupMember *tgm,
AioContext *new_context)
{
ThrottleTimers *tt = &tgm->throttle_timers;
throttle_timers_attach_aio_context(tt, new_context);
tgm->aio_context = new_context;
}
void throttle_group_detach_aio_context(ThrottleGroupMember *tgm)
{
ThrottleGroup *tg = container_of(tgm->throttle_state, ThrottleGroup, ts);
ThrottleTimers *tt = &tgm->throttle_timers;
int i;
/* Requests must have been drained */
assert(tgm->pending_reqs[0] == 0 && tgm->pending_reqs[1] == 0);
assert(qemu_co_queue_empty(&tgm->throttled_reqs[0]));
assert(qemu_co_queue_empty(&tgm->throttled_reqs[1]));
/* Kick off next ThrottleGroupMember, if necessary */
qemu_mutex_lock(&tg->lock);
for (i = 0; i < 2; i++) {
if (timer_pending(tt->timers[i])) {
tg->any_timer_armed[i] = false;
schedule_next_request(tgm, i);
}
}
qemu_mutex_unlock(&tg->lock);
throttle_timers_detach_aio_context(tt);
tgm->aio_context = NULL;
}
#undef THROTTLE_OPT_PREFIX
#define THROTTLE_OPT_PREFIX "x-"
/* Helper struct and array for QOM property setter/getter */
typedef struct {
const char *name;
BucketType type;
enum {
AVG,
MAX,
BURST_LENGTH,
IOPS_SIZE,
} category;
} ThrottleParamInfo;
static ThrottleParamInfo properties[] = {
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_TOTAL,
THROTTLE_OPS_TOTAL, AVG,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_TOTAL_MAX,
THROTTLE_OPS_TOTAL, MAX,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_TOTAL_MAX_LENGTH,
THROTTLE_OPS_TOTAL, BURST_LENGTH,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_READ,
THROTTLE_OPS_READ, AVG,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_READ_MAX,
THROTTLE_OPS_READ, MAX,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_READ_MAX_LENGTH,
THROTTLE_OPS_READ, BURST_LENGTH,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_WRITE,
THROTTLE_OPS_WRITE, AVG,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_WRITE_MAX,
THROTTLE_OPS_WRITE, MAX,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_WRITE_MAX_LENGTH,
THROTTLE_OPS_WRITE, BURST_LENGTH,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_TOTAL,
THROTTLE_BPS_TOTAL, AVG,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_TOTAL_MAX,
THROTTLE_BPS_TOTAL, MAX,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_TOTAL_MAX_LENGTH,
THROTTLE_BPS_TOTAL, BURST_LENGTH,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_READ,
THROTTLE_BPS_READ, AVG,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_READ_MAX,
THROTTLE_BPS_READ, MAX,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_READ_MAX_LENGTH,
THROTTLE_BPS_READ, BURST_LENGTH,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_WRITE,
THROTTLE_BPS_WRITE, AVG,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_WRITE_MAX,
THROTTLE_BPS_WRITE, MAX,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_BPS_WRITE_MAX_LENGTH,
THROTTLE_BPS_WRITE, BURST_LENGTH,
},
{
THROTTLE_OPT_PREFIX QEMU_OPT_IOPS_SIZE,
0, IOPS_SIZE,
}
};
/* This function edits throttle_groups and must be called under the global
* mutex */
static void throttle_group_obj_init(Object *obj)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
tg->clock_type = QEMU_CLOCK_REALTIME;
if (qtest_enabled()) {
/* For testing block IO throttling only */
tg->clock_type = QEMU_CLOCK_VIRTUAL;
}
tg->is_initialized = false;
qemu_mutex_init(&tg->lock);
throttle_init(&tg->ts);
QLIST_INIT(&tg->head);
}
/* This function edits throttle_groups and must be called under the global
* mutex */
static void throttle_group_obj_complete(UserCreatable *obj, Error **errp)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
ThrottleConfig cfg;
/* set group name to object id if it exists */
if (!tg->name && tg->parent_obj.parent) {
tg->name = object_get_canonical_path_component(OBJECT(obj));
}
/* We must have a group name at this point */
assert(tg->name);
/* error if name is duplicate */
if (throttle_group_exists(tg->name)) {
error_setg(errp, "A group with this name already exists");
return;
}
/* check validity */
throttle_get_config(&tg->ts, &cfg);
if (!throttle_is_valid(&cfg, errp)) {
return;
}
throttle_config(&tg->ts, tg->clock_type, &cfg);
QTAILQ_INSERT_TAIL(&throttle_groups, tg, list);
tg->is_initialized = true;
}
/* This function edits throttle_groups and must be called under the global
* mutex */
static void throttle_group_obj_finalize(Object *obj)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
if (tg->is_initialized) {
QTAILQ_REMOVE(&throttle_groups, tg, list);
}
qemu_mutex_destroy(&tg->lock);
g_free(tg->name);
}
static void throttle_group_set(Object *obj, Visitor *v, const char * name,
void *opaque, Error **errp)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
ThrottleConfig *cfg;
ThrottleParamInfo *info = opaque;
Error *local_err = NULL;
int64_t value;
/* If we have finished initialization, don't accept individual property
* changes through QOM. Throttle configuration limits must be set in one
* transaction, as certain combinations are invalid.
*/
if (tg->is_initialized) {
error_setg(&local_err, "Property cannot be set after initialization");
goto ret;
}
visit_type_int64(v, name, &value, &local_err);
if (local_err) {
goto ret;
}
if (value < 0) {
error_setg(&local_err, "Property values cannot be negative");
goto ret;
}
cfg = &tg->ts.cfg;
switch (info->category) {
case AVG:
cfg->buckets[info->type].avg = value;
break;
case MAX:
cfg->buckets[info->type].max = value;
break;
case BURST_LENGTH:
if (value > UINT_MAX) {
error_setg(&local_err, "%s value must be in the"
"range [0, %u]", info->name, UINT_MAX);
goto ret;
}
cfg->buckets[info->type].burst_length = value;
break;
case IOPS_SIZE:
cfg->op_size = value;
break;
}
ret:
error_propagate(errp, local_err);
return;
}
static void throttle_group_get(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
ThrottleConfig cfg;
ThrottleParamInfo *info = opaque;
int64_t value;
throttle_get_config(&tg->ts, &cfg);
switch (info->category) {
case AVG:
value = cfg.buckets[info->type].avg;
break;
case MAX:
value = cfg.buckets[info->type].max;
break;
case BURST_LENGTH:
value = cfg.buckets[info->type].burst_length;
break;
case IOPS_SIZE:
value = cfg.op_size;
break;
}
visit_type_int64(v, name, &value, errp);
}
static void throttle_group_set_limits(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
ThrottleConfig cfg;
ThrottleLimits arg = { 0 };
ThrottleLimits *argp = &arg;
Error *local_err = NULL;
visit_type_ThrottleLimits(v, name, &argp, &local_err);
if (local_err) {
goto ret;
}
qemu_mutex_lock(&tg->lock);
throttle_get_config(&tg->ts, &cfg);
throttle_limits_to_config(argp, &cfg, &local_err);
if (local_err) {
goto unlock;
}
throttle_config(&tg->ts, tg->clock_type, &cfg);
unlock:
qemu_mutex_unlock(&tg->lock);
ret:
error_propagate(errp, local_err);
return;
}
static void throttle_group_get_limits(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
ThrottleGroup *tg = THROTTLE_GROUP(obj);
ThrottleConfig cfg;
ThrottleLimits arg = { 0 };
ThrottleLimits *argp = &arg;
qemu_mutex_lock(&tg->lock);
throttle_get_config(&tg->ts, &cfg);
qemu_mutex_unlock(&tg->lock);
throttle_config_to_limits(&cfg, argp);
visit_type_ThrottleLimits(v, name, &argp, errp);
}
static bool throttle_group_can_be_deleted(UserCreatable *uc)
{
return OBJECT(uc)->ref == 1;
}
static void throttle_group_obj_class_init(ObjectClass *klass, void *class_data)
{
size_t i = 0;
UserCreatableClass *ucc = USER_CREATABLE_CLASS(klass);
ucc->complete = throttle_group_obj_complete;
ucc->can_be_deleted = throttle_group_can_be_deleted;
/* individual properties */
for (i = 0; i < sizeof(properties) / sizeof(ThrottleParamInfo); i++) {
object_class_property_add(klass,
properties[i].name,
"int",
throttle_group_get,
throttle_group_set,
NULL, &properties[i],
&error_abort);
}
/* ThrottleLimits */
object_class_property_add(klass,
"limits", "ThrottleLimits",
throttle_group_get_limits,
throttle_group_set_limits,
NULL, NULL,
&error_abort);
}
static const TypeInfo throttle_group_info = {
.name = TYPE_THROTTLE_GROUP,
.parent = TYPE_OBJECT,
.class_init = throttle_group_obj_class_init,
.instance_size = sizeof(ThrottleGroup),
.instance_init = throttle_group_obj_init,
.instance_finalize = throttle_group_obj_finalize,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
{ }
},
};
static void throttle_groups_init(void)
{
type_register_static(&throttle_group_info);
}
type_init(throttle_groups_init);
|
pmp-tool/PMP | src/qemu/src-pmp/block/copy-on-read.c | <gh_stars>1-10
/*
* Copy-on-read filter block driver
*
* Copyright (c) 2018 Red Hat, Inc.
*
* Author:
* <NAME> <<EMAIL>>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "block/block_int.h"
static int cor_open(BlockDriverState *bs, QDict *options, int flags,
Error **errp)
{
bs->file = bdrv_open_child(NULL, options, "file", bs, &child_file, false,
errp);
if (!bs->file) {
return -EINVAL;
}
bs->supported_write_flags = BDRV_REQ_WRITE_UNCHANGED |
(BDRV_REQ_FUA & bs->file->bs->supported_write_flags);
bs->supported_zero_flags = BDRV_REQ_WRITE_UNCHANGED |
((BDRV_REQ_FUA | BDRV_REQ_MAY_UNMAP | BDRV_REQ_NO_FALLBACK) &
bs->file->bs->supported_zero_flags);
return 0;
}
#define PERM_PASSTHROUGH (BLK_PERM_CONSISTENT_READ \
| BLK_PERM_WRITE \
| BLK_PERM_RESIZE)
#define PERM_UNCHANGED (BLK_PERM_ALL & ~PERM_PASSTHROUGH)
static void cor_child_perm(BlockDriverState *bs, BdrvChild *c,
const BdrvChildRole *role,
BlockReopenQueue *reopen_queue,
uint64_t perm, uint64_t shared,
uint64_t *nperm, uint64_t *nshared)
{
if (c == NULL) {
*nperm = (perm & PERM_PASSTHROUGH) | BLK_PERM_WRITE_UNCHANGED;
*nshared = (shared & PERM_PASSTHROUGH) | PERM_UNCHANGED;
return;
}
*nperm = (perm & PERM_PASSTHROUGH) |
(c->perm & PERM_UNCHANGED);
*nshared = (shared & PERM_PASSTHROUGH) |
(c->shared_perm & PERM_UNCHANGED);
}
static int64_t cor_getlength(BlockDriverState *bs)
{
return bdrv_getlength(bs->file->bs);
}
static int coroutine_fn cor_co_truncate(BlockDriverState *bs, int64_t offset,
PreallocMode prealloc, Error **errp)
{
return bdrv_co_truncate(bs->file, offset, prealloc, errp);
}
static int coroutine_fn cor_co_preadv(BlockDriverState *bs,
uint64_t offset, uint64_t bytes,
QEMUIOVector *qiov, int flags)
{
return bdrv_co_preadv(bs->file, offset, bytes, qiov,
flags | BDRV_REQ_COPY_ON_READ);
}
static int coroutine_fn cor_co_pwritev(BlockDriverState *bs,
uint64_t offset, uint64_t bytes,
QEMUIOVector *qiov, int flags)
{
return bdrv_co_pwritev(bs->file, offset, bytes, qiov, flags);
}
static int coroutine_fn cor_co_pwrite_zeroes(BlockDriverState *bs,
int64_t offset, int bytes,
BdrvRequestFlags flags)
{
return bdrv_co_pwrite_zeroes(bs->file, offset, bytes, flags);
}
static int coroutine_fn cor_co_pdiscard(BlockDriverState *bs,
int64_t offset, int bytes)
{
return bdrv_co_pdiscard(bs->file, offset, bytes);
}
static void cor_eject(BlockDriverState *bs, bool eject_flag)
{
bdrv_eject(bs->file->bs, eject_flag);
}
static void cor_lock_medium(BlockDriverState *bs, bool locked)
{
bdrv_lock_medium(bs->file->bs, locked);
}
static bool cor_recurse_is_first_non_filter(BlockDriverState *bs,
BlockDriverState *candidate)
{
return bdrv_recurse_is_first_non_filter(bs->file->bs, candidate);
}
static BlockDriver bdrv_copy_on_read = {
.format_name = "copy-on-read",
.bdrv_open = cor_open,
.bdrv_child_perm = cor_child_perm,
.bdrv_getlength = cor_getlength,
.bdrv_co_truncate = cor_co_truncate,
.bdrv_co_preadv = cor_co_preadv,
.bdrv_co_pwritev = cor_co_pwritev,
.bdrv_co_pwrite_zeroes = cor_co_pwrite_zeroes,
.bdrv_co_pdiscard = cor_co_pdiscard,
.bdrv_eject = cor_eject,
.bdrv_lock_medium = cor_lock_medium,
.bdrv_co_block_status = bdrv_co_block_status_from_file,
.bdrv_recurse_is_first_non_filter = cor_recurse_is_first_non_filter,
.has_variable_length = true,
.is_filter = true,
};
static void bdrv_copy_on_read_init(void)
{
bdrv_register(&bdrv_copy_on_read);
}
block_init(bdrv_copy_on_read_init);
|
pmp-tool/PMP | src/qemu/src-pmp/linux-user/config.h | /* PMP Modification - Begin */
#include "config.inc"
#define __NR_setpid 326
#define __NR_setflag 327
#define __NR_printmsg 328
#define __NR_validaddr 329
#define __NR_killfamily 330
extern target_ulong program_code_offset, program_code_start, program_code_end;
extern unsigned int index_path_scheme;
extern GSList *path_scheme;
extern char fname_path_scheme[BUFF_LEN], fname_path_trace[BUFF_LEN];
extern char fname_insn_tmp[BUFF_LEN], fname_dep_tmp[BUFF_LEN];
struct pair {
target_ulong first;
target_ulong second;
};
extern void do_initialize(void);
extern void read_path_scheme(void);
static inline int g_slist_compare_pair_first(const void *pointera, const void *pointerb) {
struct pair *pa = (struct pair *)(pointera);
struct pair *pb = (struct pair *)(pointerb);
if (!pa || !pb) return -1;
else return pa->first - pb->first;
}
static inline int is_program_code(target_ulong iaddr) {
return (iaddr >= program_code_start && iaddr <= program_code_end);
}
static inline int valid_addr(target_ulong insn_addr) {
return (insn_addr > ALLOCATE_SIZE);
}
/* PMP Modification - End */
|
pmp-tool/PMP | src/qemu/src-pmp/tests/libqos/aarch64-xlnx-zcu102-machine.c | <reponame>pmp-tool/PMP
/*
* libqos driver framework
*
* Copyright (c) 2018 <NAME> <<EMAIL>>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License version 2 as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/malloc.h"
#include "libqos/qgraph.h"
#include "sdhci.h"
typedef struct QXlnxZCU102Machine QXlnxZCU102Machine;
struct QXlnxZCU102Machine {
QOSGraphObject obj;
QGuestAllocator alloc;
QSDHCI_MemoryMapped sdhci;
};
#define ARM_PAGE_SIZE 4096
#define XLNX_ZCU102_RAM_ADDR 0
#define XLNX_ZCU102_RAM_SIZE 0x20000000
static void *xlnx_zcu102_get_driver(void *object, const char *interface)
{
QXlnxZCU102Machine *machine = object;
if (!g_strcmp0(interface, "memory")) {
return &machine->alloc;
}
fprintf(stderr, "%s not present in aarch64/xlnx-zcu102\n", interface);
g_assert_not_reached();
}
static QOSGraphObject *xlnx_zcu102_get_device(void *obj, const char *device)
{
QXlnxZCU102Machine *machine = obj;
if (!g_strcmp0(device, "generic-sdhci")) {
return &machine->sdhci.obj;
}
fprintf(stderr, "%s not present in aarch64/xlnx-zcu102\n", device);
g_assert_not_reached();
}
static void xlnx_zcu102_destructor(QOSGraphObject *obj)
{
QXlnxZCU102Machine *machine = (QXlnxZCU102Machine *) obj;
alloc_destroy(&machine->alloc);
}
static void *qos_create_machine_aarch64_xlnx_zcu102(QTestState *qts)
{
QXlnxZCU102Machine *machine = g_new0(QXlnxZCU102Machine, 1);
alloc_init(&machine->alloc, 0,
XLNX_ZCU102_RAM_ADDR + (1 << 20),
XLNX_ZCU102_RAM_ADDR + XLNX_ZCU102_RAM_SIZE,
ARM_PAGE_SIZE);
machine->obj.get_device = xlnx_zcu102_get_device;
machine->obj.get_driver = xlnx_zcu102_get_driver;
machine->obj.destructor = xlnx_zcu102_destructor;
/* Datasheet: UG1085 (v1.7) */
qos_init_sdhci_mm(&machine->sdhci, qts, 0xff160000, &(QSDHCIProperties) {
.version = 3,
.baseclock = 0,
.capab.sdma = true,
.capab.reg = 0x280737ec6481
});
return &machine->obj;
}
static void xlnx_zcu102_register_nodes(void)
{
qos_node_create_machine("aarch64/xlnx-zcu102",
qos_create_machine_aarch64_xlnx_zcu102);
qos_node_contains("aarch64/xlnx-zcu102", "generic-sdhci", NULL);
}
libqos_init(xlnx_zcu102_register_nodes);
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-divide/test_msa_div_u_h.c | /*
* Test program for MSA instruction DIV_U.H
*
* Copyright (C) 2018 Wave Computing, Inc.
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs.h"
#include "../../../../include/test_utils.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "DIV_U.H";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x0001000100010001ULL, 0x0001000100010001ULL, }, /* 0 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0003000300030003ULL, 0x0003000300030003ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0005000500050005ULL, 0x0005000500050005ULL, },
{ 0x0001000400010001ULL, 0x0004000100010004ULL, },
{ 0x0009000100020009ULL, 0x0001000200090001ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 8 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 16 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0002000200020002ULL, 0x0002000200020002ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0003000300030003ULL, 0x0003000300030003ULL, },
{ 0x0000000300010000ULL, 0x0003000100000003ULL, },
{ 0x0006000000010006ULL, 0x0000000100060000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 24 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0000000100000000ULL, 0x0001000000000001ULL, },
{ 0x0003000000000003ULL, 0x0000000000030000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 32 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0002000200020002ULL, 0x0002000200020002ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0004000400040004ULL, 0x0004000400040004ULL, },
{ 0x0000000300010000ULL, 0x0003000100000003ULL, },
{ 0x0007000100010007ULL, 0x0001000100070001ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 40 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0001000000000001ULL, 0x0000000000010000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 48 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0001000000000001ULL, 0x0000000000010000ULL, },
{ 0x0002000000010002ULL, 0x0000000100020000ULL, },
{ 0x0001000000000001ULL, 0x0000000000010000ULL, },
{ 0x0004000100020004ULL, 0x0001000200040001ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0008000000010008ULL, 0x0000000100080000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 56 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000100000000ULL, 0x0001000000000001ULL, },
{ 0x0000000200010000ULL, 0x0002000100000002ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000300020000ULL, 0x0003000200000003ULL, },
{ 0x0000000300000000ULL, 0x0003000000000003ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, }, /* 64 */
{ 0x0000025400000000ULL, 0x00030000000b0002ULL, },
{ 0x0000000100000000ULL, 0x0001000000010004ULL, },
{ 0x0001000a00000000ULL, 0x0000000000010000ULL, },
{ 0x0001000000010002ULL, 0x0000001000000000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0001000000000001ULL, 0x0000000000000002ULL, },
{ 0x0002000000000000ULL, 0x0000000100000000ULL, },
{ 0x0001000000040001ULL, 0x0000001100000000ULL, }, /* 72 */
{ 0x000001c300020000ULL, 0x0002000100080000ULL, },
{ 0x0001000100010001ULL, 0x0001000100010001ULL, },
{ 0x0001000700010000ULL, 0x0000000100010000ULL, },
{ 0x0000000000020002ULL, 0x0001000c00000001ULL, },
{ 0x0000003900010001ULL, 0x0007000000070002ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_DIV_U_H(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_DIV_U_H(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/target/xtensa/mmu_helper.c | /*
* Copyright (c) 2011 - 2019, <NAME>, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "qemu/units.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
{
/*
* Attempt the memory load; we don't care about the result but
* only the side-effects (ie any MMU or other exception)
*/
cpu_ldub_code_ra(env, vaddr, GETPC());
}
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
v = (v & 0xffffff00) | 0x1;
if (v != env->sregs[RASID]) {
env->sregs[RASID] = v;
tlb_flush(CPU(cpu));
}
}
static uint32_t get_page_size(const CPUXtensaState *env,
bool dtlb, uint32_t way)
{
uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
switch (way) {
case 4:
return (tlbcfg >> 16) & 0x3;
case 5:
return (tlbcfg >> 20) & 0x1;
case 6:
return (tlbcfg >> 24) & 0x1;
default:
return 0;
}
}
/*!
* Get bit mask for the virtual address bits translated by the TLB way
*/
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
bool dtlb, uint32_t way)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
bool varway56 = dtlb ?
env->config->dtlb.varway56 :
env->config->itlb.varway56;
switch (way) {
case 4:
return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
case 5:
if (varway56) {
return 0xf8000000 << get_page_size(env, dtlb, way);
} else {
return 0xf8000000;
}
case 6:
if (varway56) {
return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
} else {
return 0xf0000000;
}
default:
return 0xfffff000;
}
} else {
return REGION_PAGE_MASK;
}
}
/*!
* Get bit mask for the 'VPN without index' field.
* See ISA, 4.6.5.6, data format for RxTLB0
*/
static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{
if (way < 4) {
bool is32 = (dtlb ?
env->config->dtlb.nrefillentries :
env->config->itlb.nrefillentries) == 32;
return is32 ? 0xffff8000 : 0xffffc000;
} else if (way == 4) {
return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
} else if (way <= 6) {
uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
bool varway56 = dtlb ?
env->config->dtlb.varway56 :
env->config->itlb.varway56;
if (varway56) {
return mask << (way == 5 ? 2 : 3);
} else {
return mask << 1;
}
} else {
return 0xfffff000;
}
}
/*!
* Split virtual address into VPN (with index) and entry index
* for the given TLB way
*/
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei)
{
bool varway56 = dtlb ?
env->config->dtlb.varway56 :
env->config->itlb.varway56;
if (!dtlb) {
wi &= 7;
}
if (wi < 4) {
bool is32 = (dtlb ?
env->config->dtlb.nrefillentries :
env->config->itlb.nrefillentries) == 32;
*ei = (v >> 12) & (is32 ? 0x7 : 0x3);
} else {
switch (wi) {
case 4:
{
uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
*ei = (v >> eibase) & 0x3;
}
break;
case 5:
if (varway56) {
uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
*ei = (v >> eibase) & 0x3;
} else {
*ei = (v >> 27) & 0x1;
}
break;
case 6:
if (varway56) {
uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
*ei = (v >> eibase) & 0x7;
} else {
*ei = (v >> 28) & 0x1;
}
break;
default:
*ei = 0;
break;
}
}
*vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
}
/*!
* Split TLB address into TLB way, entry index and VPN (with index).
* See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
*/
static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t *wi, uint32_t *ei)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
*wi = v & (dtlb ? 0xf : 0x7);
split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
} else {
*vpn = v & REGION_PAGE_MASK;
*wi = 0;
*ei = (v >> 29) & 0x7;
}
}
static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
uint32_t v, bool dtlb, uint32_t *pwi)
{
uint32_t vpn;
uint32_t wi;
uint32_t ei;
split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
if (pwi) {
*pwi = wi;
}
return xtensa_tlb_get_entry(env, dtlb, wi, ei);
}
uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
} else {
return v & REGION_PAGE_MASK;
}
}
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
return entry->paddr | entry->attr;
}
void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
entry->asid = 0;
}
}
}
uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
uint32_t ei;
uint8_t ring;
int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
switch (res) {
case 0:
if (ring >= xtensa_get_ring(env)) {
return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
}
break;
case INST_TLB_MULTI_HIT_CAUSE:
case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
HELPER(exception_cause_vaddr)(env, env->pc, res, v);
break;
}
return 0;
} else {
return (v & REGION_PAGE_MASK) | 0x1;
}
}
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
xtensa_tlb_entry *entry, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn,
uint32_t pte)
{
entry->vaddr = vpn;
entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
entry->attr = pte & 0xf;
}
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
CPUState *cs = CPU(cpu);
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
if (entry->variable) {
if (entry->asid) {
tlb_flush_page(cs, entry->vaddr);
}
xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
tlb_flush_page(cs, entry->vaddr);
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"%s %d, %d, %d trying to set immutable entry\n",
__func__, dtlb, wi, ei);
}
} else {
tlb_flush_page(cs, entry->vaddr);
if (xtensa_option_enabled(env->config,
XTENSA_OPTION_REGION_TRANSLATION)) {
entry->paddr = pte & REGION_PAGE_MASK;
}
entry->attr = pte & 0xf;
}
}
void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
{
uint32_t vpn;
uint32_t wi;
uint32_t ei;
split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
}
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
uint32_t paddr;
uint32_t page_size;
unsigned access;
if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
&paddr, &page_size, &access) == 0) {
return paddr;
}
if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
&paddr, &page_size, &access) == 0) {
return paddr;
}
return ~0;
}
static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
const xtensa_tlb *tlb,
xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
unsigned wi, ei;
for (wi = 0; wi < tlb->nways; ++wi) {
for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
entry[wi][ei].asid = 0;
entry[wi][ei].variable = true;
}
}
}
static void reset_tlb_mmu_ways56(CPUXtensaState *env,
const xtensa_tlb *tlb,
xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
if (!tlb->varway56) {
static const xtensa_tlb_entry way5[] = {
{
.vaddr = 0xd0000000,
.paddr = 0,
.asid = 1,
.attr = 7,
.variable = false,
}, {
.vaddr = 0xd8000000,
.paddr = 0,
.asid = 1,
.attr = 3,
.variable = false,
}
};
static const xtensa_tlb_entry way6[] = {
{
.vaddr = 0xe0000000,
.paddr = 0xf0000000,
.asid = 1,
.attr = 7,
.variable = false,
}, {
.vaddr = 0xf0000000,
.paddr = 0xf0000000,
.asid = 1,
.attr = 3,
.variable = false,
}
};
memcpy(entry[5], way5, sizeof(way5));
memcpy(entry[6], way6, sizeof(way6));
} else {
uint32_t ei;
for (ei = 0; ei < 8; ++ei) {
entry[6][ei].vaddr = ei << 29;
entry[6][ei].paddr = ei << 29;
entry[6][ei].asid = 1;
entry[6][ei].attr = 3;
}
}
}
static void reset_tlb_region_way0(CPUXtensaState *env,
xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
unsigned ei;
for (ei = 0; ei < 8; ++ei) {
entry[0][ei].vaddr = ei << 29;
entry[0][ei].paddr = ei << 29;
entry[0][ei].asid = 1;
entry[0][ei].attr = 2;
entry[0][ei].variable = true;
}
}
void reset_mmu(CPUXtensaState *env)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
env->sregs[RASID] = 0x04030201;
env->sregs[ITLBCFG] = 0;
env->sregs[DTLBCFG] = 0;
env->autorefill_idx = 0;
reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
} else {
reset_tlb_region_way0(env, env->itlb);
reset_tlb_region_way0(env, env->dtlb);
}
}
static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
{
unsigned i;
for (i = 0; i < 4; ++i) {
if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
return i;
}
}
return 0xff;
}
/*!
* Lookup xtensa TLB for the given virtual address.
* See ISA, 4.6.2.2
*
* \param pwi: [out] way index
* \param pei: [out] entry index
* \param pring: [out] access ring
* \return 0 if ok, exception cause code otherwise
*/
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring)
{
const xtensa_tlb *tlb = dtlb ?
&env->config->dtlb : &env->config->itlb;
const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
env->dtlb : env->itlb;
int nhits = 0;
unsigned wi;
for (wi = 0; wi < tlb->nways; ++wi) {
uint32_t vpn;
uint32_t ei;
split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
unsigned ring = get_ring(env, entry[wi][ei].asid);
if (ring < 4) {
if (++nhits > 1) {
return dtlb ?
LOAD_STORE_TLB_MULTI_HIT_CAUSE :
INST_TLB_MULTI_HIT_CAUSE;
}
*pwi = wi;
*pei = ei;
*pring = ring;
}
}
}
return nhits ? 0 :
(dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
}
/*!
* Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
* See ISA, 4.6.5.10
*/
static unsigned mmu_attr_to_access(uint32_t attr)
{
unsigned access = 0;
if (attr < 12) {
access |= PAGE_READ;
if (attr & 0x1) {
access |= PAGE_EXEC;
}
if (attr & 0x2) {
access |= PAGE_WRITE;
}
switch (attr & 0xc) {
case 0:
access |= PAGE_CACHE_BYPASS;
break;
case 4:
access |= PAGE_CACHE_WB;
break;
case 8:
access |= PAGE_CACHE_WT;
break;
}
} else if (attr == 13) {
access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
}
return access;
}
/*!
* Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
* See ISA, 4.6.3.3
*/
static unsigned region_attr_to_access(uint32_t attr)
{
static const unsigned access[16] = {
[0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
[1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
[2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
[3] = PAGE_EXEC | PAGE_CACHE_WB,
[4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
[5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
[14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
};
return access[attr & 0xf];
}
/*!
* Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
* See ISA, A.2.14 The Cache Attribute Register
*/
static unsigned cacheattr_attr_to_access(uint32_t attr)
{
static const unsigned access[16] = {
[0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
[1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
[2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
[3] = PAGE_EXEC | PAGE_CACHE_WB,
[4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
[14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
};
return access[attr & 0xf];
}
static bool is_access_granted(unsigned access, int is_write)
{
switch (is_write) {
case 0:
return access & PAGE_READ;
case 1:
return access & PAGE_WRITE;
case 2:
return access & PAGE_EXEC;
default:
return 0;
}
}
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size,
unsigned *access, bool may_lookup_pt)
{
bool dtlb = is_write != 2;
uint32_t wi;
uint32_t ei;
uint8_t ring;
uint32_t vpn;
uint32_t pte;
const xtensa_tlb_entry *entry = NULL;
xtensa_tlb_entry tmp_entry;
int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
may_lookup_pt && get_pte(env, vaddr, &pte)) {
ring = (pte >> 4) & 0x3;
wi = 0;
split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
if (update_tlb) {
wi = ++env->autorefill_idx & 0x3;
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
env->sregs[EXCVADDR] = vaddr;
qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
__func__, vaddr, vpn, pte);
} else {
xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
entry = &tmp_entry;
}
ret = 0;
}
if (ret != 0) {
return ret;
}
if (entry == NULL) {
entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
}
if (ring < mmu_idx) {
return dtlb ?
LOAD_STORE_PRIVILEGE_CAUSE :
INST_FETCH_PRIVILEGE_CAUSE;
}
*access = mmu_attr_to_access(entry->attr) &
~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
if (!is_access_granted(*access, is_write)) {
return dtlb ?
(is_write ?
STORE_PROHIBITED_CAUSE :
LOAD_PROHIBITED_CAUSE) :
INST_FETCH_PROHIBITED_CAUSE;
}
*paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
*page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
return 0;
}
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
uint32_t paddr;
uint32_t page_size;
unsigned access;
uint32_t pt_vaddr =
(env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
&paddr, &page_size, &access, false);
if (ret == 0) {
qemu_log_mask(CPU_LOG_MMU,
"%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
__func__, vaddr, pt_vaddr, paddr);
} else {
qemu_log_mask(CPU_LOG_MMU,
"%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
__func__, vaddr, pt_vaddr, ret);
}
if (ret == 0) {
MemTxResult result;
*pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
&result);
if (result != MEMTX_OK) {
qemu_log_mask(CPU_LOG_MMU,
"%s: couldn't load PTE: transaction failed (%u)\n",
__func__, (unsigned)result);
ret = 1;
}
}
return ret == 0;
}
static int get_physical_addr_region(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size,
unsigned *access)
{
bool dtlb = is_write != 2;
uint32_t wi = 0;
uint32_t ei = (vaddr >> 29) & 0x7;
const xtensa_tlb_entry *entry =
xtensa_tlb_get_entry(env, dtlb, wi, ei);
*access = region_attr_to_access(entry->attr);
if (!is_access_granted(*access, is_write)) {
return dtlb ?
(is_write ?
STORE_PROHIBITED_CAUSE :
LOAD_PROHIBITED_CAUSE) :
INST_FETCH_PROHIBITED_CAUSE;
}
*paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
*page_size = ~REGION_PAGE_MASK + 1;
return 0;
}
/*!
* Convert virtual address to physical addr.
* MMU may issue pagewalk and change xtensa autorefill TLB way entry.
*
* \return 0 if ok, exception cause code otherwise
*/
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size,
unsigned *access)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
return get_physical_addr_mmu(env, update_tlb,
vaddr, is_write, mmu_idx, paddr,
page_size, access, true);
} else if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
paddr, page_size, access);
} else {
*paddr = vaddr;
*page_size = TARGET_PAGE_SIZE;
*access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >>
((vaddr & 0xe0000000) >> 27));
return 0;
}
}
static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
CPUXtensaState *env, bool dtlb)
{
unsigned wi, ei;
const xtensa_tlb *conf =
dtlb ? &env->config->dtlb : &env->config->itlb;
unsigned (*attr_to_access)(uint32_t) =
xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
mmu_attr_to_access : region_attr_to_access;
for (wi = 0; wi < conf->nways; ++wi) {
uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
const char *sz_text;
bool print_header = true;
if (sz >= 0x100000) {
sz /= MiB;
sz_text = "MB";
} else {
sz /= KiB;
sz_text = "KB";
}
for (ei = 0; ei < conf->way_size[wi]; ++ei) {
const xtensa_tlb_entry *entry =
xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (entry->asid) {
static const char * const cache_text[8] = {
[PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
[PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
[PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
[PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
};
unsigned access = attr_to_access(entry->attr);
unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
PAGE_CACHE_SHIFT;
if (print_header) {
print_header = false;
cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
cpu_fprintf(f,
"\tVaddr Paddr ASID Attr RWX Cache\n"
"\t---------- ---------- ---- ---- --- -------\n");
}
cpu_fprintf(f,
"\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
entry->vaddr,
entry->paddr,
entry->asid,
entry->attr,
(access & PAGE_READ) ? 'R' : '-',
(access & PAGE_WRITE) ? 'W' : '-',
(access & PAGE_EXEC) ? 'X' : '-',
cache_text[cache_idx] ?
cache_text[cache_idx] : "Invalid");
}
}
}
}
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
{
if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
cpu_fprintf(f, "ITLB:\n");
dump_tlb(f, cpu_fprintf, env, false);
cpu_fprintf(f, "\nDTLB:\n");
dump_tlb(f, cpu_fprintf, env, true);
} else {
cpu_fprintf(f, "No TLB for this CPU core\n");
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/block/qed.c | /*
* QEMU Enhanced Disk Format
*
* Copyright IBM, Corp. 2010
*
* Authors:
* <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU LGPL, version 2 or later.
* See the COPYING.LIB file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "block/qdict.h"
#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/bswap.h"
#include "qemu/option.h"
#include "trace.h"
#include "qed.h"
#include "sysemu/block-backend.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qobject-input-visitor.h"
#include "qapi/qapi-visit-block-core.h"
static QemuOptsList qed_create_opts;
static int bdrv_qed_probe(const uint8_t *buf, int buf_size,
const char *filename)
{
const QEDHeader *header = (const QEDHeader *)buf;
if (buf_size < sizeof(*header)) {
return 0;
}
if (le32_to_cpu(header->magic) != QED_MAGIC) {
return 0;
}
return 100;
}
/**
* Check whether an image format is raw
*
* @fmt: Backing file format, may be NULL
*/
static bool qed_fmt_is_raw(const char *fmt)
{
return fmt && strcmp(fmt, "raw") == 0;
}
static void qed_header_le_to_cpu(const QEDHeader *le, QEDHeader *cpu)
{
cpu->magic = le32_to_cpu(le->magic);
cpu->cluster_size = le32_to_cpu(le->cluster_size);
cpu->table_size = le32_to_cpu(le->table_size);
cpu->header_size = le32_to_cpu(le->header_size);
cpu->features = le64_to_cpu(le->features);
cpu->compat_features = le64_to_cpu(le->compat_features);
cpu->autoclear_features = le64_to_cpu(le->autoclear_features);
cpu->l1_table_offset = le64_to_cpu(le->l1_table_offset);
cpu->image_size = le64_to_cpu(le->image_size);
cpu->backing_filename_offset = le32_to_cpu(le->backing_filename_offset);
cpu->backing_filename_size = le32_to_cpu(le->backing_filename_size);
}
static void qed_header_cpu_to_le(const QEDHeader *cpu, QEDHeader *le)
{
le->magic = cpu_to_le32(cpu->magic);
le->cluster_size = cpu_to_le32(cpu->cluster_size);
le->table_size = cpu_to_le32(cpu->table_size);
le->header_size = cpu_to_le32(cpu->header_size);
le->features = cpu_to_le64(cpu->features);
le->compat_features = cpu_to_le64(cpu->compat_features);
le->autoclear_features = cpu_to_le64(cpu->autoclear_features);
le->l1_table_offset = cpu_to_le64(cpu->l1_table_offset);
le->image_size = cpu_to_le64(cpu->image_size);
le->backing_filename_offset = cpu_to_le32(cpu->backing_filename_offset);
le->backing_filename_size = cpu_to_le32(cpu->backing_filename_size);
}
int qed_write_header_sync(BDRVQEDState *s)
{
QEDHeader le;
int ret;
qed_header_cpu_to_le(&s->header, &le);
ret = bdrv_pwrite(s->bs->file, 0, &le, sizeof(le));
if (ret != sizeof(le)) {
return ret;
}
return 0;
}
/**
* Update header in-place (does not rewrite backing filename or other strings)
*
* This function only updates known header fields in-place and does not affect
* extra data after the QED header.
*
* No new allocating reqs can start while this function runs.
*/
static int coroutine_fn qed_write_header(BDRVQEDState *s)
{
/* We must write full sectors for O_DIRECT but cannot necessarily generate
* the data following the header if an unrecognized compat feature is
* active. Therefore, first read the sectors containing the header, update
* them, and write back.
*/
int nsectors = DIV_ROUND_UP(sizeof(QEDHeader), BDRV_SECTOR_SIZE);
size_t len = nsectors * BDRV_SECTOR_SIZE;
uint8_t *buf;
QEMUIOVector qiov;
int ret;
assert(s->allocating_acb || s->allocating_write_reqs_plugged);
buf = qemu_blockalign(s->bs, len);
qemu_iovec_init_buf(&qiov, buf, len);
ret = bdrv_co_preadv(s->bs->file, 0, qiov.size, &qiov, 0);
if (ret < 0) {
goto out;
}
/* Update header */
qed_header_cpu_to_le(&s->header, (QEDHeader *) buf);
ret = bdrv_co_pwritev(s->bs->file, 0, qiov.size, &qiov, 0);
if (ret < 0) {
goto out;
}
ret = 0;
out:
qemu_vfree(buf);
return ret;
}
static uint64_t qed_max_image_size(uint32_t cluster_size, uint32_t table_size)
{
uint64_t table_entries;
uint64_t l2_size;
table_entries = (table_size * cluster_size) / sizeof(uint64_t);
l2_size = table_entries * cluster_size;
return l2_size * table_entries;
}
static bool qed_is_cluster_size_valid(uint32_t cluster_size)
{
if (cluster_size < QED_MIN_CLUSTER_SIZE ||
cluster_size > QED_MAX_CLUSTER_SIZE) {
return false;
}
if (cluster_size & (cluster_size - 1)) {
return false; /* not power of 2 */
}
return true;
}
static bool qed_is_table_size_valid(uint32_t table_size)
{
if (table_size < QED_MIN_TABLE_SIZE ||
table_size > QED_MAX_TABLE_SIZE) {
return false;
}
if (table_size & (table_size - 1)) {
return false; /* not power of 2 */
}
return true;
}
static bool qed_is_image_size_valid(uint64_t image_size, uint32_t cluster_size,
uint32_t table_size)
{
if (image_size % BDRV_SECTOR_SIZE != 0) {
return false; /* not multiple of sector size */
}
if (image_size > qed_max_image_size(cluster_size, table_size)) {
return false; /* image is too large */
}
return true;
}
/**
* Read a string of known length from the image file
*
* @file: Image file
* @offset: File offset to start of string, in bytes
* @n: String length in bytes
* @buf: Destination buffer
* @buflen: Destination buffer length in bytes
* @ret: 0 on success, -errno on failure
*
* The string is NUL-terminated.
*/
static int qed_read_string(BdrvChild *file, uint64_t offset, size_t n,
char *buf, size_t buflen)
{
int ret;
if (n >= buflen) {
return -EINVAL;
}
ret = bdrv_pread(file, offset, buf, n);
if (ret < 0) {
return ret;
}
buf[n] = '\0';
return 0;
}
/**
* Allocate new clusters
*
* @s: QED state
* @n: Number of contiguous clusters to allocate
* @ret: Offset of first allocated cluster
*
* This function only produces the offset where the new clusters should be
* written. It updates BDRVQEDState but does not make any changes to the image
* file.
*
* Called with table_lock held.
*/
static uint64_t qed_alloc_clusters(BDRVQEDState *s, unsigned int n)
{
uint64_t offset = s->file_size;
s->file_size += n * s->header.cluster_size;
return offset;
}
QEDTable *qed_alloc_table(BDRVQEDState *s)
{
/* Honor O_DIRECT memory alignment requirements */
return qemu_blockalign(s->bs,
s->header.cluster_size * s->header.table_size);
}
/**
* Allocate a new zeroed L2 table
*
* Called with table_lock held.
*/
static CachedL2Table *qed_new_l2_table(BDRVQEDState *s)
{
CachedL2Table *l2_table = qed_alloc_l2_cache_entry(&s->l2_cache);
l2_table->table = qed_alloc_table(s);
l2_table->offset = qed_alloc_clusters(s, s->header.table_size);
memset(l2_table->table->offsets, 0,
s->header.cluster_size * s->header.table_size);
return l2_table;
}
static bool qed_plug_allocating_write_reqs(BDRVQEDState *s)
{
qemu_co_mutex_lock(&s->table_lock);
/* No reentrancy is allowed. */
assert(!s->allocating_write_reqs_plugged);
if (s->allocating_acb != NULL) {
/* Another allocating write came concurrently. This cannot happen
* from bdrv_qed_co_drain_begin, but it can happen when the timer runs.
*/
qemu_co_mutex_unlock(&s->table_lock);
return false;
}
s->allocating_write_reqs_plugged = true;
qemu_co_mutex_unlock(&s->table_lock);
return true;
}
static void qed_unplug_allocating_write_reqs(BDRVQEDState *s)
{
qemu_co_mutex_lock(&s->table_lock);
assert(s->allocating_write_reqs_plugged);
s->allocating_write_reqs_plugged = false;
qemu_co_queue_next(&s->allocating_write_reqs);
qemu_co_mutex_unlock(&s->table_lock);
}
static void coroutine_fn qed_need_check_timer_entry(void *opaque)
{
BDRVQEDState *s = opaque;
int ret;
trace_qed_need_check_timer_cb(s);
if (!qed_plug_allocating_write_reqs(s)) {
return;
}
/* Ensure writes are on disk before clearing flag */
ret = bdrv_co_flush(s->bs->file->bs);
if (ret < 0) {
qed_unplug_allocating_write_reqs(s);
return;
}
s->header.features &= ~QED_F_NEED_CHECK;
ret = qed_write_header(s);
(void) ret;
qed_unplug_allocating_write_reqs(s);
ret = bdrv_co_flush(s->bs);
(void) ret;
}
static void qed_need_check_timer_cb(void *opaque)
{
Coroutine *co = qemu_coroutine_create(qed_need_check_timer_entry, opaque);
qemu_coroutine_enter(co);
}
static void qed_start_need_check_timer(BDRVQEDState *s)
{
trace_qed_start_need_check_timer(s);
/* Use QEMU_CLOCK_VIRTUAL so we don't alter the image file while suspended for
* migration.
*/
timer_mod(s->need_check_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
NANOSECONDS_PER_SECOND * QED_NEED_CHECK_TIMEOUT);
}
/* It's okay to call this multiple times or when no timer is started */
static void qed_cancel_need_check_timer(BDRVQEDState *s)
{
trace_qed_cancel_need_check_timer(s);
timer_del(s->need_check_timer);
}
static void bdrv_qed_detach_aio_context(BlockDriverState *bs)
{
BDRVQEDState *s = bs->opaque;
qed_cancel_need_check_timer(s);
timer_free(s->need_check_timer);
}
static void bdrv_qed_attach_aio_context(BlockDriverState *bs,
AioContext *new_context)
{
BDRVQEDState *s = bs->opaque;
s->need_check_timer = aio_timer_new(new_context,
QEMU_CLOCK_VIRTUAL, SCALE_NS,
qed_need_check_timer_cb, s);
if (s->header.features & QED_F_NEED_CHECK) {
qed_start_need_check_timer(s);
}
}
static void coroutine_fn bdrv_qed_co_drain_begin(BlockDriverState *bs)
{
BDRVQEDState *s = bs->opaque;
/* Fire the timer immediately in order to start doing I/O as soon as the
* header is flushed.
*/
if (s->need_check_timer && timer_pending(s->need_check_timer)) {
qed_cancel_need_check_timer(s);
qed_need_check_timer_entry(s);
}
}
static void bdrv_qed_init_state(BlockDriverState *bs)
{
BDRVQEDState *s = bs->opaque;
memset(s, 0, sizeof(BDRVQEDState));
s->bs = bs;
qemu_co_mutex_init(&s->table_lock);
qemu_co_queue_init(&s->allocating_write_reqs);
}
/* Called with table_lock held. */
static int coroutine_fn bdrv_qed_do_open(BlockDriverState *bs, QDict *options,
int flags, Error **errp)
{
BDRVQEDState *s = bs->opaque;
QEDHeader le_header;
int64_t file_size;
int ret;
ret = bdrv_pread(bs->file, 0, &le_header, sizeof(le_header));
if (ret < 0) {
return ret;
}
qed_header_le_to_cpu(&le_header, &s->header);
if (s->header.magic != QED_MAGIC) {
error_setg(errp, "Image not in QED format");
return -EINVAL;
}
if (s->header.features & ~QED_FEATURE_MASK) {
/* image uses unsupported feature bits */
error_setg(errp, "Unsupported QED features: %" PRIx64,
s->header.features & ~QED_FEATURE_MASK);
return -ENOTSUP;
}
if (!qed_is_cluster_size_valid(s->header.cluster_size)) {
return -EINVAL;
}
/* Round down file size to the last cluster */
file_size = bdrv_getlength(bs->file->bs);
if (file_size < 0) {
return file_size;
}
s->file_size = qed_start_of_cluster(s, file_size);
if (!qed_is_table_size_valid(s->header.table_size)) {
return -EINVAL;
}
if (!qed_is_image_size_valid(s->header.image_size,
s->header.cluster_size,
s->header.table_size)) {
return -EINVAL;
}
if (!qed_check_table_offset(s, s->header.l1_table_offset)) {
return -EINVAL;
}
s->table_nelems = (s->header.cluster_size * s->header.table_size) /
sizeof(uint64_t);
s->l2_shift = ctz32(s->header.cluster_size);
s->l2_mask = s->table_nelems - 1;
s->l1_shift = s->l2_shift + ctz32(s->table_nelems);
/* Header size calculation must not overflow uint32_t */
if (s->header.header_size > UINT32_MAX / s->header.cluster_size) {
return -EINVAL;
}
if ((s->header.features & QED_F_BACKING_FILE)) {
if ((uint64_t)s->header.backing_filename_offset +
s->header.backing_filename_size >
s->header.cluster_size * s->header.header_size) {
return -EINVAL;
}
ret = qed_read_string(bs->file, s->header.backing_filename_offset,
s->header.backing_filename_size,
bs->auto_backing_file,
sizeof(bs->auto_backing_file));
if (ret < 0) {
return ret;
}
pstrcpy(bs->backing_file, sizeof(bs->backing_file),
bs->auto_backing_file);
if (s->header.features & QED_F_BACKING_FORMAT_NO_PROBE) {
pstrcpy(bs->backing_format, sizeof(bs->backing_format), "raw");
}
}
/* Reset unknown autoclear feature bits. This is a backwards
* compatibility mechanism that allows images to be opened by older
* programs, which "knock out" unknown feature bits. When an image is
* opened by a newer program again it can detect that the autoclear
* feature is no longer valid.
*/
if ((s->header.autoclear_features & ~QED_AUTOCLEAR_FEATURE_MASK) != 0 &&
!bdrv_is_read_only(bs->file->bs) && !(flags & BDRV_O_INACTIVE)) {
s->header.autoclear_features &= QED_AUTOCLEAR_FEATURE_MASK;
ret = qed_write_header_sync(s);
if (ret) {
return ret;
}
/* From here on only known autoclear feature bits are valid */
bdrv_flush(bs->file->bs);
}
s->l1_table = qed_alloc_table(s);
qed_init_l2_cache(&s->l2_cache);
ret = qed_read_l1_table_sync(s);
if (ret) {
goto out;
}
/* If image was not closed cleanly, check consistency */
if (!(flags & BDRV_O_CHECK) && (s->header.features & QED_F_NEED_CHECK)) {
/* Read-only images cannot be fixed. There is no risk of corruption
* since write operations are not possible. Therefore, allow
* potentially inconsistent images to be opened read-only. This can
* aid data recovery from an otherwise inconsistent image.
*/
if (!bdrv_is_read_only(bs->file->bs) &&
!(flags & BDRV_O_INACTIVE)) {
BdrvCheckResult result = {0};
ret = qed_check(s, &result, true);
if (ret) {
goto out;
}
}
}
bdrv_qed_attach_aio_context(bs, bdrv_get_aio_context(bs));
out:
if (ret) {
qed_free_l2_cache(&s->l2_cache);
qemu_vfree(s->l1_table);
}
return ret;
}
typedef struct QEDOpenCo {
BlockDriverState *bs;
QDict *options;
int flags;
Error **errp;
int ret;
} QEDOpenCo;
static void coroutine_fn bdrv_qed_open_entry(void *opaque)
{
QEDOpenCo *qoc = opaque;
BDRVQEDState *s = qoc->bs->opaque;
qemu_co_mutex_lock(&s->table_lock);
qoc->ret = bdrv_qed_do_open(qoc->bs, qoc->options, qoc->flags, qoc->errp);
qemu_co_mutex_unlock(&s->table_lock);
}
static int bdrv_qed_open(BlockDriverState *bs, QDict *options, int flags,
Error **errp)
{
QEDOpenCo qoc = {
.bs = bs,
.options = options,
.flags = flags,
.errp = errp,
.ret = -EINPROGRESS
};
bs->file = bdrv_open_child(NULL, options, "file", bs, &child_file,
false, errp);
if (!bs->file) {
return -EINVAL;
}
bdrv_qed_init_state(bs);
if (qemu_in_coroutine()) {
bdrv_qed_open_entry(&qoc);
} else {
assert(qemu_get_current_aio_context() == qemu_get_aio_context());
qemu_coroutine_enter(qemu_coroutine_create(bdrv_qed_open_entry, &qoc));
BDRV_POLL_WHILE(bs, qoc.ret == -EINPROGRESS);
}
BDRV_POLL_WHILE(bs, qoc.ret == -EINPROGRESS);
return qoc.ret;
}
static void bdrv_qed_refresh_limits(BlockDriverState *bs, Error **errp)
{
BDRVQEDState *s = bs->opaque;
bs->bl.pwrite_zeroes_alignment = s->header.cluster_size;
}
/* We have nothing to do for QED reopen, stubs just return
* success */
static int bdrv_qed_reopen_prepare(BDRVReopenState *state,
BlockReopenQueue *queue, Error **errp)
{
return 0;
}
static void bdrv_qed_close(BlockDriverState *bs)
{
BDRVQEDState *s = bs->opaque;
bdrv_qed_detach_aio_context(bs);
/* Ensure writes reach stable storage */
bdrv_flush(bs->file->bs);
/* Clean shutdown, no check required on next open */
if (s->header.features & QED_F_NEED_CHECK) {
s->header.features &= ~QED_F_NEED_CHECK;
qed_write_header_sync(s);
}
qed_free_l2_cache(&s->l2_cache);
qemu_vfree(s->l1_table);
}
static int coroutine_fn bdrv_qed_co_create(BlockdevCreateOptions *opts,
Error **errp)
{
BlockdevCreateOptionsQed *qed_opts;
BlockBackend *blk = NULL;
BlockDriverState *bs = NULL;
QEDHeader header;
QEDHeader le_header;
uint8_t *l1_table = NULL;
size_t l1_size;
int ret = 0;
assert(opts->driver == BLOCKDEV_DRIVER_QED);
qed_opts = &opts->u.qed;
/* Validate options and set default values */
if (!qed_opts->has_cluster_size) {
qed_opts->cluster_size = QED_DEFAULT_CLUSTER_SIZE;
}
if (!qed_opts->has_table_size) {
qed_opts->table_size = QED_DEFAULT_TABLE_SIZE;
}
if (!qed_is_cluster_size_valid(qed_opts->cluster_size)) {
error_setg(errp, "QED cluster size must be within range [%u, %u] "
"and power of 2",
QED_MIN_CLUSTER_SIZE, QED_MAX_CLUSTER_SIZE);
return -EINVAL;
}
if (!qed_is_table_size_valid(qed_opts->table_size)) {
error_setg(errp, "QED table size must be within range [%u, %u] "
"and power of 2",
QED_MIN_TABLE_SIZE, QED_MAX_TABLE_SIZE);
return -EINVAL;
}
if (!qed_is_image_size_valid(qed_opts->size, qed_opts->cluster_size,
qed_opts->table_size))
{
error_setg(errp, "QED image size must be a non-zero multiple of "
"cluster size and less than %" PRIu64 " bytes",
qed_max_image_size(qed_opts->cluster_size,
qed_opts->table_size));
return -EINVAL;
}
/* Create BlockBackend to write to the image */
bs = bdrv_open_blockdev_ref(qed_opts->file, errp);
if (bs == NULL) {
return -EIO;
}
blk = blk_new(BLK_PERM_WRITE | BLK_PERM_RESIZE, BLK_PERM_ALL);
ret = blk_insert_bs(blk, bs, errp);
if (ret < 0) {
goto out;
}
blk_set_allow_write_beyond_eof(blk, true);
/* Prepare image format */
header = (QEDHeader) {
.magic = QED_MAGIC,
.cluster_size = qed_opts->cluster_size,
.table_size = qed_opts->table_size,
.header_size = 1,
.features = 0,
.compat_features = 0,
.l1_table_offset = qed_opts->cluster_size,
.image_size = qed_opts->size,
};
l1_size = header.cluster_size * header.table_size;
/* File must start empty and grow, check truncate is supported */
ret = blk_truncate(blk, 0, PREALLOC_MODE_OFF, errp);
if (ret < 0) {
goto out;
}
if (qed_opts->has_backing_file) {
header.features |= QED_F_BACKING_FILE;
header.backing_filename_offset = sizeof(le_header);
header.backing_filename_size = strlen(qed_opts->backing_file);
if (qed_opts->has_backing_fmt) {
const char *backing_fmt = BlockdevDriver_str(qed_opts->backing_fmt);
if (qed_fmt_is_raw(backing_fmt)) {
header.features |= QED_F_BACKING_FORMAT_NO_PROBE;
}
}
}
qed_header_cpu_to_le(&header, &le_header);
ret = blk_pwrite(blk, 0, &le_header, sizeof(le_header), 0);
if (ret < 0) {
goto out;
}
ret = blk_pwrite(blk, sizeof(le_header), qed_opts->backing_file,
header.backing_filename_size, 0);
if (ret < 0) {
goto out;
}
l1_table = g_malloc0(l1_size);
ret = blk_pwrite(blk, header.l1_table_offset, l1_table, l1_size, 0);
if (ret < 0) {
goto out;
}
ret = 0; /* success */
out:
g_free(l1_table);
blk_unref(blk);
bdrv_unref(bs);
return ret;
}
static int coroutine_fn bdrv_qed_co_create_opts(const char *filename,
QemuOpts *opts,
Error **errp)
{
BlockdevCreateOptions *create_options = NULL;
QDict *qdict;
Visitor *v;
BlockDriverState *bs = NULL;
Error *local_err = NULL;
int ret;
static const QDictRenames opt_renames[] = {
{ BLOCK_OPT_BACKING_FILE, "backing-file" },
{ BLOCK_OPT_BACKING_FMT, "backing-fmt" },
{ BLOCK_OPT_CLUSTER_SIZE, "cluster-size" },
{ BLOCK_OPT_TABLE_SIZE, "table-size" },
{ NULL, NULL },
};
/* Parse options and convert legacy syntax */
qdict = qemu_opts_to_qdict_filtered(opts, NULL, &qed_create_opts, true);
if (!qdict_rename_keys(qdict, opt_renames, errp)) {
ret = -EINVAL;
goto fail;
}
/* Create and open the file (protocol layer) */
ret = bdrv_create_file(filename, opts, &local_err);
if (ret < 0) {
error_propagate(errp, local_err);
goto fail;
}
bs = bdrv_open(filename, NULL, NULL,
BDRV_O_RDWR | BDRV_O_RESIZE | BDRV_O_PROTOCOL, errp);
if (bs == NULL) {
ret = -EIO;
goto fail;
}
/* Now get the QAPI type BlockdevCreateOptions */
qdict_put_str(qdict, "driver", "qed");
qdict_put_str(qdict, "file", bs->node_name);
v = qobject_input_visitor_new_flat_confused(qdict, errp);
if (!v) {
ret = -EINVAL;
goto fail;
}
visit_type_BlockdevCreateOptions(v, NULL, &create_options, &local_err);
visit_free(v);
if (local_err) {
error_propagate(errp, local_err);
ret = -EINVAL;
goto fail;
}
/* Silently round up size */
assert(create_options->driver == BLOCKDEV_DRIVER_QED);
create_options->u.qed.size =
ROUND_UP(create_options->u.qed.size, BDRV_SECTOR_SIZE);
/* Create the qed image (format layer) */
ret = bdrv_qed_co_create(create_options, errp);
fail:
qobject_unref(qdict);
bdrv_unref(bs);
qapi_free_BlockdevCreateOptions(create_options);
return ret;
}
static int coroutine_fn bdrv_qed_co_block_status(BlockDriverState *bs,
bool want_zero,
int64_t pos, int64_t bytes,
int64_t *pnum, int64_t *map,
BlockDriverState **file)
{
BDRVQEDState *s = bs->opaque;
size_t len = MIN(bytes, SIZE_MAX);
int status;
QEDRequest request = { .l2_table = NULL };
uint64_t offset;
int ret;
qemu_co_mutex_lock(&s->table_lock);
ret = qed_find_cluster(s, &request, pos, &len, &offset);
*pnum = len;
switch (ret) {
case QED_CLUSTER_FOUND:
*map = offset | qed_offset_into_cluster(s, pos);
status = BDRV_BLOCK_DATA | BDRV_BLOCK_OFFSET_VALID;
*file = bs->file->bs;
break;
case QED_CLUSTER_ZERO:
status = BDRV_BLOCK_ZERO;
break;
case QED_CLUSTER_L2:
case QED_CLUSTER_L1:
status = 0;
break;
default:
assert(ret < 0);
status = ret;
break;
}
qed_unref_l2_cache_entry(request.l2_table);
qemu_co_mutex_unlock(&s->table_lock);
return status;
}
static BDRVQEDState *acb_to_s(QEDAIOCB *acb)
{
return acb->bs->opaque;
}
/**
* Read from the backing file or zero-fill if no backing file
*
* @s: QED state
* @pos: Byte position in device
* @qiov: Destination I/O vector
* @backing_qiov: Possibly shortened copy of qiov, to be allocated here
* @cb: Completion function
* @opaque: User data for completion function
*
* This function reads qiov->size bytes starting at pos from the backing file.
* If there is no backing file then zeroes are read.
*/
static int coroutine_fn qed_read_backing_file(BDRVQEDState *s, uint64_t pos,
QEMUIOVector *qiov,
QEMUIOVector **backing_qiov)
{
uint64_t backing_length = 0;
size_t size;
int ret;
/* If there is a backing file, get its length. Treat the absence of a
* backing file like a zero length backing file.
*/
if (s->bs->backing) {
int64_t l = bdrv_getlength(s->bs->backing->bs);
if (l < 0) {
return l;
}
backing_length = l;
}
/* Zero all sectors if reading beyond the end of the backing file */
if (pos >= backing_length ||
pos + qiov->size > backing_length) {
qemu_iovec_memset(qiov, 0, 0, qiov->size);
}
/* Complete now if there are no backing file sectors to read */
if (pos >= backing_length) {
return 0;
}
/* If the read straddles the end of the backing file, shorten it */
size = MIN((uint64_t)backing_length - pos, qiov->size);
assert(*backing_qiov == NULL);
*backing_qiov = g_new(QEMUIOVector, 1);
qemu_iovec_init(*backing_qiov, qiov->niov);
qemu_iovec_concat(*backing_qiov, qiov, 0, size);
BLKDBG_EVENT(s->bs->file, BLKDBG_READ_BACKING_AIO);
ret = bdrv_co_preadv(s->bs->backing, pos, size, *backing_qiov, 0);
if (ret < 0) {
return ret;
}
return 0;
}
/**
* Copy data from backing file into the image
*
* @s: QED state
* @pos: Byte position in device
* @len: Number of bytes
* @offset: Byte offset in image file
*/
static int coroutine_fn qed_copy_from_backing_file(BDRVQEDState *s,
uint64_t pos, uint64_t len,
uint64_t offset)
{
QEMUIOVector qiov;
QEMUIOVector *backing_qiov = NULL;
int ret;
/* Skip copy entirely if there is no work to do */
if (len == 0) {
return 0;
}
qemu_iovec_init_buf(&qiov, qemu_blockalign(s->bs, len), len);
ret = qed_read_backing_file(s, pos, &qiov, &backing_qiov);
if (backing_qiov) {
qemu_iovec_destroy(backing_qiov);
g_free(backing_qiov);
backing_qiov = NULL;
}
if (ret) {
goto out;
}
BLKDBG_EVENT(s->bs->file, BLKDBG_COW_WRITE);
ret = bdrv_co_pwritev(s->bs->file, offset, qiov.size, &qiov, 0);
if (ret < 0) {
goto out;
}
ret = 0;
out:
qemu_vfree(qemu_iovec_buf(&qiov));
return ret;
}
/**
* Link one or more contiguous clusters into a table
*
* @s: QED state
* @table: L2 table
* @index: First cluster index
* @n: Number of contiguous clusters
* @cluster: First cluster offset
*
* The cluster offset may be an allocated byte offset in the image file, the
* zero cluster marker, or the unallocated cluster marker.
*
* Called with table_lock held.
*/
static void coroutine_fn qed_update_l2_table(BDRVQEDState *s, QEDTable *table,
int index, unsigned int n,
uint64_t cluster)
{
int i;
for (i = index; i < index + n; i++) {
table->offsets[i] = cluster;
if (!qed_offset_is_unalloc_cluster(cluster) &&
!qed_offset_is_zero_cluster(cluster)) {
cluster += s->header.cluster_size;
}
}
}
/* Called with table_lock held. */
static void coroutine_fn qed_aio_complete(QEDAIOCB *acb)
{
BDRVQEDState *s = acb_to_s(acb);
/* Free resources */
qemu_iovec_destroy(&acb->cur_qiov);
qed_unref_l2_cache_entry(acb->request.l2_table);
/* Free the buffer we may have allocated for zero writes */
if (acb->flags & QED_AIOCB_ZERO) {
qemu_vfree(acb->qiov->iov[0].iov_base);
acb->qiov->iov[0].iov_base = NULL;
}
/* Start next allocating write request waiting behind this one. Note that
* requests enqueue themselves when they first hit an unallocated cluster
* but they wait until the entire request is finished before waking up the
* next request in the queue. This ensures that we don't cycle through
* requests multiple times but rather finish one at a time completely.
*/
if (acb == s->allocating_acb) {
s->allocating_acb = NULL;
if (!qemu_co_queue_empty(&s->allocating_write_reqs)) {
qemu_co_queue_next(&s->allocating_write_reqs);
} else if (s->header.features & QED_F_NEED_CHECK) {
qed_start_need_check_timer(s);
}
}
}
/**
* Update L1 table with new L2 table offset and write it out
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_write_l1_update(QEDAIOCB *acb)
{
BDRVQEDState *s = acb_to_s(acb);
CachedL2Table *l2_table = acb->request.l2_table;
uint64_t l2_offset = l2_table->offset;
int index, ret;
index = qed_l1_index(s, acb->cur_pos);
s->l1_table->offsets[index] = l2_table->offset;
ret = qed_write_l1_table(s, index, 1);
/* Commit the current L2 table to the cache */
qed_commit_l2_cache_entry(&s->l2_cache, l2_table);
/* This is guaranteed to succeed because we just committed the entry to the
* cache.
*/
acb->request.l2_table = qed_find_l2_cache_entry(&s->l2_cache, l2_offset);
assert(acb->request.l2_table != NULL);
return ret;
}
/**
* Update L2 table with new cluster offsets and write them out
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_write_l2_update(QEDAIOCB *acb, uint64_t offset)
{
BDRVQEDState *s = acb_to_s(acb);
bool need_alloc = acb->find_cluster_ret == QED_CLUSTER_L1;
int index, ret;
if (need_alloc) {
qed_unref_l2_cache_entry(acb->request.l2_table);
acb->request.l2_table = qed_new_l2_table(s);
}
index = qed_l2_index(s, acb->cur_pos);
qed_update_l2_table(s, acb->request.l2_table->table, index, acb->cur_nclusters,
offset);
if (need_alloc) {
/* Write out the whole new L2 table */
ret = qed_write_l2_table(s, &acb->request, 0, s->table_nelems, true);
if (ret) {
return ret;
}
return qed_aio_write_l1_update(acb);
} else {
/* Write out only the updated part of the L2 table */
ret = qed_write_l2_table(s, &acb->request, index, acb->cur_nclusters,
false);
if (ret) {
return ret;
}
}
return 0;
}
/**
* Write data to the image file
*
* Called with table_lock *not* held.
*/
static int coroutine_fn qed_aio_write_main(QEDAIOCB *acb)
{
BDRVQEDState *s = acb_to_s(acb);
uint64_t offset = acb->cur_cluster +
qed_offset_into_cluster(s, acb->cur_pos);
trace_qed_aio_write_main(s, acb, 0, offset, acb->cur_qiov.size);
BLKDBG_EVENT(s->bs->file, BLKDBG_WRITE_AIO);
return bdrv_co_pwritev(s->bs->file, offset, acb->cur_qiov.size,
&acb->cur_qiov, 0);
}
/**
* Populate untouched regions of new data cluster
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_write_cow(QEDAIOCB *acb)
{
BDRVQEDState *s = acb_to_s(acb);
uint64_t start, len, offset;
int ret;
qemu_co_mutex_unlock(&s->table_lock);
/* Populate front untouched region of new data cluster */
start = qed_start_of_cluster(s, acb->cur_pos);
len = qed_offset_into_cluster(s, acb->cur_pos);
trace_qed_aio_write_prefill(s, acb, start, len, acb->cur_cluster);
ret = qed_copy_from_backing_file(s, start, len, acb->cur_cluster);
if (ret < 0) {
goto out;
}
/* Populate back untouched region of new data cluster */
start = acb->cur_pos + acb->cur_qiov.size;
len = qed_start_of_cluster(s, start + s->header.cluster_size - 1) - start;
offset = acb->cur_cluster +
qed_offset_into_cluster(s, acb->cur_pos) +
acb->cur_qiov.size;
trace_qed_aio_write_postfill(s, acb, start, len, offset);
ret = qed_copy_from_backing_file(s, start, len, offset);
if (ret < 0) {
goto out;
}
ret = qed_aio_write_main(acb);
if (ret < 0) {
goto out;
}
if (s->bs->backing) {
/*
* Flush new data clusters before updating the L2 table
*
* This flush is necessary when a backing file is in use. A crash
* during an allocating write could result in empty clusters in the
* image. If the write only touched a subregion of the cluster,
* then backing image sectors have been lost in the untouched
* region. The solution is to flush after writing a new data
* cluster and before updating the L2 table.
*/
ret = bdrv_co_flush(s->bs->file->bs);
}
out:
qemu_co_mutex_lock(&s->table_lock);
return ret;
}
/**
* Check if the QED_F_NEED_CHECK bit should be set during allocating write
*/
static bool qed_should_set_need_check(BDRVQEDState *s)
{
/* The flush before L2 update path ensures consistency */
if (s->bs->backing) {
return false;
}
return !(s->header.features & QED_F_NEED_CHECK);
}
/**
* Write new data cluster
*
* @acb: Write request
* @len: Length in bytes
*
* This path is taken when writing to previously unallocated clusters.
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_write_alloc(QEDAIOCB *acb, size_t len)
{
BDRVQEDState *s = acb_to_s(acb);
int ret;
/* Cancel timer when the first allocating request comes in */
if (s->allocating_acb == NULL) {
qed_cancel_need_check_timer(s);
}
/* Freeze this request if another allocating write is in progress */
if (s->allocating_acb != acb || s->allocating_write_reqs_plugged) {
if (s->allocating_acb != NULL) {
qemu_co_queue_wait(&s->allocating_write_reqs, &s->table_lock);
assert(s->allocating_acb == NULL);
}
s->allocating_acb = acb;
return -EAGAIN; /* start over with looking up table entries */
}
acb->cur_nclusters = qed_bytes_to_clusters(s,
qed_offset_into_cluster(s, acb->cur_pos) + len);
qemu_iovec_concat(&acb->cur_qiov, acb->qiov, acb->qiov_offset, len);
if (acb->flags & QED_AIOCB_ZERO) {
/* Skip ahead if the clusters are already zero */
if (acb->find_cluster_ret == QED_CLUSTER_ZERO) {
return 0;
}
acb->cur_cluster = 1;
} else {
acb->cur_cluster = qed_alloc_clusters(s, acb->cur_nclusters);
}
if (qed_should_set_need_check(s)) {
s->header.features |= QED_F_NEED_CHECK;
ret = qed_write_header(s);
if (ret < 0) {
return ret;
}
}
if (!(acb->flags & QED_AIOCB_ZERO)) {
ret = qed_aio_write_cow(acb);
if (ret < 0) {
return ret;
}
}
return qed_aio_write_l2_update(acb, acb->cur_cluster);
}
/**
* Write data cluster in place
*
* @acb: Write request
* @offset: Cluster offset in bytes
* @len: Length in bytes
*
* This path is taken when writing to already allocated clusters.
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_write_inplace(QEDAIOCB *acb, uint64_t offset,
size_t len)
{
BDRVQEDState *s = acb_to_s(acb);
int r;
qemu_co_mutex_unlock(&s->table_lock);
/* Allocate buffer for zero writes */
if (acb->flags & QED_AIOCB_ZERO) {
struct iovec *iov = acb->qiov->iov;
if (!iov->iov_base) {
iov->iov_base = qemu_try_blockalign(acb->bs, iov->iov_len);
if (iov->iov_base == NULL) {
r = -ENOMEM;
goto out;
}
memset(iov->iov_base, 0, iov->iov_len);
}
}
/* Calculate the I/O vector */
acb->cur_cluster = offset;
qemu_iovec_concat(&acb->cur_qiov, acb->qiov, acb->qiov_offset, len);
/* Do the actual write. */
r = qed_aio_write_main(acb);
out:
qemu_co_mutex_lock(&s->table_lock);
return r;
}
/**
* Write data cluster
*
* @opaque: Write request
* @ret: QED_CLUSTER_FOUND, QED_CLUSTER_L2 or QED_CLUSTER_L1
* @offset: Cluster offset in bytes
* @len: Length in bytes
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_write_data(void *opaque, int ret,
uint64_t offset, size_t len)
{
QEDAIOCB *acb = opaque;
trace_qed_aio_write_data(acb_to_s(acb), acb, ret, offset, len);
acb->find_cluster_ret = ret;
switch (ret) {
case QED_CLUSTER_FOUND:
return qed_aio_write_inplace(acb, offset, len);
case QED_CLUSTER_L2:
case QED_CLUSTER_L1:
case QED_CLUSTER_ZERO:
return qed_aio_write_alloc(acb, len);
default:
g_assert_not_reached();
}
}
/**
* Read data cluster
*
* @opaque: Read request
* @ret: QED_CLUSTER_FOUND, QED_CLUSTER_L2 or QED_CLUSTER_L1
* @offset: Cluster offset in bytes
* @len: Length in bytes
*
* Called with table_lock held.
*/
static int coroutine_fn qed_aio_read_data(void *opaque, int ret,
uint64_t offset, size_t len)
{
QEDAIOCB *acb = opaque;
BDRVQEDState *s = acb_to_s(acb);
BlockDriverState *bs = acb->bs;
int r;
qemu_co_mutex_unlock(&s->table_lock);
/* Adjust offset into cluster */
offset += qed_offset_into_cluster(s, acb->cur_pos);
trace_qed_aio_read_data(s, acb, ret, offset, len);
qemu_iovec_concat(&acb->cur_qiov, acb->qiov, acb->qiov_offset, len);
/* Handle zero cluster and backing file reads, otherwise read
* data cluster directly.
*/
if (ret == QED_CLUSTER_ZERO) {
qemu_iovec_memset(&acb->cur_qiov, 0, 0, acb->cur_qiov.size);
r = 0;
} else if (ret != QED_CLUSTER_FOUND) {
r = qed_read_backing_file(s, acb->cur_pos, &acb->cur_qiov,
&acb->backing_qiov);
} else {
BLKDBG_EVENT(bs->file, BLKDBG_READ_AIO);
r = bdrv_co_preadv(bs->file, offset, acb->cur_qiov.size,
&acb->cur_qiov, 0);
}
qemu_co_mutex_lock(&s->table_lock);
return r;
}
/**
* Begin next I/O or complete the request
*/
static int coroutine_fn qed_aio_next_io(QEDAIOCB *acb)
{
BDRVQEDState *s = acb_to_s(acb);
uint64_t offset;
size_t len;
int ret;
qemu_co_mutex_lock(&s->table_lock);
while (1) {
trace_qed_aio_next_io(s, acb, 0, acb->cur_pos + acb->cur_qiov.size);
if (acb->backing_qiov) {
qemu_iovec_destroy(acb->backing_qiov);
g_free(acb->backing_qiov);
acb->backing_qiov = NULL;
}
acb->qiov_offset += acb->cur_qiov.size;
acb->cur_pos += acb->cur_qiov.size;
qemu_iovec_reset(&acb->cur_qiov);
/* Complete request */
if (acb->cur_pos >= acb->end_pos) {
ret = 0;
break;
}
/* Find next cluster and start I/O */
len = acb->end_pos - acb->cur_pos;
ret = qed_find_cluster(s, &acb->request, acb->cur_pos, &len, &offset);
if (ret < 0) {
break;
}
if (acb->flags & QED_AIOCB_WRITE) {
ret = qed_aio_write_data(acb, ret, offset, len);
} else {
ret = qed_aio_read_data(acb, ret, offset, len);
}
if (ret < 0 && ret != -EAGAIN) {
break;
}
}
trace_qed_aio_complete(s, acb, ret);
qed_aio_complete(acb);
qemu_co_mutex_unlock(&s->table_lock);
return ret;
}
static int coroutine_fn qed_co_request(BlockDriverState *bs, int64_t sector_num,
QEMUIOVector *qiov, int nb_sectors,
int flags)
{
QEDAIOCB acb = {
.bs = bs,
.cur_pos = (uint64_t) sector_num * BDRV_SECTOR_SIZE,
.end_pos = (sector_num + nb_sectors) * BDRV_SECTOR_SIZE,
.qiov = qiov,
.flags = flags,
};
qemu_iovec_init(&acb.cur_qiov, qiov->niov);
trace_qed_aio_setup(bs->opaque, &acb, sector_num, nb_sectors, NULL, flags);
/* Start request */
return qed_aio_next_io(&acb);
}
static int coroutine_fn bdrv_qed_co_readv(BlockDriverState *bs,
int64_t sector_num, int nb_sectors,
QEMUIOVector *qiov)
{
return qed_co_request(bs, sector_num, qiov, nb_sectors, 0);
}
static int coroutine_fn bdrv_qed_co_writev(BlockDriverState *bs,
int64_t sector_num, int nb_sectors,
QEMUIOVector *qiov, int flags)
{
assert(!flags);
return qed_co_request(bs, sector_num, qiov, nb_sectors, QED_AIOCB_WRITE);
}
static int coroutine_fn bdrv_qed_co_pwrite_zeroes(BlockDriverState *bs,
int64_t offset,
int bytes,
BdrvRequestFlags flags)
{
BDRVQEDState *s = bs->opaque;
/*
* Zero writes start without an I/O buffer. If a buffer becomes necessary
* then it will be allocated during request processing.
*/
QEMUIOVector qiov = QEMU_IOVEC_INIT_BUF(qiov, NULL, bytes);
/* Fall back if the request is not aligned */
if (qed_offset_into_cluster(s, offset) ||
qed_offset_into_cluster(s, bytes)) {
return -ENOTSUP;
}
return qed_co_request(bs, offset >> BDRV_SECTOR_BITS, &qiov,
bytes >> BDRV_SECTOR_BITS,
QED_AIOCB_WRITE | QED_AIOCB_ZERO);
}
static int coroutine_fn bdrv_qed_co_truncate(BlockDriverState *bs,
int64_t offset,
PreallocMode prealloc,
Error **errp)
{
BDRVQEDState *s = bs->opaque;
uint64_t old_image_size;
int ret;
if (prealloc != PREALLOC_MODE_OFF) {
error_setg(errp, "Unsupported preallocation mode '%s'",
PreallocMode_str(prealloc));
return -ENOTSUP;
}
if (!qed_is_image_size_valid(offset, s->header.cluster_size,
s->header.table_size)) {
error_setg(errp, "Invalid image size specified");
return -EINVAL;
}
if ((uint64_t)offset < s->header.image_size) {
error_setg(errp, "Shrinking images is currently not supported");
return -ENOTSUP;
}
old_image_size = s->header.image_size;
s->header.image_size = offset;
ret = qed_write_header_sync(s);
if (ret < 0) {
s->header.image_size = old_image_size;
error_setg_errno(errp, -ret, "Failed to update the image size");
}
return ret;
}
static int64_t bdrv_qed_getlength(BlockDriverState *bs)
{
BDRVQEDState *s = bs->opaque;
return s->header.image_size;
}
static int bdrv_qed_get_info(BlockDriverState *bs, BlockDriverInfo *bdi)
{
BDRVQEDState *s = bs->opaque;
memset(bdi, 0, sizeof(*bdi));
bdi->cluster_size = s->header.cluster_size;
bdi->is_dirty = s->header.features & QED_F_NEED_CHECK;
bdi->unallocated_blocks_are_zero = true;
return 0;
}
static int bdrv_qed_change_backing_file(BlockDriverState *bs,
const char *backing_file,
const char *backing_fmt)
{
BDRVQEDState *s = bs->opaque;
QEDHeader new_header, le_header;
void *buffer;
size_t buffer_len, backing_file_len;
int ret;
/* Refuse to set backing filename if unknown compat feature bits are
* active. If the image uses an unknown compat feature then we may not
* know the layout of data following the header structure and cannot safely
* add a new string.
*/
if (backing_file && (s->header.compat_features &
~QED_COMPAT_FEATURE_MASK)) {
return -ENOTSUP;
}
memcpy(&new_header, &s->header, sizeof(new_header));
new_header.features &= ~(QED_F_BACKING_FILE |
QED_F_BACKING_FORMAT_NO_PROBE);
/* Adjust feature flags */
if (backing_file) {
new_header.features |= QED_F_BACKING_FILE;
if (qed_fmt_is_raw(backing_fmt)) {
new_header.features |= QED_F_BACKING_FORMAT_NO_PROBE;
}
}
/* Calculate new header size */
backing_file_len = 0;
if (backing_file) {
backing_file_len = strlen(backing_file);
}
buffer_len = sizeof(new_header);
new_header.backing_filename_offset = buffer_len;
new_header.backing_filename_size = backing_file_len;
buffer_len += backing_file_len;
/* Make sure we can rewrite header without failing */
if (buffer_len > new_header.header_size * new_header.cluster_size) {
return -ENOSPC;
}
/* Prepare new header */
buffer = g_malloc(buffer_len);
qed_header_cpu_to_le(&new_header, &le_header);
memcpy(buffer, &le_header, sizeof(le_header));
buffer_len = sizeof(le_header);
if (backing_file) {
memcpy(buffer + buffer_len, backing_file, backing_file_len);
buffer_len += backing_file_len;
}
/* Write new header */
ret = bdrv_pwrite_sync(bs->file, 0, buffer, buffer_len);
g_free(buffer);
if (ret == 0) {
memcpy(&s->header, &new_header, sizeof(new_header));
}
return ret;
}
static void coroutine_fn bdrv_qed_co_invalidate_cache(BlockDriverState *bs,
Error **errp)
{
BDRVQEDState *s = bs->opaque;
Error *local_err = NULL;
int ret;
bdrv_qed_close(bs);
bdrv_qed_init_state(bs);
qemu_co_mutex_lock(&s->table_lock);
ret = bdrv_qed_do_open(bs, NULL, bs->open_flags, &local_err);
qemu_co_mutex_unlock(&s->table_lock);
if (local_err) {
error_propagate_prepend(errp, local_err,
"Could not reopen qed layer: ");
return;
} else if (ret < 0) {
error_setg_errno(errp, -ret, "Could not reopen qed layer");
return;
}
}
static int bdrv_qed_co_check(BlockDriverState *bs, BdrvCheckResult *result,
BdrvCheckMode fix)
{
BDRVQEDState *s = bs->opaque;
int ret;
qemu_co_mutex_lock(&s->table_lock);
ret = qed_check(s, result, !!fix);
qemu_co_mutex_unlock(&s->table_lock);
return ret;
}
static QemuOptsList qed_create_opts = {
.name = "qed-create-opts",
.head = QTAILQ_HEAD_INITIALIZER(qed_create_opts.head),
.desc = {
{
.name = BLOCK_OPT_SIZE,
.type = QEMU_OPT_SIZE,
.help = "Virtual disk size"
},
{
.name = BLOCK_OPT_BACKING_FILE,
.type = QEMU_OPT_STRING,
.help = "File name of a base image"
},
{
.name = BLOCK_OPT_BACKING_FMT,
.type = QEMU_OPT_STRING,
.help = "Image format of the base image"
},
{
.name = BLOCK_OPT_CLUSTER_SIZE,
.type = QEMU_OPT_SIZE,
.help = "Cluster size (in bytes)",
.def_value_str = stringify(QED_DEFAULT_CLUSTER_SIZE)
},
{
.name = BLOCK_OPT_TABLE_SIZE,
.type = QEMU_OPT_SIZE,
.help = "L1/L2 table size (in clusters)"
},
{ /* end of list */ }
}
};
static BlockDriver bdrv_qed = {
.format_name = "qed",
.instance_size = sizeof(BDRVQEDState),
.create_opts = &qed_create_opts,
.supports_backing = true,
.bdrv_probe = bdrv_qed_probe,
.bdrv_open = bdrv_qed_open,
.bdrv_close = bdrv_qed_close,
.bdrv_reopen_prepare = bdrv_qed_reopen_prepare,
.bdrv_child_perm = bdrv_format_default_perms,
.bdrv_co_create = bdrv_qed_co_create,
.bdrv_co_create_opts = bdrv_qed_co_create_opts,
.bdrv_has_zero_init = bdrv_has_zero_init_1,
.bdrv_co_block_status = bdrv_qed_co_block_status,
.bdrv_co_readv = bdrv_qed_co_readv,
.bdrv_co_writev = bdrv_qed_co_writev,
.bdrv_co_pwrite_zeroes = bdrv_qed_co_pwrite_zeroes,
.bdrv_co_truncate = bdrv_qed_co_truncate,
.bdrv_getlength = bdrv_qed_getlength,
.bdrv_get_info = bdrv_qed_get_info,
.bdrv_refresh_limits = bdrv_qed_refresh_limits,
.bdrv_change_backing_file = bdrv_qed_change_backing_file,
.bdrv_co_invalidate_cache = bdrv_qed_co_invalidate_cache,
.bdrv_co_check = bdrv_qed_co_check,
.bdrv_detach_aio_context = bdrv_qed_detach_aio_context,
.bdrv_attach_aio_context = bdrv_qed_attach_aio_context,
.bdrv_co_drain_begin = bdrv_qed_co_drain_begin,
};
static void bdrv_qed_init(void)
{
bdrv_register(&bdrv_qed);
}
block_init(bdrv_qed_init);
|
pmp-tool/PMP | src/qemu/src-pmp/contrib/vhost-user-scsi/vhost-user-scsi.c | <filename>src/qemu/src-pmp/contrib/vhost-user-scsi/vhost-user-scsi.c
/*
* vhost-user-scsi sample application
*
* Copyright (c) 2016 Nutanix Inc. All rights reserved.
*
* Author:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 only.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include <iscsi/iscsi.h>
#include <iscsi/scsi-lowlevel.h>
#include "contrib/libvhost-user/libvhost-user-glib.h"
#include "standard-headers/linux/virtio_scsi.h"
#define VUS_ISCSI_INITIATOR "iqn.2016-11.com.nutanix:vhost-user-scsi"
typedef struct VusIscsiLun {
struct iscsi_context *iscsi_ctx;
int iscsi_lun;
} VusIscsiLun;
typedef struct VusDev {
VugDev parent;
VusIscsiLun lun;
GMainLoop *loop;
} VusDev;
/** libiscsi integration **/
typedef struct virtio_scsi_cmd_req VirtIOSCSICmdReq;
typedef struct virtio_scsi_cmd_resp VirtIOSCSICmdResp;
static int vus_iscsi_add_lun(VusIscsiLun *lun, char *iscsi_uri)
{
struct iscsi_url *iscsi_url;
struct iscsi_context *iscsi_ctx;
int ret = 0;
assert(lun);
assert(iscsi_uri);
assert(!lun->iscsi_ctx);
iscsi_ctx = iscsi_create_context(VUS_ISCSI_INITIATOR);
if (!iscsi_ctx) {
g_warning("Unable to create iSCSI context");
return -1;
}
iscsi_url = iscsi_parse_full_url(iscsi_ctx, iscsi_uri);
if (!iscsi_url) {
g_warning("Unable to parse iSCSI URL: %s", iscsi_get_error(iscsi_ctx));
goto fail;
}
iscsi_set_session_type(iscsi_ctx, ISCSI_SESSION_NORMAL);
iscsi_set_header_digest(iscsi_ctx, ISCSI_HEADER_DIGEST_NONE_CRC32C);
if (iscsi_full_connect_sync(iscsi_ctx, iscsi_url->portal, iscsi_url->lun)) {
g_warning("Unable to login to iSCSI portal: %s",
iscsi_get_error(iscsi_ctx));
goto fail;
}
lun->iscsi_ctx = iscsi_ctx;
lun->iscsi_lun = iscsi_url->lun;
g_debug("Context %p created for lun 0: %s", iscsi_ctx, iscsi_uri);
out:
if (iscsi_url) {
iscsi_destroy_url(iscsi_url);
}
return ret;
fail:
(void)iscsi_destroy_context(iscsi_ctx);
ret = -1;
goto out;
}
static struct scsi_task *scsi_task_new(int cdb_len, uint8_t *cdb, int dir,
int xfer_len)
{
struct scsi_task *task;
assert(cdb_len > 0);
assert(cdb);
task = g_new0(struct scsi_task, 1);
memcpy(task->cdb, cdb, cdb_len);
task->cdb_size = cdb_len;
task->xfer_dir = dir;
task->expxferlen = xfer_len;
return task;
}
static int get_cdb_len(uint8_t *cdb)
{
assert(cdb);
switch (cdb[0] >> 5) {
case 0: return 6;
case 1: /* fall through */
case 2: return 10;
case 4: return 16;
case 5: return 12;
}
g_warning("Unable to determine cdb len (0x%02hhX)", cdb[0] >> 5);
return -1;
}
static int handle_cmd_sync(struct iscsi_context *ctx,
VirtIOSCSICmdReq *req,
struct iovec *out, unsigned int out_len,
VirtIOSCSICmdResp *rsp,
struct iovec *in, unsigned int in_len)
{
struct scsi_task *task;
uint32_t dir;
uint32_t len;
int cdb_len;
int i;
assert(ctx);
assert(req);
assert(rsp);
if (!(!req->lun[1] && req->lun[2] == 0x40 && !req->lun[3])) {
/* Ignore anything different than target=0, lun=0 */
g_debug("Ignoring unconnected lun (0x%hhX, 0x%hhX)",
req->lun[1], req->lun[3]);
rsp->status = SCSI_STATUS_CHECK_CONDITION;
memset(rsp->sense, 0, sizeof(rsp->sense));
rsp->sense_len = 18;
rsp->sense[0] = 0x70;
rsp->sense[2] = SCSI_SENSE_ILLEGAL_REQUEST;
rsp->sense[7] = 10;
rsp->sense[12] = 0x24;
return 0;
}
cdb_len = get_cdb_len(req->cdb);
if (cdb_len == -1) {
return -1;
}
len = 0;
if (!out_len && !in_len) {
dir = SCSI_XFER_NONE;
} else if (out_len) {
dir = SCSI_XFER_WRITE;
for (i = 0; i < out_len; i++) {
len += out[i].iov_len;
}
} else {
dir = SCSI_XFER_READ;
for (i = 0; i < in_len; i++) {
len += in[i].iov_len;
}
}
task = scsi_task_new(cdb_len, req->cdb, dir, len);
if (dir == SCSI_XFER_WRITE) {
task->iovector_out.iov = (struct scsi_iovec *)out;
task->iovector_out.niov = out_len;
} else if (dir == SCSI_XFER_READ) {
task->iovector_in.iov = (struct scsi_iovec *)in;
task->iovector_in.niov = in_len;
}
g_debug("Sending iscsi cmd (cdb_len=%d, dir=%d, task=%p)",
cdb_len, dir, task);
if (!iscsi_scsi_command_sync(ctx, 0, task, NULL)) {
g_warning("Error serving SCSI command");
g_free(task);
return -1;
}
memset(rsp, 0, sizeof(*rsp));
rsp->status = task->status;
rsp->resid = task->residual;
if (task->status == SCSI_STATUS_CHECK_CONDITION) {
rsp->response = VIRTIO_SCSI_S_FAILURE;
rsp->sense_len = task->datain.size - 2;
memcpy(rsp->sense, &task->datain.data[2], rsp->sense_len);
}
g_free(task);
g_debug("Filled in rsp: status=%hhX, resid=%u, response=%hhX, sense_len=%u",
rsp->status, rsp->resid, rsp->response, rsp->sense_len);
return 0;
}
/** libvhost-user callbacks **/
static void vus_panic_cb(VuDev *vu_dev, const char *buf)
{
VugDev *gdev;
VusDev *vdev_scsi;
assert(vu_dev);
gdev = container_of(vu_dev, VugDev, parent);
vdev_scsi = container_of(gdev, VusDev, parent);
if (buf) {
g_warning("vu_panic: %s", buf);
}
g_main_loop_quit(vdev_scsi->loop);
}
static void vus_proc_req(VuDev *vu_dev, int idx)
{
VugDev *gdev;
VusDev *vdev_scsi;
VuVirtq *vq;
assert(vu_dev);
gdev = container_of(vu_dev, VugDev, parent);
vdev_scsi = container_of(gdev, VusDev, parent);
if (idx < 0 || idx >= VHOST_MAX_NR_VIRTQUEUE) {
g_warning("VQ Index out of range: %d", idx);
vus_panic_cb(vu_dev, NULL);
return;
}
vq = vu_get_queue(vu_dev, idx);
if (!vq) {
g_warning("Error fetching VQ (dev=%p, idx=%d)", vu_dev, idx);
vus_panic_cb(vu_dev, NULL);
return;
}
g_debug("Got kicked on vq[%d]@%p", idx, vq);
while (1) {
VuVirtqElement *elem;
VirtIOSCSICmdReq *req;
VirtIOSCSICmdResp *rsp;
elem = vu_queue_pop(vu_dev, vq, sizeof(VuVirtqElement));
if (!elem) {
g_debug("No more elements pending on vq[%d]@%p", idx, vq);
break;
}
g_debug("Popped elem@%p", elem);
assert(!(elem->out_num > 1 && elem->in_num > 1));
assert(elem->out_num > 0 && elem->in_num > 0);
if (elem->out_sg[0].iov_len < sizeof(VirtIOSCSICmdReq)) {
g_warning("Invalid virtio-scsi req header");
vus_panic_cb(vu_dev, NULL);
break;
}
req = (VirtIOSCSICmdReq *)elem->out_sg[0].iov_base;
if (elem->in_sg[0].iov_len < sizeof(VirtIOSCSICmdResp)) {
g_warning("Invalid virtio-scsi rsp header");
vus_panic_cb(vu_dev, NULL);
break;
}
rsp = (VirtIOSCSICmdResp *)elem->in_sg[0].iov_base;
if (handle_cmd_sync(vdev_scsi->lun.iscsi_ctx,
req, &elem->out_sg[1], elem->out_num - 1,
rsp, &elem->in_sg[1], elem->in_num - 1) != 0) {
vus_panic_cb(vu_dev, NULL);
break;
}
vu_queue_push(vu_dev, vq, elem, 0);
vu_queue_notify(vu_dev, vq);
free(elem);
}
}
static void vus_queue_set_started(VuDev *vu_dev, int idx, bool started)
{
VuVirtq *vq;
assert(vu_dev);
if (idx < 0 || idx >= VHOST_MAX_NR_VIRTQUEUE) {
g_warning("VQ Index out of range: %d", idx);
vus_panic_cb(vu_dev, NULL);
return;
}
vq = vu_get_queue(vu_dev, idx);
if (idx == 0 || idx == 1) {
g_debug("queue %d unimplemented", idx);
} else {
vu_set_queue_handler(vu_dev, vq, started ? vus_proc_req : NULL);
}
}
static const VuDevIface vus_iface = {
.queue_set_started = vus_queue_set_started,
};
/** misc helpers **/
static int unix_sock_new(char *unix_fn)
{
int sock;
struct sockaddr_un un;
size_t len;
assert(unix_fn);
sock = socket(AF_UNIX, SOCK_STREAM, 0);
if (sock <= 0) {
perror("socket");
return -1;
}
un.sun_family = AF_UNIX;
(void)snprintf(un.sun_path, sizeof(un.sun_path), "%s", unix_fn);
len = sizeof(un.sun_family) + strlen(un.sun_path);
(void)unlink(unix_fn);
if (bind(sock, (struct sockaddr *)&un, len) < 0) {
perror("bind");
goto fail;
}
if (listen(sock, 1) < 0) {
perror("listen");
goto fail;
}
return sock;
fail:
(void)close(sock);
return -1;
}
/** vhost-user-scsi **/
int main(int argc, char **argv)
{
VusDev *vdev_scsi = NULL;
char *unix_fn = NULL;
char *iscsi_uri = NULL;
int lsock = -1, csock = -1, opt, err = EXIT_SUCCESS;
while ((opt = getopt(argc, argv, "u:i:")) != -1) {
switch (opt) {
case 'h':
goto help;
case 'u':
unix_fn = g_strdup(optarg);
break;
case 'i':
iscsi_uri = g_strdup(optarg);
break;
default:
goto help;
}
}
if (!unix_fn || !iscsi_uri) {
goto help;
}
lsock = unix_sock_new(unix_fn);
if (lsock < 0) {
goto err;
}
csock = accept(lsock, NULL, NULL);
if (csock < 0) {
perror("accept");
goto err;
}
vdev_scsi = g_new0(VusDev, 1);
vdev_scsi->loop = g_main_loop_new(NULL, FALSE);
if (vus_iscsi_add_lun(&vdev_scsi->lun, iscsi_uri) != 0) {
goto err;
}
vug_init(&vdev_scsi->parent, csock, vus_panic_cb, &vus_iface);
g_main_loop_run(vdev_scsi->loop);
vug_deinit(&vdev_scsi->parent);
out:
if (vdev_scsi) {
g_main_loop_unref(vdev_scsi->loop);
g_free(vdev_scsi);
unlink(unix_fn);
}
if (csock >= 0) {
close(csock);
}
if (lsock >= 0) {
close(lsock);
}
g_free(unix_fn);
g_free(iscsi_uri);
return err;
err:
err = EXIT_FAILURE;
goto out;
help:
fprintf(stderr, "Usage: %s [ -u unix_sock_path -i iscsi_uri ] | [ -h ]\n",
argv[0]);
fprintf(stderr, " -u path to unix socket\n");
fprintf(stderr, " -i iscsi uri for lun 0\n");
fprintf(stderr, " -h print help and quit\n");
goto err;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/vmgenid-test.c | /*
* QTest testcase for VM Generation ID
*
* Copyright (c) 2016 Red Hat, Inc.
* Copyright (c) 2017 Skyport Systems
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/bitmap.h"
#include "qemu/uuid.h"
#include "hw/acpi/acpi-defs.h"
#include "boot-sector.h"
#include "acpi-utils.h"
#include "libqtest.h"
#include "qapi/qmp/qdict.h"
#define VGID_GUID "324e6eaf-d1d1-4bf6-bf41-b9bb6c91fb87"
#define VMGENID_GUID_OFFSET 40 /* allow space for
* OVMF SDT Header Probe Supressor
*/
#define RSDP_ADDR_INVALID 0x100000 /* RSDP must be below this address */
static uint32_t acpi_find_vgia(QTestState *qts)
{
uint32_t rsdp_offset;
uint32_t guid_offset = 0;
uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */];
uint32_t rsdt_len, table_length;
uint8_t *rsdt, *ent;
/* Wait for guest firmware to finish and start the payload. */
boot_sector_test(qts);
/* Tables should be initialized now. */
rsdp_offset = acpi_find_rsdp_address(qts);
g_assert_cmphex(rsdp_offset, <, RSDP_ADDR_INVALID);
acpi_parse_rsdp_table(qts, rsdp_offset, rsdp_table);
acpi_fetch_table(qts, &rsdt, &rsdt_len, &rsdp_table[16 /* RsdtAddress */],
"RSDT", true);
ACPI_FOREACH_RSDT_ENTRY(rsdt, rsdt_len, ent, 4 /* Entry size */) {
uint8_t *table_aml;
acpi_fetch_table(qts, &table_aml, &table_length, ent, NULL, true);
if (!memcmp(table_aml + 16 /* OEM Table ID */, "VMGENID", 7)) {
uint32_t vgia_val;
uint8_t *aml = &table_aml[36 /* AML byte-code start */];
/* the first entry in the table should be VGIA
* That's all we need
*/
g_assert(aml[0 /* name_op*/] == 0x08);
g_assert(memcmp(&aml[1 /* name */], "VGIA", 4) == 0);
g_assert(aml[5 /* value op */] == 0x0C /* dword */);
memcpy(&vgia_val, &aml[6 /* value */], 4);
/* The GUID is written at a fixed offset into the fw_cfg file
* in order to implement the "OVMF SDT Header probe suppressor"
* see docs/specs/vmgenid.txt for more details
*/
guid_offset = le32_to_cpu(vgia_val) + VMGENID_GUID_OFFSET;
g_free(table_aml);
break;
}
g_free(table_aml);
}
g_free(rsdt);
return guid_offset;
}
static void read_guid_from_memory(QTestState *qts, QemuUUID *guid)
{
uint32_t vmgenid_addr;
int i;
vmgenid_addr = acpi_find_vgia(qts);
g_assert(vmgenid_addr);
/* Read the GUID directly from guest memory */
for (i = 0; i < 16; i++) {
guid->data[i] = qtest_readb(qts, vmgenid_addr + i);
}
/* The GUID is in little-endian format in the guest, while QEMU
* uses big-endian. Swap after reading.
*/
*guid = qemu_uuid_bswap(*guid);
}
static void read_guid_from_monitor(QTestState *qts, QemuUUID *guid)
{
QDict *rsp, *rsp_ret;
const char *guid_str;
rsp = qtest_qmp(qts, "{ 'execute': 'query-vm-generation-id' }");
if (qdict_haskey(rsp, "return")) {
rsp_ret = qdict_get_qdict(rsp, "return");
g_assert(qdict_haskey(rsp_ret, "guid"));
guid_str = qdict_get_str(rsp_ret, "guid");
g_assert(qemu_uuid_parse(guid_str, guid) == 0);
}
qobject_unref(rsp);
}
static char disk[] = "tests/vmgenid-test-disk-XXXXXX";
#define GUID_CMD(guid) \
"-machine accel=kvm:tcg " \
"-device vmgenid,id=testvgid,guid=%s " \
"-drive id=hd0,if=none,file=%s,format=raw " \
"-device ide-hd,drive=hd0 ", guid, disk
static void vmgenid_set_guid_test(void)
{
QemuUUID expected, measured;
QTestState *qts;
g_assert(qemu_uuid_parse(VGID_GUID, &expected) == 0);
qts = qtest_initf(GUID_CMD(VGID_GUID));
/* Read the GUID from accessing guest memory */
read_guid_from_memory(qts, &measured);
g_assert(memcmp(measured.data, expected.data, sizeof(measured.data)) == 0);
qtest_quit(qts);
}
static void vmgenid_set_guid_auto_test(void)
{
QemuUUID measured;
QTestState *qts;
qts = qtest_initf(GUID_CMD("auto"));
read_guid_from_memory(qts, &measured);
/* Just check that the GUID is non-null */
g_assert(!qemu_uuid_is_null(&measured));
qtest_quit(qts);
}
static void vmgenid_query_monitor_test(void)
{
QemuUUID expected, measured;
QTestState *qts;
g_assert(qemu_uuid_parse(VGID_GUID, &expected) == 0);
qts = qtest_initf(GUID_CMD(VGID_GUID));
/* Read the GUID via the monitor */
read_guid_from_monitor(qts, &measured);
g_assert(memcmp(measured.data, expected.data, sizeof(measured.data)) == 0);
qtest_quit(qts);
}
int main(int argc, char **argv)
{
int ret;
ret = boot_sector_init(disk);
if (ret) {
return ret;
}
g_test_init(&argc, &argv, NULL);
qtest_add_func("/vmgenid/vmgenid/set-guid",
vmgenid_set_guid_test);
qtest_add_func("/vmgenid/vmgenid/set-guid-auto",
vmgenid_set_guid_auto_test);
qtest_add_func("/vmgenid/vmgenid/query-monitor",
vmgenid_query_monitor_test);
ret = g_test_run();
boot_sector_cleanup(disk);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-add/test_msa_adds_s_b.c | /*
* Test program for MSA instruction ADDS_S.B
*
* Copyright (C) 2019 RT-RK Computer Based Systems LLC
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "ADDS_S.B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0xfefefefefefefefeULL, 0xfefefefefefefefeULL, }, /* 0 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0xa9a9a9a9a9a9a9a9ULL, 0xa9a9a9a9a9a9a9a9ULL, },
{ 0x5454545454545454ULL, 0x5454545454545454ULL, },
{ 0xcbcbcbcbcbcbcbcbULL, 0xcbcbcbcbcbcbcbcbULL, },
{ 0x3232323232323232ULL, 0x3232323232323232ULL, },
{ 0xe28d37e28d37e28dULL, 0x37e28d37e28d37e2ULL, },
{ 0x1b70c61b70c61b70ULL, 0xc61b70c61b70c61bULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0xe38e38e38e38e38eULL, 0x38e38e38e38e38e3ULL, },
{ 0x1c71c71c71c71c71ULL, 0xc71c71c71c71c71cULL, },
{ 0xa9a9a9a9a9a9a9a9ULL, 0xa9a9a9a9a9a9a9a9ULL, }, /* 16 */
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0x8080808080808080ULL, 0x8080808080808080ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x8080808080808080ULL, 0x8080808080808080ULL, },
{ 0xddddddddddddddddULL, 0xddddddddddddddddULL, },
{ 0x8d80e28d80e28d80ULL, 0xe28d80e28d80e28dULL, },
{ 0xc61b80c61b80c61bULL, 0x80c61b80c61b80c6ULL, },
{ 0x5454545454545454ULL, 0x5454545454545454ULL, }, /* 24 */
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x2121212121212121ULL, 0x2121212121212121ULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0x38e37f38e37f38e3ULL, 0x7f38e37f38e37f38ULL, },
{ 0x717f1c717f1c717fULL, 0x1c717f1c717f1c71ULL, },
{ 0xcbcbcbcbcbcbcbcbULL, 0xcbcbcbcbcbcbcbcbULL, }, /* 32 */
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0x8080808080808080ULL, 0x8080808080808080ULL, },
{ 0x2121212121212121ULL, 0x2121212121212121ULL, },
{ 0x9898989898989898ULL, 0x9898989898989898ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0xaf8004af8004af80ULL, 0x04af8004af8004afULL, },
{ 0xe83d93e83d93e83dULL, 0x93e83d93e83d93e8ULL, },
{ 0x3232323232323232ULL, 0x3232323232323232ULL, }, /* 40 */
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0xddddddddddddddddULL, 0xddddddddddddddddULL, },
{ 0x7f7f7f7f7f7f7f7fULL, 0x7f7f7f7f7f7f7f7fULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x6666666666666666ULL, 0x6666666666666666ULL, },
{ 0x16c16b16c16b16c1ULL, 0x6b16c16b16c16b16ULL, },
{ 0x4f7ffa4f7ffa4f7fULL, 0xfa4f7ffa4f7ffa4fULL, },
{ 0xe28d37e28d37e28dULL, 0x37e28d37e28d37e2ULL, }, /* 48 */
{ 0xe38e38e38e38e38eULL, 0x38e38e38e38e38e3ULL, },
{ 0x8d80e28d80e28d80ULL, 0xe28d80e28d80e28dULL, },
{ 0x38e37f38e37f38e3ULL, 0x7f38e37f38e37f38ULL, },
{ 0xaf8004af8004af80ULL, 0x04af8004af8004afULL, },
{ 0x16c16b16c16b16c1ULL, 0x6b16c16b16c16b16ULL, },
{ 0xc68070c68070c680ULL, 0x70c68070c68070c6ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x1b70c61b70c61b70ULL, 0xc61b70c61b70c61bULL, }, /* 56 */
{ 0x1c71c71c71c71c71ULL, 0xc71c71c71c71c71cULL, },
{ 0xc61b80c61b80c61bULL, 0x80c61b80c61b80c6ULL, },
{ 0x717f1c717f1c717fULL, 0x1c717f1c717f1c71ULL, },
{ 0xe83d93e83d93e83dULL, 0x93e83d93e83d93e8ULL, },
{ 0x4f7ffa4f7ffa4f7fULL, 0xfa4f7ffa4f7ffa4fULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x387f8e387f8e387fULL, 0x8e387f8e387f8e38ULL, },
{ 0x807fcc98507f7f7fULL, 0x7f7f167ffc7f8018ULL, }, /* 64 */
{ 0x8328e62f75f51c48ULL, 0x5d5ec678137f0208ULL, },
{ 0x807f9480e131e0c0ULL, 0x723fd15da97fd520ULL, },
{ 0xf87ffc197f7f377fULL, 0xd8589336a77f92acULL, },
{ 0x8328e62f75f51c48ULL, 0x5d5ec678137f0208ULL, },
{ 0xf680007f7f808e10ULL, 0x24ee80342a7e7ff8ULL, },
{ 0xa718ae0d06808088ULL, 0x39cf8119c06a7710ULL, },
{ 0x6b0d167f7fc4a956ULL, 0x9fe880f2be7f349cULL, },
{ 0x807f9480e131e0c0ULL, 0x723fd15da97fd520ULL, }, /* 72 */
{ 0xa718ae0d06808088ULL, 0x39cf8119c06a7710ULL, },
{ 0x807f8080809e8080ULL, 0x4eb08cfe80564a28ULL, },
{ 0x1c7fc4f7170080ceULL, 0xb4c980d7806d07b4ULL, },
{ 0xf87ffc197f7f377fULL, 0xd8589336a77f92acULL, },
{ 0x6b0d167f7fc4a956ULL, 0x9fe880f2be7f349cULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_ADDS_S_B(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_ADDS_S_B(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/net/e1000.c | <reponame>pmp-tool/PMP
/*
* QEMU e1000 emulation
*
* Software developer's manual:
* http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
*
* <NAME>, Tutis Systems Ltd. for Qumranet Inc.
* Copyright (c) 2008 Qumranet
* Based on work done by:
* Copyright (c) 2007 <NAME>
* Copyright (c) 2004 <NAME>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "net/net.h"
#include "net/checksum.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"
#include "qemu/iov.h"
#include "qemu/range.h"
#include "e1000x_common.h"
#include "trace.h"
static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/* #define E1000_DEBUG */
#ifdef E1000_DEBUG
enum {
DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
};
#define DBGBIT(x) (1<<DEBUG_##x)
static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
#define DBGOUT(what, fmt, ...) do { \
if (debugflags & DBGBIT(what)) \
fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
} while (0)
#else
#define DBGOUT(what, fmt, ...) do {} while (0)
#endif
#define IOPORT_SIZE 0x40
#define PNPMMIO_SIZE 0x20000
#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
#define MAXIMUM_ETHERNET_HDR_LEN (14+4)
/*
* HW models:
* E1000_DEV_ID_82540EM works with Windows, Linux, and OS X <= 10.8
* E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
* E1000_DEV_ID_82545EM_COPPER works with Linux and OS X >= 10.6
* Others never tested
*/
typedef struct E1000State_st {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
NICState *nic;
NICConf conf;
MemoryRegion mmio;
MemoryRegion io;
uint32_t mac_reg[0x8000];
uint16_t phy_reg[0x20];
uint16_t eeprom_data[64];
uint32_t rxbuf_size;
uint32_t rxbuf_min_shift;
struct e1000_tx {
unsigned char header[256];
unsigned char vlan_header[4];
/* Fields vlan and data must not be reordered or separated. */
unsigned char vlan[4];
unsigned char data[0x10000];
uint16_t size;
unsigned char vlan_needed;
unsigned char sum_needed;
bool cptse;
e1000x_txd_props props;
e1000x_txd_props tso_props;
uint16_t tso_frames;
} tx;
struct {
uint32_t val_in; /* shifted in from guest driver */
uint16_t bitnum_in;
uint16_t bitnum_out;
uint16_t reading;
uint32_t old_eecd;
} eecd_state;
QEMUTimer *autoneg_timer;
QEMUTimer *mit_timer; /* Mitigation timer. */
bool mit_timer_on; /* Mitigation timer is running. */
bool mit_irq_level; /* Tracks interrupt pin level. */
uint32_t mit_ide; /* Tracks E1000_TXD_CMD_IDE bit. */
QEMUTimer *flush_queue_timer;
/* Compatibility flags for migration to/from qemu 1.3.0 and older */
#define E1000_FLAG_AUTONEG_BIT 0
#define E1000_FLAG_MIT_BIT 1
#define E1000_FLAG_MAC_BIT 2
#define E1000_FLAG_TSO_BIT 3
#define E1000_FLAG_AUTONEG (1 << E1000_FLAG_AUTONEG_BIT)
#define E1000_FLAG_MIT (1 << E1000_FLAG_MIT_BIT)
#define E1000_FLAG_MAC (1 << E1000_FLAG_MAC_BIT)
#define E1000_FLAG_TSO (1 << E1000_FLAG_TSO_BIT)
uint32_t compat_flags;
bool received_tx_tso;
bool use_tso_for_migration;
e1000x_txd_props mig_props;
} E1000State;
#define chkflag(x) (s->compat_flags & E1000_FLAG_##x)
typedef struct E1000BaseClass {
PCIDeviceClass parent_class;
uint16_t phy_id2;
} E1000BaseClass;
#define TYPE_E1000_BASE "e1000-base"
#define E1000(obj) \
OBJECT_CHECK(E1000State, (obj), TYPE_E1000_BASE)
#define E1000_DEVICE_CLASS(klass) \
OBJECT_CLASS_CHECK(E1000BaseClass, (klass), TYPE_E1000_BASE)
#define E1000_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
static void
e1000_link_up(E1000State *s)
{
e1000x_update_regs_on_link_up(s->mac_reg, s->phy_reg);
/* E1000_STATUS_LU is tested by e1000_can_receive() */
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
static void
e1000_autoneg_done(E1000State *s)
{
e1000x_update_regs_on_autoneg_done(s->mac_reg, s->phy_reg);
/* E1000_STATUS_LU is tested by e1000_can_receive() */
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
static bool
have_autoneg(E1000State *s)
{
return chkflag(AUTONEG) && (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN);
}
static void
set_phy_ctrl(E1000State *s, int index, uint16_t val)
{
/* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
s->phy_reg[PHY_CTRL] = val & ~(0x3f |
MII_CR_RESET |
MII_CR_RESTART_AUTO_NEG);
/*
* QEMU 1.3 does not support link auto-negotiation emulation, so if we
* migrate during auto negotiation, after migration the link will be
* down.
*/
if (have_autoneg(s) && (val & MII_CR_RESTART_AUTO_NEG)) {
e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer);
}
}
static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
[PHY_CTRL] = set_phy_ctrl,
};
enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
static const char phy_regcap[0x20] = {
[PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
[PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R,
[PHY_AUTONEG_EXP] = PHY_R,
};
/* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */
static const uint16_t phy_reg_init[] = {
[PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
MII_CR_FULL_DUPLEX |
MII_CR_AUTO_NEG_EN,
[PHY_STATUS] = MII_SR_EXTENDED_CAPS |
MII_SR_LINK_STATUS | /* link initially up */
MII_SR_AUTONEG_CAPS |
/* MII_SR_AUTONEG_COMPLETE: initially NOT completed */
MII_SR_PREAMBLE_SUPPRESS |
MII_SR_EXTENDED_STATUS |
MII_SR_10T_HD_CAPS |
MII_SR_10T_FD_CAPS |
MII_SR_100X_HD_CAPS |
MII_SR_100X_FD_CAPS,
[PHY_ID1] = 0x141,
/* [PHY_ID2] configured per DevId, from e1000_reset() */
[PHY_AUTONEG_ADV] = 0xde1,
[PHY_LP_ABILITY] = 0x1e0,
[PHY_1000T_CTRL] = 0x0e00,
[PHY_1000T_STATUS] = 0x3c00,
[M88E1000_PHY_SPEC_CTRL] = 0x360,
[M88E1000_PHY_SPEC_STATUS] = 0xac00,
[M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60,
};
static const uint32_t mac_reg_init[] = {
[PBA] = 0x00100030,
[LEDCTL] = 0x602,
[CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
[STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
E1000_STATUS_LU,
[MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
E1000_MANC_RMCP_EN,
};
/* Helper function, *curr == 0 means the value is not set */
static inline void
mit_update_delay(uint32_t *curr, uint32_t value)
{
if (value && (*curr == 0 || value < *curr)) {
*curr = value;
}
}
static void
set_interrupt_cause(E1000State *s, int index, uint32_t val)
{
PCIDevice *d = PCI_DEVICE(s);
uint32_t pending_ints;
uint32_t mit_delay;
s->mac_reg[ICR] = val;
/*
* Make sure ICR and ICS registers have the same value.
* The spec says that the ICS register is write-only. However in practice,
* on real hardware ICS is readable, and for reads it has the same value as
* ICR (except that ICS does not have the clear on read behaviour of ICR).
*
* The VxWorks PRO/1000 driver uses this behaviour.
*/
s->mac_reg[ICS] = val;
pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]);
if (!s->mit_irq_level && pending_ints) {
/*
* Here we detect a potential raising edge. We postpone raising the
* interrupt line if we are inside the mitigation delay window
* (s->mit_timer_on == 1).
* We provide a partial implementation of interrupt mitigation,
* emulating only RADV, TADV and ITR (lower 16 bits, 1024ns units for
* RADV and TADV, 256ns units for ITR). RDTR is only used to enable
* RADV; relative timers based on TIDV and RDTR are not implemented.
*/
if (s->mit_timer_on) {
return;
}
if (chkflag(MIT)) {
/* Compute the next mitigation delay according to pending
* interrupts and the current values of RADV (provided
* RDTR!=0), TADV and ITR.
* Then rearm the timer.
*/
mit_delay = 0;
if (s->mit_ide &&
(pending_ints & (E1000_ICR_TXQE | E1000_ICR_TXDW))) {
mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4);
}
if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) {
mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4);
}
mit_update_delay(&mit_delay, s->mac_reg[ITR]);
/*
* According to e1000 SPEC, the Ethernet controller guarantees
* a maximum observable interrupt rate of 7813 interrupts/sec.
* Thus if mit_delay < 500 then the delay should be set to the
* minimum delay possible which is 500.
*/
mit_delay = (mit_delay < 500) ? 500 : mit_delay;
s->mit_timer_on = 1;
timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
mit_delay * 256);
s->mit_ide = 0;
}
}
s->mit_irq_level = (pending_ints != 0);
pci_set_irq(d, s->mit_irq_level);
}
static void
e1000_mit_timer(void *opaque)
{
E1000State *s = opaque;
s->mit_timer_on = 0;
/* Call set_interrupt_cause to update the irq level (if necessary). */
set_interrupt_cause(s, 0, s->mac_reg[ICR]);
}
static void
set_ics(E1000State *s, int index, uint32_t val)
{
DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
s->mac_reg[IMS]);
set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
}
static void
e1000_autoneg_timer(void *opaque)
{
E1000State *s = opaque;
if (!qemu_get_queue(s->nic)->link_down) {
e1000_autoneg_done(s);
set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */
}
}
static void e1000_reset(void *opaque)
{
E1000State *d = opaque;
E1000BaseClass *edc = E1000_DEVICE_GET_CLASS(d);
uint8_t *macaddr = d->conf.macaddr.a;
timer_del(d->autoneg_timer);
timer_del(d->mit_timer);
timer_del(d->flush_queue_timer);
d->mit_timer_on = 0;
d->mit_irq_level = 0;
d->mit_ide = 0;
memset(d->phy_reg, 0, sizeof d->phy_reg);
memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
d->phy_reg[PHY_ID2] = edc->phy_id2;
memset(d->mac_reg, 0, sizeof d->mac_reg);
memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
d->rxbuf_min_shift = 1;
memset(&d->tx, 0, sizeof d->tx);
if (qemu_get_queue(d->nic)->link_down) {
e1000x_update_regs_on_link_down(d->mac_reg, d->phy_reg);
}
e1000x_reset_mac_addr(d->nic, d->mac_reg, macaddr);
}
static void
set_ctrl(E1000State *s, int index, uint32_t val)
{
/* RST is self clearing */
s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
}
static void
e1000_flush_queue_timer(void *opaque)
{
E1000State *s = opaque;
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
static void
set_rx_control(E1000State *s, int index, uint32_t val)
{
s->mac_reg[RCTL] = val;
s->rxbuf_size = e1000x_rxbufsize(val);
s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
s->mac_reg[RCTL]);
timer_mod(s->flush_queue_timer,
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
}
static void
set_mdic(E1000State *s, int index, uint32_t val)
{
uint32_t data = val & E1000_MDIC_DATA_MASK;
uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
else if (val & E1000_MDIC_OP_READ) {
DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
if (!(phy_regcap[addr] & PHY_R)) {
DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
val |= E1000_MDIC_ERROR;
} else
val = (val ^ data) | s->phy_reg[addr];
} else if (val & E1000_MDIC_OP_WRITE) {
DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
if (!(phy_regcap[addr] & PHY_W)) {
DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
val |= E1000_MDIC_ERROR;
} else {
if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
phyreg_writeops[addr](s, index, data);
} else {
s->phy_reg[addr] = data;
}
}
}
s->mac_reg[MDIC] = val | E1000_MDIC_READY;
if (val & E1000_MDIC_INT_EN) {
set_ics(s, 0, E1000_ICR_MDAC);
}
}
static uint32_t
get_eecd(E1000State *s, int index)
{
uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
s->eecd_state.bitnum_out, s->eecd_state.reading);
if (!s->eecd_state.reading ||
((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
ret |= E1000_EECD_DO;
return ret;
}
static void
set_eecd(E1000State *s, int index, uint32_t val)
{
uint32_t oldval = s->eecd_state.old_eecd;
s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
if (!(E1000_EECD_CS & val)) { /* CS inactive; nothing to do */
return;
}
if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */
s->eecd_state.val_in = 0;
s->eecd_state.bitnum_in = 0;
s->eecd_state.bitnum_out = 0;
s->eecd_state.reading = 0;
}
if (!(E1000_EECD_SK & (val ^ oldval))) { /* no clock edge */
return;
}
if (!(E1000_EECD_SK & val)) { /* falling edge */
s->eecd_state.bitnum_out++;
return;
}
s->eecd_state.val_in <<= 1;
if (val & E1000_EECD_DI)
s->eecd_state.val_in |= 1;
if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
EEPROM_READ_OPCODE_MICROWIRE);
}
DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
s->eecd_state.reading);
}
static uint32_t
flash_eerd_read(E1000State *s, int x)
{
unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
return (s->mac_reg[EERD]);
if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
return (E1000_EEPROM_RW_REG_DONE | r);
return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
E1000_EEPROM_RW_REG_DONE | r);
}
static void
putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
{
uint32_t sum;
if (cse && cse < n)
n = cse + 1;
if (sloc < n-1) {
sum = net_checksum_add(n-css, data+css);
stw_be_p(data + sloc, net_checksum_finish_nozero(sum));
}
}
static inline void
inc_tx_bcast_or_mcast_count(E1000State *s, const unsigned char *arr)
{
if (!memcmp(arr, bcast, sizeof bcast)) {
e1000x_inc_reg_if_not_full(s->mac_reg, BPTC);
} else if (arr[0] & 1) {
e1000x_inc_reg_if_not_full(s->mac_reg, MPTC);
}
}
static void
e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
{
static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
PTC1023, PTC1522 };
NetClientState *nc = qemu_get_queue(s->nic);
if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
nc->info->receive(nc, buf, size);
} else {
qemu_send_packet(nc, buf, size);
}
inc_tx_bcast_or_mcast_count(s, buf);
e1000x_increase_size_stats(s->mac_reg, PTCregs, size);
}
static void
xmit_seg(E1000State *s)
{
uint16_t len;
unsigned int frames = s->tx.tso_frames, css, sofar;
struct e1000_tx *tp = &s->tx;
struct e1000x_txd_props *props = tp->cptse ? &tp->tso_props : &tp->props;
if (tp->cptse) {
css = props->ipcss;
DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
frames, tp->size, css);
if (props->ip) { /* IPv4 */
stw_be_p(tp->data+css+2, tp->size - css);
stw_be_p(tp->data+css+4,
lduw_be_p(tp->data + css + 4) + frames);
} else { /* IPv6 */
stw_be_p(tp->data+css+4, tp->size - css);
}
css = props->tucss;
len = tp->size - css;
DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", props->tcp, css, len);
if (props->tcp) {
sofar = frames * props->mss;
stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
if (props->paylen - sofar > props->mss) {
tp->data[css + 13] &= ~9; /* PSH, FIN */
} else if (frames) {
e1000x_inc_reg_if_not_full(s->mac_reg, TSCTC);
}
} else { /* UDP */
stw_be_p(tp->data+css+4, len);
}
if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
unsigned int phsum;
// add pseudo-header length before checksum calculation
void *sp = tp->data + props->tucso;
phsum = lduw_be_p(sp) + len;
phsum = (phsum >> 16) + (phsum & 0xffff);
stw_be_p(sp, phsum);
}
tp->tso_frames++;
}
if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
putsum(tp->data, tp->size, props->tucso, props->tucss, props->tucse);
}
if (tp->sum_needed & E1000_TXD_POPTS_IXSM) {
putsum(tp->data, tp->size, props->ipcso, props->ipcss, props->ipcse);
}
if (tp->vlan_needed) {
memmove(tp->vlan, tp->data, 4);
memmove(tp->data, tp->data + 4, 8);
memcpy(tp->data + 8, tp->vlan_header, 4);
e1000_send_packet(s, tp->vlan, tp->size + 4);
} else {
e1000_send_packet(s, tp->data, tp->size);
}
e1000x_inc_reg_if_not_full(s->mac_reg, TPT);
e1000x_grow_8reg_if_not_full(s->mac_reg, TOTL, s->tx.size);
s->mac_reg[GPTC] = s->mac_reg[TPT];
s->mac_reg[GOTCL] = s->mac_reg[TOTL];
s->mac_reg[GOTCH] = s->mac_reg[TOTH];
}
static void
process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
{
PCIDevice *d = PCI_DEVICE(s);
uint32_t txd_lower = le32_to_cpu(dp->lower.data);
uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
unsigned int split_size = txd_lower & 0xffff, bytes, sz;
unsigned int msh = 0xfffff;
uint64_t addr;
struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
struct e1000_tx *tp = &s->tx;
s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);
if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
if (le32_to_cpu(xp->cmd_and_length) & E1000_TXD_CMD_TSE) {
e1000x_read_tx_ctx_descr(xp, &tp->tso_props);
s->use_tso_for_migration = 1;
tp->tso_frames = 0;
} else {
e1000x_read_tx_ctx_descr(xp, &tp->props);
s->use_tso_for_migration = 0;
}
return;
} else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
// data descriptor
if (tp->size == 0) {
tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
}
tp->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
} else {
// legacy descriptor
tp->cptse = 0;
}
if (e1000x_vlan_enabled(s->mac_reg) &&
e1000x_is_vlan_txd(txd_lower) &&
(tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
tp->vlan_needed = 1;
stw_be_p(tp->vlan_header,
le16_to_cpu(s->mac_reg[VET]));
stw_be_p(tp->vlan_header + 2,
le16_to_cpu(dp->upper.fields.special));
}
addr = le64_to_cpu(dp->buffer_addr);
if (tp->cptse) {
msh = tp->tso_props.hdr_len + tp->tso_props.mss;
do {
bytes = split_size;
if (tp->size + bytes > msh)
bytes = msh - tp->size;
bytes = MIN(sizeof(tp->data) - tp->size, bytes);
pci_dma_read(d, addr, tp->data + tp->size, bytes);
sz = tp->size + bytes;
if (sz >= tp->tso_props.hdr_len
&& tp->size < tp->tso_props.hdr_len) {
memmove(tp->header, tp->data, tp->tso_props.hdr_len);
}
tp->size = sz;
addr += bytes;
if (sz == msh) {
xmit_seg(s);
memmove(tp->data, tp->header, tp->tso_props.hdr_len);
tp->size = tp->tso_props.hdr_len;
}
split_size -= bytes;
} while (bytes && split_size);
} else {
split_size = MIN(sizeof(tp->data) - tp->size, split_size);
pci_dma_read(d, addr, tp->data + tp->size, split_size);
tp->size += split_size;
}
if (!(txd_lower & E1000_TXD_CMD_EOP))
return;
if (!(tp->cptse && tp->size < tp->tso_props.hdr_len)) {
xmit_seg(s);
}
tp->tso_frames = 0;
tp->sum_needed = 0;
tp->vlan_needed = 0;
tp->size = 0;
tp->cptse = 0;
}
static uint32_t
txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
{
PCIDevice *d = PCI_DEVICE(s);
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
return 0;
txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
dp->upper.data = cpu_to_le32(txd_upper);
pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp),
&dp->upper, sizeof(dp->upper));
return E1000_ICR_TXDW;
}
static uint64_t tx_desc_base(E1000State *s)
{
uint64_t bah = s->mac_reg[TDBAH];
uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
return (bah << 32) + bal;
}
static void
start_xmit(E1000State *s)
{
PCIDevice *d = PCI_DEVICE(s);
dma_addr_t base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
DBGOUT(TX, "tx disabled\n");
return;
}
while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
base = tx_desc_base(s) +
sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
pci_dma_read(d, base, &desc, sizeof(desc));
DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
(void *)(intptr_t)desc.buffer_addr, desc.lower.data,
desc.upper.data);
process_tx_desc(s, &desc);
cause |= txdesc_writeback(s, base, &desc);
if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
s->mac_reg[TDH] = 0;
/*
* the following could happen only if guest sw assigns
* bogus values to TDT/TDLEN.
* there's nothing too intelligent we could do about this.
*/
if (s->mac_reg[TDH] == tdh_start ||
tdh_start >= s->mac_reg[TDLEN] / sizeof(desc)) {
DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
break;
}
}
set_ics(s, 0, cause);
}
static int
receive_filter(E1000State *s, const uint8_t *buf, int size)
{
uint32_t rctl = s->mac_reg[RCTL];
int isbcast = !memcmp(buf, bcast, sizeof bcast), ismcast = (buf[0] & 1);
if (e1000x_is_vlan_packet(buf, le16_to_cpu(s->mac_reg[VET])) &&
e1000x_vlan_rx_filter_enabled(s->mac_reg)) {
uint16_t vid = lduw_be_p(buf + 14);
uint32_t vfta = ldl_le_p((uint32_t*)(s->mac_reg + VFTA) +
((vid >> 5) & 0x7f));
if ((vfta & (1 << (vid & 0x1f))) == 0)
return 0;
}
if (!isbcast && !ismcast && (rctl & E1000_RCTL_UPE)) { /* promiscuous ucast */
return 1;
}
if (ismcast && (rctl & E1000_RCTL_MPE)) { /* promiscuous mcast */
e1000x_inc_reg_if_not_full(s->mac_reg, MPRC);
return 1;
}
if (isbcast && (rctl & E1000_RCTL_BAM)) { /* broadcast enabled */
e1000x_inc_reg_if_not_full(s->mac_reg, BPRC);
return 1;
}
return e1000x_rx_group_filter(s->mac_reg, buf);
}
static void
e1000_set_link_status(NetClientState *nc)
{
E1000State *s = qemu_get_nic_opaque(nc);
uint32_t old_status = s->mac_reg[STATUS];
if (nc->link_down) {
e1000x_update_regs_on_link_down(s->mac_reg, s->phy_reg);
} else {
if (have_autoneg(s) &&
!(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer);
} else {
e1000_link_up(s);
}
}
if (s->mac_reg[STATUS] != old_status)
set_ics(s, 0, E1000_ICR_LSC);
}
static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
{
int bufs;
/* Fast-path short packets */
if (total_size <= s->rxbuf_size) {
return s->mac_reg[RDH] != s->mac_reg[RDT];
}
if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
} else if (s->mac_reg[RDH] > s->mac_reg[RDT]) {
bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
s->mac_reg[RDT] - s->mac_reg[RDH];
} else {
return false;
}
return total_size <= bufs * s->rxbuf_size;
}
static int
e1000_can_receive(NetClientState *nc)
{
E1000State *s = qemu_get_nic_opaque(nc);
return e1000x_rx_ready(&s->parent_obj, s->mac_reg) &&
e1000_has_rxbufs(s, 1) && !timer_pending(s->flush_queue_timer);
}
static uint64_t rx_desc_base(E1000State *s)
{
uint64_t bah = s->mac_reg[RDBAH];
uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
return (bah << 32) + bal;
}
static void
e1000_receiver_overrun(E1000State *s, size_t size)
{
trace_e1000_receiver_overrun(size, s->mac_reg[RDH], s->mac_reg[RDT]);
e1000x_inc_reg_if_not_full(s->mac_reg, RNBC);
e1000x_inc_reg_if_not_full(s->mac_reg, MPC);
set_ics(s, 0, E1000_ICS_RXO);
}
static ssize_t
e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
{
E1000State *s = qemu_get_nic_opaque(nc);
PCIDevice *d = PCI_DEVICE(s);
struct e1000_rx_desc desc;
dma_addr_t base;
unsigned int n, rdt;
uint32_t rdh_start;
uint16_t vlan_special = 0;
uint8_t vlan_status = 0;
uint8_t min_buf[MIN_BUF_SIZE];
struct iovec min_iov;
uint8_t *filter_buf = iov->iov_base;
size_t size = iov_size(iov, iovcnt);
size_t iov_ofs = 0;
size_t desc_offset;
size_t desc_size;
size_t total_size;
if (!e1000x_hw_rx_enabled(s->mac_reg)) {
return -1;
}
if (timer_pending(s->flush_queue_timer)) {
return 0;
}
/* Pad to minimum Ethernet frame length */
if (size < sizeof(min_buf)) {
iov_to_buf(iov, iovcnt, 0, min_buf, size);
memset(&min_buf[size], 0, sizeof(min_buf) - size);
e1000x_inc_reg_if_not_full(s->mac_reg, RUC);
min_iov.iov_base = filter_buf = min_buf;
min_iov.iov_len = size = sizeof(min_buf);
iovcnt = 1;
iov = &min_iov;
} else if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) {
/* This is very unlikely, but may happen. */
iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN);
filter_buf = min_buf;
}
/* Discard oversized packets if !LPE and !SBP. */
if (e1000x_is_oversized(s->mac_reg, size)) {
return size;
}
if (!receive_filter(s, filter_buf, size)) {
return size;
}
if (e1000x_vlan_enabled(s->mac_reg) &&
e1000x_is_vlan_packet(filter_buf, le16_to_cpu(s->mac_reg[VET]))) {
vlan_special = cpu_to_le16(lduw_be_p(filter_buf + 14));
iov_ofs = 4;
if (filter_buf == iov->iov_base) {
memmove(filter_buf + 4, filter_buf, 12);
} else {
iov_from_buf(iov, iovcnt, 4, filter_buf, 12);
while (iov->iov_len <= iov_ofs) {
iov_ofs -= iov->iov_len;
iov++;
}
}
vlan_status = E1000_RXD_STAT_VP;
size -= 4;
}
rdh_start = s->mac_reg[RDH];
desc_offset = 0;
total_size = size + e1000x_fcs_len(s->mac_reg);
if (!e1000_has_rxbufs(s, total_size)) {
e1000_receiver_overrun(s, total_size);
return -1;
}
do {
desc_size = total_size - desc_offset;
if (desc_size > s->rxbuf_size) {
desc_size = s->rxbuf_size;
}
base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
pci_dma_read(d, base, &desc, sizeof(desc));
desc.special = vlan_special;
desc.status |= (vlan_status | E1000_RXD_STAT_DD);
if (desc.buffer_addr) {
if (desc_offset < size) {
size_t iov_copy;
hwaddr ba = le64_to_cpu(desc.buffer_addr);
size_t copy_size = size - desc_offset;
if (copy_size > s->rxbuf_size) {
copy_size = s->rxbuf_size;
}
do {
iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
pci_dma_write(d, ba, iov->iov_base + iov_ofs, iov_copy);
copy_size -= iov_copy;
ba += iov_copy;
iov_ofs += iov_copy;
if (iov_ofs == iov->iov_len) {
iov++;
iov_ofs = 0;
}
} while (copy_size);
}
desc_offset += desc_size;
desc.length = cpu_to_le16(desc_size);
if (desc_offset >= total_size) {
desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
} else {
/* Guest zeroing out status is not a hardware requirement.
Clear EOP in case guest didn't do it. */
desc.status &= ~E1000_RXD_STAT_EOP;
}
} else { // as per intel docs; skip descriptors with null buf addr
DBGOUT(RX, "Null RX descriptor!!\n");
}
pci_dma_write(d, base, &desc, sizeof(desc));
if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
s->mac_reg[RDH] = 0;
/* see comment in start_xmit; same here */
if (s->mac_reg[RDH] == rdh_start ||
rdh_start >= s->mac_reg[RDLEN] / sizeof(desc)) {
DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
e1000_receiver_overrun(s, total_size);
return -1;
}
} while (desc_offset < total_size);
e1000x_update_rx_total_stats(s->mac_reg, size, total_size);
n = E1000_ICS_RXT0;
if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
rdt += s->mac_reg[RDLEN] / sizeof(desc);
if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
s->rxbuf_min_shift)
n |= E1000_ICS_RXDMT0;
set_ics(s, 0, n);
return size;
}
static ssize_t
e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
const struct iovec iov = {
.iov_base = (uint8_t *)buf,
.iov_len = size
};
return e1000_receive_iov(nc, &iov, 1);
}
static uint32_t
mac_readreg(E1000State *s, int index)
{
return s->mac_reg[index];
}
static uint32_t
mac_low4_read(E1000State *s, int index)
{
return s->mac_reg[index] & 0xf;
}
static uint32_t
mac_low11_read(E1000State *s, int index)
{
return s->mac_reg[index] & 0x7ff;
}
static uint32_t
mac_low13_read(E1000State *s, int index)
{
return s->mac_reg[index] & 0x1fff;
}
static uint32_t
mac_low16_read(E1000State *s, int index)
{
return s->mac_reg[index] & 0xffff;
}
static uint32_t
mac_icr_read(E1000State *s, int index)
{
uint32_t ret = s->mac_reg[ICR];
DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
set_interrupt_cause(s, 0, 0);
return ret;
}
static uint32_t
mac_read_clr4(E1000State *s, int index)
{
uint32_t ret = s->mac_reg[index];
s->mac_reg[index] = 0;
return ret;
}
static uint32_t
mac_read_clr8(E1000State *s, int index)
{
uint32_t ret = s->mac_reg[index];
s->mac_reg[index] = 0;
s->mac_reg[index-1] = 0;
return ret;
}
static void
mac_writereg(E1000State *s, int index, uint32_t val)
{
uint32_t macaddr[2];
s->mac_reg[index] = val;
if (index == RA + 1) {
macaddr[0] = cpu_to_le32(s->mac_reg[RA]);
macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]);
qemu_format_nic_info_str(qemu_get_queue(s->nic), (uint8_t *)macaddr);
}
}
static void
set_rdt(E1000State *s, int index, uint32_t val)
{
s->mac_reg[index] = val & 0xffff;
if (e1000_has_rxbufs(s, 1)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
}
static void
set_16bit(E1000State *s, int index, uint32_t val)
{
s->mac_reg[index] = val & 0xffff;
}
static void
set_dlen(E1000State *s, int index, uint32_t val)
{
s->mac_reg[index] = val & 0xfff80;
}
static void
set_tctl(E1000State *s, int index, uint32_t val)
{
s->mac_reg[index] = val;
s->mac_reg[TDT] &= 0xffff;
start_xmit(s);
}
static void
set_icr(E1000State *s, int index, uint32_t val)
{
DBGOUT(INTERRUPT, "set_icr %x\n", val);
set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
}
static void
set_imc(E1000State *s, int index, uint32_t val)
{
s->mac_reg[IMS] &= ~val;
set_ics(s, 0, 0);
}
static void
set_ims(E1000State *s, int index, uint32_t val)
{
s->mac_reg[IMS] |= val;
set_ics(s, 0, 0);
}
#define getreg(x) [x] = mac_readreg
static uint32_t (*macreg_readops[])(E1000State *, int) = {
getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL),
getreg(GOTCL),
[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
[GOTCH] = mac_read_clr8, [GORCH] = mac_read_clr8,
[PRC64] = mac_read_clr4, [PRC127] = mac_read_clr4,
[PRC255] = mac_read_clr4, [PRC511] = mac_read_clr4,
[PRC1023] = mac_read_clr4, [PRC1522] = mac_read_clr4,
[PTC64] = mac_read_clr4, [PTC127] = mac_read_clr4,
[PTC255] = mac_read_clr4, [PTC511] = mac_read_clr4,
[PTC1023] = mac_read_clr4, [PTC1522] = mac_read_clr4,
[GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
[TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
[RUC] = mac_read_clr4, [ROC] = mac_read_clr4,
[BPRC] = mac_read_clr4, [MPRC] = mac_read_clr4,
[TSCTC] = mac_read_clr4, [BPTC] = mac_read_clr4,
[MPTC] = mac_read_clr4,
[ICR] = mac_icr_read, [EECD] = get_eecd,
[EERD] = flash_eerd_read,
[RDFH] = mac_low13_read, [RDFT] = mac_low13_read,
[RDFHS] = mac_low13_read, [RDFTS] = mac_low13_read,
[RDFPC] = mac_low13_read,
[TDFH] = mac_low11_read, [TDFT] = mac_low11_read,
[TDFHS] = mac_low13_read, [TDFTS] = mac_low13_read,
[TDFPC] = mac_low13_read,
[AIT] = mac_low16_read,
[CRCERRS ... MPC] = &mac_readreg,
[IP6AT ... IP6AT+3] = &mac_readreg, [IP4AT ... IP4AT+6] = &mac_readreg,
[FFLT ... FFLT+6] = &mac_low11_read,
[RA ... RA+31] = &mac_readreg,
[WUPM ... WUPM+31] = &mac_readreg,
[MTA ... MTA+127] = &mac_readreg,
[VFTA ... VFTA+127] = &mac_readreg,
[FFMT ... FFMT+254] = &mac_low4_read,
[FFVT ... FFVT+254] = &mac_readreg,
[PBM ... PBM+16383] = &mac_readreg,
};
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
#define putreg(x) [x] = mac_writereg
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC),
putreg(TDFH), putreg(TDFT), putreg(TDFHS), putreg(TDFTS),
putreg(TDFPC), putreg(RDFH), putreg(RDFT), putreg(RDFHS),
putreg(RDFTS), putreg(RDFPC), putreg(IPAV), putreg(WUC),
putreg(WUS), putreg(AIT),
[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
[TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
[IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
[RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
[ITR] = set_16bit,
[IP6AT ... IP6AT+3] = &mac_writereg, [IP4AT ... IP4AT+6] = &mac_writereg,
[FFLT ... FFLT+6] = &mac_writereg,
[RA ... RA+31] = &mac_writereg,
[WUPM ... WUPM+31] = &mac_writereg,
[MTA ... MTA+127] = &mac_writereg,
[VFTA ... VFTA+127] = &mac_writereg,
[FFMT ... FFMT+254] = &mac_writereg, [FFVT ... FFVT+254] = &mac_writereg,
[PBM ... PBM+16383] = &mac_writereg,
};
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 };
#define markflag(x) ((E1000_FLAG_##x << 2) | MAC_ACCESS_FLAG_NEEDED)
/* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p]
* f - flag bits (up to 6 possible flags)
* n - flag needed
* p - partially implenented */
static const uint8_t mac_reg_access[0x8000] = {
[RDTR] = markflag(MIT), [TADV] = markflag(MIT),
[RADV] = markflag(MIT), [ITR] = markflag(MIT),
[IPAV] = markflag(MAC), [WUC] = markflag(MAC),
[IP6AT] = markflag(MAC), [IP4AT] = markflag(MAC),
[FFVT] = markflag(MAC), [WUPM] = markflag(MAC),
[ECOL] = markflag(MAC), [MCC] = markflag(MAC),
[DC] = markflag(MAC), [TNCRS] = markflag(MAC),
[RLEC] = markflag(MAC), [XONRXC] = markflag(MAC),
[XOFFTXC] = markflag(MAC), [RFC] = markflag(MAC),
[TSCTFC] = markflag(MAC), [MGTPRC] = markflag(MAC),
[WUS] = markflag(MAC), [AIT] = markflag(MAC),
[FFLT] = markflag(MAC), [FFMT] = markflag(MAC),
[SCC] = markflag(MAC), [FCRUC] = markflag(MAC),
[LATECOL] = markflag(MAC), [COLC] = markflag(MAC),
[SEQEC] = markflag(MAC), [CEXTERR] = markflag(MAC),
[XONTXC] = markflag(MAC), [XOFFRXC] = markflag(MAC),
[RJC] = markflag(MAC), [RNBC] = markflag(MAC),
[MGTPDC] = markflag(MAC), [MGTPTC] = markflag(MAC),
[RUC] = markflag(MAC), [ROC] = markflag(MAC),
[GORCL] = markflag(MAC), [GORCH] = markflag(MAC),
[GOTCL] = markflag(MAC), [GOTCH] = markflag(MAC),
[BPRC] = markflag(MAC), [MPRC] = markflag(MAC),
[TSCTC] = markflag(MAC), [PRC64] = markflag(MAC),
[PRC127] = markflag(MAC), [PRC255] = markflag(MAC),
[PRC511] = markflag(MAC), [PRC1023] = markflag(MAC),
[PRC1522] = markflag(MAC), [PTC64] = markflag(MAC),
[PTC127] = markflag(MAC), [PTC255] = markflag(MAC),
[PTC511] = markflag(MAC), [PTC1023] = markflag(MAC),
[PTC1522] = markflag(MAC), [MPTC] = markflag(MAC),
[BPTC] = markflag(MAC),
[TDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[TDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[TDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[TDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[TDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[RDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[RDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[RDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[RDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[RDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL,
[PBM] = markflag(MAC) | MAC_ACCESS_PARTIAL,
};
static void
e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
if (index < NWRITEOPS && macreg_writeops[index]) {
if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED)
|| (s->compat_flags & (mac_reg_access[index] >> 2))) {
if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "
"It is not fully implemented.\n", index<<2);
}
macreg_writeops[index](s, index, val);
} else { /* "flag needed" bit is set, but the flag is not active */
DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n",
index<<2);
}
} else if (index < NREADOPS && macreg_readops[index]) {
DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n",
index<<2, val);
} else {
DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
index<<2, val);
}
}
static uint64_t
e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
if (index < NREADOPS && macreg_readops[index]) {
if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED)
|| (s->compat_flags & (mac_reg_access[index] >> 2))) {
if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
"It is not fully implemented.\n", index<<2);
}
return macreg_readops[index](s, index);
} else { /* "flag needed" bit is set, but the flag is not active */
DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n",
index<<2);
}
} else {
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
}
return 0;
}
static const MemoryRegionOps e1000_mmio_ops = {
.read = e1000_mmio_read,
.write = e1000_mmio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static uint64_t e1000_io_read(void *opaque, hwaddr addr,
unsigned size)
{
E1000State *s = opaque;
(void)s;
return 0;
}
static void e1000_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
E1000State *s = opaque;
(void)s;
}
static const MemoryRegionOps e1000_io_ops = {
.read = e1000_io_read,
.write = e1000_io_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static bool is_version_1(void *opaque, int version_id)
{
return version_id == 1;
}
static int e1000_pre_save(void *opaque)
{
E1000State *s = opaque;
NetClientState *nc = qemu_get_queue(s->nic);
/* If the mitigation timer is active, emulate a timeout now. */
if (s->mit_timer_on) {
e1000_mit_timer(s);
}
/*
* If link is down and auto-negotiation is supported and ongoing,
* complete auto-negotiation immediately. This allows us to look
* at MII_SR_AUTONEG_COMPLETE to infer link status on load.
*/
if (nc->link_down && have_autoneg(s)) {
s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
}
/* Decide which set of props to migrate in the main structure */
if (chkflag(TSO) || !s->use_tso_for_migration) {
/* Either we're migrating with the extra subsection, in which
* case the mig_props is always 'props' OR
* we've not got the subsection, but 'props' was the last
* updated.
*/
s->mig_props = s->tx.props;
} else {
/* We're not using the subsection, and 'tso_props' was
* the last updated.
*/
s->mig_props = s->tx.tso_props;
}
return 0;
}
static int e1000_post_load(void *opaque, int version_id)
{
E1000State *s = opaque;
NetClientState *nc = qemu_get_queue(s->nic);
if (!chkflag(MIT)) {
s->mac_reg[ITR] = s->mac_reg[RDTR] = s->mac_reg[RADV] =
s->mac_reg[TADV] = 0;
s->mit_irq_level = false;
}
s->mit_ide = 0;
s->mit_timer_on = false;
/* nc.link_down can't be migrated, so infer link_down according
* to link status bit in mac_reg[STATUS].
* Alternatively, restart link negotiation if it was in progress. */
nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0;
if (have_autoneg(s) &&
!(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
nc->link_down = false;
timer_mod(s->autoneg_timer,
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
}
s->tx.props = s->mig_props;
if (!s->received_tx_tso) {
/* We received only one set of offload data (tx.props)
* and haven't got tx.tso_props. The best we can do
* is dupe the data.
*/
s->tx.tso_props = s->mig_props;
}
return 0;
}
static int e1000_tx_tso_post_load(void *opaque, int version_id)
{
E1000State *s = opaque;
s->received_tx_tso = true;
return 0;
}
static bool e1000_mit_state_needed(void *opaque)
{
E1000State *s = opaque;
return chkflag(MIT);
}
static bool e1000_full_mac_needed(void *opaque)
{
E1000State *s = opaque;
return chkflag(MAC);
}
static bool e1000_tso_state_needed(void *opaque)
{
E1000State *s = opaque;
return chkflag(TSO);
}
static const VMStateDescription vmstate_e1000_mit_state = {
.name = "e1000/mit_state",
.version_id = 1,
.minimum_version_id = 1,
.needed = e1000_mit_state_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32(mac_reg[RDTR], E1000State),
VMSTATE_UINT32(mac_reg[RADV], E1000State),
VMSTATE_UINT32(mac_reg[TADV], E1000State),
VMSTATE_UINT32(mac_reg[ITR], E1000State),
VMSTATE_BOOL(mit_irq_level, E1000State),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_e1000_full_mac_state = {
.name = "e1000/full_mac_state",
.version_id = 1,
.minimum_version_id = 1,
.needed = e1000_full_mac_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_e1000_tx_tso_state = {
.name = "e1000/tx_tso_state",
.version_id = 1,
.minimum_version_id = 1,
.needed = e1000_tso_state_needed,
.post_load = e1000_tx_tso_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT8(tx.tso_props.ipcss, E1000State),
VMSTATE_UINT8(tx.tso_props.ipcso, E1000State),
VMSTATE_UINT16(tx.tso_props.ipcse, E1000State),
VMSTATE_UINT8(tx.tso_props.tucss, E1000State),
VMSTATE_UINT8(tx.tso_props.tucso, E1000State),
VMSTATE_UINT16(tx.tso_props.tucse, E1000State),
VMSTATE_UINT32(tx.tso_props.paylen, E1000State),
VMSTATE_UINT8(tx.tso_props.hdr_len, E1000State),
VMSTATE_UINT16(tx.tso_props.mss, E1000State),
VMSTATE_INT8(tx.tso_props.ip, E1000State),
VMSTATE_INT8(tx.tso_props.tcp, E1000State),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_e1000 = {
.name = "e1000",
.version_id = 2,
.minimum_version_id = 1,
.pre_save = e1000_pre_save,
.post_load = e1000_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, E1000State),
VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
VMSTATE_UNUSED(4), /* Was mmio_base. */
VMSTATE_UINT32(rxbuf_size, E1000State),
VMSTATE_UINT32(rxbuf_min_shift, E1000State),
VMSTATE_UINT32(eecd_state.val_in, E1000State),
VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
VMSTATE_UINT16(eecd_state.reading, E1000State),
VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
VMSTATE_UINT8(mig_props.ipcss, E1000State),
VMSTATE_UINT8(mig_props.ipcso, E1000State),
VMSTATE_UINT16(mig_props.ipcse, E1000State),
VMSTATE_UINT8(mig_props.tucss, E1000State),
VMSTATE_UINT8(mig_props.tucso, E1000State),
VMSTATE_UINT16(mig_props.tucse, E1000State),
VMSTATE_UINT32(mig_props.paylen, E1000State),
VMSTATE_UINT8(mig_props.hdr_len, E1000State),
VMSTATE_UINT16(mig_props.mss, E1000State),
VMSTATE_UINT16(tx.size, E1000State),
VMSTATE_UINT16(tx.tso_frames, E1000State),
VMSTATE_UINT8(tx.sum_needed, E1000State),
VMSTATE_INT8(mig_props.ip, E1000State),
VMSTATE_INT8(mig_props.tcp, E1000State),
VMSTATE_BUFFER(tx.header, E1000State),
VMSTATE_BUFFER(tx.data, E1000State),
VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
VMSTATE_UINT32(mac_reg[CTRL], E1000State),
VMSTATE_UINT32(mac_reg[EECD], E1000State),
VMSTATE_UINT32(mac_reg[EERD], E1000State),
VMSTATE_UINT32(mac_reg[GPRC], E1000State),
VMSTATE_UINT32(mac_reg[GPTC], E1000State),
VMSTATE_UINT32(mac_reg[ICR], E1000State),
VMSTATE_UINT32(mac_reg[ICS], E1000State),
VMSTATE_UINT32(mac_reg[IMC], E1000State),
VMSTATE_UINT32(mac_reg[IMS], E1000State),
VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
VMSTATE_UINT32(mac_reg[MANC], E1000State),
VMSTATE_UINT32(mac_reg[MDIC], E1000State),
VMSTATE_UINT32(mac_reg[MPC], E1000State),
VMSTATE_UINT32(mac_reg[PBA], E1000State),
VMSTATE_UINT32(mac_reg[RCTL], E1000State),
VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
VMSTATE_UINT32(mac_reg[RDH], E1000State),
VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
VMSTATE_UINT32(mac_reg[RDT], E1000State),
VMSTATE_UINT32(mac_reg[STATUS], E1000State),
VMSTATE_UINT32(mac_reg[SWSM], E1000State),
VMSTATE_UINT32(mac_reg[TCTL], E1000State),
VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
VMSTATE_UINT32(mac_reg[TDH], E1000State),
VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
VMSTATE_UINT32(mac_reg[TDT], E1000State),
VMSTATE_UINT32(mac_reg[TORH], E1000State),
VMSTATE_UINT32(mac_reg[TORL], E1000State),
VMSTATE_UINT32(mac_reg[TOTH], E1000State),
VMSTATE_UINT32(mac_reg[TOTL], E1000State),
VMSTATE_UINT32(mac_reg[TPR], E1000State),
VMSTATE_UINT32(mac_reg[TPT], E1000State),
VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
VMSTATE_UINT32(mac_reg[WUFC], E1000State),
VMSTATE_UINT32(mac_reg[VET], E1000State),
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
&vmstate_e1000_mit_state,
&vmstate_e1000_full_mac_state,
&vmstate_e1000_tx_tso_state,
NULL
}
};
/*
* EEPROM contents documented in Tables 5-2 and 5-3, pp. 98-102.
* Note: A valid DevId will be inserted during pci_e1000_init().
*/
static const uint16_t e1000_eeprom_template[64] = {
0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040,
0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
};
/* PCI interface */
static void
e1000_mmio_setup(E1000State *d)
{
int i;
const uint32_t excluded_regs[] = {
E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
};
memory_region_init_io(&d->mmio, OBJECT(d), &e1000_mmio_ops, d,
"e1000-mmio", PNPMMIO_SIZE);
memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
excluded_regs[i+1] - excluded_regs[i] - 4);
memory_region_init_io(&d->io, OBJECT(d), &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
}
static void
pci_e1000_uninit(PCIDevice *dev)
{
E1000State *d = E1000(dev);
timer_del(d->autoneg_timer);
timer_free(d->autoneg_timer);
timer_del(d->mit_timer);
timer_free(d->mit_timer);
timer_del(d->flush_queue_timer);
timer_free(d->flush_queue_timer);
qemu_del_nic(d->nic);
}
static NetClientInfo net_e1000_info = {
.type = NET_CLIENT_DRIVER_NIC,
.size = sizeof(NICState),
.can_receive = e1000_can_receive,
.receive = e1000_receive,
.receive_iov = e1000_receive_iov,
.link_status_changed = e1000_set_link_status,
};
static void e1000_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len)
{
E1000State *s = E1000(pci_dev);
pci_default_write_config(pci_dev, address, val, len);
if (range_covers_byte(address, len, PCI_COMMAND) &&
(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
}
static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
E1000State *d = E1000(pci_dev);
uint8_t *pci_conf;
uint8_t *macaddr;
pci_dev->config_write = e1000_write_config;
pci_conf = pci_dev->config;
/* TODO: RST# value should be 0, PCI spec 6.2.4 */
pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
e1000_mmio_setup(d);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
qemu_macaddr_default_if_unset(&d->conf.macaddr);
macaddr = d->conf.macaddr.a;
e1000x_core_prepare_eeprom(d->eeprom_data,
e1000_eeprom_template,
sizeof(e1000_eeprom_template),
PCI_DEVICE_GET_CLASS(pci_dev)->device_id,
macaddr);
d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
object_get_typename(OBJECT(d)), dev->id, d);
qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr);
d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d);
d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d);
d->flush_queue_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
e1000_flush_queue_timer, d);
}
static void qdev_e1000_reset(DeviceState *dev)
{
E1000State *d = E1000(dev);
e1000_reset(d);
}
static Property e1000_properties[] = {
DEFINE_NIC_PROPERTIES(E1000State, conf),
DEFINE_PROP_BIT("autonegotiation", E1000State,
compat_flags, E1000_FLAG_AUTONEG_BIT, true),
DEFINE_PROP_BIT("mitigation", E1000State,
compat_flags, E1000_FLAG_MIT_BIT, true),
DEFINE_PROP_BIT("extra_mac_registers", E1000State,
compat_flags, E1000_FLAG_MAC_BIT, true),
DEFINE_PROP_BIT("migrate_tso_props", E1000State,
compat_flags, E1000_FLAG_TSO_BIT, true),
DEFINE_PROP_END_OF_LIST(),
};
typedef struct E1000Info {
const char *name;
uint16_t device_id;
uint8_t revision;
uint16_t phy_id2;
} E1000Info;
static void e1000_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
E1000BaseClass *e = E1000_DEVICE_CLASS(klass);
const E1000Info *info = data;
k->realize = pci_e1000_realize;
k->exit = pci_e1000_uninit;
k->romfile = "efi-e1000.rom";
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = info->device_id;
k->revision = info->revision;
e->phy_id2 = info->phy_id2;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->desc = "Intel Gigabit Ethernet";
dc->reset = qdev_e1000_reset;
dc->vmsd = &vmstate_e1000;
dc->props = e1000_properties;
}
static void e1000_instance_init(Object *obj)
{
E1000State *n = E1000(obj);
device_add_bootindex_property(obj, &n->conf.bootindex,
"bootindex", "/ethernet-phy@0",
DEVICE(n), NULL);
}
static const TypeInfo e1000_base_info = {
.name = TYPE_E1000_BASE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(E1000State),
.instance_init = e1000_instance_init,
.class_size = sizeof(E1000BaseClass),
.abstract = true,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
static const E1000Info e1000_devices[] = {
{
.name = "e1000",
.device_id = E1000_DEV_ID_82540EM,
.revision = 0x03,
.phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,
},
{
.name = "e1000-82544gc",
.device_id = E1000_DEV_ID_82544GC_COPPER,
.revision = 0x03,
.phy_id2 = E1000_PHY_ID2_82544x,
},
{
.name = "e1000-82545em",
.device_id = E1000_DEV_ID_82545EM_COPPER,
.revision = 0x03,
.phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,
},
};
static void e1000_register_types(void)
{
int i;
type_register_static(&e1000_base_info);
for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) {
const E1000Info *info = &e1000_devices[i];
TypeInfo type_info = {};
type_info.name = info->name;
type_info.parent = TYPE_E1000_BASE;
type_info.class_data = (void *)info;
type_info.class_init = e1000_class_init;
type_info.instance_init = e1000_instance_init;
type_register(&type_info);
}
}
type_init(e1000_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/roms/SLOF/lib/libhvcall/brokensc1.c | <filename>src/qemu/src-pmp/roms/SLOF/lib/libhvcall/brokensc1.c
#include <stdint.h>
#include <stddef.h>
#include <cpu.h>
#include "libhvcall.h"
#include "byteorder.h"
// #define DEBUG_PATCHERY
#define H_SET_DABR 0x28
#define INS_SC1 0x44000022
#define INS_SC1_REPLACE 0x7c000268
extern volatile uint32_t sc1ins;
static unsigned long hcall(uint32_t inst, unsigned long arg0, unsigned long arg1)
{
register unsigned long r3 asm("r3") = arg0;
register unsigned long r4 asm("r4") = arg1;
register unsigned long r5 asm("r5") = inst;
asm volatile("bl 1f \n"
"1: \n"
"li 11, 2f - 1b \n"
"mflr 12 \n"
"add 11, 11, 12 \n"
"stw 5, 0(11) \n"
"dcbst 0, 11 \n"
"sync \n"
"icbi 0, 11 \n"
"isync \n"
"2: \n"
".long 0 \n"
: "=r" (r3)
: "r" (r3), "r" (r4), "r" (r5)
: "ctr", "r0", "r6", "r7", "r8", "r9", "r10", "r11",
"r12", "r13", "r31", "lr", "cc");
return r3;
}
static int check_broken_sc1(void)
{
long r;
/*
* Check if we can do a simple hcall. If it works, we are running in
* a sane environment and everything's fine. If it doesn't, we need
* to patch the hypercall instruction to something that traps into
* supervisor mode.
*/
r = hcall(INS_SC1, H_SET_DABR, 0);
if (r == H_PRIVILEGE) {
/* We found a broken sc1 host! */
return 1;
}
/* All is fine */
return 0;
}
int patch_broken_sc1(void *start, void *end, uint32_t *test_ins)
{
uint32_t *p;
/* The sc 1 instruction */
uint32_t sc1 = INS_SC1;
/* An illegal instruction that KVM interprets as sc 1 */
uint32_t sc1_replacement = INS_SC1_REPLACE;
int is_le = (test_ins && *test_ins == 0x48000008);
#ifdef DEBUG_PATCHERY
int cnt = 0;
#endif
/* The host is sane, get out of here */
if (!check_broken_sc1())
return 0;
/* We only get here with a broken sc1 implementation */
/* Trim the range we scan to not cover the data section */
if (test_ins) {
/* This is the cpu table matcher for 970FX */
uint32_t end_bytes[] = { 0xffff0000, 0x3c0000 };
/*
* The .__start symbol contains a trap instruction followed
* by lots of zeros.
*/
uint32_t start_bytes[] = { 0x7fe00008, 0, 0, 0, 0 };
if (is_le) {
end_bytes[0] = bswap_32(end_bytes[0]);
end_bytes[1] = bswap_32(end_bytes[1]);
start_bytes[1] = bswap_32(start_bytes[1]);
}
/* Find the start of the text section */
for (p = test_ins; (long)p > (long)start; p--) {
if (p[0] == start_bytes[0] &&
p[1] == start_bytes[1] &&
p[2] == start_bytes[2] &&
p[3] == start_bytes[3] &&
p[4] == start_bytes[4]) {
/*
* We found a match of the instruction sequence
* trap
* .long 0
* .long 0
* .long 0
* .long 0
* which marks the beginning of the .text
* section on all Linux kernels I've checked.
*/
#ifdef DEBUG_PATCHERY
printf("Shortened start from %p to %p\n", end, p);
#endif
start = p;
break;
}
}
/* Find the end of the text section */
for (p = start; (long)p < (long)end; p++) {
if (p[0] == end_bytes[0] && p[1] == end_bytes[1]) {
/*
* We found a match of the PPC970FX entry in the
* guest kernel's CPU table. That table is
* usually found early in the .data section and
* thus marks the end of the .text section for
* us which we need to patch.
*/
#ifdef DEBUG_PATCHERY
printf("Shortened end from %p to %p\n", end, p);
#endif
end = p;
break;
}
}
}
if (is_le) {
/*
* The kernel was built for LE mode, so our sc1 and replacement
* opcodes are in the wrong byte order. Reverse them.
*/
sc1 = bswap_32(sc1);
sc1_replacement = bswap_32(sc1_replacement);
}
/* Patch all sc 1 instructions to reserved instruction 31/308 */
for (p = start; (long)p < (long)end; p++) {
if (*p == sc1) {
*p = sc1_replacement;
flush_cache(p, sizeof(*p));
#ifdef DEBUG_PATCHERY
cnt++;
#endif
}
}
#ifdef DEBUG_PATCHERY
printf("Patched %d instructions (%p - %p)\n", cnt, start, end);
#endif
return 1;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/ppc/spapr_irq.c | <filename>src/qemu/src-pmp/hw/ppc/spapr_irq.c
/*
* QEMU PowerPC sPAPR IRQ interface
*
* Copyright (c) 2018, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_xive.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "cpu-models.h"
#include "sysemu/kvm.h"
#include "trace.h"
void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis)
{
spapr->irq_map_nr = nr_msis;
spapr->irq_map = bitmap_new(spapr->irq_map_nr);
}
int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
Error **errp)
{
int irq;
/*
* The 'align_mask' parameter of bitmap_find_next_zero_area()
* should be one less than a power of 2; 0 means no
* alignment. Adapt the 'align' value of the former allocator
* to fit the requirements of bitmap_find_next_zero_area()
*/
align -= 1;
irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
align);
if (irq == spapr->irq_map_nr) {
error_setg(errp, "can't find a free %d-IRQ block", num);
return -1;
}
bitmap_set(spapr->irq_map, irq, num);
return irq + SPAPR_IRQ_MSI;
}
void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num)
{
bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
}
void spapr_irq_msi_reset(SpaprMachineState *spapr)
{
bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
}
/*
* XICS IRQ backend.
*/
static ICSState *spapr_ics_create(SpaprMachineState *spapr,
int nr_irqs, Error **errp)
{
Error *local_err = NULL;
Object *obj;
obj = object_new(TYPE_ICS_SIMPLE);
object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
&error_abort);
object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
if (local_err) {
goto error;
}
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
goto error;
}
return ICS_BASE(obj);
error:
error_propagate(errp, local_err);
return NULL;
}
static void spapr_irq_init_xics(SpaprMachineState *spapr, int nr_irqs,
Error **errp)
{
MachineState *machine = MACHINE(spapr);
Error *local_err = NULL;
bool xics_kvm = false;
if (kvm_enabled()) {
if (machine_kernel_irqchip_allowed(machine) &&
!xics_kvm_init(spapr, &local_err)) {
xics_kvm = true;
}
if (machine_kernel_irqchip_required(machine) && !xics_kvm) {
error_prepend(&local_err,
"kernel_irqchip requested but unavailable: ");
goto error;
}
error_free(local_err);
local_err = NULL;
}
if (!xics_kvm) {
xics_spapr_init(spapr);
}
spapr->ics = spapr_ics_create(spapr, nr_irqs, &local_err);
error:
error_propagate(errp, local_err);
}
#define ICS_IRQ_FREE(ics, srcno) \
(!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
static int spapr_irq_claim_xics(SpaprMachineState *spapr, int irq, bool lsi,
Error **errp)
{
ICSState *ics = spapr->ics;
assert(ics);
if (!ics_valid_irq(ics, irq)) {
error_setg(errp, "IRQ %d is invalid", irq);
return -1;
}
if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
error_setg(errp, "IRQ %d is not free", irq);
return -1;
}
ics_set_irq_type(ics, irq - ics->offset, lsi);
return 0;
}
static void spapr_irq_free_xics(SpaprMachineState *spapr, int irq, int num)
{
ICSState *ics = spapr->ics;
uint32_t srcno = irq - ics->offset;
int i;
if (ics_valid_irq(ics, irq)) {
trace_spapr_irq_free(0, irq, num);
for (i = srcno; i < srcno + num; ++i) {
if (ICS_IRQ_FREE(ics, i)) {
trace_spapr_irq_free_warn(0, i);
}
memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
}
}
}
static qemu_irq spapr_qirq_xics(SpaprMachineState *spapr, int irq)
{
ICSState *ics = spapr->ics;
uint32_t srcno = irq - ics->offset;
if (ics_valid_irq(ics, irq)) {
return spapr->qirqs[srcno];
}
return NULL;
}
static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *mon)
{
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
}
ics_pic_print_info(spapr->ics, mon);
}
static void spapr_irq_cpu_intc_create_xics(SpaprMachineState *spapr,
PowerPCCPU *cpu, Error **errp)
{
Error *local_err = NULL;
Object *obj;
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
obj = icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr),
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
spapr_cpu->icp = ICP(obj);
}
static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id)
{
if (!kvm_irqchip_in_kernel()) {
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
icp_resend(spapr_cpu_state(cpu)->icp);
}
}
return 0;
}
static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val)
{
SpaprMachineState *spapr = opaque;
ics_simple_set_irq(spapr->ics, srcno, val);
}
static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp)
{
/* TODO: create the KVM XICS device */
}
static const char *spapr_irq_get_nodename_xics(SpaprMachineState *spapr)
{
return XICS_NODENAME;
}
#define SPAPR_IRQ_XICS_NR_IRQS 0x1000
#define SPAPR_IRQ_XICS_NR_MSIS \
(XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
SpaprIrq spapr_irq_xics = {
.nr_irqs = SPAPR_IRQ_XICS_NR_IRQS,
.nr_msis = SPAPR_IRQ_XICS_NR_MSIS,
.ov5 = SPAPR_OV5_XIVE_LEGACY,
.init = spapr_irq_init_xics,
.claim = spapr_irq_claim_xics,
.free = spapr_irq_free_xics,
.qirq = spapr_qirq_xics,
.print_info = spapr_irq_print_info_xics,
.dt_populate = spapr_dt_xics,
.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
.post_load = spapr_irq_post_load_xics,
.reset = spapr_irq_reset_xics,
.set_irq = spapr_irq_set_irq_xics,
.get_nodename = spapr_irq_get_nodename_xics,
};
/*
* XIVE IRQ backend.
*/
static void spapr_irq_init_xive(SpaprMachineState *spapr, int nr_irqs,
Error **errp)
{
MachineState *machine = MACHINE(spapr);
uint32_t nr_servers = spapr_max_server_number(spapr);
DeviceState *dev;
int i;
/* KVM XIVE device not yet available */
if (kvm_enabled()) {
if (machine_kernel_irqchip_required(machine)) {
error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
return;
}
}
dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs);
/*
* 8 XIVE END structures per CPU. One for each available priority
*/
qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
qdev_init_nofail(dev);
spapr->xive = SPAPR_XIVE(dev);
/* Enable the CPU IPIs */
for (i = 0; i < nr_servers; ++i) {
spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
}
spapr_xive_hcall_init(spapr);
}
static int spapr_irq_claim_xive(SpaprMachineState *spapr, int irq, bool lsi,
Error **errp)
{
if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
error_setg(errp, "IRQ %d is invalid", irq);
return -1;
}
return 0;
}
static void spapr_irq_free_xive(SpaprMachineState *spapr, int irq, int num)
{
int i;
for (i = irq; i < irq + num; ++i) {
spapr_xive_irq_free(spapr->xive, i);
}
}
static qemu_irq spapr_qirq_xive(SpaprMachineState *spapr, int irq)
{
SpaprXive *xive = spapr->xive;
if (irq >= xive->nr_irqs) {
return NULL;
}
/* The sPAPR machine/device should have claimed the IRQ before */
assert(xive_eas_is_valid(&xive->eat[irq]));
return spapr->qirqs[irq];
}
static void spapr_irq_print_info_xive(SpaprMachineState *spapr,
Monitor *mon)
{
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
}
spapr_xive_pic_print_info(spapr->xive, mon);
}
static void spapr_irq_cpu_intc_create_xive(SpaprMachineState *spapr,
PowerPCCPU *cpu, Error **errp)
{
Error *local_err = NULL;
Object *obj;
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
spapr_cpu->tctx = XIVE_TCTX(obj);
/*
* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
* don't beneficiate from the reset of the XIVE IRQ backend
*/
spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
}
static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id)
{
return 0;
}
static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp)
{
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
/* (TCG) Set the OS CAM line of the thread interrupt context. */
spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
}
/* Activate the XIVE MMIOs */
spapr_xive_mmio_set_enabled(spapr->xive, true);
}
static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val)
{
SpaprMachineState *spapr = opaque;
xive_source_set_irq(&spapr->xive->source, srcno, val);
}
static const char *spapr_irq_get_nodename_xive(SpaprMachineState *spapr)
{
return spapr->xive->nodename;
}
/*
* XIVE uses the full IRQ number space. Set it to 8K to be compatible
* with XICS.
*/
#define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
#define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
SpaprIrq spapr_irq_xive = {
.nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS,
.nr_msis = SPAPR_IRQ_XIVE_NR_MSIS,
.ov5 = SPAPR_OV5_XIVE_EXPLOIT,
.init = spapr_irq_init_xive,
.claim = spapr_irq_claim_xive,
.free = spapr_irq_free_xive,
.qirq = spapr_qirq_xive,
.print_info = spapr_irq_print_info_xive,
.dt_populate = spapr_dt_xive,
.cpu_intc_create = spapr_irq_cpu_intc_create_xive,
.post_load = spapr_irq_post_load_xive,
.reset = spapr_irq_reset_xive,
.set_irq = spapr_irq_set_irq_xive,
.get_nodename = spapr_irq_get_nodename_xive,
};
/*
* Dual XIVE and XICS IRQ backend.
*
* Both interrupt mode, XIVE and XICS, objects are created but the
* machine starts in legacy interrupt mode (XICS). It can be changed
* by the CAS negotiation process and, in that case, the new mode is
* activated after an extra machine reset.
*/
/*
* Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
* default.
*/
static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr)
{
return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
&spapr_irq_xive : &spapr_irq_xics;
}
static void spapr_irq_init_dual(SpaprMachineState *spapr, int nr_irqs,
Error **errp)
{
MachineState *machine = MACHINE(spapr);
Error *local_err = NULL;
if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
error_setg(errp, "No KVM support for the 'dual' machine");
return;
}
spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
}
static int spapr_irq_claim_dual(SpaprMachineState *spapr, int irq, bool lsi,
Error **errp)
{
Error *local_err = NULL;
int ret;
ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return ret;
}
ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return ret;
}
return ret;
}
static void spapr_irq_free_dual(SpaprMachineState *spapr, int irq, int num)
{
spapr_irq_xics.free(spapr, irq, num);
spapr_irq_xive.free(spapr, irq, num);
}
static qemu_irq spapr_qirq_dual(SpaprMachineState *spapr, int irq)
{
return spapr_irq_current(spapr)->qirq(spapr, irq);
}
static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *mon)
{
spapr_irq_current(spapr)->print_info(spapr, mon);
}
static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr,
uint32_t nr_servers, void *fdt,
uint32_t phandle)
{
spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle);
}
static void spapr_irq_cpu_intc_create_dual(SpaprMachineState *spapr,
PowerPCCPU *cpu, Error **errp)
{
Error *local_err = NULL;
spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
spapr_irq_xics.cpu_intc_create(spapr, cpu, errp);
}
static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id)
{
/*
* Force a reset of the XIVE backend after migration. The machine
* defaults to XICS at startup.
*/
if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
spapr_irq_xive.reset(spapr, &error_fatal);
}
return spapr_irq_current(spapr)->post_load(spapr, version_id);
}
static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp)
{
/*
* Deactivate the XIVE MMIOs. The XIVE backend will reenable them
* if selected.
*/
spapr_xive_mmio_set_enabled(spapr->xive, false);
spapr_irq_current(spapr)->reset(spapr, errp);
}
static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val)
{
SpaprMachineState *spapr = opaque;
spapr_irq_current(spapr)->set_irq(spapr, srcno, val);
}
static const char *spapr_irq_get_nodename_dual(SpaprMachineState *spapr)
{
return spapr_irq_current(spapr)->get_nodename(spapr);
}
/*
* Define values in sync with the XIVE and XICS backend
*/
#define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
#define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
SpaprIrq spapr_irq_dual = {
.nr_irqs = SPAPR_IRQ_DUAL_NR_IRQS,
.nr_msis = SPAPR_IRQ_DUAL_NR_MSIS,
.ov5 = SPAPR_OV5_XIVE_BOTH,
.init = spapr_irq_init_dual,
.claim = spapr_irq_claim_dual,
.free = spapr_irq_free_dual,
.qirq = spapr_qirq_dual,
.print_info = spapr_irq_print_info_dual,
.dt_populate = spapr_irq_dt_populate_dual,
.cpu_intc_create = spapr_irq_cpu_intc_create_dual,
.post_load = spapr_irq_post_load_dual,
.reset = spapr_irq_reset_dual,
.set_irq = spapr_irq_set_irq_dual,
.get_nodename = spapr_irq_get_nodename_dual,
};
static void spapr_irq_check(SpaprMachineState *spapr, Error **errp)
{
MachineState *machine = MACHINE(spapr);
/*
* Sanity checks on non-P9 machines. On these, XIVE is not
* advertised, see spapr_dt_ov5_platform_support()
*/
if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
0, spapr->max_compat_pvr)) {
/*
* If the 'dual' interrupt mode is selected, force XICS as CAS
* negotiation is useless.
*/
if (spapr->irq == &spapr_irq_dual) {
spapr->irq = &spapr_irq_xics;
return;
}
/*
* Non-P9 machines using only XIVE is a bogus setup. We have two
* scenarios to take into account because of the compat mode:
*
* 1. POWER7/8 machines should fail to init later on when creating
* the XIVE interrupt presenters because a POWER9 exception
* model is required.
* 2. POWER9 machines using the POWER8 compat mode won't fail and
* will let the OS boot with a partial XIVE setup : DT
* properties but no hcalls.
*
* To cover both and not confuse the OS, add an early failure in
* QEMU.
*/
if (spapr->irq == &spapr_irq_xive) {
error_setg(errp, "XIVE-only machines require a POWER9 CPU");
return;
}
}
}
/*
* sPAPR IRQ frontend routines for devices
*/
void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
{
MachineState *machine = MACHINE(spapr);
Error *local_err = NULL;
if (machine_kernel_irqchip_split(machine)) {
error_setg(errp, "kernel_irqchip split mode not supported on pseries");
return;
}
if (!kvm_enabled() && machine_kernel_irqchip_required(machine)) {
error_setg(errp,
"kernel_irqchip requested but only available with KVM");
return;
}
spapr_irq_check(spapr, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
/* Initialize the MSI IRQ allocator. */
if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
}
spapr->irq->init(spapr, spapr->irq->nr_irqs, errp);
spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
spapr->irq->nr_irqs);
}
int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp)
{
return spapr->irq->claim(spapr, irq, lsi, errp);
}
void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
{
spapr->irq->free(spapr, irq, num);
}
qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
{
return spapr->irq->qirq(spapr, irq);
}
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
{
return spapr->irq->post_load(spapr, version_id);
}
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
{
if (spapr->irq->reset) {
spapr->irq->reset(spapr, errp);
}
}
int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp)
{
const char *nodename = spapr->irq->get_nodename(spapr);
int offset, phandle;
offset = fdt_subnode_offset(fdt, 0, nodename);
if (offset < 0) {
error_setg(errp, "Can't find node \"%s\": %s", nodename,
fdt_strerror(offset));
return -1;
}
phandle = fdt_get_phandle(fdt, offset);
if (!phandle) {
error_setg(errp, "Can't get phandle of node \"%s\"", nodename);
return -1;
}
return phandle;
}
/*
* XICS legacy routines - to deprecate one day
*/
static int ics_find_free_block(ICSState *ics, int num, int alignnum)
{
int first, i;
for (first = 0; first < ics->nr_irqs; first += alignnum) {
if (num > (ics->nr_irqs - first)) {
return -1;
}
for (i = first; i < first + num; ++i) {
if (!ICS_IRQ_FREE(ics, i)) {
break;
}
}
if (i == (first + num)) {
return first;
}
}
return -1;
}
int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
{
ICSState *ics = spapr->ics;
int first = -1;
assert(ics);
/*
* MSIMesage::data is used for storing VIRQ so
* it has to be aligned to num to support multiple
* MSI vectors. MSI-X is not affected by this.
* The hint is used for the first IRQ, the rest should
* be allocated continuously.
*/
if (align) {
assert((num == 1) || (num == 2) || (num == 4) ||
(num == 8) || (num == 16) || (num == 32));
first = ics_find_free_block(ics, num, num);
} else {
first = ics_find_free_block(ics, num, 1);
}
if (first < 0) {
error_setg(errp, "can't find a free %d-IRQ block", num);
return -1;
}
return first + ics->offset;
}
#define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
SpaprIrq spapr_irq_xics_legacy = {
.nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
.ov5 = SPAPR_OV5_XIVE_LEGACY,
.init = spapr_irq_init_xics,
.claim = spapr_irq_claim_xics,
.free = spapr_irq_free_xics,
.qirq = spapr_qirq_xics,
.print_info = spapr_irq_print_info_xics,
.dt_populate = spapr_dt_xics,
.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
.post_load = spapr_irq_post_load_xics,
.set_irq = spapr_irq_set_irq_xics,
.get_nodename = spapr_irq_get_nodename_xics,
};
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_w.c | <filename>src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_w.c<gh_stars>1-10
/*
* Test program for MSA instruction ILVL.W
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "ILVL.W";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, }, /* 0 */
{ 0xffffffff00000000ULL, 0xffffffff00000000ULL, },
{ 0xffffffffaaaaaaaaULL, 0xffffffffaaaaaaaaULL, },
{ 0xffffffff55555555ULL, 0xffffffff55555555ULL, },
{ 0xffffffffccccccccULL, 0xffffffffccccccccULL, },
{ 0xffffffff33333333ULL, 0xffffffff33333333ULL, },
{ 0xffffffffe38e38e3ULL, 0xffffffff38e38e38ULL, },
{ 0xffffffff1c71c71cULL, 0xffffffffc71c71c7ULL, },
{ 0x00000000ffffffffULL, 0x00000000ffffffffULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x00000000aaaaaaaaULL, 0x00000000aaaaaaaaULL, },
{ 0x0000000055555555ULL, 0x0000000055555555ULL, },
{ 0x00000000ccccccccULL, 0x00000000ccccccccULL, },
{ 0x0000000033333333ULL, 0x0000000033333333ULL, },
{ 0x00000000e38e38e3ULL, 0x0000000038e38e38ULL, },
{ 0x000000001c71c71cULL, 0x00000000c71c71c7ULL, },
{ 0xaaaaaaaaffffffffULL, 0xaaaaaaaaffffffffULL, }, /* 16 */
{ 0xaaaaaaaa00000000ULL, 0xaaaaaaaa00000000ULL, },
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0xaaaaaaaa55555555ULL, 0xaaaaaaaa55555555ULL, },
{ 0xaaaaaaaaccccccccULL, 0xaaaaaaaaccccccccULL, },
{ 0xaaaaaaaa33333333ULL, 0xaaaaaaaa33333333ULL, },
{ 0xaaaaaaaae38e38e3ULL, 0xaaaaaaaa38e38e38ULL, },
{ 0xaaaaaaaa1c71c71cULL, 0xaaaaaaaac71c71c7ULL, },
{ 0x55555555ffffffffULL, 0x55555555ffffffffULL, }, /* 24 */
{ 0x5555555500000000ULL, 0x5555555500000000ULL, },
{ 0x55555555aaaaaaaaULL, 0x55555555aaaaaaaaULL, },
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0x55555555ccccccccULL, 0x55555555ccccccccULL, },
{ 0x5555555533333333ULL, 0x5555555533333333ULL, },
{ 0x55555555e38e38e3ULL, 0x5555555538e38e38ULL, },
{ 0x555555551c71c71cULL, 0x55555555c71c71c7ULL, },
{ 0xccccccccffffffffULL, 0xccccccccffffffffULL, }, /* 32 */
{ 0xcccccccc00000000ULL, 0xcccccccc00000000ULL, },
{ 0xccccccccaaaaaaaaULL, 0xccccccccaaaaaaaaULL, },
{ 0xcccccccc55555555ULL, 0xcccccccc55555555ULL, },
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0xcccccccc33333333ULL, 0xcccccccc33333333ULL, },
{ 0xcccccccce38e38e3ULL, 0xcccccccc38e38e38ULL, },
{ 0xcccccccc1c71c71cULL, 0xccccccccc71c71c7ULL, },
{ 0x33333333ffffffffULL, 0x33333333ffffffffULL, }, /* 40 */
{ 0x3333333300000000ULL, 0x3333333300000000ULL, },
{ 0x33333333aaaaaaaaULL, 0x33333333aaaaaaaaULL, },
{ 0x3333333355555555ULL, 0x3333333355555555ULL, },
{ 0x33333333ccccccccULL, 0x33333333ccccccccULL, },
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0x33333333e38e38e3ULL, 0x3333333338e38e38ULL, },
{ 0x333333331c71c71cULL, 0x33333333c71c71c7ULL, },
{ 0xe38e38e3ffffffffULL, 0x38e38e38ffffffffULL, }, /* 48 */
{ 0xe38e38e300000000ULL, 0x38e38e3800000000ULL, },
{ 0xe38e38e3aaaaaaaaULL, 0x38e38e38aaaaaaaaULL, },
{ 0xe38e38e355555555ULL, 0x38e38e3855555555ULL, },
{ 0xe38e38e3ccccccccULL, 0x38e38e38ccccccccULL, },
{ 0xe38e38e333333333ULL, 0x38e38e3833333333ULL, },
{ 0xe38e38e3e38e38e3ULL, 0x38e38e3838e38e38ULL, },
{ 0xe38e38e31c71c71cULL, 0x38e38e38c71c71c7ULL, },
{ 0x1c71c71cffffffffULL, 0xc71c71c7ffffffffULL, }, /* 56 */
{ 0x1c71c71c00000000ULL, 0xc71c71c700000000ULL, },
{ 0x1c71c71caaaaaaaaULL, 0xc71c71c7aaaaaaaaULL, },
{ 0x1c71c71c55555555ULL, 0xc71c71c755555555ULL, },
{ 0x1c71c71cccccccccULL, 0xc71c71c7ccccccccULL, },
{ 0x1c71c71c33333333ULL, 0xc71c71c733333333ULL, },
{ 0x1c71c71ce38e38e3ULL, 0xc71c71c738e38e38ULL, },
{ 0x1c71c71c1c71c71cULL, 0xc71c71c7c71c71c7ULL, },
{ 0xfe7bb00cfe7bb00cULL, 0x4b670b5e4b670b5eULL, }, /* 64 */
{ 0xfe7bb00c153f52fcULL, 0x4b670b5e12f7bb1aULL, },
{ 0xfe7bb00cab2b2514ULL, 0x4b670b5e27d8c6ffULL, },
{ 0xfe7bb00ca942e2a0ULL, 0x4b670b5e8df188d8ULL, },
{ 0x153f52fcfe7bb00cULL, 0x12f7bb1a4b670b5eULL, },
{ 0x153f52fc153f52fcULL, 0x12f7bb1a12f7bb1aULL, },
{ 0x153f52fcab2b2514ULL, 0x12f7bb1a27d8c6ffULL, },
{ 0x153f52fca942e2a0ULL, 0x12f7bb1a8df188d8ULL, },
{ 0xab2b2514fe7bb00cULL, 0x27d8c6ff4b670b5eULL, }, /* 72 */
{ 0xab2b2514153f52fcULL, 0x27d8c6ff12f7bb1aULL, },
{ 0xab2b2514ab2b2514ULL, 0x27d8c6ff27d8c6ffULL, },
{ 0xab2b2514a942e2a0ULL, 0x27d8c6ff8df188d8ULL, },
{ 0xa942e2a0fe7bb00cULL, 0x8df188d84b670b5eULL, },
{ 0xa942e2a0153f52fcULL, 0x8df188d812f7bb1aULL, },
{ 0xa942e2a0ab2b2514ULL, 0x8df188d827d8c6ffULL, },
{ 0xa942e2a0a942e2a0ULL, 0x8df188d88df188d8ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_ILVL_W(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_ILVL_W(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/libqos/virtio-pci.h | /*
* libqos virtio PCI definitions
*
* Copyright (c) 2014 <NAME>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef LIBQOS_VIRTIO_PCI_H
#define LIBQOS_VIRTIO_PCI_H
#include "libqos/virtio.h"
#include "libqos/pci.h"
#include "libqos/qgraph.h"
typedef struct QVirtioPCIDevice {
QOSGraphObject obj;
QVirtioDevice vdev;
QPCIDevice *pdev;
QPCIBar bar;
uint16_t config_msix_entry;
uint64_t config_msix_addr;
uint32_t config_msix_data;
} QVirtioPCIDevice;
typedef struct QVirtQueuePCI {
QVirtQueue vq;
uint16_t msix_entry;
uint64_t msix_addr;
uint32_t msix_data;
} QVirtQueuePCI;
extern const QVirtioBus qvirtio_pci;
void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * addr);
QVirtioPCIDevice *virtio_pci_new(QPCIBus *bus, QPCIAddress * addr);
/* virtio-pci object functions available for subclasses that
* override the original start_hw and destroy
* function. All virtio-xxx-pci subclass that override must
* take care of calling these two functions in the respective
* places
*/
void qvirtio_pci_destructor(QOSGraphObject *obj);
void qvirtio_pci_start_hw(QOSGraphObject *obj);
void qvirtio_pci_device_enable(QVirtioPCIDevice *d);
void qvirtio_pci_device_disable(QVirtioPCIDevice *d);
void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
QGuestAllocator *alloc, uint16_t entry);
void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
QGuestAllocator *alloc, uint16_t entry);
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/migration/migration.h | <filename>src/qemu/src-pmp/migration/migration.h<gh_stars>1-10
/*
* QEMU live migration
*
* Copyright IBM, Corp. 2008
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
*/
#ifndef QEMU_MIGRATION_H
#define QEMU_MIGRATION_H
#include "qemu-common.h"
#include "qapi/qapi-types-migration.h"
#include "qemu/thread.h"
#include "exec/cpu-common.h"
#include "qemu/coroutine_int.h"
#include "hw/qdev.h"
#include "io/channel.h"
#include "net/announce.h"
struct PostcopyBlocktimeContext;
#define MIGRATION_RESUME_ACK_VALUE (1)
/* State for the incoming migration */
struct MigrationIncomingState {
QEMUFile *from_src_file;
/*
* Free at the start of the main state load, set as the main thread finishes
* loading state.
*/
QemuEvent main_thread_load_event;
/* For network announces */
AnnounceTimer announce_timer;
size_t largest_page_size;
bool have_fault_thread;
QemuThread fault_thread;
QemuSemaphore fault_thread_sem;
/* Set this when we want the fault thread to quit */
bool fault_thread_quit;
bool have_listen_thread;
QemuThread listen_thread;
QemuSemaphore listen_thread_sem;
/* For the kernel to send us notifications */
int userfault_fd;
/* To notify the fault_thread to wake, e.g., when need to quit */
int userfault_event_fd;
QEMUFile *to_src_file;
QemuMutex rp_mutex; /* We send replies from multiple threads */
/* RAMBlock of last request sent to source */
RAMBlock *last_rb;
void *postcopy_tmp_page;
void *postcopy_tmp_zero_page;
/* PostCopyFD's for external userfaultfds & handlers of shared memory */
GArray *postcopy_remote_fds;
QEMUBH *bh;
int state;
bool have_colo_incoming_thread;
QemuThread colo_incoming_thread;
/* The coroutine we should enter (back) after failover */
Coroutine *migration_incoming_co;
QemuSemaphore colo_incoming_sem;
/*
* PostcopyBlocktimeContext to keep information for postcopy
* live migration, to calculate vCPU block time
* */
struct PostcopyBlocktimeContext *blocktime_ctx;
/* notify PAUSED postcopy incoming migrations to try to continue */
bool postcopy_recover_triggered;
QemuSemaphore postcopy_pause_sem_dst;
QemuSemaphore postcopy_pause_sem_fault;
/* List of listening socket addresses */
SocketAddressList *socket_address_list;
};
MigrationIncomingState *migration_incoming_get_current(void);
void migration_incoming_state_destroy(void);
/*
* Functions to work with blocktime context
*/
void fill_destination_postcopy_migration_info(MigrationInfo *info);
#define TYPE_MIGRATION "migration"
#define MIGRATION_CLASS(klass) \
OBJECT_CLASS_CHECK(MigrationClass, (klass), TYPE_MIGRATION)
#define MIGRATION_OBJ(obj) \
OBJECT_CHECK(MigrationState, (obj), TYPE_MIGRATION)
#define MIGRATION_GET_CLASS(obj) \
OBJECT_GET_CLASS(MigrationClass, (obj), TYPE_MIGRATION)
typedef struct MigrationClass {
/*< private >*/
DeviceClass parent_class;
} MigrationClass;
struct MigrationState
{
/*< private >*/
DeviceState parent_obj;
/*< public >*/
size_t bytes_xfer;
size_t xfer_limit;
QemuThread thread;
QEMUBH *cleanup_bh;
QEMUFile *to_dst_file;
/*
* Protects to_dst_file pointer. We need to make sure we won't
* yield or hang during the critical section, since this lock will
* be used in OOB command handler.
*/
QemuMutex qemu_file_lock;
/*
* Used to allow urgent requests to override rate limiting.
*/
QemuSemaphore rate_limit_sem;
/* pages already send at the beginning of current iteration */
uint64_t iteration_initial_pages;
/* pages transferred per second */
double pages_per_second;
/* bytes already send at the beginning of current iteration */
uint64_t iteration_initial_bytes;
/* time at the start of current iteration */
int64_t iteration_start_time;
/*
* The final stage happens when the remaining data is smaller than
* this threshold; it's calculated from the requested downtime and
* measured bandwidth
*/
int64_t threshold_size;
/* params from 'migrate-set-parameters' */
MigrationParameters parameters;
int state;
/* State related to return path */
struct {
QEMUFile *from_dst_file;
QemuThread rp_thread;
bool error;
QemuSemaphore rp_sem;
} rp_state;
double mbps;
/* Timestamp when recent migration starts (ms) */
int64_t start_time;
/* Total time used by latest migration (ms) */
int64_t total_time;
/* Timestamp when VM is down (ms) to migrate the last stuff */
int64_t downtime_start;
int64_t downtime;
int64_t expected_downtime;
bool enabled_capabilities[MIGRATION_CAPABILITY__MAX];
int64_t setup_time;
/*
* Whether guest was running when we enter the completion stage.
* If migration is interrupted by any reason, we need to continue
* running the guest on source.
*/
bool vm_was_running;
/* Flag set once the migration has been asked to enter postcopy */
bool start_postcopy;
/* Flag set after postcopy has sent the device state */
bool postcopy_after_devices;
/* Flag set once the migration thread is running (and needs joining) */
bool migration_thread_running;
/* Flag set once the migration thread called bdrv_inactivate_all */
bool block_inactive;
/* Migration is paused due to pause-before-switchover */
QemuSemaphore pause_sem;
/* The semaphore is used to notify COLO thread that failover is finished */
QemuSemaphore colo_exit_sem;
/* The semaphore is used to notify COLO thread to do checkpoint */
QemuSemaphore colo_checkpoint_sem;
int64_t colo_checkpoint_time;
QEMUTimer *colo_delay_timer;
/* The first error that has occurred.
We used the mutex to be able to return the 1st error message */
Error *error;
/* mutex to protect errp */
QemuMutex error_mutex;
/* Do we have to clean up -b/-i from old migrate parameters */
/* This feature is deprecated and will be removed */
bool must_remove_block_options;
/*
* Global switch on whether we need to store the global state
* during migration.
*/
bool store_global_state;
/* Whether we send QEMU_VM_CONFIGURATION during migration */
bool send_configuration;
/* Whether we send section footer during migration */
bool send_section_footer;
/* Needed by postcopy-pause state */
QemuSemaphore postcopy_pause_sem;
QemuSemaphore postcopy_pause_rp_sem;
/*
* Whether we abort the migration if decompression errors are
* detected at the destination. It is left at false for qemu
* older than 3.0, since only newer qemu sends streams that
* do not trigger spurious decompression errors.
*/
bool decompress_error_check;
};
void migrate_set_state(int *state, int old_state, int new_state);
void migration_fd_process_incoming(QEMUFile *f);
void migration_ioc_process_incoming(QIOChannel *ioc, Error **errp);
void migration_incoming_process(void);
bool migration_has_all_channels(void);
uint64_t migrate_max_downtime(void);
void migrate_set_error(MigrationState *s, const Error *error);
void migrate_fd_error(MigrationState *s, const Error *error);
void migrate_fd_connect(MigrationState *s, Error *error_in);
bool migration_is_setup_or_active(int state);
void migrate_init(MigrationState *s);
bool migration_is_blocked(Error **errp);
/* True if outgoing migration has entered postcopy phase */
bool migration_in_postcopy(void);
MigrationState *migrate_get_current(void);
bool migrate_postcopy(void);
bool migrate_release_ram(void);
bool migrate_postcopy_ram(void);
bool migrate_zero_blocks(void);
bool migrate_dirty_bitmaps(void);
bool migrate_ignore_shared(void);
bool migrate_auto_converge(void);
bool migrate_use_multifd(void);
bool migrate_pause_before_switchover(void);
int migrate_multifd_channels(void);
int migrate_use_xbzrle(void);
int64_t migrate_xbzrle_cache_size(void);
bool migrate_colo_enabled(void);
bool migrate_use_block(void);
bool migrate_use_block_incremental(void);
int migrate_max_cpu_throttle(void);
bool migrate_use_return_path(void);
uint64_t ram_get_total_transferred_pages(void);
bool migrate_use_compression(void);
int migrate_compress_level(void);
int migrate_compress_threads(void);
int migrate_compress_wait_thread(void);
int migrate_decompress_threads(void);
bool migrate_use_events(void);
bool migrate_postcopy_blocktime(void);
/* Sending on the return path - generic and then for each message type */
void migrate_send_rp_shut(MigrationIncomingState *mis,
uint32_t value);
void migrate_send_rp_pong(MigrationIncomingState *mis,
uint32_t value);
int migrate_send_rp_req_pages(MigrationIncomingState *mis, const char* rbname,
ram_addr_t start, size_t len);
void migrate_send_rp_recv_bitmap(MigrationIncomingState *mis,
char *block_name);
void migrate_send_rp_resume_ack(MigrationIncomingState *mis, uint32_t value);
void dirty_bitmap_mig_before_vm_start(void);
void init_dirty_bitmap_incoming_migration(void);
void migrate_add_address(SocketAddress *address);
int foreach_not_ignored_block(RAMBlockIterFunc func, void *opaque);
#define qemu_ram_foreach_block \
#warning "Use foreach_not_ignored_block in migration code"
void migration_make_urgent_request(void);
void migration_consume_urgent_request(void);
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/slirp/src/misc.h | /* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 1995 <NAME>.
*/
#ifndef MISC_H
#define MISC_H
#include "libslirp.h"
struct gfwd_list {
SlirpWriteCb write_cb;
void *opaque;
struct in_addr ex_addr; /* Server address */
int ex_fport; /* Port to telnet to */
char *ex_exec; /* Command line of what to exec */
struct gfwd_list *ex_next;
};
#define EMU_NONE 0x0
/* TCP emulations */
#define EMU_CTL 0x1
#define EMU_FTP 0x2
#define EMU_KSH 0x3
#define EMU_IRC 0x4
#define EMU_REALAUDIO 0x5
#define EMU_RLOGIN 0x6
#define EMU_IDENT 0x7
#define EMU_NOCONNECT 0x10 /* Don't connect */
struct tos_t {
uint16_t lport;
uint16_t fport;
uint8_t tos;
uint8_t emu;
};
struct emu_t {
uint16_t lport;
uint16_t fport;
uint8_t tos;
uint8_t emu;
struct emu_t *next;
};
struct slirp_quehead {
struct slirp_quehead *qh_link;
struct slirp_quehead *qh_rlink;
};
void slirp_insque(void *, void *);
void slirp_remque(void *);
int fork_exec(struct socket *so, const char *ex);
struct gfwd_list *
add_guestfwd(struct gfwd_list **ex_ptr,
SlirpWriteCb write_cb, void *opaque,
struct in_addr addr, int port);
struct gfwd_list *
add_exec(struct gfwd_list **ex_ptr, const char *cmdline,
struct in_addr addr, int port);
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-divide/test_msa_div_s_b.c | <gh_stars>1-10
/*
* Test program for MSA instruction DIV_S.B
*
* Copyright (C) 2018 Wave Computing, Inc.
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs.h"
#include "../../../../include/test_utils.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "DIV_S.B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x0101010101010101ULL, 0x0101010101010101ULL, }, /* 0 */
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 8 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x5656565656565656ULL, 0x5656565656565656ULL, }, /* 16 */
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0200ff0200ff0200ULL, 0xff0200ff0200ff02ULL, },
{ 0xfd0001fd0001fd00ULL, 0x01fd0001fd0001fdULL, },
{ 0xababababababababULL, 0xababababababababULL, }, /* 24 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xfe0001fe0001fe00ULL, 0x01fe0001fe0001feULL, },
{ 0x0300ff0300ff0300ULL, 0xff0300ff0300ff03ULL, },
{ 0x3434343434343434ULL, 0x3434343434343434ULL, }, /* 32 */
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0100000100000100ULL, 0x0001000001000001ULL, },
{ 0xff0000ff0000ff00ULL, 0x00ff0000ff0000ffULL, },
{ 0xcdcdcdcdcdcdcdcdULL, 0xcdcdcdcdcdcdcdcdULL, }, /* 40 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xff0000ff0000ff00ULL, 0x00ff0000ff0000ffULL, },
{ 0x0100000100000100ULL, 0x0001000001000001ULL, },
{ 0x1d72c81d72c81d72ULL, 0xc81d72c81d72c81dULL, }, /* 48 */
{ 0x0101ff0101ff0101ULL, 0xff0101ff0101ff01ULL, },
{ 0x0001000001000001ULL, 0x0000010000010000ULL, },
{ 0x00ff0000ff0000ffULL, 0x0000ff0000ff0000ULL, },
{ 0x0002ff0002ff0002ULL, 0xff0002ff0002ff00ULL, },
{ 0x00fe0100fe0100feULL, 0x0100fe0100fe0100ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0xffff00ffff00ffffULL, 0x00ffff00ffff00ffULL, },
{ 0xe48f39e48f39e48fULL, 0x39e48f39e48f39e4ULL, }, /* 56 */
{ 0xffff01ffff01ffffULL, 0x01ffff01ffff01ffULL, },
{ 0x00ff0000ff0000ffULL, 0x0000ff0000ff0000ULL, },
{ 0x0001000001000001ULL, 0x0000010000010000ULL, },
{ 0x00fe0100fe0100feULL, 0x0100fe0100fe0100ULL, },
{ 0x0002ff0002ff0002ULL, 0xff0002ff0002ff00ULL, },
{ 0x0000ff0000ff0000ULL, 0xff0000ff0000ff00ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, }, /* 64 */
{ 0x18ff01000000ff08ULL, 0x04f50003000100fdULL, },
{ 0x0101000000fe0000ULL, 0x01fe00a20002fe00ULL, },
{ 0xff01ff000002fe00ULL, 0x00fa00fe00010200ULL, },
{ 0x000000ff01ff0000ULL, 0x0000fa00f600ff00ULL, },
{ 0x0101ff0101010101ULL, 0x0101010101010101ULL, },
{ 0x000000ffff020000ULL, 0x000001e600010200ULL, },
{ 0x0000000100fe0100ULL, 0x000000000000fe00ULL, },
{ 0x00000301ff00fffeULL, 0x0000fb002a000001ULL, }, /* 72 */
{ 0x10ff0100000002f0ULL, 0x02040000fc0000fbULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0001fdff00ff03ffULL, 0x000200000000ff00ULL, },
{ 0x000000ff02000001ULL, 0xff00f6002b0000f8ULL, },
{ 0xeaffff0001000009ULL, 0xfa0101fffc010018ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_DIV_S_B(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_DIV_S_B(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/target/s390x/vec.h | <reponame>pmp-tool/PMP<filename>src/qemu/src-pmp/target/s390x/vec.h<gh_stars>1-10
/*
* QEMU TCG support -- s390x vector utilitites
*
* Copyright (C) 2019 Red Hat Inc
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef S390X_VEC_H
#define S390X_VEC_H
typedef union S390Vector {
uint64_t doubleword[2];
uint32_t word[4];
uint16_t halfword[8];
uint8_t byte[16];
} S390Vector;
/*
* Each vector is stored as two 64bit host values. So when talking about
* byte/halfword/word numbers, we have to take care of proper translation
* between element numbers.
*
* Big Endian (target/possible host)
* B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15]
* HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7]
* W: [ 0][ 1] - [ 2][ 3]
* DW: [ 0] - [ 1]
*
* Little Endian (possible host)
* B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8]
* HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4]
* W: [ 1][ 0] - [ 3][ 2]
* DW: [ 0] - [ 1]
*/
#ifndef HOST_WORDS_BIGENDIAN
#define H1(x) ((x) ^ 7)
#define H2(x) ((x) ^ 3)
#define H4(x) ((x) ^ 1)
#else
#define H1(x) (x)
#define H2(x) (x)
#define H4(x) (x)
#endif
static inline uint8_t s390_vec_read_element8(const S390Vector *v, uint8_t enr)
{
g_assert(enr < 16);
return v->byte[H1(enr)];
}
static inline uint16_t s390_vec_read_element16(const S390Vector *v, uint8_t enr)
{
g_assert(enr < 8);
return v->halfword[H2(enr)];
}
static inline uint32_t s390_vec_read_element32(const S390Vector *v, uint8_t enr)
{
g_assert(enr < 4);
return v->word[H4(enr)];
}
static inline uint64_t s390_vec_read_element64(const S390Vector *v, uint8_t enr)
{
g_assert(enr < 2);
return v->doubleword[enr];
}
static inline void s390_vec_write_element8(S390Vector *v, uint8_t enr,
uint8_t data)
{
g_assert(enr < 16);
v->byte[H1(enr)] = data;
}
static inline void s390_vec_write_element16(S390Vector *v, uint8_t enr,
uint16_t data)
{
g_assert(enr < 8);
v->halfword[H2(enr)] = data;
}
static inline void s390_vec_write_element32(S390Vector *v, uint8_t enr,
uint32_t data)
{
g_assert(enr < 4);
v->word[H4(enr)] = data;
}
static inline void s390_vec_write_element64(S390Vector *v, uint8_t enr,
uint64_t data)
{
g_assert(enr < 2);
v->doubleword[enr] = data;
}
#endif /* S390X_VEC_H */
|
pmp-tool/PMP | src/qemu/src-pmp/hw/pci/pcie.c | /*
* pcie.c
*
* Copyright (c) 2010 <NAME> <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pcie.h"
#include "hw/pci/msix.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pcie_regs.h"
#include "hw/pci/pcie_port.h"
#include "qemu/range.h"
//#define DEBUG_PCIE
#ifdef DEBUG_PCIE
# define PCIE_DPRINTF(fmt, ...) \
fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
#else
# define PCIE_DPRINTF(fmt, ...) do {} while (0)
#endif
#define PCIE_DEV_PRINTF(dev, fmt, ...) \
PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
/***************************************************************************
* pci express capability helper functions
*/
static void
pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
{
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
/* capability register
interrupt message number defaults to 0 */
pci_set_word(exp_cap + PCI_EXP_FLAGS,
((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
version);
/* device capability register
* table 7-12:
* roll based error reporting bit must be set by all
* Functions conforming to the ECN, PCI Express Base
* Specification, Revision 1.1., or subsequent PCI Express Base
* Specification revisions.
*/
pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
pci_set_long(exp_cap + PCI_EXP_LNKCAP,
(port << PCI_EXP_LNKCAP_PN_SHIFT) |
PCI_EXP_LNKCAP_ASPMS_0S |
QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) |
QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT));
pci_set_word(exp_cap + PCI_EXP_LNKSTA,
QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) |
QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT));
if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_DLLLA);
}
/* We changed link status bits over time, and changing them across
* migrations is generally fine as hardware changes them too.
* Let's not bother checking.
*/
pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
}
static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
{
PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT);
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
/* Skip anything that isn't a PCIESlot */
if (!s) {
return;
}
/* Clear and fill LNKCAP from what was configured above */
pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP,
PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
QEMU_PCI_EXP_LNKCAP_MLW(s->width) |
QEMU_PCI_EXP_LNKCAP_MLS(s->speed));
/*
* Link bandwidth notification is required for all root ports and
* downstream ports supporting links wider than x1 or multiple link
* speeds.
*/
if (s->width > QEMU_PCI_EXP_LNK_X1 ||
s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
PCI_EXP_LNKCAP_LBNC);
}
if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
/*
* Hot-plug capable downstream ports and downstream ports supporting
* link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC
* to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which
* we also hardwire to 1b here. 2.5GT/s hot-plug slots should also
* technically implement this, but it's not done here for compatibility.
*/
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
PCI_EXP_LNKCAP_DLLLARC);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_DLLLA);
/*
* Target Link Speed defaults to the highest link speed supported by
* the component. 2.5GT/s devices are permitted to hardwire to zero.
*/
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2,
PCI_EXP_LNKCTL2_TLS);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2,
QEMU_PCI_EXP_LNKCAP_MLS(s->speed) &
PCI_EXP_LNKCTL2_TLS);
}
/*
* 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is
* actually a reference to the highest bit supported in this register.
* We assume the device supports all link speeds.
*/
if (s->speed > QEMU_PCI_EXP_LNK_5GT) {
pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U);
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
PCI_EXP_LNKCAP2_SLS_2_5GB |
PCI_EXP_LNKCAP2_SLS_5_0GB |
PCI_EXP_LNKCAP2_SLS_8_0GB);
if (s->speed > QEMU_PCI_EXP_LNK_8GT) {
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
PCI_EXP_LNKCAP2_SLS_16_0GB);
}
}
}
int pcie_cap_init(PCIDevice *dev, uint8_t offset,
uint8_t type, uint8_t port,
Error **errp)
{
/* PCIe cap v2 init */
int pos;
uint8_t *exp_cap;
assert(pci_is_express(dev));
pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
PCI_EXP_VER2_SIZEOF, errp);
if (pos < 0) {
return pos;
}
dev->exp.exp_cap = pos;
exp_cap = dev->config + pos;
/* Filling values common with v1 */
pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
/* Fill link speed and width options */
pcie_cap_fill_slot_lnk(dev);
/* Filling v2 specific values */
pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
/* read-only to behave like a 'NULL' Extended Capability Header */
pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
}
return pos;
}
int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
uint8_t port)
{
/* PCIe cap v1 init */
int pos;
Error *local_err = NULL;
assert(pci_is_express(dev));
pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
PCI_EXP_VER1_SIZEOF, &local_err);
if (pos < 0) {
error_report_err(local_err);
return pos;
}
dev->exp.exp_cap = pos;
pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
return pos;
}
static int
pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
{
uint8_t type = PCI_EXP_TYPE_ENDPOINT;
Error *local_err = NULL;
int ret;
/*
* Windows guests will report Code 10, device cannot start, if
* a regular Endpoint type is exposed on a root complex. These
* should instead be Root Complex Integrated Endpoints.
*/
if (pci_bus_is_express(pci_get_bus(dev))
&& pci_bus_is_root(pci_get_bus(dev))) {
type = PCI_EXP_TYPE_RC_END;
}
if (cap_size == PCI_EXP_VER1_SIZEOF) {
return pcie_cap_v1_init(dev, offset, type, 0);
} else {
ret = pcie_cap_init(dev, offset, type, 0, &local_err);
if (ret < 0) {
error_report_err(local_err);
}
return ret;
}
}
int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
{
return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
}
int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
{
return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
}
void pcie_cap_exit(PCIDevice *dev)
{
pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
}
void pcie_cap_v1_exit(PCIDevice *dev)
{
pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
}
uint8_t pcie_cap_get_type(const PCIDevice *dev)
{
uint32_t pos = dev->exp.exp_cap;
assert(pos > 0);
return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
}
/* MSI/MSI-X */
/* pci express interrupt message number */
/* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
{
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
assert(vector < 32);
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
vector << PCI_EXP_FLAGS_IRQ_SHIFT);
}
uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
{
return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
}
void pcie_cap_deverr_init(PCIDevice *dev)
{
uint32_t pos = dev->exp.exp_cap;
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
PCI_EXP_DEVCAP_RBER);
pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
}
void pcie_cap_deverr_reset(PCIDevice *dev)
{
uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
pci_long_test_and_clear_mask(devctl,
PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
}
void pcie_cap_lnkctl_init(PCIDevice *dev)
{
uint32_t pos = dev->exp.exp_cap;
pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
}
void pcie_cap_lnkctl_reset(PCIDevice *dev)
{
uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
pci_long_test_and_clear_mask(lnkctl,
PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
}
static void hotplug_event_update_event_status(PCIDevice *dev)
{
uint32_t pos = dev->exp.exp_cap;
uint8_t *exp_cap = dev->config + pos;
uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
(sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
}
static void hotplug_event_notify(PCIDevice *dev)
{
bool prev = dev->exp.hpev_notified;
hotplug_event_update_event_status(dev);
if (prev == dev->exp.hpev_notified) {
return;
}
/* Note: the logic above does not take into account whether interrupts
* are masked. The result is that interrupt will be sent when it is
* subsequently unmasked. This appears to be legal: Section 6.7.3.4:
* The Port may optionally send an MSI when there are hot-plug events that
* occur while interrupt generation is disabled, and interrupt generation is
* subsequently enabled. */
if (msix_enabled(dev)) {
msix_notify(dev, pcie_cap_flags_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_cap_flags_get_vector(dev));
} else {
pci_set_irq(dev, dev->exp.hpev_notified);
}
}
static void hotplug_event_clear(PCIDevice *dev)
{
hotplug_event_update_event_status(dev);
if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
pci_irq_deassert(dev);
}
}
/*
* A PCI Express Hot-Plug Event has occurred, so update slot status register
* and notify OS of the event if necessary.
*
* 6.7.3 PCI Express Hot-Plug Events
* 6.7.3.4 Software Notification of Hot-Plug Events
*/
static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
{
/* Minor optimization: if nothing changed - no event is needed. */
if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
PCI_EXP_SLTSTA, event)) {
return;
}
hotplug_event_notify(dev);
}
static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev,
Error **errp)
{
uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
if (sltsta & PCI_EXP_SLTSTA_EIS) {
/* the slot is electromechanically locked.
* This error is propagated up to qdev and then to HMP/QMP.
*/
error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
}
}
void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp);
}
void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
PCIDevice *pci_dev = PCI_DEVICE(dev);
/* Don't send event when device is enabled during qemu machine creation:
* it is present on boot, no hotplug event is necessary. We do send an
* event when the device is disabled later. */
if (!dev->hotplugged) {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_PDS);
if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_DLLLA);
}
return;
}
/* To enable multifunction hot-plug, we just ensure the function
* 0 added last. When function 0 is added, we set the sltsta and
* inform OS via event notification.
*/
if (pci_get_function_0(pci_dev)) {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_PDS);
if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_DLLLA);
}
pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
}
}
void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
object_property_set_bool(OBJECT(dev), false, "realized", NULL);
}
static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
{
HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev));
hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort);
object_unparent(OBJECT(dev));
}
void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
Error *local_err = NULL;
PCIDevice *pci_dev = PCI_DEVICE(dev);
PCIBus *bus = pci_get_bus(pci_dev);
pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
/* In case user cancel the operation of multi-function hot-add,
* remove the function that is unexposed to guest individually,
* without interaction with guest.
*/
if (pci_dev->devfn &&
!bus->devices[0]) {
pcie_unplug_device(bus, pci_dev, NULL);
return;
}
pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
}
/* pci express slot for pci express root/downstream port
PCI express capability slot registers */
void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
{
uint32_t pos = dev->exp.exp_cap;
pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
PCI_EXP_FLAGS_SLOT);
pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
~PCI_EXP_SLTCAP_PSN);
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
(slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
PCI_EXP_SLTCAP_EIP |
PCI_EXP_SLTCAP_HPS |
PCI_EXP_SLTCAP_HPC |
PCI_EXP_SLTCAP_PIP |
PCI_EXP_SLTCAP_AIP |
PCI_EXP_SLTCAP_ABP);
if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
PCI_EXP_SLTCAP_PCP);
pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PCC);
pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PCC);
}
pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PIC |
PCI_EXP_SLTCTL_AIC);
pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PIC_OFF |
PCI_EXP_SLTCTL_AIC_OFF);
pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PIC |
PCI_EXP_SLTCTL_AIC |
PCI_EXP_SLTCTL_HPIE |
PCI_EXP_SLTCTL_CCIE |
PCI_EXP_SLTCTL_PDCE |
PCI_EXP_SLTCTL_ABPE);
/* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
* make the bit writable here in order to detect 1b is written.
* pcie_cap_slot_write_config() test-and-clear the bit, so
* this bit always returns 0 to the guest.
*/
pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_EIC);
pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
PCI_EXP_HP_EV_SUPPORTED);
dev->exp.hpev_notified = false;
qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
OBJECT(dev), NULL);
}
void pcie_cap_slot_reset(PCIDevice *dev)
{
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
uint8_t port_type = pcie_cap_get_type(dev);
assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
port_type == PCI_EXP_TYPE_ROOT_PORT);
PCIE_DEV_PRINTF(dev, "reset\n");
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_EIC |
PCI_EXP_SLTCTL_PIC |
PCI_EXP_SLTCTL_AIC |
PCI_EXP_SLTCTL_HPIE |
PCI_EXP_SLTCTL_CCIE |
PCI_EXP_SLTCTL_PDCE |
PCI_EXP_SLTCTL_ABPE);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_AIC_OFF);
if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
/* Downstream ports enforce device number 0. */
bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
uint16_t pic;
if (populated) {
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PCC);
} else {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PCC);
}
pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
}
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_EIS |/* on reset,
the lock is released */
PCI_EXP_SLTSTA_CC |
PCI_EXP_SLTSTA_PDC |
PCI_EXP_SLTSTA_ABP);
hotplug_event_update_event_status(dev);
}
void pcie_cap_slot_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len)
{
uint32_t pos = dev->exp.exp_cap;
uint8_t *exp_cap = dev->config + pos;
uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
hotplug_event_clear(dev);
}
if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
return;
}
if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_EIC)) {
sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
"sltsta -> 0x%02"PRIx16"\n",
sltsta);
}
/*
* If the slot is polulated, power indicator is off and power
* controller is off, it is safe to detach the devices.
*/
if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) {
PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
pcie_unplug_device, NULL);
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_PDS);
if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_DLLLA);
}
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_PDC);
}
hotplug_event_notify(dev);
/*
* 6.7.3.2 Command Completed Events
*
* Software issues a command to a hot-plug capable Downstream Port by
* issuing a write transaction that targets any portion of the Port’s Slot
* Control register. A single write to the Slot Control register is
* considered to be a single command, even if the write affects more than
* one field in the Slot Control register. In response to this transaction,
* the Port must carry out the requested actions and then set the
* associated status field for the command completed event. */
/* Real hardware might take a while to complete requested command because
* physical movement would be involved like locking the electromechanical
* lock. However in our case, command is completed instantaneously above,
* so send a command completion event right now.
*/
pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
}
int pcie_cap_slot_post_load(void *opaque, int version_id)
{
PCIDevice *dev = opaque;
hotplug_event_update_event_status(dev);
return 0;
}
void pcie_cap_slot_push_attention_button(PCIDevice *dev)
{
pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
}
/* root control/capabilities/status. PME isn't emulated for now */
void pcie_cap_root_init(PCIDevice *dev)
{
pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
PCI_EXP_RTCTL_SEFEE);
}
void pcie_cap_root_reset(PCIDevice *dev)
{
pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
}
/* function level reset(FLR) */
void pcie_cap_flr_init(PCIDevice *dev)
{
pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
PCI_EXP_DEVCAP_FLR);
/* Although reading BCR_FLR returns always 0,
* the bit is made writable here in order to detect the 1b is written
* pcie_cap_flr_write_config() test-and-clear the bit, so
* this bit always returns 0 to the guest.
*/
pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_BCR_FLR);
}
void pcie_cap_flr_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len)
{
uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
/* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
so the handler can detect FLR by looking at this bit. */
pci_device_reset(dev);
pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
}
}
/* Alternative Routing-ID Interpretation (ARI)
* forwarding support for root and downstream ports
*/
void pcie_cap_arifwd_init(PCIDevice *dev)
{
uint32_t pos = dev->exp.exp_cap;
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
PCI_EXP_DEVCAP2_ARI);
pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
PCI_EXP_DEVCTL2_ARI);
}
void pcie_cap_arifwd_reset(PCIDevice *dev)
{
uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
}
bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
{
if (!pci_is_express(dev)) {
return false;
}
if (!dev->exp.exp_cap) {
return false;
}
return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
PCI_EXP_DEVCTL2_ARI;
}
/**************************************************************************
* pci express extended capability list management functions
* uint16_t ext_cap_id (16 bit)
* uint8_t cap_ver (4 bit)
* uint16_t cap_offset (12 bit)
* uint16_t ext_cap_size
*/
/* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id,
uint16_t *prev_p)
{
uint16_t prev = 0;
uint16_t next;
uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
if (!header) {
/* no extended capability */
next = 0;
goto out;
}
for (next = PCI_CONFIG_SPACE_SIZE; next;
prev = next, next = PCI_EXT_CAP_NEXT(header)) {
assert(next >= PCI_CONFIG_SPACE_SIZE);
assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
header = pci_get_long(dev->config + next);
if (PCI_EXT_CAP_ID(header) == cap_id) {
break;
}
}
out:
if (prev_p) {
*prev_p = prev;
}
return next;
}
uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
{
return pcie_find_capability_list(dev, cap_id, NULL);
}
static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
{
uint32_t header = pci_get_long(dev->config + pos);
assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
pci_set_long(dev->config + pos, header);
}
/*
* Caller must supply valid (offset, size) such that the range wouldn't
* overlap with other capability or other registers.
* This function doesn't check it.
*/
void pcie_add_capability(PCIDevice *dev,
uint16_t cap_id, uint8_t cap_ver,
uint16_t offset, uint16_t size)
{
assert(offset >= PCI_CONFIG_SPACE_SIZE);
assert(offset < offset + size);
assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
assert(size >= 8);
assert(pci_is_express(dev));
if (offset != PCI_CONFIG_SPACE_SIZE) {
uint16_t prev;
/*
* 0xffffffff is not a valid cap id (it's a 16 bit field). use
* internally to find the last capability in the linked list.
*/
pcie_find_capability_list(dev, 0xffffffff, &prev);
assert(prev >= PCI_CONFIG_SPACE_SIZE);
pcie_ext_cap_set_next(dev, prev, offset);
}
pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0));
/* Make capability read-only by default */
memset(dev->wmask + offset, 0, size);
memset(dev->w1cmask + offset, 0, size);
/* Check capability by default */
memset(dev->cmask + offset, 0xFF, size);
}
/*
* Sync the PCIe Link Status negotiated speed and width of a bridge with the
* downstream device. If downstream device is not present, re-write with the
* Link Capability fields. If downstream device reports invalid width or
* speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such
* values interfere with PCIe native hotplug detecting new devices). Limit
* width and speed to bridge capabilities for compatibility. Use config_read
* to access the downstream device since it could be an assigned device with
* volatile link information.
*/
void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
{
PCIBridge *br = PCI_BRIDGE(bridge_dev);
PCIBus *bus = pci_bridge_get_sec_bus(br);
PCIDevice *target = bus->devices[0];
uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap;
uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP);
if (!target || !target->exp.exp_cap) {
lnksta = lnkcap;
} else {
lnksta = target->config_read(target,
target->exp.exp_cap + PCI_EXP_LNKSTA,
sizeof(lnksta));
if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) {
lnksta &= ~PCI_EXP_LNKSTA_NLW;
lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW;
} else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
}
if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) {
lnksta &= ~PCI_EXP_LNKSTA_CLS;
lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS;
} else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
}
}
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta &
(PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW));
}
/**************************************************************************
* pci express extended capability helper functions
*/
/* ARI */
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
{
pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
offset, PCI_ARI_SIZEOF);
pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
}
void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
{
static const int pci_dsn_ver = 1;
static const int pci_dsn_cap = 4;
pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
PCI_EXT_CAP_DSN_SIZEOF);
pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
}
void pcie_ats_init(PCIDevice *dev, uint16_t offset)
{
pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
offset, PCI_EXT_CAP_ATS_SIZEOF);
dev->exp.ats_cap = offset;
/* Invalidate Queue Depth 0, Page Aligned Request 0 */
pci_set_word(dev->config + offset + PCI_ATS_CAP, 0);
/* STU 0, Disabled by default */
pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f);
}
/* ACS (Access Control Services) */
void pcie_acs_init(PCIDevice *dev, uint16_t offset)
{
bool is_downstream = pci_is_express_downstream_port(dev);
uint16_t cap_bits = 0;
/* For endpoints, only multifunction devs may have an ACS capability: */
assert(is_downstream ||
(dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) ||
PCI_FUNC(dev->devfn));
pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset,
PCI_ACS_SIZEOF);
dev->exp.acs_cap = offset;
if (is_downstream) {
/*
* Downstream ports must implement SV, TB, RR, CR, UF, and DT (with
* caveats on the latter four that we ignore for simplicity).
* Endpoints may also implement a subset of ACS capabilities,
* but these are optional if the endpoint does not support
* peer-to-peer between functions and thus omitted here.
*/
cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT;
}
pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits);
pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits);
}
void pcie_acs_reset(PCIDevice *dev)
{
if (dev->exp.acs_cap) {
pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/qga/commands-win32.c | <reponame>pmp-tool/PMP
/*
* QEMU Guest Agent win32-specific command implementations
*
* Copyright IBM Corp. 2012
*
* Authors:
* <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include <wtypes.h>
#include <powrprof.h>
#include <winsock2.h>
#include <ws2tcpip.h>
#include <iptypes.h>
#include <iphlpapi.h>
#ifdef CONFIG_QGA_NTDDSCSI
#include <winioctl.h>
#include <ntddscsi.h>
#include <setupapi.h>
#include <cfgmgr32.h>
#include <initguid.h>
#endif
#include <lm.h>
#include <wtsapi32.h>
#include <wininet.h>
#include "guest-agent-core.h"
#include "vss-win32.h"
#include "qga-qapi-commands.h"
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "qemu/queue.h"
#include "qemu/host-utils.h"
#include "qemu/base64.h"
#ifndef SHTDN_REASON_FLAG_PLANNED
#define SHTDN_REASON_FLAG_PLANNED 0x80000000
#endif
/* multiple of 100 nanoseconds elapsed between windows baseline
* (1/1/1601) and Unix Epoch (1/1/1970), accounting for leap years */
#define W32_FT_OFFSET (10000000ULL * 60 * 60 * 24 * \
(365 * (1970 - 1601) + \
(1970 - 1601) / 4 - 3))
#define INVALID_SET_FILE_POINTER ((DWORD)-1)
typedef struct GuestFileHandle {
int64_t id;
HANDLE fh;
QTAILQ_ENTRY(GuestFileHandle) next;
} GuestFileHandle;
static struct {
QTAILQ_HEAD(, GuestFileHandle) filehandles;
} guest_file_state = {
.filehandles = QTAILQ_HEAD_INITIALIZER(guest_file_state.filehandles),
};
#define FILE_GENERIC_APPEND (FILE_GENERIC_WRITE & ~FILE_WRITE_DATA)
typedef struct OpenFlags {
const char *forms;
DWORD desired_access;
DWORD creation_disposition;
} OpenFlags;
static OpenFlags guest_file_open_modes[] = {
{"r", GENERIC_READ, OPEN_EXISTING},
{"rb", GENERIC_READ, OPEN_EXISTING},
{"w", GENERIC_WRITE, CREATE_ALWAYS},
{"wb", GENERIC_WRITE, CREATE_ALWAYS},
{"a", FILE_GENERIC_APPEND, OPEN_ALWAYS },
{"r+", GENERIC_WRITE|GENERIC_READ, OPEN_EXISTING},
{"rb+", GENERIC_WRITE|GENERIC_READ, OPEN_EXISTING},
{"r+b", GENERIC_WRITE|GENERIC_READ, OPEN_EXISTING},
{"w+", GENERIC_WRITE|GENERIC_READ, CREATE_ALWAYS},
{"wb+", GENERIC_WRITE|GENERIC_READ, CREATE_ALWAYS},
{"w+b", GENERIC_WRITE|GENERIC_READ, CREATE_ALWAYS},
{"a+", FILE_GENERIC_APPEND|GENERIC_READ, OPEN_ALWAYS },
{"ab+", FILE_GENERIC_APPEND|GENERIC_READ, OPEN_ALWAYS },
{"a+b", FILE_GENERIC_APPEND|GENERIC_READ, OPEN_ALWAYS }
};
#define debug_error(msg) do { \
char *suffix = g_win32_error_message(GetLastError()); \
g_debug("%s: %s", (msg), suffix); \
g_free(suffix); \
} while (0)
static OpenFlags *find_open_flag(const char *mode_str)
{
int mode;
Error **errp = NULL;
for (mode = 0; mode < ARRAY_SIZE(guest_file_open_modes); ++mode) {
OpenFlags *flags = guest_file_open_modes + mode;
if (strcmp(flags->forms, mode_str) == 0) {
return flags;
}
}
error_setg(errp, "invalid file open mode '%s'", mode_str);
return NULL;
}
static int64_t guest_file_handle_add(HANDLE fh, Error **errp)
{
GuestFileHandle *gfh;
int64_t handle;
handle = ga_get_fd_handle(ga_state, errp);
if (handle < 0) {
return -1;
}
gfh = g_new0(GuestFileHandle, 1);
gfh->id = handle;
gfh->fh = fh;
QTAILQ_INSERT_TAIL(&guest_file_state.filehandles, gfh, next);
return handle;
}
static GuestFileHandle *guest_file_handle_find(int64_t id, Error **errp)
{
GuestFileHandle *gfh;
QTAILQ_FOREACH(gfh, &guest_file_state.filehandles, next) {
if (gfh->id == id) {
return gfh;
}
}
error_setg(errp, "handle '%" PRId64 "' has not been found", id);
return NULL;
}
static void handle_set_nonblocking(HANDLE fh)
{
DWORD file_type, pipe_state;
file_type = GetFileType(fh);
if (file_type != FILE_TYPE_PIPE) {
return;
}
/* If file_type == FILE_TYPE_PIPE, according to MSDN
* the specified file is socket or named pipe */
if (!GetNamedPipeHandleState(fh, &pipe_state, NULL,
NULL, NULL, NULL, 0)) {
return;
}
/* The fd is named pipe fd */
if (pipe_state & PIPE_NOWAIT) {
return;
}
pipe_state |= PIPE_NOWAIT;
SetNamedPipeHandleState(fh, &pipe_state, NULL, NULL);
}
int64_t qmp_guest_file_open(const char *path, bool has_mode,
const char *mode, Error **errp)
{
int64_t fd = -1;
HANDLE fh;
HANDLE templ_file = NULL;
DWORD share_mode = FILE_SHARE_READ;
DWORD flags_and_attr = FILE_ATTRIBUTE_NORMAL;
LPSECURITY_ATTRIBUTES sa_attr = NULL;
OpenFlags *guest_flags;
GError *gerr = NULL;
wchar_t *w_path = NULL;
if (!has_mode) {
mode = "r";
}
slog("guest-file-open called, filepath: %s, mode: %s", path, mode);
guest_flags = find_open_flag(mode);
if (guest_flags == NULL) {
error_setg(errp, "invalid file open mode");
goto done;
}
w_path = g_utf8_to_utf16(path, -1, NULL, NULL, &gerr);
if (!w_path) {
goto done;
}
fh = CreateFileW(w_path, guest_flags->desired_access, share_mode, sa_attr,
guest_flags->creation_disposition, flags_and_attr,
templ_file);
if (fh == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(), "failed to open file '%s'",
path);
goto done;
}
/* set fd non-blocking to avoid common use cases (like reading from a
* named pipe) from hanging the agent
*/
handle_set_nonblocking(fh);
fd = guest_file_handle_add(fh, errp);
if (fd < 0) {
CloseHandle(fh);
error_setg(errp, "failed to add handle to qmp handle table");
goto done;
}
slog("guest-file-open, handle: % " PRId64, fd);
done:
if (gerr) {
error_setg(errp, QERR_QGA_COMMAND_FAILED, gerr->message);
g_error_free(gerr);
}
g_free(w_path);
return fd;
}
void qmp_guest_file_close(int64_t handle, Error **errp)
{
bool ret;
GuestFileHandle *gfh = guest_file_handle_find(handle, errp);
slog("guest-file-close called, handle: %" PRId64, handle);
if (gfh == NULL) {
return;
}
ret = CloseHandle(gfh->fh);
if (!ret) {
error_setg_win32(errp, GetLastError(), "failed close handle");
return;
}
QTAILQ_REMOVE(&guest_file_state.filehandles, gfh, next);
g_free(gfh);
}
static void acquire_privilege(const char *name, Error **errp)
{
HANDLE token = NULL;
TOKEN_PRIVILEGES priv;
Error *local_err = NULL;
if (OpenProcessToken(GetCurrentProcess(),
TOKEN_ADJUST_PRIVILEGES|TOKEN_QUERY, &token))
{
if (!LookupPrivilegeValue(NULL, name, &priv.Privileges[0].Luid)) {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"no luid for requested privilege");
goto out;
}
priv.PrivilegeCount = 1;
priv.Privileges[0].Attributes = SE_PRIVILEGE_ENABLED;
if (!AdjustTokenPrivileges(token, FALSE, &priv, 0, NULL, 0)) {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"unable to acquire requested privilege");
goto out;
}
} else {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"failed to open privilege token");
}
out:
if (token) {
CloseHandle(token);
}
error_propagate(errp, local_err);
}
static void execute_async(DWORD WINAPI (*func)(LPVOID), LPVOID opaque,
Error **errp)
{
Error *local_err = NULL;
HANDLE thread = CreateThread(NULL, 0, func, opaque, 0, NULL);
if (!thread) {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"failed to dispatch asynchronous command");
error_propagate(errp, local_err);
}
}
void qmp_guest_shutdown(bool has_mode, const char *mode, Error **errp)
{
Error *local_err = NULL;
UINT shutdown_flag = EWX_FORCE;
slog("guest-shutdown called, mode: %s", mode);
if (!has_mode || strcmp(mode, "powerdown") == 0) {
shutdown_flag |= EWX_POWEROFF;
} else if (strcmp(mode, "halt") == 0) {
shutdown_flag |= EWX_SHUTDOWN;
} else if (strcmp(mode, "reboot") == 0) {
shutdown_flag |= EWX_REBOOT;
} else {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "mode",
"halt|powerdown|reboot");
return;
}
/* Request a shutdown privilege, but try to shut down the system
anyway. */
acquire_privilege(SE_SHUTDOWN_NAME, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (!ExitWindowsEx(shutdown_flag, SHTDN_REASON_FLAG_PLANNED)) {
slog("guest-shutdown failed: %lu", GetLastError());
error_setg(errp, QERR_UNDEFINED_ERROR);
}
}
GuestFileRead *qmp_guest_file_read(int64_t handle, bool has_count,
int64_t count, Error **errp)
{
GuestFileRead *read_data = NULL;
guchar *buf;
HANDLE fh;
bool is_ok;
DWORD read_count;
GuestFileHandle *gfh = guest_file_handle_find(handle, errp);
if (!gfh) {
return NULL;
}
if (!has_count) {
count = QGA_READ_COUNT_DEFAULT;
} else if (count < 0 || count >= UINT32_MAX) {
error_setg(errp, "value '%" PRId64
"' is invalid for argument count", count);
return NULL;
}
fh = gfh->fh;
buf = g_malloc0(count+1);
is_ok = ReadFile(fh, buf, count, &read_count, NULL);
if (!is_ok) {
error_setg_win32(errp, GetLastError(), "failed to read file");
slog("guest-file-read failed, handle %" PRId64, handle);
} else {
buf[read_count] = 0;
read_data = g_new0(GuestFileRead, 1);
read_data->count = (size_t)read_count;
read_data->eof = read_count == 0;
if (read_count != 0) {
read_data->buf_b64 = g_base64_encode(buf, read_count);
}
}
g_free(buf);
return read_data;
}
GuestFileWrite *qmp_guest_file_write(int64_t handle, const char *buf_b64,
bool has_count, int64_t count,
Error **errp)
{
GuestFileWrite *write_data = NULL;
guchar *buf;
gsize buf_len;
bool is_ok;
DWORD write_count;
GuestFileHandle *gfh = guest_file_handle_find(handle, errp);
HANDLE fh;
if (!gfh) {
return NULL;
}
fh = gfh->fh;
buf = qbase64_decode(buf_b64, -1, &buf_len, errp);
if (!buf) {
return NULL;
}
if (!has_count) {
count = buf_len;
} else if (count < 0 || count > buf_len) {
error_setg(errp, "value '%" PRId64
"' is invalid for argument count", count);
goto done;
}
is_ok = WriteFile(fh, buf, count, &write_count, NULL);
if (!is_ok) {
error_setg_win32(errp, GetLastError(), "failed to write to file");
slog("guest-file-write-failed, handle: %" PRId64, handle);
} else {
write_data = g_new0(GuestFileWrite, 1);
write_data->count = (size_t) write_count;
}
done:
g_free(buf);
return write_data;
}
GuestFileSeek *qmp_guest_file_seek(int64_t handle, int64_t offset,
GuestFileWhence *whence_code,
Error **errp)
{
GuestFileHandle *gfh;
GuestFileSeek *seek_data;
HANDLE fh;
LARGE_INTEGER new_pos, off_pos;
off_pos.QuadPart = offset;
BOOL res;
int whence;
Error *err = NULL;
gfh = guest_file_handle_find(handle, errp);
if (!gfh) {
return NULL;
}
/* We stupidly exposed 'whence':'int' in our qapi */
whence = ga_parse_whence(whence_code, &err);
if (err) {
error_propagate(errp, err);
return NULL;
}
fh = gfh->fh;
res = SetFilePointerEx(fh, off_pos, &new_pos, whence);
if (!res) {
error_setg_win32(errp, GetLastError(), "failed to seek file");
return NULL;
}
seek_data = g_new0(GuestFileSeek, 1);
seek_data->position = new_pos.QuadPart;
return seek_data;
}
void qmp_guest_file_flush(int64_t handle, Error **errp)
{
HANDLE fh;
GuestFileHandle *gfh = guest_file_handle_find(handle, errp);
if (!gfh) {
return;
}
fh = gfh->fh;
if (!FlushFileBuffers(fh)) {
error_setg_win32(errp, GetLastError(), "failed to flush file");
}
}
#ifdef CONFIG_QGA_NTDDSCSI
static STORAGE_BUS_TYPE win2qemu[] = {
[BusTypeUnknown] = GUEST_DISK_BUS_TYPE_UNKNOWN,
[BusTypeScsi] = GUEST_DISK_BUS_TYPE_SCSI,
[BusTypeAtapi] = GUEST_DISK_BUS_TYPE_IDE,
[BusTypeAta] = GUEST_DISK_BUS_TYPE_IDE,
[BusType1394] = GUEST_DISK_BUS_TYPE_IEEE1394,
[BusTypeSsa] = GUEST_DISK_BUS_TYPE_SSA,
[BusTypeFibre] = GUEST_DISK_BUS_TYPE_SSA,
[BusTypeUsb] = GUEST_DISK_BUS_TYPE_USB,
[BusTypeRAID] = GUEST_DISK_BUS_TYPE_RAID,
[BusTypeiScsi] = GUEST_DISK_BUS_TYPE_ISCSI,
[BusTypeSas] = GUEST_DISK_BUS_TYPE_SAS,
[BusTypeSata] = GUEST_DISK_BUS_TYPE_SATA,
[BusTypeSd] = GUEST_DISK_BUS_TYPE_SD,
[BusTypeMmc] = GUEST_DISK_BUS_TYPE_MMC,
#if (_WIN32_WINNT >= 0x0601)
[BusTypeVirtual] = GUEST_DISK_BUS_TYPE_VIRTUAL,
[BusTypeFileBackedVirtual] = GUEST_DISK_BUS_TYPE_FILE_BACKED_VIRTUAL,
#endif
};
static GuestDiskBusType find_bus_type(STORAGE_BUS_TYPE bus)
{
if (bus >= ARRAY_SIZE(win2qemu) || (int)bus < 0) {
return GUEST_DISK_BUS_TYPE_UNKNOWN;
}
return win2qemu[(int)bus];
}
DEFINE_GUID(GUID_DEVINTERFACE_DISK,
0x53f56307L, 0xb6bf, 0x11d0, 0x94, 0xf2,
0x00, 0xa0, 0xc9, 0x1e, 0xfb, 0x8b);
DEFINE_GUID(GUID_DEVINTERFACE_STORAGEPORT,
0x2accfe60L, 0xc130, 0x11d2, 0xb0, 0x82,
0x00, 0xa0, 0xc9, 0x1e, 0xfb, 0x8b);
static GuestPCIAddress *get_pci_info(int number, Error **errp)
{
HDEVINFO dev_info;
SP_DEVINFO_DATA dev_info_data;
SP_DEVICE_INTERFACE_DATA dev_iface_data;
HANDLE dev_file;
int i;
GuestPCIAddress *pci = NULL;
bool partial_pci = false;
pci = g_malloc0(sizeof(*pci));
pci->domain = -1;
pci->slot = -1;
pci->function = -1;
pci->bus = -1;
dev_info = SetupDiGetClassDevs(&GUID_DEVINTERFACE_DISK, 0, 0,
DIGCF_PRESENT | DIGCF_DEVICEINTERFACE);
if (dev_info == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(), "failed to get devices tree");
goto out;
}
g_debug("enumerating devices");
dev_info_data.cbSize = sizeof(SP_DEVINFO_DATA);
dev_iface_data.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
for (i = 0; SetupDiEnumDeviceInfo(dev_info, i, &dev_info_data); i++) {
PSP_DEVICE_INTERFACE_DETAIL_DATA pdev_iface_detail_data = NULL;
STORAGE_DEVICE_NUMBER sdn;
char *parent_dev_id = NULL;
HDEVINFO parent_dev_info;
SP_DEVINFO_DATA parent_dev_info_data;
DWORD j;
DWORD size = 0;
g_debug("getting device path");
if (SetupDiEnumDeviceInterfaces(dev_info, &dev_info_data,
&GUID_DEVINTERFACE_DISK, 0,
&dev_iface_data)) {
while (!SetupDiGetDeviceInterfaceDetail(dev_info, &dev_iface_data,
pdev_iface_detail_data,
size, &size,
&dev_info_data)) {
if (GetLastError() == ERROR_INSUFFICIENT_BUFFER) {
pdev_iface_detail_data = g_malloc(size);
pdev_iface_detail_data->cbSize =
sizeof(*pdev_iface_detail_data);
} else {
error_setg_win32(errp, GetLastError(),
"failed to get device interfaces");
goto free_dev_info;
}
}
dev_file = CreateFile(pdev_iface_detail_data->DevicePath, 0,
FILE_SHARE_READ, NULL, OPEN_EXISTING, 0,
NULL);
g_free(pdev_iface_detail_data);
if (!DeviceIoControl(dev_file, IOCTL_STORAGE_GET_DEVICE_NUMBER,
NULL, 0, &sdn, sizeof(sdn), &size, NULL)) {
CloseHandle(dev_file);
error_setg_win32(errp, GetLastError(),
"failed to get device slot number");
goto free_dev_info;
}
CloseHandle(dev_file);
if (sdn.DeviceNumber != number) {
continue;
}
} else {
error_setg_win32(errp, GetLastError(),
"failed to get device interfaces");
goto free_dev_info;
}
g_debug("found device slot %d. Getting storage controller", number);
{
CONFIGRET cr;
DEVINST dev_inst, parent_dev_inst;
ULONG dev_id_size = 0;
size = 0;
while (!SetupDiGetDeviceInstanceId(dev_info, &dev_info_data,
parent_dev_id, size, &size)) {
if (GetLastError() == ERROR_INSUFFICIENT_BUFFER) {
parent_dev_id = g_malloc(size);
} else {
error_setg_win32(errp, GetLastError(),
"failed to get device instance ID");
goto out;
}
}
/*
* CM API used here as opposed to
* SetupDiGetDeviceProperty(..., DEVPKEY_Device_Parent, ...)
* which exports are only available in mingw-w64 6+
*/
cr = CM_Locate_DevInst(&dev_inst, parent_dev_id, 0);
if (cr != CR_SUCCESS) {
g_error("CM_Locate_DevInst failed with code %lx", cr);
error_setg_win32(errp, GetLastError(),
"failed to get device instance");
goto out;
}
cr = CM_Get_Parent(&parent_dev_inst, dev_inst, 0);
if (cr != CR_SUCCESS) {
g_error("CM_Get_Parent failed with code %lx", cr);
error_setg_win32(errp, GetLastError(),
"failed to get parent device instance");
goto out;
}
cr = CM_Get_Device_ID_Size(&dev_id_size, parent_dev_inst, 0);
if (cr != CR_SUCCESS) {
g_error("CM_Get_Device_ID_Size failed with code %lx", cr);
error_setg_win32(errp, GetLastError(),
"failed to get parent device ID length");
goto out;
}
++dev_id_size;
if (dev_id_size > size) {
g_free(parent_dev_id);
parent_dev_id = g_malloc(dev_id_size);
}
cr = CM_Get_Device_ID(parent_dev_inst, parent_dev_id, dev_id_size,
0);
if (cr != CR_SUCCESS) {
g_error("CM_Get_Device_ID failed with code %lx", cr);
error_setg_win32(errp, GetLastError(),
"failed to get parent device ID");
goto out;
}
}
g_debug("querying storage controller %s for PCI information",
parent_dev_id);
parent_dev_info =
SetupDiGetClassDevs(&GUID_DEVINTERFACE_STORAGEPORT, parent_dev_id,
NULL, DIGCF_PRESENT | DIGCF_DEVICEINTERFACE);
g_free(parent_dev_id);
if (parent_dev_info == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(),
"failed to get parent device");
goto out;
}
parent_dev_info_data.cbSize = sizeof(SP_DEVINFO_DATA);
if (!SetupDiEnumDeviceInfo(parent_dev_info, 0, &parent_dev_info_data)) {
error_setg_win32(errp, GetLastError(),
"failed to get parent device data");
goto out;
}
for (j = 0;
SetupDiEnumDeviceInfo(parent_dev_info, j, &parent_dev_info_data);
j++) {
DWORD addr, bus, ui_slot, type;
int func, slot;
/*
* There is no need to allocate buffer in the next functions. The
* size is known and ULONG according to
* https://msdn.microsoft.com/en-us/library/windows/hardware/ff543095(v=vs.85).aspx
*/
if (!SetupDiGetDeviceRegistryProperty(
parent_dev_info, &parent_dev_info_data, SPDRP_BUSNUMBER,
&type, (PBYTE)&bus, size, NULL)) {
debug_error("failed to get PCI bus");
bus = -1;
partial_pci = true;
}
/*
* The function retrieves the device's address. This value will be
* transformed into device function and number
*/
if (!SetupDiGetDeviceRegistryProperty(
parent_dev_info, &parent_dev_info_data, SPDRP_ADDRESS,
&type, (PBYTE)&addr, size, NULL)) {
debug_error("failed to get PCI address");
addr = -1;
partial_pci = true;
}
/*
* This call returns UINumber of DEVICE_CAPABILITIES structure.
* This number is typically a user-perceived slot number.
*/
if (!SetupDiGetDeviceRegistryProperty(
parent_dev_info, &parent_dev_info_data, SPDRP_UI_NUMBER,
&type, (PBYTE)&ui_slot, size, NULL)) {
debug_error("failed to get PCI slot");
ui_slot = -1;
partial_pci = true;
}
/*
* SetupApi gives us the same information as driver with
* IoGetDeviceProperty. According to Microsoft:
*
* FunctionNumber = (USHORT)((propertyAddress) & 0x0000FFFF)
* DeviceNumber = (USHORT)(((propertyAddress) >> 16) & 0x0000FFFF)
* SPDRP_ADDRESS is propertyAddress, so we do the same.
*
* https://docs.microsoft.com/en-us/windows/desktop/api/setupapi/nf-setupapi-setupdigetdeviceregistrypropertya
*/
if (partial_pci) {
pci->domain = -1;
pci->slot = -1;
pci->function = -1;
pci->bus = -1;
continue;
} else {
func = ((int)addr == -1) ? -1 : addr & 0x0000FFFF;
slot = ((int)addr == -1) ? -1 : (addr >> 16) & 0x0000FFFF;
if ((int)ui_slot != slot) {
g_debug("mismatch with reported slot values: %d vs %d",
(int)ui_slot, slot);
}
pci->domain = 0;
pci->slot = (int)ui_slot;
pci->function = func;
pci->bus = (int)bus;
break;
}
}
SetupDiDestroyDeviceInfoList(parent_dev_info);
break;
}
free_dev_info:
SetupDiDestroyDeviceInfoList(dev_info);
out:
return pci;
}
static void get_disk_properties(HANDLE vol_h, GuestDiskAddress *disk,
Error **errp)
{
STORAGE_PROPERTY_QUERY query;
STORAGE_DEVICE_DESCRIPTOR *dev_desc, buf;
DWORD received;
ULONG size = sizeof(buf);
dev_desc = &buf;
query.PropertyId = StorageDeviceProperty;
query.QueryType = PropertyStandardQuery;
if (!DeviceIoControl(vol_h, IOCTL_STORAGE_QUERY_PROPERTY, &query,
sizeof(STORAGE_PROPERTY_QUERY), dev_desc,
size, &received, NULL)) {
error_setg_win32(errp, GetLastError(), "failed to get bus type");
return;
}
disk->bus_type = find_bus_type(dev_desc->BusType);
g_debug("bus type %d", disk->bus_type);
/* Query once more. Now with long enough buffer. */
size = dev_desc->Size;
dev_desc = g_malloc0(size);
if (!DeviceIoControl(vol_h, IOCTL_STORAGE_QUERY_PROPERTY, &query,
sizeof(STORAGE_PROPERTY_QUERY), dev_desc,
size, &received, NULL)) {
error_setg_win32(errp, GetLastError(), "failed to get serial number");
g_debug("failed to get serial number");
goto out_free;
}
if (dev_desc->SerialNumberOffset > 0) {
const char *serial;
size_t len;
if (dev_desc->SerialNumberOffset >= received) {
error_setg(errp, "failed to get serial number: offset outside the buffer");
g_debug("serial number offset outside the buffer");
goto out_free;
}
serial = (char *)dev_desc + dev_desc->SerialNumberOffset;
len = received - dev_desc->SerialNumberOffset;
g_debug("serial number \"%s\"", serial);
if (*serial != 0) {
disk->serial = g_strndup(serial, len);
disk->has_serial = true;
}
}
out_free:
g_free(dev_desc);
return;
}
static void get_single_disk_info(int disk_number,
GuestDiskAddress *disk, Error **errp)
{
SCSI_ADDRESS addr, *scsi_ad;
DWORD len;
HANDLE disk_h;
Error *local_err = NULL;
scsi_ad = &addr;
g_debug("getting disk info for: %s", disk->dev);
disk_h = CreateFile(disk->dev, 0, FILE_SHARE_READ, NULL, OPEN_EXISTING,
0, NULL);
if (disk_h == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(), "failed to open disk");
return;
}
get_disk_properties(disk_h, disk, &local_err);
if (local_err) {
error_propagate(errp, local_err);
goto err_close;
}
g_debug("bus type %d", disk->bus_type);
/* always set pci_controller as required by schema. get_pci_info() should
* report -1 values for non-PCI buses rather than fail. fail the command
* if that doesn't hold since that suggests some other unexpected
* breakage
*/
disk->pci_controller = get_pci_info(disk_number, &local_err);
if (local_err) {
error_propagate(errp, local_err);
goto err_close;
}
if (disk->bus_type == GUEST_DISK_BUS_TYPE_SCSI
|| disk->bus_type == GUEST_DISK_BUS_TYPE_IDE
|| disk->bus_type == GUEST_DISK_BUS_TYPE_RAID
/* This bus type is not supported before Windows Server 2003 SP1 */
|| disk->bus_type == GUEST_DISK_BUS_TYPE_SAS
) {
/* We are able to use the same ioctls for different bus types
* according to Microsoft docs
* https://technet.microsoft.com/en-us/library/ee851589(v=ws.10).aspx */
g_debug("getting SCSI info");
if (DeviceIoControl(disk_h, IOCTL_SCSI_GET_ADDRESS, NULL, 0, scsi_ad,
sizeof(SCSI_ADDRESS), &len, NULL)) {
disk->unit = addr.Lun;
disk->target = addr.TargetId;
disk->bus = addr.PathId;
}
/* We do not set error in this case, because we still have enough
* information about volume. */
}
err_close:
CloseHandle(disk_h);
return;
}
/* VSS provider works with volumes, thus there is no difference if
* the volume consist of spanned disks. Info about the first disk in the
* volume is returned for the spanned disk group (LVM) */
static GuestDiskAddressList *build_guest_disk_info(char *guid, Error **errp)
{
Error *local_err = NULL;
GuestDiskAddressList *list = NULL, *cur_item = NULL;
GuestDiskAddress *disk = NULL;
int i;
HANDLE vol_h;
DWORD size;
PVOLUME_DISK_EXTENTS extents = NULL;
/* strip final backslash */
char *name = g_strdup(guid);
if (g_str_has_suffix(name, "\\")) {
name[strlen(name) - 1] = 0;
}
g_debug("opening %s", name);
vol_h = CreateFile(name, 0, FILE_SHARE_READ, NULL, OPEN_EXISTING,
0, NULL);
if (vol_h == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(), "failed to open volume");
goto out;
}
/* Get list of extents */
g_debug("getting disk extents");
size = sizeof(VOLUME_DISK_EXTENTS);
extents = g_malloc0(size);
if (!DeviceIoControl(vol_h, IOCTL_VOLUME_GET_VOLUME_DISK_EXTENTS, NULL,
0, extents, size, &size, NULL)) {
DWORD last_err = GetLastError();
if (last_err == ERROR_MORE_DATA) {
/* Try once more with big enough buffer */
g_free(extents);
extents = g_malloc0(size);
if (!DeviceIoControl(
vol_h, IOCTL_VOLUME_GET_VOLUME_DISK_EXTENTS, NULL,
0, extents, size, NULL, NULL)) {
error_setg_win32(errp, GetLastError(),
"failed to get disk extents");
goto out;
}
} else if (last_err == ERROR_INVALID_FUNCTION) {
/* Possibly CD-ROM or a shared drive. Try to pass the volume */
g_debug("volume not on disk");
disk = g_malloc0(sizeof(GuestDiskAddress));
disk->has_dev = true;
disk->dev = g_strdup(name);
get_single_disk_info(0xffffffff, disk, &local_err);
if (local_err) {
g_debug("failed to get disk info, ignoring error: %s",
error_get_pretty(local_err));
error_free(local_err);
goto out;
}
list = g_malloc0(sizeof(*list));
list->value = disk;
disk = NULL;
list->next = NULL;
goto out;
} else {
error_setg_win32(errp, GetLastError(),
"failed to get disk extents");
goto out;
}
}
g_debug("Number of extents: %lu", extents->NumberOfDiskExtents);
/* Go through each extent */
for (i = 0; i < extents->NumberOfDiskExtents; i++) {
disk = g_malloc0(sizeof(GuestDiskAddress));
/* Disk numbers directly correspond to numbers used in UNCs
*
* See documentation for DISK_EXTENT:
* https://docs.microsoft.com/en-us/windows/desktop/api/winioctl/ns-winioctl-_disk_extent
*
* See also Naming Files, Paths and Namespaces:
* https://docs.microsoft.com/en-us/windows/desktop/FileIO/naming-a-file#win32-device-namespaces
*/
disk->has_dev = true;
disk->dev = g_strdup_printf("\\\\.\\PhysicalDrive%lu",
extents->Extents[i].DiskNumber);
get_single_disk_info(extents->Extents[i].DiskNumber, disk, &local_err);
if (local_err) {
error_propagate(errp, local_err);
goto out;
}
cur_item = g_malloc0(sizeof(*list));
cur_item->value = disk;
disk = NULL;
cur_item->next = list;
list = cur_item;
}
out:
if (vol_h != INVALID_HANDLE_VALUE) {
CloseHandle(vol_h);
}
qapi_free_GuestDiskAddress(disk);
g_free(extents);
g_free(name);
return list;
}
#else
static GuestDiskAddressList *build_guest_disk_info(char *guid, Error **errp)
{
return NULL;
}
#endif /* CONFIG_QGA_NTDDSCSI */
static GuestFilesystemInfo *build_guest_fsinfo(char *guid, Error **errp)
{
DWORD info_size;
char mnt, *mnt_point;
char fs_name[32];
char vol_info[MAX_PATH+1];
size_t len;
uint64_t i64FreeBytesToCaller, i64TotalBytes, i64FreeBytes;
GuestFilesystemInfo *fs = NULL;
GetVolumePathNamesForVolumeName(guid, (LPCH)&mnt, 0, &info_size);
if (GetLastError() != ERROR_MORE_DATA) {
error_setg_win32(errp, GetLastError(), "failed to get volume name");
return NULL;
}
mnt_point = g_malloc(info_size + 1);
if (!GetVolumePathNamesForVolumeName(guid, mnt_point, info_size,
&info_size)) {
error_setg_win32(errp, GetLastError(), "failed to get volume name");
goto free;
}
len = strlen(mnt_point);
mnt_point[len] = '\\';
mnt_point[len+1] = 0;
if (!GetVolumeInformation(mnt_point, vol_info, sizeof(vol_info), NULL, NULL,
NULL, (LPSTR)&fs_name, sizeof(fs_name))) {
if (GetLastError() != ERROR_NOT_READY) {
error_setg_win32(errp, GetLastError(), "failed to get volume info");
}
goto free;
}
fs_name[sizeof(fs_name) - 1] = 0;
fs = g_malloc(sizeof(*fs));
fs->name = g_strdup(guid);
fs->has_total_bytes = false;
fs->has_used_bytes = false;
if (len == 0) {
fs->mountpoint = g_strdup("System Reserved");
} else {
fs->mountpoint = g_strndup(mnt_point, len);
if (GetDiskFreeSpaceEx(fs->mountpoint,
(PULARGE_INTEGER) & i64FreeBytesToCaller,
(PULARGE_INTEGER) & i64TotalBytes,
(PULARGE_INTEGER) & i64FreeBytes)) {
fs->used_bytes = i64TotalBytes - i64FreeBytes;
fs->total_bytes = i64TotalBytes;
fs->has_total_bytes = true;
fs->has_used_bytes = true;
}
}
fs->type = g_strdup(fs_name);
fs->disk = build_guest_disk_info(guid, errp);
free:
g_free(mnt_point);
return fs;
}
GuestFilesystemInfoList *qmp_guest_get_fsinfo(Error **errp)
{
HANDLE vol_h;
GuestFilesystemInfoList *new, *ret = NULL;
char guid[256];
vol_h = FindFirstVolume(guid, sizeof(guid));
if (vol_h == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(), "failed to find any volume");
return NULL;
}
do {
GuestFilesystemInfo *info = build_guest_fsinfo(guid, errp);
if (info == NULL) {
continue;
}
new = g_malloc(sizeof(*ret));
new->value = info;
new->next = ret;
ret = new;
} while (FindNextVolume(vol_h, guid, sizeof(guid)));
if (GetLastError() != ERROR_NO_MORE_FILES) {
error_setg_win32(errp, GetLastError(), "failed to find next volume");
}
FindVolumeClose(vol_h);
return ret;
}
/*
* Return status of freeze/thaw
*/
GuestFsfreezeStatus qmp_guest_fsfreeze_status(Error **errp)
{
if (!vss_initialized()) {
error_setg(errp, QERR_UNSUPPORTED);
return 0;
}
if (ga_is_frozen(ga_state)) {
return GUEST_FSFREEZE_STATUS_FROZEN;
}
return GUEST_FSFREEZE_STATUS_THAWED;
}
/*
* Freeze local file systems using Volume Shadow-copy Service.
* The frozen state is limited for up to 10 seconds by VSS.
*/
int64_t qmp_guest_fsfreeze_freeze(Error **errp)
{
return qmp_guest_fsfreeze_freeze_list(false, NULL, errp);
}
int64_t qmp_guest_fsfreeze_freeze_list(bool has_mountpoints,
strList *mountpoints,
Error **errp)
{
int i;
Error *local_err = NULL;
if (!vss_initialized()) {
error_setg(errp, QERR_UNSUPPORTED);
return 0;
}
slog("guest-fsfreeze called");
/* cannot risk guest agent blocking itself on a write in this state */
ga_set_frozen(ga_state);
qga_vss_fsfreeze(&i, true, mountpoints, &local_err);
if (local_err) {
error_propagate(errp, local_err);
goto error;
}
return i;
error:
local_err = NULL;
qmp_guest_fsfreeze_thaw(&local_err);
if (local_err) {
g_debug("cleanup thaw: %s", error_get_pretty(local_err));
error_free(local_err);
}
return 0;
}
/*
* Thaw local file systems using Volume Shadow-copy Service.
*/
int64_t qmp_guest_fsfreeze_thaw(Error **errp)
{
int i;
if (!vss_initialized()) {
error_setg(errp, QERR_UNSUPPORTED);
return 0;
}
qga_vss_fsfreeze(&i, false, NULL, errp);
ga_unset_frozen(ga_state);
return i;
}
static void guest_fsfreeze_cleanup(void)
{
Error *err = NULL;
if (!vss_initialized()) {
return;
}
if (ga_is_frozen(ga_state) == GUEST_FSFREEZE_STATUS_FROZEN) {
qmp_guest_fsfreeze_thaw(&err);
if (err) {
slog("failed to clean up frozen filesystems: %s",
error_get_pretty(err));
error_free(err);
}
}
vss_deinit(true);
}
/*
* Walk list of mounted file systems in the guest, and discard unused
* areas.
*/
GuestFilesystemTrimResponse *
qmp_guest_fstrim(bool has_minimum, int64_t minimum, Error **errp)
{
GuestFilesystemTrimResponse *resp;
HANDLE handle;
WCHAR guid[MAX_PATH] = L"";
OSVERSIONINFO osvi;
BOOL win8_or_later;
ZeroMemory(&osvi, sizeof(OSVERSIONINFO));
osvi.dwOSVersionInfoSize = sizeof(OSVERSIONINFO);
GetVersionEx(&osvi);
win8_or_later = (osvi.dwMajorVersion > 6 ||
((osvi.dwMajorVersion == 6) &&
(osvi.dwMinorVersion >= 2)));
if (!win8_or_later) {
error_setg(errp, "fstrim is only supported for Win8+");
return NULL;
}
handle = FindFirstVolumeW(guid, ARRAYSIZE(guid));
if (handle == INVALID_HANDLE_VALUE) {
error_setg_win32(errp, GetLastError(), "failed to find any volume");
return NULL;
}
resp = g_new0(GuestFilesystemTrimResponse, 1);
do {
GuestFilesystemTrimResult *res;
GuestFilesystemTrimResultList *list;
PWCHAR uc_path;
DWORD char_count = 0;
char *path, *out;
GError *gerr = NULL;
gchar * argv[4];
GetVolumePathNamesForVolumeNameW(guid, NULL, 0, &char_count);
if (GetLastError() != ERROR_MORE_DATA) {
continue;
}
if (GetDriveTypeW(guid) != DRIVE_FIXED) {
continue;
}
uc_path = g_malloc(sizeof(WCHAR) * char_count);
if (!GetVolumePathNamesForVolumeNameW(guid, uc_path, char_count,
&char_count) || !*uc_path) {
/* strange, but this condition could be faced even with size == 2 */
g_free(uc_path);
continue;
}
res = g_new0(GuestFilesystemTrimResult, 1);
path = g_utf16_to_utf8(uc_path, char_count, NULL, NULL, &gerr);
g_free(uc_path);
if (!path) {
res->has_error = true;
res->error = g_strdup(gerr->message);
g_error_free(gerr);
break;
}
res->path = path;
list = g_new0(GuestFilesystemTrimResultList, 1);
list->value = res;
list->next = resp->paths;
resp->paths = list;
memset(argv, 0, sizeof(argv));
argv[0] = (gchar *)"defrag.exe";
argv[1] = (gchar *)"/L";
argv[2] = path;
if (!g_spawn_sync(NULL, argv, NULL, G_SPAWN_SEARCH_PATH, NULL, NULL,
&out /* stdout */, NULL /* stdin */,
NULL, &gerr)) {
res->has_error = true;
res->error = g_strdup(gerr->message);
g_error_free(gerr);
} else {
/* defrag.exe is UGLY. Exit code is ALWAYS zero.
Error is reported in the output with something like
(x89000020) etc code in the stdout */
int i;
gchar **lines = g_strsplit(out, "\r\n", 0);
g_free(out);
for (i = 0; lines[i] != NULL; i++) {
if (g_strstr_len(lines[i], -1, "(0x") == NULL) {
continue;
}
res->has_error = true;
res->error = g_strdup(lines[i]);
break;
}
g_strfreev(lines);
}
} while (FindNextVolumeW(handle, guid, ARRAYSIZE(guid)));
FindVolumeClose(handle);
return resp;
}
typedef enum {
GUEST_SUSPEND_MODE_DISK,
GUEST_SUSPEND_MODE_RAM
} GuestSuspendMode;
static void check_suspend_mode(GuestSuspendMode mode, Error **errp)
{
SYSTEM_POWER_CAPABILITIES sys_pwr_caps;
Error *local_err = NULL;
ZeroMemory(&sys_pwr_caps, sizeof(sys_pwr_caps));
if (!GetPwrCapabilities(&sys_pwr_caps)) {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"failed to determine guest suspend capabilities");
goto out;
}
switch (mode) {
case GUEST_SUSPEND_MODE_DISK:
if (!sys_pwr_caps.SystemS4) {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"suspend-to-disk not supported by OS");
}
break;
case GUEST_SUSPEND_MODE_RAM:
if (!sys_pwr_caps.SystemS3) {
error_setg(&local_err, QERR_QGA_COMMAND_FAILED,
"suspend-to-ram not supported by OS");
}
break;
default:
error_setg(&local_err, QERR_INVALID_PARAMETER_VALUE, "mode",
"GuestSuspendMode");
}
out:
error_propagate(errp, local_err);
}
static DWORD WINAPI do_suspend(LPVOID opaque)
{
GuestSuspendMode *mode = opaque;
DWORD ret = 0;
if (!SetSuspendState(*mode == GUEST_SUSPEND_MODE_DISK, TRUE, TRUE)) {
slog("failed to suspend guest, %lu", GetLastError());
ret = -1;
}
g_free(mode);
return ret;
}
void qmp_guest_suspend_disk(Error **errp)
{
Error *local_err = NULL;
GuestSuspendMode *mode = g_new(GuestSuspendMode, 1);
*mode = GUEST_SUSPEND_MODE_DISK;
check_suspend_mode(*mode, &local_err);
acquire_privilege(SE_SHUTDOWN_NAME, &local_err);
execute_async(do_suspend, mode, &local_err);
if (local_err) {
error_propagate(errp, local_err);
g_free(mode);
}
}
void qmp_guest_suspend_ram(Error **errp)
{
Error *local_err = NULL;
GuestSuspendMode *mode = g_new(GuestSuspendMode, 1);
*mode = GUEST_SUSPEND_MODE_RAM;
check_suspend_mode(*mode, &local_err);
acquire_privilege(SE_SHUTDOWN_NAME, &local_err);
execute_async(do_suspend, mode, &local_err);
if (local_err) {
error_propagate(errp, local_err);
g_free(mode);
}
}
void qmp_guest_suspend_hybrid(Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
}
static IP_ADAPTER_ADDRESSES *guest_get_adapters_addresses(Error **errp)
{
IP_ADAPTER_ADDRESSES *adptr_addrs = NULL;
ULONG adptr_addrs_len = 0;
DWORD ret;
/* Call the first time to get the adptr_addrs_len. */
GetAdaptersAddresses(AF_UNSPEC, GAA_FLAG_INCLUDE_PREFIX,
NULL, adptr_addrs, &adptr_addrs_len);
adptr_addrs = g_malloc(adptr_addrs_len);
ret = GetAdaptersAddresses(AF_UNSPEC, GAA_FLAG_INCLUDE_PREFIX,
NULL, adptr_addrs, &adptr_addrs_len);
if (ret != ERROR_SUCCESS) {
error_setg_win32(errp, ret, "failed to get adapters addresses");
g_free(adptr_addrs);
adptr_addrs = NULL;
}
return adptr_addrs;
}
static char *guest_wctomb_dup(WCHAR *wstr)
{
char *str;
size_t i;
i = wcslen(wstr) + 1;
str = g_malloc(i);
WideCharToMultiByte(CP_ACP, WC_COMPOSITECHECK,
wstr, -1, str, i, NULL, NULL);
return str;
}
static char *guest_addr_to_str(IP_ADAPTER_UNICAST_ADDRESS *ip_addr,
Error **errp)
{
char addr_str[INET6_ADDRSTRLEN + INET_ADDRSTRLEN];
DWORD len;
int ret;
if (ip_addr->Address.lpSockaddr->sa_family == AF_INET ||
ip_addr->Address.lpSockaddr->sa_family == AF_INET6) {
len = sizeof(addr_str);
ret = WSAAddressToString(ip_addr->Address.lpSockaddr,
ip_addr->Address.iSockaddrLength,
NULL,
addr_str,
&len);
if (ret != 0) {
error_setg_win32(errp, WSAGetLastError(),
"failed address presentation form conversion");
return NULL;
}
return g_strdup(addr_str);
}
return NULL;
}
static int64_t guest_ip_prefix(IP_ADAPTER_UNICAST_ADDRESS *ip_addr)
{
/* For Windows Vista/2008 and newer, use the OnLinkPrefixLength
* field to obtain the prefix.
*/
return ip_addr->OnLinkPrefixLength;
}
#define INTERFACE_PATH_BUF_SZ 512
static DWORD get_interface_index(const char *guid)
{
ULONG index;
DWORD status;
wchar_t wbuf[INTERFACE_PATH_BUF_SZ];
snwprintf(wbuf, INTERFACE_PATH_BUF_SZ, L"\\device\\tcpip_%s", guid);
wbuf[INTERFACE_PATH_BUF_SZ - 1] = 0;
status = GetAdapterIndex (wbuf, &index);
if (status != NO_ERROR) {
return (DWORD)~0;
} else {
return index;
}
}
typedef NETIOAPI_API (WINAPI *GetIfEntry2Func)(PMIB_IF_ROW2 Row);
static int guest_get_network_stats(const char *name,
GuestNetworkInterfaceStat *stats)
{
OSVERSIONINFO os_ver;
os_ver.dwOSVersionInfoSize = sizeof(OSVERSIONINFO);
GetVersionEx(&os_ver);
if (os_ver.dwMajorVersion >= 6) {
MIB_IF_ROW2 a_mid_ifrow;
GetIfEntry2Func getifentry2_ex;
DWORD if_index = 0;
HMODULE module = GetModuleHandle("iphlpapi");
PVOID func = GetProcAddress(module, "GetIfEntry2");
if (func == NULL) {
return -1;
}
getifentry2_ex = (GetIfEntry2Func)func;
if_index = get_interface_index(name);
if (if_index == (DWORD)~0) {
return -1;
}
memset(&a_mid_ifrow, 0, sizeof(a_mid_ifrow));
a_mid_ifrow.InterfaceIndex = if_index;
if (NO_ERROR == getifentry2_ex(&a_mid_ifrow)) {
stats->rx_bytes = a_mid_ifrow.InOctets;
stats->rx_packets = a_mid_ifrow.InUcastPkts;
stats->rx_errs = a_mid_ifrow.InErrors;
stats->rx_dropped = a_mid_ifrow.InDiscards;
stats->tx_bytes = a_mid_ifrow.OutOctets;
stats->tx_packets = a_mid_ifrow.OutUcastPkts;
stats->tx_errs = a_mid_ifrow.OutErrors;
stats->tx_dropped = a_mid_ifrow.OutDiscards;
return 0;
}
}
return -1;
}
GuestNetworkInterfaceList *qmp_guest_network_get_interfaces(Error **errp)
{
IP_ADAPTER_ADDRESSES *adptr_addrs, *addr;
IP_ADAPTER_UNICAST_ADDRESS *ip_addr = NULL;
GuestNetworkInterfaceList *head = NULL, *cur_item = NULL;
GuestIpAddressList *head_addr, *cur_addr;
GuestNetworkInterfaceList *info;
GuestNetworkInterfaceStat *interface_stat = NULL;
GuestIpAddressList *address_item = NULL;
unsigned char *mac_addr;
char *addr_str;
WORD wsa_version;
WSADATA wsa_data;
int ret;
adptr_addrs = guest_get_adapters_addresses(errp);
if (adptr_addrs == NULL) {
return NULL;
}
/* Make WSA APIs available. */
wsa_version = MAKEWORD(2, 2);
ret = WSAStartup(wsa_version, &wsa_data);
if (ret != 0) {
error_setg_win32(errp, ret, "failed socket startup");
goto out;
}
for (addr = adptr_addrs; addr; addr = addr->Next) {
info = g_malloc0(sizeof(*info));
if (cur_item == NULL) {
head = cur_item = info;
} else {
cur_item->next = info;
cur_item = info;
}
info->value = g_malloc0(sizeof(*info->value));
info->value->name = guest_wctomb_dup(addr->FriendlyName);
if (addr->PhysicalAddressLength != 0) {
mac_addr = addr->PhysicalAddress;
info->value->hardware_address =
g_strdup_printf("%02x:%02x:%02x:%02x:%02x:%02x",
(int) mac_addr[0], (int) mac_addr[1],
(int) mac_addr[2], (int) mac_addr[3],
(int) mac_addr[4], (int) mac_addr[5]);
info->value->has_hardware_address = true;
}
head_addr = NULL;
cur_addr = NULL;
for (ip_addr = addr->FirstUnicastAddress;
ip_addr;
ip_addr = ip_addr->Next) {
addr_str = guest_addr_to_str(ip_addr, errp);
if (addr_str == NULL) {
continue;
}
address_item = g_malloc0(sizeof(*address_item));
if (!cur_addr) {
head_addr = cur_addr = address_item;
} else {
cur_addr->next = address_item;
cur_addr = address_item;
}
address_item->value = g_malloc0(sizeof(*address_item->value));
address_item->value->ip_address = addr_str;
address_item->value->prefix = guest_ip_prefix(ip_addr);
if (ip_addr->Address.lpSockaddr->sa_family == AF_INET) {
address_item->value->ip_address_type =
GUEST_IP_ADDRESS_TYPE_IPV4;
} else if (ip_addr->Address.lpSockaddr->sa_family == AF_INET6) {
address_item->value->ip_address_type =
GUEST_IP_ADDRESS_TYPE_IPV6;
}
}
if (head_addr) {
info->value->has_ip_addresses = true;
info->value->ip_addresses = head_addr;
}
if (!info->value->has_statistics) {
interface_stat = g_malloc0(sizeof(*interface_stat));
if (guest_get_network_stats(addr->AdapterName,
interface_stat) == -1) {
info->value->has_statistics = false;
g_free(interface_stat);
} else {
info->value->statistics = interface_stat;
info->value->has_statistics = true;
}
}
}
WSACleanup();
out:
g_free(adptr_addrs);
return head;
}
int64_t qmp_guest_get_time(Error **errp)
{
SYSTEMTIME ts = {0};
FILETIME tf;
GetSystemTime(&ts);
if (ts.wYear < 1601 || ts.wYear > 30827) {
error_setg(errp, "Failed to get time");
return -1;
}
if (!SystemTimeToFileTime(&ts, &tf)) {
error_setg(errp, "Failed to convert system time: %d", (int)GetLastError());
return -1;
}
return ((((int64_t)tf.dwHighDateTime << 32) | tf.dwLowDateTime)
- W32_FT_OFFSET) * 100;
}
void qmp_guest_set_time(bool has_time, int64_t time_ns, Error **errp)
{
Error *local_err = NULL;
SYSTEMTIME ts;
FILETIME tf;
LONGLONG time;
if (!has_time) {
/* Unfortunately, Windows libraries don't provide an easy way to access
* RTC yet:
*
* https://msdn.microsoft.com/en-us/library/aa908981.aspx
*
* Instead, a workaround is to use the Windows win32tm command to
* resync the time using the Windows Time service.
*/
LPVOID msg_buffer;
DWORD ret_flags;
HRESULT hr = system("w32tm /resync /nowait");
if (GetLastError() != 0) {
strerror_s((LPTSTR) & msg_buffer, 0, errno);
error_setg(errp, "system(...) failed: %s", (LPCTSTR)msg_buffer);
} else if (hr != 0) {
if (hr == HRESULT_FROM_WIN32(ERROR_SERVICE_NOT_ACTIVE)) {
error_setg(errp, "Windows Time service not running on the "
"guest");
} else {
if (!FormatMessage(FORMAT_MESSAGE_ALLOCATE_BUFFER |
FORMAT_MESSAGE_FROM_SYSTEM |
FORMAT_MESSAGE_IGNORE_INSERTS, NULL,
(DWORD)hr, MAKELANGID(LANG_NEUTRAL,
SUBLANG_DEFAULT), (LPTSTR) & msg_buffer, 0,
NULL)) {
error_setg(errp, "w32tm failed with error (0x%lx), couldn'"
"t retrieve error message", hr);
} else {
error_setg(errp, "w32tm failed with error (0x%lx): %s", hr,
(LPCTSTR)msg_buffer);
LocalFree(msg_buffer);
}
}
} else if (!InternetGetConnectedState(&ret_flags, 0)) {
error_setg(errp, "No internet connection on guest, sync not "
"accurate");
}
return;
}
/* Validate time passed by user. */
if (time_ns < 0 || time_ns / 100 > INT64_MAX - W32_FT_OFFSET) {
error_setg(errp, "Time %" PRId64 "is invalid", time_ns);
return;
}
time = time_ns / 100 + W32_FT_OFFSET;
tf.dwLowDateTime = (DWORD) time;
tf.dwHighDateTime = (DWORD) (time >> 32);
if (!FileTimeToSystemTime(&tf, &ts)) {
error_setg(errp, "Failed to convert system time %d",
(int)GetLastError());
return;
}
acquire_privilege(SE_SYSTEMTIME_NAME, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
if (!SetSystemTime(&ts)) {
error_setg(errp, "Failed to set time to guest: %d", (int)GetLastError());
return;
}
}
GuestLogicalProcessorList *qmp_guest_get_vcpus(Error **errp)
{
PSYSTEM_LOGICAL_PROCESSOR_INFORMATION pslpi, ptr;
DWORD length;
GuestLogicalProcessorList *head, **link;
Error *local_err = NULL;
int64_t current;
ptr = pslpi = NULL;
length = 0;
current = 0;
head = NULL;
link = &head;
if ((GetLogicalProcessorInformation(pslpi, &length) == FALSE) &&
(GetLastError() == ERROR_INSUFFICIENT_BUFFER) &&
(length > sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION))) {
ptr = pslpi = g_malloc0(length);
if (GetLogicalProcessorInformation(pslpi, &length) == FALSE) {
error_setg(&local_err, "Failed to get processor information: %d",
(int)GetLastError());
}
} else {
error_setg(&local_err,
"Failed to get processor information buffer length: %d",
(int)GetLastError());
}
while ((local_err == NULL) && (length > 0)) {
if (pslpi->Relationship == RelationProcessorCore) {
ULONG_PTR cpu_bits = pslpi->ProcessorMask;
while (cpu_bits > 0) {
if (!!(cpu_bits & 1)) {
GuestLogicalProcessor *vcpu;
GuestLogicalProcessorList *entry;
vcpu = g_malloc0(sizeof *vcpu);
vcpu->logical_id = current++;
vcpu->online = true;
vcpu->has_can_offline = true;
entry = g_malloc0(sizeof *entry);
entry->value = vcpu;
*link = entry;
link = &entry->next;
}
cpu_bits >>= 1;
}
}
length -= sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
pslpi++; /* next entry */
}
g_free(ptr);
if (local_err == NULL) {
if (head != NULL) {
return head;
}
/* there's no guest with zero VCPUs */
error_setg(&local_err, "Guest reported zero VCPUs");
}
qapi_free_GuestLogicalProcessorList(head);
error_propagate(errp, local_err);
return NULL;
}
int64_t qmp_guest_set_vcpus(GuestLogicalProcessorList *vcpus, Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
return -1;
}
static gchar *
get_net_error_message(gint error)
{
HMODULE module = NULL;
gchar *retval = NULL;
wchar_t *msg = NULL;
int flags;
size_t nchars;
flags = FORMAT_MESSAGE_ALLOCATE_BUFFER |
FORMAT_MESSAGE_IGNORE_INSERTS |
FORMAT_MESSAGE_FROM_SYSTEM;
if (error >= NERR_BASE && error <= MAX_NERR) {
module = LoadLibraryExW(L"netmsg.dll", NULL, LOAD_LIBRARY_AS_DATAFILE);
if (module != NULL) {
flags |= FORMAT_MESSAGE_FROM_HMODULE;
}
}
FormatMessageW(flags, module, error, 0, (LPWSTR)&msg, 0, NULL);
if (msg != NULL) {
nchars = wcslen(msg);
if (nchars >= 2 &&
msg[nchars - 1] == L'\n' &&
msg[nchars - 2] == L'\r') {
msg[nchars - 2] = L'\0';
}
retval = g_utf16_to_utf8(msg, -1, NULL, NULL, NULL);
LocalFree(msg);
}
if (module != NULL) {
FreeLibrary(module);
}
return retval;
}
void qmp_guest_set_user_password(const char *username,
const char *password,
bool crypted,
Error **errp)
{
NET_API_STATUS nas;
char *rawpasswddata = NULL;
size_t rawpasswdlen;
wchar_t *user = NULL, *wpass = NULL;
USER_INFO_1003 pi1003 = { 0, };
GError *gerr = NULL;
if (crypted) {
error_setg(errp, QERR_UNSUPPORTED);
return;
}
rawpasswddata = (char *)qbase64_decode(password, -1, &rawpasswdlen, errp);
if (!rawpasswddata) {
return;
}
rawpasswddata = g_renew(char, rawpasswddata, rawpasswdlen + 1);
rawpasswddata[rawpasswdlen] = '\0';
user = g_utf8_to_utf16(username, -1, NULL, NULL, &gerr);
if (!user) {
goto done;
}
wpass = g_utf8_to_utf16(rawpasswddata, -1, NULL, NULL, &gerr);
if (!wpass) {
goto done;
}
pi1003.usri1003_password = <PASSWORD>;
nas = NetUserSetInfo(NULL, user,
1003, (LPBYTE)&pi1003,
NULL);
if (nas != NERR_Success) {
gchar *msg = get_net_error_message(nas);
error_setg(errp, "failed to set password: %s", msg);
g_free(msg);
}
done:
if (gerr) {
error_setg(errp, QERR_QGA_COMMAND_FAILED, gerr->message);
g_error_free(gerr);
}
g_free(user);
g_free(wpass);
g_free(rawpasswddata);
}
GuestMemoryBlockList *qmp_guest_get_memory_blocks(Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
return NULL;
}
GuestMemoryBlockResponseList *
qmp_guest_set_memory_blocks(GuestMemoryBlockList *mem_blks, Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
return NULL;
}
GuestMemoryBlockInfo *qmp_guest_get_memory_block_info(Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
return NULL;
}
/* add unsupported commands to the blacklist */
GList *ga_command_blacklist_init(GList *blacklist)
{
const char *list_unsupported[] = {
"guest-suspend-hybrid",
"guest-set-vcpus",
"guest-get-memory-blocks", "guest-set-memory-blocks",
"guest-get-memory-block-size",
NULL};
char **p = (char **)list_unsupported;
while (*p) {
blacklist = g_list_append(blacklist, g_strdup(*p++));
}
if (!vss_init(true)) {
g_debug("vss_init failed, vss commands are going to be disabled");
const char *list[] = {
"guest-get-fsinfo", "guest-fsfreeze-status",
"guest-fsfreeze-freeze", "guest-fsfreeze-thaw", NULL};
p = (char **)list;
while (*p) {
blacklist = g_list_append(blacklist, g_strdup(*p++));
}
}
return blacklist;
}
/* register init/cleanup routines for stateful command groups */
void ga_command_state_init(GAState *s, GACommandState *cs)
{
if (!vss_initialized()) {
ga_command_state_add(cs, NULL, guest_fsfreeze_cleanup);
}
}
/* MINGW is missing two fields: IncomingFrames & OutgoingFrames */
typedef struct _GA_WTSINFOA {
WTS_CONNECTSTATE_CLASS State;
DWORD SessionId;
DWORD IncomingBytes;
DWORD OutgoingBytes;
DWORD IncomingFrames;
DWORD OutgoingFrames;
DWORD IncomingCompressedBytes;
DWORD OutgoingCompressedBy;
CHAR WinStationName[WINSTATIONNAME_LENGTH];
CHAR Domain[DOMAIN_LENGTH];
CHAR UserName[USERNAME_LENGTH + 1];
LARGE_INTEGER ConnectTime;
LARGE_INTEGER DisconnectTime;
LARGE_INTEGER LastInputTime;
LARGE_INTEGER LogonTime;
LARGE_INTEGER CurrentTime;
} GA_WTSINFOA;
GuestUserList *qmp_guest_get_users(Error **err)
{
#define QGA_NANOSECONDS 10000000
GHashTable *cache = NULL;
GuestUserList *head = NULL, *cur_item = NULL;
DWORD buffer_size = 0, count = 0, i = 0;
GA_WTSINFOA *info = NULL;
WTS_SESSION_INFOA *entries = NULL;
GuestUserList *item = NULL;
GuestUser *user = NULL;
gpointer value = NULL;
INT64 login = 0;
double login_time = 0;
cache = g_hash_table_new(g_str_hash, g_str_equal);
if (WTSEnumerateSessionsA(NULL, 0, 1, &entries, &count)) {
for (i = 0; i < count; ++i) {
buffer_size = 0;
info = NULL;
if (WTSQuerySessionInformationA(
NULL,
entries[i].SessionId,
WTSSessionInfo,
(LPSTR *)&info,
&buffer_size
)) {
if (strlen(info->UserName) == 0) {
WTSFreeMemory(info);
continue;
}
login = info->LogonTime.QuadPart;
login -= W32_FT_OFFSET;
login_time = ((double)login) / QGA_NANOSECONDS;
if (g_hash_table_contains(cache, info->UserName)) {
value = g_hash_table_lookup(cache, info->UserName);
user = (GuestUser *)value;
if (user->login_time > login_time) {
user->login_time = login_time;
}
} else {
item = g_new0(GuestUserList, 1);
item->value = g_new0(GuestUser, 1);
item->value->user = g_strdup(info->UserName);
item->value->domain = g_strdup(info->Domain);
item->value->has_domain = true;
item->value->login_time = login_time;
g_hash_table_add(cache, item->value->user);
if (!cur_item) {
head = cur_item = item;
} else {
cur_item->next = item;
cur_item = item;
}
}
}
WTSFreeMemory(info);
}
WTSFreeMemory(entries);
}
g_hash_table_destroy(cache);
return head;
}
typedef struct _ga_matrix_lookup_t {
int major;
int minor;
char const *version;
char const *version_id;
} ga_matrix_lookup_t;
static ga_matrix_lookup_t const WIN_VERSION_MATRIX[2][8] = {
{
/* Desktop editions */
{ 5, 0, "Microsoft Windows 2000", "2000"},
{ 5, 1, "Microsoft Windows XP", "xp"},
{ 6, 0, "Microsoft Windows Vista", "vista"},
{ 6, 1, "Microsoft Windows 7" "7"},
{ 6, 2, "Microsoft Windows 8", "8"},
{ 6, 3, "Microsoft Windows 8.1", "8.1"},
{10, 0, "Microsoft Windows 10", "10"},
{ 0, 0, 0}
},{
/* Server editions */
{ 5, 2, "Microsoft Windows Server 2003", "2003"},
{ 6, 0, "Microsoft Windows Server 2008", "2008"},
{ 6, 1, "Microsoft Windows Server 2008 R2", "2008r2"},
{ 6, 2, "Microsoft Windows Server 2012", "2012"},
{ 6, 3, "Microsoft Windows Server 2012 R2", "2012r2"},
{ 0, 0, 0},
{ 0, 0, 0},
{ 0, 0, 0}
}
};
typedef struct _ga_win_10_0_server_t {
int final_build;
char const *version;
char const *version_id;
} ga_win_10_0_server_t;
static ga_win_10_0_server_t const WIN_10_0_SERVER_VERSION_MATRIX[3] = {
{14393, "Microsoft Windows Server 2016", "2016"},
{17763, "Microsoft Windows Server 2019", "2019"},
{0, 0}
};
static void ga_get_win_version(RTL_OSVERSIONINFOEXW *info, Error **errp)
{
typedef NTSTATUS(WINAPI * rtl_get_version_t)(
RTL_OSVERSIONINFOEXW *os_version_info_ex);
info->dwOSVersionInfoSize = sizeof(RTL_OSVERSIONINFOEXW);
HMODULE module = GetModuleHandle("ntdll");
PVOID fun = GetProcAddress(module, "RtlGetVersion");
if (fun == NULL) {
error_setg(errp, QERR_QGA_COMMAND_FAILED,
"Failed to get address of RtlGetVersion");
return;
}
rtl_get_version_t rtl_get_version = (rtl_get_version_t)fun;
rtl_get_version(info);
return;
}
static char *ga_get_win_name(OSVERSIONINFOEXW const *os_version, bool id)
{
DWORD major = os_version->dwMajorVersion;
DWORD minor = os_version->dwMinorVersion;
DWORD build = os_version->dwBuildNumber;
int tbl_idx = (os_version->wProductType != VER_NT_WORKSTATION);
ga_matrix_lookup_t const *table = WIN_VERSION_MATRIX[tbl_idx];
ga_win_10_0_server_t const *win_10_0_table = WIN_10_0_SERVER_VERSION_MATRIX;
while (table->version != NULL) {
if (major == 10 && minor == 0 && tbl_idx) {
while (win_10_0_table->version != NULL) {
if (build <= win_10_0_table->final_build) {
if (id) {
return g_strdup(win_10_0_table->version_id);
} else {
return g_strdup(win_10_0_table->version);
}
}
win_10_0_table++;
}
} else if (major == table->major && minor == table->minor) {
if (id) {
return g_strdup(table->version_id);
} else {
return g_strdup(table->version);
}
}
++table;
}
slog("failed to lookup Windows version: major=%lu, minor=%lu",
major, minor);
return g_strdup("N/A");
}
static char *ga_get_win_product_name(Error **errp)
{
HKEY key = NULL;
DWORD size = 128;
char *result = g_malloc0(size);
LONG err = ERROR_SUCCESS;
err = RegOpenKeyA(HKEY_LOCAL_MACHINE,
"SOFTWARE\\Microsoft\\Windows NT\\CurrentVersion",
&key);
if (err != ERROR_SUCCESS) {
error_setg_win32(errp, err, "failed to open registry key");
goto fail;
}
err = RegQueryValueExA(key, "ProductName", NULL, NULL,
(LPBYTE)result, &size);
if (err == ERROR_MORE_DATA) {
slog("ProductName longer than expected (%lu bytes), retrying",
size);
g_free(result);
result = NULL;
if (size > 0) {
result = g_malloc0(size);
err = RegQueryValueExA(key, "ProductName", NULL, NULL,
(LPBYTE)result, &size);
}
}
if (err != ERROR_SUCCESS) {
error_setg_win32(errp, err, "failed to retrive ProductName");
goto fail;
}
return result;
fail:
g_free(result);
return NULL;
}
static char *ga_get_current_arch(void)
{
SYSTEM_INFO info;
GetNativeSystemInfo(&info);
char *result = NULL;
switch (info.wProcessorArchitecture) {
case PROCESSOR_ARCHITECTURE_AMD64:
result = g_strdup("x86_64");
break;
case PROCESSOR_ARCHITECTURE_ARM:
result = g_strdup("arm");
break;
case PROCESSOR_ARCHITECTURE_IA64:
result = g_strdup("ia64");
break;
case PROCESSOR_ARCHITECTURE_INTEL:
result = g_strdup("x86");
break;
case PROCESSOR_ARCHITECTURE_UNKNOWN:
default:
slog("unknown processor architecture 0x%0x",
info.wProcessorArchitecture);
result = g_strdup("unknown");
break;
}
return result;
}
GuestOSInfo *qmp_guest_get_osinfo(Error **errp)
{
Error *local_err = NULL;
OSVERSIONINFOEXW os_version = {0};
bool server;
char *product_name;
GuestOSInfo *info;
ga_get_win_version(&os_version, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return NULL;
}
server = os_version.wProductType != VER_NT_WORKSTATION;
product_name = ga_get_win_product_name(&local_err);
if (product_name == NULL) {
error_propagate(errp, local_err);
return NULL;
}
info = g_new0(GuestOSInfo, 1);
info->has_kernel_version = true;
info->kernel_version = g_strdup_printf("%lu.%lu",
os_version.dwMajorVersion,
os_version.dwMinorVersion);
info->has_kernel_release = true;
info->kernel_release = g_strdup_printf("%lu",
os_version.dwBuildNumber);
info->has_machine = true;
info->machine = ga_get_current_arch();
info->has_id = true;
info->id = g_strdup("mswindows");
info->has_name = true;
info->name = g_strdup("Microsoft Windows");
info->has_pretty_name = true;
info->pretty_name = product_name;
info->has_version = true;
info->version = ga_get_win_name(&os_version, false);
info->has_version_id = true;
info->version_id = ga_get_win_name(&os_version, true);
info->has_variant = true;
info->variant = g_strdup(server ? "server" : "client");
info->has_variant_id = true;
info->variant_id = g_strdup(server ? "server" : "client");
return info;
}
|
pmp-tool/PMP | src/qemu/src-pmp/linux-user/qemu.h | <gh_stars>1-10
#ifndef QEMU_H
#define QEMU_H
#include "hostdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#undef DEBUG_REMAP
#ifdef DEBUG_REMAP
#endif /* DEBUG_REMAP */
#include "exec/user/abitypes.h"
#include "exec/user/thunk.h"
#include "syscall_defs.h"
#include "target_syscall.h"
#include "exec/gdbstub.h"
#include "qemu/queue.h"
/* This is the size of the host kernel's sigset_t, needed where we make
* direct system calls that take a sigset_t pointer and a size.
*/
#define SIGSET_T_SIZE (_NSIG / 8)
/* This struct is used to hold certain information about the image.
* Basically, it replicates in user space what would be certain
* task_struct fields in the kernel
*/
struct image_info {
abi_ulong load_bias;
abi_ulong load_addr;
abi_ulong start_code;
abi_ulong end_code;
abi_ulong start_data;
abi_ulong end_data;
abi_ulong start_brk;
abi_ulong brk;
abi_ulong start_mmap;
abi_ulong start_stack;
abi_ulong stack_limit;
abi_ulong entry;
abi_ulong code_offset;
abi_ulong data_offset;
abi_ulong saved_auxv;
abi_ulong auxv_len;
abi_ulong arg_start;
abi_ulong arg_end;
abi_ulong arg_strings;
abi_ulong env_strings;
abi_ulong file_string;
uint32_t elf_flags;
int personality;
abi_ulong alignment;
/* The fields below are used in FDPIC mode. */
abi_ulong loadmap_addr;
uint16_t nsegs;
void *loadsegs;
abi_ulong pt_dynamic_addr;
abi_ulong interpreter_loadmap_addr;
abi_ulong interpreter_pt_dynamic_addr;
struct image_info *other_info;
#ifdef TARGET_MIPS
int fp_abi;
int interp_fp_abi;
#endif
};
#ifdef TARGET_I386
/* Information about the current linux thread */
struct vm86_saved_state {
uint32_t eax; /* return code */
uint32_t ebx;
uint32_t ecx;
uint32_t edx;
uint32_t esi;
uint32_t edi;
uint32_t ebp;
uint32_t esp;
uint32_t eflags;
uint32_t eip;
uint16_t cs, ss, ds, es, fs, gs;
};
#endif
#if defined(TARGET_ARM) && defined(TARGET_ABI32)
/* FPU emulator */
#include "nwfpe/fpa11.h"
#endif
#define MAX_SIGQUEUE_SIZE 1024
struct emulated_sigtable {
int pending; /* true if signal is pending */
target_siginfo_t info;
};
/* NOTE: we force a big alignment so that the stack stored after is
aligned too */
typedef struct TaskState {
pid_t ts_tid; /* tid (or pid) of this task */
#ifdef TARGET_ARM
# ifdef TARGET_ABI32
/* FPA state */
FPA11 fpa;
# endif
int swi_errno;
#endif
#if defined(TARGET_I386) && !defined(TARGET_X86_64)
abi_ulong target_v86;
struct vm86_saved_state vm86_saved_regs;
struct target_vm86plus_struct vm86plus;
uint32_t v86flags;
uint32_t v86mask;
#endif
abi_ulong child_tidptr;
#ifdef TARGET_M68K
int sim_syscalls;
abi_ulong tp_value;
#endif
#if defined(TARGET_ARM) || defined(TARGET_M68K)
/* Extra fields for semihosted binaries. */
abi_ulong heap_base;
abi_ulong heap_limit;
#endif
abi_ulong stack_base;
int used; /* non zero if used */
struct image_info *info;
struct linux_binprm *bprm;
struct emulated_sigtable sync_signal;
struct emulated_sigtable sigtab[TARGET_NSIG];
/* This thread's signal mask, as requested by the guest program.
* The actual signal mask of this thread may differ:
* + we don't let SIGSEGV and SIGBUS be blocked while running guest code
* + sometimes we block all signals to avoid races
*/
sigset_t signal_mask;
/* The signal mask imposed by a guest sigsuspend syscall, if we are
* currently in the middle of such a syscall
*/
sigset_t sigsuspend_mask;
/* Nonzero if we're leaving a sigsuspend and sigsuspend_mask is valid. */
int in_sigsuspend;
/* Nonzero if process_pending_signals() needs to do something (either
* handle a pending signal or unblock signals).
* This flag is written from a signal handler so should be accessed via
* the atomic_read() and atomic_set() functions. (It is not accessed
* from multiple threads.)
*/
int signal_pending;
} __attribute__((aligned(16))) TaskState;
extern char *exec_path;
void init_task_state(TaskState *ts);
void task_settid(TaskState *);
void stop_all_tasks(void);
extern const char *qemu_uname_release;
extern unsigned long mmap_min_addr;
/* ??? See if we can avoid exposing so much of the loader internals. */
/* Read a good amount of data initially, to hopefully get all the
program headers loaded. */
#define BPRM_BUF_SIZE 1024
/*
* This structure is used to hold the arguments that are
* used when loading binaries.
*/
struct linux_binprm {
char buf[BPRM_BUF_SIZE] __attribute__((aligned));
abi_ulong p;
int fd;
int e_uid, e_gid;
int argc, envc;
char **argv;
char **envp;
char * filename; /* Name of binary */
int (*core_dump)(int, const CPUArchState *); /* coredump routine */
};
void do_init_thread(struct target_pt_regs *regs, struct image_info *infop);
abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp,
abi_ulong stringp, int push_ptr);
int loader_exec(int fdexec, const char *filename, char **argv, char **envp,
struct target_pt_regs * regs, struct image_info *infop,
struct linux_binprm *);
/* Returns true if the image uses the FDPIC ABI. If this is the case,
* we have to provide some information (loadmap, pt_dynamic_info) such
* that the program can be relocated adequately. This is also useful
* when handling signals.
*/
int info_is_fdpic(struct image_info *info);
uint32_t get_elf_eflags(int fd);
int load_elf_binary(struct linux_binprm *bprm, struct image_info *info);
int load_flt_binary(struct linux_binprm *bprm, struct image_info *info);
abi_long memcpy_to_target(abi_ulong dest, const void *src,
unsigned long len);
void target_set_brk(abi_ulong new_brk);
abi_long do_brk(abi_ulong new_brk);
void syscall_init(void);
abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6, abi_long arg7,
abi_long arg8);
void gemu_log(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
extern __thread CPUState *thread_cpu;
void cpu_loop(CPUArchState *env);
const char *target_strerror(int err);
int get_osversion(void);
void init_qemu_uname_release(void);
void fork_start(void);
void fork_end(int child);
/* Creates the initial guest address space in the host memory space using
* the given host start address hint and size. The guest_start parameter
* specifies the start address of the guest space. guest_base will be the
* difference between the host start address computed by this function and
* guest_start. If fixed is specified, then the mapped address space must
* start at host_start. The real start address of the mapped memory space is
* returned or -1 if there was an error.
*/
unsigned long init_guest_space(unsigned long host_start,
unsigned long host_size,
unsigned long guest_start,
bool fixed);
#include "qemu/log.h"
/* safe_syscall.S */
/**
* safe_syscall:
* @int number: number of system call to make
* ...: arguments to the system call
*
* Call a system call if guest signal not pending.
* This has the same API as the libc syscall() function, except that it
* may return -1 with errno == TARGET_ERESTARTSYS if a signal was pending.
*
* Returns: the system call result, or -1 with an error code in errno
* (Errnos are host errnos; we rely on TARGET_ERESTARTSYS not clashing
* with any of the host errno values.)
*/
/* A guide to using safe_syscall() to handle interactions between guest
* syscalls and guest signals:
*
* Guest syscalls come in two flavours:
*
* (1) Non-interruptible syscalls
*
* These are guest syscalls that never get interrupted by signals and
* so never return EINTR. They can be implemented straightforwardly in
* QEMU: just make sure that if the implementation code has to make any
* blocking calls that those calls are retried if they return EINTR.
* It's also OK to implement these with safe_syscall, though it will be
* a little less efficient if a signal is delivered at the 'wrong' moment.
*
* Some non-interruptible syscalls need to be handled using block_signals()
* to block signals for the duration of the syscall. This mainly applies
* to code which needs to modify the data structures used by the
* host_signal_handler() function and the functions it calls, including
* all syscalls which change the thread's signal mask.
*
* (2) Interruptible syscalls
*
* These are guest syscalls that can be interrupted by signals and
* for which we need to either return EINTR or arrange for the guest
* syscall to be restarted. This category includes both syscalls which
* always restart (and in the kernel return -ERESTARTNOINTR), ones
* which only restart if there is no handler (kernel returns -ERESTARTNOHAND
* or -ERESTART_RESTARTBLOCK), and the most common kind which restart
* if the handler was registered with SA_RESTART (kernel returns
* -ERESTARTSYS). System calls which are only interruptible in some
* situations (like 'open') also need to be handled this way.
*
* Here it is important that the host syscall is made
* via this safe_syscall() function, and *not* via the host libc.
* If the host libc is used then the implementation will appear to work
* most of the time, but there will be a race condition where a
* signal could arrive just before we make the host syscall inside libc,
* and then then guest syscall will not correctly be interrupted.
* Instead the implementation of the guest syscall can use the safe_syscall
* function but otherwise just return the result or errno in the usual
* way; the main loop code will take care of restarting the syscall
* if appropriate.
*
* (If the implementation needs to make multiple host syscalls this is
* OK; any which might really block must be via safe_syscall(); for those
* which are only technically blocking (ie which we know in practice won't
* stay in the host kernel indefinitely) it's OK to use libc if necessary.
* You must be able to cope with backing out correctly if some safe_syscall
* you make in the implementation returns either -TARGET_ERESTARTSYS or
* EINTR though.)
*
* block_signals() cannot be used for interruptible syscalls.
*
*
* How and why the safe_syscall implementation works:
*
* The basic setup is that we make the host syscall via a known
* section of host native assembly. If a signal occurs, our signal
* handler checks the interrupted host PC against the addresse of that
* known section. If the PC is before or at the address of the syscall
* instruction then we change the PC to point at a "return
* -TARGET_ERESTARTSYS" code path instead, and then exit the signal handler
* (causing the safe_syscall() call to immediately return that value).
* Then in the main.c loop if we see this magic return value we adjust
* the guest PC to wind it back to before the system call, and invoke
* the guest signal handler as usual.
*
* This winding-back will happen in two cases:
* (1) signal came in just before we took the host syscall (a race);
* in this case we'll take the guest signal and have another go
* at the syscall afterwards, and this is indistinguishable for the
* guest from the timing having been different such that the guest
* signal really did win the race
* (2) signal came in while the host syscall was blocking, and the
* host kernel decided the syscall should be restarted;
* in this case we want to restart the guest syscall also, and so
* rewinding is the right thing. (Note that "restart" semantics mean
* "first call the signal handler, then reattempt the syscall".)
* The other situation to consider is when a signal came in while the
* host syscall was blocking, and the host kernel decided that the syscall
* should not be restarted; in this case QEMU's host signal handler will
* be invoked with the PC pointing just after the syscall instruction,
* with registers indicating an EINTR return; the special code in the
* handler will not kick in, and we will return EINTR to the guest as
* we should.
*
* Notice that we can leave the host kernel to make the decision for
* us about whether to do a restart of the syscall or not; we do not
* need to check SA_RESTART flags in QEMU or distinguish the various
* kinds of restartability.
*/
#ifdef HAVE_SAFE_SYSCALL
/* The core part of this function is implemented in assembly */
extern long safe_syscall_base(int *pending, long number, ...);
#define safe_syscall(...) \
({ \
long ret_; \
int *psp_ = &((TaskState *)thread_cpu->opaque)->signal_pending; \
ret_ = safe_syscall_base(psp_, __VA_ARGS__); \
if (is_error(ret_)) { \
errno = -ret_; \
ret_ = -1; \
} \
ret_; \
})
#else
/* Fallback for architectures which don't yet provide a safe-syscall assembly
* fragment; note that this is racy!
* This should go away when all host architectures have been updated.
*/
#define safe_syscall syscall
#endif
/* syscall.c */
int host_to_target_waitstatus(int status);
/* strace.c */
void print_syscall(int num,
abi_long arg1, abi_long arg2, abi_long arg3,
abi_long arg4, abi_long arg5, abi_long arg6);
void print_syscall_ret(int num, abi_long arg1);
/**
* print_taken_signal:
* @target_signum: target signal being taken
* @tinfo: target_siginfo_t which will be passed to the guest for the signal
*
* Print strace output indicating that this signal is being taken by the guest,
* in a format similar to:
* --- SIGSEGV {si_signo=SIGSEGV, si_code=SI_KERNEL, si_addr=0} ---
*/
void print_taken_signal(int target_signum, const target_siginfo_t *tinfo);
extern int do_strace;
/* signal.c */
void process_pending_signals(CPUArchState *cpu_env);
void signal_init(void);
int queue_signal(CPUArchState *env, int sig, int si_type,
target_siginfo_t *info);
void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info);
void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo);
int target_to_host_signal(int sig);
int host_to_target_signal(int sig);
long do_sigreturn(CPUArchState *env);
long do_rt_sigreturn(CPUArchState *env);
abi_long do_sigaltstack(abi_ulong uss_addr, abi_ulong uoss_addr, abi_ulong sp);
int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset);
abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx,
abi_ulong unew_ctx, abi_long ctx_size);
/**
* block_signals: block all signals while handling this guest syscall
*
* Block all signals, and arrange that the signal mask is returned to
* its correct value for the guest before we resume execution of guest code.
* If this function returns non-zero, then the caller should immediately
* return -TARGET_ERESTARTSYS to the main loop, which will take the pending
* signal and restart execution of the syscall.
* If block_signals() returns zero, then the caller can continue with
* emulation of the system call knowing that no signals can be taken
* (and therefore that no race conditions will result).
* This should only be called once, because if it is called a second time
* it will always return non-zero. (Think of it like a mutex that can't
* be recursively locked.)
* Signals will be unblocked again by process_pending_signals().
*
* Return value: non-zero if there was a pending signal, zero if not.
*/
int block_signals(void); /* Returns non zero if signal pending */
#ifdef TARGET_I386
/* vm86.c */
void save_v86_state(CPUX86State *env);
void handle_vm86_trap(CPUX86State *env, int trapno);
void handle_vm86_fault(CPUX86State *env);
int do_vm86(CPUX86State *env, long subfunction, abi_ulong v86_addr);
#elif defined(TARGET_SPARC64)
void sparc64_set_context(CPUSPARCState *env);
void sparc64_get_context(CPUSPARCState *env);
#endif
/* mmap.c */
int target_mprotect(abi_ulong start, abi_ulong len, int prot);
abi_long target_mmap(abi_ulong start, abi_ulong len, int prot,
int flags, int fd, abi_ulong offset);
int target_munmap(abi_ulong start, abi_ulong len);
abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size,
abi_ulong new_size, unsigned long flags,
abi_ulong new_addr);
extern unsigned long last_brk;
extern abi_ulong mmap_next_start;
abi_ulong mmap_find_vma(abi_ulong, abi_ulong);
void mmap_fork_start(void);
void mmap_fork_end(int child);
/* main.c */
extern unsigned long guest_stack_size;
/* user access */
#define VERIFY_READ 0
#define VERIFY_WRITE 1 /* implies read access */
static inline int access_ok(int type, abi_ulong addr, abi_ulong size)
{
return page_check_range((target_ulong)addr, size,
(type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0;
}
/* NOTE __get_user and __put_user use host pointers and don't check access.
These are usually used to access struct data members once the struct has
been locked - usually with lock_user_struct. */
/*
* Tricky points:
* - Use __builtin_choose_expr to avoid type promotion from ?:,
* - Invalid sizes result in a compile time error stemming from
* the fact that abort has no parameters.
* - It's easier to use the endian-specific unaligned load/store
* functions than host-endian unaligned load/store plus tswapN.
* - The pragmas are necessary only to silence a clang false-positive
* warning: see https://bugs.llvm.org/show_bug.cgi?id=39113 .
* - gcc has bugs in its _Pragma() support in some versions, eg
* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83256 -- so we only
* include the warning-suppression pragmas for clang
*/
#if defined(__clang__) && __has_warning("-Waddress-of-packed-member")
#define PRAGMA_DISABLE_PACKED_WARNING \
_Pragma("GCC diagnostic push"); \
_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"")
#define PRAGMA_REENABLE_PACKED_WARNING \
_Pragma("GCC diagnostic pop")
#else
#define PRAGMA_DISABLE_PACKED_WARNING
#define PRAGMA_REENABLE_PACKED_WARNING
#endif
#define __put_user_e(x, hptr, e) \
do { \
PRAGMA_DISABLE_PACKED_WARNING; \
(__builtin_choose_expr(sizeof(*(hptr)) == 1, stb_p, \
__builtin_choose_expr(sizeof(*(hptr)) == 2, stw_##e##_p, \
__builtin_choose_expr(sizeof(*(hptr)) == 4, stl_##e##_p, \
__builtin_choose_expr(sizeof(*(hptr)) == 8, stq_##e##_p, abort)))) \
((hptr), (x)), (void)0); \
PRAGMA_REENABLE_PACKED_WARNING; \
} while (0)
#define __get_user_e(x, hptr, e) \
do { \
PRAGMA_DISABLE_PACKED_WARNING; \
((x) = (typeof(*hptr))( \
__builtin_choose_expr(sizeof(*(hptr)) == 1, ldub_p, \
__builtin_choose_expr(sizeof(*(hptr)) == 2, lduw_##e##_p, \
__builtin_choose_expr(sizeof(*(hptr)) == 4, ldl_##e##_p, \
__builtin_choose_expr(sizeof(*(hptr)) == 8, ldq_##e##_p, abort)))) \
(hptr)), (void)0); \
PRAGMA_REENABLE_PACKED_WARNING; \
} while (0)
#ifdef TARGET_WORDS_BIGENDIAN
# define __put_user(x, hptr) __put_user_e(x, hptr, be)
# define __get_user(x, hptr) __get_user_e(x, hptr, be)
#else
# define __put_user(x, hptr) __put_user_e(x, hptr, le)
# define __get_user(x, hptr) __get_user_e(x, hptr, le)
#endif
/* put_user()/get_user() take a guest address and check access */
/* These are usually used to access an atomic data type, such as an int,
* that has been passed by address. These internally perform locking
* and unlocking on the data type.
*/
#define put_user(x, gaddr, target_type) \
({ \
abi_ulong __gaddr = (gaddr); \
target_type *__hptr; \
abi_long __ret = 0; \
if ((__hptr = lock_user(VERIFY_WRITE, __gaddr, sizeof(target_type), 0))) { \
__put_user((x), __hptr); \
unlock_user(__hptr, __gaddr, sizeof(target_type)); \
} else \
__ret = -TARGET_EFAULT; \
__ret; \
})
#define get_user(x, gaddr, target_type) \
({ \
abi_ulong __gaddr = (gaddr); \
target_type *__hptr; \
abi_long __ret = 0; \
if ((__hptr = lock_user(VERIFY_READ, __gaddr, sizeof(target_type), 1))) { \
__get_user((x), __hptr); \
unlock_user(__hptr, __gaddr, 0); \
} else { \
/* avoid warning */ \
(x) = 0; \
__ret = -TARGET_EFAULT; \
} \
__ret; \
})
#define put_user_ual(x, gaddr) put_user((x), (gaddr), abi_ulong)
#define put_user_sal(x, gaddr) put_user((x), (gaddr), abi_long)
#define put_user_u64(x, gaddr) put_user((x), (gaddr), uint64_t)
#define put_user_s64(x, gaddr) put_user((x), (gaddr), int64_t)
#define put_user_u32(x, gaddr) put_user((x), (gaddr), uint32_t)
#define put_user_s32(x, gaddr) put_user((x), (gaddr), int32_t)
#define put_user_u16(x, gaddr) put_user((x), (gaddr), uint16_t)
#define put_user_s16(x, gaddr) put_user((x), (gaddr), int16_t)
#define put_user_u8(x, gaddr) put_user((x), (gaddr), uint8_t)
#define put_user_s8(x, gaddr) put_user((x), (gaddr), int8_t)
#define get_user_ual(x, gaddr) get_user((x), (gaddr), abi_ulong)
#define get_user_sal(x, gaddr) get_user((x), (gaddr), abi_long)
#define get_user_u64(x, gaddr) get_user((x), (gaddr), uint64_t)
#define get_user_s64(x, gaddr) get_user((x), (gaddr), int64_t)
#define get_user_u32(x, gaddr) get_user((x), (gaddr), uint32_t)
#define get_user_s32(x, gaddr) get_user((x), (gaddr), int32_t)
#define get_user_u16(x, gaddr) get_user((x), (gaddr), uint16_t)
#define get_user_s16(x, gaddr) get_user((x), (gaddr), int16_t)
#define get_user_u8(x, gaddr) get_user((x), (gaddr), uint8_t)
#define get_user_s8(x, gaddr) get_user((x), (gaddr), int8_t)
/* copy_from_user() and copy_to_user() are usually used to copy data
* buffers between the target and host. These internally perform
* locking/unlocking of the memory.
*/
abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len);
abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len);
/* Functions for accessing guest memory. The tget and tput functions
read/write single values, byteswapping as necessary. The lock_user function
gets a pointer to a contiguous area of guest memory, but does not perform
any byteswapping. lock_user may return either a pointer to the guest
memory, or a temporary buffer. */
/* Lock an area of guest memory into the host. If copy is true then the
host area will have the same contents as the guest. */
static inline void *lock_user(int type, abi_ulong guest_addr, long len, int copy)
{
if (!access_ok(type, guest_addr, len))
return NULL;
#ifdef DEBUG_REMAP
{
void *addr;
addr = g_malloc(len);
if (copy)
memcpy(addr, g2h(guest_addr), len);
else
memset(addr, 0, len);
return addr;
}
#else
return g2h(guest_addr);
#endif
}
/* Unlock an area of guest memory. The first LEN bytes must be
flushed back to guest memory. host_ptr = NULL is explicitly
allowed and does nothing. */
static inline void unlock_user(void *host_ptr, abi_ulong guest_addr,
long len)
{
#ifdef DEBUG_REMAP
if (!host_ptr)
return;
if (host_ptr == g2h(guest_addr))
return;
if (len > 0)
memcpy(g2h(guest_addr), host_ptr, len);
g_free(host_ptr);
#endif
}
/* Return the length of a string in target memory or -TARGET_EFAULT if
access error. */
abi_long target_strlen(abi_ulong gaddr);
/* Like lock_user but for null terminated strings. */
static inline void *lock_user_string(abi_ulong guest_addr)
{
abi_long len;
len = target_strlen(guest_addr);
if (len < 0)
return NULL;
return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1);
}
/* Helper macros for locking/unlocking a target struct. */
#define lock_user_struct(type, host_ptr, guest_addr, copy) \
(host_ptr = lock_user(type, guest_addr, sizeof(*host_ptr), copy))
#define unlock_user_struct(host_ptr, guest_addr, copy) \
unlock_user(host_ptr, guest_addr, (copy) ? sizeof(*host_ptr) : 0)
#include <pthread.h>
static inline int is_error(abi_long ret)
{
return (abi_ulong)ret >= (abi_ulong)(-4096);
}
/**
* preexit_cleanup: housekeeping before the guest exits
*
* env: the CPU state
* code: the exit code
*/
void preexit_cleanup(CPUArchState *env, int code);
/* Include target-specific struct and function definitions;
* they may need access to the target-independent structures
* above, so include them last.
*/
#include "target_cpu.h"
#include "target_structs.h"
#endif /* QEMU_H */
|
pmp-tool/PMP | src/qemu/src-pmp/target/riscv/pmp.c | /*
* QEMU RISC-V PMP (Physical Memory Protection)
*
* Author: <NAME>, <EMAIL>
* <NAME>, <EMAIL>
*
* This provides a RISC-V Physical Memory Protection implementation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "cpu.h"
#include "qemu-common.h"
#ifndef CONFIG_USER_ONLY
#define RISCV_DEBUG_PMP 0
#define PMP_DEBUG(fmt, ...) \
do { \
if (RISCV_DEBUG_PMP) { \
qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
} \
} while (0)
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
/*
* Accessor method to extract address matching type 'a field' from cfg reg
*/
static inline uint8_t pmp_get_a_field(uint8_t cfg)
{
uint8_t a = cfg >> 3;
return a & 0x3;
}
/*
* Check whether a PMP is locked or not.
*/
static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
{
if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
return 1;
}
/* Top PMP has no 'next' to check */
if ((pmp_index + 1u) >= MAX_RISCV_PMPS) {
return 0;
}
/* In TOR mode, need to check the lock bit of the next pmp
* (if there is a next)
*/
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
(PMP_AMATCH_TOR == a_field)) {
return 1;
}
return 0;
}
/*
* Count the number of active rules.
*/
static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
{
return env->pmp_state.num_rules;
}
/*
* Accessor to get the cfg reg for a specific PMP/HART
*/
static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
{
if (pmp_index < MAX_RISCV_PMPS) {
return env->pmp_state.pmp[pmp_index].cfg_reg;
}
return 0;
}
/*
* Accessor to set the cfg reg for a specific PMP/HART
* Bounds checks and relevant lock bit.
*/
static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
if (!pmp_is_locked(env, pmp_index)) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - out of bounds\n");
}
}
static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
{
/*
aaaa...aaa0 8-byte NAPOT range
aaaa...aa01 16-byte NAPOT range
aaaa...a011 32-byte NAPOT range
...
aa01...1111 2^XLEN-byte NAPOT range
a011...1111 2^(XLEN+1)-byte NAPOT range
0111...1111 2^(XLEN+2)-byte NAPOT range
1111...1111 Reserved
*/
if (a == -1) {
*sa = 0u;
*ea = -1;
return;
} else {
target_ulong t1 = ctz64(~a);
target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
*sa = base;
*ea = base + range;
}
}
/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
* end address values.
* This function is called relatively infrequently whereas the check that
* an address is within a pmp rule is called often, so optimise that one
*/
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
{
int i;
env->pmp_state.num_rules = 0;
uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
target_ulong prev_addr = 0u;
target_ulong sa = 0u;
target_ulong ea = 0u;
if (pmp_index >= 1u) {
prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg;
}
switch (pmp_get_a_field(this_cfg)) {
case PMP_AMATCH_OFF:
sa = 0u;
ea = -1;
break;
case PMP_AMATCH_TOR:
sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
ea = (this_addr << 2) - 1u;
break;
case PMP_AMATCH_NA4:
sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
ea = (this_addr + 4u) - 1u;
break;
case PMP_AMATCH_NAPOT:
pmp_decode_napot(this_addr, &sa, &ea);
break;
default:
sa = 0u;
ea = 0u;
break;
}
env->pmp_state.addr[pmp_index].sa = sa;
env->pmp_state.addr[pmp_index].ea = ea;
for (i = 0; i < MAX_RISCV_PMPS; i++) {
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
if (PMP_AMATCH_OFF != a_field) {
env->pmp_state.num_rules++;
}
}
}
static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
{
int result = 0;
if ((addr >= env->pmp_state.addr[pmp_index].sa)
&& (addr <= env->pmp_state.addr[pmp_index].ea)) {
result = 1;
} else {
result = 0;
}
return result;
}
/*
* Public Interface
*/
/*
* Check if the address has required RWX privs to complete desired operation
*/
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs)
{
int i = 0;
int ret = -1;
target_ulong s = 0;
target_ulong e = 0;
pmp_priv_t allowed_privs = 0;
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
return true;
}
/* 1.10 draft priv spec states there is an implicit order
from low to high */
for (i = 0; i < MAX_RISCV_PMPS; i++) {
s = pmp_is_in_range(env, i, addr);
e = pmp_is_in_range(env, i, addr + size);
/* partially inside */
if ((s + e) == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"pmp violation - access is partially inside\n");
ret = 0;
break;
}
/* fully inside */
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
if ((s + e) == 2) {
if (PMP_AMATCH_OFF == a_field) {
return 1;
}
allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
if ((env->priv != PRV_M) || pmp_is_locked(env, i)) {
allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
}
if ((privs & allowed_privs) == privs) {
ret = 1;
break;
} else {
ret = 0;
break;
}
}
}
/* No rule matched */
if (ret == -1) {
if (env->priv == PRV_M) {
ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
* M-Mode access, the access succeeds */
} else {
ret = 0; /* Other modes are not allowed to succeed if they don't
* match a rule, but there are rules. We've checked for
* no rule earlier in this function. */
}
}
return ret == 1 ? true : false;
}
/*
* Handle a write to a pmpcfg CSP
*/
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
target_ulong val)
{
int i;
uint8_t cfg_val;
PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
env->mhartid, reg_index, val);
if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - incorrect address\n");
return;
}
for (i = 0; i < sizeof(target_ulong); i++) {
cfg_val = (val >> 8 * i) & 0xff;
pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
cfg_val);
}
}
/*
* Handle a read from a pmpcfg CSP
*/
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
{
int i;
target_ulong cfg_val = 0;
target_ulong val = 0;
for (i = 0; i < sizeof(target_ulong); i++) {
val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
cfg_val |= (val << (i * 8));
}
PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
env->mhartid, reg_index, cfg_val);
return cfg_val;
}
/*
* Handle a write to a pmpaddr CSP
*/
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val)
{
PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
env->mhartid, addr_index, val);
if (addr_index < MAX_RISCV_PMPS) {
if (!pmp_is_locked(env, addr_index)) {
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - out of bounds\n");
}
}
/*
* Handle a read from a pmpaddr CSP
*/
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
{
PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
env->mhartid, addr_index,
env->pmp_state.pmp[addr_index].addr_reg);
if (addr_index < MAX_RISCV_PMPS) {
return env->pmp_state.pmp[addr_index].addr_reg;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr read - out of bounds\n");
return 0;
}
}
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/roms/skiboot/platforms/astbmc/p9dsu.c | <gh_stars>1-10
/* Copyright 2017 Supermicro Inc.
* Copyright 2018 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <device.h>
#include <console.h>
#include <chip.h>
#include <ipmi.h>
#include <psi.h>
#include <npu-regs.h>
#include <opal-internal.h>
#include <cpu.h>
#include <timebase.h>
#include "astbmc.h"
static bool p9dsu_riser_found = false;
static const struct slot_table_entry p9dsu1u_phb0_0_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "UIO Slot1",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb0_1_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "UIO Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb0_2_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard LAN",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb0_3_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard SAS",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb0_4_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard BMC",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb0_5_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard USB",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb8_0_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot1",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb8_1_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO-R Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb8_2_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot3",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb8_3_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot4",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu1u_phb_table[] = {
{
.etype = st_phb,
.location = ST_LOC_PHB(0,0),
.children = p9dsu1u_phb0_0_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,1),
.children = p9dsu1u_phb0_1_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,2),
.children = p9dsu1u_phb0_2_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,3),
.children = p9dsu1u_phb0_3_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,4),
.children = p9dsu1u_phb0_4_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,5),
.children = p9dsu1u_phb0_5_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,0),
.children = p9dsu1u_phb8_0_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,1),
.children = p9dsu1u_phb8_1_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,2),
.children = p9dsu1u_phb8_2_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,3),
.children = p9dsu1u_phb8_3_slot,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb0_0_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "UIO Slot1",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb0_1_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "UIO Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb0_2_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard LAN",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb0_3_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard SAS",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb0_4_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard BMC",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb0_5_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard USB",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb8_0_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot1",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb8_1_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO-R Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb8_2_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot3",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb8_3_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot4",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb8_4_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot5",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2u_phb_table[] = {
{
.etype = st_phb,
.location = ST_LOC_PHB(0,0),
.children = p9dsu2u_phb0_0_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,1),
.children = p9dsu2u_phb0_1_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,2),
.children = p9dsu2u_phb0_2_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,3),
.children = p9dsu2u_phb0_3_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,4),
.children = p9dsu2u_phb0_4_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,5),
.children = p9dsu2u_phb0_5_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,0),
.children = p9dsu2u_phb8_0_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,1),
.children = p9dsu2u_phb8_1_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,2),
.children = p9dsu2u_phb8_2_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,3),
.children = p9dsu2u_phb8_3_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,4),
.children = p9dsu2u_phb8_4_slot,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_uio_plx_down[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0x1,0),
.name = "UIO Slot2",
.power_limit = 75,
},
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0x8,0),
.name = "PLX SWITCH UIO Slot2",
.power_limit = 75,
},
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0x9,0),
.name = "PLX DOWN LAN UIO Slot2",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_uio_plx_up[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.children = p9dsu2uess_uio_plx_down,
.name = "PLX UP UIO Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_wio_plx_down[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0x1,0),
.name = "WIO Slot3",
.power_limit = 75,
},
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0x8,0),
.name = "PLX SWITCH WIO Slot3",
.power_limit = 75,
},
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0x9,0),
.name = "WIO Slot3",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_wio_plx_up[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.children = p9dsu2uess_wio_plx_down,
.name = "PLX UP WIO Slot3",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb0_0_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "UIO Slot1",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb0_1_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.children = p9dsu2uess_uio_plx_up,
.name = "PLX UIO Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb0_2_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "UIO Slot3",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb0_3_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard SAS",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb0_4_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard BMC",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb0_5_slot[] = {
{
.etype = st_builtin_dev,
.location = ST_LOC_DEVFN(0,0),
.name = "Onboard USB",
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb8_0_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot1",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb8_1_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO-R Slot2",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb8_2_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.children = p9dsu2uess_wio_plx_up,
.name = "PLX WIO Slot3",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb8_3_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot4",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb8_4_slot[] = {
{
.etype = st_pluggable_slot,
.location = ST_LOC_DEVFN(0,0),
.name = "WIO Slot5",
.power_limit = 75,
},
{ .etype = st_end },
};
static const struct slot_table_entry p9dsu2uess_phb_table[] = {
{
.etype = st_phb,
.location = ST_LOC_PHB(0,0),
.children = p9dsu2uess_phb0_0_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,1),
.children = p9dsu2uess_phb0_1_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,2),
.children = p9dsu2uess_phb0_2_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,3),
.children = p9dsu2uess_phb0_3_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,4),
.children = p9dsu2uess_phb0_4_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(0,5),
.children = p9dsu2uess_phb0_5_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,0),
.children = p9dsu2uess_phb8_0_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,1),
.children = p9dsu2uess_phb8_1_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,2),
.children = p9dsu2uess_phb8_2_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,3),
.children = p9dsu2uess_phb8_3_slot,
},
{
.etype = st_phb,
.location = ST_LOC_PHB(8,4),
.children = p9dsu2uess_phb8_4_slot,
},
{ .etype = st_end },
};
/*
* HACK: Hostboot doesn't export the correct data for the system VPD EEPROM
* for this system. So we need to work around it here.
*/
static void p9dsu_dt_fixups(void)
{
struct dt_node *n = dt_find_by_path(dt_root,
"/xscom@603fc00000000/i2cm@a2000/i2c-bus@0/eeprom@50");
if (n) {
dt_check_del_prop(n, "compatible");
dt_add_property_string(n, "compatible", "atmel,24c256");
dt_check_del_prop(n, "label");
dt_add_property_string(n, "label", "system-vpd");
}
}
static bool p9dsu_probe(void)
{
if (!(dt_node_is_compatible(dt_root, "supermicro,p9dsu") ||
dt_node_is_compatible(dt_root, "supermicro,p9dsu1u") ||
dt_node_is_compatible(dt_root, "supermicro,p9dsu2u") ||
dt_node_is_compatible(dt_root, "supermicro,p9dsu2uess")))
return false;
p9dsu_riser_found = true;
/* Lot of common early inits here */
astbmc_early_init();
/* Setup UART for use by OPAL (Linux hvc) */
uart_set_console_policy(UART_CONSOLE_OPAL);
p9dsu_dt_fixups();
if (dt_node_is_compatible(dt_root, "supermicro,p9dsu1u")) {
prlog(PR_INFO, "Detected p9dsu1u variant\n");
slot_table_init(p9dsu1u_phb_table);
} else if (dt_node_is_compatible(dt_root, "supermicro,p9dsu2u")) {
prlog(PR_INFO, "Detected p9dsu2u variant\n");
slot_table_init(p9dsu2u_phb_table);
} else if (dt_node_is_compatible(dt_root, "supermicro,p9dsu2uess")) {
prlog(PR_INFO, "Detected p9dsu2uess variant\n");
slot_table_init(p9dsu2uess_phb_table);
} else {
/*
* else we need to ask the BMC what subtype we are, but we need IPMI
* which we don't get until astbmc_init(), so we delay setting up the
* slot table until later.
*
* This only applies if you're using a Hostboot that doesn't do this
* for us.
*/
p9dsu_riser_found = false;
}
return true;
}
static void p9dsu_riser_query_complete(struct ipmi_msg *m)
{
u8 *riser_id = (u8*)m->user_data;
lwsync();
*riser_id = m->data[0];
ipmi_free_msg(m);
}
static void p9dsu_init(void)
{
u8 smc_riser_req[] = {0x03, 0x70, 0x01, 0x02};
struct ipmi_msg *ipmi_msg;
u8 riser_id = 0;
const char *p9dsu_variant;
int timeout_ms = 3000;
astbmc_init();
/*
* Now we have IPMI up and running we can ask the BMC for what p9dsu
* variant we are if Hostboot isn't the patched one that does this
* for us.
*/
if (!p9dsu_riser_found) {
ipmi_msg = ipmi_mkmsg(IPMI_DEFAULT_INTERFACE,
IPMI_CODE(IPMI_NETFN_APP, 0x52),
p9dsu_riser_query_complete,
&riser_id,
smc_riser_req, sizeof(smc_riser_req), 1);
ipmi_queue_msg(ipmi_msg);
while(riser_id==0 && timeout_ms > 0) {
time_wait_ms(10);
timeout_ms -= 10;
}
switch (riser_id) {
case 0x9:
p9dsu_variant = "supermicro,p9dsu1u";
slot_table_init(p9dsu1u_phb_table);
break;
case 0x19:
p9dsu_variant = "supermicro,p9dsu2u";
slot_table_init(p9dsu2u_phb_table);
break;
case 0x1D:
p9dsu_variant = "supermicro,p9dsu2uess";
slot_table_init(p9dsu2uess_phb_table);
break;
default:
prlog(PR_ERR, "Defaulting to p9dsu2uess\n");
p9dsu_variant = "supermicro,p9dsu2uess";
slot_table_init(p9dsu2uess_phb_table);
break;
}
prlog(PR_INFO,"Detected %s variant via IPMI\n", p9dsu_variant);
dt_check_del_prop(dt_root, "compatible");
dt_add_property_strings(dt_root, "compatible", "ibm,powernv",
"supermicro,p9dsu", p9dsu_variant);
}
}
static const struct bmc_sw_config bmc_sw_smc = {
.ipmi_oem_partial_add_esel = IPMI_CODE(0x3a, 0xf0),
.ipmi_oem_hiomap_cmd = IPMI_CODE(0x3a, 0x5a),
};
/* Provided by <NAME> (SMC) */
const struct bmc_hw_config p9dsu_bmc_hw = {
.scu_revision_id = 0x04030303,
.mcr_configuration = 0x11000756,
.mcr_scu_mpll = 0x000071c1,
.mcr_scu_strap = 0x00000000,
};
static const struct bmc_platform bmc_plat_ast2500_smc = {
.name = "SMC",
.hw = &p9dsu_bmc_hw,
.sw = &bmc_sw_smc,
};
DECLARE_PLATFORM(p9dsu1u) = {
.name = "p9dsu",
.probe = p9dsu_probe,
.init = p9dsu_init,
.start_preload_resource = flash_start_preload_resource,
.resource_loaded = flash_resource_loaded,
.bmc = &bmc_plat_ast2500_smc,
.pci_get_slot_info = slot_table_get_slot_info,
.cec_power_down = astbmc_ipmi_power_down,
.cec_reboot = astbmc_ipmi_reboot,
.elog_commit = ipmi_elog_commit,
.exit = ipmi_wdt_final_reset,
.terminate = ipmi_terminate,
};
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-divide/test_msa_div_u_b.c | <gh_stars>1-10
/*
* Test program for MSA instruction DIV_U.B
*
* Copyright (C) 2018 Wave Computing, Inc.
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs.h"
#include "../../../../include/test_utils.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "DIV_U.B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0x0101010101010101ULL, 0x0101010101010101ULL, }, /* 0 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0303030303030303ULL, 0x0303030303030303ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0505050505050505ULL, 0x0505050505050505ULL, },
{ 0x0101040101040101ULL, 0x0401010401010401ULL, },
{ 0x0902010902010902ULL, 0x0109020109020109ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 8 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 16 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0202020202020202ULL, 0x0202020202020202ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0303030303030303ULL, 0x0303030303030303ULL, },
{ 0x0001030001030001ULL, 0x0300010300010300ULL, },
{ 0x0601000601000601ULL, 0x0006010006010006ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 24 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0000010000010000ULL, 0x0100000100000100ULL, },
{ 0x0300000300000300ULL, 0x0003000003000003ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 32 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0202020202020202ULL, 0x0202020202020202ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0404040404040404ULL, 0x0404040404040404ULL, },
{ 0x0001030001030001ULL, 0x0300010300010300ULL, },
{ 0x0701010701010701ULL, 0x0107010107010107ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 40 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0100000100000100ULL, 0x0001000001000001ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 48 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0100000100000100ULL, 0x0001000001000001ULL, },
{ 0x0201000201000201ULL, 0x0002010002010002ULL, },
{ 0x0100000100000100ULL, 0x0001000001000001ULL, },
{ 0x0402010402010402ULL, 0x0104020104020104ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0801000801000801ULL, 0x0008010008010008ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, }, /* 56 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0000010000010000ULL, 0x0100000100000100ULL, },
{ 0x0001020001020001ULL, 0x0200010200010200ULL, },
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x0002030002030002ULL, 0x0300020300020300ULL, },
{ 0x0000030000030000ULL, 0x0300000300000300ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, }, /* 64 */
{ 0x0000ff0200000008ULL, 0x040000030c010200ULL, },
{ 0x0001010100000000ULL, 0x0100000001020400ULL, },
{ 0x01010a0200020000ULL, 0x0000000001010000ULL, },
{ 0x0101000001010200ULL, 0x0002110000000015ULL, },
{ 0x0101ff0101010101ULL, 0x0101010101010101ULL, },
{ 0x0102000000000100ULL, 0x000100000001020cULL, },
{ 0x0202000100030000ULL, 0x0001010000000001ULL, },
{ 0x0100000004020102ULL, 0x0002120200000001ULL, }, /* 72 */
{ 0x0000ff0102010010ULL, 0x0200010908000000ULL, },
{ 0x0101010101010101ULL, 0x0101010101010101ULL, },
{ 0x0101070201040001ULL, 0x0000010101000000ULL, },
{ 0x0000000002000201ULL, 0x01020c020000010dULL, },
{ 0x0000ff0001000109ULL, 0x0700000808010200ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_DIV_U_B(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_DIV_U_B(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/xtensa/mx_pic.c | <reponame>pmp-tool/PMP
/*
* Copyright (c) 2013 - 2019, <NAME>, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/xtensa/mx_pic.h"
#include "qemu/log.h"
#define MX_MAX_CPU 32
#define MX_MAX_IRQ 32
#define MIROUT 0x0
#define MIPICAUSE 0x100
#define MIPISET 0x140
#define MIENG 0x180
#define MIENGSET 0x184
#define MIASG 0x188
#define MIASGSET 0x18c
#define MIPIPART 0x190
#define SYSCFGID 0x1a0
#define MPSCORE 0x200
#define CCON 0x220
struct XtensaMxPic {
unsigned n_cpu;
unsigned n_irq;
uint32_t ext_irq_state;
uint32_t mieng;
uint32_t miasg;
uint32_t mirout[MX_MAX_IRQ];
uint32_t mipipart;
uint32_t runstall;
qemu_irq *irq_inputs;
struct XtensaMxPicCpu {
XtensaMxPic *mx;
qemu_irq *irq;
qemu_irq runstall;
uint32_t mipicause;
uint32_t mirout_cache;
uint32_t irq_state_cache;
uint32_t ccon;
MemoryRegion reg;
} cpu[MX_MAX_CPU];
};
static uint64_t xtensa_mx_pic_ext_reg_read(void *opaque, hwaddr offset,
unsigned size)
{
struct XtensaMxPicCpu *mx_cpu = opaque;
struct XtensaMxPic *mx = mx_cpu->mx;
if (offset < MIROUT + MX_MAX_IRQ) {
return mx->mirout[offset - MIROUT];
} else if (offset >= MIPICAUSE && offset < MIPICAUSE + MX_MAX_CPU) {
return mx->cpu[offset - MIPICAUSE].mipicause;
} else {
switch (offset) {
case MIENG:
return mx->mieng;
case MIASG:
return mx->miasg;
case MIPIPART:
return mx->mipipart;
case SYSCFGID:
return ((mx->n_cpu - 1) << 18) | (mx_cpu - mx->cpu);
case MPSCORE:
return mx->runstall;
case CCON:
return mx_cpu->ccon;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"unknown RER in MX PIC range: 0x%08x\n",
(uint32_t)offset);
return 0;
}
}
}
static uint32_t xtensa_mx_pic_get_ipi_for_cpu(const XtensaMxPic *mx,
unsigned cpu)
{
uint32_t mipicause = mx->cpu[cpu].mipicause;
uint32_t mipipart = mx->mipipart;
return (((mipicause & 1) << (mipipart & 3)) |
((mipicause & 0x000e) != 0) << ((mipipart >> 2) & 3) |
((mipicause & 0x00f0) != 0) << ((mipipart >> 4) & 3) |
((mipicause & 0xff00) != 0) << ((mipipart >> 6) & 3)) & 0x7;
}
static uint32_t xtensa_mx_pic_get_ext_irq_for_cpu(const XtensaMxPic *mx,
unsigned cpu)
{
return ((((mx->ext_irq_state & mx->mieng) | mx->miasg) &
mx->cpu[cpu].mirout_cache) << 2) |
xtensa_mx_pic_get_ipi_for_cpu(mx, cpu);
}
static void xtensa_mx_pic_update_cpu(XtensaMxPic *mx, unsigned cpu)
{
uint32_t irq = xtensa_mx_pic_get_ext_irq_for_cpu(mx, cpu);
uint32_t changed_irq = mx->cpu[cpu].irq_state_cache ^ irq;
unsigned i;
qemu_log_mask(CPU_LOG_INT, "%s: CPU %d, irq: %08x, changed_irq: %08x\n",
__func__, cpu, irq, changed_irq);
mx->cpu[cpu].irq_state_cache = irq;
for (i = 0; changed_irq; ++i) {
uint32_t mask = 1u << i;
if (changed_irq & mask) {
changed_irq ^= mask;
qemu_set_irq(mx->cpu[cpu].irq[i], irq & mask);
}
}
}
static void xtensa_mx_pic_update_all(XtensaMxPic *mx)
{
unsigned cpu;
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
xtensa_mx_pic_update_cpu(mx, cpu);
}
}
static void xtensa_mx_pic_ext_reg_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
struct XtensaMxPicCpu *mx_cpu = opaque;
struct XtensaMxPic *mx = mx_cpu->mx;
unsigned cpu;
if (offset < MIROUT + mx->n_irq) {
mx->mirout[offset - MIROUT] = v;
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
uint32_t mask = 1u << (offset - MIROUT);
if (!(mx->cpu[cpu].mirout_cache & mask) != !(v & (1u << cpu))) {
mx->cpu[cpu].mirout_cache ^= mask;
xtensa_mx_pic_update_cpu(mx, cpu);
}
}
} else if (offset >= MIPICAUSE && offset < MIPICAUSE + mx->n_cpu) {
cpu = offset - MIPICAUSE;
mx->cpu[cpu].mipicause &= ~v;
xtensa_mx_pic_update_cpu(mx, cpu);
} else if (offset >= MIPISET && offset < MIPISET + 16) {
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
if (v & (1u << cpu)) {
mx->cpu[cpu].mipicause |= 1u << (offset - MIPISET);
xtensa_mx_pic_update_cpu(mx, cpu);
}
}
} else {
uint32_t change = 0;
uint32_t oldv, newv;
const char *name = "???";
switch (offset) {
case MIENG:
change = mx->mieng & v;
oldv = mx->mieng;
mx->mieng &= ~v;
newv = mx->mieng;
name = "MIENG";
break;
case MIENGSET:
change = ~mx->mieng & v;
oldv = mx->mieng;
mx->mieng |= v;
newv = mx->mieng;
name = "MIENG";
break;
case MIASG:
change = mx->miasg & v;
oldv = mx->miasg;
mx->miasg &= ~v;
newv = mx->miasg;
name = "MIASG";
break;
case MIASGSET:
change = ~mx->miasg & v;
oldv = mx->miasg;
mx->miasg |= v;
newv = mx->miasg;
name = "MIASG";
break;
case MIPIPART:
change = mx->mipipart ^ v;
oldv = mx->mipipart;
mx->mipipart = v;
newv = mx->mipipart;
name = "MIPIPART";
break;
case MPSCORE:
change = mx->runstall ^ v;
oldv = mx->runstall;
mx->runstall = v;
newv = mx->runstall;
name = "RUNSTALL";
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
if (change & (1u << cpu)) {
qemu_set_irq(mx->cpu[cpu].runstall, v & (1u << cpu));
}
}
break;
case CCON:
mx_cpu->ccon = v & 0x1;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"unknown WER in MX PIC range: 0x%08x = 0x%08x\n",
(uint32_t)offset, (uint32_t)v);
break;
}
if (change) {
qemu_log_mask(CPU_LOG_INT,
"%s: %s changed by CPU %d: %08x -> %08x\n",
__func__, name, (int)(mx_cpu - mx->cpu),
oldv, newv);
xtensa_mx_pic_update_all(mx);
}
}
}
static const MemoryRegionOps xtensa_mx_pic_ops = {
.read = xtensa_mx_pic_ext_reg_read,
.write = xtensa_mx_pic_ext_reg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.unaligned = true,
},
};
MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx,
qemu_irq *irq,
qemu_irq runstall)
{
struct XtensaMxPicCpu *mx_cpu = mx->cpu + mx->n_cpu;
mx_cpu->mx = mx;
mx_cpu->irq = irq;
mx_cpu->runstall = runstall;
memory_region_init_io(&mx_cpu->reg, NULL, &xtensa_mx_pic_ops, mx_cpu,
"mx_pic", 0x280);
++mx->n_cpu;
return &mx_cpu->reg;
}
static void xtensa_mx_pic_set_irq(void *opaque, int irq, int active)
{
XtensaMxPic *mx = opaque;
if (irq < mx->n_irq) {
uint32_t old_irq_state = mx->ext_irq_state;
if (active) {
mx->ext_irq_state |= 1u << irq;
} else {
mx->ext_irq_state &= ~(1u << irq);
}
if (old_irq_state != mx->ext_irq_state) {
qemu_log_mask(CPU_LOG_INT,
"%s: IRQ %d, active: %d, ext_irq_state: %08x -> %08x\n",
__func__, irq, active,
old_irq_state, mx->ext_irq_state);
xtensa_mx_pic_update_all(mx);
}
} else {
qemu_log_mask(LOG_GUEST_ERROR, "%s: IRQ %d out of range\n",
__func__, irq);
}
}
XtensaMxPic *xtensa_mx_pic_init(unsigned n_irq)
{
XtensaMxPic *mx = calloc(1, sizeof(XtensaMxPic));
mx->n_irq = n_irq + 1;
mx->irq_inputs = qemu_allocate_irqs(xtensa_mx_pic_set_irq, mx,
mx->n_irq);
return mx;
}
void xtensa_mx_pic_reset(void *opaque)
{
XtensaMxPic *mx = opaque;
unsigned i;
mx->ext_irq_state = 0;
mx->mieng = mx->n_irq < 32 ? (1u << mx->n_irq) - 1 : ~0u;
mx->miasg = 0;
mx->mipipart = 0;
for (i = 0; i < mx->n_irq; ++i) {
mx->mirout[i] = 1;
}
for (i = 0; i < mx->n_cpu; ++i) {
mx->cpu[i].mipicause = 0;
mx->cpu[i].mirout_cache = i ? 0 : mx->mieng;
mx->cpu[i].irq_state_cache = 0;
mx->cpu[i].ccon = 0;
}
mx->runstall = (1u << mx->n_cpu) - 2;
for (i = 0; i < mx->n_cpu; ++i) {
qemu_set_irq(mx->cpu[i].runstall, i > 0);
}
}
qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx)
{
return mx->irq_inputs + 1;
}
|
pmp-tool/PMP | src/qemu/src-pmp/target/riscv/translate.c | <reponame>pmp-tool/PMP
/*
* RISC-V emulation for qemu: main translation routines.
*
* Copyright (c) 2016-2017 <NAME>, <EMAIL>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "tcg-op.h"
#include "disas/disas.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
#include "exec/log.h"
#include "instmap.h"
/* global register indices */
static TCGv cpu_gpr[32], cpu_pc;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
#include "exec/gen-icount.h"
typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
no previous fp instruction. Note that we exit the TB when writing
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
} DisasContext;
#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
[0 ... 7] = -1,
[0] = MO_SB,
[1] = MO_TESW,
[2] = MO_TESL,
[4] = MO_UB,
[5] = MO_TEUW,
#ifdef TARGET_RISCV64
[3] = MO_TEQ,
[6] = MO_TEUL,
#endif
};
#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
#define CASE_OP_32_64(X) case X
#endif
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
return ctx->misa & ext;
}
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
TCGv_i32 helper_tmp = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
TCGv_i32 helper_tmp = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception_debug(void)
{
TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
}
static void gen_exception_illegal(DisasContext *ctx)
{
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
}
static void gen_exception_inst_addr_mis(DisasContext *ctx)
{
generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
if (unlikely(ctx->base.singlestep_enabled)) {
return false;
}
#ifndef CONFIG_USER_ONLY
return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (use_goto_tb(ctx, dest)) {
/* chaining is only allowed when the jump is to the same page */
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
if (ctx->base.singlestep_enabled) {
gen_exception_debug();
} else {
tcg_gen_lookup_and_goto_ptr();
}
}
}
/* Wrapper for getting reg values - need to check of reg is zero since
* cpu_gpr[0] is not actually allocated
*/
static inline void gen_get_gpr(TCGv t, int reg_num)
{
if (reg_num == 0) {
tcg_gen_movi_tl(t, 0);
} else {
tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
}
}
/* Wrapper for setting reg values - need to check of reg is zero since
* cpu_gpr[0] is not actually allocated. this is more for safety purposes,
* since we usually avoid calling the OP_TYPE_gen function if we see a write to
* $zero
*/
static inline void gen_set_gpr(int reg_num_dst, TCGv t)
{
if (reg_num_dst != 0) {
tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
}
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv rl = tcg_temp_new();
TCGv rh = tcg_temp_new();
tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
/* fix up for one negative */
tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
tcg_gen_and_tl(rl, rl, arg2);
tcg_gen_sub_tl(ret, rh, rl);
tcg_temp_free(rl);
tcg_temp_free(rh);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, cond2, zeroreg, resultopt1;
/*
* Handle by altering args to tcg_gen_div to produce req'd results:
* For overflow: want source1 in source1 and 1 in source2
* For div by zero: want -1 in source1 and 1 in source2 -> -1 result
*/
cond1 = tcg_temp_new();
cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
((target_ulong)1) << (TARGET_LONG_BITS - 1));
tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
/* if div by zero, set source1 to -1, otherwise don't change */
tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
resultopt1);
/* if overflow or div by zero, set source2 to 1, else don't change */
tcg_gen_or_tl(cond1, cond1, cond2);
tcg_gen_movi_tl(resultopt1, (target_ulong)1);
tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
resultopt1);
tcg_gen_div_tl(ret, source1, source2);
tcg_temp_free(cond1);
tcg_temp_free(cond2);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, zeroreg, resultopt1;
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
resultopt1);
tcg_gen_movi_tl(resultopt1, (target_ulong)1);
tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
resultopt1);
tcg_gen_divu_tl(ret, source1, source2);
tcg_temp_free(cond1);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, cond2, zeroreg, resultopt1;
cond1 = tcg_temp_new();
cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
tcg_gen_movi_tl(resultopt1, 1L);
tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
(target_ulong)1 << (TARGET_LONG_BITS - 1));
tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
/* if overflow or div by zero, set source2 to 1, else don't change */
tcg_gen_or_tl(cond2, cond1, cond2);
tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
resultopt1);
tcg_gen_rem_tl(resultopt1, source1, source2);
/* if div by zero, just return the original dividend */
tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
source1);
tcg_temp_free(cond1);
tcg_temp_free(cond2);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, zeroreg, resultopt1;
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
tcg_gen_movi_tl(resultopt1, (target_ulong)1);
tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
resultopt1);
tcg_gen_remu_tl(resultopt1, source1, source2);
/* if div by zero, just return the original dividend */
tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
source1);
tcg_temp_free(cond1);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
}
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
}
}
if (rd != 0) {
tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
}
gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
#ifdef TARGET_RISCV64
static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
if (memop < 0) {
gen_exception_illegal(ctx);
return;
}
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
gen_set_gpr(rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
gen_get_gpr(dat, rs2);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
if (memop < 0) {
gen_exception_illegal(ctx);
return;
}
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
tcg_temp_free(t0);
tcg_temp_free(dat);
}
#endif
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_temp_free(tmp);
}
#else
static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
#if !defined(TARGET_RISCV64)
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
TCGv t0;
if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
switch (opc) {
case OPC_RISC_FLW:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
break;
case OPC_RISC_FLD:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
}
tcg_temp_free(t0);
mark_fs_dirty(ctx);
}
static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
int rs2, target_long imm)
{
TCGv t0;
if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
switch (opc) {
case OPC_RISC_FSW:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
break;
case OPC_RISC_FSD:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
}
tcg_temp_free(t0);
}
#endif
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
if (ctx->frm == rm) {
return;
}
ctx->frm = rm;
t0 = tcg_const_i32(rm);
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
}
static void decode_RV32_64C0(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode);
uint8_t rs1s = GET_C_RS1S(ctx->opcode);
switch (funct3) {
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
GET_C_LW_IMM(ctx->opcode));
#endif
break;
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
GET_C_LW_IMM(ctx->opcode));
#endif
break;
}
}
static void decode_RV32_64C(DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
switch (op) {
case 0:
decode_RV32_64C0(ctx);
break;
}
}
#define EX_SH(amount) \
static int ex_shift_##amount(int imm) \
{ \
return imm << amount; \
}
EX_SH(1)
EX_SH(2)
EX_SH(3)
EX_SH(4)
EX_SH(12)
#define REQUIRE_EXT(ctx, ext) do { \
if (!has_ext(ctx, ext)) { \
return false; \
} \
} while (0)
static int ex_rvc_register(int reg)
{
return 8 + reg;
}
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
tcg_gen_movi_tl(source2, a->imm);
(*func)(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
#ifdef TARGET_RISCV64
static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_add_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_sub_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_mul_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
(*func)(source1, source1, source2);
tcg_gen_ext32s_tl(source1, source1);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
(*func)(source1, source1, source2);
tcg_gen_ext32s_tl(source1, source1);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
(*func)(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
static bool gen_shift(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1 = tcg_temp_new();
TCGv source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
(*func)(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
bool decode_insn16(DisasContext *ctx, uint16_t insn);
/* auto-generated decoder*/
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, ctx->opcode)) {
/* fall back to old decoder */
decode_RV32_64C(ctx);
}
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
gen_exception_illegal(ctx);
}
}
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cs->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
{
}
static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
tcg_gen_insn_start(ctx->base.pc_next);
}
static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
const CPUBreakpoint *bp)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
ctx->base.is_jmp = DISAS_NORETURN;
gen_exception_debug();
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
ctx->base.pc_next += 4;
return true;
}
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu->env_ptr;
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
target_ulong page_start;
page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
}
}
static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NORETURN:
break;
default:
g_assert_not_reached();
}
}
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
{
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
}
static const TranslatorOps riscv_tr_ops = {
.init_disas_context = riscv_tr_init_disas_context,
.tb_start = riscv_tr_tb_start,
.insn_start = riscv_tr_insn_start,
.breakpoint_check = riscv_tr_breakpoint_check,
.translate_insn = riscv_tr_translate_insn,
.tb_stop = riscv_tr_tb_stop,
.disas_log = riscv_tr_disas_log,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
DisasContext ctx;
translator_loop(&riscv_tr_ops, &ctx.base, cs, tb);
}
void riscv_translate_init(void)
{
int i;
/* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
/* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
/* registers, unless you specifically block reads/writes to reg 0 */
cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) {
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
}
for (i = 0; i < 32; i++) {
cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
}
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
}
|
pmp-tool/PMP | src/qemu/src-pmp/include/authz/simple.h | <reponame>pmp-tool/PMP<gh_stars>1-10
/*
* QEMU simple authorization driver
*
* Copyright (c) 2018 Red Hat, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef QAUTHZ_SIMPLE_H__
#define QAUTHZ_SIMPLE_H__
#include "authz/base.h"
#define TYPE_QAUTHZ_SIMPLE "authz-simple"
#define QAUTHZ_SIMPLE_CLASS(klass) \
OBJECT_CLASS_CHECK(QAuthZSimpleClass, (klass), \
TYPE_QAUTHZ_SIMPLE)
#define QAUTHZ_SIMPLE_GET_CLASS(obj) \
OBJECT_GET_CLASS(QAuthZSimpleClass, (obj), \
TYPE_QAUTHZ_SIMPLE)
#define QAUTHZ_SIMPLE(obj) \
OBJECT_CHECK(QAuthZSimple, (obj), \
TYPE_QAUTHZ_SIMPLE)
typedef struct QAuthZSimple QAuthZSimple;
typedef struct QAuthZSimpleClass QAuthZSimpleClass;
/**
* QAuthZSimple:
*
* This authorization driver provides a simple mechanism
* for granting access based on an exact matched username.
*
* To create an instance of this class via QMP:
*
* {
* "execute": "object-add",
* "arguments": {
* "qom-type": "authz-simple",
* "id": "authz0",
* "props": {
* "identity": "fred"
* }
* }
* }
*
* Or via the command line
*
* -object authz-simple,id=authz0,identity=fred
*
*/
struct QAuthZSimple {
QAuthZ parent_obj;
char *identity;
};
struct QAuthZSimpleClass {
QAuthZClass parent_class;
};
QAuthZSimple *qauthz_simple_new(const char *id,
const char *identity,
Error **errp);
#endif /* QAUTHZ_SIMPLE_H__ */
|
pmp-tool/PMP | src/qemu/src-pmp/hw/tpm/tpm_ppi.c | /*
* tpm_ppi.c - TPM Physical Presence Interface
*
* Copyright (C) 2018 IBM Corporation
*
* Authors:
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "sysemu/memory_mapping.h"
#include "sysemu/reset.h"
#include "migration/vmstate.h"
#include "tpm_ppi.h"
#include "trace.h"
void tpm_ppi_reset(TPMPPI *tpmppi)
{
if (tpmppi->buf[0x15a /* movv, docs/specs/tpm.txt */] & 0x1) {
GuestPhysBlockList guest_phys_blocks;
GuestPhysBlock *block;
guest_phys_blocks_init(&guest_phys_blocks);
guest_phys_blocks_append(&guest_phys_blocks);
QTAILQ_FOREACH(block, &guest_phys_blocks.head, next) {
trace_tpm_ppi_memset(block->host_addr,
block->target_end - block->target_start);
memset(block->host_addr, 0,
block->target_end - block->target_start);
memory_region_set_dirty(block->mr, 0,
block->target_end - block->target_start);
}
guest_phys_blocks_free(&guest_phys_blocks);
}
}
void tpm_ppi_init(TPMPPI *tpmppi, struct MemoryRegion *m,
hwaddr addr, Object *obj)
{
tpmppi->buf = g_malloc0(HOST_PAGE_ALIGN(TPM_PPI_ADDR_SIZE));
memory_region_init_ram_device_ptr(&tpmppi->ram, obj, "tpm-ppi",
TPM_PPI_ADDR_SIZE, tpmppi->buf);
vmstate_register_ram(&tpmppi->ram, DEVICE(obj));
memory_region_add_subregion(m, addr, &tpmppi->ram);
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/smbios/smbios_type_38.c | <gh_stars>1-10
/*
* IPMI SMBIOS firmware handling
*
* Copyright (c) 2015,2016 <NAME>, MontaVista Software, LLC
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "hw/ipmi/ipmi.h"
#include "hw/firmware/smbios.h"
#include "qemu/error-report.h"
#include "smbios_build.h"
/* SMBIOS type 38 - IPMI */
struct smbios_type_38 {
struct smbios_structure_header header;
uint8_t interface_type;
uint8_t ipmi_spec_revision;
uint8_t i2c_slave_address;
uint8_t nv_storage_device_address;
uint64_t base_address;
uint8_t base_address_modifier;
uint8_t interrupt_number;
} QEMU_PACKED;
static void smbios_build_one_type_38(IPMIFwInfo *info)
{
uint64_t baseaddr = info->base_address;
SMBIOS_BUILD_TABLE_PRE(38, 0x3000, true);
t->interface_type = info->interface_type;
t->ipmi_spec_revision = ((info->ipmi_spec_major_revision << 4)
| info->ipmi_spec_minor_revision);
t->i2c_slave_address = info->i2c_slave_address;
t->nv_storage_device_address = 0;
assert(info->ipmi_spec_minor_revision <= 15);
assert(info->ipmi_spec_major_revision <= 15);
/* or 1 to set it to I/O space */
switch (info->memspace) {
case IPMI_MEMSPACE_IO:
baseaddr |= 1;
break;
case IPMI_MEMSPACE_MEM32:
case IPMI_MEMSPACE_MEM64:
break;
case IPMI_MEMSPACE_SMBUS:
baseaddr <<= 1;
break;
}
t->base_address = cpu_to_le64(baseaddr);
t->base_address_modifier = 0;
if (info->irq_type == IPMI_LEVEL_IRQ) {
t->base_address_modifier |= 1;
}
switch (info->register_spacing) {
case 1:
break;
case 4:
t->base_address_modifier |= 1 << 6;
break;
case 16:
t->base_address_modifier |= 2 << 6;
break;
default:
error_report("IPMI register spacing %d is not compatible with"
" SMBIOS, ignoring this entry.", info->register_spacing);
return;
}
t->interrupt_number = info->interrupt_number;
SMBIOS_BUILD_TABLE_POST;
}
static void smbios_add_ipmi_devices(BusState *bus)
{
BusChild *kid;
QTAILQ_FOREACH(kid, &bus->children, sibling) {
DeviceState *dev = kid->child;
Object *obj = object_dynamic_cast(OBJECT(dev), TYPE_IPMI_INTERFACE);
BusState *childbus;
if (obj) {
IPMIInterface *ii;
IPMIInterfaceClass *iic;
IPMIFwInfo info;
ii = IPMI_INTERFACE(obj);
iic = IPMI_INTERFACE_GET_CLASS(obj);
memset(&info, 0, sizeof(info));
iic->get_fwinfo(ii, &info);
smbios_build_one_type_38(&info);
continue;
}
QLIST_FOREACH(childbus, &dev->child_bus, sibling) {
smbios_add_ipmi_devices(childbus);
}
}
}
void smbios_build_type_38_table(void)
{
BusState *bus;
bus = sysbus_get_default();
if (bus) {
smbios_add_ipmi_devices(bus);
}
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/isa/mips64r6/bit-swap/test_mips64r6_bitswap.c | /*
* Test program for MIPS64R6 instruction BITSWAP
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *instruction_name = "BITSWAP";
int32_t ret;
uint32_t i;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0xffffffffffffffffULL, /* 0 */
0x0000000000000000ULL,
0x0000000055555555ULL,
0xffffffffaaaaaaaaULL,
0x0000000033333333ULL,
0xffffffffccccccccULL,
0x00000000711cc771ULL,
0xffffffff8ee3388eULL,
0x000000000f0f0f0fULL, /* 8 */
0xfffffffff0f0f0f0ULL,
0x00000000071f7cf0ULL,
0xfffffffff8e0830fULL,
0xfffffffff0033ff0ULL,
0x000000000ffcc00fULL,
0x0000000007fc017fULL,
0xfffffffff803fe80ULL,
0xffffffffff00ff00ULL, /* 16 */
0x0000000000ff00ffULL,
0xfffffffff01fc07fULL,
0x000000000fe03f80ULL,
0x0000000000ff03f0ULL,
0xffffffffff00fc0fULL,
0x0000000001f07f00ULL,
0xfffffffffe0f80ffULL,
0x000000000f00ff0fULL, /* 24 */
0xfffffffff0ff00f0ULL,
0x000000007f00f0ffULL,
0xffffffff80ff0f00ULL,
0xffffffffff0300ffULL,
0x0000000000fcff00ULL,
0xffffffffff1f00f0ULL,
0x0000000000e0ff0fULL,
0xffffffffffff0000ULL, /* 32 */
0x000000000000ffffULL,
0xfffffffffcff0700ULL,
0x000000000300f8ffULL,
0xfffffffff0ff3f00ULL,
0x000000000f00c0ffULL,
0xffffffffc0ffff01ULL,
0x000000003f0000feULL,
0x0000000000ffff0fULL, /* 40 */
0xffffffffff0000f0ULL,
0x0000000000fcff7fULL,
0xffffffffff030080ULL,
0x0000000000f0ffffULL,
0xffffffffff0f0000ULL,
0x0000000000c0ffffULL,
0xffffffffff3f0000ULL,
0x000000000000ffffULL, /* 48 */
0xffffffffffff0000ULL,
0x000000000000fcffULL,
0xffffffffffff0300ULL,
0x000000000000f0ffULL,
0xffffffffffff0f00ULL,
0x000000000000c0ffULL,
0xffffffffffff3f00ULL,
0x00000000000000ffULL, /* 56 */
0xffffffffffffff00ULL,
0x00000000000000fcULL,
0xffffffffffffff03ULL,
0x00000000000000f0ULL,
0xffffffffffffff0fULL,
0x00000000000000c0ULL,
0xffffffffffffff3fULL,
0x000000001446aa02ULL, /* 64 */
0xffffffffb2c9e310ULL,
0xffffffff9df3d101ULL,
0x000000007a8c4772ULL,
0xffffffffbef5421aULL,
0xffffffffff50749fULL,
0xffffffffa6533d52ULL,
0x000000005965ed41ULL,
0x000000006a756792ULL, /* 72 */
0xffffffffa69ba7ebULL,
0xffffffff93d363d8ULL,
0xffffffff8c152675ULL,
0x00000000654a5750ULL,
0xffffffff98c48615ULL,
0x00000000447def39ULL,
0x000000004f9a7bb5ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < TEST_COUNT_TOTAL; i++) {
if (i < PATTERN_INPUTS_64_COUNT) {
do_mips64r6_BITSWAP(b64_pattern + i, b64_result + i);
} else {
do_mips64r6_BITSWAP(b64_random + (i - PATTERN_INPUTS_64_COUNT),
b64_result + i);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
b64_result, b64_expect);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/boot-serial-test.c | /*
* Test serial output of some machines.
*
* Copyright 2016 <NAME>, Red Hat Inc.
*
* This work is licensed under the terms of the GNU GPL, version 2
* or later. See the COPYING file in the top-level directory.
*
* This test is used to check that the serial output of the firmware
* (that we provide for some machines) or some small mini-kernels that
* we provide here contains an expected string. Thus we check that the
* firmware/kernel still boots at least to a certain point and so we
* know that the machine is not completely broken.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
static const uint8_t kernel_mcf5208[] = {
0x41, 0xf9, 0xfc, 0x06, 0x00, 0x00, /* lea 0xfc060000,%a0 */
0x10, 0x3c, 0x00, 0x54, /* move.b #'T',%d0 */
0x11, 0x7c, 0x00, 0x04, 0x00, 0x08, /* move.b #4,8(%a0) Enable TX */
0x11, 0x40, 0x00, 0x0c, /* move.b %d0,12(%a0) Print 'T' */
0x60, 0xfa /* bra.s loop */
};
static const uint8_t kernel_pls3adsp1800[] = {
0xb0, 0x00, 0x84, 0x00, /* imm 0x8400 */
0x30, 0x60, 0x00, 0x04, /* addik r3,r0,4 */
0x30, 0x80, 0x00, 0x54, /* addik r4,r0,'T' */
0xf0, 0x83, 0x00, 0x00, /* sbi r4,r3,0 */
0xb8, 0x00, 0xff, 0xfc /* bri -4 loop */
};
static const uint8_t kernel_plml605[] = {
0xe0, 0x83, 0x00, 0xb0, /* imm 0x83e0 */
0x00, 0x10, 0x60, 0x30, /* addik r3,r0,0x1000 */
0x54, 0x00, 0x80, 0x30, /* addik r4,r0,'T' */
0x00, 0x00, 0x83, 0xf0, /* sbi r4,r3,0 */
0xfc, 0xff, 0x00, 0xb8 /* bri -4 loop */
};
static const uint8_t bios_moxiesim[] = {
0x20, 0x10, 0x00, 0x00, 0x03, 0xf8, /* ldi.s r1,0x3f8 */
0x1b, 0x20, 0x00, 0x00, 0x00, 0x54, /* ldi.b r2,'T' */
0x1e, 0x12, /* st.b r1,r2 */
0x1a, 0x00, 0x00, 0x00, 0x10, 0x00 /* jmpa 0x1000 */
};
static const uint8_t bios_raspi2[] = {
0x08, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8] Get base */
0x54, 0x20, 0xa0, 0xe3, /* mov r2,#'T' */
0x00, 0x20, 0xc3, 0xe5, /* strb r2,[r3] */
0xfb, 0xff, 0xff, 0xea, /* b loop */
0x00, 0x10, 0x20, 0x3f, /* 0x3f201000 = UART0 base addr */
};
static const uint8_t kernel_aarch64[] = {
0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */
0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 */
0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] */
0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
};
static const uint8_t kernel_nrf51[] = {
0x00, 0x00, 0x00, 0x00, /* Stack top address */
0x09, 0x00, 0x00, 0x00, /* Reset handler address */
0x04, 0x4a, /* ldr r2, [pc, #16] Get ENABLE */
0x04, 0x21, /* movs r1, #4 */
0x11, 0x60, /* str r1, [r2] */
0x04, 0x4a, /* ldr r2, [pc, #16] Get STARTTX */
0x01, 0x21, /* movs r1, #1 */
0x11, 0x60, /* str r1, [r2] */
0x03, 0x4a, /* ldr r2, [pc, #12] Get TXD */
0x54, 0x21, /* movs r1, 'T' */
0x11, 0x60, /* str r1, [r2] */
0xfe, 0xe7, /* b . */
0x00, 0x25, 0x00, 0x40, /* 0x40002500 = UART ENABLE */
0x08, 0x20, 0x00, 0x40, /* 0x40002008 = UART STARTTX */
0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
};
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
const char *extra; /* Additional parameters */
const char *expect; /* Expected string in the serial output */
size_t codesize; /* Size of the kernel or bios data */
const uint8_t *kernel; /* Set in case we use our own mini kernel */
const uint8_t *bios; /* Set in case we use our own mini bios */
} testdef_t;
static testdef_t tests[] = {
{ "alpha", "clipper", "", "PCI:" },
{ "ppc", "ppce500", "", "U-Boot" },
{ "ppc", "40p", "-vga none -boot d", "Trying cd:," },
{ "ppc", "g3beige", "", "PowerPC,750" },
{ "ppc", "mac99", "", "PowerPC,G4" },
{ "ppc", "sam460ex", "-m 256", "DRAM: 256 MiB" },
{ "ppc64", "ppce500", "", "U-Boot" },
{ "ppc64", "40p", "-m 192", "Memory: 192M" },
{ "ppc64", "mac99", "", "PowerPC,970FX" },
{ "ppc64", "pseries",
"-machine cap-cfpc=broken,cap-sbbc=broken,cap-ibs=broken",
"Open Firmware" },
{ "ppc64", "powernv", "-cpu POWER8", "OPAL" },
{ "ppc64", "sam460ex", "-device e1000", "8086 100e" },
{ "i386", "isapc", "-cpu qemu32 -device sga", "SGABIOS" },
{ "i386", "pc", "-device sga", "SGABIOS" },
{ "i386", "q35", "-device sga", "SGABIOS" },
{ "x86_64", "isapc", "-cpu qemu32 -device sga", "SGABIOS" },
{ "x86_64", "q35", "-device sga", "SGABIOS" },
{ "sparc", "LX", "", "TMS390S10" },
{ "sparc", "SS-4", "", "MB86904" },
{ "sparc", "SS-600MP", "", "TMS390Z55" },
{ "sparc64", "sun4u", "", "UltraSPARC" },
{ "s390x", "s390-ccw-virtio", "", "virtio device" },
{ "m68k", "mcf5208evb", "", "TT", sizeof(kernel_mcf5208), kernel_mcf5208 },
{ "microblaze", "petalogix-s3adsp1800", "", "TT",
sizeof(kernel_pls3adsp1800), kernel_pls3adsp1800 },
{ "microblazeel", "petalogix-ml605", "", "TT",
sizeof(kernel_plml605), kernel_plml605 },
{ "moxie", "moxiesim", "", "TT", sizeof(bios_moxiesim), 0, bios_moxiesim },
{ "arm", "raspi2", "", "TT", sizeof(bios_raspi2), 0, bios_raspi2 },
{ "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
{ "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
{ "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
{ NULL }
};
static bool check_guest_output(QTestState *qts, const testdef_t *test, int fd)
{
int nbr = 0, pos = 0, ccnt;
time_t now, start = time(NULL);
char ch;
/* Poll serial output... */
while (1) {
ccnt = 0;
while (ccnt++ < 512 && (nbr = read(fd, &ch, 1)) == 1) {
if (ch == test->expect[pos]) {
pos += 1;
if (test->expect[pos] == '\0') {
/* We've reached the end of the expected string! */
return true;
}
} else {
pos = 0;
}
}
g_assert(nbr >= 0);
/* Wait only if the child is still alive. */
if (!qtest_probe_child(qts)) {
break;
}
/* Wait at most 360 seconds. */
now = time(NULL);
if (now - start >= 360) {
break;
}
g_usleep(10000);
}
return false;
}
static void test_machine(const void *data)
{
const testdef_t *test = data;
char serialtmp[] = "/tmp/qtest-boot-serial-sXXXXXX";
char codetmp[] = "/tmp/qtest-boot-serial-cXXXXXX";
const char *codeparam = "";
const uint8_t *code = NULL;
QTestState *qts;
int ser_fd;
ser_fd = mkstemp(serialtmp);
g_assert(ser_fd != -1);
if (test->kernel) {
code = test->kernel;
codeparam = "-kernel";
} else if (test->bios) {
code = test->bios;
codeparam = "-bios";
}
if (code) {
ssize_t wlen;
int code_fd;
code_fd = mkstemp(codetmp);
g_assert(code_fd != -1);
wlen = write(code_fd, code, test->codesize);
g_assert(wlen == test->codesize);
close(code_fd);
}
/*
* Make sure that this test uses tcg if available: It is used as a
* fast-enough smoketest for that.
*/
qts = qtest_initf("%s %s -M %s,accel=tcg:kvm -no-shutdown "
"-chardev file,id=serial0,path=%s "
"-serial chardev:serial0 %s",
codeparam, code ? codetmp : "", test->machine,
serialtmp, test->extra);
if (code) {
unlink(codetmp);
}
if (!check_guest_output(qts, test, ser_fd)) {
g_error("Failed to find expected string. Please check '%s'",
serialtmp);
}
unlink(serialtmp);
qtest_quit(qts);
close(ser_fd);
}
int main(int argc, char *argv[])
{
const char *arch = qtest_get_arch();
int i;
g_test_init(&argc, &argv, NULL);
for (i = 0; tests[i].arch != NULL; i++) {
if (strcmp(arch, tests[i].arch) == 0) {
char *name = g_strdup_printf("boot-serial/%s", tests[i].machine);
qtest_add_data_func(name, &tests[i], test_machine);
g_free(name);
}
}
return g_test_run();
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/libqos/x86_64_pc-machine.c | /*
* libqos driver framework
*
* Copyright (c) 2018 <NAME> <<EMAIL>>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License version 2 as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/qgraph.h"
#include "pci-pc.h"
#include "malloc-pc.h"
typedef struct QX86PCMachine QX86PCMachine;
typedef struct i440FX_pcihost i440FX_pcihost;
typedef struct QSDHCI_PCI QSDHCI_PCI;
struct i440FX_pcihost {
QOSGraphObject obj;
QPCIBusPC pci;
};
struct QX86PCMachine {
QOSGraphObject obj;
QGuestAllocator alloc;
i440FX_pcihost bridge;
};
/* i440FX_pcihost */
static QOSGraphObject *i440FX_host_get_device(void *obj, const char *device)
{
i440FX_pcihost *host = obj;
if (!g_strcmp0(device, "pci-bus-pc")) {
return &host->pci.obj;
}
fprintf(stderr, "%s not present in i440FX-pcihost\n", device);
g_assert_not_reached();
}
static void qos_create_i440FX_host(i440FX_pcihost *host,
QTestState *qts,
QGuestAllocator *alloc)
{
host->obj.get_device = i440FX_host_get_device;
qpci_init_pc(&host->pci, qts, alloc);
}
/* x86_64/pc machine */
static void pc_destructor(QOSGraphObject *obj)
{
QX86PCMachine *machine = (QX86PCMachine *) obj;
alloc_destroy(&machine->alloc);
}
static void *pc_get_driver(void *object, const char *interface)
{
QX86PCMachine *machine = object;
if (!g_strcmp0(interface, "memory")) {
return &machine->alloc;
}
fprintf(stderr, "%s not present in x86_64/pc\n", interface);
g_assert_not_reached();
}
static QOSGraphObject *pc_get_device(void *obj, const char *device)
{
QX86PCMachine *machine = obj;
if (!g_strcmp0(device, "i440FX-pcihost")) {
return &machine->bridge.obj;
}
fprintf(stderr, "%s not present in x86_64/pc\n", device);
g_assert_not_reached();
}
static void *qos_create_machine_pc(QTestState *qts)
{
QX86PCMachine *machine = g_new0(QX86PCMachine, 1);
machine->obj.get_device = pc_get_device;
machine->obj.get_driver = pc_get_driver;
machine->obj.destructor = pc_destructor;
pc_alloc_init(&machine->alloc, qts, ALLOC_NO_FLAGS);
qos_create_i440FX_host(&machine->bridge, qts, &machine->alloc);
return &machine->obj;
}
static void pc_machine_register_nodes(void)
{
qos_node_create_machine("i386/pc", qos_create_machine_pc);
qos_node_contains("i386/pc", "i440FX-pcihost", NULL);
qos_node_create_machine("x86_64/pc", qos_create_machine_pc);
qos_node_contains("x86_64/pc", "i440FX-pcihost", NULL);
qos_node_create_driver("i440FX-pcihost", NULL);
qos_node_contains("i440FX-pcihost", "pci-bus-pc", NULL);
}
libqos_init(pc_machine_register_nodes);
|
pmp-tool/PMP | src/qemu/src-pmp/include/hw/block/flash.h | #ifndef HW_FLASH_H
#define HW_FLASH_H
/* NOR flash devices */
#include "exec/memory.h"
/* pflash_cfi01.c */
#define TYPE_PFLASH_CFI01 "cfi.pflash01"
#define PFLASH_CFI01(obj) \
OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01)
typedef struct PFlashCFI01 PFlashCFI01;
PFlashCFI01 *pflash_cfi01_register(hwaddr base,
const char *name,
hwaddr size,
BlockBackend *blk,
uint32_t sector_len,
int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
int be);
BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
/* pflash_cfi02.c */
#define TYPE_PFLASH_CFI02 "cfi.pflash02"
#define PFLASH_CFI02(obj) \
OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02)
typedef struct PFlashCFI02 PFlashCFI02;
PFlashCFI02 *pflash_cfi02_register(hwaddr base,
const char *name,
hwaddr size,
BlockBackend *blk,
uint32_t sector_len,
int nb_mappings,
int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
uint16_t unlock_addr0,
uint16_t unlock_addr1,
int be);
/* nand.c */
DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
uint8_t ce, uint8_t wp, uint8_t gnd);
void nand_getpins(DeviceState *dev, int *rb);
void nand_setio(DeviceState *dev, uint32_t value);
uint32_t nand_getio(DeviceState *dev);
uint32_t nand_getbuswidth(DeviceState *dev);
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xec
#define NAND_MFR_FUJITSU 0x04
#define NAND_MFR_NATIONAL 0x8f
#define NAND_MFR_RENESAS 0x07
#define NAND_MFR_STMICRO 0x20
#define NAND_MFR_HYNIX 0xad
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
void *onenand_raw_otp(DeviceState *onenand_device);
/* ecc.c */
typedef struct {
uint8_t cp; /* Column parity */
uint16_t lp[2]; /* Line parity */
uint16_t count;
} ECCState;
uint8_t ecc_digest(ECCState *s, uint8_t sample);
void ecc_reset(ECCState *s);
extern VMStateDescription vmstate_ecc_state;
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/include/wrappers_msa.h | /*
* Header file for wrappers around MSA instructions assembler invocations
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#ifndef WRAPPERS_MSA_H
#define WRAPPERS_MSA_H
#define DO_MSA__WD__WS(suffix, mnemonic) \
static inline void do_msa_##suffix(void *input, void *output) \
{ \
__asm__ volatile ( \
"move $t0, %0\n\t" \
"ld.d $w11, 0($t0)\n\t" \
#mnemonic " $w10, $w11\n\t" \
"move $t0, %1\n\t" \
"st.d $w10, 0($t0)\n\t" \
: \
: "r" (input), "r" (output) \
: "t0", "memory" \
); \
}
#define DO_MSA__WD__WD(suffix, mnemonic) \
static inline void do_msa_##suffix(void *input, void *output) \
{ \
__asm__ volatile ( \
"move $t0, %0\n\t" \
"ld.d $w11, 0($t0)\n\t" \
#mnemonic " $w10, $w10\n\t" \
"move $t0, %1\n\t" \
"st.d $w10, 0($t0)\n\t" \
: \
: "r" (input), "r" (output) \
: "t0", "memory" \
); \
}
DO_MSA__WD__WS(NLOC_B, nloc.b)
DO_MSA__WD__WS(NLOC_H, nloc.h)
DO_MSA__WD__WS(NLOC_W, nloc.w)
DO_MSA__WD__WS(NLOC_D, nloc.d)
DO_MSA__WD__WS(NLZC_B, nlzc.b)
DO_MSA__WD__WS(NLZC_H, nlzc.h)
DO_MSA__WD__WS(NLZC_W, nlzc.w)
DO_MSA__WD__WS(NLZC_D, nlzc.d)
DO_MSA__WD__WS(PCNT_B, pcnt.b)
DO_MSA__WD__WS(PCNT_H, pcnt.h)
DO_MSA__WD__WS(PCNT_W, pcnt.w)
DO_MSA__WD__WS(PCNT_D, pcnt.d)
#define DO_MSA__WD__WS_WT(suffix, mnemonic) \
static inline void do_msa_##suffix(void *input1, void *input2, \
void *output) \
{ \
__asm__ volatile ( \
"move $t0, %0\n\t" \
"ld.d $w11, 0($t0)\n\t" \
"move $t0, %1\n\t" \
"ld.d $w12, 0($t0)\n\t" \
#mnemonic " $w10, $w11, $w12\n\t" \
"move $t0, %2\n\t" \
"st.d $w10, 0($t0)\n\t" \
: \
: "r" (input1), "r" (input2), "r" (output) \
: "t0", "memory" \
); \
}
#define DO_MSA__WD__WD_WT(suffix, mnemonic) \
static inline void do_msa_##suffix(void *input1, void *input2, \
void *output) \
{ \
__asm__ volatile ( \
"move $t0, %0\n\t" \
"ld.d $w11, 0($t0)\n\t" \
"move $t0, %1\n\t" \
"ld.d $w12, 0($t0)\n\t" \
#mnemonic " $w10, $w10, $w12\n\t" \
"move $t0, %2\n\t" \
"st.d $w10, 0($t0)\n\t" \
: \
: "r" (input1), "r" (input2), "r" (output) \
: "t0", "memory" \
); \
}
#define DO_MSA__WD__WS_WD(suffix, mnemonic) \
static inline void do_msa_##suffix(void *input1, void *input2, \
void *output) \
{ \
__asm__ volatile ( \
"move $t0, %0\n\t" \
"ld.d $w11, 0($t0)\n\t" \
"move $t0, %1\n\t" \
"ld.d $w12, 0($t0)\n\t" \
#mnemonic " $w10, $w11, $w10\n\t" \
"move $t0, %2\n\t" \
"st.d $w10, 0($t0)\n\t" \
: \
: "r" (input1), "r" (input2), "r" (output) \
: "t0", "memory" \
); \
}
DO_MSA__WD__WS_WT(ILVEV_B, ilvev.b)
DO_MSA__WD__WS_WT(ILVEV_H, ilvev.h)
DO_MSA__WD__WS_WT(ILVEV_W, ilvev.w)
DO_MSA__WD__WS_WT(ILVEV_D, ilvev.d)
DO_MSA__WD__WS_WT(ILVOD_B, ilvod.b)
DO_MSA__WD__WS_WT(ILVOD_H, ilvod.h)
DO_MSA__WD__WS_WT(ILVOD_W, ilvod.w)
DO_MSA__WD__WS_WT(ILVOD_D, ilvod.d)
DO_MSA__WD__WS_WT(ILVL_B, ilvl.b)
DO_MSA__WD__WS_WT(ILVL_H, ilvl.h)
DO_MSA__WD__WS_WT(ILVL_W, ilvl.w)
DO_MSA__WD__WS_WT(ILVL_D, ilvl.d)
DO_MSA__WD__WS_WT(ILVR_B, ilvr.b)
DO_MSA__WD__WS_WT(ILVR_H, ilvr.h)
DO_MSA__WD__WS_WT(ILVR_W, ilvr.w)
DO_MSA__WD__WS_WT(ILVR_D, ilvr.d)
DO_MSA__WD__WS_WT(AND_V, and.v)
DO_MSA__WD__WS_WT(NOR_V, nor.v)
DO_MSA__WD__WS_WT(OR_V, or.v)
DO_MSA__WD__WS_WT(XOR_V, xor.v)
DO_MSA__WD__WS_WT(CEQ_B, ceq.b)
DO_MSA__WD__WS_WT(CEQ_H, ceq.h)
DO_MSA__WD__WS_WT(CEQ_W, ceq.w)
DO_MSA__WD__WS_WT(CEQ_D, ceq.d)
DO_MSA__WD__WS_WT(CLE_S_B, cle_s.b)
DO_MSA__WD__WS_WT(CLE_S_H, cle_s.h)
DO_MSA__WD__WS_WT(CLE_S_W, cle_s.w)
DO_MSA__WD__WS_WT(CLE_S_D, cle_s.d)
DO_MSA__WD__WS_WT(CLE_U_B, cle_u.b)
DO_MSA__WD__WS_WT(CLE_U_H, cle_u.h)
DO_MSA__WD__WS_WT(CLE_U_W, cle_u.w)
DO_MSA__WD__WS_WT(CLE_U_D, cle_u.d)
DO_MSA__WD__WS_WT(CLT_S_B, clt_s.b)
DO_MSA__WD__WS_WT(CLT_S_H, clt_s.h)
DO_MSA__WD__WS_WT(CLT_S_W, clt_s.w)
DO_MSA__WD__WS_WT(CLT_S_D, clt_s.d)
DO_MSA__WD__WS_WT(CLT_U_B, clt_u.b)
DO_MSA__WD__WS_WT(CLT_U_H, clt_u.h)
DO_MSA__WD__WS_WT(CLT_U_W, clt_u.w)
DO_MSA__WD__WS_WT(CLT_U_D, clt_u.d)
DO_MSA__WD__WS_WT(MAX_A_B, max_a.b)
DO_MSA__WD__WS_WT(MAX_A_H, max_a.h)
DO_MSA__WD__WS_WT(MAX_A_W, max_a.w)
DO_MSA__WD__WS_WT(MAX_A_D, max_a.d)
DO_MSA__WD__WS_WT(MIN_A_B, min_a.b)
DO_MSA__WD__WS_WT(MIN_A_H, min_a.h)
DO_MSA__WD__WS_WT(MIN_A_W, min_a.w)
DO_MSA__WD__WS_WT(MIN_A_D, min_a.d)
DO_MSA__WD__WS_WT(MAX_S_B, max_s.b)
DO_MSA__WD__WS_WT(MAX_S_H, max_s.h)
DO_MSA__WD__WS_WT(MAX_S_W, max_s.w)
DO_MSA__WD__WS_WT(MAX_S_D, max_s.d)
DO_MSA__WD__WS_WT(MIN_S_B, min_s.b)
DO_MSA__WD__WS_WT(MIN_S_H, min_s.h)
DO_MSA__WD__WS_WT(MIN_S_W, min_s.w)
DO_MSA__WD__WS_WT(MIN_S_D, min_s.d)
DO_MSA__WD__WS_WT(MAX_U_B, max_u.b)
DO_MSA__WD__WS_WT(MAX_U_H, max_u.h)
DO_MSA__WD__WS_WT(MAX_U_W, max_u.w)
DO_MSA__WD__WS_WT(MAX_U_D, max_u.d)
DO_MSA__WD__WS_WT(MIN_U_B, min_u.b)
DO_MSA__WD__WS_WT(MIN_U_H, min_u.h)
DO_MSA__WD__WS_WT(MIN_U_W, min_u.w)
DO_MSA__WD__WS_WT(MIN_U_D, min_u.d)
DO_MSA__WD__WS_WT(BCLR_B, bclr.b)
DO_MSA__WD__WS_WT(BCLR_H, bclr.h)
DO_MSA__WD__WS_WT(BCLR_W, bclr.w)
DO_MSA__WD__WS_WT(BCLR_D, bclr.d)
DO_MSA__WD__WS_WT(BSET_B, bset.b)
DO_MSA__WD__WS_WT(BSET_H, bset.h)
DO_MSA__WD__WS_WT(BSET_W, bset.w)
DO_MSA__WD__WS_WT(BSET_D, bset.d)
DO_MSA__WD__WS_WT(BNEG_B, bneg.b)
DO_MSA__WD__WS_WT(BNEG_H, bneg.h)
DO_MSA__WD__WS_WT(BNEG_W, bneg.w)
DO_MSA__WD__WS_WT(BNEG_D, bneg.d)
DO_MSA__WD__WS_WT(PCKEV_B, pckev.b)
DO_MSA__WD__WS_WT(PCKEV_H, pckev.h)
DO_MSA__WD__WS_WT(PCKEV_W, pckev.w)
DO_MSA__WD__WS_WT(PCKEV_D, pckev.d)
DO_MSA__WD__WS_WT(PCKOD_B, pckod.b)
DO_MSA__WD__WS_WT(PCKOD_H, pckod.h)
DO_MSA__WD__WS_WT(PCKOD_W, pckod.w)
DO_MSA__WD__WS_WT(PCKOD_D, pckod.d)
DO_MSA__WD__WS_WT(VSHF_B, vshf.b)
DO_MSA__WD__WS_WT(VSHF_H, vshf.h)
DO_MSA__WD__WS_WT(VSHF_W, vshf.w)
DO_MSA__WD__WS_WT(VSHF_D, vshf.d)
DO_MSA__WD__WS_WT(SLL_B, sll.b)
DO_MSA__WD__WS_WT(SLL_H, sll.h)
DO_MSA__WD__WS_WT(SLL_W, sll.w)
DO_MSA__WD__WS_WT(SLL_D, sll.d)
DO_MSA__WD__WS_WT(SRA_B, sra.b)
DO_MSA__WD__WS_WT(SRA_H, sra.h)
DO_MSA__WD__WS_WT(SRA_W, sra.w)
DO_MSA__WD__WS_WT(SRA_D, sra.d)
DO_MSA__WD__WS_WT(SRAR_B, srar.b)
DO_MSA__WD__WS_WT(SRAR_H, srar.h)
DO_MSA__WD__WS_WT(SRAR_W, srar.w)
DO_MSA__WD__WS_WT(SRAR_D, srar.d)
DO_MSA__WD__WS_WT(SRL_B, srl.b)
DO_MSA__WD__WS_WT(SRL_H, srl.h)
DO_MSA__WD__WS_WT(SRL_W, srl.w)
DO_MSA__WD__WS_WT(SRL_D, srl.d)
DO_MSA__WD__WS_WT(SRLR_B, srlr.b)
DO_MSA__WD__WS_WT(SRLR_H, srlr.h)
DO_MSA__WD__WS_WT(SRLR_W, srlr.w)
DO_MSA__WD__WS_WT(SRLR_D, srlr.d)
DO_MSA__WD__WS_WT(BMNZ_V, bmnz.v)
DO_MSA__WD__WS_WT(BMZ_V, bmz.v)
DO_MSA__WD__WS_WT(FMAX_W, fmax.w)
DO_MSA__WD__WS_WT(FMAX_D, fmax.d)
DO_MSA__WD__WS_WT(FMAX_A_W, fmax_a.w)
DO_MSA__WD__WS_WT(FMAX_A_D, fmax_a.d)
DO_MSA__WD__WS_WT(FMIN_W, fmin.w)
DO_MSA__WD__WS_WT(FMIN_D, fmin.d)
DO_MSA__WD__WS_WT(FMIN_A_W, fmin_a.w)
DO_MSA__WD__WS_WT(FMIN_A_D, fmin_a.d)
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/disas/arm.c | <filename>src/qemu/src-pmp/disas/arm.c<gh_stars>1-10
/* Instruction printing code for the ARM
Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
2007, Free Software Foundation, Inc.
Contributed by <NAME> (<EMAIL>)
Modification by <NAME> (<EMAIL>)
This file is part of libopcodes.
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* Start of qemu specific additions. Mostly this is stub definitions
for things we don't care about. */
#include "qemu/osdep.h"
#include "disas/bfd.h"
#define ARM_EXT_V1 0
#define ARM_EXT_V2 0
#define ARM_EXT_V2S 0
#define ARM_EXT_V3 0
#define ARM_EXT_V3M 0
#define ARM_EXT_V4 0
#define ARM_EXT_V4T 0
#define ARM_EXT_V5 0
#define ARM_EXT_V5T 0
#define ARM_EXT_V5ExP 0
#define ARM_EXT_V5E 0
#define ARM_EXT_V5J 0
#define ARM_EXT_V6 0
#define ARM_EXT_V6K 0
#define ARM_EXT_V6Z 0
#define ARM_EXT_V6T2 0
#define ARM_EXT_V7 0
#define ARM_EXT_DIV 0
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0
#define ARM_CEXT_MAVERICK 0
#define ARM_CEXT_IWMMXT 0
#define FPU_FPA_EXT_V1 0
#define FPU_FPA_EXT_V2 0
#define FPU_VFP_EXT_NONE 0
#define FPU_VFP_EXT_V1xD 0
#define FPU_VFP_EXT_V1 0
#define FPU_VFP_EXT_V2 0
#define FPU_MAVERICK 0
#define FPU_VFP_EXT_V3 0
#define FPU_NEON_EXT_V1 0
/* Assume host uses ieee float. */
static void floatformat_to_double (unsigned char *data, double *dest)
{
union {
uint32_t i;
float f;
} u;
u.i = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
*dest = u.f;
}
static int arm_read_memory(bfd_vma memaddr, bfd_byte *b, int length,
struct disassemble_info *info)
{
assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
memaddr ^= 2;
}
return info->read_memory_func(memaddr, b, length, info);
}
/* End of qemu specific additions. */
struct opcode32
{
unsigned long arch; /* Architecture defining this insn. */
unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
const char *assembler; /* How to disassemble this insn. */
};
struct opcode16
{
unsigned long arch; /* Architecture defining this insn. */
unsigned short value, mask; /* Recognise insn if (op&mask)==value. */
const char *assembler; /* How to disassemble this insn. */
};
/* print_insn_coprocessor recognizes the following format control codes:
%% %
%c print condition code (always bits 28-31 in ARM mode)
%q print shifter argument
%u print condition code (unconditional in ARM mode)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
%C print vstr/vldr address operand
%I print cirrus signed shift immediate: bits 0..3|4..6
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
%<bitfield>k print immediate for VFPv3 conversion instruction
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>f print a floating point constant if >7 else a
floating point register
%<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
%<bitfield>g print as an iWMMXt 64-bit register
%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%y<code> print a single precision VFP reg.
Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
%z<code> print a double precision VFP reg
Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
%L print as an iWMMXt N/M width field.
%Z print the Immediate of a WSHUFH instruction.
%l like 'A' except use byte offsets for 'B' & 'H'
versions.
%i print 5-bit immediate in bits 8,3..0
(print "32" when 0)
%r print register offset address for wldt/wstr instruction
*/
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
static const struct opcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
{ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
{ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
#define FIRST_IWMMXT_INSN 0x0e130130
#define IWMMXT_INSN_COUNT 73
{ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
{ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
{ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
{ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
{ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
{ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
{ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
{ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
{ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
{ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
{ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
{ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
{ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
{ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
{ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
{ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
{ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
{ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
{ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
{ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
{ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
{ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
{ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
{ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
{ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
/* Floating point coprocessor (FPA) instructions */
{FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
{FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
{FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
{FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
{FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
{FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
{FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
{FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
{FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
{FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
{FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
/* Register load/store */
{FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
{FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
{FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
{FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
{FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
{FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
/* Data transfer between ARM and NEON registers */
{FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
{FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
{FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
{FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
{FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
{FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
{FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
{FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
{FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
{FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
{FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
{FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
{FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
{FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
/* Floating point coprocessor (VFP) instructions */
{FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
{FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
{FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
{FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
{FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
{FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"},
{FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"},
{FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
{FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
{FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
{FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
{FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
{FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
{FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
{FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"},
{FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
{FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
{FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
{FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
{FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
{FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
{FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
{FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
{FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
{FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
{FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
{FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
{FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
{FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
{FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
{FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
{FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
{FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
{FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
{FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
{FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
{FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
{FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
{FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
{FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
{FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
{FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"},
{FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"},
{FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
{FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
{FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
{FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
{FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
{FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
{FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
{FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
{FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
{FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
{FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
{FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
{FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
{FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
{FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
{FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
{FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
/* Cirrus coprocessor instructions. */
{ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
{ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
{ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
{ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
{ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
{ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* Generic coprocessor instructions */
{ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions */
{ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
/* V5 coprocessor instructions */
{ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{0, 0, 0, 0}
};
/* Neon opcode table: This does not encode the top byte -- that is
checked by the print_insn_neon routine, as it depends on whether we are
doing thumb32 or arm32 disassembly. */
/* print_insn_neon recognizes the following format control codes:
%% %
%c print condition code
%A print v{st,ld}[1234] operands
%B print v{st,ld}[1234] any one operands
%C print v{st,ld}[1234] single->all operands
%D print scalar
%E print vmov, vmvn, vorr, vbic encoded constant
%F print vtbl,vtbx register list
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
%<bitfield>e print the 2^N - bitfield in decimal
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%<bitfield>R print as a NEON D or Q register
%<bitfield>Sn print byte scaled width limited by n
%<bitfield>Tn print short scaled width limited by n
%<bitfield>Un print long scaled width limited by n
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order */
static const struct opcode32 neon_opcodes[] =
{
/* Extract */
{FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
{FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
/* Move data element to all lanes */
{FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
{FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
{FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
/* Table lookup */
{FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
/* Two registers, miscellaneous */
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
{FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
/* Three registers of the same length */
{FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* One register and an immediate value */
{FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
{FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
/* Two registers and a shift amount */
{FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
{FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
{FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
{FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
{FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
{FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
{FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
{FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
{FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
{FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
{FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
{FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
{FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
{FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
{FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
{FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
{FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
{FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
{FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
{FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
/* Three registers of different lengths */
{FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
/* Two registers and a scalar */
{FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
/* Element and structure load/store */
{FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
{FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
{FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
{FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
{FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
{FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
{FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
{FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
{FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
{FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
{FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
{FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
{FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
{FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
{FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
{0,0 ,0, 0}
};
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
ordered: they must be searched linearly from the top to obtain a correct
match. */
/* print_insn_arm recognizes the following format control codes:
%% %
%a print address for ldr/str instruction
%s print address for ldr/str halfword/signextend instruction
%b print branch destination
%c print condition code (always bits 28-31)
%m print register mask for ldm/stm instruction
%o print operand2 (immediate or register + shift)
%p print 'p' iff bits 12-15 are 15
%t print 't' iff bit 21 set and bit 24 clear
%B print arm BLX(1) destination
%C print the PSR sub type.
%U print barrier type.
%P print address for pli instruction.
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
%<bitfield>W print the bitfield plus one in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
%e print arm SMI operand (bits 0..7,8..19).
%E print the LSB and WIDTH fields of a BFI or BFC instruction.
%V print the 16-bit immediate field of a MOVT or MOVW instruction. */
static const struct opcode32 arm_opcodes[] =
{
/* ARM instructions. */
{ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
{ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
{ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"},
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
/* IDIV instructions. */
{ARM_EXT_DIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_DIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
/* V7 instructions. */
{ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
{ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
{ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
{ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
{ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
/* ARM V6T2 instructions. */
{ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
{ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
{ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"},
{ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"},
{ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
{ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
{ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
{ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
/* ARM V6Z instructions. */
{ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
/* ARM V6K instructions. */
{ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
{ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
{ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
{ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
{ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
{ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
{ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
/* ARM V6K NOP hints. */
{ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
{ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
{ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
{ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
{ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
/* ARM V6 instructions. */
{ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
{ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
{ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
{ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
{ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
{ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"},
{ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"},
{ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"},
{ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
{ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
{ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
{ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
{ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"},
{ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"},
{ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
{ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
{ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
{ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"},
{ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"},
{ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
{ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
{ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
{ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"},
{ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"},
{ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
/* V5J instruction. */
{ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
/* V5 Instructions. */
{ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
{ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
{ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
{ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
/* V5E "El Segundo" Instructions. */
{ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
{ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
{ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
{ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
{ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
{ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
{ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
/* ARM Instructions. */
{ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"},
{ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"},
{ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
{ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
{ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"},
{ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"},
{ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"},
{ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"},
{ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
{ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
{ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"},
{ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"},
{ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"},
{ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
{ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"},
{ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"},
{ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
{ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
{ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
{ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
{ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"},
{ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
{ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
{ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"},
{ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
{ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
{ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
/* The rest. */
{ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
{0, 0x00000000, 0x00000000, 0}
};
/* print_insn_thumb16 recognizes the following format control codes:
%S print Thumb register (bits 3..5 as high number if bit 6 set)
%D print Thumb register (bits 0..2 as high number if bit 7 set)
%<bitfield>I print bitfield as a signed decimal
(top bit of range being the sign bit)
%N print Thumb register mask (with LR)
%O print Thumb register mask (with PC)
%M print Thumb register mask
%b print CZB's 6-bit unsigned branch destination
%s print Thumb right-shift immediate (6..10; 0 == 32).
%c print the condition code
%C print the condition code, or "s" if not conditional
%x print warning if conditional an not at end of IT block"
%X print "\t; unpredictable <IT:code>" if conditional
%I print IT instruction suffix and operands
%<bitfield>r print bitfield as an ARM register
%<bitfield>d print bitfield as a decimal
%<bitfield>H print (bitfield * 2) as a decimal
%<bitfield>W print (bitfield * 4) as a decimal
%<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
%<bitfield>B print Thumb branch destination (signed displacement)
%<bitfield>c print bitfield as a condition code
%<bitnum>'c print specified char iff bit is one
%<bitnum>?ab print a if bit is one else print b. */
static const struct opcode16 thumb_opcodes[] =
{
/* Thumb instructions. */
/* ARM V6K no-argument instructions. */
{ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
{ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
{ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
{ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
{ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
{ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
/* ARM V6T2 instructions. */
{ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
{ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
{ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
/* ARM V6. */
{ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
{ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
{ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
{ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
{ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
/* ARM V5 ISA extends Thumb. */
{ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
/* This is BLX(2). BLX(1) is a 32-bit instruction. */
{ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
/* ARM V4T ISA (Thumb v1). */
{ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
/* Format 4. */
{ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
{ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
/* format 13 */
{ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
{ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
/* format 5 */
{ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
{ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
{ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
{ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
/* format 14 */
{ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
{ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
/* format 2 */
{ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
{ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
{ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
{ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
/* format 8 */
{ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
{ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
{ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
/* format 7 */
{ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
{ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
/* format 1 */
{ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
{ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
{ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
/* format 3 */
{ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
{ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
{ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
{ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
/* format 6 */
{ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
/* format 9 */
{ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
{ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
{ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
{ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
/* format 10 */
{ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
{ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
/* format 11 */
{ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
{ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
/* format 12 */
{ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"},
{ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
/* format 15 */
{ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
{ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
/* format 17 */
{ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
/* format 16 */
{ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"},
{ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
/* format 18 */
{ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
/* The E800 .. FFFF range is unconditionally redirected to the
32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
are processed via that table. Thus, we can never encounter a
bare "second half of BL/BLX(1)" instruction here. */
{ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
{0, 0, 0, 0}
};
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
We adopt the convention that hw1 is the high 16 bits of .value and
.mask, hw2 the low 16 bits.
print_insn_thumb32 recognizes the following format control codes:
%% %
%I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
%M print a modified 12-bit immediate (same location)
%J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
%K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
%S print a possibly-shifted Rm
%a print the address of a plain load/store
%w print the width and signedness of a core load/store
%m print register mask for ldm/stm
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
%R print the rotation field of an SXT instruction
%U print barrier type.
%P print address for pli instruction.
%c print the condition code
%x print warning if conditional an not at end of IT block"
%X print "\t; unpredictable <IT:code>" if conditional
%<bitfield>d print bitfield in decimal
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>c print bitfield as a condition code
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
With one exception at the bottom (done because BL and BLX(1) need
to come dead last), this table was machine-sorted first in
decreasing order of number of bits set in the mask, then in
increasing numeric order of mask, then in increasing numeric order
of opcode. This order is not the clearest for a human reader, but
is guaranteed never to catch a special-case bit pattern with a more
general mask, which is important, because this instruction encoding
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
{ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
{ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
{ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
{ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
{ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
/* Instructions defined in the basic V6T2 set. */
{ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
{ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
{ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
{ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
{ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
{ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
{ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
{ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
{ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
{ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
{ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
{ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"},
{ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
{ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
{ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
{ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
{ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
{ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
{ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
{ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
{ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
{ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
{ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
{ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
{ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
{ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
{ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
{ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
{ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
{ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
{ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
{ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
{ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
{ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
{ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
{ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
{ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
{ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
{ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
{ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
{ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
{ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
{ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
{ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
{ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
{ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
{ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
{ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
{ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
{ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
{ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
{ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
{ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
{ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
{ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
{ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
{ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
{ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
{ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
{ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
{ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
{ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
{ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
{ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
{ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
{ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
{ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
{ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
{ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
{ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
{ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
{ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
{ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
{ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
{ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
{ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
{ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
{ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
{ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
/* Filter out Bcc with cond=E or F, which are used for other instructions. */
{ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
{ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
{ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
{ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
/* These have been 32-bit since the invention of Thumb. */
{ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"},
{ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
/* Fallback. */
{ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
{0, 0, 0, 0}
};
static const char *const arm_conditional[] =
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
"hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
static const char *const arm_fp_const[] =
{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
static const char *const arm_shift[] =
{"lsl", "lsr", "asr", "ror"};
typedef struct
{
const char *name;
const char *description;
const char *reg_names[16];
}
arm_regname;
static const arm_regname regnames[] =
{
{ "raw" , "Select raw register names",
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
{ "gcc", "Select register names used by GCC",
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
{ "std", "Select register names used in ARM's ISA documentation",
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
{ "apcs", "Select register names used in the APCS",
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
{ "atpcs", "Select register names used in the ATPCS",
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
{ "special-atpcs", "Select special register names used in the ATPCS",
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
};
static const char *const iwmmxt_wwnames[] =
{"b", "h", "w", "d"};
static const char *const iwmmxt_wwssnames[] =
{"b", "bus", "bc", "bss",
"h", "hus", "hc", "hss",
"w", "wus", "wc", "wss",
"d", "dus", "dc", "dss"
};
static const char *const iwmmxt_regnames[] =
{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
"wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
};
static const char *const iwmmxt_cregnames[] =
{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
"wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
};
/* Default to GCC register name set. */
static unsigned int regname_selected = 1;
#define arm_regnames regnames[regname_selected].reg_names
static bfd_boolean force_thumb = false;
/* Current IT instruction state. This contains the same state as the IT
bits in the CPSR. */
static unsigned int ifthen_state;
/* IT state for the next instruction. */
static unsigned int ifthen_next_state;
/* The address of the insn for which the IT state is valid. */
static bfd_vma ifthen_address;
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
/* Cached mapping symbol state. */
enum map_type {
MAP_ARM,
MAP_THUMB,
MAP_DATA
};
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
Returns pointer to following character of the format string and
fills in *VALUEP and *WIDTHP with the extracted value and number of
bits extracted. WIDTHP can be NULL. */
static const char *
arm_decode_bitfield (const char *ptr, unsigned long insn,
unsigned long *valuep, int *widthp)
{
unsigned long value = 0;
int width = 0;
do
{
int start, end;
int bits;
for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
start = start * 10 + *ptr - '0';
if (*ptr == '-')
for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
end = end * 10 + *ptr - '0';
else
end = start;
bits = end - start;
if (bits < 0)
abort ();
value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
width += bits + 1;
}
while (*ptr++ == ',');
*valuep = value;
if (widthp)
*widthp = width;
return ptr - 1;
}
static void
arm_decode_shift (long given, fprintf_function func, void *stream,
int print_shift)
{
func (stream, "%s", arm_regnames[given & 0xf]);
if ((given & 0xff0) != 0)
{
if ((given & 0x10) == 0)
{
int amount = (given & 0xf80) >> 7;
int shift = (given & 0x60) >> 5;
if (amount == 0)
{
if (shift == 3)
{
func (stream, ", rrx");
return;
}
amount = 32;
}
if (print_shift)
func (stream, ", %s #%d", arm_shift[shift], amount);
else
func (stream, ", #%d", amount);
}
else if (print_shift)
func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
arm_regnames[(given & 0xf00) >> 8]);
else
func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
}
}
/* Print one coprocessor instruction on INFO->STREAM.
Return true if the instruction matched, false if this is not a
recognised coprocessor instruction. */
static bfd_boolean
print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
bfd_boolean thumb)
{
const struct opcode32 *insn;
void *stream = info->stream;
fprintf_function func = info->fprintf_func;
unsigned long mask;
unsigned long value;
int cond;
for (insn = coprocessor_opcodes; insn->assembler; insn++)
{
if (insn->value == FIRST_IWMMXT_INSN
&& info->mach != bfd_mach_arm_XScale
&& info->mach != bfd_mach_arm_iWMMXt
&& info->mach != bfd_mach_arm_iWMMXt2)
insn = insn + IWMMXT_INSN_COUNT;
mask = insn->mask;
value = insn->value;
if (thumb)
{
/* The high 4 bits are 0xe for Arm conditional instructions, and
0xe for arm unconditional instructions. The rest of the
encoding is the same. */
mask |= 0xf0000000;
value |= 0xe0000000;
if (ifthen_state)
cond = IFTHEN_COND;
else
cond = 16;
}
else
{
/* Only match unconditional instructions against unconditional
patterns. */
if ((given & 0xf0000000) == 0xf0000000)
{
mask |= 0xf0000000;
cond = 16;
}
else
{
cond = (given >> 28) & 0xf;
if (cond == 0xe)
cond = 16;
}
}
if ((given & mask) == value)
{
const char *c;
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case '%':
func (stream, "%%");
break;
case 'A':
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if ((given & (1 << 24)) != 0)
{
int offset = given & 0xff;
if (offset)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4,
((given & 0x00200000) != 0 ? "!" : ""));
else
func (stream, "]");
}
else
{
int offset = given & 0xff;
func (stream, "]");
if (given & (1 << 21))
{
if (offset)
func (stream, ", #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4);
}
else
func (stream, ", {%d}", offset);
}
break;
case 'B':
{
int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
int offset = (given >> 1) & 0x3f;
if (offset == 1)
func (stream, "{d%d}", regno);
else if (regno + offset > 32)
func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
else
func (stream, "{d%d-d%d}", regno, regno + offset - 1);
}
break;
case 'C':
{
int rn = (given >> 16) & 0xf;
int offset = (given & 0xff) * 4;
int add = (given >> 23) & 1;
func (stream, "[%s", arm_regnames[rn]);
if (offset)
{
if (!add)
offset = -offset;
func (stream, ", #%d", offset);
}
func (stream, "]");
if (rn == 15)
{
func (stream, "\t; ");
/* FIXME: Unsure if info->bytes_per_chunk is the
right thing to use here. */
info->print_address_func (offset + pc
+ info->bytes_per_chunk * 2, info);
}
}
break;
case 'c':
func (stream, "%s", arm_conditional[cond]);
break;
case 'I':
/* Print a Cirrus/DSP shift immediate. */
/* Immediates are 7bit signed ints with bits 0..3 in
bits 0..3 of opcode and bits 4..6 in bits 5..7
of opcode. */
{
int imm;
imm = (given & 0xf) | ((given & 0xe0) >> 1);
/* Is ``imm'' a negative number? */
if (imm & 0x40)
imm |= (~0u << 7);
func (stream, "%d", imm);
}
break;
case 'F':
switch (given & 0x00408000)
{
case 0:
func (stream, "4");
break;
case 0x8000:
func (stream, "1");
break;
case 0x00400000:
func (stream, "2");
break;
default:
func (stream, "3");
}
break;
case 'P':
switch (given & 0x00080080)
{
case 0:
func (stream, "s");
break;
case 0x80:
func (stream, "d");
break;
case 0x00080000:
func (stream, "e");
break;
default:
func (stream, "<illegal precision>");
break;
}
break;
case 'Q':
switch (given & 0x00408000)
{
case 0:
func (stream, "s");
break;
case 0x8000:
func (stream, "d");
break;
case 0x00400000:
func (stream, "e");
break;
default:
func (stream, "p");
break;
}
break;
case 'R':
switch (given & 0x60)
{
case 0:
break;
case 0x20:
func (stream, "p");
break;
case 0x40:
func (stream, "m");
break;
default:
func (stream, "z");
break;
}
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int width;
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
switch (*c)
{
case 'r':
func (stream, "%s", arm_regnames[value]);
break;
case 'D':
func (stream, "d%ld", value);
break;
case 'Q':
if (value & 1)
func (stream, "<illegal reg q%ld.5>", value >> 1);
else
func (stream, "q%ld", value >> 1);
break;
case 'd':
func (stream, "%ld", value);
break;
case 'k':
{
int from = (given & (1 << 7)) ? 32 : 16;
func (stream, "%ld", from - value);
}
break;
case 'f':
if (value > 7)
func (stream, "#%s", arm_fp_const[value & 7]);
else
func (stream, "f%ld", value);
break;
case 'w':
if (width == 2)
func (stream, "%s", iwmmxt_wwnames[value]);
else
func (stream, "%s", iwmmxt_wwssnames[value]);
break;
case 'g':
func (stream, "%s", iwmmxt_regnames[value]);
break;
case 'G':
func (stream, "%s", iwmmxt_cregnames[value]);
break;
case 'x':
func (stream, "0x%lx", value);
break;
case '`':
c++;
if (value == 0)
func (stream, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
func (stream, "%c", *c);
break;
case '?':
func (stream, "%c", c[(1 << width) - (int)value]);
c += 1 << width;
break;
default:
abort ();
}
break;
case 'y':
case 'z':
{
int single = *c++ == 'y';
int regno;
switch (*c)
{
case '4': /* Sm pair */
func (stream, "{");
/* Fall through. */
case '0': /* Sm, Dm */
regno = given & 0x0000000f;
if (single)
{
regno <<= 1;
regno += (given >> 5) & 1;
}
else
regno += ((given >> 5) & 1) << 4;
break;
case '1': /* Sd, Dd */
regno = (given >> 12) & 0x0000000f;
if (single)
{
regno <<= 1;
regno += (given >> 22) & 1;
}
else
regno += ((given >> 22) & 1) << 4;
break;
case '2': /* Sn, Dn */
regno = (given >> 16) & 0x0000000f;
if (single)
{
regno <<= 1;
regno += (given >> 7) & 1;
}
else
regno += ((given >> 7) & 1) << 4;
break;
case '3': /* List */
func (stream, "{");
regno = (given >> 12) & 0x0000000f;
if (single)
{
regno <<= 1;
regno += (given >> 22) & 1;
}
else
regno += ((given >> 22) & 1) << 4;
break;
default:
abort ();
}
func (stream, "%c%d", single ? 's' : 'd', regno);
if (*c == '3')
{
int count = given & 0xff;
if (single == 0)
count >>= 1;
if (--count)
{
func (stream, "-%c%d",
single ? 's' : 'd',
regno + count);
}
func (stream, "}");
}
else if (*c == '4')
func (stream, ", %c%d}", single ? 's' : 'd',
regno + 1);
}
break;
case 'L':
switch (given & 0x00400100)
{
case 0x00000000: func (stream, "b"); break;
case 0x00400000: func (stream, "h"); break;
case 0x00000100: func (stream, "w"); break;
case 0x00400100: func (stream, "d"); break;
default:
break;
}
break;
case 'Z':
{
int value;
/* given (20, 23) | given (0, 3) */
value = ((given >> 16) & 0xf0) | (given & 0xf);
func (stream, "%d", value);
}
break;
case 'l':
/* This is like the 'A' operator, except that if
the width field "M" is zero, then the offset is
*not* multiplied by four. */
{
int offset = given & 0xff;
int multiplier = (given & 0x00000100) ? 4 : 1;
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if (offset)
{
if ((given & 0x01000000) != 0)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * multiplier,
((given & 0x00200000) != 0 ? "!" : ""));
else
func (stream, "], #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * multiplier);
}
else
func (stream, "]");
}
break;
case 'r':
{
int imm4 = (given >> 4) & 0xf;
int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1);
int ubit = (given >> 23) & 1;
const char *rm = arm_regnames [given & 0xf];
const char *rn = arm_regnames [(given >> 16) & 0xf];
switch (puw_bits)
{
case 1:
/* fall through */
case 3:
func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
if (imm4)
func (stream, ", lsl #%d", imm4);
break;
case 4:
/* fall through */
case 5:
/* fall through */
case 6:
/* fall through */
case 7:
func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
if (imm4 > 0)
func (stream, ", lsl #%d", imm4);
func (stream, "]");
if (puw_bits == 5 || puw_bits == 7)
func (stream, "!");
break;
default:
func (stream, "INVALID");
}
}
break;
case 'i':
{
long imm5;
imm5 = ((given & 0x100) >> 4) | (given & 0xf);
func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
}
break;
default:
abort ();
}
}
}
else
func (stream, "%c", *c);
}
return true;
}
}
return false;
}
static void
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
void *stream = info->stream;
fprintf_function func = info->fprintf_func;
if (((given & 0x000f0000) == 0x000f0000)
&& ((given & 0x02000000) == 0))
{
int offset = given & 0xfff;
func (stream, "[pc");
if (given & 0x01000000)
{
if ((given & 0x00800000) == 0)
offset = - offset;
/* Pre-indexed. */
func (stream, ", #%d]", offset);
offset += pc + 8;
/* Cope with the possibility of write-back
being used. Probably a very dangerous thing
for the programmer to do, but who are we to
argue ? */
if (given & 0x00200000)
func (stream, "!");
}
else
{
/* Post indexed. */
func (stream, "], #%d", offset);
/* ie ignore the offset. */
offset = pc + 8;
}
func (stream, "\t; ");
info->print_address_func (offset, info);
}
else
{
func (stream, "[%s",
arm_regnames[(given >> 16) & 0xf]);
if ((given & 0x01000000) != 0)
{
if ((given & 0x02000000) == 0)
{
int offset = given & 0xfff;
if (offset)
func (stream, ", #%s%d",
(((given & 0x00800000) == 0)
? "-" : ""), offset);
}
else
{
func (stream, ", %s",
(((given & 0x00800000) == 0)
? "-" : ""));
arm_decode_shift (given, func, stream, 1);
}
func (stream, "]%s",
((given & 0x00200000) != 0) ? "!" : "");
}
else
{
if ((given & 0x02000000) == 0)
{
int offset = given & 0xfff;
if (offset)
func (stream, "], #%s%d",
(((given & 0x00800000) == 0)
? "-" : ""), offset);
else
func (stream, "]");
}
else
{
func (stream, "], %s",
(((given & 0x00800000) == 0)
? "-" : ""));
arm_decode_shift (given, func, stream, 1);
}
}
}
}
/* Print one neon instruction on INFO->STREAM.
Return true if the instruction matched, false if this is not a
recognised neon instruction. */
static bfd_boolean
print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
const struct opcode32 *insn;
void *stream = info->stream;
fprintf_function func = info->fprintf_func;
if (thumb)
{
if ((given & 0xef000000) == 0xef000000)
{
/* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
unsigned long bit28 = given & (1 << 28);
given &= 0x00ffffff;
if (bit28)
given |= 0xf3000000;
else
given |= 0xf2000000;
}
else if ((given & 0xff000000) == 0xf9000000)
given ^= 0xf9000000 ^ 0xf4000000;
else
return false;
}
for (insn = neon_opcodes; insn->assembler; insn++)
{
if ((given & insn->mask) == insn->value)
{
const char *c;
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case '%':
func (stream, "%%");
break;
case 'c':
if (thumb && ifthen_state)
func (stream, "%s", arm_conditional[IFTHEN_COND]);
break;
case 'A':
{
static const unsigned char enc[16] =
{
0x4, 0x14, /* st4 0,1 */
0x4, /* st1 2 */
0x4, /* st2 3 */
0x3, /* st3 4 */
0x13, /* st3 5 */
0x3, /* st1 6 */
0x1, /* st1 7 */
0x2, /* st2 8 */
0x12, /* st2 9 */
0x2, /* st1 10 */
0, 0, 0, 0, 0
};
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
int rn = ((given >> 16) & 0xf);
int rm = ((given >> 0) & 0xf);
int align = ((given >> 4) & 0x3);
int type = ((given >> 8) & 0xf);
int n = enc[type] & 0xf;
int stride = (enc[type] >> 4) + 1;
int ix;
func (stream, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
else if (n == 1)
func (stream, "d%d", rd);
else
func (stream, "d%d-d%d", rd, rd + n - 1);
func (stream, "}, [%s", arm_regnames[rn]);
if (align)
func (stream, ", :%d", 32 << align);
func (stream, "]");
if (rm == 0xd)
func (stream, "!");
else if (rm != 0xf)
func (stream, ", %s", arm_regnames[rm]);
}
break;
case 'B':
{
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
int rn = ((given >> 16) & 0xf);
int rm = ((given >> 0) & 0xf);
int idx_align = ((given >> 4) & 0xf);
int align = 0;
int size = ((given >> 10) & 0x3);
int idx = idx_align >> (size + 1);
int length = ((given >> 8) & 3) + 1;
int stride = 1;
int i;
if (length > 1 && size > 0)
stride = (idx_align & (1 << size)) ? 2 : 1;
switch (length)
{
case 1:
{
int amask = (1 << size) - 1;
if ((idx_align & (1 << size)) != 0)
return false;
if (size > 0)
{
if ((idx_align & amask) == amask)
align = 8 << size;
else if ((idx_align & amask) != 0)
return false;
}
}
break;
case 2:
if (size == 2 && (idx_align & 2) != 0)
return false;
align = (idx_align & 1) ? 16 << size : 0;
break;
case 3:
if ((size == 2 && (idx_align & 3) != 0)
|| (idx_align & 1) != 0)
return false;
break;
case 4:
if (size == 2)
{
if ((idx_align & 3) == 3)
return false;
align = (idx_align & 3) * 64;
}
else
align = (idx_align & 1) ? 32 << size : 0;
break;
default:
abort ();
}
func (stream, "{");
for (i = 0; i < length; i++)
func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
rd + i * stride, idx);
func (stream, "}, [%s", arm_regnames[rn]);
if (align)
func (stream, ", :%d", align);
func (stream, "]");
if (rm == 0xd)
func (stream, "!");
else if (rm != 0xf)
func (stream, ", %s", arm_regnames[rm]);
}
break;
case 'C':
{
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
int rn = ((given >> 16) & 0xf);
int rm = ((given >> 0) & 0xf);
int align = ((given >> 4) & 0x1);
int size = ((given >> 6) & 0x3);
int type = ((given >> 8) & 0x3);
int n = type + 1;
int stride = ((given >> 5) & 0x1);
int ix;
if (stride && (n == 1))
n++;
else
stride++;
func (stream, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
else if (n == 1)
func (stream, "d%d[]", rd);
else
func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
func (stream, "}, [%s", arm_regnames[rn]);
if (align)
{
int align = (8 * (type + 1)) << size;
if (type == 3)
align = (size > 1) ? align >> 1 : align;
if (type == 2 || (type == 0 && !size))
func (stream, ", :<bad align %d>", align);
else
func (stream, ", :%d", align);
}
func (stream, "]");
if (rm == 0xd)
func (stream, "!");
else if (rm != 0xf)
func (stream, ", %s", arm_regnames[rm]);
}
break;
case 'D':
{
int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
int size = (given >> 20) & 3;
int reg = raw_reg & ((4 << size) - 1);
int ix = raw_reg >> size >> 2;
func (stream, "d%d[%d]", reg, ix);
}
break;
case 'E':
/* Neon encoded constant for mov, mvn, vorr, vbic */
{
int bits = 0;
int cmode = (given >> 8) & 0xf;
int op = (given >> 5) & 0x1;
unsigned long value = 0, hival = 0;
unsigned shift;
int size = 0;
int isfloat = 0;
bits |= ((given >> 24) & 1) << 7;
bits |= ((given >> 16) & 7) << 4;
bits |= ((given >> 0) & 15) << 0;
if (cmode < 8)
{
shift = (cmode >> 1) & 3;
value = (unsigned long)bits << (8 * shift);
size = 32;
}
else if (cmode < 12)
{
shift = (cmode >> 1) & 1;
value = (unsigned long)bits << (8 * shift);
size = 16;
}
else if (cmode < 14)
{
shift = (cmode & 1) + 1;
value = (unsigned long)bits << (8 * shift);
value |= (1ul << (8 * shift)) - 1;
size = 32;
}
else if (cmode == 14)
{
if (op)
{
/* bit replication into bytes */
int ix;
unsigned long mask;
value = 0;
hival = 0;
for (ix = 7; ix >= 0; ix--)
{
mask = ((bits >> ix) & 1) ? 0xff : 0;
if (ix <= 3)
value = (value << 8) | mask;
else
hival = (hival << 8) | mask;
}
size = 64;
}
else
{
/* byte replication */
value = (unsigned long)bits;
size = 8;
}
}
else if (!op)
{
/* floating point encoding */
int tmp;
value = (unsigned long)(bits & 0x7f) << 19;
value |= (unsigned long)(bits & 0x80) << 24;
tmp = bits & 0x40 ? 0x3c : 0x40;
value |= (unsigned long)tmp << 24;
size = 32;
isfloat = 1;
}
else
{
func (stream, "<illegal constant %.8x:%x:%x>",
bits, cmode, op);
break;
}
switch (size)
{
case 8:
func (stream, "#%ld\t; 0x%.2lx", value, value);
break;
case 16:
func (stream, "#%ld\t; 0x%.4lx", value, value);
break;
case 32:
if (isfloat)
{
unsigned char valbytes[4];
double fvalue;
/* Do this a byte at a time so we don't have to
worry about the host's endianness. */
valbytes[0] = value & 0xff;
valbytes[1] = (value >> 8) & 0xff;
valbytes[2] = (value >> 16) & 0xff;
valbytes[3] = (value >> 24) & 0xff;
floatformat_to_double (valbytes, &fvalue);
func (stream, "#%.7g\t; 0x%.8lx", fvalue,
value);
}
else
func (stream, "#%ld\t; 0x%.8lx",
(long) ((value & 0x80000000)
? value | ~0xffffffffl : value), value);
break;
case 64:
func (stream, "#0x%.8lx%.8lx", hival, value);
break;
default:
abort ();
}
}
break;
case 'F':
{
int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
int num = (given >> 8) & 0x3;
if (!num)
func (stream, "{d%d}", regno);
else if (num + regno >= 32)
func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
else
func (stream, "{d%d-d%d}", regno, regno + num);
}
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int width;
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
switch (*c)
{
case 'r':
func (stream, "%s", arm_regnames[value]);
break;
case 'd':
func (stream, "%ld", value);
break;
case 'e':
func (stream, "%ld", (1ul << width) - value);
break;
case 'S':
case 'T':
case 'U':
/* various width encodings */
{
int base = 8 << (*c - 'S'); /* 8,16 or 32 */
int limit;
unsigned low, high;
c++;
if (*c >= '0' && *c <= '9')
limit = *c - '0';
else if (*c >= 'a' && *c <= 'f')
limit = *c - 'a' + 10;
else
abort ();
low = limit >> 2;
high = limit & 3;
if (value < low || value > high)
func (stream, "<illegal width %d>", base << value);
else
func (stream, "%d", base << value);
}
break;
case 'R':
if (given & (1 << 6))
goto Q;
/* FALLTHROUGH */
case 'D':
func (stream, "d%ld", value);
break;
case 'Q':
Q:
if (value & 1)
func (stream, "<illegal reg q%ld.5>", value >> 1);
else
func (stream, "q%ld", value >> 1);
break;
case '`':
c++;
if (value == 0)
func (stream, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
func (stream, "%c", *c);
break;
case '?':
func (stream, "%c", c[(1 << width) - (int)value]);
c += 1 << width;
break;
default:
abort ();
}
break;
default:
abort ();
}
}
}
else
func (stream, "%c", *c);
}
return true;
}
}
return false;
}
/* Print one ARM instruction from PC on INFO->STREAM. */
static void
print_insn_arm_internal (bfd_vma pc, struct disassemble_info *info, long given)
{
const struct opcode32 *insn;
void *stream = info->stream;
fprintf_function func = info->fprintf_func;
if (print_insn_coprocessor (pc, info, given, false))
return;
if (print_insn_neon (info, given, false))
return;
for (insn = arm_opcodes; insn->assembler; insn++)
{
if (insn->value == FIRST_IWMMXT_INSN
&& info->mach != bfd_mach_arm_XScale
&& info->mach != bfd_mach_arm_iWMMXt)
insn = insn + IWMMXT_INSN_COUNT;
if ((given & insn->mask) == insn->value
/* Special case: an instruction with all bits set in the condition field
(0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
or by the catchall at the end of the table. */
&& ((given & 0xF0000000) != 0xF0000000
|| (insn->mask & 0xF0000000) == 0xF0000000
|| (insn->mask == 0 && insn->value == 0)))
{
const char *c;
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case '%':
func (stream, "%%");
break;
case 'a':
print_arm_address (pc, info, given);
break;
case 'P':
/* Set P address bit and use normal address
printing routine. */
print_arm_address (pc, info, given | (1 << 24));
break;
case 's':
if ((given & 0x004f0000) == 0x004f0000)
{
/* PC relative with immediate offset. */
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
if ((given & 0x00800000) == 0)
offset = -offset;
func (stream, "[pc, #%d]\t; ", offset);
info->print_address_func (offset + pc + 8, info);
}
else
{
func (stream, "[%s",
arm_regnames[(given >> 16) & 0xf]);
if ((given & 0x01000000) != 0)
{
/* Pre-indexed. */
if ((given & 0x00400000) == 0x00400000)
{
/* Immediate. */
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
if (offset)
func (stream, ", #%s%d",
(((given & 0x00800000) == 0)
? "-" : ""), offset);
}
else
{
/* Register. */
func (stream, ", %s%s",
(((given & 0x00800000) == 0)
? "-" : ""),
arm_regnames[given & 0xf]);
}
func (stream, "]%s",
((given & 0x00200000) != 0) ? "!" : "");
}
else
{
/* Post-indexed. */
if ((given & 0x00400000) == 0x00400000)
{
/* Immediate. */
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
if (offset)
func (stream, "], #%s%d",
(((given & 0x00800000) == 0)
? "-" : ""), offset);
else
func (stream, "]");
}
else
{
/* Register. */
func (stream, "], %s%s",
(((given & 0x00800000) == 0)
? "-" : ""),
arm_regnames[given & 0xf]);
}
}
}
break;
case 'b':
{
int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
info->print_address_func (disp*4 + pc + 8, info);
}
break;
case 'c':
if (((given >> 28) & 0xf) != 0xe)
func (stream, "%s",
arm_conditional [(given >> 28) & 0xf]);
break;
case 'm':
{
int started = 0;
int reg;
func (stream, "{");
for (reg = 0; reg < 16; reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
func (stream, ", ");
started = 1;
func (stream, "%s", arm_regnames[reg]);
}
func (stream, "}");
}
break;
case 'q':
arm_decode_shift (given, func, stream, 0);
break;
case 'o':
if ((given & 0x02000000) != 0)
{
int rotate = (given & 0xf00) >> 7;
int immed = (given & 0xff);
immed = (((immed << (32 - rotate))
| (immed >> rotate)) & 0xffffffff);
func (stream, "#%d\t; 0x%x", immed, immed);
}
else
arm_decode_shift (given, func, stream, 1);
break;
case 'p':
if ((given & 0x0000f000) == 0x0000f000)
func (stream, "p");
break;
case 't':
if ((given & 0x01200000) == 0x00200000)
func (stream, "t");
break;
case 'A':
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if ((given & (1 << 24)) != 0)
{
int offset = given & 0xff;
if (offset)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4,
((given & 0x00200000) != 0 ? "!" : ""));
else
func (stream, "]");
}
else
{
int offset = given & 0xff;
func (stream, "]");
if (given & (1 << 21))
{
if (offset)
func (stream, ", #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4);
}
else
func (stream, ", {%d}", offset);
}
break;
case 'B':
/* Print ARM V5 BLX(1) address: pc+25 bits. */
{
bfd_vma address;
bfd_vma offset = 0;
if (given & 0x00800000)
/* Is signed, hi bits should be ones. */
offset = (-1) ^ 0x00ffffff;
/* Offset is (SignExtend(offset field)<<2). */
offset += given & 0x00ffffff;
offset <<= 2;
address = offset + pc + 8;
if (given & 0x01000000)
/* H bit allows addressing to 2-byte boundaries. */
address += 2;
info->print_address_func (address, info);
}
break;
case 'C':
func (stream, "_");
if (given & 0x80000)
func (stream, "f");
if (given & 0x40000)
func (stream, "s");
if (given & 0x20000)
func (stream, "x");
if (given & 0x10000)
func (stream, "c");
break;
case 'U':
switch (given & 0xf)
{
case 0xf: func(stream, "sy"); break;
case 0x7: func(stream, "un"); break;
case 0xe: func(stream, "st"); break;
case 0x6: func(stream, "unst"); break;
default:
func(stream, "#%d", (int)given & 0xf);
break;
}
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int width;
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
switch (*c)
{
case 'r':
func (stream, "%s", arm_regnames[value]);
break;
case 'd':
func (stream, "%ld", value);
break;
case 'b':
func (stream, "%ld", value * 8);
break;
case 'W':
func (stream, "%ld", value + 1);
break;
case 'x':
func (stream, "0x%08lx", value);
/* Some SWI instructions have special
meanings. */
if ((given & 0x0fffffff) == 0x0FF00000)
func (stream, "\t; IMB");
else if ((given & 0x0fffffff) == 0x0FF00001)
func (stream, "\t; IMBRange");
break;
case 'X':
func (stream, "%01lx", value & 0xf);
break;
case '`':
c++;
if (value == 0)
func (stream, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
func (stream, "%c", *c);
break;
case '?':
func (stream, "%c", c[(1 << width) - (int)value]);
c += 1 << width;
break;
default:
abort ();
}
break;
case 'e':
{
int imm;
imm = (given & 0xf) | ((given & 0xfff00) >> 4);
func (stream, "%d", imm);
}
break;
case 'E':
/* LSB and WIDTH fields of BFI or BFC. The machine-
language instruction encodes LSB and MSB. */
{
long msb = (given & 0x001f0000) >> 16;
long lsb = (given & 0x00000f80) >> 7;
long width = msb - lsb + 1;
if (width > 0)
func (stream, "#%lu, #%lu", lsb, width);
else
func (stream, "(invalid: %lu:%lu)", lsb, msb);
}
break;
case 'V':
/* 16-bit unsigned immediate from a MOVT or MOVW
instruction, encoded in bits 0:11 and 15:19. */
{
long hi = (given & 0x000f0000) >> 4;
long lo = (given & 0x00000fff);
long imm16 = hi | lo;
func (stream, "#%lu\t; 0x%lx", imm16, imm16);
}
break;
default:
abort ();
}
}
}
else
func (stream, "%c", *c);
}
return;
}
}
abort ();
}
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
static void
print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
{
const struct opcode16 *insn;
void *stream = info->stream;
fprintf_function func = info->fprintf_func;
for (insn = thumb_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
const char *c = insn->assembler;
for (; *c; c++)
{
int domaskpc = 0;
int domasklr = 0;
if (*c != '%')
{
func (stream, "%c", *c);
continue;
}
switch (*++c)
{
case '%':
func (stream, "%%");
break;
case 'c':
if (ifthen_state)
func (stream, "%s", arm_conditional[IFTHEN_COND]);
break;
case 'C':
if (ifthen_state)
func (stream, "%s", arm_conditional[IFTHEN_COND]);
else
func (stream, "s");
break;
case 'I':
{
unsigned int tmp;
ifthen_next_state = given & 0xff;
for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
}
break;
case 'x':
if (ifthen_next_state)
func (stream, "\t; unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
func (stream, "\t; unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
case 'S':
{
long reg;
reg = (given >> 3) & 0x7;
if (given & (1 << 6))
reg += 8;
func (stream, "%s", arm_regnames[reg]);
}
break;
case 'D':
{
long reg;
reg = given & 0x7;
if (given & (1 << 7))
reg += 8;
func (stream, "%s", arm_regnames[reg]);
}
break;
case 'N':
if (given & (1 << 8))
domasklr = 1;
/* Fall through. */
case 'O':
if (*c == 'O' && (given & (1 << 8)))
domaskpc = 1;
/* Fall through. */
case 'M':
{
int started = 0;
int reg;
func (stream, "{");
/* It would be nice if we could spot
ranges, and generate the rS-rE format: */
for (reg = 0; (reg < 8); reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
func (stream, ", ");
started = 1;
func (stream, "%s", arm_regnames[reg]);
}
if (domasklr)
{
if (started)
func (stream, ", ");
started = 1;
func (stream, "%s", arm_regnames[14] /* "lr" */);
}
if (domaskpc)
{
if (started)
func (stream, ", ");
func (stream, "%s", arm_regnames[15] /* "pc" */);
}
func (stream, "}");
}
break;
case 'b':
/* Print ARM V6T2 CZB address: pc+4+6 bits. */
{
bfd_vma address = (pc + 4
+ ((given & 0x00f8) >> 2)
+ ((given & 0x0200) >> 3));
info->print_address_func (address, info);
}
break;
case 's':
/* Right shift immediate -- bits 6..10; 1-31 print
as themselves, 0 prints as 32. */
{
long imm = (given & 0x07c0) >> 6;
if (imm == 0)
imm = 32;
func (stream, "#%ld", imm);
}
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int bitstart = *c++ - '0';
int bitend = 0;
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
{
long reg;
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
if (!bitend)
abort ();
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
switch (*c)
{
case 'r':
func (stream, "%s", arm_regnames[reg]);
break;
case 'd':
func (stream, "%ld", reg);
break;
case 'H':
func (stream, "%ld", reg << 1);
break;
case 'W':
func (stream, "%ld", reg << 2);
break;
case 'a':
/* PC-relative address -- the bottom two
bits of the address are dropped
before the calculation. */
info->print_address_func
(((pc + 4) & ~3) + (reg << 2), info);
break;
case 'x':
func (stream, "0x%04lx", reg);
break;
case 'B':
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
info->print_address_func (reg * 2 + pc + 4, info);
break;
case 'c':
func (stream, "%s", arm_conditional [reg]);
break;
default:
abort ();
}
}
break;
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
func (stream, "%c", *c);
break;
case '?':
++c;
if ((given & (1 << bitstart)) != 0)
func (stream, "%c", *c++);
else
func (stream, "%c", *++c);
break;
default:
abort ();
}
}
break;
default:
abort ();
}
}
return;
}
/* No match. */
abort ();
}
/* Return the name of an V7M special register. */
static const char *
psr_name (int regno)
{
switch (regno)
{
case 0: return "APSR";
case 1: return "IAPSR";
case 2: return "EAPSR";
case 3: return "PSR";
case 5: return "IPSR";
case 6: return "EPSR";
case 7: return "IEPSR";
case 8: return "MSP";
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
case 18: return "BASEPRI_MASK";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
}
}
/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
static void
print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
const struct opcode32 *insn;
void *stream = info->stream;
fprintf_function func = info->fprintf_func;
if (print_insn_coprocessor (pc, info, given, true))
return;
if (print_insn_neon (info, given, true))
return;
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
const char *c = insn->assembler;
for (; *c; c++)
{
if (*c != '%')
{
func (stream, "%c", *c);
continue;
}
switch (*++c)
{
case '%':
func (stream, "%%");
break;
case 'c':
if (ifthen_state)
func (stream, "%s", arm_conditional[IFTHEN_COND]);
break;
case 'x':
if (ifthen_next_state)
func (stream, "\t; unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
func (stream, "\t; unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
case 'I':
{
unsigned int imm12 = 0;
imm12 |= (given & 0x000000ffu);
imm12 |= (given & 0x00007000u) >> 4;
imm12 |= (given & 0x04000000u) >> 15;
func (stream, "#%u\t; 0x%x", imm12, imm12);
}
break;
case 'M':
{
unsigned int bits = 0, imm, imm8, mod;
bits |= (given & 0x000000ffu);
bits |= (given & 0x00007000u) >> 4;
bits |= (given & 0x04000000u) >> 15;
imm8 = (bits & 0x0ff);
mod = (bits & 0xf00) >> 8;
switch (mod)
{
case 0: imm = imm8; break;
case 1: imm = ((imm8<<16) | imm8); break;
case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
default:
mod = (bits & 0xf80) >> 7;
imm8 = (bits & 0x07f) | 0x80;
imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
}
func (stream, "#%u\t; 0x%x", imm, imm);
}
break;
case 'J':
{
unsigned int imm = 0;
imm |= (given & 0x000000ffu);
imm |= (given & 0x00007000u) >> 4;
imm |= (given & 0x04000000u) >> 15;
imm |= (given & 0x000f0000u) >> 4;
func (stream, "#%u\t; 0x%x", imm, imm);
}
break;
case 'K':
{
unsigned int imm = 0;
imm |= (given & 0x000f0000u) >> 16;
imm |= (given & 0x00000ff0u) >> 0;
imm |= (given & 0x0000000fu) << 12;
func (stream, "#%u\t; 0x%x", imm, imm);
}
break;
case 'S':
{
unsigned int reg = (given & 0x0000000fu);
unsigned int stp = (given & 0x00000030u) >> 4;
unsigned int imm = 0;
imm |= (given & 0x000000c0u) >> 6;
imm |= (given & 0x00007000u) >> 10;
func (stream, "%s", arm_regnames[reg]);
switch (stp)
{
case 0:
if (imm > 0)
func (stream, ", lsl #%u", imm);
break;
case 1:
if (imm == 0)
imm = 32;
func (stream, ", lsr #%u", imm);
break;
case 2:
if (imm == 0)
imm = 32;
func (stream, ", asr #%u", imm);
break;
case 3:
if (imm == 0)
func (stream, ", rrx");
else
func (stream, ", ror #%u", imm);
}
}
break;
case 'a':
{
unsigned int Rn = (given & 0x000f0000) >> 16;
unsigned int U = (given & 0x00800000) >> 23;
unsigned int op = (given & 0x00000f00) >> 8;
unsigned int i12 = (given & 0x00000fff);
unsigned int i8 = (given & 0x000000ff);
bfd_boolean writeback = false, postind = false;
int offset = 0;
func (stream, "[%s", arm_regnames[Rn]);
if (U) /* 12-bit positive immediate offset */
offset = i12;
else if (Rn == 15) /* 12-bit negative immediate offset */
offset = -(int)i12;
else if (op == 0x0) /* shifted register offset */
{
unsigned int Rm = (i8 & 0x0f);
unsigned int sh = (i8 & 0x30) >> 4;
func (stream, ", %s", arm_regnames[Rm]);
if (sh)
func (stream, ", lsl #%u", sh);
func (stream, "]");
break;
}
else switch (op)
{
case 0xE: /* 8-bit positive immediate offset */
offset = i8;
break;
case 0xC: /* 8-bit negative immediate offset */
offset = -i8;
break;
case 0xF: /* 8-bit + preindex with wb */
offset = i8;
writeback = true;
break;
case 0xD: /* 8-bit - preindex with wb */
offset = -i8;
writeback = true;
break;
case 0xB: /* 8-bit + postindex */
offset = i8;
postind = true;
break;
case 0x9: /* 8-bit - postindex */
offset = -i8;
postind = true;
break;
default:
func (stream, ", <undefined>]");
goto skip;
}
if (postind)
func (stream, "], #%d", offset);
else
{
if (offset)
func (stream, ", #%d", offset);
func (stream, writeback ? "]!" : "]");
}
if (Rn == 15)
{
func (stream, "\t; ");
info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
skip:
break;
case 'A':
{
unsigned int P = (given & 0x01000000) >> 24;
unsigned int U = (given & 0x00800000) >> 23;
unsigned int W = (given & 0x00400000) >> 21;
unsigned int Rn = (given & 0x000f0000) >> 16;
unsigned int off = (given & 0x000000ff);
func (stream, "[%s", arm_regnames[Rn]);
if (P)
{
if (off || !U)
func (stream, ", #%c%u", U ? '+' : '-', off * 4);
func (stream, "]");
if (W)
func (stream, "!");
}
else
{
func (stream, "], ");
if (W)
func (stream, "#%c%u", U ? '+' : '-', off * 4);
else
func (stream, "{%u}", off);
}
}
break;
case 'w':
{
unsigned int Sbit = (given & 0x01000000) >> 24;
unsigned int type = (given & 0x00600000) >> 21;
switch (type)
{
case 0: func (stream, Sbit ? "sb" : "b"); break;
case 1: func (stream, Sbit ? "sh" : "h"); break;
case 2:
if (Sbit)
func (stream, "??");
break;
case 3:
func (stream, "??");
break;
}
}
break;
case 'm':
{
int started = 0;
int reg;
func (stream, "{");
for (reg = 0; reg < 16; reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
func (stream, ", ");
started = 1;
func (stream, "%s", arm_regnames[reg]);
}
func (stream, "}");
}
break;
case 'E':
{
unsigned int msb = (given & 0x0000001f);
unsigned int lsb = 0;
lsb |= (given & 0x000000c0u) >> 6;
lsb |= (given & 0x00007000u) >> 10;
func (stream, "#%u, #%u", lsb, msb - lsb + 1);
}
break;
case 'F':
{
unsigned int width = (given & 0x0000001f) + 1;
unsigned int lsb = 0;
lsb |= (given & 0x000000c0u) >> 6;
lsb |= (given & 0x00007000u) >> 10;
func (stream, "#%u, #%u", lsb, width);
}
break;
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
unsigned int J1 = (given & 0x00002000u) >> 13;
unsigned int J2 = (given & 0x00000800u) >> 11;
int offset = 0;
offset |= !S << 20;
offset |= J2 << 19;
offset |= J1 << 18;
offset |= (given & 0x003f0000) >> 4;
offset |= (given & 0x000007ff) << 1;
offset -= (1 << 20);
info->print_address_func (pc + 4 + offset, info);
}
break;
case 'B':
{
unsigned int S = (given & 0x04000000u) >> 26;
unsigned int I1 = (given & 0x00002000u) >> 13;
unsigned int I2 = (given & 0x00000800u) >> 11;
int offset = 0;
offset |= !S << 24;
offset |= !(I1 ^ S) << 23;
offset |= !(I2 ^ S) << 22;
offset |= (given & 0x03ff0000u) >> 4;
offset |= (given & 0x000007ffu) << 1;
offset -= (1 << 24);
offset += pc + 4;
/* BLX target addresses are always word aligned. */
if ((given & 0x00001000u) == 0)
offset &= ~2u;
info->print_address_func (offset, info);
}
break;
case 's':
{
unsigned int shift = 0;
shift |= (given & 0x000000c0u) >> 6;
shift |= (given & 0x00007000u) >> 10;
if (given & 0x00200000u)
func (stream, ", asr #%u", shift);
else if (shift)
func (stream, ", lsl #%u", shift);
/* else print nothing - lsl #0 */
}
break;
case 'R':
{
unsigned int rot = (given & 0x00000030) >> 4;
if (rot)
func (stream, ", ror #%u", rot * 8);
}
break;
case 'U':
switch (given & 0xf)
{
case 0xf: func(stream, "sy"); break;
case 0x7: func(stream, "un"); break;
case 0xe: func(stream, "st"); break;
case 0x6: func(stream, "unst"); break;
default:
func(stream, "#%d", (int)given & 0xf);
break;
}
break;
case 'C':
if ((given & 0xff) == 0)
{
func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
if (given & 0x800)
func (stream, "f");
if (given & 0x400)
func (stream, "s");
if (given & 0x200)
func (stream, "x");
if (given & 0x100)
func (stream, "c");
}
else
{
func (stream, "%s", psr_name (given & 0xff));
}
break;
case 'D':
if ((given & 0xff) == 0)
func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
else
func (stream, "%s", psr_name (given & 0xff));
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int width;
unsigned long val;
c = arm_decode_bitfield (c, given, &val, &width);
switch (*c)
{
case 'd': func (stream, "%lu", val); break;
case 'W': func (stream, "%lu", val * 4); break;
case 'r': func (stream, "%s", arm_regnames[val]); break;
case 'c':
func (stream, "%s", arm_conditional[val]);
break;
case '\'':
c++;
if (val == ((1ul << width) - 1))
func (stream, "%c", *c);
break;
case '`':
c++;
if (val == 0)
func (stream, "%c", *c);
break;
case '?':
func (stream, "%c", c[(1 << width) - (int)val]);
c += 1 << width;
break;
default:
abort ();
}
}
break;
default:
abort ();
}
}
return;
}
/* No match. */
abort ();
}
/* Print data bytes on INFO->STREAM. */
static void
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
long given)
{
switch (info->bytes_per_chunk)
{
case 1:
info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
break;
case 2:
info->fprintf_func (info->stream, ".short\t0x%04lx", given);
break;
case 4:
info->fprintf_func (info->stream, ".word\t0x%08lx", given);
break;
default:
abort ();
}
}
/* Search back through the insn stream to determine if this instruction is
conditionally executed. */
static void
find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
bfd_boolean little)
{
unsigned char b[2];
unsigned int insn;
int status;
/* COUNT is twice the number of instructions seen. It will be odd if we
just crossed an instruction boundary. */
int count;
int it_count;
unsigned int seen_it;
bfd_vma addr;
ifthen_address = pc;
ifthen_state = 0;
addr = pc;
count = 1;
it_count = 0;
seen_it = 0;
/* Scan backwards looking for IT instructions, keeping track of where
instruction boundaries are. We don't know if something is actually an
IT instruction until we find a definite instruction boundary. */
for (;;)
{
if (addr == 0 || info->symbol_at_address_func(addr, info))
{
/* A symbol must be on an instruction boundary, and will not
be within an IT block. */
if (seen_it && (count & 1))
break;
return;
}
addr -= 2;
status = arm_read_memory (addr, (bfd_byte *)b, 2, info);
if (status)
return;
if (little)
insn = (b[0]) | (b[1] << 8);
else
insn = (b[1]) | (b[0] << 8);
if (seen_it)
{
if ((insn & 0xf800) < 0xe800)
{
/* Addr + 2 is an instruction boundary. See if this matches
the expected boundary based on the position of the last
IT candidate. */
if (count & 1)
break;
seen_it = 0;
}
}
if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
{
/* This could be an IT instruction. */
seen_it = insn;
it_count = count >> 1;
}
if ((insn & 0xf800) >= 0xe800)
count++;
else
count = (count + 2) | 1;
/* IT blocks contain at most 4 instructions. */
if (count >= 8 && !seen_it)
return;
}
/* We found an IT instruction. */
ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
if ((ifthen_state & 0xf) == 0)
ifthen_state = 0;
}
/* NOTE: There are no checks in these routines that
the relevant number of data bytes exist. */
int
print_insn_arm (bfd_vma pc, struct disassemble_info *info)
{
unsigned char b[4];
long given;
int status;
int is_thumb = false;
int is_data = false;
unsigned int size = 4;
void (*printer) (bfd_vma, struct disassemble_info *, long);
int little;
little = (info->endian == BFD_ENDIAN_LITTLE);
is_thumb |= (pc & 1);
pc &= ~(bfd_vma)1;
if (force_thumb)
is_thumb = true;
info->bytes_per_line = 4;
if (is_data)
{
int i;
/* size was already set above. */
info->bytes_per_chunk = size;
printer = print_insn_data;
status = arm_read_memory (pc, (bfd_byte *)b, size, info);
given = 0;
if (little)
for (i = size - 1; i >= 0; i--)
given = b[i] | (given << 8);
else
for (i = 0; i < (int) size; i++)
given = b[i] | (given << 8);
}
else if (!is_thumb)
{
/* In ARM mode endianness is a straightforward issue: the instruction
is four bytes long and is either ordered 0123 or 3210. */
printer = print_insn_arm_internal;
info->bytes_per_chunk = 4;
size = 4;
status = arm_read_memory (pc, (bfd_byte *)b, 4, info);
if (little)
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned)b[3] << 24);
else
given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned)b[0] << 24);
}
else
{
/* In Thumb mode we have the additional wrinkle of two
instruction lengths. Fortunately, the bits that determine
the length of the current instruction are always to be found
in the first two bytes. */
printer = print_insn_thumb16;
info->bytes_per_chunk = 2;
size = 2;
status = arm_read_memory (pc, (bfd_byte *)b, 2, info);
if (little)
given = (b[0]) | (b[1] << 8);
else
given = (b[1]) | (b[0] << 8);
if (!status)
{
/* These bit patterns signal a four-byte Thumb
instruction. */
if ((given & 0xF800) == 0xF800
|| (given & 0xF800) == 0xF000
|| (given & 0xF800) == 0xE800)
{
status = arm_read_memory (pc + 2, (bfd_byte *)b, 2, info);
if (little)
given = (b[0]) | (b[1] << 8) | (given << 16);
else
given = (b[1]) | (b[0] << 8) | (given << 16);
printer = print_insn_thumb32;
size = 4;
}
}
if (ifthen_address != pc)
find_ifthen_state(pc, info, little);
if (ifthen_state)
{
if ((ifthen_state & 0xf) == 0x8)
ifthen_next_state = 0;
else
ifthen_next_state = (ifthen_state & 0xe0)
| ((ifthen_state & 0xf) << 1);
}
}
if (status)
{
info->memory_error_func (status, pc, info);
return -1;
}
if (info->flags & INSN_HAS_RELOC)
/* If the instruction has a reloc associated with it, then
the offset field in the instruction will actually be the
addend for the reloc. (We are using REL type relocs).
In such cases, we can ignore the pc when computing
addresses, since the addend is not currently pc-relative. */
pc = 0;
/* We include the hexdump of the instruction. The format here
matches that used by objdump and the ARM ARM (in particular,
32 bit Thumb instructions are displayed as pairs of halfwords,
not as a single word.) */
if (is_thumb)
{
if (size == 2)
{
info->fprintf_func(info->stream, "%04lx ",
((unsigned long)given) & 0xffff);
}
else
{
info->fprintf_func(info->stream, "%04lx %04lx ",
(((unsigned long)given) >> 16) & 0xffff,
((unsigned long)given) & 0xffff);
}
}
else
{
info->fprintf_func(info->stream, "%08lx ",
((unsigned long)given) & 0xffffffff);
}
printer (pc, info, given);
if (is_thumb)
{
ifthen_state = ifthen_next_state;
ifthen_address += size;
}
return size;
}
|
pmp-tool/PMP | src/qemu/src-pmp/roms/openbios/drivers/lsi.c | /*
* OpenBIOS LSI driver
*
* Copyright (C) 2018 <NAME> <<EMAIL>>
*
* Based upon drivers/esp.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2
*
*/
#include "config.h"
#include "libc/byteorder.h"
#include "libc/vsprintf.h"
#include "libopenbios/bindings.h"
#include "drivers/drivers.h"
#include "scsi.h"
typedef struct sd_private {
unsigned int bs;
const char *media_str[2];
uint32_t sectors;
uint8_t media;
uint8_t id;
uint8_t present;
char model[40];
} sd_private_t;
typedef struct lsi_table {
uint32_t id;
uint32_t id_addr;
uint32_t msg_out_len;
uint32_t msg_out_ptr;
uint32_t cmd_len;
uint32_t cmd_ptr;
uint32_t data_in_len;
uint32_t data_in_ptr;
uint32_t status_len;
uint32_t status_ptr;
uint32_t msg_in_len;
uint32_t msg_in_ptr;
} lsi_table_t;
typedef struct lsi_private {
volatile uint8_t *mmio;
uint32_t *scripts;
uint32_t *scripts_iova;
lsi_table_t *table;
lsi_table_t *table_iova;
volatile uint8_t *buffer;
volatile uint8_t *buffer_iova;
sd_private_t sd[8];
} lsi_private_t;
static lsi_private_t *global_lsi;
#ifdef CONFIG_DEBUG_LSI
#define DPRINTF(fmt, args...) \
do { printk(fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif
/* DECLARE data structures for the nodes. */
DECLARE_UNNAMED_NODE(ob_sd, INSTALL_OPEN, sizeof(sd_private_t *));
DECLARE_UNNAMED_NODE(ob_lsi, INSTALL_OPEN, sizeof(lsi_private_t **));
#ifdef CONFIG_DEBUG_LSI
static void dump_drive(sd_private_t *drive)
{
printk("SCSI DRIVE @%lx:\n", (unsigned long)drive);
printk("id: %d\n", drive->id);
printk("media: %s\n", drive->media_str[0]);
printk("media: %s\n", drive->media_str[1]);
printk("model: %s\n", drive->model);
printk("sectors: %d\n", drive->sectors);
printk("present: %d\n", drive->present);
printk("bs: %d\n", drive->bs);
}
#endif
#define PHASE_DO 0
#define PHASE_DI 1
#define PHASE_CMD 2
#define PHASE_ST 3
#define PHASE_MO 6
#define PHASE_MI 7
#define LSI_DSTAT 0x0c
#define LSI_DSA 0x10
#define LSI_ISTAT0 0x14
#define LSI_DSP 0x2c
#define LSI_SIST0 0x42
#define LSI_SIST1 0x43
#define LSI_ISTAT0_DIP 0x01
#define LSI_ISTAT0_SIP 0x02
/* Indirection table */
#define LSI_TABLE_OFFSET(x) (((uintptr_t)&(x)) - ((uintptr_t)lsi->table))
#define LSI_TABLE_MSG_OUT_OFFSET 0x0
#define LSI_TABLE_CMD_OFFSET 0x2
#define LSI_TABLE_DATA_OFFSET 0x20
#define LSI_TABLE_STATUS_OFFSET 0x10
#define LSI_TABLE_MSG_IN_OFFSET 0x12
static void
init_scripts(lsi_private_t *lsi)
{
/* Initialise SCRIPTS for the commands we are interested in */
/* 1 - INQUIRY / READ CAPACITY */
/* 1.0 Select with ATN */
lsi->scripts[0x0] = __cpu_to_le32(0x47000000);
lsi->scripts[0x1] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 1.1 Select LUN */
lsi->scripts[0x2] = __cpu_to_le32(0x10000000 | (PHASE_MO << 24));
lsi->scripts[0x3] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_out_len));
/* 1.2 Send command */
lsi->scripts[0x4] = __cpu_to_le32(0x10000000 | (PHASE_CMD << 24));
lsi->scripts[0x5] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->cmd_len));
/* 1.3 Data in */
lsi->scripts[0x6] = __cpu_to_le32(0x10000000 | (PHASE_DI << 24));
lsi->scripts[0x7] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->data_in_len));
/* 1.4 Status */
lsi->scripts[0x8] = __cpu_to_le32(0x10000000 | (PHASE_ST << 24));
lsi->scripts[0x9] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->status_len));
/* 1.5 Message in */
lsi->scripts[0xa] = __cpu_to_le32(0x10000000 | (PHASE_MI << 24));
lsi->scripts[0xb] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_in_len));
/* 1.6 Wait disconnect */
lsi->scripts[0xc] = __cpu_to_le32(0x48000000);
lsi->scripts[0xd] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 1.7 Interrupt */
lsi->scripts[0xe] = __cpu_to_le32(0x98080000);
lsi->scripts[0xf] = 0x0;
/* 2 - TEST UNIT READY */
/* 2.0 Select with ATN */
lsi->scripts[0x10] = __cpu_to_le32(0x47000000);
lsi->scripts[0x11] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 2.1 Select LUN */
lsi->scripts[0x12] = __cpu_to_le32(0x10000000 | (PHASE_MO << 24));
lsi->scripts[0x13] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_out_len));
/* 2.2 Send command */
lsi->scripts[0x14] = __cpu_to_le32(0x10000000 | (PHASE_CMD << 24));
lsi->scripts[0x15] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->cmd_len));
/* 2.3 Status */
lsi->scripts[0x16] = __cpu_to_le32(0x10000000 | (PHASE_ST << 24));
lsi->scripts[0x17] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->status_len));
/* 2.4 Message in */
lsi->scripts[0x18] = __cpu_to_le32(0x10000000 | (PHASE_MI << 24));
lsi->scripts[0x19] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_in_len));
/* 2.5 Wait disconnect */
lsi->scripts[0x1a] = __cpu_to_le32(0x48000000);
lsi->scripts[0x1b] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 2.6 Interrupt */
lsi->scripts[0x1c] = __cpu_to_le32(0x98080000);
lsi->scripts[0x1d] = 0x0;
/* 3 - READ 10 */
/* 3.0 Select with ATN */
lsi->scripts[0x20] = __cpu_to_le32(0x47000000);
lsi->scripts[0x21] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 3.1 Select LUN */
lsi->scripts[0x22] = __cpu_to_le32(0x10000000 | (PHASE_MO << 24));
lsi->scripts[0x23] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_out_len));
/* 3.2 Send command */
lsi->scripts[0x24] = __cpu_to_le32(0x10000000 | (PHASE_CMD << 24));
lsi->scripts[0x25] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->cmd_len));
/* 3.3 Message in */
lsi->scripts[0x26] = __cpu_to_le32(0x10000000 | (PHASE_MI << 24));
lsi->scripts[0x27] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_in_len));
/* 3.6 Interrupt */
lsi->scripts[0x28] = __cpu_to_le32(0x98080000);
lsi->scripts[0x29] = 0x0;
/* 3.7 Wait reselect */
lsi->scripts[0x2a] = __cpu_to_le32(0x50000000);
lsi->scripts[0x2b] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 3.8 Message in */
lsi->scripts[0x2c] = __cpu_to_le32(0x10000000 | (PHASE_MI << 24));
lsi->scripts[0x2d] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->msg_in_len));
/* 3.9 Data in */
lsi->scripts[0x2e] = __cpu_to_le32(0x10000000 | (PHASE_DI << 24));
lsi->scripts[0x2f] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->data_in_len));
/* 3.10 Wait disconnect */
lsi->scripts[0x30] = __cpu_to_le32(0x48000000);
lsi->scripts[0x31] = __cpu_to_le32(LSI_TABLE_OFFSET(lsi->table->id));
/* 3.11 Interrupt */
lsi->scripts[0x32] = __cpu_to_le32(0x98080000);
lsi->scripts[0x33] = 0x0;
}
static void
init_table(lsi_private_t *lsi)
{
uint32_t dsa;
/* Initialise indirect table */
lsi->table->msg_out_ptr = __cpu_to_le32((uintptr_t)&lsi->buffer_iova[LSI_TABLE_MSG_OUT_OFFSET]);
lsi->table->cmd_ptr = __cpu_to_le32((uintptr_t)&lsi->buffer_iova[LSI_TABLE_CMD_OFFSET]);
lsi->table->data_in_ptr = __cpu_to_le32((uintptr_t)&lsi->buffer_iova[LSI_TABLE_DATA_OFFSET]);
lsi->table->status_ptr = __cpu_to_le32((uintptr_t)&lsi->buffer_iova[LSI_TABLE_STATUS_OFFSET]);
lsi->table->msg_in_ptr = __cpu_to_le32((uintptr_t)&lsi->buffer_iova[LSI_TABLE_MSG_IN_OFFSET]);
/* Set the DSA to point to the base of our data table */
dsa = (uintptr_t)lsi->table_iova;
lsi->mmio[LSI_DSA] = dsa & 0xff;
lsi->mmio[LSI_DSA + 1] = (dsa >> 8) & 0xff;
lsi->mmio[LSI_DSA + 2] = (dsa >> 16) & 0xff;
lsi->mmio[LSI_DSA + 3] = (dsa >> 24) & 0xff;
}
static unsigned int
lsi_interrupt_status(lsi_private_t *lsi)
{
uint32_t istat, sist0, sist1, dstat;
/* Wait for interrupt status */
while ((istat = lsi->mmio[LSI_ISTAT0]) == 0);
if (istat & LSI_ISTAT0_SIP) {
/* If SCSI interrupt, clear SCSI interrupt registers */
sist0 = lsi->mmio[LSI_SIST0];
sist1 = lsi->mmio[LSI_SIST1];
if (sist0 != 0 || sist1 != 0) {
return 1;
}
}
if (istat & LSI_ISTAT0_DIP) {
/* If DMA interrupt, clear DMA interrupt register */
dstat = lsi->mmio[LSI_DSTAT];
if ((dstat & 0x7f) != 0x4) {
return 1;
}
}
return 0;
}
static unsigned int
inquiry(lsi_private_t *lsi, sd_private_t *sd)
{
const char *media[2] = { "UNKNOWN", "UNKNOWN"};
uint8_t *buffer;
// Setup command = Inquiry
memset((uint8_t *)&lsi->buffer[LSI_TABLE_CMD_OFFSET], 0, 7);
lsi->buffer[LSI_TABLE_MSG_OUT_OFFSET] = 0x80;
lsi->table->msg_out_len = __cpu_to_le32(0x1);
lsi->buffer[LSI_TABLE_CMD_OFFSET] = INQUIRY;
lsi->table->cmd_len = __cpu_to_le32(0x6);
lsi->buffer[LSI_TABLE_CMD_OFFSET + 4] = 36;
lsi->table->data_in_len = __cpu_to_le32(36);
lsi->table->status_len = __cpu_to_le32(0x1);
lsi->table->msg_in_len = __cpu_to_le32(0x1);
lsi->table->id = __cpu_to_le32((sd->id << 16));
lsi->table->id_addr = __cpu_to_le32(&lsi->scripts_iova[0x2]);
/* Write DSP to start DMA engine */
uint32_t dsp = (uintptr_t)lsi->scripts_iova;
lsi->mmio[LSI_DSP] = dsp & 0xff;
lsi->mmio[LSI_DSP + 1] = (dsp >> 8) & 0xff;
lsi->mmio[LSI_DSP + 2] = (dsp >> 16) & 0xff;
lsi->mmio[LSI_DSP + 3] = (dsp >> 24) & 0xff;
if (lsi_interrupt_status(lsi)) {
sd->present = 0;
sd->media = -1;
return 0;
}
buffer = (uint8_t *)&lsi->buffer[LSI_TABLE_DATA_OFFSET];
sd->present = 1;
sd->media = buffer[0];
switch (sd->media) {
case TYPE_DISK:
media[0] = "disk";
media[1] = "hd";
break;
case TYPE_ROM:
media[0] = "cdrom";
media[1] = "cd";
break;
}
sd->media_str[0] = media[0];
sd->media_str[1] = media[1];
memcpy(sd->model, &buffer[16], 16);
sd->model[17] = '\0';
return 1;
}
static unsigned int
read_capacity(lsi_private_t *lsi, sd_private_t *sd)
{
uint8_t *buffer;
// Setup command = Read Capacity
memset((uint8_t *)&lsi->buffer[LSI_TABLE_CMD_OFFSET], 0, 11);
lsi->buffer[LSI_TABLE_MSG_OUT_OFFSET] = 0x80;
lsi->table->msg_out_len = __cpu_to_le32(0x1);
lsi->buffer[LSI_TABLE_CMD_OFFSET] = READ_CAPACITY;
lsi->table->cmd_len = __cpu_to_le32(0x11);
lsi->table->data_in_len = __cpu_to_le32(0x8);
lsi->table->status_len = __cpu_to_le32(0x1);
lsi->table->msg_in_len = __cpu_to_le32(0x1);
lsi->table->id = __cpu_to_le32((sd->id << 16));
lsi->table->id_addr = __cpu_to_le32(&lsi->scripts_iova[0x2]);
/* Write DSP to start DMA engine */
uint32_t dsp = (uintptr_t)lsi->scripts_iova;
lsi->mmio[LSI_DSP] = dsp & 0xff;
lsi->mmio[LSI_DSP + 1] = (dsp >> 8) & 0xff;
lsi->mmio[LSI_DSP + 2] = (dsp >> 16) & 0xff;
lsi->mmio[LSI_DSP + 3] = (dsp >> 24) & 0xff;
if (lsi_interrupt_status(lsi)) {
sd->sectors = 0;
sd->bs = 0;
DPRINTF("read_capacity id %d failed\n", sd->id);
return 0;
}
buffer = (uint8_t *)&lsi->buffer[LSI_TABLE_DATA_OFFSET];
sd->bs = (buffer[4] << 24) | (buffer[5] << 16) | (buffer[6] << 8) | buffer[7];
sd->sectors = ((buffer[0] << 24) | (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]) * (sd->bs / 512);
DPRINTF("read_capacity id %d bs %d sectors %d\n", sd->id, sd->bs,
sd->sectors);
return 1;
}
static unsigned int
test_unit_ready(lsi_private_t *lsi, sd_private_t *sd)
{
/* Setup command = Test Unit Ready */
memset((uint8_t *)&lsi->buffer[LSI_TABLE_CMD_OFFSET], 0, 7);
lsi->buffer[LSI_TABLE_MSG_OUT_OFFSET] = 0x80;
lsi->table->msg_out_len = __cpu_to_le32(0x1);
lsi->buffer[LSI_TABLE_CMD_OFFSET] = TEST_UNIT_READY;
lsi->table->cmd_len = __cpu_to_le32(0x6);
lsi->table->status_len = __cpu_to_le32(0x1);
lsi->table->msg_in_len = __cpu_to_le32(0x1);
lsi->table->id = __cpu_to_le32((sd->id << 16));
lsi->table->id_addr = __cpu_to_le32(&lsi->scripts_iova[0x12]);
/* Write DSP to start DMA engine */
uint32_t dsp = (uintptr_t)&lsi->scripts_iova[0x10];
lsi->mmio[LSI_DSP] = dsp & 0xff;
lsi->mmio[LSI_DSP + 1] = (dsp >> 8) & 0xff;
lsi->mmio[LSI_DSP + 2] = (dsp >> 16) & 0xff;
lsi->mmio[LSI_DSP + 3] = (dsp >> 24) & 0xff;
if (lsi_interrupt_status(lsi)) {
DPRINTF("test_unit_ready id %d failed\n", sd->id);
return 0;
}
DPRINTF("test_unit_ready id %d success\n", sd->id);
return 1;
}
static void
ob_lsi_dma_alloc(__attribute__((unused)) lsi_private_t **lsi)
{
call_parent_method("dma-alloc");
}
static void
ob_lsi_dma_free(__attribute__((unused)) lsi_private_t **lsi)
{
call_parent_method("dma-free");
}
static void
ob_lsi_dma_map_in(__attribute__((unused)) lsi_private_t **lsi)
{
call_parent_method("dma-map-in");
}
static void
ob_lsi_dma_map_out(__attribute__((unused)) lsi_private_t **lsi)
{
call_parent_method("dma-map-out");
}
static void
ob_lsi_dma_sync(__attribute__((unused)) lsi_private_t **lsi)
{
call_parent_method("dma-sync");
}
// offset is in sectors
static int
ob_sd_read_sector(lsi_private_t *lsi, sd_private_t *sd, int offset)
{
uint32_t dsp;
DPRINTF("ob_sd_read_sector id %d sector=%d\n",
sd->id, offset);
// Setup command = Read(10)
memset((uint8_t *)&lsi->buffer[LSI_TABLE_CMD_OFFSET], 0, 10);
lsi->buffer[LSI_TABLE_MSG_OUT_OFFSET] = 0x80;
lsi->table->msg_out_len = __cpu_to_le32(0x1);
lsi->buffer[LSI_TABLE_CMD_OFFSET] = READ_10;
lsi->buffer[LSI_TABLE_CMD_OFFSET + 2] = (offset >> 24) & 0xff;
lsi->buffer[LSI_TABLE_CMD_OFFSET + 3] = (offset >> 16) & 0xff;;
lsi->buffer[LSI_TABLE_CMD_OFFSET + 4] = (offset >> 8) & 0xff;
lsi->buffer[LSI_TABLE_CMD_OFFSET + 5] = offset & 0xff;
lsi->buffer[LSI_TABLE_CMD_OFFSET + 7] = 0;
lsi->buffer[LSI_TABLE_CMD_OFFSET + 8] = 1;
lsi->table->cmd_len = __cpu_to_le32(0xa);
lsi->table->data_in_len = __cpu_to_le32(sd->bs);
lsi->table->status_len = __cpu_to_le32(0x1);
lsi->table->msg_in_len = __cpu_to_le32(0x2);
lsi->table->id = __cpu_to_le32((sd->id << 16));
lsi->table->id_addr = __cpu_to_le32(&lsi->scripts_iova[0x22]);
/* Write DSP to start DMA engine */
dsp = (uintptr_t)&lsi->scripts_iova[0x20];
lsi->mmio[LSI_DSP] = dsp & 0xff;
lsi->mmio[LSI_DSP + 1] = (dsp >> 8) & 0xff;
lsi->mmio[LSI_DSP + 2] = (dsp >> 16) & 0xff;
lsi->mmio[LSI_DSP + 3] = (dsp >> 24) & 0xff;
if (lsi_interrupt_status(lsi)) {
return 1;
}
// Reslect and data transfer
lsi->table->msg_in_len = __cpu_to_le32(0x1);
lsi->table->data_in_len = __cpu_to_le32(sd->bs);
/* Write DSP to start DMA engine */
dsp = (uintptr_t)&lsi->scripts_iova[0x2a];
lsi->mmio[LSI_DSP] = dsp & 0xff;
lsi->mmio[LSI_DSP + 1] = (dsp >> 8) & 0xff;
lsi->mmio[LSI_DSP + 2] = (dsp >> 16) & 0xff;
lsi->mmio[LSI_DSP + 3] = (dsp >> 24) & 0xff;
if (lsi_interrupt_status(lsi)) {
return 1;
}
return 0;
}
static void
ob_sd_read_blocks(sd_private_t **sd)
{
cell n = POP(), cnt = n;
ucell blk = POP();
char *dest = (char*)POP();
int pos, spb, sect_offset;
DPRINTF("ob_sd_read_blocks id %d %lx block=%d n=%d\n", (*sd)->id, (unsigned long)dest, blk, n );
if ((*sd)->bs == 0) {
PUSH(0);
return;
}
spb = (*sd)->bs / 512;
while (n) {
sect_offset = blk / spb;
pos = (blk - sect_offset * spb) * 512;
if (ob_sd_read_sector(global_lsi, *sd, sect_offset)) {
DPRINTF("ob_sd_read_blocks: error\n");
RET(0);
}
while (n && pos < spb * 512) {
memcpy(dest, (uint8_t *)&global_lsi->buffer[LSI_TABLE_DATA_OFFSET] + pos, 512);
pos += 512;
dest += 512;
n--;
blk++;
}
}
PUSH(cnt);
}
static void
ob_sd_block_size(__attribute__((unused))sd_private_t **sd)
{
PUSH(512);
}
static void
ob_sd_open(__attribute__((unused))sd_private_t **sd)
{
int ret = 1, id;
phandle_t ph;
fword("my-unit");
id = POP();
*sd = &global_lsi->sd[id];
#ifdef CONFIG_DEBUG_LSI
{
char *args;
fword("my-args");
args = pop_fstr_copy();
DPRINTF("opening drive %d args %s\n", id, args);
free(args);
}
#endif
selfword("open-deblocker");
/* interpose disk-label */
ph = find_dev("/packages/disk-label");
fword("my-args");
PUSH_ph( ph );
fword("interpose");
RET ( -ret );
}
static void
ob_sd_close(__attribute__((unused)) sd_private_t **sd)
{
selfword("close-deblocker");
}
NODE_METHODS(ob_sd) = {
{ "open", ob_sd_open },
{ "close", ob_sd_close },
{ "read-blocks", ob_sd_read_blocks },
{ "block-size", ob_sd_block_size },
};
static void
ob_lsi_decodeunit(__attribute__((unused)) lsi_private_t **lsi_p)
{
/* ( str len -- id ) */
fword("parse-hex");
}
static void
ob_lsi_encodeunit(__attribute__((unused)) lsi_private_t **lsi_p)
{
/* ( id -- str len ) */
fword("pocket");
fword("tohexstr");
}
static void
ob_lsi_open(__attribute__((unused)) lsi_private_t **lsi_p)
{
PUSH(-1);
}
static void
ob_lsi_close(__attribute__((unused)) lsi_private_t **lsi_p)
{
return;
}
NODE_METHODS(ob_lsi) = {
{ "open" , ob_lsi_open },
{ "close" , ob_lsi_close },
{ "decode-unit", ob_lsi_decodeunit },
{ "encode-unit", ob_lsi_encodeunit },
{ "dma-alloc", ob_lsi_dma_alloc },
{ "dma-free", ob_lsi_dma_free },
{ "dma-map-in", ob_lsi_dma_map_in },
{ "dma-map-out", ob_lsi_dma_map_out },
{ "dma-sync", ob_lsi_dma_sync },
};
static void
add_alias(const char *device, const char *alias)
{
DPRINTF("add_alias dev \"%s\" = alias \"%s\"\n", device, alias);
push_str("/aliases");
fword("find-device");
push_str(device);
fword("encode-string");
push_str(alias);
fword("property");
}
int
ob_lsi_init(const char *path, uint64_t mmio, uint64_t ram)
{
int id, diskcount = 0, cdcount = 0, *counter_ptr;
char nodebuff[256], aliasbuff[256];
phandle_t ph = get_cur_dev();
lsi_private_t *lsi;
int i;
ucell addr;
REGISTER_NODE_METHODS(ob_lsi, path);
lsi = malloc(sizeof(lsi_private_t));
if (!lsi) {
DPRINTF("Can't allocate LSI private structure\n");
return -1;
}
global_lsi = lsi;
/* Buffer for commands */
fword("my-self");
push_str(path);
feval("open-dev to my-self");
PUSH(0x1000);
feval("dma-alloc");
addr = POP();
lsi->buffer = cell2pointer(addr);
PUSH(addr);
PUSH(0x1000);
PUSH(0);
feval("dma-map-in");
addr = POP();
lsi->buffer_iova = cell2pointer(addr);
PUSH(0x40 * sizeof(uint32_t));
feval("dma-alloc");
addr = POP();
lsi->scripts = cell2pointer(addr);
PUSH(addr);
PUSH(0x40 * sizeof(uint32_t));
PUSH(0);
feval("dma-map-in");
addr = POP();
lsi->scripts_iova = cell2pointer(addr);
PUSH(sizeof(lsi_table_t));
feval("dma-alloc");
addr = POP();
lsi->table = cell2pointer(addr);
PUSH(addr);
PUSH(sizeof(lsi_table_t));
PUSH(0);
feval("dma-map-in");
addr = POP();
lsi->table_iova = cell2pointer(addr);
set_int_property(ph, "#address-cells", 1);
set_int_property(ph, "#size-cells", 0);
feval("to my-self");
/* Initialise SCRIPTS */
lsi->mmio = (uint8_t *)(uint32_t)mmio;
init_scripts(lsi);
init_table(lsi);
/* Scan the SCSI bus */
for (id = 0; id < 8; id++) {
lsi->sd[id].id = id;
if (!inquiry(lsi, &lsi->sd[id])) {
DPRINTF("Unit %d not present\n", id);
continue;
}
/* Clear Unit Attention condition from reset */
for (i = 0; i < 5; i++) {
if (test_unit_ready(lsi, &lsi->sd[id])) {
break;
}
}
if (i == 5) {
DPRINTF("Unit %d present but won't become ready\n", id);
continue;
}
DPRINTF("Unit %d present\n", id);
read_capacity(lsi, &lsi->sd[id]);
#ifdef CONFIG_DEBUG_LSI
dump_drive(&lsi->sd[id]);
#endif
}
for (id = 0; id < 8; id++) {
if (!lsi->sd[id].present)
continue;
fword("new-device");
push_str("sd");
fword("device-name");
push_str("block");
fword("device-type");
fword("is-deblocker");
PUSH(id);
fword("encode-int");
PUSH(0);
fword("encode-int");
fword("encode+");
push_str("reg");
fword("property");
fword("finish-device");
snprintf(nodebuff, sizeof(nodebuff), "%s/sd@%d",
get_path_from_ph(ph), id);
REGISTER_NODE_METHODS(ob_sd, nodebuff);
if (lsi->sd[id].media == TYPE_ROM) {
counter_ptr = &cdcount;
} else {
counter_ptr = &diskcount;
}
if (*counter_ptr == 0) {
add_alias(nodebuff, lsi->sd[id].media_str[0]);
add_alias(nodebuff, lsi->sd[id].media_str[1]);
}
snprintf(aliasbuff, sizeof(aliasbuff), "%s%d",
lsi->sd[id].media_str[0], *counter_ptr);
add_alias(nodebuff, aliasbuff);
snprintf(aliasbuff, sizeof(aliasbuff), "%s%d",
lsi->sd[id].media_str[1], *counter_ptr);
add_alias(nodebuff, aliasbuff);
}
return 0;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/bios-tables-test.c | <filename>src/qemu/src-pmp/tests/bios-tables-test.c
/*
* Boot order test cases.
*
* Copyright (c) 2013 Red Hat Inc.
*
* Authors:
* <NAME> <<EMAIL>>,
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include <glib/gstdio.h>
#include "qemu-common.h"
#include "hw/firmware/smbios.h"
#include "qemu/bitmap.h"
#include "acpi-utils.h"
#include "boot-sector.h"
#define MACHINE_PC "pc"
#define MACHINE_Q35 "q35"
#define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML"
typedef struct {
const char *machine;
const char *variant;
uint32_t rsdp_addr;
uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */];
GArray *tables;
uint32_t smbios_ep_addr;
struct smbios_21_entry_point smbios_ep_table;
uint8_t *required_struct_types;
int required_struct_types_len;
QTestState *qts;
} test_data;
static char disk[] = "tests/acpi-test-disk-XXXXXX";
static const char *data_dir = "tests/data/acpi";
#ifdef CONFIG_IASL
static const char *iasl = stringify(CONFIG_IASL);
#else
static const char *iasl;
#endif
static bool compare_signature(const AcpiSdtTable *sdt, const char *signature)
{
return !memcmp(sdt->aml, signature, 4);
}
static void cleanup_table_descriptor(AcpiSdtTable *table)
{
g_free(table->aml);
if (table->aml_file &&
!table->tmp_files_retain &&
g_strstr_len(table->aml_file, -1, "aml-")) {
unlink(table->aml_file);
}
g_free(table->aml_file);
g_free(table->asl);
if (table->asl_file &&
!table->tmp_files_retain) {
unlink(table->asl_file);
}
g_free(table->asl_file);
}
static void free_test_data(test_data *data)
{
int i;
for (i = 0; i < data->tables->len; ++i) {
cleanup_table_descriptor(&g_array_index(data->tables, AcpiSdtTable, i));
}
g_array_free(data->tables, true);
}
static void test_acpi_rsdp_address(test_data *data)
{
uint32_t off = acpi_find_rsdp_address(data->qts);
g_assert_cmphex(off, <, 0x100000);
data->rsdp_addr = off;
}
static void test_acpi_rsdp_table(test_data *data)
{
uint8_t *rsdp_table = data->rsdp_table, revision;
uint32_t addr = data->rsdp_addr;
acpi_parse_rsdp_table(data->qts, addr, rsdp_table);
revision = rsdp_table[15 /* Revision offset */];
switch (revision) {
case 0: /* ACPI 1.0 RSDP */
/* With rev 1, checksum is only for the first 20 bytes */
g_assert(!acpi_calc_checksum(rsdp_table, 20));
break;
case 2: /* ACPI 2.0+ RSDP */
/* With revision 2, we have 2 checksums */
g_assert(!acpi_calc_checksum(rsdp_table, 20));
g_assert(!acpi_calc_checksum(rsdp_table, 36));
break;
default:
g_assert_not_reached();
}
}
static void test_acpi_rsdt_table(test_data *data)
{
AcpiSdtTable rsdt = {};
uint8_t *ent;
/* read RSDT table */
acpi_fetch_table(data->qts, &rsdt.aml, &rsdt.aml_len,
&data->rsdp_table[16 /* RsdtAddress */], "RSDT", true);
/* Load all tables and add to test list directly RSDT referenced tables */
ACPI_FOREACH_RSDT_ENTRY(rsdt.aml, rsdt.aml_len, ent, 4 /* Entry size */) {
AcpiSdtTable ssdt_table = {};
acpi_fetch_table(data->qts, &ssdt_table.aml, &ssdt_table.aml_len, ent,
NULL, true);
/* Add table to ASL test tables list */
g_array_append_val(data->tables, ssdt_table);
}
cleanup_table_descriptor(&rsdt);
}
static void test_acpi_fadt_table(test_data *data)
{
/* FADT table is 1st */
AcpiSdtTable table = g_array_index(data->tables, typeof(table), 0);
uint8_t *fadt_aml = table.aml;
uint32_t fadt_len = table.aml_len;
g_assert(compare_signature(&table, "FACP"));
/* Since DSDT/FACS isn't in RSDT, add them to ASL test list manually */
acpi_fetch_table(data->qts, &table.aml, &table.aml_len,
fadt_aml + 36 /* FIRMWARE_CTRL */, "FACS", false);
g_array_append_val(data->tables, table);
acpi_fetch_table(data->qts, &table.aml, &table.aml_len,
fadt_aml + 40 /* DSDT */, "DSDT", true);
g_array_append_val(data->tables, table);
memset(fadt_aml + 36, 0, 4); /* sanitize FIRMWARE_CTRL ptr */
memset(fadt_aml + 40, 0, 4); /* sanitize DSDT ptr */
if (fadt_aml[8 /* FADT Major Version */] >= 3) {
memset(fadt_aml + 132, 0, 8); /* sanitize X_FIRMWARE_CTRL ptr */
memset(fadt_aml + 140, 0, 8); /* sanitize X_DSDT ptr */
}
/* update checksum */
fadt_aml[9 /* Checksum */] = 0;
fadt_aml[9 /* Checksum */] -= acpi_calc_checksum(fadt_aml, fadt_len);
}
static void dump_aml_files(test_data *data, bool rebuild)
{
AcpiSdtTable *sdt;
GError *error = NULL;
gchar *aml_file = NULL;
gint fd;
ssize_t ret;
int i;
for (i = 0; i < data->tables->len; ++i) {
const char *ext = data->variant ? data->variant : "";
sdt = &g_array_index(data->tables, AcpiSdtTable, i);
g_assert(sdt->aml);
if (rebuild) {
aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
sdt->aml, ext);
fd = g_open(aml_file, O_WRONLY|O_TRUNC|O_CREAT,
S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH);
} else {
fd = g_file_open_tmp("aml-XXXXXX", &sdt->aml_file, &error);
g_assert_no_error(error);
}
g_assert(fd >= 0);
ret = qemu_write_full(fd, sdt->aml, sdt->aml_len);
g_assert(ret == sdt->aml_len);
close(fd);
g_free(aml_file);
}
}
static bool load_asl(GArray *sdts, AcpiSdtTable *sdt)
{
AcpiSdtTable *temp;
GError *error = NULL;
GString *command_line = g_string_new(iasl);
gint fd;
gchar *out, *out_err;
gboolean ret;
int i;
fd = g_file_open_tmp("asl-XXXXXX.dsl", &sdt->asl_file, &error);
g_assert_no_error(error);
close(fd);
/* build command line */
g_string_append_printf(command_line, " -p %s ", sdt->asl_file);
if (compare_signature(sdt, "DSDT") ||
compare_signature(sdt, "SSDT")) {
for (i = 0; i < sdts->len; ++i) {
temp = &g_array_index(sdts, AcpiSdtTable, i);
if (compare_signature(temp, "DSDT") ||
compare_signature(temp, "SSDT")) {
g_string_append_printf(command_line, "-e %s ", temp->aml_file);
}
}
}
g_string_append_printf(command_line, "-d %s", sdt->aml_file);
/* pass 'out' and 'out_err' in order to be redirected */
ret = g_spawn_command_line_sync(command_line->str, &out, &out_err, NULL, &error);
g_assert_no_error(error);
if (ret) {
ret = g_file_get_contents(sdt->asl_file, &sdt->asl,
&sdt->asl_len, &error);
g_assert(ret);
g_assert_no_error(error);
ret = (sdt->asl_len > 0);
}
g_free(out);
g_free(out_err);
g_string_free(command_line, true);
return !ret;
}
#define COMMENT_END "*/"
#define DEF_BLOCK "DefinitionBlock ("
#define BLOCK_NAME_END ","
static GString *normalize_asl(gchar *asl_code)
{
GString *asl = g_string_new(asl_code);
gchar *comment, *block_name;
/* strip comments (different generation days) */
comment = g_strstr_len(asl->str, asl->len, COMMENT_END);
if (comment) {
comment += strlen(COMMENT_END);
while (*comment == '\n') {
comment++;
}
asl = g_string_erase(asl, 0, comment - asl->str);
}
/* strip def block name (it has file path in it) */
if (g_str_has_prefix(asl->str, DEF_BLOCK)) {
block_name = g_strstr_len(asl->str, asl->len, BLOCK_NAME_END);
g_assert(block_name);
asl = g_string_erase(asl, 0,
block_name + sizeof(BLOCK_NAME_END) - asl->str);
}
return asl;
}
static GArray *load_expected_aml(test_data *data)
{
int i;
AcpiSdtTable *sdt;
GError *error = NULL;
gboolean ret;
gsize aml_len;
GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable));
if (getenv("V")) {
fputc('\n', stderr);
}
for (i = 0; i < data->tables->len; ++i) {
AcpiSdtTable exp_sdt;
gchar *aml_file = NULL;
const char *ext = data->variant ? data->variant : "";
sdt = &g_array_index(data->tables, AcpiSdtTable, i);
memset(&exp_sdt, 0, sizeof(exp_sdt));
try_again:
aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
sdt->aml, ext);
if (getenv("V")) {
fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
}
if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
exp_sdt.aml_file = aml_file;
} else if (*ext != '\0') {
/* try fallback to generic (extension less) expected file */
ext = "";
g_free(aml_file);
goto try_again;
}
g_assert(exp_sdt.aml_file);
if (getenv("V")) {
fprintf(stderr, "Using expected file '%s'\n", aml_file);
}
ret = g_file_get_contents(aml_file, (gchar **)&exp_sdt.aml,
&aml_len, &error);
exp_sdt.aml_len = aml_len;
g_assert(ret);
g_assert_no_error(error);
g_assert(exp_sdt.aml);
g_assert(exp_sdt.aml_len);
g_array_append_val(exp_tables, exp_sdt);
}
return exp_tables;
}
/* test the list of tables in @data->tables against reference tables */
static void test_acpi_asl(test_data *data)
{
int i;
AcpiSdtTable *sdt, *exp_sdt;
test_data exp_data;
gboolean exp_err, err;
memset(&exp_data, 0, sizeof(exp_data));
exp_data.tables = load_expected_aml(data);
dump_aml_files(data, false);
for (i = 0; i < data->tables->len; ++i) {
GString *asl, *exp_asl;
sdt = &g_array_index(data->tables, AcpiSdtTable, i);
exp_sdt = &g_array_index(exp_data.tables, AcpiSdtTable, i);
err = load_asl(data->tables, sdt);
asl = normalize_asl(sdt->asl);
exp_err = load_asl(exp_data.tables, exp_sdt);
exp_asl = normalize_asl(exp_sdt->asl);
/* TODO: check for warnings */
g_assert(!err || exp_err);
if (g_strcmp0(asl->str, exp_asl->str)) {
if (exp_err) {
fprintf(stderr,
"Warning! iasl couldn't parse the expected aml\n");
} else {
sdt->tmp_files_retain = true;
exp_sdt->tmp_files_retain = true;
fprintf(stderr,
"acpi-test: Warning! %.4s mismatch. "
"Actual [asl:%s, aml:%s], Expected [asl:%s, aml:%s].\n",
exp_sdt->aml, sdt->asl_file, sdt->aml_file,
exp_sdt->asl_file, exp_sdt->aml_file);
if (getenv("V")) {
const char *diff_cmd = getenv("DIFF");
if (diff_cmd) {
int ret G_GNUC_UNUSED;
char *diff = g_strdup_printf("%s %s %s", diff_cmd,
exp_sdt->asl_file, sdt->asl_file);
ret = system(diff) ;
g_free(diff);
} else {
fprintf(stderr, "acpi-test: Warning. not showing "
"difference since no diff utility is specified. "
"Set 'DIFF' environment variable to a preferred "
"diff utility and run 'make V=1 check' again to "
"see ASL difference.");
}
}
}
}
g_string_free(asl, true);
g_string_free(exp_asl, true);
}
free_test_data(&exp_data);
}
static bool smbios_ep_table_ok(test_data *data)
{
struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
uint32_t addr = data->smbios_ep_addr;
qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table));
if (memcmp(ep_table->anchor_string, "_SM_", 4)) {
return false;
}
if (memcmp(ep_table->intermediate_anchor_string, "_DMI_", 5)) {
return false;
}
if (ep_table->structure_table_length == 0) {
return false;
}
if (ep_table->number_of_structures == 0) {
return false;
}
if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table) ||
acpi_calc_checksum((uint8_t *)ep_table + 0x10,
sizeof *ep_table - 0x10)) {
return false;
}
return true;
}
static void test_smbios_entry_point(test_data *data)
{
uint32_t off;
/* find smbios entry point structure */
for (off = 0xf0000; off < 0x100000; off += 0x10) {
uint8_t sig[] = "_SM_";
int i;
for (i = 0; i < sizeof sig - 1; ++i) {
sig[i] = qtest_readb(data->qts, off + i);
}
if (!memcmp(sig, "_SM_", sizeof sig)) {
/* signature match, but is this a valid entry point? */
data->smbios_ep_addr = off;
if (smbios_ep_table_ok(data)) {
break;
}
}
}
g_assert_cmphex(off, <, 0x100000);
}
static inline bool smbios_single_instance(uint8_t type)
{
switch (type) {
case 0:
case 1:
case 2:
case 3:
case 16:
case 32:
case 127:
return true;
default:
return false;
}
}
static void test_smbios_structs(test_data *data)
{
DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
uint32_t addr = le32_to_cpu(ep_table->structure_table_address);
int i, len, max_len = 0;
uint8_t type, prv, crt;
/* walk the smbios tables */
for (i = 0; i < le16_to_cpu(ep_table->number_of_structures); i++) {
/* grab type and formatted area length from struct header */
type = qtest_readb(data->qts, addr);
g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE);
len = qtest_readb(data->qts, addr + 1);
/* single-instance structs must not have been encountered before */
if (smbios_single_instance(type)) {
g_assert(!test_bit(type, struct_bitmap));
}
set_bit(type, struct_bitmap);
/* seek to end of unformatted string area of this struct ("\0\0") */
prv = crt = 1;
while (prv || crt) {
prv = crt;
crt = qtest_readb(data->qts, addr + len);
len++;
}
/* keep track of max. struct size */
if (max_len < len) {
max_len = len;
g_assert_cmpuint(max_len, <=, ep_table->max_structure_size);
}
/* start of next structure */
addr += len;
}
/* total table length and max struct size must match entry point values */
g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), ==,
addr - le32_to_cpu(ep_table->structure_table_address));
g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), ==, max_len);
/* required struct types must all be present */
for (i = 0; i < data->required_struct_types_len; i++) {
g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
}
}
static void test_acpi_one(const char *params, test_data *data)
{
char *args;
/* Disable kernel irqchip to be able to override apic irq0. */
args = g_strdup_printf("-machine %s,accel=%s,kernel-irqchip=off "
"-net none -display none %s "
"-drive id=hd0,if=none,file=%s,format=raw "
"-device ide-hd,drive=hd0 ",
data->machine, "kvm:tcg",
params ? params : "", disk);
data->qts = qtest_init(args);
boot_sector_test(data->qts);
data->tables = g_array_new(false, true, sizeof(AcpiSdtTable));
test_acpi_rsdp_address(data);
test_acpi_rsdp_table(data);
test_acpi_rsdt_table(data);
test_acpi_fadt_table(data);
if (iasl) {
if (getenv(ACPI_REBUILD_EXPECTED_AML)) {
dump_aml_files(data, true);
} else {
test_acpi_asl(data);
}
}
test_smbios_entry_point(data);
test_smbios_structs(data);
assert(!global_qtest);
qtest_quit(data->qts);
g_free(args);
}
static uint8_t base_required_struct_types[] = {
0, 1, 3, 4, 16, 17, 19, 32, 127
};
static void test_acpi_piix4_tcg(void)
{
test_data data;
/* Supplying -machine accel argument overrides the default (qtest).
* This is to make guest actually run.
*/
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.required_struct_types = base_required_struct_types;
data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one(NULL, &data);
free_test_data(&data);
}
static void test_acpi_piix4_tcg_bridge(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".bridge";
data.required_struct_types = base_required_struct_types;
data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one("-device pci-bridge,chassis_nr=1", &data);
free_test_data(&data);
}
static void test_acpi_q35_tcg(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.required_struct_types = base_required_struct_types;
data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one(NULL, &data);
free_test_data(&data);
}
static void test_acpi_q35_tcg_bridge(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".bridge";
data.required_struct_types = base_required_struct_types;
data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one("-device pci-bridge,chassis_nr=1",
&data);
free_test_data(&data);
}
static void test_acpi_q35_tcg_mmio64(void)
{
test_data data = {
.machine = MACHINE_Q35,
.variant = ".mmio64",
.required_struct_types = base_required_struct_types,
.required_struct_types_len = ARRAY_SIZE(base_required_struct_types)
};
test_acpi_one("-m 128M,slots=1,maxmem=2G "
"-device pci-testdev,membar=2G",
&data);
free_test_data(&data);
}
static void test_acpi_piix4_tcg_cphp(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".cphp";
test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6"
" -numa node -numa node"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
}
static void test_acpi_q35_tcg_cphp(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".cphp";
test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6"
" -numa node -numa node"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
}
static uint8_t ipmi_required_struct_types[] = {
0, 1, 3, 4, 16, 17, 19, 32, 38, 127
};
static void test_acpi_q35_tcg_ipmi(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".ipmibt";
data.required_struct_types = ipmi_required_struct_types;
data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
" -device isa-ipmi-bt,bmc=bmc0",
&data);
free_test_data(&data);
}
static void test_acpi_piix4_tcg_ipmi(void)
{
test_data data;
/* Supplying -machine accel argument overrides the default (qtest).
* This is to make guest actually run.
*/
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".ipmikcs";
data.required_struct_types = ipmi_required_struct_types;
data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
" -device isa-ipmi-kcs,irq=0,bmc=bmc0",
&data);
free_test_data(&data);
}
static void test_acpi_q35_tcg_memhp(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".memhp";
test_acpi_one(" -m 128,slots=3,maxmem=1G"
" -numa node -numa node"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
}
static void test_acpi_piix4_tcg_memhp(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".memhp";
test_acpi_one(" -m 128,slots=3,maxmem=1G"
" -numa node -numa node"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
}
static void test_acpi_q35_tcg_numamem(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".numamem";
test_acpi_one(" -numa node -numa node,mem=128", &data);
free_test_data(&data);
}
static void test_acpi_piix4_tcg_numamem(void)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".numamem";
test_acpi_one(" -numa node -numa node,mem=128", &data);
free_test_data(&data);
}
static void test_acpi_tcg_dimm_pxm(const char *machine)
{
test_data data;
memset(&data, 0, sizeof(data));
data.machine = machine;
data.variant = ".dimmpxm";
test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu"
" -smp 4,sockets=4"
" -m 128M,slots=3,maxmem=1G"
" -numa node,mem=32M,nodeid=0"
" -numa node,mem=32M,nodeid=1"
" -numa node,mem=32M,nodeid=2"
" -numa node,mem=32M,nodeid=3"
" -numa cpu,node-id=0,socket-id=0"
" -numa cpu,node-id=1,socket-id=1"
" -numa cpu,node-id=2,socket-id=2"
" -numa cpu,node-id=3,socket-id=3"
" -object memory-backend-ram,id=ram0,size=128M"
" -object memory-backend-ram,id=nvm0,size=128M"
" -device pc-dimm,id=dimm0,memdev=ram0,node=1"
" -device nvdimm,id=dimm1,memdev=nvm0,node=2",
&data);
free_test_data(&data);
}
static void test_acpi_q35_tcg_dimm_pxm(void)
{
test_acpi_tcg_dimm_pxm(MACHINE_Q35);
}
static void test_acpi_piix4_tcg_dimm_pxm(void)
{
test_acpi_tcg_dimm_pxm(MACHINE_PC);
}
int main(int argc, char *argv[])
{
const char *arch = qtest_get_arch();
int ret;
ret = boot_sector_init(disk);
if(ret)
return ret;
g_test_init(&argc, &argv, NULL);
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
qtest_add_func("acpi/piix4", test_acpi_piix4_tcg);
qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge);
qtest_add_func("acpi/q35", test_acpi_q35_tcg);
qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);
qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi);
qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi);
qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp);
qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp);
qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp);
qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp);
qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem);
qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem);
qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm);
qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
}
ret = g_test_run();
boot_sector_cleanup(disk);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/int-add/test_msa_hadd_s_h.c | <reponame>pmp-tool/PMP
/*
* Test program for MSA instruction HADD_S.H
*
* Copyright (C) 2019 RT-RK Computer Based Systems LLC
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "HADD_S.H";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0xfffefffefffefffeULL, 0xfffefffefffefffeULL, }, /* 0 */
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0xffa9ffa9ffa9ffa9ULL, 0xffa9ffa9ffa9ffa9ULL, },
{ 0x0054005400540054ULL, 0x0054005400540054ULL, },
{ 0xffcbffcbffcbffcbULL, 0xffcbffcbffcbffcbULL, },
{ 0x0032003200320032ULL, 0x0032003200320032ULL, },
{ 0xff8dffe20037ff8dULL, 0xffe20037ff8dffe2ULL, },
{ 0x0070001bffc60070ULL, 0x001bffc60070001bULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0xffaaffaaffaaffaaULL, 0xffaaffaaffaaffaaULL, },
{ 0x0055005500550055ULL, 0x0055005500550055ULL, },
{ 0xffccffccffccffccULL, 0xffccffccffccffccULL, },
{ 0x0033003300330033ULL, 0x0033003300330033ULL, },
{ 0xff8effe30038ff8eULL, 0xffe30038ff8effe3ULL, },
{ 0x0071001cffc70071ULL, 0x001cffc70071001cULL, },
{ 0xffa9ffa9ffa9ffa9ULL, 0xffa9ffa9ffa9ffa9ULL, }, /* 16 */
{ 0xffaaffaaffaaffaaULL, 0xffaaffaaffaaffaaULL, },
{ 0xff54ff54ff54ff54ULL, 0xff54ff54ff54ff54ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0xff76ff76ff76ff76ULL, 0xff76ff76ff76ff76ULL, },
{ 0xffddffddffddffddULL, 0xffddffddffddffddULL, },
{ 0xff38ff8dffe2ff38ULL, 0xff8dffe2ff38ff8dULL, },
{ 0x001bffc6ff71001bULL, 0xffc6ff71001bffc6ULL, },
{ 0x0054005400540054ULL, 0x0054005400540054ULL, }, /* 24 */
{ 0x0055005500550055ULL, 0x0055005500550055ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x00aa00aa00aa00aaULL, 0x00aa00aa00aa00aaULL, },
{ 0x0021002100210021ULL, 0x0021002100210021ULL, },
{ 0x0088008800880088ULL, 0x0088008800880088ULL, },
{ 0xffe30038008dffe3ULL, 0x0038008dffe30038ULL, },
{ 0x00c60071001c00c6ULL, 0x0071001c00c60071ULL, },
{ 0xffcbffcbffcbffcbULL, 0xffcbffcbffcbffcbULL, }, /* 32 */
{ 0xffccffccffccffccULL, 0xffccffccffccffccULL, },
{ 0xff76ff76ff76ff76ULL, 0xff76ff76ff76ff76ULL, },
{ 0x0021002100210021ULL, 0x0021002100210021ULL, },
{ 0xff98ff98ff98ff98ULL, 0xff98ff98ff98ff98ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0xff5affaf0004ff5aULL, 0xffaf0004ff5affafULL, },
{ 0x003dffe8ff93003dULL, 0xffe8ff93003dffe8ULL, },
{ 0x0032003200320032ULL, 0x0032003200320032ULL, }, /* 40 */
{ 0x0033003300330033ULL, 0x0033003300330033ULL, },
{ 0xffddffddffddffddULL, 0xffddffddffddffddULL, },
{ 0x0088008800880088ULL, 0x0088008800880088ULL, },
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, },
{ 0x0066006600660066ULL, 0x0066006600660066ULL, },
{ 0xffc10016006bffc1ULL, 0x0016006bffc10016ULL, },
{ 0x00a4004ffffa00a4ULL, 0x004ffffa00a4004fULL, },
{ 0xffe20037ff8dffe2ULL, 0x0037ff8dffe20037ULL, }, /* 48 */
{ 0xffe30038ff8effe3ULL, 0x0038ff8effe30038ULL, },
{ 0xff8dffe2ff38ff8dULL, 0xffe2ff38ff8dffe2ULL, },
{ 0x0038008dffe30038ULL, 0x008dffe30038008dULL, },
{ 0xffaf0004ff5affafULL, 0x0004ff5affaf0004ULL, },
{ 0x0016006bffc10016ULL, 0x006bffc10016006bULL, },
{ 0xff71001bffc6ff71ULL, 0x001bffc6ff71001bULL, },
{ 0x00540054ff550054ULL, 0x0054ff5500540054ULL, },
{ 0x001bffc60070001bULL, 0xffc60070001bffc6ULL, }, /* 56 */
{ 0x001cffc70071001cULL, 0xffc70071001cffc7ULL, },
{ 0xffc6ff71001bffc6ULL, 0xff71001bffc6ff71ULL, },
{ 0x0071001c00c60071ULL, 0x001c00c60071001cULL, },
{ 0xffe8ff93003dffe8ULL, 0xff93003dffe8ff93ULL, },
{ 0x004ffffa00a4004fULL, 0xfffa00a4004ffffaULL, },
{ 0xffaaffaa00a9ffaaULL, 0xffaa00a9ffaaffaaULL, },
{ 0x008dffe30038008dULL, 0xffe30038008dffe3ULL, },
{ 0xfff2ffb2008a0095ULL, 0x00b200690079ffbcULL, }, /* 64 */
{ 0xff460049ffbb005dULL, 0x00420025003dffacULL, },
{ 0xffe2ff90fff7ffd5ULL, 0x0023000a0029ffc4ULL, },
{ 0xffd70033005900a3ULL, 0x003cffe30040ff50ULL, },
{ 0x0065ffcc00af0007ULL, 0x007900190090005eULL, },
{ 0xffb90063ffe0ffcfULL, 0x0009ffd50054004eULL, },
{ 0x0055ffaa001cff47ULL, 0xffeaffba00400066ULL, },
{ 0x004a004d007e0015ULL, 0x0003ff930057fff2ULL, },
{ 0x0016ff7a001bffcbULL, 0x008e002400260031ULL, }, /* 72 */
{ 0xff6a0011ff4cff93ULL, 0x001effe0ffea0021ULL, },
{ 0x0006ff58ff88ff0bULL, 0xffffffc5ffd60039ULL, },
{ 0xfffbfffbffeaffd9ULL, 0x0018ff9effedffc5ULL, },
{ 0x00daffe200c00022ULL, 0xfff4ffe60024ffeeULL, },
{ 0x002e0079fff1ffeaULL, 0xff84ffa2ffe8ffdeULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_HADD_S_H(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_HADD_S_H(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/i2c/smbus_master.c | <reponame>pmp-tool/PMP
/*
* QEMU SMBus host (master) emulation.
*
* This code emulates SMBus transactions from the master point of view,
* it runs the individual I2C transaction to do the SMBus protocol
* over I2C.
*
* Copyright (c) 2007 CodeSourcery.
* Written by <NAME>
*
* This code is licensed under the LGPL.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/i2c/i2c.h"
#include "hw/i2c/smbus_master.h"
/* Master device commands. */
int smbus_quick_command(I2CBus *bus, uint8_t addr, int read)
{
if (i2c_start_transfer(bus, addr, read)) {
return -1;
}
i2c_end_transfer(bus);
return 0;
}
int smbus_receive_byte(I2CBus *bus, uint8_t addr)
{
uint8_t data;
if (i2c_start_transfer(bus, addr, 1)) {
return -1;
}
data = i2c_recv(bus);
i2c_nack(bus);
i2c_end_transfer(bus);
return data;
}
int smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data)
{
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, data);
i2c_end_transfer(bus);
return 0;
}
int smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command)
{
uint8_t data;
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, command);
if (i2c_start_transfer(bus, addr, 1)) {
i2c_end_transfer(bus);
return -1;
}
data = i2c_recv(bus);
i2c_nack(bus);
i2c_end_transfer(bus);
return data;
}
int smbus_write_byte(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t data)
{
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, command);
i2c_send(bus, data);
i2c_end_transfer(bus);
return 0;
}
int smbus_read_word(I2CBus *bus, uint8_t addr, uint8_t command)
{
uint16_t data;
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, command);
if (i2c_start_transfer(bus, addr, 1)) {
i2c_end_transfer(bus);
return -1;
}
data = i2c_recv(bus);
data |= i2c_recv(bus) << 8;
i2c_nack(bus);
i2c_end_transfer(bus);
return data;
}
int smbus_write_word(I2CBus *bus, uint8_t addr, uint8_t command, uint16_t data)
{
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, command);
i2c_send(bus, data & 0xff);
i2c_send(bus, data >> 8);
i2c_end_transfer(bus);
return 0;
}
int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
int len, bool recv_len, bool send_cmd)
{
int rlen;
int i;
if (send_cmd) {
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, command);
}
if (i2c_start_transfer(bus, addr, 1)) {
if (send_cmd) {
i2c_end_transfer(bus);
}
return -1;
}
if (recv_len) {
rlen = i2c_recv(bus);
} else {
rlen = len;
}
if (rlen > len) {
rlen = 0;
}
for (i = 0; i < rlen; i++) {
data[i] = i2c_recv(bus);
}
i2c_nack(bus);
i2c_end_transfer(bus);
return rlen;
}
int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
int len, bool send_len)
{
int i;
if (len > 32) {
len = 32;
}
if (i2c_start_transfer(bus, addr, 0)) {
return -1;
}
i2c_send(bus, command);
if (send_len) {
i2c_send(bus, len);
}
for (i = 0; i < len; i++) {
i2c_send(bus, data[i]);
}
i2c_end_transfer(bus);
return 0;
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_b.c | <filename>src/qemu/src-pmp/tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_b.c
/*
* Test program for MSA instruction ILVEV.B
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_msa.h"
#include "../../../../include/test_inputs_128.h"
#include "../../../../include/test_utils_128.h"
#define TEST_COUNT_TOTAL ( \
(PATTERN_INPUTS_SHORT_COUNT) * (PATTERN_INPUTS_SHORT_COUNT) + \
(RANDOM_INPUTS_SHORT_COUNT) * (RANDOM_INPUTS_SHORT_COUNT))
int32_t main(void)
{
char *instruction_name = "*ILVEV.B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b128_result[TEST_COUNT_TOTAL][2];
uint64_t b128_expect[TEST_COUNT_TOTAL][2] = {
{ 0xffffffffffffffffULL, 0xffffffffffffffffULL, }, /* 0 */
{ 0xff00ff00ff00ff00ULL, 0xff00ff00ff00ff00ULL, },
{ 0xffaaffaaffaaffaaULL, 0xffaaffaaffaaffaaULL, },
{ 0xff55ff55ff55ff55ULL, 0xff55ff55ff55ff55ULL, },
{ 0xffccffccffccffccULL, 0xffccffccffccffccULL, },
{ 0xff33ff33ff33ff33ULL, 0xff33ff33ff33ff33ULL, },
{ 0xff8effe3ff38ff8eULL, 0xffe3ff38ff8effe3ULL, },
{ 0xff71ff1cffc7ff71ULL, 0xff1cffc7ff71ff1cULL, },
{ 0x00ff00ff00ff00ffULL, 0x00ff00ff00ff00ffULL, }, /* 8 */
{ 0x0000000000000000ULL, 0x0000000000000000ULL, },
{ 0x00aa00aa00aa00aaULL, 0x00aa00aa00aa00aaULL, },
{ 0x0055005500550055ULL, 0x0055005500550055ULL, },
{ 0x00cc00cc00cc00ccULL, 0x00cc00cc00cc00ccULL, },
{ 0x0033003300330033ULL, 0x0033003300330033ULL, },
{ 0x008e00e30038008eULL, 0x00e30038008e00e3ULL, },
{ 0x0071001c00c70071ULL, 0x001c00c70071001cULL, },
{ 0xaaffaaffaaffaaffULL, 0xaaffaaffaaffaaffULL, }, /* 16 */
{ 0xaa00aa00aa00aa00ULL, 0xaa00aa00aa00aa00ULL, },
{ 0xaaaaaaaaaaaaaaaaULL, 0xaaaaaaaaaaaaaaaaULL, },
{ 0xaa55aa55aa55aa55ULL, 0xaa55aa55aa55aa55ULL, },
{ 0xaaccaaccaaccaaccULL, 0xaaccaaccaaccaaccULL, },
{ 0xaa33aa33aa33aa33ULL, 0xaa33aa33aa33aa33ULL, },
{ 0xaa8eaae3aa38aa8eULL, 0xaae3aa38aa8eaae3ULL, },
{ 0xaa71aa1caac7aa71ULL, 0xaa1caac7aa71aa1cULL, },
{ 0x55ff55ff55ff55ffULL, 0x55ff55ff55ff55ffULL, }, /* 24 */
{ 0x5500550055005500ULL, 0x5500550055005500ULL, },
{ 0x55aa55aa55aa55aaULL, 0x55aa55aa55aa55aaULL, },
{ 0x5555555555555555ULL, 0x5555555555555555ULL, },
{ 0x55cc55cc55cc55ccULL, 0x55cc55cc55cc55ccULL, },
{ 0x5533553355335533ULL, 0x5533553355335533ULL, },
{ 0x558e55e35538558eULL, 0x55e35538558e55e3ULL, },
{ 0x5571551c55c75571ULL, 0x551c55c75571551cULL, },
{ 0xccffccffccffccffULL, 0xccffccffccffccffULL, }, /* 32 */
{ 0xcc00cc00cc00cc00ULL, 0xcc00cc00cc00cc00ULL, },
{ 0xccaaccaaccaaccaaULL, 0xccaaccaaccaaccaaULL, },
{ 0xcc55cc55cc55cc55ULL, 0xcc55cc55cc55cc55ULL, },
{ 0xccccccccccccccccULL, 0xccccccccccccccccULL, },
{ 0xcc33cc33cc33cc33ULL, 0xcc33cc33cc33cc33ULL, },
{ 0xcc8ecce3cc38cc8eULL, 0xcce3cc38cc8ecce3ULL, },
{ 0xcc71cc1cccc7cc71ULL, 0xcc1cccc7cc71cc1cULL, },
{ 0x33ff33ff33ff33ffULL, 0x33ff33ff33ff33ffULL, }, /* 40 */
{ 0x3300330033003300ULL, 0x3300330033003300ULL, },
{ 0x33aa33aa33aa33aaULL, 0x33aa33aa33aa33aaULL, },
{ 0x3355335533553355ULL, 0x3355335533553355ULL, },
{ 0x33cc33cc33cc33ccULL, 0x33cc33cc33cc33ccULL, },
{ 0x3333333333333333ULL, 0x3333333333333333ULL, },
{ 0x338e33e33338338eULL, 0x33e33338338e33e3ULL, },
{ 0x3371331c33c73371ULL, 0x331c33c73371331cULL, },
{ 0x8effe3ff38ff8effULL, 0xe3ff38ff8effe3ffULL, }, /* 48 */
{ 0x8e00e30038008e00ULL, 0xe30038008e00e300ULL, },
{ 0x8eaae3aa38aa8eaaULL, 0xe3aa38aa8eaae3aaULL, },
{ 0x8e55e35538558e55ULL, 0xe35538558e55e355ULL, },
{ 0x8ecce3cc38cc8eccULL, 0xe3cc38cc8ecce3ccULL, },
{ 0x8e33e33338338e33ULL, 0xe33338338e33e333ULL, },
{ 0x8e8ee3e338388e8eULL, 0xe3e338388e8ee3e3ULL, },
{ 0x8e71e31c38c78e71ULL, 0xe31c38c78e71e31cULL, },
{ 0x71ff1cffc7ff71ffULL, 0x1cffc7ff71ff1cffULL, }, /* 56 */
{ 0x71001c00c7007100ULL, 0x1c00c70071001c00ULL, },
{ 0x71aa1caac7aa71aaULL, 0x1caac7aa71aa1caaULL, },
{ 0x71551c55c7557155ULL, 0x1c55c75571551c55ULL, },
{ 0x71cc1cccc7cc71ccULL, 0x1cccc7cc71cc1cccULL, },
{ 0x71331c33c7337133ULL, 0x1c33c73371331c33ULL, },
{ 0x718e1ce3c738718eULL, 0x1ce3c738718e1ce3ULL, },
{ 0x71711c1cc7c77171ULL, 0x1c1cc7c771711c1cULL, },
{ 0x6a6acccc62624040ULL, 0x67675e5e7b7b0c0cULL, }, /* 64 */
{ 0x6abecc6362934008ULL, 0x67f75e1a7b3f0cfcULL, },
{ 0x6a5accaa62cf4080ULL, 0x67d85eff7b2b0c14ULL, },
{ 0x6a4fcc4d6231404eULL, 0x67f15ed87b420ca0ULL, },
{ 0xbe6a63cc93620840ULL, 0xf7671a5e3f7bfc0cULL, },
{ 0xbebe636393930808ULL, 0xf7f71a1a3f3ffcfcULL, },
{ 0xbe5a63aa93cf0880ULL, 0xf7d81aff3f2bfc14ULL, },
{ 0xbe4f634d9331084eULL, 0xf7f11ad83f42fca0ULL, },
{ 0x5a6aaacccf628040ULL, 0xd867ff5e2b7b140cULL, }, /* 72 */
{ 0x5abeaa63cf938008ULL, 0xd8f7ff1a2b3f14fcULL, },
{ 0x5a5aaaaacfcf8080ULL, 0xd8d8ffff2b2b1414ULL, },
{ 0x5a4faa4dcf31804eULL, 0xd8f1ffd82b4214a0ULL, },
{ 0x4f6a4dcc31624e40ULL, 0xf167d85e427ba00cULL, },
{ 0x4fbe4d6331934e08ULL, 0xf1f7d81a423fa0fcULL, },
{ 0x4f5a4daa31cf4e80ULL, 0xf1d8d8ff422ba014ULL, },
{ 0x4f4f4d4d31314e4eULL, 0xf1f1d8d84242a0a0ULL, },
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_SHORT_COUNT; j++) {
do_msa_ILVEV_B(b128_pattern[i], b128_pattern[j],
b128_result[PATTERN_INPUTS_SHORT_COUNT * i + j]);
}
}
for (i = 0; i < RANDOM_INPUTS_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_SHORT_COUNT; j++) {
do_msa_ILVEV_B(b128_random[i], b128_random[j],
b128_result[((PATTERN_INPUTS_SHORT_COUNT) *
(PATTERN_INPUTS_SHORT_COUNT)) +
RANDOM_INPUTS_SHORT_COUNT * i + j]);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
&b128_result[0][0], &b128_expect[0][0]);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/i386/pc_piix.c | <reponame>pmp-tool/PMP<filename>src/qemu/src-pmp/hw/i386/pc_piix.c
/*
* QEMU PC System Emulator
*
* Copyright (c) 2003-2004 <NAME>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h"
#include "hw/loader.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_ids.h"
#include "hw/usb.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/ide.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "sysemu/arch_init.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/xen/xen.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "hw/acpi/acpi.h"
#include "cpu.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#ifdef CONFIG_XEN
#include <xen/hvm/hvm_info_table.h>
#include "hw/xen/xen_pt.h"
#endif
#include "migration/global_state.h"
#include "migration/misc.h"
#include "kvm_i386.h"
#include "sysemu/numa.h"
#define MAX_IDE_BUS 2
static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
/* PC hardware initialisation */
static void pc_init1(MachineState *machine,
const char *host_type, const char *pci_type)
{
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
int i;
PCIBus *pci_bus;
ISABus *isa_bus;
PCII440FXState *i440fx_state;
int piix3_devfn = -1;
qemu_irq *i8259;
qemu_irq smi_irq;
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
MemoryRegion *ram_memory;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
ram_addr_t lowmem;
/*
* Calculate ram split, for memory below and above 4G. It's a bit
* complicated for backward compatibility reasons ...
*
* - Traditional split is 3.5G (lowmem = 0xe0000000). This is the
* default value for max_ram_below_4g now.
*
* - Then, to gigabyte align the memory, we move the split to 3G
* (lowmem = 0xc0000000). But only in case we have to split in
* the first place, i.e. ram_size is larger than (traditional)
* lowmem. And for new machine types (gigabyte_align = true)
* only, for live migration compatibility reasons.
*
* - Next the max-ram-below-4g option was added, which allowed to
* reduce lowmem to a smaller value, to allow a larger PCI I/O
* window below 4G. qemu doesn't enforce gigabyte alignment here,
* but prints a warning.
*
* - Finally max-ram-below-4g got updated to also allow raising lowmem,
* so legacy non-PAE guests can get as much memory as possible in
* the 32bit address space below 4G.
*
* - Note that Xen has its own ram setp code in xen_ram_init(),
* called via xen_hvm_init().
*
* Examples:
* qemu -M pc-1.7 -m 4G (old default) -> 3584M low, 512M high
* qemu -M pc -m 4G (new default) -> 3072M low, 1024M high
* qemu -M pc,max-ram-below-4g=2G -m 4G -> 2048M low, 2048M high
* qemu -M pc,max-ram-below-4g=4G -m 3968M -> 3968M low (=4G-128M)
*/
if (xen_enabled()) {
xen_hvm_init(pcms, &ram_memory);
} else {
if (!pcms->max_ram_below_4g) {
pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */
}
lowmem = pcms->max_ram_below_4g;
if (machine->ram_size >= pcms->max_ram_below_4g) {
if (pcmc->gigabyte_align) {
if (lowmem > 0xc0000000) {
lowmem = 0xc0000000;
}
if (lowmem & (1 * GiB - 1)) {
warn_report("Large machine and max_ram_below_4g "
"(%" PRIu64 ") not a multiple of 1G; "
"possible bad performance.",
pcms->max_ram_below_4g);
}
}
}
if (machine->ram_size >= lowmem) {
pcms->above_4g_mem_size = machine->ram_size - lowmem;
pcms->below_4g_mem_size = lowmem;
} else {
pcms->above_4g_mem_size = 0;
pcms->below_4g_mem_size = machine->ram_size;
}
}
pc_cpus_init(pcms);
if (kvm_enabled() && pcmc->kvmclock_enabled) {
kvmclock_create();
}
if (pcmc->pci_enabled) {
pci_memory = g_new(MemoryRegion, 1);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
} else {
pci_memory = NULL;
rom_memory = system_memory;
}
pc_guest_info_init(pcms);
if (pcmc->smbios_defaults) {
MachineClass *mc = MACHINE_GET_CLASS(machine);
/* These values are guest ABI, do not change */
smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)",
mc->name, pcmc->smbios_legacy_mode,
pcmc->smbios_uuid_encoded,
SMBIOS_ENTRY_POINT_21);
}
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(pcms, system_memory,
rom_memory, &ram_memory);
} else if (machine->kernel_filename != NULL) {
/* For xen HVM direct kernel boot, load linux here */
xen_load_linux(pcms);
}
gsi_state = g_malloc0(sizeof(*gsi_state));
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pcmc->pci_enabled);
pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
GSI_NUM_PINS);
} else {
pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
if (pcmc->pci_enabled) {
pci_bus = i440fx_init(host_type,
pci_type,
&i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
system_memory, system_io, machine->ram_size,
pcms->below_4g_mem_size,
pcms->above_4g_mem_size,
pci_memory, ram_memory);
pcms->bus = pci_bus;
} else {
pci_bus = NULL;
i440fx_state = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
&error_abort);
no_hpet = 1;
}
isa_bus_irqs(isa_bus, pcms->gsi);
if (kvm_pic_in_kernel()) {
i8259 = kvm_i8259_init(isa_bus);
} else if (xen_enabled()) {
i8259 = xen_interrupt_controller_init();
} else {
i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
}
for (i = 0; i < ISA_NUM_IRQS; i++) {
gsi_state->i8259_irq[i] = i8259[i];
}
g_free(i8259);
if (pcmc->pci_enabled) {
ioapic_init_gsi(gsi_state, "i440fx");
}
pc_register_ferr_irq(pcms->gsi[13]);
pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL);
assert(pcms->vmport != ON_OFF_AUTO__MAX);
if (pcms->vmport == ON_OFF_AUTO_AUTO) {
pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
}
/* init basic PC hardware */
pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, true,
(pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
0x4);
pc_nic_init(pcmc, isa_bus, pci_bus);
ide_drive_get(hd, ARRAY_SIZE(hd));
if (pcmc->pci_enabled) {
PCIDevice *dev;
if (xen_enabled()) {
dev = pci_piix3_xen_ide_init(pci_bus, hd, piix3_devfn + 1);
} else {
dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
}
idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
} else {
for(i = 0; i < MAX_IDE_BUS; i++) {
ISADevice *dev;
char busname[] = "ide.0";
dev = isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i],
ide_irq[i],
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
/*
* The ide bus name is ide.0 for the first bus and ide.1 for the
* second one.
*/
busname[4] = '0' + i;
idebus[i] = qdev_get_child_bus(DEVICE(dev), busname);
}
}
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
if (pcmc->pci_enabled && machine_usb(machine)) {
pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
}
if (pcmc->pci_enabled && acpi_enabled) {
DeviceState *piix4_pm;
I2CBus *smbus;
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
/* TODO: Populate SPD eeprom data. */
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
pcms->gsi[9], smi_irq,
pc_machine_is_smm_enabled(pcms),
&piix4_pm);
smbus_eeprom_init(smbus, 8, NULL, 0);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
(Object **)&pcms->acpi_dev,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG, &error_abort);
object_property_set_link(OBJECT(machine), OBJECT(piix4_pm),
PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
}
if (machine->nvdimms_state->is_enabled) {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
pcms->fw_cfg, OBJECT(pcms));
}
}
/* Looking for a pc_compat_2_4() function? It doesn't exist.
* pc_compat_*() functions that run on machine-init time and
* change global QEMU state are deprecated. Please don't create
* one, and implement any pc-*-2.4 (and newer) compat code in
* HW_COMPAT_*, PC_COMPAT_*, or * pc_*_machine_options().
*/
static void pc_compat_2_3_fn(MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
if (kvm_enabled()) {
pcms->smm = ON_OFF_AUTO_OFF;
}
}
static void pc_compat_2_2_fn(MachineState *machine)
{
pc_compat_2_3_fn(machine);
}
static void pc_compat_2_1_fn(MachineState *machine)
{
pc_compat_2_2_fn(machine);
x86_cpu_change_kvm_default("svm", NULL);
}
static void pc_compat_2_0_fn(MachineState *machine)
{
pc_compat_2_1_fn(machine);
}
static void pc_compat_1_7_fn(MachineState *machine)
{
pc_compat_2_0_fn(machine);
x86_cpu_change_kvm_default("x2apic", NULL);
}
static void pc_compat_1_6_fn(MachineState *machine)
{
pc_compat_1_7_fn(machine);
}
static void pc_compat_1_5_fn(MachineState *machine)
{
pc_compat_1_6_fn(machine);
}
static void pc_compat_1_4_fn(MachineState *machine)
{
pc_compat_1_5_fn(machine);
}
static void pc_compat_1_3(MachineState *machine)
{
pc_compat_1_4_fn(machine);
enable_compat_apic_id_mode();
}
/* PC compat function for pc-0.14 to pc-1.2 */
static void pc_compat_1_2(MachineState *machine)
{
pc_compat_1_3(machine);
x86_cpu_change_kvm_default("kvm-pv-eoi", NULL);
}
/* PC compat function for pc-0.12 and pc-0.13 */
static void pc_compat_0_13(MachineState *machine)
{
pc_compat_1_2(machine);
}
static void pc_init_isa(MachineState *machine)
{
pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, TYPE_I440FX_PCI_DEVICE);
}
#ifdef CONFIG_XEN
static void pc_xen_hvm_init_pci(MachineState *machine)
{
const char *pci_type = has_igd_gfx_passthru ?
TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE : TYPE_I440FX_PCI_DEVICE;
pc_init1(machine,
TYPE_I440FX_PCI_HOST_BRIDGE,
pci_type);
}
static void pc_xen_hvm_init(MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
if (!xen_enabled()) {
error_report("xenfv machine requires the xen accelerator");
exit(1);
}
pc_xen_hvm_init_pci(machine);
pci_create_simple(pcms->bus, -1, "xen-platform");
}
#endif
#define DEFINE_I440FX_MACHINE(suffix, name, compatfn, optionfn) \
static void pc_init_##suffix(MachineState *machine) \
{ \
void (*compat)(MachineState *m) = (compatfn); \
if (compat) { \
compat(machine); \
} \
pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, \
TYPE_I440FX_PCI_DEVICE); \
} \
DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
static void pc_i440fx_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pcmc->default_nic_model = "e1000";
m->family = "pc_piix";
m->desc = "Standard PC (i440FX + PIIX, 1996)";
m->default_machine_opts = "firmware=bios-256k.bin";
m->default_display = "std";
machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
}
static void pc_i440fx_4_0_machine_options(MachineClass *m)
{
pc_i440fx_machine_options(m);
m->alias = "pc";
m->is_default = 1;
}
DEFINE_I440FX_MACHINE(v4_0, "pc-i440fx-4.0", NULL,
pc_i440fx_4_0_machine_options);
static void pc_i440fx_3_1_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_4_0_machine_options(m);
m->is_default = 0;
m->smbus_no_migration_support = true;
m->alias = NULL;
pcmc->pvh_enabled = false;
compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
}
DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL,
pc_i440fx_3_1_machine_options);
static void pc_i440fx_3_0_machine_options(MachineClass *m)
{
pc_i440fx_3_1_machine_options(m);
compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
}
DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL,
pc_i440fx_3_0_machine_options);
static void pc_i440fx_2_12_machine_options(MachineClass *m)
{
pc_i440fx_3_0_machine_options(m);
compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
}
DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12", NULL,
pc_i440fx_2_12_machine_options);
static void pc_i440fx_2_11_machine_options(MachineClass *m)
{
pc_i440fx_2_12_machine_options(m);
compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
}
DEFINE_I440FX_MACHINE(v2_11, "pc-i440fx-2.11", NULL,
pc_i440fx_2_11_machine_options);
static void pc_i440fx_2_10_machine_options(MachineClass *m)
{
pc_i440fx_2_11_machine_options(m);
compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
m->auto_enable_numa_with_memhp = false;
}
DEFINE_I440FX_MACHINE(v2_10, "pc-i440fx-2.10", NULL,
pc_i440fx_2_10_machine_options);
static void pc_i440fx_2_9_machine_options(MachineClass *m)
{
pc_i440fx_2_10_machine_options(m);
compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
}
DEFINE_I440FX_MACHINE(v2_9, "pc-i440fx-2.9", NULL,
pc_i440fx_2_9_machine_options);
static void pc_i440fx_2_8_machine_options(MachineClass *m)
{
pc_i440fx_2_9_machine_options(m);
compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
}
DEFINE_I440FX_MACHINE(v2_8, "pc-i440fx-2.8", NULL,
pc_i440fx_2_8_machine_options);
static void pc_i440fx_2_7_machine_options(MachineClass *m)
{
pc_i440fx_2_8_machine_options(m);
compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
}
DEFINE_I440FX_MACHINE(v2_7, "pc-i440fx-2.7", NULL,
pc_i440fx_2_7_machine_options);
static void pc_i440fx_2_6_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_7_machine_options(m);
pcmc->legacy_cpu_hotplug = true;
pcmc->linuxboot_dma_enabled = false;
compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
}
DEFINE_I440FX_MACHINE(v2_6, "pc-i440fx-2.6", NULL,
pc_i440fx_2_6_machine_options);
static void pc_i440fx_2_5_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_6_machine_options(m);
pcmc->save_tsc_khz = false;
m->legacy_fw_cfg_order = 1;
compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
}
DEFINE_I440FX_MACHINE(v2_5, "pc-i440fx-2.5", NULL,
pc_i440fx_2_5_machine_options);
static void pc_i440fx_2_4_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_5_machine_options(m);
m->hw_version = "2.4.0";
pcmc->broken_reserved_end = true;
compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
}
DEFINE_I440FX_MACHINE(v2_4, "pc-i440fx-2.4", NULL,
pc_i440fx_2_4_machine_options)
static void pc_i440fx_2_3_machine_options(MachineClass *m)
{
pc_i440fx_2_4_machine_options(m);
m->hw_version = "2.3.0";
compat_props_add(m->compat_props, hw_compat_2_3, hw_compat_2_3_len);
compat_props_add(m->compat_props, pc_compat_2_3, pc_compat_2_3_len);
}
DEFINE_I440FX_MACHINE(v2_3, "pc-i440fx-2.3", pc_compat_2_3_fn,
pc_i440fx_2_3_machine_options);
static void pc_i440fx_2_2_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_3_machine_options(m);
m->hw_version = "2.2.0";
m->default_machine_opts = "firmware=bios-256k.bin,suppress-vmdesc=on";
compat_props_add(m->compat_props, hw_compat_2_2, hw_compat_2_2_len);
compat_props_add(m->compat_props, pc_compat_2_2, pc_compat_2_2_len);
pcmc->rsdp_in_ram = false;
}
DEFINE_I440FX_MACHINE(v2_2, "pc-i440fx-2.2", pc_compat_2_2_fn,
pc_i440fx_2_2_machine_options);
static void pc_i440fx_2_1_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_2_machine_options(m);
m->hw_version = "2.1.0";
m->default_display = NULL;
compat_props_add(m->compat_props, hw_compat_2_1, hw_compat_2_1_len);
compat_props_add(m->compat_props, pc_compat_2_1, pc_compat_2_1_len);
pcmc->smbios_uuid_encoded = false;
pcmc->enforce_aligned_dimm = false;
}
DEFINE_I440FX_MACHINE(v2_1, "pc-i440fx-2.1", pc_compat_2_1_fn,
pc_i440fx_2_1_machine_options);
static void pc_i440fx_2_0_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_1_machine_options(m);
m->hw_version = "2.0.0";
compat_props_add(m->compat_props, pc_compat_2_0, pc_compat_2_0_len);
pcmc->smbios_legacy_mode = true;
pcmc->has_reserved_memory = false;
/* This value depends on the actual DSDT and SSDT compiled into
* the source QEMU; unfortunately it depends on the binary and
* not on the machine type, so we cannot make pc-i440fx-1.7 work on
* both QEMU 1.7 and QEMU 2.0.
*
* Large variations cause migration to fail for more than one
* consecutive value of the "-smp" maxcpus option.
*
* For small variations of the kind caused by different iasl versions,
* the 4k rounding usually leaves slack. However, there could be still
* one or two values that break. For QEMU 1.7 and QEMU 2.0 the
* slack is only ~10 bytes before one "-smp maxcpus" value breaks!
*
* 6652 is valid for QEMU 2.0, the right value for pc-i440fx-1.7 on
* QEMU 1.7 it is 6414. For RHEL/CentOS 7.0 it is 6418.
*/
pcmc->legacy_acpi_table_size = 6652;
pcmc->acpi_data_size = 0x10000;
}
DEFINE_I440FX_MACHINE(v2_0, "pc-i440fx-2.0", pc_compat_2_0_fn,
pc_i440fx_2_0_machine_options);
static void pc_i440fx_1_7_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_0_machine_options(m);
m->hw_version = "1.7.0";
m->default_machine_opts = NULL;
m->option_rom_has_mr = true;
compat_props_add(m->compat_props, pc_compat_1_7, pc_compat_1_7_len);
pcmc->smbios_defaults = false;
pcmc->gigabyte_align = false;
pcmc->legacy_acpi_table_size = 6414;
}
DEFINE_I440FX_MACHINE(v1_7, "pc-i440fx-1.7", pc_compat_1_7_fn,
pc_i440fx_1_7_machine_options);
static void pc_i440fx_1_6_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_1_7_machine_options(m);
m->hw_version = "1.6.0";
m->rom_file_has_mr = false;
compat_props_add(m->compat_props, pc_compat_1_6, pc_compat_1_6_len);
pcmc->has_acpi_build = false;
}
DEFINE_I440FX_MACHINE(v1_6, "pc-i440fx-1.6", pc_compat_1_6_fn,
pc_i440fx_1_6_machine_options);
static void pc_i440fx_1_5_machine_options(MachineClass *m)
{
pc_i440fx_1_6_machine_options(m);
m->hw_version = "1.5.0";
compat_props_add(m->compat_props, pc_compat_1_5, pc_compat_1_5_len);
}
DEFINE_I440FX_MACHINE(v1_5, "pc-i440fx-1.5", pc_compat_1_5_fn,
pc_i440fx_1_5_machine_options);
static void pc_i440fx_1_4_machine_options(MachineClass *m)
{
pc_i440fx_1_5_machine_options(m);
m->hw_version = "1.4.0";
m->hot_add_cpu = NULL;
compat_props_add(m->compat_props, pc_compat_1_4, pc_compat_1_4_len);
}
DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4", pc_compat_1_4_fn,
pc_i440fx_1_4_machine_options);
static void pc_i440fx_1_3_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("1.3.0")
{ "usb-tablet", "usb_version", "1" },
{ "virtio-net-pci", "ctrl_mac_addr", "off" },
{ "virtio-net-pci", "mq", "off" },
{ "e1000", "autonegotiation", "off" },
};
pc_i440fx_1_4_machine_options(m);
m->hw_version = "1.3.0";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v1_3, "pc-1.3", pc_compat_1_3,
pc_i440fx_1_3_machine_options);
static void pc_i440fx_1_2_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("1.2.0")
{ "nec-usb-xhci", "msi", "off" },
{ "nec-usb-xhci", "msix", "off" },
{ "qxl", "revision", "3" },
{ "qxl-vga", "revision", "3" },
{ "VGA", "mmio", "off" },
};
pc_i440fx_1_3_machine_options(m);
m->hw_version = "1.2.0";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v1_2, "pc-1.2", pc_compat_1_2,
pc_i440fx_1_2_machine_options);
static void pc_i440fx_1_1_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("1.1.0")
{ "virtio-scsi-pci", "hotplug", "off" },
{ "virtio-scsi-pci", "param_change", "off" },
{ "VGA", "vgamem_mb", "8" },
{ "vmware-svga", "vgamem_mb", "8" },
{ "qxl-vga", "vgamem_mb", "8" },
{ "qxl", "vgamem_mb", "8" },
{ "virtio-blk-pci", "config-wce", "off" },
};
pc_i440fx_1_2_machine_options(m);
m->hw_version = "1.1.0";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v1_1, "pc-1.1", pc_compat_1_2,
pc_i440fx_1_1_machine_options);
static void pc_i440fx_1_0_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("1.0")
{ TYPE_ISA_FDC, "check_media_rate", "off" },
{ "virtio-balloon-pci", "class", stringify(PCI_CLASS_MEMORY_RAM) },
{ "apic-common", "vapic", "off" },
{ TYPE_USB_DEVICE, "full-path", "no" },
};
pc_i440fx_1_1_machine_options(m);
m->hw_version = "1.0";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v1_0, "pc-1.0", pc_compat_1_2,
pc_i440fx_1_0_machine_options);
static void pc_i440fx_0_15_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("0.15")
};
pc_i440fx_1_0_machine_options(m);
m->hw_version = "0.15";
m->deprecation_reason = "use a newer machine type instead";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v0_15, "pc-0.15", pc_compat_1_2,
pc_i440fx_0_15_machine_options);
static void pc_i440fx_0_14_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("0.14")
{ "virtio-blk-pci", "event_idx", "off" },
{ "virtio-serial-pci", "event_idx", "off" },
{ "virtio-net-pci", "event_idx", "off" },
{ "virtio-balloon-pci", "event_idx", "off" },
{ "qxl", "revision", "2" },
{ "qxl-vga", "revision", "2" },
};
pc_i440fx_0_15_machine_options(m);
m->hw_version = "0.14";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v0_14, "pc-0.14", pc_compat_1_2,
pc_i440fx_0_14_machine_options);
static void pc_i440fx_0_13_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("0.13")
{ TYPE_PCI_DEVICE, "command_serr_enable", "off" },
{ "AC97", "use_broken_id", "1" },
{ "virtio-9p-pci", "vectors", "0" },
{ "VGA", "rombar", "0" },
{ "vmware-svga", "rombar", "0" },
};
pc_i440fx_0_14_machine_options(m);
m->hw_version = "0.13";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
pcmc->kvmclock_enabled = false;
}
DEFINE_I440FX_MACHINE(v0_13, "pc-0.13", pc_compat_0_13,
pc_i440fx_0_13_machine_options);
static void pc_i440fx_0_12_machine_options(MachineClass *m)
{
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("0.12")
{ "virtio-serial-pci", "max_ports", "1" },
{ "virtio-serial-pci", "vectors", "0" },
{ "usb-mouse", "serial", "1" },
{ "usb-tablet", "serial", "1" },
{ "usb-kbd", "serial", "1" },
};
pc_i440fx_0_13_machine_options(m);
m->hw_version = "0.12";
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
DEFINE_I440FX_MACHINE(v0_12, "pc-0.12", pc_compat_0_13,
pc_i440fx_0_12_machine_options);
typedef struct {
uint16_t gpu_device_id;
uint16_t pch_device_id;
uint8_t pch_revision_id;
} IGDDeviceIDInfo;
/* In real world different GPU should have different PCH. But actually
* the different PCH DIDs likely map to different PCH SKUs. We do the
* same thing for the GPU. For PCH, the different SKUs are going to be
* all the same silicon design and implementation, just different
* features turn on and off with fuses. The SW interfaces should be
* consistent across all SKUs in a given family (eg LPT). But just same
* features may not be supported.
*
* Most of these different PCH features probably don't matter to the
* Gfx driver, but obviously any difference in display port connections
* will so it should be fine with any PCH in case of passthrough.
*
* So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)
* scenarios, 0x9cc3 for BDW(Broadwell).
*/
static const IGDDeviceIDInfo igd_combo_id_infos[] = {
/* HSW Classic */
{0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */
{0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */
{0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */
{0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */
{0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */
/* HSW ULT */
{0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */
{0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */
{0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */
{0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */
{0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */
{0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */
/* HSW CRW */
{0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */
{0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */
/* HSW Server */
{0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */
/* HSW SRVR */
{0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */
/* BSW */
{0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */
{0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */
{0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */
{0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */
{0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */
{0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */
{0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */
{0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */
{0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */
{0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */
{0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */
};
static void isa_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->desc = "ISA bridge faked to support IGD PT";
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_BRIDGE_ISA;
};
static TypeInfo isa_bridge_info = {
.name = "igd-passthrough-isa-bridge",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = isa_bridge_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
static void pt_graphics_register_types(void)
{
type_register_static(&isa_bridge_info);
}
type_init(pt_graphics_register_types)
void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id)
{
struct PCIDevice *bridge_dev;
int i, num;
uint16_t pch_dev_id = 0xffff;
uint8_t pch_rev_id;
num = ARRAY_SIZE(igd_combo_id_infos);
for (i = 0; i < num; i++) {
if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) {
pch_dev_id = igd_combo_id_infos[i].pch_device_id;
pch_rev_id = igd_combo_id_infos[i].pch_revision_id;
}
}
if (pch_dev_id == 0xffff) {
return;
}
/* Currently IGD drivers always need to access PCH by 1f.0. */
bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0),
"igd-passthrough-isa-bridge");
/*
* Note that vendor id is always PCI_VENDOR_ID_INTEL.
*/
if (!bridge_dev) {
fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n");
return;
}
pci_config_set_device_id(bridge_dev->config, pch_dev_id);
pci_config_set_revision(bridge_dev->config, pch_rev_id);
}
static void isapc_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
m->desc = "ISA-only PC";
m->max_cpus = 1;
m->option_rom_has_mr = true;
m->rom_file_has_mr = false;
pcmc->pci_enabled = false;
pcmc->has_acpi_build = false;
pcmc->smbios_defaults = false;
pcmc->gigabyte_align = false;
pcmc->smbios_legacy_mode = true;
pcmc->has_reserved_memory = false;
pcmc->default_nic_model = "ne2k_isa";
m->default_cpu_type = X86_CPU_TYPE_NAME("486");
}
DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa,
isapc_machine_options);
#ifdef CONFIG_XEN
static void xenfv_machine_options(MachineClass *m)
{
m->desc = "Xen Fully-virtualized PC";
m->max_cpus = HVM_MAX_VCPUS;
m->default_machine_opts = "accel=xen";
}
DEFINE_PC_MACHINE(xenfv, "xenfv", pc_xen_hvm_init,
xenfv_machine_options);
#endif
|
pmp-tool/PMP | src/qemu/src-pmp/hw/gpio/nrf51_gpio.c | <gh_stars>1-10
/*
* nRF51 System-on-Chip general purpose input/output register definition
*
* Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
* Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf
*
* Copyright 2018 <NAME> <<EMAIL>>
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/gpio/nrf51_gpio.h"
#include "trace.h"
/*
* Check if the output driver is connected to the direction switch
* given the current configuration and logic level.
* It is not differentiated between standard and "high"(-power) drive modes.
*/
static bool is_connected(uint32_t config, uint32_t level)
{
bool state;
uint32_t drive_config = extract32(config, 8, 3);
switch (drive_config) {
case 0 ... 3:
state = true;
break;
case 4 ... 5:
state = level != 0;
break;
case 6 ... 7:
state = level == 0;
break;
default:
g_assert_not_reached();
break;
}
return state;
}
static int pull_value(uint32_t config)
{
int pull = extract32(config, 2, 2);
if (pull == NRF51_GPIO_PULLDOWN) {
return 0;
} else if (pull == NRF51_GPIO_PULLUP) {
return 1;
}
return -1;
}
static void update_output_irq(NRF51GPIOState *s, size_t i,
bool connected, bool level)
{
int64_t irq_level = connected ? level : -1;
bool old_connected = extract32(s->old_out_connected, i, 1);
bool old_level = extract32(s->old_out, i, 1);
if ((old_connected != connected) || (old_level != level)) {
qemu_set_irq(s->output[i], irq_level);
trace_nrf51_gpio_update_output_irq(i, irq_level);
}
s->old_out = deposit32(s->old_out, i, 1, level);
s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected);
}
static void update_state(NRF51GPIOState *s)
{
int pull;
size_t i;
bool connected_out, dir, connected_in, out, in, input;
for (i = 0; i < NRF51_GPIO_PINS; i++) {
pull = pull_value(s->cnf[i]);
dir = extract32(s->cnf[i], 0, 1);
connected_in = extract32(s->in_mask, i, 1);
out = extract32(s->out, i, 1);
in = extract32(s->in, i, 1);
input = !extract32(s->cnf[i], 1, 1);
connected_out = is_connected(s->cnf[i], out) && dir;
if (!input) {
if (pull >= 0) {
/* Input buffer disconnected from external drives */
s->in = deposit32(s->in, i, 1, pull);
}
} else {
if (connected_out && connected_in && out != in) {
/* Pin both driven externally and internally */
qemu_log_mask(LOG_GUEST_ERROR,
"GPIO pin %zu short circuited\n", i);
}
if (!connected_in) {
/*
* Floating input: the output stimulates IN if connected,
* otherwise pull-up/pull-down resistors put a value on both
* IN and OUT.
*/
if (pull >= 0 && !connected_out) {
connected_out = true;
out = pull;
}
if (connected_out) {
s->in = deposit32(s->in, i, 1, out);
}
}
}
update_output_irq(s, i, connected_out, out);
}
}
/*
* Direction is exposed in both the DIR register and the DIR bit
* of each PINs CNF configuration register. Reflect bits for pins in DIR
* to individual pin configuration registers.
*/
static void reflect_dir_bit_in_cnf(NRF51GPIOState *s)
{
size_t i;
uint32_t value = s->dir;
for (i = 0; i < NRF51_GPIO_PINS; i++) {
s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01);
}
}
static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size)
{
NRF51GPIOState *s = NRF51_GPIO(opaque);
uint64_t r = 0;
size_t idx;
switch (offset) {
case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR:
r = s->out;
break;
case NRF51_GPIO_REG_IN:
r = s->in;
break;
case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR:
r = s->dir;
break;
case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END:
idx = (offset - NRF51_GPIO_REG_CNF_START) / 4;
r = s->cnf[idx];
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: bad read offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
}
trace_nrf51_gpio_read(offset, r);
return r;
}
static void nrf51_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned int size)
{
NRF51GPIOState *s = NRF51_GPIO(opaque);
size_t idx;
trace_nrf51_gpio_write(offset, value);
switch (offset) {
case NRF51_GPIO_REG_OUT:
s->out = value;
break;
case NRF51_GPIO_REG_OUTSET:
s->out |= value;
break;
case NRF51_GPIO_REG_OUTCLR:
s->out &= ~value;
break;
case NRF51_GPIO_REG_DIR:
s->dir = value;
reflect_dir_bit_in_cnf(s);
break;
case NRF51_GPIO_REG_DIRSET:
s->dir |= value;
reflect_dir_bit_in_cnf(s);
break;
case NRF51_GPIO_REG_DIRCLR:
s->dir &= ~value;
reflect_dir_bit_in_cnf(s);
break;
case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END:
idx = (offset - NRF51_GPIO_REG_CNF_START) / 4;
s->cnf[idx] = value;
/*
* direction is exposed in both the DIR register and the DIR bit
* of each PINs CNF configuration register.
*/
s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: bad write offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
}
update_state(s);
}
static const MemoryRegionOps gpio_ops = {
.read = nrf51_gpio_read,
.write = nrf51_gpio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
static void nrf51_gpio_set(void *opaque, int line, int value)
{
NRF51GPIOState *s = NRF51_GPIO(opaque);
trace_nrf51_gpio_set(line, value);
assert(line >= 0 && line < NRF51_GPIO_PINS);
s->in_mask = deposit32(s->in_mask, line, 1, value >= 0);
if (value >= 0) {
s->in = deposit32(s->in, line, 1, value != 0);
}
update_state(s);
}
static void nrf51_gpio_reset(DeviceState *dev)
{
NRF51GPIOState *s = NRF51_GPIO(dev);
size_t i;
s->out = 0;
s->old_out = 0;
s->old_out_connected = 0;
s->in = 0;
s->in_mask = 0;
s->dir = 0;
for (i = 0; i < NRF51_GPIO_PINS; i++) {
s->cnf[i] = 0x00000002;
}
}
static const VMStateDescription vmstate_nrf51_gpio = {
.name = TYPE_NRF51_GPIO,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(out, NRF51GPIOState),
VMSTATE_UINT32(in, NRF51GPIOState),
VMSTATE_UINT32(in_mask, NRF51GPIOState),
VMSTATE_UINT32(dir, NRF51GPIOState),
VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS),
VMSTATE_UINT32(old_out, NRF51GPIOState),
VMSTATE_UINT32(old_out_connected, NRF51GPIOState),
VMSTATE_END_OF_LIST()
}
};
static void nrf51_gpio_init(Object *obj)
{
NRF51GPIOState *s = NRF51_GPIO(obj);
memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
TYPE_NRF51_GPIO, NRF51_GPIO_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS);
qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS);
}
static void nrf51_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_nrf51_gpio;
dc->reset = nrf51_gpio_reset;
dc->desc = "nRF51 GPIO";
}
static const TypeInfo nrf51_gpio_info = {
.name = TYPE_NRF51_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NRF51GPIOState),
.instance_init = nrf51_gpio_init,
.class_init = nrf51_gpio_class_init
};
static void nrf51_gpio_register_types(void)
{
type_register_static(&nrf51_gpio_info);
}
type_init(nrf51_gpio_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/ui/egl-headless.c | #include "qemu/osdep.h"
#include "qemu-common.h"
#include "sysemu/sysemu.h"
#include "ui/console.h"
#include "ui/egl-helpers.h"
#include "ui/egl-context.h"
#include "ui/shader.h"
typedef struct egl_dpy {
DisplayChangeListener dcl;
DisplaySurface *ds;
QemuGLShader *gls;
egl_fb guest_fb;
egl_fb cursor_fb;
egl_fb blit_fb;
bool y_0_top;
uint32_t pos_x;
uint32_t pos_y;
} egl_dpy;
/* ------------------------------------------------------------------ */
static void egl_refresh(DisplayChangeListener *dcl)
{
graphic_hw_update(dcl->con);
}
static void egl_gfx_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
{
}
static void egl_gfx_switch(DisplayChangeListener *dcl,
struct DisplaySurface *new_surface)
{
egl_dpy *edpy = container_of(dcl, egl_dpy, dcl);
edpy->ds = new_surface;
}
static QEMUGLContext egl_create_context(DisplayChangeListener *dcl,
QEMUGLParams *params)
{
eglMakeCurrent(qemu_egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE,
qemu_egl_rn_ctx);
return qemu_egl_create_context(dcl, params);
}
static void egl_scanout_disable(DisplayChangeListener *dcl)
{
egl_dpy *edpy = container_of(dcl, egl_dpy, dcl);
egl_fb_destroy(&edpy->guest_fb);
egl_fb_destroy(&edpy->blit_fb);
}
static void egl_scanout_texture(DisplayChangeListener *dcl,
uint32_t backing_id,
bool backing_y_0_top,
uint32_t backing_width,
uint32_t backing_height,
uint32_t x, uint32_t y,
uint32_t w, uint32_t h)
{
egl_dpy *edpy = container_of(dcl, egl_dpy, dcl);
edpy->y_0_top = backing_y_0_top;
/* source framebuffer */
egl_fb_setup_for_tex(&edpy->guest_fb,
backing_width, backing_height, backing_id, false);
/* dest framebuffer */
if (edpy->blit_fb.width != backing_width ||
edpy->blit_fb.height != backing_height) {
egl_fb_destroy(&edpy->blit_fb);
egl_fb_setup_new_tex(&edpy->blit_fb, backing_width, backing_height);
}
}
static void egl_scanout_dmabuf(DisplayChangeListener *dcl,
QemuDmaBuf *dmabuf)
{
egl_dmabuf_import_texture(dmabuf);
if (!dmabuf->texture) {
return;
}
egl_scanout_texture(dcl, dmabuf->texture,
false, dmabuf->width, dmabuf->height,
0, 0, dmabuf->width, dmabuf->height);
}
static void egl_cursor_dmabuf(DisplayChangeListener *dcl,
QemuDmaBuf *dmabuf, bool have_hot,
uint32_t hot_x, uint32_t hot_y)
{
egl_dpy *edpy = container_of(dcl, egl_dpy, dcl);
if (dmabuf) {
egl_dmabuf_import_texture(dmabuf);
if (!dmabuf->texture) {
return;
}
egl_fb_setup_for_tex(&edpy->cursor_fb, dmabuf->width, dmabuf->height,
dmabuf->texture, false);
} else {
egl_fb_destroy(&edpy->cursor_fb);
}
}
static void egl_cursor_position(DisplayChangeListener *dcl,
uint32_t pos_x, uint32_t pos_y)
{
egl_dpy *edpy = container_of(dcl, egl_dpy, dcl);
edpy->pos_x = pos_x;
edpy->pos_y = pos_y;
}
static void egl_release_dmabuf(DisplayChangeListener *dcl,
QemuDmaBuf *dmabuf)
{
egl_dmabuf_release_texture(dmabuf);
}
static void egl_scanout_flush(DisplayChangeListener *dcl,
uint32_t x, uint32_t y,
uint32_t w, uint32_t h)
{
egl_dpy *edpy = container_of(dcl, egl_dpy, dcl);
if (!edpy->guest_fb.texture || !edpy->ds) {
return;
}
assert(surface_width(edpy->ds) == edpy->guest_fb.width);
assert(surface_height(edpy->ds) == edpy->guest_fb.height);
assert(surface_format(edpy->ds) == PIXMAN_x8r8g8b8);
if (edpy->cursor_fb.texture) {
/* have cursor -> render using textures */
egl_texture_blit(edpy->gls, &edpy->blit_fb, &edpy->guest_fb,
!edpy->y_0_top);
egl_texture_blend(edpy->gls, &edpy->blit_fb, &edpy->cursor_fb,
!edpy->y_0_top, edpy->pos_x, edpy->pos_y,
1.0, 1.0);
} else {
/* no cursor -> use simple framebuffer blit */
egl_fb_blit(&edpy->blit_fb, &edpy->guest_fb, edpy->y_0_top);
}
egl_fb_read(surface_data(edpy->ds), &edpy->blit_fb);
dpy_gfx_update(edpy->dcl.con, x, y, w, h);
}
static const DisplayChangeListenerOps egl_ops = {
.dpy_name = "egl-headless",
.dpy_refresh = egl_refresh,
.dpy_gfx_update = egl_gfx_update,
.dpy_gfx_switch = egl_gfx_switch,
.dpy_gl_ctx_create = egl_create_context,
.dpy_gl_ctx_destroy = qemu_egl_destroy_context,
.dpy_gl_ctx_make_current = qemu_egl_make_context_current,
.dpy_gl_ctx_get_current = qemu_egl_get_current_context,
.dpy_gl_scanout_disable = egl_scanout_disable,
.dpy_gl_scanout_texture = egl_scanout_texture,
.dpy_gl_scanout_dmabuf = egl_scanout_dmabuf,
.dpy_gl_cursor_dmabuf = egl_cursor_dmabuf,
.dpy_gl_cursor_position = egl_cursor_position,
.dpy_gl_release_dmabuf = egl_release_dmabuf,
.dpy_gl_update = egl_scanout_flush,
};
static void early_egl_headless_init(DisplayOptions *opts)
{
display_opengl = 1;
}
static void egl_headless_init(DisplayState *ds, DisplayOptions *opts)
{
DisplayGLMode mode = opts->has_gl ? opts->gl : DISPLAYGL_MODE_ON;
QemuConsole *con;
egl_dpy *edpy;
int idx;
if (egl_rendernode_init(opts->u.egl_headless.rendernode, mode) < 0) {
error_report("egl: render node init failed");
exit(1);
}
for (idx = 0;; idx++) {
con = qemu_console_lookup_by_index(idx);
if (!con || !qemu_console_is_graphic(con)) {
break;
}
edpy = g_new0(egl_dpy, 1);
edpy->dcl.con = con;
edpy->dcl.ops = &egl_ops;
edpy->gls = qemu_gl_init_shader();
register_displaychangelistener(&edpy->dcl);
}
}
static QemuDisplay qemu_display_egl = {
.type = DISPLAY_TYPE_EGL_HEADLESS,
.early_init = early_egl_headless_init,
.init = egl_headless_init,
};
static void register_egl(void)
{
qemu_display_register(&qemu_display_egl);
}
type_init(register_egl);
|
pmp-tool/PMP | src/qemu/src-pmp/slirp/src/misc.c | <reponame>pmp-tool/PMP
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 1995 <NAME>.
*/
#include "slirp.h"
inline void
insque(void *a, void *b)
{
register struct quehead *element = (struct quehead *) a;
register struct quehead *head = (struct quehead *) b;
element->qh_link = head->qh_link;
head->qh_link = (struct quehead *)element;
element->qh_rlink = (struct quehead *)head;
((struct quehead *)(element->qh_link))->qh_rlink
= (struct quehead *)element;
}
inline void
remque(void *a)
{
register struct quehead *element = (struct quehead *) a;
((struct quehead *)(element->qh_link))->qh_rlink = element->qh_rlink;
((struct quehead *)(element->qh_rlink))->qh_link = element->qh_link;
element->qh_rlink = NULL;
}
/* TODO: IPv6 */
struct gfwd_list *
add_guestfwd(struct gfwd_list **ex_ptr,
SlirpWriteCb write_cb, void *opaque,
struct in_addr addr, int port)
{
struct gfwd_list *f = g_new0(struct gfwd_list, 1);
f->write_cb = write_cb;
f->opaque = opaque;
f->ex_fport = port;
f->ex_addr = addr;
f->ex_next = *ex_ptr;
*ex_ptr = f;
return f;
}
struct gfwd_list *
add_exec(struct gfwd_list **ex_ptr, const char *cmdline,
struct in_addr addr, int port)
{
struct gfwd_list *f = add_guestfwd(ex_ptr, NULL, NULL, addr, port);
f->ex_exec = g_strdup(cmdline);
return f;
}
static int
slirp_socketpair_with_oob(int sv[2])
{
struct sockaddr_in addr = {
.sin_family = AF_INET,
.sin_port = 0,
.sin_addr.s_addr = INADDR_ANY,
};
socklen_t addrlen = sizeof(addr);
int ret, s;
sv[1] = -1;
s = slirp_socket(AF_INET, SOCK_STREAM, 0);
if (s < 0 || bind(s, (struct sockaddr *)&addr, addrlen) < 0 ||
listen(s, 1) < 0 ||
getsockname(s, (struct sockaddr *)&addr, &addrlen) < 0) {
goto err;
}
sv[1] = slirp_socket(AF_INET, SOCK_STREAM, 0);
if (sv[1] < 0) {
goto err;
}
/*
* This connect won't block because we've already listen()ed on
* the server end (even though we won't accept() the connection
* until later on).
*/
do {
ret = connect(sv[1], (struct sockaddr *)&addr, addrlen);
} while (ret < 0 && errno == EINTR);
if (ret < 0) {
goto err;
}
do {
sv[0] = accept(s, (struct sockaddr *)&addr, &addrlen);
} while (sv[0] < 0 && errno == EINTR);
if (sv[0] < 0) {
goto err;
}
closesocket(s);
return 0;
err:
g_critical("slirp_socketpair(): %s", strerror(errno));
if (s >= 0) {
closesocket(s);
}
if (sv[1] >= 0) {
closesocket(sv[1]);
}
return -1;
}
static void
fork_exec_child_setup(gpointer data)
{
#ifndef _WIN32
setsid();
#endif
}
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
#if !GLIB_CHECK_VERSION(2, 58, 0)
typedef struct SlirpGSpawnFds {
GSpawnChildSetupFunc child_setup;
gpointer user_data;
gint stdin_fd;
gint stdout_fd;
gint stderr_fd;
} SlirpGSpawnFds;
static inline void
slirp_gspawn_fds_setup(gpointer user_data)
{
SlirpGSpawnFds *q = (SlirpGSpawnFds *)user_data;
dup2(q->stdin_fd, 0);
dup2(q->stdout_fd, 1);
dup2(q->stderr_fd, 2);
q->child_setup(q->user_data);
}
#endif
static inline gboolean
g_spawn_async_with_fds_slirp(const gchar *working_directory,
gchar **argv,
gchar **envp,
GSpawnFlags flags,
GSpawnChildSetupFunc child_setup,
gpointer user_data,
GPid *child_pid,
gint stdin_fd,
gint stdout_fd,
gint stderr_fd,
GError **error)
{
#if GLIB_CHECK_VERSION(2, 58, 0)
return g_spawn_async_with_fds(working_directory, argv, envp, flags,
child_setup, user_data,
child_pid, stdin_fd, stdout_fd, stderr_fd,
error);
#else
SlirpGSpawnFds setup = {
.child_setup = child_setup,
.user_data = user_data,
.stdin_fd = stdin_fd,
.stdout_fd = stdout_fd,
.stderr_fd = stderr_fd,
};
return g_spawn_async(working_directory, argv, envp, flags,
slirp_gspawn_fds_setup, &setup,
child_pid, error);
#endif
}
#define g_spawn_async_with_fds(wd, argv, env, f, c, d, p, ifd, ofd, efd, err) \
g_spawn_async_with_fds_slirp(wd, argv, env, f, c, d, p, ifd, ofd, efd, err)
#pragma GCC diagnostic pop
int
fork_exec(struct socket *so, const char *ex)
{
GError *err = NULL;
char **argv;
int opt, sp[2];
DEBUG_CALL("fork_exec");
DEBUG_ARG("so = %p", so);
DEBUG_ARG("ex = %p", ex);
if (slirp_socketpair_with_oob(sp) < 0) {
return 0;
}
argv = g_strsplit(ex, " ", -1);
g_spawn_async_with_fds(NULL /* cwd */,
argv,
NULL /* env */,
G_SPAWN_SEARCH_PATH,
fork_exec_child_setup, NULL /* data */,
NULL /* child_pid */,
sp[1], sp[1], sp[1],
&err);
g_strfreev(argv);
if (err) {
g_critical("fork_exec: %s", err->message);
g_error_free(err);
closesocket(sp[0]);
closesocket(sp[1]);
return 0;
}
so->s = sp[0];
closesocket(sp[1]);
slirp_socket_set_fast_reuse(so->s);
opt = 1;
setsockopt(so->s, SOL_SOCKET, SO_OOBINLINE, &opt, sizeof(int));
slirp_set_nonblock(so->s);
so->slirp->cb->register_poll_fd(so->s, so->slirp->opaque);
return 1;
}
char *slirp_connection_info(Slirp *slirp)
{
GString *str = g_string_new(NULL);
const char * const tcpstates[] = {
[TCPS_CLOSED] = "CLOSED",
[TCPS_LISTEN] = "LISTEN",
[TCPS_SYN_SENT] = "SYN_SENT",
[TCPS_SYN_RECEIVED] = "SYN_RCVD",
[TCPS_ESTABLISHED] = "ESTABLISHED",
[TCPS_CLOSE_WAIT] = "CLOSE_WAIT",
[TCPS_FIN_WAIT_1] = "FIN_WAIT_1",
[TCPS_CLOSING] = "CLOSING",
[TCPS_LAST_ACK] = "LAST_ACK",
[TCPS_FIN_WAIT_2] = "FIN_WAIT_2",
[TCPS_TIME_WAIT] = "TIME_WAIT",
};
struct in_addr dst_addr;
struct sockaddr_in src;
socklen_t src_len;
uint16_t dst_port;
struct socket *so;
const char *state;
char buf[20];
g_string_append_printf(str,
" Protocol[State] FD Source Address Port "
"Dest. Address Port RecvQ SendQ\n");
/* TODO: IPv6 */
for (so = slirp->tcb.so_next; so != &slirp->tcb; so = so->so_next) {
if (so->so_state & SS_HOSTFWD) {
state = "HOST_FORWARD";
} else if (so->so_tcpcb) {
state = tcpstates[so->so_tcpcb->t_state];
} else {
state = "NONE";
}
if (so->so_state & (SS_HOSTFWD | SS_INCOMING)) {
src_len = sizeof(src);
getsockname(so->s, (struct sockaddr *)&src, &src_len);
dst_addr = so->so_laddr;
dst_port = so->so_lport;
} else {
src.sin_addr = so->so_laddr;
src.sin_port = so->so_lport;
dst_addr = so->so_faddr;
dst_port = so->so_fport;
}
snprintf(buf, sizeof(buf), " TCP[%s]", state);
g_string_append_printf(str, "%-19s %3d %15s %5d ", buf, so->s,
src.sin_addr.s_addr ? inet_ntoa(src.sin_addr) : "*",
ntohs(src.sin_port));
g_string_append_printf(str, "%15s %5d %5d %5d\n",
inet_ntoa(dst_addr), ntohs(dst_port),
so->so_rcv.sb_cc, so->so_snd.sb_cc);
}
for (so = slirp->udb.so_next; so != &slirp->udb; so = so->so_next) {
if (so->so_state & SS_HOSTFWD) {
snprintf(buf, sizeof(buf), " UDP[HOST_FORWARD]");
src_len = sizeof(src);
getsockname(so->s, (struct sockaddr *)&src, &src_len);
dst_addr = so->so_laddr;
dst_port = so->so_lport;
} else {
snprintf(buf, sizeof(buf), " UDP[%d sec]",
(so->so_expire - curtime) / 1000);
src.sin_addr = so->so_laddr;
src.sin_port = so->so_lport;
dst_addr = so->so_faddr;
dst_port = so->so_fport;
}
g_string_append_printf(str, "%-19s %3d %15s %5d ", buf, so->s,
src.sin_addr.s_addr ? inet_ntoa(src.sin_addr) : "*",
ntohs(src.sin_port));
g_string_append_printf(str, "%15s %5d %5d %5d\n",
inet_ntoa(dst_addr), ntohs(dst_port),
so->so_rcv.sb_cc, so->so_snd.sb_cc);
}
for (so = slirp->icmp.so_next; so != &slirp->icmp; so = so->so_next) {
snprintf(buf, sizeof(buf), " ICMP[%d sec]",
(so->so_expire - curtime) / 1000);
src.sin_addr = so->so_laddr;
dst_addr = so->so_faddr;
g_string_append_printf(str, "%-19s %3d %15s - ", buf, so->s,
src.sin_addr.s_addr ? inet_ntoa(src.sin_addr) : "*");
g_string_append_printf(str, "%15s - %5d %5d\n", inet_ntoa(dst_addr),
so->so_rcv.sb_cc, so->so_snd.sb_cc);
}
return g_string_free(str, FALSE);
}
|
pmp-tool/PMP | src/qemu/src-pmp/tests/uefi-test-tools/UefiTestToolsPkg/Include/Guid/BiosTablesTest.h | <gh_stars>1-10
/** @file
Expose the address(es) of the ACPI RSD PTR table(s) in a MB-aligned structure
to the hypervisor.
The hypervisor locates the MB-aligned structure based on the signature GUID
that is at offset 0 in the structure. Once the RSD PTR address(es) are
retrieved, the hypervisor may perform various ACPI checks.
This feature is a development aid, for supporting ACPI table unit tests in
hypervisors. Do not enable in production builds.
Copyright (C) 2019, Red Hat, Inc.
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License that accompanies this
distribution. The full text of the license may be found at
<http://opensource.org/licenses/bsd-license.php>.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __BIOS_TABLES_TEST_H__
#define __BIOS_TABLES_TEST_H__
#include <Uefi/UefiBaseType.h>
#define BIOS_TABLES_TEST_GUID \
{ \
0x5478594e, \
0xdfcb, \
0x425f, \
{ 0x8e, 0x42, 0xc8, 0xaf, 0xf8, 0x8a, 0x88, 0x7a } \
}
extern EFI_GUID gBiosTablesTestGuid;
//
// The following structure must be allocated in Boot Services Data type memory,
// aligned at a 1MB boundary.
//
#pragma pack (1)
typedef struct {
//
// The signature GUID is written to the MB-aligned structure from
// gBiosTablesTestGuid, but with all bits inverted. That's the actual GUID
// value that the hypervisor should look for at each MB boundary, looping
// over all guest RAM pages with that alignment, until a match is found. The
// bit-flipping occurs in order not to store the actual GUID in any UEFI
// executable, which might confuse guest memory analysis. Note that EFI_GUID
// has little endian representation.
//
EFI_GUID InverseSignatureGuid;
//
// The Rsdp10 and Rsdp20 fields may be read when the signature GUID matches.
// Rsdp10 is the guest-physical address of the ACPI 1.0 specification RSD PTR
// table, in 8-byte little endian representation. Rsdp20 is the same, for the
// ACPI 2.0 or later specification RSD PTR table. Each of these fields may be
// zero (independently of the other) if the UEFI System Table does not
// provide the corresponding UEFI Configuration Table.
//
EFI_PHYSICAL_ADDRESS Rsdp10;
EFI_PHYSICAL_ADDRESS Rsdp20;
} BIOS_TABLES_TEST;
#pragma pack ()
#endif // __BIOS_TABLES_TEST_H__
|
pmp-tool/PMP | src/qemu/src-pmp/include/hw/xen/xen_common.h | #ifndef QEMU_HW_XEN_COMMON_H
#define QEMU_HW_XEN_COMMON_H
/*
* If we have new enough libxenctrl then we do not want/need these compat
* interfaces, despite what the user supplied cflags might say. They
* must be undefined before including xenctrl.h
*/
#undef XC_WANT_COMPAT_EVTCHN_API
#undef XC_WANT_COMPAT_GNTTAB_API
#undef XC_WANT_COMPAT_MAP_FOREIGN_API
#include <xenctrl.h>
#include <xenstore.h>
#include <xen/io/xenbus.h>
#include "hw/hw.h"
#include "hw/xen/xen.h"
#include "hw/pci/pci.h"
#include "qemu/queue.h"
#include "hw/xen/trace.h"
extern xc_interface *xen_xc;
/*
* We don't support Xen prior to 4.2.0.
*/
/* Xen 4.2 through 4.6 */
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40701
typedef xc_interface xenforeignmemory_handle;
typedef xc_evtchn xenevtchn_handle;
typedef xc_gnttab xengnttab_handle;
typedef evtchn_port_or_error_t xenevtchn_port_or_error_t;
#define xenevtchn_open(l, f) xc_evtchn_open(l, f);
#define xenevtchn_close(h) xc_evtchn_close(h)
#define xenevtchn_fd(h) xc_evtchn_fd(h)
#define xenevtchn_pending(h) xc_evtchn_pending(h)
#define xenevtchn_notify(h, p) xc_evtchn_notify(h, p)
#define xenevtchn_bind_interdomain(h, d, p) xc_evtchn_bind_interdomain(h, d, p)
#define xenevtchn_unmask(h, p) xc_evtchn_unmask(h, p)
#define xenevtchn_unbind(h, p) xc_evtchn_unbind(h, p)
#define xengnttab_open(l, f) xc_gnttab_open(l, f)
#define xengnttab_close(h) xc_gnttab_close(h)
#define xengnttab_set_max_grants(h, n) xc_gnttab_set_max_grants(h, n)
#define xengnttab_map_grant_ref(h, d, r, p) xc_gnttab_map_grant_ref(h, d, r, p)
#define xengnttab_unmap(h, a, n) xc_gnttab_munmap(h, a, n)
#define xengnttab_map_grant_refs(h, c, d, r, p) \
xc_gnttab_map_grant_refs(h, c, d, r, p)
#define xengnttab_map_domain_grant_refs(h, c, d, r, p) \
xc_gnttab_map_domain_grant_refs(h, c, d, r, p)
#define xenforeignmemory_open(l, f) xen_xc
#define xenforeignmemory_close(h)
static inline void *xenforeignmemory_map(xc_interface *h, uint32_t dom,
int prot, size_t pages,
const xen_pfn_t arr[/*pages*/],
int err[/*pages*/])
{
if (err)
return xc_map_foreign_bulk(h, dom, prot, arr, err, pages);
else
return xc_map_foreign_pages(h, dom, prot, arr, pages);
}
#define xenforeignmemory_unmap(h, p, s) munmap(p, s * XC_PAGE_SIZE)
#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40701 */
#include <xenevtchn.h>
#include <xengnttab.h>
#include <xenforeignmemory.h>
#endif
extern xenforeignmemory_handle *xen_fmem;
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40900
typedef xc_interface xendevicemodel_handle;
#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40900 */
#undef XC_WANT_COMPAT_DEVICEMODEL_API
#include <xendevicemodel.h>
#endif
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 41100
static inline int xendevicemodel_relocate_memory(
xendevicemodel_handle *dmod, domid_t domid, uint32_t size, uint64_t src_gfn,
uint64_t dst_gfn)
{
uint32_t i;
int rc;
for (i = 0; i < size; i++) {
unsigned long idx = src_gfn + i;
xen_pfn_t gpfn = dst_gfn + i;
rc = xc_domain_add_to_physmap(xen_xc, domid, XENMAPSPACE_gmfn, idx,
gpfn);
if (rc) {
return rc;
}
}
return 0;
}
static inline int xendevicemodel_pin_memory_cacheattr(
xendevicemodel_handle *dmod, domid_t domid, uint64_t start, uint64_t end,
uint32_t type)
{
return xc_domain_pin_memory_cacheattr(xen_xc, domid, start, end, type);
}
typedef void xenforeignmemory_resource_handle;
#define XENMEM_resource_ioreq_server 0
#define XENMEM_resource_ioreq_server_frame_bufioreq 0
#define XENMEM_resource_ioreq_server_frame_ioreq(n) (1 + (n))
static inline xenforeignmemory_resource_handle *xenforeignmemory_map_resource(
xenforeignmemory_handle *fmem, domid_t domid, unsigned int type,
unsigned int id, unsigned long frame, unsigned long nr_frames,
void **paddr, int prot, int flags)
{
errno = EOPNOTSUPP;
return NULL;
}
#endif /* CONFIG_XEN_CTRL_INTERFACE_VERSION < 41100 */
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 41000
#define XEN_COMPAT_PHYSMAP
static inline void *xenforeignmemory_map2(xenforeignmemory_handle *h,
uint32_t dom, void *addr,
int prot, int flags, size_t pages,
const xen_pfn_t arr[/*pages*/],
int err[/*pages*/])
{
assert(addr == NULL && flags == 0);
return xenforeignmemory_map(h, dom, prot, pages, arr, err);
}
static inline int xentoolcore_restrict_all(domid_t domid)
{
errno = ENOTTY;
return -1;
}
static inline int xendevicemodel_shutdown(xendevicemodel_handle *dmod,
domid_t domid, unsigned int reason)
{
errno = ENOTTY;
return -1;
}
#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 41000 */
#include <xentoolcore.h>
#endif
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40900
static inline xendevicemodel_handle *xendevicemodel_open(
struct xentoollog_logger *logger, unsigned int open_flags)
{
return xen_xc;
}
#if CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40500
static inline int xendevicemodel_create_ioreq_server(
xendevicemodel_handle *dmod, domid_t domid, int handle_bufioreq,
ioservid_t *id)
{
return xc_hvm_create_ioreq_server(dmod, domid, handle_bufioreq,
id);
}
static inline int xendevicemodel_get_ioreq_server_info(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id,
xen_pfn_t *ioreq_pfn, xen_pfn_t *bufioreq_pfn,
evtchn_port_t *bufioreq_port)
{
return xc_hvm_get_ioreq_server_info(dmod, domid, id, ioreq_pfn,
bufioreq_pfn, bufioreq_port);
}
static inline int xendevicemodel_map_io_range_to_ioreq_server(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int is_mmio,
uint64_t start, uint64_t end)
{
return xc_hvm_map_io_range_to_ioreq_server(dmod, domid, id, is_mmio,
start, end);
}
static inline int xendevicemodel_unmap_io_range_from_ioreq_server(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int is_mmio,
uint64_t start, uint64_t end)
{
return xc_hvm_unmap_io_range_from_ioreq_server(dmod, domid, id, is_mmio,
start, end);
}
static inline int xendevicemodel_map_pcidev_to_ioreq_server(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id,
uint16_t segment, uint8_t bus, uint8_t device, uint8_t function)
{
return xc_hvm_map_pcidev_to_ioreq_server(dmod, domid, id, segment,
bus, device, function);
}
static inline int xendevicemodel_unmap_pcidev_from_ioreq_server(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id,
uint16_t segment, uint8_t bus, uint8_t device, uint8_t function)
{
return xc_hvm_unmap_pcidev_from_ioreq_server(dmod, domid, id, segment,
bus, device, function);
}
static inline int xendevicemodel_destroy_ioreq_server(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id)
{
return xc_hvm_destroy_ioreq_server(dmod, domid, id);
}
static inline int xendevicemodel_set_ioreq_server_state(
xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int enabled)
{
return xc_hvm_set_ioreq_server_state(dmod, domid, id, enabled);
}
#endif /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40500 */
static inline int xendevicemodel_set_pci_intx_level(
xendevicemodel_handle *dmod, domid_t domid, uint16_t segment,
uint8_t bus, uint8_t device, uint8_t intx, unsigned int level)
{
return xc_hvm_set_pci_intx_level(dmod, domid, segment, bus, device,
intx, level);
}
static inline int xendevicemodel_set_isa_irq_level(
xendevicemodel_handle *dmod, domid_t domid, uint8_t irq,
unsigned int level)
{
return xc_hvm_set_isa_irq_level(dmod, domid, irq, level);
}
static inline int xendevicemodel_set_pci_link_route(
xendevicemodel_handle *dmod, domid_t domid, uint8_t link, uint8_t irq)
{
return xc_hvm_set_pci_link_route(dmod, domid, link, irq);
}
static inline int xendevicemodel_inject_msi(
xendevicemodel_handle *dmod, domid_t domid, uint64_t msi_addr,
uint32_t msi_data)
{
return xc_hvm_inject_msi(dmod, domid, msi_addr, msi_data);
}
static inline int xendevicemodel_track_dirty_vram(
xendevicemodel_handle *dmod, domid_t domid, uint64_t first_pfn,
uint32_t nr, unsigned long *dirty_bitmap)
{
return xc_hvm_track_dirty_vram(dmod, domid, first_pfn, nr,
dirty_bitmap);
}
static inline int xendevicemodel_modified_memory(
xendevicemodel_handle *dmod, domid_t domid, uint64_t first_pfn,
uint32_t nr)
{
return xc_hvm_modified_memory(dmod, domid, first_pfn, nr);
}
static inline int xendevicemodel_set_mem_type(
xendevicemodel_handle *dmod, domid_t domid, hvmmem_type_t mem_type,
uint64_t first_pfn, uint32_t nr)
{
return xc_hvm_set_mem_type(dmod, domid, mem_type, first_pfn, nr);
}
#endif
extern xendevicemodel_handle *xen_dmod;
static inline int xen_set_mem_type(domid_t domid, hvmmem_type_t type,
uint64_t first_pfn, uint32_t nr)
{
return xendevicemodel_set_mem_type(xen_dmod, domid, type, first_pfn,
nr);
}
static inline int xen_set_pci_intx_level(domid_t domid, uint16_t segment,
uint8_t bus, uint8_t device,
uint8_t intx, unsigned int level)
{
return xendevicemodel_set_pci_intx_level(xen_dmod, domid, segment, bus,
device, intx, level);
}
static inline int xen_set_pci_link_route(domid_t domid, uint8_t link,
uint8_t irq)
{
return xendevicemodel_set_pci_link_route(xen_dmod, domid, link, irq);
}
static inline int xen_inject_msi(domid_t domid, uint64_t msi_addr,
uint32_t msi_data)
{
return xendevicemodel_inject_msi(xen_dmod, domid, msi_addr, msi_data);
}
static inline int xen_set_isa_irq_level(domid_t domid, uint8_t irq,
unsigned int level)
{
return xendevicemodel_set_isa_irq_level(xen_dmod, domid, irq, level);
}
static inline int xen_track_dirty_vram(domid_t domid, uint64_t first_pfn,
uint32_t nr, unsigned long *bitmap)
{
return xendevicemodel_track_dirty_vram(xen_dmod, domid, first_pfn, nr,
bitmap);
}
static inline int xen_modified_memory(domid_t domid, uint64_t first_pfn,
uint32_t nr)
{
return xendevicemodel_modified_memory(xen_dmod, domid, first_pfn, nr);
}
static inline int xen_restrict(domid_t domid)
{
int rc;
rc = xentoolcore_restrict_all(domid);
trace_xen_domid_restrict(rc ? errno : 0);
return rc;
}
void destroy_hvm_domain(bool reboot);
/* shutdown/destroy current domain because of an error */
void xen_shutdown_fatal_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
#ifdef HVM_PARAM_VMPORT_REGS_PFN
static inline int xen_get_vmport_regs_pfn(xc_interface *xc, domid_t dom,
xen_pfn_t *vmport_regs_pfn)
{
int rc;
uint64_t value;
rc = xc_hvm_param_get(xc, dom, HVM_PARAM_VMPORT_REGS_PFN, &value);
if (rc >= 0) {
*vmport_regs_pfn = (xen_pfn_t) value;
}
return rc;
}
#else
static inline int xen_get_vmport_regs_pfn(xc_interface *xc, domid_t dom,
xen_pfn_t *vmport_regs_pfn)
{
return -ENOSYS;
}
#endif
/* Xen before 4.6 */
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40600
#ifndef HVM_IOREQSRV_BUFIOREQ_ATOMIC
#define HVM_IOREQSRV_BUFIOREQ_ATOMIC 2
#endif
#endif
static inline int xen_get_default_ioreq_server_info(domid_t dom,
xen_pfn_t *ioreq_pfn,
xen_pfn_t *bufioreq_pfn,
evtchn_port_t
*bufioreq_evtchn)
{
unsigned long param;
int rc;
rc = xc_get_hvm_param(xen_xc, dom, HVM_PARAM_IOREQ_PFN, ¶m);
if (rc < 0) {
fprintf(stderr, "failed to get HVM_PARAM_IOREQ_PFN\n");
return -1;
}
*ioreq_pfn = param;
rc = xc_get_hvm_param(xen_xc, dom, HVM_PARAM_BUFIOREQ_PFN, ¶m);
if (rc < 0) {
fprintf(stderr, "failed to get HVM_PARAM_BUFIOREQ_PFN\n");
return -1;
}
*bufioreq_pfn = param;
rc = xc_get_hvm_param(xen_xc, dom, HVM_PARAM_BUFIOREQ_EVTCHN,
¶m);
if (rc < 0) {
fprintf(stderr, "failed to get HVM_PARAM_BUFIOREQ_EVTCHN\n");
return -1;
}
*bufioreq_evtchn = param;
return 0;
}
/* Xen before 4.5 */
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40500
#ifndef HVM_PARAM_BUFIOREQ_EVTCHN
#define HVM_PARAM_BUFIOREQ_EVTCHN 26
#endif
#define IOREQ_TYPE_PCI_CONFIG 2
typedef uint16_t ioservid_t;
static inline void xen_map_memory_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
static inline void xen_unmap_memory_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
static inline void xen_map_io_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
static inline void xen_unmap_io_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
static inline void xen_map_pcidev(domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
}
static inline void xen_unmap_pcidev(domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
}
static inline void xen_create_ioreq_server(domid_t dom,
ioservid_t *ioservid)
{
}
static inline void xen_destroy_ioreq_server(domid_t dom,
ioservid_t ioservid)
{
}
static inline int xen_get_ioreq_server_info(domid_t dom,
ioservid_t ioservid,
xen_pfn_t *ioreq_pfn,
xen_pfn_t *bufioreq_pfn,
evtchn_port_t *bufioreq_evtchn)
{
return xen_get_default_ioreq_server_info(dom, ioreq_pfn,
bufioreq_pfn,
bufioreq_evtchn);
}
static inline int xen_set_ioreq_server_state(domid_t dom,
ioservid_t ioservid,
bool enable)
{
return 0;
}
/* Xen 4.5 */
#else
static bool use_default_ioreq_server;
static inline void xen_map_memory_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = int128_get64(section->size);
hwaddr end_addr = start_addr + size - 1;
if (use_default_ioreq_server) {
return;
}
trace_xen_map_mmio_range(ioservid, start_addr, end_addr);
xendevicemodel_map_io_range_to_ioreq_server(xen_dmod, dom, ioservid, 1,
start_addr, end_addr);
}
static inline void xen_unmap_memory_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = int128_get64(section->size);
hwaddr end_addr = start_addr + size - 1;
if (use_default_ioreq_server) {
return;
}
trace_xen_unmap_mmio_range(ioservid, start_addr, end_addr);
xendevicemodel_unmap_io_range_from_ioreq_server(xen_dmod, dom, ioservid,
1, start_addr, end_addr);
}
static inline void xen_map_io_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = int128_get64(section->size);
hwaddr end_addr = start_addr + size - 1;
if (use_default_ioreq_server) {
return;
}
trace_xen_map_portio_range(ioservid, start_addr, end_addr);
xendevicemodel_map_io_range_to_ioreq_server(xen_dmod, dom, ioservid, 0,
start_addr, end_addr);
}
static inline void xen_unmap_io_section(domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = int128_get64(section->size);
hwaddr end_addr = start_addr + size - 1;
if (use_default_ioreq_server) {
return;
}
trace_xen_unmap_portio_range(ioservid, start_addr, end_addr);
xendevicemodel_unmap_io_range_from_ioreq_server(xen_dmod, dom, ioservid,
0, start_addr, end_addr);
}
static inline void xen_map_pcidev(domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
if (use_default_ioreq_server) {
return;
}
trace_xen_map_pcidev(ioservid, pci_dev_bus_num(pci_dev),
PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn));
xendevicemodel_map_pcidev_to_ioreq_server(xen_dmod, dom, ioservid, 0,
pci_dev_bus_num(pci_dev),
PCI_SLOT(pci_dev->devfn),
PCI_FUNC(pci_dev->devfn));
}
static inline void xen_unmap_pcidev(domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
if (use_default_ioreq_server) {
return;
}
trace_xen_unmap_pcidev(ioservid, pci_dev_bus_num(pci_dev),
PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn));
xendevicemodel_unmap_pcidev_from_ioreq_server(xen_dmod, dom, ioservid, 0,
pci_dev_bus_num(pci_dev),
PCI_SLOT(pci_dev->devfn),
PCI_FUNC(pci_dev->devfn));
}
static inline void xen_create_ioreq_server(domid_t dom,
ioservid_t *ioservid)
{
int rc = xendevicemodel_create_ioreq_server(xen_dmod, dom,
HVM_IOREQSRV_BUFIOREQ_ATOMIC,
ioservid);
if (rc == 0) {
trace_xen_ioreq_server_create(*ioservid);
return;
}
*ioservid = 0;
use_default_ioreq_server = true;
trace_xen_default_ioreq_server();
}
static inline void xen_destroy_ioreq_server(domid_t dom,
ioservid_t ioservid)
{
if (use_default_ioreq_server) {
return;
}
trace_xen_ioreq_server_destroy(ioservid);
xendevicemodel_destroy_ioreq_server(xen_dmod, dom, ioservid);
}
static inline int xen_get_ioreq_server_info(domid_t dom,
ioservid_t ioservid,
xen_pfn_t *ioreq_pfn,
xen_pfn_t *bufioreq_pfn,
evtchn_port_t *bufioreq_evtchn)
{
if (use_default_ioreq_server) {
return xen_get_default_ioreq_server_info(dom, ioreq_pfn,
bufioreq_pfn,
bufioreq_evtchn);
}
return xendevicemodel_get_ioreq_server_info(xen_dmod, dom, ioservid,
ioreq_pfn, bufioreq_pfn,
bufioreq_evtchn);
}
static inline int xen_set_ioreq_server_state(domid_t dom,
ioservid_t ioservid,
bool enable)
{
if (use_default_ioreq_server) {
return 0;
}
trace_xen_ioreq_server_state(ioservid, enable);
return xendevicemodel_set_ioreq_server_state(xen_dmod, dom, ioservid,
enable);
}
#endif
/* Xen before 4.8 */
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40800
struct xengnttab_grant_copy_segment {
union xengnttab_copy_ptr {
void *virt;
struct {
uint32_t ref;
uint16_t offset;
uint16_t domid;
} foreign;
} source, dest;
uint16_t len;
uint16_t flags;
int16_t status;
};
typedef struct xengnttab_grant_copy_segment xengnttab_grant_copy_segment_t;
static inline int xengnttab_grant_copy(xengnttab_handle *xgt, uint32_t count,
xengnttab_grant_copy_segment_t *segs)
{
return -ENOSYS;
}
#endif
#endif /* QEMU_HW_XEN_COMMON_H */
|
pmp-tool/PMP | src/qemu/src-pmp/hw/hppa/dino.c | <reponame>pmp-tool/PMP
/*
* HP-PARISC Dino PCI chipset emulation.
*
* (C) 2017 by <NAME> <<EMAIL>>
*
* This work is licensed under the GNU GPL license version 2 or later.
*
* Documentation available at:
* https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
* https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/hw.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hppa_sys.h"
#include "exec/address-spaces.h"
#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
#define DINO_IAR0 0x004
#define DINO_IODC 0x008
#define DINO_IRR0 0x00C /* RO */
#define DINO_IAR1 0x010
#define DINO_IRR1 0x014 /* RO */
#define DINO_IMR 0x018
#define DINO_IPR 0x01C
#define DINO_TOC_ADDR 0x020
#define DINO_ICR 0x024
#define DINO_ILR 0x028 /* RO */
#define DINO_IO_COMMAND 0x030 /* WO */
#define DINO_IO_STATUS 0x034 /* RO */
#define DINO_IO_CONTROL 0x038
#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */
#define DINO_IO_ERR_INFO 0x044 /* RO */
#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */
#define DINO_IO_FBB_EN 0x05c
#define DINO_IO_ADDR_EN 0x060
#define DINO_PCI_CONFIG_ADDR 0x064
#define DINO_PCI_CONFIG_DATA 0x068
#define DINO_PCI_IO_DATA 0x06c
#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */
#define DINO_GSC2X_CONFIG 0x7b4 /* RO */
#define DINO_GMASK 0x800
#define DINO_PAMR 0x804
#define DINO_PAPR 0x808
#define DINO_DAMODE 0x80c
#define DINO_PCICMD 0x810
#define DINO_PCISTS 0x814 /* R/WC */
#define DINO_MLTIM 0x81c
#define DINO_BRDG_FEAT 0x820
#define DINO_PCIROR 0x824
#define DINO_PCIWOR 0x828
#define DINO_TLTIM 0x830
#define DINO_IRQS 11 /* bits 0-10 are architected */
#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
#define DINO_LOCAL_IRQS (DINO_IRQS + 1)
#define DINO_MASK_IRQ(x) (1 << (x))
#define PCIINTA 0x001
#define PCIINTB 0x002
#define PCIINTC 0x004
#define PCIINTD 0x008
#define PCIINTE 0x010
#define PCIINTF 0x020
#define GSCEXTINT 0x040
/* #define xxx 0x080 - bit 7 is "default" */
/* #define xxx 0x100 - bit 8 not used */
/* #define xxx 0x200 - bit 9 not used */
#define RS232INT 0x400
#define DINO_MEM_CHUNK_SIZE (8 * MiB)
#define DINO_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
typedef struct DinoState {
PCIHostState parent_obj;
/* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */
uint32_t iar0;
uint32_t iar1;
uint32_t imr;
uint32_t ipr;
uint32_t icr;
uint32_t ilr;
uint32_t io_addr_en;
uint32_t io_control;
MemoryRegion this_mem;
MemoryRegion pci_mem;
MemoryRegion pci_mem_alias[32];
AddressSpace bm_as;
MemoryRegion bm;
MemoryRegion bm_ram_alias;
MemoryRegion bm_pci_alias;
MemoryRegion bm_cpu_alias;
MemoryRegion cpu0_eir_mem;
} DinoState;
/*
* Dino can forward memory accesses from the CPU in the range between
* 0xf0800000 and 0xff000000 to the PCI bus.
*/
static void gsc_to_pci_forwarding(DinoState *s)
{
uint32_t io_addr_en, tmp;
int enabled, i;
tmp = extract32(s->io_control, 7, 2);
enabled = (tmp == 0x01);
io_addr_en = s->io_addr_en;
memory_region_transaction_begin();
for (i = 1; i < 31; i++) {
MemoryRegion *mem = &s->pci_mem_alias[i];
if (enabled && (io_addr_en & (1U << i))) {
if (!memory_region_is_mapped(mem)) {
uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
memory_region_add_subregion(get_system_memory(), addr, mem);
}
} else if (memory_region_is_mapped(mem)) {
memory_region_del_subregion(get_system_memory(), mem);
}
}
memory_region_transaction_commit();
}
static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write,
MemTxAttrs attrs)
{
switch (addr) {
case DINO_IAR0:
case DINO_IAR1:
case DINO_IRR0:
case DINO_IRR1:
case DINO_IMR:
case DINO_IPR:
case DINO_ICR:
case DINO_ILR:
case DINO_IO_CONTROL:
case DINO_IO_ADDR_EN:
case DINO_PCI_IO_DATA:
return true;
case DINO_PCI_IO_DATA + 2:
return size <= 2;
case DINO_PCI_IO_DATA + 1:
case DINO_PCI_IO_DATA + 3:
return size == 1;
}
return false;
}
static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
uint64_t *data, unsigned size,
MemTxAttrs attrs)
{
DinoState *s = opaque;
MemTxResult ret = MEMTX_OK;
AddressSpace *io;
uint16_t ioaddr;
uint32_t val;
switch (addr) {
case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
/* Read from PCI IO space. */
io = &address_space_io;
ioaddr = s->parent_obj.config_reg + (addr & 3);
switch (size) {
case 1:
val = address_space_ldub(io, ioaddr, attrs, &ret);
break;
case 2:
val = address_space_lduw_be(io, ioaddr, attrs, &ret);
break;
case 4:
val = address_space_ldl_be(io, ioaddr, attrs, &ret);
break;
default:
g_assert_not_reached();
}
break;
case DINO_IO_ADDR_EN:
val = s->io_addr_en;
break;
case DINO_IO_CONTROL:
val = s->io_control;
break;
case DINO_IAR0:
val = s->iar0;
break;
case DINO_IAR1:
val = s->iar1;
break;
case DINO_IMR:
val = s->imr;
break;
case DINO_ICR:
val = s->icr;
break;
case DINO_IPR:
val = s->ipr;
/* Any read to IPR clears the register. */
s->ipr = 0;
break;
case DINO_ILR:
val = s->ilr;
break;
case DINO_IRR0:
val = s->ilr & s->imr & ~s->icr;
break;
case DINO_IRR1:
val = s->ilr & s->imr & s->icr;
break;
default:
/* Controlled by dino_chip_mem_valid above. */
g_assert_not_reached();
}
*data = val;
return ret;
}
static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
DinoState *s = opaque;
AddressSpace *io;
MemTxResult ret;
uint16_t ioaddr;
switch (addr) {
case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
/* Write into PCI IO space. */
io = &address_space_io;
ioaddr = s->parent_obj.config_reg + (addr & 3);
switch (size) {
case 1:
address_space_stb(io, ioaddr, val, attrs, &ret);
break;
case 2:
address_space_stw_be(io, ioaddr, val, attrs, &ret);
break;
case 4:
address_space_stl_be(io, ioaddr, val, attrs, &ret);
break;
default:
g_assert_not_reached();
}
return ret;
case DINO_IO_ADDR_EN:
/* Never allow first (=firmware) and last (=Dino) areas. */
s->io_addr_en = val & 0x7ffffffe;
gsc_to_pci_forwarding(s);
break;
case DINO_IO_CONTROL:
s->io_control = val;
gsc_to_pci_forwarding(s);
break;
case DINO_IAR0:
s->iar0 = val;
break;
case DINO_IAR1:
s->iar1 = val;
break;
case DINO_IMR:
s->imr = val;
break;
case DINO_ICR:
s->icr = val;
break;
case DINO_IPR:
/* Any write to IPR clears the register. */
s->ipr = 0;
break;
case DINO_ILR:
case DINO_IRR0:
case DINO_IRR1:
/* These registers are read-only. */
break;
default:
/* Controlled by dino_chip_mem_valid above. */
g_assert_not_reached();
}
return MEMTX_OK;
}
static const MemoryRegionOps dino_chip_ops = {
.read_with_attrs = dino_chip_read_with_attrs,
.write_with_attrs = dino_chip_write_with_attrs,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4,
.accepts = dino_chip_mem_valid,
},
.impl = {
.min_access_size = 1,
.max_access_size = 4,
},
};
static const VMStateDescription vmstate_dino = {
.name = "Dino",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(iar0, DinoState),
VMSTATE_UINT32(iar1, DinoState),
VMSTATE_UINT32(imr, DinoState),
VMSTATE_UINT32(ipr, DinoState),
VMSTATE_UINT32(icr, DinoState),
VMSTATE_UINT32(ilr, DinoState),
VMSTATE_UINT32(io_addr_en, DinoState),
VMSTATE_UINT32(io_control, DinoState),
VMSTATE_END_OF_LIST()
}
};
/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */
static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
{
PCIHostState *s = opaque;
return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
}
static void dino_config_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
static const MemoryRegionOps dino_config_data_ops = {
.read = dino_config_data_read,
.write = dino_config_data_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
{
PCIHostState *s = opaque;
return s->config_reg;
}
static void dino_config_addr_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
s->config_reg = val & ~3U;
}
static const MemoryRegionOps dino_config_addr_ops = {
.read = dino_config_addr_read,
.write = dino_config_addr_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.endianness = DEVICE_BIG_ENDIAN,
};
static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
int devfn)
{
DinoState *s = opaque;
return &s->bm_as;
}
/*
* Dino interrupts are connected as shown on Page 78, Table 23
* (Little-endian bit numbers)
* 0 PCI INTA
* 1 PCI INTB
* 2 PCI INTC
* 3 PCI INTD
* 4 PCI INTE
* 5 PCI INTF
* 6 GSC External Interrupt
* 7 Bus Error for "less than fatal" mode
* 8 PS2
* 9 Unused
* 10 RS232
*/
static void dino_set_irq(void *opaque, int irq, int level)
{
DinoState *s = opaque;
uint32_t bit = 1u << irq;
uint32_t old_ilr = s->ilr;
if (level) {
uint32_t ena = bit & ~old_ilr;
s->ipr |= ena;
s->ilr = old_ilr | bit;
if (ena & s->imr) {
uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
stl_be_phys(&address_space_memory, iar & -32, iar & 31);
}
} else {
s->ilr = old_ilr & ~bit;
}
}
static int dino_pci_map_irq(PCIDevice *d, int irq_num)
{
int slot = d->devfn >> 3;
assert(irq_num >= 0 && irq_num <= 3);
return slot & 0x03;
}
static void dino_set_timer_irq(void *opaque, int irq, int level)
{
/* ??? Not connected. */
}
static void dino_set_serial_irq(void *opaque, int irq, int level)
{
dino_set_irq(opaque, 10, level);
}
PCIBus *dino_init(MemoryRegion *addr_space,
qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
{
DeviceState *dev;
DinoState *s;
PCIBus *b;
int i;
dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
s = DINO_PCI_HOST_BRIDGE(dev);
/* Dino PCI access from main memory. */
memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
s, "dino", 4096);
memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
/* Dino PCI config. */
memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
&dino_config_addr_ops, dev, "pci-conf-idx", 4);
memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
&dino_config_data_ops, dev, "pci-conf-data", 4);
memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
&s->parent_obj.conf_mem);
memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
&s->parent_obj.data_mem);
/* Dino PCI bus memory. */
memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);
b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
&s->pci_mem, get_system_io(),
PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
s->parent_obj.bus = b;
qdev_init_nofail(dev);
/* Set up windows into PCI bus memory. */
for (i = 1; i < 31; i++) {
uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
char *name = g_strdup_printf("PCI Outbound Window %d", i);
memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
name, &s->pci_mem, addr,
DINO_MEM_CHUNK_SIZE);
}
/* Set up PCI view of memory: Bus master address space. */
memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
"bm-system", addr_space, 0,
0xf0000000 + DINO_MEM_CHUNK_SIZE);
memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
"bm-pci", &s->pci_mem,
0xf0000000 + DINO_MEM_CHUNK_SIZE,
30 * DINO_MEM_CHUNK_SIZE);
memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
"bm-cpu", addr_space, 0xfff00000,
0xfffff);
memory_region_add_subregion(&s->bm, 0,
&s->bm_ram_alias);
memory_region_add_subregion(&s->bm,
0xf0000000 + DINO_MEM_CHUNK_SIZE,
&s->bm_pci_alias);
memory_region_add_subregion(&s->bm, 0xfff00000,
&s->bm_cpu_alias);
address_space_init(&s->bm_as, &s->bm, "pci-bm");
pci_setup_iommu(b, dino_pcihost_set_iommu, s);
*p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
*p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
return b;
}
static void dino_pcihost_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_dino;
}
static const TypeInfo dino_pcihost_info = {
.name = TYPE_DINO_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(DinoState),
.class_init = dino_pcihost_class_init,
};
static void dino_register_types(void)
{
type_register_static(&dino_pcihost_info);
}
type_init(dino_register_types)
|
pmp-tool/PMP | src/qemu/src-pmp/tests/tcg/mips/user/isa/mips64r6/bit-count/test_mips64r6_clo.c | <reponame>pmp-tool/PMP
/*
* Test program for MIPS64R6 instruction CLO
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 <NAME> <<EMAIL>>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *instruction_name = "CLO";
int32_t ret;
uint32_t i;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x0000000000000020ULL, /* 0 */
0x0000000000000000ULL,
0x0000000000000001ULL,
0x0000000000000000ULL,
0x0000000000000002ULL,
0x0000000000000000ULL,
0x0000000000000003ULL,
0x0000000000000000ULL,
0x0000000000000004ULL, /* 8 */
0x0000000000000000ULL,
0x0000000000000005ULL,
0x0000000000000000ULL,
0x0000000000000006ULL,
0x0000000000000000ULL,
0x0000000000000007ULL,
0x0000000000000000ULL,
0x0000000000000008ULL, /* 16 */
0x0000000000000000ULL,
0x0000000000000009ULL,
0x0000000000000000ULL,
0x000000000000000aULL,
0x0000000000000000ULL,
0x000000000000000bULL,
0x0000000000000000ULL,
0x000000000000000cULL, /* 24 */
0x0000000000000000ULL,
0x000000000000000dULL,
0x0000000000000000ULL,
0x000000000000000eULL,
0x0000000000000000ULL,
0x000000000000000fULL,
0x0000000000000000ULL,
0x0000000000000010ULL, /* 32 */
0x0000000000000000ULL,
0x0000000000000011ULL,
0x0000000000000000ULL,
0x0000000000000012ULL,
0x0000000000000000ULL,
0x0000000000000013ULL,
0x0000000000000000ULL,
0x0000000000000014ULL, /* 40 */
0x0000000000000000ULL,
0x0000000000000015ULL,
0x0000000000000000ULL,
0x0000000000000016ULL,
0x0000000000000000ULL,
0x0000000000000017ULL,
0x0000000000000000ULL,
0x0000000000000018ULL, /* 48 */
0x0000000000000000ULL,
0x0000000000000019ULL,
0x0000000000000000ULL,
0x000000000000001aULL,
0x0000000000000000ULL,
0x000000000000001bULL,
0x0000000000000000ULL,
0x000000000000001cULL, /* 56 */
0x0000000000000000ULL,
0x000000000000001dULL,
0x0000000000000000ULL,
0x000000000000001eULL,
0x0000000000000000ULL,
0x000000000000001fULL,
0x0000000000000000ULL,
0x0000000000000001ULL, /* 64 */
0x0000000000000005ULL,
0x0000000000000001ULL,
0x0000000000000000ULL,
0x0000000000000001ULL,
0x0000000000000002ULL,
0x0000000000000001ULL,
0x0000000000000006ULL,
0x0000000000000000ULL, /* 72 */
0x0000000000000001ULL,
0x0000000000000001ULL,
0x0000000000000001ULL,
0x0000000000000003ULL,
0x0000000000000001ULL,
0x0000000000000000ULL,
0x0000000000000001ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < TEST_COUNT_TOTAL; i++) {
if (i < PATTERN_INPUTS_64_COUNT) {
do_mips64r6_CLO(b64_pattern_se + i, b64_result + i);
} else {
do_mips64r6_CLO(b64_random_se + (i - PATTERN_INPUTS_64_COUNT),
b64_result + i);
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(instruction_name, TEST_COUNT_TOTAL, elapsed_time,
b64_result, b64_expect);
return ret;
}
|
pmp-tool/PMP | src/qemu/src-pmp/hw/display/virtio-gpu.c | /*
* Virtio GPU Device
*
* Copyright Red Hat, Inc. 2013-2014
*
* Authors:
* <NAME> <<EMAIL>>
* <NAME> <<EMAIL>>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "qemu/iov.h"
#include "ui/console.h"
#include "trace.h"
#include "sysemu/dma.h"
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-gpu.h"
#include "hw/virtio/virtio-bus.h"
#include "hw/display/edid.h"
#include "migration/blocker.h"
#include "qemu/log.h"
#include "qapi/error.h"
#define VIRTIO_GPU_VM_VERSION 1
static struct virtio_gpu_simple_resource*
virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id);
static void virtio_gpu_cleanup_mapping(VirtIOGPU *g,
struct virtio_gpu_simple_resource *res);
static void
virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr)
{
le32_to_cpus(&hdr->type);
le32_to_cpus(&hdr->flags);
le64_to_cpus(&hdr->fence_id);
le32_to_cpus(&hdr->ctx_id);
le32_to_cpus(&hdr->padding);
}
static void virtio_gpu_bswap_32(void *ptr,
size_t size)
{
#ifdef HOST_WORDS_BIGENDIAN
size_t i;
struct virtio_gpu_ctrl_hdr *hdr = (struct virtio_gpu_ctrl_hdr *) ptr;
virtio_gpu_ctrl_hdr_bswap(hdr);
i = sizeof(struct virtio_gpu_ctrl_hdr);
while (i < size) {
le32_to_cpus((uint32_t *)(ptr + i));
i = i + sizeof(uint32_t);
}
#endif
}
static void
virtio_gpu_t2d_bswap(struct virtio_gpu_transfer_to_host_2d *t2d)
{
virtio_gpu_ctrl_hdr_bswap(&t2d->hdr);
le32_to_cpus(&t2d->r.x);
le32_to_cpus(&t2d->r.y);
le32_to_cpus(&t2d->r.width);
le32_to_cpus(&t2d->r.height);
le64_to_cpus(&t2d->offset);
le32_to_cpus(&t2d->resource_id);
le32_to_cpus(&t2d->padding);
}
#ifdef CONFIG_VIRGL
#include <virglrenderer.h>
#define VIRGL(_g, _virgl, _simple, ...) \
do { \
if (_g->use_virgl_renderer) { \
_virgl(__VA_ARGS__); \
} else { \
_simple(__VA_ARGS__); \
} \
} while (0)
#else
#define VIRGL(_g, _virgl, _simple, ...) \
do { \
_simple(__VA_ARGS__); \
} while (0)
#endif
static void update_cursor_data_simple(VirtIOGPU *g,
struct virtio_gpu_scanout *s,
uint32_t resource_id)
{
struct virtio_gpu_simple_resource *res;
uint32_t pixels;
res = virtio_gpu_find_resource(g, resource_id);
if (!res) {
return;
}
if (pixman_image_get_width(res->image) != s->current_cursor->width ||
pixman_image_get_height(res->image) != s->current_cursor->height) {
return;
}
pixels = s->current_cursor->width * s->current_cursor->height;
memcpy(s->current_cursor->data,
pixman_image_get_data(res->image),
pixels * sizeof(uint32_t));
}
#ifdef CONFIG_VIRGL
static void update_cursor_data_virgl(VirtIOGPU *g,
struct virtio_gpu_scanout *s,
uint32_t resource_id)
{
uint32_t width, height;
uint32_t pixels, *data;
data = virgl_renderer_get_cursor_data(resource_id, &width, &height);
if (!data) {
return;
}
if (width != s->current_cursor->width ||
height != s->current_cursor->height) {
free(data);
return;
}
pixels = s->current_cursor->width * s->current_cursor->height;
memcpy(s->current_cursor->data, data, pixels * sizeof(uint32_t));
free(data);
}
#endif
static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
{
struct virtio_gpu_scanout *s;
bool move = cursor->hdr.type == VIRTIO_GPU_CMD_MOVE_CURSOR;
if (cursor->pos.scanout_id >= g->conf.max_outputs) {
return;
}
s = &g->scanout[cursor->pos.scanout_id];
trace_virtio_gpu_update_cursor(cursor->pos.scanout_id,
cursor->pos.x,
cursor->pos.y,
move ? "move" : "update",
cursor->resource_id);
if (!move) {
if (!s->current_cursor) {
s->current_cursor = cursor_alloc(64, 64);
}
s->current_cursor->hot_x = cursor->hot_x;
s->current_cursor->hot_y = cursor->hot_y;
if (cursor->resource_id > 0) {
VIRGL(g, update_cursor_data_virgl, update_cursor_data_simple,
g, s, cursor->resource_id);
}
dpy_cursor_define(s->con, s->current_cursor);
s->cursor = *cursor;
} else {
s->cursor.pos.x = cursor->pos.x;
s->cursor.pos.y = cursor->pos.y;
}
dpy_mouse_set(s->con, cursor->pos.x, cursor->pos.y,
cursor->resource_id ? 1 : 0);
}
static void virtio_gpu_get_config(VirtIODevice *vdev, uint8_t *config)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
memcpy(config, &g->virtio_config, sizeof(g->virtio_config));
}
static void virtio_gpu_set_config(VirtIODevice *vdev, const uint8_t *config)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
struct virtio_gpu_config vgconfig;
memcpy(&vgconfig, config, sizeof(g->virtio_config));
if (vgconfig.events_clear) {
g->virtio_config.events_read &= ~vgconfig.events_clear;
}
}
static uint64_t virtio_gpu_get_features(VirtIODevice *vdev, uint64_t features,
Error **errp)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
if (virtio_gpu_virgl_enabled(g->conf)) {
features |= (1 << VIRTIO_GPU_F_VIRGL);
}
if (virtio_gpu_edid_enabled(g->conf)) {
features |= (1 << VIRTIO_GPU_F_EDID);
}
return features;
}
static void virtio_gpu_set_features(VirtIODevice *vdev, uint64_t features)
{
static const uint32_t virgl = (1 << VIRTIO_GPU_F_VIRGL);
VirtIOGPU *g = VIRTIO_GPU(vdev);
g->use_virgl_renderer = ((features & virgl) == virgl);
trace_virtio_gpu_features(g->use_virgl_renderer);
}
static void virtio_gpu_notify_event(VirtIOGPU *g, uint32_t event_type)
{
g->virtio_config.events_read |= event_type;
virtio_notify_config(&g->parent_obj);
}
static struct virtio_gpu_simple_resource *
virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id)
{
struct virtio_gpu_simple_resource *res;
QTAILQ_FOREACH(res, &g->reslist, next) {
if (res->resource_id == resource_id) {
return res;
}
}
return NULL;
}
void virtio_gpu_ctrl_response(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd,
struct virtio_gpu_ctrl_hdr *resp,
size_t resp_len)
{
size_t s;
if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE) {
resp->flags |= VIRTIO_GPU_FLAG_FENCE;
resp->fence_id = cmd->cmd_hdr.fence_id;
resp->ctx_id = cmd->cmd_hdr.ctx_id;
}
virtio_gpu_ctrl_hdr_bswap(resp);
s = iov_from_buf(cmd->elem.in_sg, cmd->elem.in_num, 0, resp, resp_len);
if (s != resp_len) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: response size incorrect %zu vs %zu\n",
__func__, s, resp_len);
}
virtqueue_push(cmd->vq, &cmd->elem, s);
virtio_notify(VIRTIO_DEVICE(g), cmd->vq);
cmd->finished = true;
}
void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd,
enum virtio_gpu_ctrl_type type)
{
struct virtio_gpu_ctrl_hdr resp;
memset(&resp, 0, sizeof(resp));
resp.type = type;
virtio_gpu_ctrl_response(g, cmd, &resp, sizeof(resp));
}
static void
virtio_gpu_fill_display_info(VirtIOGPU *g,
struct virtio_gpu_resp_display_info *dpy_info)
{
int i;
for (i = 0; i < g->conf.max_outputs; i++) {
if (g->enabled_output_bitmask & (1 << i)) {
dpy_info->pmodes[i].enabled = 1;
dpy_info->pmodes[i].r.width = cpu_to_le32(g->req_state[i].width);
dpy_info->pmodes[i].r.height = cpu_to_le32(g->req_state[i].height);
}
}
}
void virtio_gpu_get_display_info(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_resp_display_info display_info;
trace_virtio_gpu_cmd_get_display_info();
memset(&display_info, 0, sizeof(display_info));
display_info.hdr.type = VIRTIO_GPU_RESP_OK_DISPLAY_INFO;
virtio_gpu_fill_display_info(g, &display_info);
virtio_gpu_ctrl_response(g, cmd, &display_info.hdr,
sizeof(display_info));
}
static void
virtio_gpu_generate_edid(VirtIOGPU *g, int scanout,
struct virtio_gpu_resp_edid *edid)
{
qemu_edid_info info = {
.prefx = g->req_state[scanout].width,
.prefy = g->req_state[scanout].height,
};
edid->size = cpu_to_le32(sizeof(edid->edid));
qemu_edid_generate(edid->edid, sizeof(edid->edid), &info);
}
void virtio_gpu_get_edid(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_resp_edid edid;
struct virtio_gpu_cmd_get_edid get_edid;
VIRTIO_GPU_FILL_CMD(get_edid);
virtio_gpu_bswap_32(&get_edid, sizeof(get_edid));
if (get_edid.scanout >= g->conf.max_outputs) {
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
return;
}
trace_virtio_gpu_cmd_get_edid(get_edid.scanout);
memset(&edid, 0, sizeof(edid));
edid.hdr.type = VIRTIO_GPU_RESP_OK_EDID;
virtio_gpu_generate_edid(g, get_edid.scanout, &edid);
virtio_gpu_ctrl_response(g, cmd, &edid.hdr, sizeof(edid));
}
static pixman_format_code_t get_pixman_format(uint32_t virtio_gpu_format)
{
switch (virtio_gpu_format) {
case VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM:
return PIXMAN_BE_b8g8r8x8;
case VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM:
return PIXMAN_BE_b8g8r8a8;
case VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM:
return PIXMAN_BE_x8r8g8b8;
case VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM:
return PIXMAN_BE_a8r8g8b8;
case VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM:
return PIXMAN_BE_r8g8b8x8;
case VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM:
return PIXMAN_BE_r8g8b8a8;
case VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM:
return PIXMAN_BE_x8b8g8r8;
case VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM:
return PIXMAN_BE_a8b8g8r8;
default:
return 0;
}
}
static uint32_t calc_image_hostmem(pixman_format_code_t pformat,
uint32_t width, uint32_t height)
{
/* Copied from pixman/pixman-bits-image.c, skip integer overflow check.
* pixman_image_create_bits will fail in case it overflow.
*/
int bpp = PIXMAN_FORMAT_BPP(pformat);
int stride = ((width * bpp + 0x1f) >> 5) * sizeof(uint32_t);
return height * stride;
}
static void virtio_gpu_resource_create_2d(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
pixman_format_code_t pformat;
struct virtio_gpu_simple_resource *res;
struct virtio_gpu_resource_create_2d c2d;
VIRTIO_GPU_FILL_CMD(c2d);
virtio_gpu_bswap_32(&c2d, sizeof(c2d));
trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
c2d.width, c2d.height);
if (c2d.resource_id == 0) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n",
__func__);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
res = virtio_gpu_find_resource(g, c2d.resource_id);
if (res) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already exists %d\n",
__func__, c2d.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
res = g_new0(struct virtio_gpu_simple_resource, 1);
res->width = c2d.width;
res->height = c2d.height;
res->format = c2d.format;
res->resource_id = c2d.resource_id;
pformat = get_pixman_format(c2d.format);
if (!pformat) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: host couldn't handle guest format %d\n",
__func__, c2d.format);
g_free(res);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
return;
}
res->hostmem = calc_image_hostmem(pformat, c2d.width, c2d.height);
if (res->hostmem + g->hostmem < g->conf.max_hostmem) {
res->image = pixman_image_create_bits(pformat,
c2d.width,
c2d.height,
NULL, 0);
}
if (!res->image) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: resource creation failed %d %d %d\n",
__func__, c2d.resource_id, c2d.width, c2d.height);
g_free(res);
cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY;
return;
}
QTAILQ_INSERT_HEAD(&g->reslist, res, next);
g->hostmem += res->hostmem;
}
static void virtio_gpu_disable_scanout(VirtIOGPU *g, int scanout_id)
{
struct virtio_gpu_scanout *scanout = &g->scanout[scanout_id];
struct virtio_gpu_simple_resource *res;
DisplaySurface *ds = NULL;
if (scanout->resource_id == 0) {
return;
}
res = virtio_gpu_find_resource(g, scanout->resource_id);
if (res) {
res->scanout_bitmask &= ~(1 << scanout_id);
}
if (scanout_id == 0) {
/* primary head */
ds = qemu_create_message_surface(scanout->width ?: 640,
scanout->height ?: 480,
"Guest disabled display.");
}
dpy_gfx_replace_surface(scanout->con, ds);
scanout->resource_id = 0;
scanout->ds = NULL;
scanout->width = 0;
scanout->height = 0;
}
static void virtio_gpu_resource_destroy(VirtIOGPU *g,
struct virtio_gpu_simple_resource *res)
{
int i;
if (res->scanout_bitmask) {
for (i = 0; i < g->conf.max_outputs; i++) {
if (res->scanout_bitmask & (1 << i)) {
virtio_gpu_disable_scanout(g, i);
}
}
}
pixman_image_unref(res->image);
virtio_gpu_cleanup_mapping(g, res);
QTAILQ_REMOVE(&g->reslist, res, next);
g->hostmem -= res->hostmem;
g_free(res);
}
static void virtio_gpu_resource_unref(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_simple_resource *res;
struct virtio_gpu_resource_unref unref;
VIRTIO_GPU_FILL_CMD(unref);
virtio_gpu_bswap_32(&unref, sizeof(unref));
trace_virtio_gpu_cmd_res_unref(unref.resource_id);
res = virtio_gpu_find_resource(g, unref.resource_id);
if (!res) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
__func__, unref.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
virtio_gpu_resource_destroy(g, res);
}
static void virtio_gpu_transfer_to_host_2d(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_simple_resource *res;
int h;
uint32_t src_offset, dst_offset, stride;
int bpp;
pixman_format_code_t format;
struct virtio_gpu_transfer_to_host_2d t2d;
VIRTIO_GPU_FILL_CMD(t2d);
virtio_gpu_t2d_bswap(&t2d);
trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
res = virtio_gpu_find_resource(g, t2d.resource_id);
if (!res || !res->iov) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
__func__, t2d.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
if (t2d.r.x > res->width ||
t2d.r.y > res->height ||
t2d.r.width > res->width ||
t2d.r.height > res->height ||
t2d.r.x + t2d.r.width > res->width ||
t2d.r.y + t2d.r.height > res->height) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: transfer bounds outside resource"
" bounds for resource %d: %d %d %d %d vs %d %d\n",
__func__, t2d.resource_id, t2d.r.x, t2d.r.y,
t2d.r.width, t2d.r.height, res->width, res->height);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
return;
}
format = pixman_image_get_format(res->image);
bpp = DIV_ROUND_UP(PIXMAN_FORMAT_BPP(format), 8);
stride = pixman_image_get_stride(res->image);
if (t2d.offset || t2d.r.x || t2d.r.y ||
t2d.r.width != pixman_image_get_width(res->image)) {
void *img_data = pixman_image_get_data(res->image);
for (h = 0; h < t2d.r.height; h++) {
src_offset = t2d.offset + stride * h;
dst_offset = (t2d.r.y + h) * stride + (t2d.r.x * bpp);
iov_to_buf(res->iov, res->iov_cnt, src_offset,
(uint8_t *)img_data
+ dst_offset, t2d.r.width * bpp);
}
} else {
iov_to_buf(res->iov, res->iov_cnt, 0,
pixman_image_get_data(res->image),
pixman_image_get_stride(res->image)
* pixman_image_get_height(res->image));
}
}
static void virtio_gpu_resource_flush(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_simple_resource *res;
struct virtio_gpu_resource_flush rf;
pixman_region16_t flush_region;
int i;
VIRTIO_GPU_FILL_CMD(rf);
virtio_gpu_bswap_32(&rf, sizeof(rf));
trace_virtio_gpu_cmd_res_flush(rf.resource_id,
rf.r.width, rf.r.height, rf.r.x, rf.r.y);
res = virtio_gpu_find_resource(g, rf.resource_id);
if (!res) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
__func__, rf.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
if (rf.r.x > res->width ||
rf.r.y > res->height ||
rf.r.width > res->width ||
rf.r.height > res->height ||
rf.r.x + rf.r.width > res->width ||
rf.r.y + rf.r.height > res->height) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: flush bounds outside resource"
" bounds for resource %d: %d %d %d %d vs %d %d\n",
__func__, rf.resource_id, rf.r.x, rf.r.y,
rf.r.width, rf.r.height, res->width, res->height);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
return;
}
pixman_region_init_rect(&flush_region,
rf.r.x, rf.r.y, rf.r.width, rf.r.height);
for (i = 0; i < g->conf.max_outputs; i++) {
struct virtio_gpu_scanout *scanout;
pixman_region16_t region, finalregion;
pixman_box16_t *extents;
if (!(res->scanout_bitmask & (1 << i))) {
continue;
}
scanout = &g->scanout[i];
pixman_region_init(&finalregion);
pixman_region_init_rect(®ion, scanout->x, scanout->y,
scanout->width, scanout->height);
pixman_region_intersect(&finalregion, &flush_region, ®ion);
pixman_region_translate(&finalregion, -scanout->x, -scanout->y);
extents = pixman_region_extents(&finalregion);
/* work out the area we need to update for each console */
dpy_gfx_update(g->scanout[i].con,
extents->x1, extents->y1,
extents->x2 - extents->x1,
extents->y2 - extents->y1);
pixman_region_fini(®ion);
pixman_region_fini(&finalregion);
}
pixman_region_fini(&flush_region);
}
static void virtio_unref_resource(pixman_image_t *image, void *data)
{
pixman_image_unref(data);
}
static void virtio_gpu_set_scanout(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_simple_resource *res, *ores;
struct virtio_gpu_scanout *scanout;
pixman_format_code_t format;
uint32_t offset;
int bpp;
struct virtio_gpu_set_scanout ss;
VIRTIO_GPU_FILL_CMD(ss);
virtio_gpu_bswap_32(&ss, sizeof(ss));
trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
ss.r.width, ss.r.height, ss.r.x, ss.r.y);
if (ss.scanout_id >= g->conf.max_outputs) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
__func__, ss.scanout_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
return;
}
g->enable = 1;
if (ss.resource_id == 0) {
virtio_gpu_disable_scanout(g, ss.scanout_id);
return;
}
/* create a surface for this scanout */
res = virtio_gpu_find_resource(g, ss.resource_id);
if (!res) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
__func__, ss.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
if (ss.r.x > res->width ||
ss.r.y > res->height ||
ss.r.width > res->width ||
ss.r.height > res->height ||
ss.r.x + ss.r.width > res->width ||
ss.r.y + ss.r.height > res->height) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout %d bounds for"
" resource %d, (%d,%d)+%d,%d vs %d %d\n",
__func__, ss.scanout_id, ss.resource_id, ss.r.x, ss.r.y,
ss.r.width, ss.r.height, res->width, res->height);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
return;
}
scanout = &g->scanout[ss.scanout_id];
format = pixman_image_get_format(res->image);
bpp = DIV_ROUND_UP(PIXMAN_FORMAT_BPP(format), 8);
offset = (ss.r.x * bpp) + ss.r.y * pixman_image_get_stride(res->image);
if (!scanout->ds || surface_data(scanout->ds)
!= ((uint8_t *)pixman_image_get_data(res->image) + offset) ||
scanout->width != ss.r.width ||
scanout->height != ss.r.height) {
pixman_image_t *rect;
void *ptr = (uint8_t *)pixman_image_get_data(res->image) + offset;
rect = pixman_image_create_bits(format, ss.r.width, ss.r.height, ptr,
pixman_image_get_stride(res->image));
pixman_image_ref(res->image);
pixman_image_set_destroy_function(rect, virtio_unref_resource,
res->image);
/* realloc the surface ptr */
scanout->ds = qemu_create_displaysurface_pixman(rect);
if (!scanout->ds) {
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
}
pixman_image_unref(rect);
dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, scanout->ds);
}
ores = virtio_gpu_find_resource(g, scanout->resource_id);
if (ores) {
ores->scanout_bitmask &= ~(1 << ss.scanout_id);
}
res->scanout_bitmask |= (1 << ss.scanout_id);
scanout->resource_id = ss.resource_id;
scanout->x = ss.r.x;
scanout->y = ss.r.y;
scanout->width = ss.r.width;
scanout->height = ss.r.height;
}
int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
struct virtio_gpu_resource_attach_backing *ab,
struct virtio_gpu_ctrl_command *cmd,
uint64_t **addr, struct iovec **iov)
{
struct virtio_gpu_mem_entry *ents;
size_t esize, s;
int i;
if (ab->nr_entries > 16384) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: nr_entries is too big (%d > 16384)\n",
__func__, ab->nr_entries);
return -1;
}
esize = sizeof(*ents) * ab->nr_entries;
ents = g_malloc(esize);
s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
sizeof(*ab), ents, esize);
if (s != esize) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: command data size incorrect %zu vs %zu\n",
__func__, s, esize);
g_free(ents);
return -1;
}
*iov = g_malloc0(sizeof(struct iovec) * ab->nr_entries);
if (addr) {
*addr = g_malloc0(sizeof(uint64_t) * ab->nr_entries);
}
for (i = 0; i < ab->nr_entries; i++) {
uint64_t a = le64_to_cpu(ents[i].addr);
uint32_t l = le32_to_cpu(ents[i].length);
hwaddr len = l;
(*iov)[i].iov_len = l;
(*iov)[i].iov_base = dma_memory_map(VIRTIO_DEVICE(g)->dma_as,
a, &len, DMA_DIRECTION_TO_DEVICE);
if (addr) {
(*addr)[i] = a;
}
if (!(*iov)[i].iov_base || len != l) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to map MMIO memory for"
" resource %d element %d\n",
__func__, ab->resource_id, i);
virtio_gpu_cleanup_mapping_iov(g, *iov, i);
g_free(ents);
*iov = NULL;
if (addr) {
g_free(*addr);
*addr = NULL;
}
return -1;
}
}
g_free(ents);
return 0;
}
void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
struct iovec *iov, uint32_t count)
{
int i;
for (i = 0; i < count; i++) {
dma_memory_unmap(VIRTIO_DEVICE(g)->dma_as,
iov[i].iov_base, iov[i].iov_len,
DMA_DIRECTION_TO_DEVICE,
iov[i].iov_len);
}
g_free(iov);
}
static void virtio_gpu_cleanup_mapping(VirtIOGPU *g,
struct virtio_gpu_simple_resource *res)
{
virtio_gpu_cleanup_mapping_iov(g, res->iov, res->iov_cnt);
res->iov = NULL;
res->iov_cnt = 0;
g_free(res->addrs);
res->addrs = NULL;
}
static void
virtio_gpu_resource_attach_backing(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_simple_resource *res;
struct virtio_gpu_resource_attach_backing ab;
int ret;
VIRTIO_GPU_FILL_CMD(ab);
virtio_gpu_bswap_32(&ab, sizeof(ab));
trace_virtio_gpu_cmd_res_back_attach(ab.resource_id);
res = virtio_gpu_find_resource(g, ab.resource_id);
if (!res) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
__func__, ab.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
if (res->iov) {
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
}
ret = virtio_gpu_create_mapping_iov(g, &ab, cmd, &res->addrs, &res->iov);
if (ret != 0) {
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
}
res->iov_cnt = ab.nr_entries;
}
static void
virtio_gpu_resource_detach_backing(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
struct virtio_gpu_simple_resource *res;
struct virtio_gpu_resource_detach_backing detach;
VIRTIO_GPU_FILL_CMD(detach);
virtio_gpu_bswap_32(&detach, sizeof(detach));
trace_virtio_gpu_cmd_res_back_detach(detach.resource_id);
res = virtio_gpu_find_resource(g, detach.resource_id);
if (!res || !res->iov) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
__func__, detach.resource_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
return;
}
virtio_gpu_cleanup_mapping(g, res);
}
static void virtio_gpu_simple_process_cmd(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
virtio_gpu_ctrl_hdr_bswap(&cmd->cmd_hdr);
switch (cmd->cmd_hdr.type) {
case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
virtio_gpu_get_display_info(g, cmd);
break;
case VIRTIO_GPU_CMD_GET_EDID:
virtio_gpu_get_edid(g, cmd);
break;
case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
virtio_gpu_resource_create_2d(g, cmd);
break;
case VIRTIO_GPU_CMD_RESOURCE_UNREF:
virtio_gpu_resource_unref(g, cmd);
break;
case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
virtio_gpu_resource_flush(g, cmd);
break;
case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
virtio_gpu_transfer_to_host_2d(g, cmd);
break;
case VIRTIO_GPU_CMD_SET_SCANOUT:
virtio_gpu_set_scanout(g, cmd);
break;
case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
virtio_gpu_resource_attach_backing(g, cmd);
break;
case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
virtio_gpu_resource_detach_backing(g, cmd);
break;
default:
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
break;
}
if (!cmd->finished) {
virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error ? cmd->error :
VIRTIO_GPU_RESP_OK_NODATA);
}
}
static void virtio_gpu_handle_ctrl_cb(VirtIODevice *vdev, VirtQueue *vq)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
qemu_bh_schedule(g->ctrl_bh);
}
static void virtio_gpu_handle_cursor_cb(VirtIODevice *vdev, VirtQueue *vq)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
qemu_bh_schedule(g->cursor_bh);
}
void virtio_gpu_process_cmdq(VirtIOGPU *g)
{
struct virtio_gpu_ctrl_command *cmd;
while (!QTAILQ_EMPTY(&g->cmdq)) {
cmd = QTAILQ_FIRST(&g->cmdq);
if (g->renderer_blocked) {
break;
}
/* process command */
VIRGL(g, virtio_gpu_virgl_process_cmd, virtio_gpu_simple_process_cmd,
g, cmd);
QTAILQ_REMOVE(&g->cmdq, cmd, next);
if (virtio_gpu_stats_enabled(g->conf)) {
g->stats.requests++;
}
if (!cmd->finished) {
QTAILQ_INSERT_TAIL(&g->fenceq, cmd, next);
g->inflight++;
if (virtio_gpu_stats_enabled(g->conf)) {
if (g->stats.max_inflight < g->inflight) {
g->stats.max_inflight = g->inflight;
}
fprintf(stderr, "inflight: %3d (+)\r", g->inflight);
}
} else {
g_free(cmd);
}
}
}
static void virtio_gpu_handle_ctrl(VirtIODevice *vdev, VirtQueue *vq)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
struct virtio_gpu_ctrl_command *cmd;
if (!virtio_queue_ready(vq)) {
return;
}
#ifdef CONFIG_VIRGL
if (!g->renderer_inited && g->use_virgl_renderer) {
virtio_gpu_virgl_init(g);
g->renderer_inited = true;
}
#endif
cmd = virtqueue_pop(vq, sizeof(struct virtio_gpu_ctrl_command));
while (cmd) {
cmd->vq = vq;
cmd->error = 0;
cmd->finished = false;
QTAILQ_INSERT_TAIL(&g->cmdq, cmd, next);
cmd = virtqueue_pop(vq, sizeof(struct virtio_gpu_ctrl_command));
}
virtio_gpu_process_cmdq(g);
#ifdef CONFIG_VIRGL
if (g->use_virgl_renderer) {
virtio_gpu_virgl_fence_poll(g);
}
#endif
}
static void virtio_gpu_ctrl_bh(void *opaque)
{
VirtIOGPU *g = opaque;
virtio_gpu_handle_ctrl(&g->parent_obj, g->ctrl_vq);
}
static void virtio_gpu_handle_cursor(VirtIODevice *vdev, VirtQueue *vq)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
VirtQueueElement *elem;
size_t s;
struct virtio_gpu_update_cursor cursor_info;
if (!virtio_queue_ready(vq)) {
return;
}
for (;;) {
elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
if (!elem) {
break;
}
s = iov_to_buf(elem->out_sg, elem->out_num, 0,
&cursor_info, sizeof(cursor_info));
if (s != sizeof(cursor_info)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: cursor size incorrect %zu vs %zu\n",
__func__, s, sizeof(cursor_info));
} else {
virtio_gpu_bswap_32(&cursor_info, sizeof(cursor_info));
update_cursor(g, &cursor_info);
}
virtqueue_push(vq, elem, 0);
virtio_notify(vdev, vq);
g_free(elem);
}
}
static void virtio_gpu_cursor_bh(void *opaque)
{
VirtIOGPU *g = opaque;
virtio_gpu_handle_cursor(&g->parent_obj, g->cursor_vq);
}
static void virtio_gpu_invalidate_display(void *opaque)
{
}
static void virtio_gpu_update_display(void *opaque)
{
}
static void virtio_gpu_text_update(void *opaque, console_ch_t *chardata)
{
}
static int virtio_gpu_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
{
VirtIOGPU *g = opaque;
if (idx >= g->conf.max_outputs) {
return -1;
}
g->req_state[idx].x = info->xoff;
g->req_state[idx].y = info->yoff;
g->req_state[idx].width = info->width;
g->req_state[idx].height = info->height;
if (info->width && info->height) {
g->enabled_output_bitmask |= (1 << idx);
} else {
g->enabled_output_bitmask &= ~(1 << idx);
}
/* send event to guest */
virtio_gpu_notify_event(g, VIRTIO_GPU_EVENT_DISPLAY);
return 0;
}
static void virtio_gpu_gl_block(void *opaque, bool block)
{
VirtIOGPU *g = opaque;
if (block) {
g->renderer_blocked++;
} else {
g->renderer_blocked--;
}
assert(g->renderer_blocked >= 0);
if (g->renderer_blocked == 0) {
#ifdef CONFIG_VIRGL
if (g->renderer_reset) {
g->renderer_reset = false;
virtio_gpu_virgl_reset(g);
}
#endif
virtio_gpu_process_cmdq(g);
}
}
const GraphicHwOps virtio_gpu_ops = {
.invalidate = virtio_gpu_invalidate_display,
.gfx_update = virtio_gpu_update_display,
.text_update = virtio_gpu_text_update,
.ui_info = virtio_gpu_ui_info,
.gl_block = virtio_gpu_gl_block,
};
static const VMStateDescription vmstate_virtio_gpu_scanout = {
.name = "virtio-gpu-one-scanout",
.version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(resource_id, struct virtio_gpu_scanout),
VMSTATE_UINT32(width, struct virtio_gpu_scanout),
VMSTATE_UINT32(height, struct virtio_gpu_scanout),
VMSTATE_INT32(x, struct virtio_gpu_scanout),
VMSTATE_INT32(y, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.resource_id, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.hot_x, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.hot_y, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.pos.x, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.pos.y, struct virtio_gpu_scanout),
VMSTATE_END_OF_LIST()
},
};
static const VMStateDescription vmstate_virtio_gpu_scanouts = {
.name = "virtio-gpu-scanouts",
.version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_INT32(enable, struct VirtIOGPU),
VMSTATE_UINT32_EQUAL(conf.max_outputs, struct VirtIOGPU, NULL),
VMSTATE_STRUCT_VARRAY_UINT32(scanout, struct VirtIOGPU,
conf.max_outputs, 1,
vmstate_virtio_gpu_scanout,
struct virtio_gpu_scanout),
VMSTATE_END_OF_LIST()
},
};
static int virtio_gpu_save(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field, QJSON *vmdesc)
{
VirtIOGPU *g = opaque;
struct virtio_gpu_simple_resource *res;
int i;
/* in 2d mode we should never find unprocessed commands here */
assert(QTAILQ_EMPTY(&g->cmdq));
QTAILQ_FOREACH(res, &g->reslist, next) {
qemu_put_be32(f, res->resource_id);
qemu_put_be32(f, res->width);
qemu_put_be32(f, res->height);
qemu_put_be32(f, res->format);
qemu_put_be32(f, res->iov_cnt);
for (i = 0; i < res->iov_cnt; i++) {
qemu_put_be64(f, res->addrs[i]);
qemu_put_be32(f, res->iov[i].iov_len);
}
qemu_put_buffer(f, (void *)pixman_image_get_data(res->image),
pixman_image_get_stride(res->image) * res->height);
}
qemu_put_be32(f, 0); /* end of list */
return vmstate_save_state(f, &vmstate_virtio_gpu_scanouts, g, NULL);
}
static int virtio_gpu_load(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field)
{
VirtIOGPU *g = opaque;
struct virtio_gpu_simple_resource *res;
struct virtio_gpu_scanout *scanout;
uint32_t resource_id, pformat;
int i;
g->hostmem = 0;
resource_id = qemu_get_be32(f);
while (resource_id != 0) {
res = g_new0(struct virtio_gpu_simple_resource, 1);
res->resource_id = resource_id;
res->width = qemu_get_be32(f);
res->height = qemu_get_be32(f);
res->format = qemu_get_be32(f);
res->iov_cnt = qemu_get_be32(f);
/* allocate */
pformat = get_pixman_format(res->format);
if (!pformat) {
g_free(res);
return -EINVAL;
}
res->image = pixman_image_create_bits(pformat,
res->width, res->height,
NULL, 0);
if (!res->image) {
g_free(res);
return -EINVAL;
}
res->hostmem = calc_image_hostmem(pformat, res->width, res->height);
res->addrs = g_new(uint64_t, res->iov_cnt);
res->iov = g_new(struct iovec, res->iov_cnt);
/* read data */
for (i = 0; i < res->iov_cnt; i++) {
res->addrs[i] = qemu_get_be64(f);
res->iov[i].iov_len = qemu_get_be32(f);
}
qemu_get_buffer(f, (void *)pixman_image_get_data(res->image),
pixman_image_get_stride(res->image) * res->height);
/* restore mapping */
for (i = 0; i < res->iov_cnt; i++) {
hwaddr len = res->iov[i].iov_len;
res->iov[i].iov_base =
dma_memory_map(VIRTIO_DEVICE(g)->dma_as,
res->addrs[i], &len, DMA_DIRECTION_TO_DEVICE);
if (!res->iov[i].iov_base || len != res->iov[i].iov_len) {
/* Clean up the half-a-mapping we just created... */
if (res->iov[i].iov_base) {
dma_memory_unmap(VIRTIO_DEVICE(g)->dma_as,
res->iov[i].iov_base,
res->iov[i].iov_len,
DMA_DIRECTION_TO_DEVICE,
res->iov[i].iov_len);
}
/* ...and the mappings for previous loop iterations */
res->iov_cnt = i;
virtio_gpu_cleanup_mapping(g, res);
pixman_image_unref(res->image);
g_free(res);
return -EINVAL;
}
}
QTAILQ_INSERT_HEAD(&g->reslist, res, next);
g->hostmem += res->hostmem;
resource_id = qemu_get_be32(f);
}
/* load & apply scanout state */
vmstate_load_state(f, &vmstate_virtio_gpu_scanouts, g, 1);
for (i = 0; i < g->conf.max_outputs; i++) {
scanout = &g->scanout[i];
if (!scanout->resource_id) {
continue;
}
res = virtio_gpu_find_resource(g, scanout->resource_id);
if (!res) {
return -EINVAL;
}
scanout->ds = qemu_create_displaysurface_pixman(res->image);
if (!scanout->ds) {
return -EINVAL;
}
dpy_gfx_replace_surface(scanout->con, scanout->ds);
dpy_gfx_update_full(scanout->con);
if (scanout->cursor.resource_id) {
update_cursor(g, &scanout->cursor);
}
res->scanout_bitmask |= (1 << i);
}
return 0;
}
static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
{
VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
VirtIOGPU *g = VIRTIO_GPU(qdev);
bool have_virgl;
Error *local_err = NULL;
int i;
if (g->conf.max_outputs > VIRTIO_GPU_MAX_SCANOUTS) {
error_setg(errp, "invalid max_outputs > %d", VIRTIO_GPU_MAX_SCANOUTS);
return;
}
g->use_virgl_renderer = false;
#if !defined(CONFIG_VIRGL) || defined(HOST_WORDS_BIGENDIAN)
have_virgl = false;
#else
have_virgl = display_opengl;
#endif
if (!have_virgl) {
g->conf.flags &= ~(1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED);
}
if (virtio_gpu_virgl_enabled(g->conf)) {
error_setg(&g->migration_blocker, "virgl is not yet migratable");
migrate_add_blocker(g->migration_blocker, &local_err);
if (local_err) {
error_propagate(errp, local_err);
error_free(g->migration_blocker);
return;
}
}
g->virtio_config.num_scanouts = cpu_to_le32(g->conf.max_outputs);
virtio_init(VIRTIO_DEVICE(g), "virtio-gpu", VIRTIO_ID_GPU,
sizeof(struct virtio_gpu_config));
g->req_state[0].width = g->conf.xres;
g->req_state[0].height = g->conf.yres;
if (virtio_gpu_virgl_enabled(g->conf)) {
/* use larger control queue in 3d mode */
g->ctrl_vq = virtio_add_queue(vdev, 256, virtio_gpu_handle_ctrl_cb);
g->cursor_vq = virtio_add_queue(vdev, 16, virtio_gpu_handle_cursor_cb);
#if defined(CONFIG_VIRGL)
g->virtio_config.num_capsets = virtio_gpu_virgl_get_num_capsets(g);
#else
g->virtio_config.num_capsets = 0;
#endif
} else {
g->ctrl_vq = virtio_add_queue(vdev, 64, virtio_gpu_handle_ctrl_cb);
g->cursor_vq = virtio_add_queue(vdev, 16, virtio_gpu_handle_cursor_cb);
}
g->ctrl_bh = qemu_bh_new(virtio_gpu_ctrl_bh, g);
g->cursor_bh = qemu_bh_new(virtio_gpu_cursor_bh, g);
QTAILQ_INIT(&g->reslist);
QTAILQ_INIT(&g->cmdq);
QTAILQ_INIT(&g->fenceq);
g->enabled_output_bitmask = 1;
for (i = 0; i < g->conf.max_outputs; i++) {
g->scanout[i].con =
graphic_console_init(DEVICE(g), i, &virtio_gpu_ops, g);
if (i > 0) {
dpy_gfx_replace_surface(g->scanout[i].con, NULL);
}
}
}
static void virtio_gpu_device_unrealize(DeviceState *qdev, Error **errp)
{
VirtIOGPU *g = VIRTIO_GPU(qdev);
if (g->migration_blocker) {
migrate_del_blocker(g->migration_blocker);
error_free(g->migration_blocker);
}
}
static void virtio_gpu_instance_init(Object *obj)
{
}
static void virtio_gpu_reset(VirtIODevice *vdev)
{
VirtIOGPU *g = VIRTIO_GPU(vdev);
struct virtio_gpu_simple_resource *res, *tmp;
struct virtio_gpu_ctrl_command *cmd;
int i;
g->enable = 0;
QTAILQ_FOREACH_SAFE(res, &g->reslist, next, tmp) {
virtio_gpu_resource_destroy(g, res);
}
for (i = 0; i < g->conf.max_outputs; i++) {
g->scanout[i].resource_id = 0;
g->scanout[i].width = 0;
g->scanout[i].height = 0;
g->scanout[i].x = 0;
g->scanout[i].y = 0;
g->scanout[i].ds = NULL;
}
while (!QTAILQ_EMPTY(&g->cmdq)) {
cmd = QTAILQ_FIRST(&g->cmdq);
QTAILQ_REMOVE(&g->cmdq, cmd, next);
g_free(cmd);
}
while (!QTAILQ_EMPTY(&g->fenceq)) {
cmd = QTAILQ_FIRST(&g->fenceq);
QTAILQ_REMOVE(&g->fenceq, cmd, next);
g->inflight--;
g_free(cmd);
}
#ifdef CONFIG_VIRGL
if (g->use_virgl_renderer) {
if (g->renderer_blocked) {
g->renderer_reset = true;
} else {
virtio_gpu_virgl_reset(g);
}
g->use_virgl_renderer = 0;
}
#endif
}
/*
* For historical reasons virtio_gpu does not adhere to virtio migration
* scheme as described in doc/virtio-migration.txt, in a sense that no
* save/load callback are provided to the core. Instead the device data
* is saved/loaded after the core data.
*
* Because of this we need a special vmsd.
*/
static const VMStateDescription vmstate_virtio_gpu = {
.name = "virtio-gpu",
.minimum_version_id = VIRTIO_GPU_VM_VERSION,
.version_id = VIRTIO_GPU_VM_VERSION,
.fields = (VMStateField[]) {
VMSTATE_VIRTIO_DEVICE /* core */,
{
.name = "virtio-gpu",
.info = &(const VMStateInfo) {
.name = "virtio-gpu",
.get = virtio_gpu_load,
.put = virtio_gpu_save,
},
.flags = VMS_SINGLE,
} /* device */,
VMSTATE_END_OF_LIST()
},
};
static Property virtio_gpu_properties[] = {
DEFINE_PROP_UINT32("max_outputs", VirtIOGPU, conf.max_outputs, 1),
DEFINE_PROP_SIZE("max_hostmem", VirtIOGPU, conf.max_hostmem, 256 * MiB),
#ifdef CONFIG_VIRGL
DEFINE_PROP_BIT("virgl", VirtIOGPU, conf.flags,
VIRTIO_GPU_FLAG_VIRGL_ENABLED, true),
DEFINE_PROP_BIT("stats", VirtIOGPU, conf.flags,
VIRTIO_GPU_FLAG_STATS_ENABLED, false),
#endif
DEFINE_PROP_BIT("edid", VirtIOGPU, conf.flags,
VIRTIO_GPU_FLAG_EDID_ENABLED, false),
DEFINE_PROP_UINT32("xres", VirtIOGPU, conf.xres, 1024),
DEFINE_PROP_UINT32("yres", VirtIOGPU, conf.yres, 768),
DEFINE_PROP_END_OF_LIST(),
};
static void virtio_gpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
vdc->realize = virtio_gpu_device_realize;
vdc->unrealize = virtio_gpu_device_unrealize;
vdc->get_config = virtio_gpu_get_config;
vdc->set_config = virtio_gpu_set_config;
vdc->get_features = virtio_gpu_get_features;
vdc->set_features = virtio_gpu_set_features;
vdc->reset = virtio_gpu_reset;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->props = virtio_gpu_properties;
dc->vmsd = &vmstate_virtio_gpu;
dc->hotpluggable = false;
}
static const TypeInfo virtio_gpu_info = {
.name = TYPE_VIRTIO_GPU,
.parent = TYPE_VIRTIO_DEVICE,
.instance_size = sizeof(VirtIOGPU),
.instance_init = virtio_gpu_instance_init,
.class_init = virtio_gpu_class_init,
};
static void virtio_register_types(void)
{
type_register_static(&virtio_gpu_info);
}
type_init(virtio_register_types)
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctrl_hdr) != 24);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_update_cursor) != 56);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_unref) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_2d) != 40);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_set_scanout) != 48);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_flush) != 48);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_to_host_2d) != 56);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_mem_entry) != 16);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_attach_backing) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_detach_backing) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_display_info) != 408);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_transfer_host_3d) != 72);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resource_create_3d) != 72);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_create) != 96);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_destroy) != 24);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_ctx_resource) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_cmd_submit) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset_info) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset_info) != 40);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_get_capset) != 32);
QEMU_BUILD_BUG_ON(sizeof(struct virtio_gpu_resp_capset) != 24);
|
pmp-tool/PMP | src/qemu/src-pmp/tests/display-vga-test.c | <reponame>pmp-tool/PMP
/*
* QTest testcase for vga cards
*
* Copyright (c) 2014 Red Hat, Inc
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
static void pci_cirrus(void)
{
qtest_start("-vga none -device cirrus-vga");
qtest_end();
}
static void pci_stdvga(void)
{
qtest_start("-vga none -device VGA");
qtest_end();
}
static void pci_secondary(void)
{
qtest_start("-vga none -device secondary-vga");
qtest_end();
}
static void pci_multihead(void)
{
qtest_start("-vga none -device VGA -device secondary-vga");
qtest_end();
}
static void pci_virtio_gpu(void)
{
qtest_start("-vga none -device virtio-gpu-pci");
qtest_end();
}
static void pci_virtio_vga(void)
{
qtest_start("-vga none -device virtio-vga");
qtest_end();
}
int main(int argc, char **argv)
{
const char *arch = qtest_get_arch();
g_test_init(&argc, &argv, NULL);
if (strcmp(arch, "alpha") == 0 || strcmp(arch, "i386") == 0 ||
strcmp(arch, "mips") == 0 || strcmp(arch, "x86_64") == 0) {
qtest_add_func("/display/pci/cirrus", pci_cirrus);
}
qtest_add_func("/display/pci/stdvga", pci_stdvga);
qtest_add_func("/display/pci/secondary", pci_secondary);
qtest_add_func("/display/pci/multihead", pci_multihead);
qtest_add_func("/display/pci/virtio-gpu", pci_virtio_gpu);
if (g_str_equal(arch, "i386") || g_str_equal(arch, "x86_64") ||
g_str_equal(arch, "hppa") || g_str_equal(arch, "ppc64")) {
qtest_add_func("/display/pci/virtio-vga", pci_virtio_vga);
}
return g_test_run();
}
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.