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module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_0_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_0_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 02/15/2011 - Added read_early_done_enable to the wire breakout
1.2 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This block is responsible for communicating with the host processor/
descriptor prefetching master block. It uses FIFOs to buffer descriptors
to keep the read and write masters operating without intervention from a
host processor. This block is comprised of three main blocks:
1) Descriptor buffer
2) CSR
3) Response
The descriptor buffer recieves descriptors from a host/prefetcher and
registers the incoming byte lanes. When the descriptor 'go' bit has been
written, the descriptor is committed to the read/write descriptor buffers.
From there the descriptors are exposed to the read and write masters without
intervention from the host. The descriptor port is either 128 or 256 bits
wide depending on whether or not the enhanced features setting has been enabled.
Since the port is write only minimial logic will be created in the fabric
to adapt the byte enables for narrow masters connecting to this port. This
port contains a single address so address bits are exposed to the fabric.
The CSR (control-status register) block is used to provide information
back to the host as well as allow the SGDMA to be controlled on a
non-descriptor basis. The host driver should be written to mostly interact
with this port as interrupts and status information is accessible from this
block.
The optional response block is used to feed information on a per descriptor
basis back to the host or prefetching descriptor master. In most cases the
port will be used for sharing infomation about ST->MM transfers.
Communication between this block and the masters is performed using pairs
of Avalon-ST port connections. When the SGDMA is setup for MM->ST then the
write master port connections are removed and visa vera for ST->MM and the
read master. For more detailed information refer to "SGDMA_dispatcher_ug.pdf"
for more details.
Author: JCJB
Date: 08/13/2010
1.0 - Initial release
1.1 - Changed the stopped and resetting logic to correctly reflect the state
of the hardware (this block and the masters).
1.2 - Added stop descriptors logic
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module dispatcher (
clk,
reset,
// 128/256 bit write only port for feeding the dispatcher descriptors, no address since it's only one word wide, blocking when too many descriptors are buffered
descriptor_writedata,
descriptor_byteenable,
descriptor_write,
descriptor_waitrequest,
// control and status port, 32 bits wide with a read latency of 2 and non-blocking
csr_writedata,
csr_byteenable,
csr_write,
csr_readdata,
csr_read,
csr_address, // 4 addresses when ENHANCED_FEATURES is off (zero) otherwise 8 addresses are available
csr_irq, // only available if the response port is not an ST source (in that case the SGDMA pre-fetching block will issue interrupts)
// response slave port (when "RESPONSE_PORT" is set to 0), 32 bits wide, read only, and a read latency of 3 cycles
mm_response_readdata,
mm_response_read,
mm_response_address, // only two addresses
mm_response_byteenable, // last byte read pops the response FIFO
mm_response_waitrequest,
// response source port (when "RESPONSE_PORT" is set to 1),
src_response_data,
src_response_valid,
src_response_ready,
// write master source port (sends commands to write master)
src_write_master_data,
src_write_master_valid,
src_write_master_ready,
// write master sink port (recieves response from write master)
snk_write_master_data,
snk_write_master_valid,
snk_write_master_ready,
// read master source port (sends commands to read master)
src_read_master_data,
src_read_master_valid,
src_read_master_ready,
// read master sink port (recieves response from the read master)
snk_read_master_data,
snk_read_master_valid,
snk_read_master_ready
);
// y = log2(x)
function integer log2;
input integer x;
begin
x = x-1;
for(log2=0; x>0; log2=log2+1)
x = x>>1;
end
endfunction
parameter MODE = 0; // 0 for MM->MM, 1 for MM->ST, 2 for ST->MM
parameter RESPONSE_PORT = 0; // 0 for MM, 1 for ST, 2 for Disabled // normally disabled for all but ST->MM transfers
parameter DESCRIPTOR_FIFO_DEPTH = 128; // 16-1024 in powers of 2
parameter ENHANCED_FEATURES = 1; // 1 for Enabled, 0 for Disabled
parameter DESCRIPTOR_WIDTH = 256; // 256 when enhanced mode is on, 128 for off (needs to be controlled by callback since it influences data width)
parameter DESCRIPTOR_BYTEENABLE_WIDTH = 32; // 32 when enhanced mode is on, 16 for off (needs to be controlled by callback since it influences byte enable width)
parameter CSR_ADDRESS_WIDTH = 3; // always 3 bits wide
localparam RESPONSE_FIFO_DEPTH = 2 * DESCRIPTOR_FIFO_DEPTH;
localparam DESCRIPTOR_FIFO_DEPTH_LOG2 = log2(DESCRIPTOR_FIFO_DEPTH);
localparam RESPONSE_FIFO_DEPTH_LOG2 = log2(RESPONSE_FIFO_DEPTH);
input clk;
input reset;
input [DESCRIPTOR_WIDTH-1:0] descriptor_writedata;
input [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable;
input descriptor_write;
output wire descriptor_waitrequest;
input [31:0] csr_writedata;
input [3:0] csr_byteenable;
input csr_write;
output wire [31:0] csr_readdata;
input csr_read;
input [CSR_ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
// Used by a host with a master (like Nios II)
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address;
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
// Used by a pre-fetching master
output wire [255:0] src_response_data; // making wide in case we need to jam more signals in here, unnecessary bits will be grounded/optimized away
output wire src_response_valid;
input src_response_ready;
output wire [255:0] src_write_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away
output wire src_write_master_valid;
input src_write_master_ready;
input [255:0] snk_write_master_data; // might need to jam more bits in......
input snk_write_master_valid;
output wire snk_write_master_ready;
output wire [255:0] src_read_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away
output wire src_read_master_valid;
input src_read_master_ready;
input [255:0] snk_read_master_data; // might need to jam more bits in......
input snk_read_master_valid;
output wire snk_read_master_ready;
/* Internal wires and registers */
// descriptor information
wire read_command_valid;
wire read_command_ready;
wire [255:0] read_command_data;
wire read_command_empty;
wire read_command_full;
wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] read_command_used; // true used signal so extra MSB is included
wire write_command_valid;
wire write_command_ready;
wire [255:0] write_command_data;
wire write_command_empty;
wire write_command_full;
wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] write_command_used; // true used signal so extra MSB is included
wire [31:0] sequence_number;
wire transfer_complete_IRQ_mask;
wire early_termination_IRQ_mask;
wire [7:0] error_IRQ_mask;
wire descriptor_buffer_empty;
wire descriptor_buffer_full;
wire [15:0] write_descriptor_watermark;
wire [15:0] read_descriptor_watermark;
wire [31:0] descriptor_watermark;
wire busy;
wire done;
wire done_strobe;
wire stop_issuing_commands;
wire stop;
wire sw_reset;
wire stop_on_error;
wire stop_on_early_termination;
wire stop_descriptors;
wire reset_stalled;
wire master_stop_state;
wire descriptors_stop_state;
wire stop_state;
wire stopped_on_error;
wire stopped_on_early_termination;
wire response_fifo_full;
wire response_fifo_empty;
wire [15:0] response_watermark;
wire [7:0] response_error;
wire response_early_termination;
wire [31:0] response_actual_bytes_transferred;
/************************************************ REGISTERS *******************************************************/
/********************************************** END REGISTERS *****************************************************/
/******************************************* MODULE DECLERATIONS **************************************************/
// the descriptor buffers block instantiates the descriptor FIFOs and handshaking logic with the master command ports
descriptor_buffers the_descriptor_buffers (
.clk (clk),
.reset (reset),
.writedata (descriptor_writedata),
.write (descriptor_write),
.byteenable (descriptor_byteenable),
.waitrequest (descriptor_waitrequest),
.read_command_valid (read_command_valid),
.read_command_ready (read_command_ready),
.read_command_data (read_command_data),
.read_command_empty (read_command_empty),
.read_command_full (read_command_full),
.read_command_used (read_command_used),
.write_command_valid (write_command_valid),
.write_command_ready (write_command_ready),
.write_command_data (write_command_data),
.write_command_empty (write_command_empty),
.write_command_full (write_command_full),
.write_command_used (write_command_used),
.stop_issuing_commands (stop_issuing_commands),
.stop (stop),
.sw_reset (sw_reset),
.sequence_number (sequence_number),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask)
);
defparam the_descriptor_buffers.MODE = MODE;
defparam the_descriptor_buffers.DATA_WIDTH = DESCRIPTOR_WIDTH;
defparam the_descriptor_buffers.BYTE_ENABLE_WIDTH = DESCRIPTOR_WIDTH/8;
defparam the_descriptor_buffers.FIFO_DEPTH = DESCRIPTOR_FIFO_DEPTH;
defparam the_descriptor_buffers.FIFO_DEPTH_LOG2 = DESCRIPTOR_FIFO_DEPTH_LOG2;
// Control and status registers (and interrupts when a host connects directly to this block)
csr_block the_csr_block (
.clk (clk),
.reset (reset),
.csr_writedata (csr_writedata),
.csr_write (csr_write),
.csr_byteenable (csr_byteenable),
.csr_readdata (csr_readdata),
.csr_read (csr_read),
.csr_address (csr_address),
.csr_irq (csr_irq),
.done_strobe (done_strobe),
.busy (busy),
.descriptor_buffer_empty (descriptor_buffer_empty),
.descriptor_buffer_full (descriptor_buffer_full),
.stop_state (stop_state),
.stopped_on_error (stopped_on_error),
.stopped_on_early_termination (stopped_on_early_termination),
.stop_descriptors (stop_descriptors),
.reset_stalled (reset_stalled), // from the master(s) to tell the CSR block that it's still resetting
.stop (stop),
.sw_reset (sw_reset),
.stop_on_error (stop_on_error),
.stop_on_early_termination (stop_on_early_termination),
.sequence_number (sequence_number),
.descriptor_watermark (descriptor_watermark),
.response_watermark (response_watermark),
.response_buffer_empty (response_fifo_empty),
.response_buffer_full (response_fifo_full),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.error (response_error),
.early_termination (response_early_termination)
);
defparam the_csr_block.ADDRESS_WIDTH = CSR_ADDRESS_WIDTH;
// Optional response port. When using a directly connected host it'll be a slave port and using a pre-fetching descriptor master it will be a streaming source port.
response_block the_response_block (
.clk (clk),
.reset (reset),
.mm_response_readdata (mm_response_readdata),
.mm_response_read (mm_response_read),
.mm_response_address (mm_response_address),
.mm_response_byteenable (mm_response_byteenable),
.mm_response_waitrequest (mm_response_waitrequest),
.src_response_data (src_response_data),
.src_response_valid (src_response_valid),
.src_response_ready (src_response_ready),
.sw_reset (sw_reset),
.response_watermark (response_watermark),
.response_fifo_full (response_fifo_full),
.response_fifo_empty (response_fifo_empty),
.done_strobe (done_strobe),
.actual_bytes_transferred (response_actual_bytes_transferred),
.error (response_error),
.early_termination (response_early_termination),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.descriptor_buffer_full (descriptor_buffer_full)
);
defparam the_response_block.RESPONSE_PORT = RESPONSE_PORT;
defparam the_response_block.FIFO_DEPTH = RESPONSE_FIFO_DEPTH;
defparam the_response_block.FIFO_DEPTH_LOG2 = RESPONSE_FIFO_DEPTH_LOG2;
/***************************************** END MODULE DECLERATIONS ************************************************/
/****************************************** COMBINATIONAL SIGNALS *************************************************/
// this block issues the commands so it's always ready for a response. The response FIFO fill level will be used to
// make sure additional ST-->MM commands are not issued if there is no room to catch the response.
assign snk_write_master_ready = 1'b1;
assign snk_read_master_ready = 1'b1;
assign done = (MODE == 1)? snk_read_master_ready : snk_write_master_ready;
assign done_strobe = (MODE == 1)? (snk_read_master_ready & snk_read_master_valid) : (snk_write_master_ready & snk_write_master_valid);
assign stop_issuing_commands = (response_fifo_full == 1) | (stop_descriptors == 1);
assign src_write_master_valid = write_command_valid;
assign write_command_ready = src_write_master_ready;
assign src_write_master_data = write_command_data;
assign src_read_master_valid = read_command_valid;
assign read_command_ready = src_read_master_ready;
assign src_read_master_data = read_command_data;
assign busy = (read_command_empty == 0) | (write_command_empty == 0) | // still have descriptors buffered in the FIFOs
(done == 0); // current transfer is still occuring
assign descriptor_buffer_empty = (read_command_empty == 1) & (write_command_empty == 1);
assign descriptor_buffer_full = (read_command_full == 1) | (write_command_full == 1);
assign write_descriptor_watermark = 16'h0000 | write_command_used; // zero padding the upper unused bits
assign read_descriptor_watermark = 16'h0000 | read_command_used; // zero padding the upper unused bits
assign descriptor_watermark = {write_descriptor_watermark, read_descriptor_watermark};
assign reset_stalled = snk_read_master_data[0] | snk_write_master_data[32];
assign master_stop_state = ((MODE == 0)? (snk_read_master_data[1] & snk_write_master_data[33]) :
(MODE == 1)? snk_read_master_data[1] : snk_write_master_data[33]);
assign descriptors_stop_state = (stop_descriptors == 1) & ((MODE == 0)? ((src_read_master_ready == 1) & (src_write_master_ready == 1)) :
(MODE == 1)? (src_read_master_ready == 1) : (src_write_master_ready == 1));
assign stop_state = (master_stop_state == 1) | (descriptors_stop_state == 1);
assign response_actual_bytes_transferred = snk_write_master_data[31:0];
assign response_error = snk_write_master_data[41:34];
assign response_early_termination = snk_write_master_data[42];
/**************************************** END COMBINATIONAL SIGNALS ***********************************************/
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
// Converts the 256-bit DMA master to the 64-bit PCIe slave
// Doesn't handle any special cases - the GUI validates that the parameters are consistant with our assumptions
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
// Converts the 256-bit DMA master to the 64-bit PCIe slave
// Doesn't handle any special cases - the GUI validates that the parameters are consistant with our assumptions
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux using MUXF7/8.
// Any generic_baseblocks_v2_1_0_mux ratio.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// mux_enc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_0_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux using MUXF7/8.
// Any generic_baseblocks_v2_1_0_mux ratio.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// mux_enc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_0_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
|
// megafunction wizard: %ALTTEMP_SENSE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTTEMP_SENSE
// ============================================================
// File Name: temp_sense.v
// Megafunction Name(s):
// ALTTEMP_SENSE
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix V" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" ce clk clr tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 12.0SP2 cbx_alttemp_sense 2012:08:02:15:11:11:SJ cbx_cycloneii 2012:08:02:15:11:11:SJ cbx_lpm_add_sub 2012:08:02:15:11:11:SJ cbx_lpm_compare 2012:08:02:15:11:11:SJ cbx_lpm_counter 2012:08:02:15:11:11:SJ cbx_lpm_decode 2012:08:02:15:11:11:SJ cbx_mgl 2012:08:02:15:40:54:SJ cbx_stratix 2012:08:02:15:11:11:SJ cbx_stratixii 2012:08:02:15:11:11:SJ cbx_stratixiii 2012:08:02:15:11:11:SJ cbx_stratixv 2012:08:02:15:11:11:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixv_tsdblock 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module temp_sense_alttemp_sense_v8t
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo));
defparam
sd1.clock_divider_enable = "true",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule //temp_sense_alttemp_sense_v8t
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: CLK_FREQUENCY STRING "50.0"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_ENABLE STRING "ON"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_VALUE NUMERIC "80"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alttemp_sense"
// Retrieval info: CONSTANT: NUMBER_OF_SAMPLES NUMERIC "128"
// Retrieval info: CONSTANT: POI_CAL_TEMPERATURE NUMERIC "85"
// Retrieval info: CONSTANT: SIM_TSDCALO NUMERIC "0"
// Retrieval info: CONSTANT: USER_OFFSET_ENABLE STRING "off"
// Retrieval info: CONSTANT: USE_WYS STRING "on"
// Retrieval info: USED_PORT: ce 0 0 0 0 INPUT NODEFVAL "ce"
// Retrieval info: CONNECT: @ce 0 0 0 0 ce 0 0 0 0
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: USED_PORT: clr 0 0 0 0 INPUT NODEFVAL "clr"
// Retrieval info: CONNECT: @clr 0 0 0 0 clr 0 0 0 0
// Retrieval info: USED_PORT: tsdcaldone 0 0 0 0 OUTPUT NODEFVAL "tsdcaldone"
// Retrieval info: CONNECT: tsdcaldone 0 0 0 0 @tsdcaldone 0 0 0 0
// Retrieval info: USED_PORT: tsdcalo 0 0 8 0 OUTPUT NODEFVAL "tsdcalo[7..0]"
// Retrieval info: CONNECT: tsdcalo 0 0 8 0 @tsdcalo 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.cmp FALSE TRUE
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule |
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule |
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k_18.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "18"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "18"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/05/2009
This FIFO module behaves similar to scfifo in legacy mode. It has an
output latency of 1 or 2 clock cycles and does not support look ahead
mode. Unlike scfifo this FIFO allows you to write to any of the byte
lanes before committing the word. This allows you to write the full
word in multiple clock cycles and then you assert the "push" signal to
commit the data. To read data out of the FIFO assert "pop" and wait
1 or 2 clock cycles for valid data to arrive.
Version 1.1
1.0 - Uses 'altsyncram' which will not be optimized away if the
FIFO inputs are grounded. This will need to be replaced
with inferred memory once Quartus II supports inferred
with byte enables (currently it instantiates multiple
seperate memories.
1.1 - Seperated the asynchronous reset into seperate async. and sync.
resets.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/05/2009
This FIFO module behaves similar to scfifo in legacy mode. It has an
output latency of 1 or 2 clock cycles and does not support look ahead
mode. Unlike scfifo this FIFO allows you to write to any of the byte
lanes before committing the word. This allows you to write the full
word in multiple clock cycles and then you assert the "push" signal to
commit the data. To read data out of the FIFO assert "pop" and wait
1 or 2 clock cycles for valid data to arrive.
Version 1.1
1.0 - Uses 'altsyncram' which will not be optimized away if the
FIFO inputs are grounded. This will need to be replaced
with inferred memory once Quartus II supports inferred
with byte enables (currently it instantiates multiple
seperate memories.
1.1 - Seperated the asynchronous reset into seperate async. and sync.
resets.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(* $Date: 2013-01-16 22:29:57 -0500 (Wed, 16 Jan 2013) $ *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
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// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 1.2
This block is responsible determine the appropriate burst count based on the
master length register as well as the buffer watermark and eop/early termination
conditions.
Within this block is a burst counter which is used to control when the next burst
is started. This down counter is loaded with whatever burst count is presented
to the fabric and counts down when waitrequest is deasserted. When it reaches 1
it can either start another burst or reach 0. When the counter reaches 0 this is
considered the idle state which can occur if there is not enough data buffered to
start another burst.
During write bursts the address and burst count must be held for all the beats.
This block will register the address and burst count to keep these signals
held constant to the fabric. This block will not begin a burst until enough
data has been buffered to start the burst so it will assert the stall signal
to keep the write master from advancing to the next word (just like waitrequest)
and will filter the write signal accordingly.
Revision History:
1.0 Initial version
1.1 Added sw_stop and stopped so that the write master will not be
stopped in the middle of a burst write transaction.
1.2 Added the sink ready and valid signals to this block and qualified the
eop signal with them.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 1.2
This block is responsible determine the appropriate burst count based on the
master length register as well as the buffer watermark and eop/early termination
conditions.
Within this block is a burst counter which is used to control when the next burst
is started. This down counter is loaded with whatever burst count is presented
to the fabric and counts down when waitrequest is deasserted. When it reaches 1
it can either start another burst or reach 0. When the counter reaches 0 this is
considered the idle state which can occur if there is not enough data buffered to
start another burst.
During write bursts the address and burst count must be held for all the beats.
This block will register the address and burst count to keep these signals
held constant to the fabric. This block will not begin a burst until enough
data has been buffered to start the burst so it will assert the stall signal
to keep the write master from advancing to the next word (just like waitrequest)
and will filter the write signal accordingly.
Revision History:
1.0 Initial version
1.1 Added sw_stop and stopped so that the write master will not be
stopped in the middle of a burst write transaction.
1.2 Added the sink ready and valid signals to this block and qualified the
eop signal with them.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/25/2009
Version 1.0
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/17/2010
Version 2.7
This read master module is responsible for reading data from memory and writing
the contents out to a streaming source port. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as the state of the master (reset/stop) is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming
2.1 Fixed bugs in the control logic which was causing too many reads to be posted
2.2 Added burst support and renamed the top level module to read master
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Added early done support for non unaligned or non packet based transfers
2.6 Fixed a flow control issue in the pending reads counter and too many reads pending
signal to avoid potential FIFO overflow issues. The read master now requires the
FIFO depth to be 4x the maximum burst count setting.
2.7 Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
src_data,
src_valid,
src_ready,
src_sop,
src_eop,
src_empty,
src_error,
src_channel,
// data path master port
master_address,
master_read,
master_byteenable,
master_readdata,
master_waitrequest,
master_readdatavalid,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter CHANNEL_ENABLE = 0;
parameter CHANNEL_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when the channel enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0; // when enabled stride must be disabled, 1 to enable, 0 to disable
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set maximum_burst_count to 1 (will be automatically done by .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(maximum_burst_count) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value "maximum_burst_count" will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
// when packet data is supported then we need to buffer the empty, eop, sop, error, and channel bits
localparam FIFO_WIDTH = DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2 + ERROR_WIDTH + CHANNEL_WIDTH;
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // default stride distance used when stride is disabled. 1 means increment the address by a word (i.e. sequential transfer)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path source port
output wire [DATA_WIDTH-1:0] src_data;
output wire src_valid;
input src_ready;
output wire src_sop;
output wire src_eop;
output wire [NUMBER_OF_SYMBOLS_LOG2-1:0] src_empty;
output wire [ERROR_WIDTH-1:0] src_error;
output wire [CHANNEL_WIDTH-1:0] src_channel;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_read;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
input [DATA_WIDTH-1:0] master_readdata;
input master_readdatavalid;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal signals
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire [7:0] descriptor_channel;
wire descriptor_generate_sop;
wire descriptor_generate_eop;
wire [7:0] descriptor_error;
wire [7:0] descriptor_programmable_burst_count;
wire descriptor_early_done_enable;
wire sw_stop_in;
wire sw_reset_in;
reg early_done_enable_d1;
reg [ERROR_WIDTH-1:0] error_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg generate_sop_d1;
reg generate_eop_d1;
reg [ADDRESS_WIDTH-1:0] address_counter;
reg [LENGTH_WIDTH-1:0] length_counter;
reg [CHANNEL_WIDTH-1:0] channel_d1;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignment the master starts
reg first_access; // used to determine if the first read is occuring
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
reg [FIFO_DEPTH_LOG2:0] pending_reads_counter;
reg [FIFO_DEPTH_LOG2:0] pending_reads_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire too_many_pending_reads;
wire read_complete; // handy signal for determining when a read has occured and completed
wire address_increment_enable;
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire go;
wire done; // asserted when last read is issued
reg done_d1;
wire done_strobe;
wire all_reads_returned; // asserted when last read returns
reg all_reads_returned_d1;
wire all_reads_returned_strobe;
reg all_reads_returned_strobe_d1;
reg all_reads_returned_strobe_d2; // used to trigger src_response_ready later than when the last read returns since the MM to ST has two pipeline stages
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout;
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout_rearranged;
wire MM_to_ST_adapter_sop;
wire MM_to_ST_adapter_eop;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] MM_to_ST_adapter_empty;
wire masked_sop;
wire masked_eop;
reg flush;
reg stopped;
wire length_sync_reset;
wire set_src_response_valid;
reg master_read_reg;
/********************************************* REGISTERS **************************************************/
// registering descriptor information
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error_d1 <= 0;
generate_sop_d1 <= 0;
generate_eop_d1 <= 0;
channel_d1 <= 0;
stride_d1 <= 0;
programmable_burst_count_d1 <= 0;
early_done_enable_d1 <= 0;
end
else if (go == 1)
begin
error_d1 <= descriptor_error[ERROR_WIDTH-1:0];
generate_sop_d1 <= descriptor_generate_sop;
generate_eop_d1 <= descriptor_generate_eop;
channel_d1 <= descriptor_channel[CHANNEL_WIDTH-1:0];
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
early_done_enable_d1 <= ((UNALIGNED_ACCESSES_ENABLE == 1) | (PACKET_ENABLE == 1))? 0 : descriptor_early_done_enable; // early done cannot be used when unaligned data or packet support is enabled
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first read of a transaction, this will be used to determine what value will be used to increment the counters
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (address_increment_enable == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1)
begin
length_counter <= 0;
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// the pending reads counter is used to determine how many outstanding reads are posted. This will be used to determine
// if more reads can be posted based on the number of unused words in the FIFO.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
pending_reads_counter <= 0;
end
else
begin
pending_reads_counter <= pending_reads_mux;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // master is done coming out of reset (need this to be set high so that done_strobe doesn't fire)
end
else
begin
done_d1 <= done;
end
end
// this is the 'final done' condition, since reads are pipelined need to make sure they have all returned before the master is really done.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_d1 <= 1;
end
else
begin
all_reads_returned_d1 <= all_reads_returned;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
flush <= 0;
end
else
begin
if ((pending_reads_counter == 0) & (flush == 1))
begin
flush <= 0;
end
else if ((sw_reset_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
flush <= 1; // will be used to reset the length counter to 0 and flush out pending reads (by letting them return without buffering them)
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (sw_reset_in == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if ((src_response_ready == 1) & (src_response_valid == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_strobe_d1 <= 0;
all_reads_returned_strobe_d2 <= 0;
end
else
begin
all_reads_returned_strobe_d1 <= all_reads_returned_strobe;
all_reads_returned_strobe_d2 <= all_reads_returned_strobe_d1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (flush == 1)
begin
src_response_valid <= 0;
end
else if (set_src_response_valid == 1) // all the reads have returned with MM to ST adapter latency taken into consideration
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
master_read_reg <= 0;
end
else
begin
if ((done == 0) & (too_many_pending_reads == 0) & (sw_stop_in == 0) & (sw_reset_in == 0))
begin
master_read_reg <= 1;
end
else if ((done == 1) | ((read_complete == 1) & ((too_many_pending_reads == 1) | (sw_stop_in == 1))))
begin
master_read_reg <= 0;
end
end
end
/******************************************* END REGISTERS ************************************************/
/************************************** MODULE INSTANTIATIONS *********************************************/
// This block is pipelined and can't throttle the reads
MM_to_ST_Adapter the_MM_to_ST_adapter (
.clk (clk),
.reset (reset),
.length (descriptor_length[LENGTH_WIDTH-1:0]),
.length_counter (length_counter),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.reads_pending (pending_reads_counter),
.start (go),
.readdata (master_readdata),
.readdatavalid (master_readdatavalid),
.fifo_data (MM_to_ST_adapter_dataout),
.fifo_write (fifo_write),
.fifo_empty (MM_to_ST_adapter_empty),
.fifo_sop (MM_to_ST_adapter_sop),
.fifo_eop (MM_to_ST_adapter_eop)
);
defparam the_MM_to_ST_adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_MM_to_ST_adapter.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_MM_to_ST_adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_MM_to_ST_adapter.BYTE_ADDRESS_WIDTH = BYTE_ENABLE_WIDTH_LOG2;
defparam the_MM_to_ST_adapter.READS_PENDING_WIDTH = FIFO_DEPTH_LOG2 + 1;
defparam the_MM_to_ST_adapter.EMPTY_WIDTH = NUMBER_OF_SYMBOLS_LOG2;
defparam the_MM_to_ST_adapter.PACKET_SUPPORT = PACKET_ENABLE;
defparam the_MM_to_ST_adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
defparam the_MM_to_ST_adapter.FULL_WORD_ACCESS_ONLY = ONLY_FULL_ACCESS_ENABLE;
// buffered sop, eop, empty, data (in that order). sop, eop, and empty are only buffered when packet support is enabled
scfifo the_master_to_st_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used),
.q (fifo_read_data),
.rdreq (fifo_read),
.wrreq (fifo_write)
);
defparam the_master_to_st_fifo.lpm_width = FIFO_WIDTH;
defparam the_master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_master_to_st_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_master_to_st_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.underflow_checking = "OFF";
defparam the_master_to_st_fifo.overflow_checking = "OFF";
// burst block that takes the length and short access enables and forms a burst count based on them. If any of the short access bits are asserted the block will default to a burst count of 1
read_burst_control the_read_burst_control (
.address (master_address),
.length (length_counter),
.maximum_burst_count (maximum_burst_count),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.burst_count (master_burstcount)
);
defparam the_read_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_read_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_read_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_read_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_read_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_read_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/************************************ END MODULE INSTANTIATIONS *******************************************/
/******************************** CONTROL AND COMBINATIONAL SIGNALS ***************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[140:109], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_channel = snk_command_data[71:64];
assign descriptor_generate_sop = snk_command_data[72];
assign descriptor_generate_eop = snk_command_data[73];
assign descriptor_programmable_burst_count = snk_command_data[83:76];
assign descriptor_stride = snk_command_data[99:84];
assign descriptor_error = snk_command_data[107:100];
assign descriptor_early_done_enable = snk_command_data[108];
assign sw_stop_in = snk_command_data[74];
assign sw_reset_in = snk_command_data[75];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
// swap the bytes if big endian is enabled
generate
if (BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign MM_to_ST_adapter_dataout_rearranged[j +8 -1: j] = MM_to_ST_adapter_dataout[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
end
end
else
begin
assign MM_to_ST_adapter_dataout_rearranged = MM_to_ST_adapter_dataout;
end
endgenerate
assign masked_sop = MM_to_ST_adapter_sop & generate_sop_d1;
assign masked_eop = MM_to_ST_adapter_eop & generate_eop_d1;
assign fifo_write_data = {error_d1, channel_d1, masked_sop, masked_eop, ((masked_eop == 1)? MM_to_ST_adapter_empty : {NUMBER_OF_SYMBOLS_LOG2{1'b0}} ), MM_to_ST_adapter_dataout_rearranged};
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before sending them to the data stream
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign src_data[i +SYMBOL_WIDTH -1: i] = fifo_read_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
assign src_empty = (PACKET_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 - 1) : DATA_WIDTH] : 0;
assign src_eop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2] : 0;
assign src_sop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 1] : 0;
assign src_channel = (CHANNEL_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 1): (DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2)] : 0;
assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 2)] : 0;
assign short_first_access_size = BYTE_ENABLE_WIDTH - (address_counter & LSB_MASK);
assign short_last_access_size = length_counter & LSB_MASK;
assign short_first_and_last_access_size = length_counter & LSB_MASK;
/* special case transfer enables and counter increment values (address and length counter)
short_first_access_enable is for transfers that start unaligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (aligned or unaligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
assign short_first_access_enable = ((address_counter & LSB_MASK) != 0) & (first_access == 1) & (first_word_boundary_not_reached_d1 == 0);
assign short_last_access_enable = (first_access == 0) & (length_counter < BYTE_ENABLE_WIDTH);
assign short_first_and_last_access_enable = (first_access == 1) & (first_word_boundary_not_reached_d1 == 1);
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH * master_burstcount;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = length_counter < BYTE_ENABLE_WIDTH; // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
endgenerate
// the burst count will be 1 for all short accesses
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size or master_burstcount)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size;
3'b010: bytes_to_transfer_mux = short_last_access_size;
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH * master_burstcount; // this is the only time master_burstcount can be a value other than 1
endcase
end
always @ (master_readdatavalid or read_complete or pending_reads_counter or master_burstcount)
begin
case ({master_readdatavalid, read_complete})
2'b00: pending_reads_mux = pending_reads_counter; // no read posted and no read data returned
2'b01: pending_reads_mux = (pending_reads_counter + master_burstcount); // read posted and no read data returned
2'b10: pending_reads_mux = (pending_reads_counter - 1'b1); // no read posted but read data returned
2'b11: pending_reads_mux = (pending_reads_counter + master_burstcount - 1'b1); // read posted and read data returned
endcase
end
assign src_valid = (fifo_empty == 0);
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign done = (length_counter == 0); // all reads are posted but the master is not done since there could be reads pending
assign done_strobe = (done == 1) & (done_d1 == 0);
assign fifo_read = (src_valid == 1) & (src_ready == 1);
assign length_sync_reset = (flush == 1) & (pending_reads_counter == 0); // resetting the length counter will trigger the done condition
assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count << 1))); // making sure a full burst can be posted, using 2x maximum_burst_count since the read signal is pipelined and so this signal will be late using maximum_burst_count alone
assign read_complete = (master_read == 1) & (master_waitrequest == 0);
assign address_increment_enable = read_complete;
assign master_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // master always asserts all byte enables and filters the data as it comes in (may lead to destructive reads in some cases)
generate if (DATA_WIDTH > 8)
begin
assign master_address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign master_address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign master_read = master_read_reg & (done == 0); // need to mask the read with done so that it doesn't issue one extra read at the end
assign all_reads_returned = (done == 1) & (pending_reads_counter == 0);
assign all_reads_returned_strobe = (all_reads_returned == 1) & (all_reads_returned_d1 == 0);
// for now the done and early done strobes are the same. Both will be triggered when the last data returns
generate
if (UNALIGNED_ACCESSES_ENABLE == 1) // need to use the delayed strobe since there are two stages of pipelining in the MM to ST adapter
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe_d2, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
else
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
endgenerate
assign set_src_response_valid = (UNALIGNED_ACCESSES_ENABLE == 1)? all_reads_returned_strobe_d2 : // all the reads have returned with MM to ST adapter latency taken into consideration
(early_done_enable_d1 == 1)? done_strobe : all_reads_returned_strobe; // when early done is enabled then the done strobe is sufficient to trigger the next command can enter, otherwise need to wait for the pending reads to return
/****************************** END CONTROL AND COMBINATIONAL SIGNALS *************************************/
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/17/2010
Version 2.7
This read master module is responsible for reading data from memory and writing
the contents out to a streaming source port. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as the state of the master (reset/stop) is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming
2.1 Fixed bugs in the control logic which was causing too many reads to be posted
2.2 Added burst support and renamed the top level module to read master
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Added early done support for non unaligned or non packet based transfers
2.6 Fixed a flow control issue in the pending reads counter and too many reads pending
signal to avoid potential FIFO overflow issues. The read master now requires the
FIFO depth to be 4x the maximum burst count setting.
2.7 Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
src_data,
src_valid,
src_ready,
src_sop,
src_eop,
src_empty,
src_error,
src_channel,
// data path master port
master_address,
master_read,
master_byteenable,
master_readdata,
master_waitrequest,
master_readdatavalid,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter CHANNEL_ENABLE = 0;
parameter CHANNEL_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when the channel enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0; // when enabled stride must be disabled, 1 to enable, 0 to disable
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set maximum_burst_count to 1 (will be automatically done by .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(maximum_burst_count) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value "maximum_burst_count" will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
// when packet data is supported then we need to buffer the empty, eop, sop, error, and channel bits
localparam FIFO_WIDTH = DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2 + ERROR_WIDTH + CHANNEL_WIDTH;
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // default stride distance used when stride is disabled. 1 means increment the address by a word (i.e. sequential transfer)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path source port
output wire [DATA_WIDTH-1:0] src_data;
output wire src_valid;
input src_ready;
output wire src_sop;
output wire src_eop;
output wire [NUMBER_OF_SYMBOLS_LOG2-1:0] src_empty;
output wire [ERROR_WIDTH-1:0] src_error;
output wire [CHANNEL_WIDTH-1:0] src_channel;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_read;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
input [DATA_WIDTH-1:0] master_readdata;
input master_readdatavalid;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal signals
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire [7:0] descriptor_channel;
wire descriptor_generate_sop;
wire descriptor_generate_eop;
wire [7:0] descriptor_error;
wire [7:0] descriptor_programmable_burst_count;
wire descriptor_early_done_enable;
wire sw_stop_in;
wire sw_reset_in;
reg early_done_enable_d1;
reg [ERROR_WIDTH-1:0] error_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg generate_sop_d1;
reg generate_eop_d1;
reg [ADDRESS_WIDTH-1:0] address_counter;
reg [LENGTH_WIDTH-1:0] length_counter;
reg [CHANNEL_WIDTH-1:0] channel_d1;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignment the master starts
reg first_access; // used to determine if the first read is occuring
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
reg [FIFO_DEPTH_LOG2:0] pending_reads_counter;
reg [FIFO_DEPTH_LOG2:0] pending_reads_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire too_many_pending_reads;
wire read_complete; // handy signal for determining when a read has occured and completed
wire address_increment_enable;
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire go;
wire done; // asserted when last read is issued
reg done_d1;
wire done_strobe;
wire all_reads_returned; // asserted when last read returns
reg all_reads_returned_d1;
wire all_reads_returned_strobe;
reg all_reads_returned_strobe_d1;
reg all_reads_returned_strobe_d2; // used to trigger src_response_ready later than when the last read returns since the MM to ST has two pipeline stages
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout;
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout_rearranged;
wire MM_to_ST_adapter_sop;
wire MM_to_ST_adapter_eop;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] MM_to_ST_adapter_empty;
wire masked_sop;
wire masked_eop;
reg flush;
reg stopped;
wire length_sync_reset;
wire set_src_response_valid;
reg master_read_reg;
/********************************************* REGISTERS **************************************************/
// registering descriptor information
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error_d1 <= 0;
generate_sop_d1 <= 0;
generate_eop_d1 <= 0;
channel_d1 <= 0;
stride_d1 <= 0;
programmable_burst_count_d1 <= 0;
early_done_enable_d1 <= 0;
end
else if (go == 1)
begin
error_d1 <= descriptor_error[ERROR_WIDTH-1:0];
generate_sop_d1 <= descriptor_generate_sop;
generate_eop_d1 <= descriptor_generate_eop;
channel_d1 <= descriptor_channel[CHANNEL_WIDTH-1:0];
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
early_done_enable_d1 <= ((UNALIGNED_ACCESSES_ENABLE == 1) | (PACKET_ENABLE == 1))? 0 : descriptor_early_done_enable; // early done cannot be used when unaligned data or packet support is enabled
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first read of a transaction, this will be used to determine what value will be used to increment the counters
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (address_increment_enable == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1)
begin
length_counter <= 0;
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// the pending reads counter is used to determine how many outstanding reads are posted. This will be used to determine
// if more reads can be posted based on the number of unused words in the FIFO.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
pending_reads_counter <= 0;
end
else
begin
pending_reads_counter <= pending_reads_mux;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // master is done coming out of reset (need this to be set high so that done_strobe doesn't fire)
end
else
begin
done_d1 <= done;
end
end
// this is the 'final done' condition, since reads are pipelined need to make sure they have all returned before the master is really done.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_d1 <= 1;
end
else
begin
all_reads_returned_d1 <= all_reads_returned;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
flush <= 0;
end
else
begin
if ((pending_reads_counter == 0) & (flush == 1))
begin
flush <= 0;
end
else if ((sw_reset_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
flush <= 1; // will be used to reset the length counter to 0 and flush out pending reads (by letting them return without buffering them)
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (sw_reset_in == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if ((src_response_ready == 1) & (src_response_valid == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_strobe_d1 <= 0;
all_reads_returned_strobe_d2 <= 0;
end
else
begin
all_reads_returned_strobe_d1 <= all_reads_returned_strobe;
all_reads_returned_strobe_d2 <= all_reads_returned_strobe_d1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (flush == 1)
begin
src_response_valid <= 0;
end
else if (set_src_response_valid == 1) // all the reads have returned with MM to ST adapter latency taken into consideration
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
master_read_reg <= 0;
end
else
begin
if ((done == 0) & (too_many_pending_reads == 0) & (sw_stop_in == 0) & (sw_reset_in == 0))
begin
master_read_reg <= 1;
end
else if ((done == 1) | ((read_complete == 1) & ((too_many_pending_reads == 1) | (sw_stop_in == 1))))
begin
master_read_reg <= 0;
end
end
end
/******************************************* END REGISTERS ************************************************/
/************************************** MODULE INSTANTIATIONS *********************************************/
// This block is pipelined and can't throttle the reads
MM_to_ST_Adapter the_MM_to_ST_adapter (
.clk (clk),
.reset (reset),
.length (descriptor_length[LENGTH_WIDTH-1:0]),
.length_counter (length_counter),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.reads_pending (pending_reads_counter),
.start (go),
.readdata (master_readdata),
.readdatavalid (master_readdatavalid),
.fifo_data (MM_to_ST_adapter_dataout),
.fifo_write (fifo_write),
.fifo_empty (MM_to_ST_adapter_empty),
.fifo_sop (MM_to_ST_adapter_sop),
.fifo_eop (MM_to_ST_adapter_eop)
);
defparam the_MM_to_ST_adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_MM_to_ST_adapter.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_MM_to_ST_adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_MM_to_ST_adapter.BYTE_ADDRESS_WIDTH = BYTE_ENABLE_WIDTH_LOG2;
defparam the_MM_to_ST_adapter.READS_PENDING_WIDTH = FIFO_DEPTH_LOG2 + 1;
defparam the_MM_to_ST_adapter.EMPTY_WIDTH = NUMBER_OF_SYMBOLS_LOG2;
defparam the_MM_to_ST_adapter.PACKET_SUPPORT = PACKET_ENABLE;
defparam the_MM_to_ST_adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
defparam the_MM_to_ST_adapter.FULL_WORD_ACCESS_ONLY = ONLY_FULL_ACCESS_ENABLE;
// buffered sop, eop, empty, data (in that order). sop, eop, and empty are only buffered when packet support is enabled
scfifo the_master_to_st_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used),
.q (fifo_read_data),
.rdreq (fifo_read),
.wrreq (fifo_write)
);
defparam the_master_to_st_fifo.lpm_width = FIFO_WIDTH;
defparam the_master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_master_to_st_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_master_to_st_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.underflow_checking = "OFF";
defparam the_master_to_st_fifo.overflow_checking = "OFF";
// burst block that takes the length and short access enables and forms a burst count based on them. If any of the short access bits are asserted the block will default to a burst count of 1
read_burst_control the_read_burst_control (
.address (master_address),
.length (length_counter),
.maximum_burst_count (maximum_burst_count),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.burst_count (master_burstcount)
);
defparam the_read_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_read_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_read_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_read_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_read_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_read_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/************************************ END MODULE INSTANTIATIONS *******************************************/
/******************************** CONTROL AND COMBINATIONAL SIGNALS ***************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[140:109], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_channel = snk_command_data[71:64];
assign descriptor_generate_sop = snk_command_data[72];
assign descriptor_generate_eop = snk_command_data[73];
assign descriptor_programmable_burst_count = snk_command_data[83:76];
assign descriptor_stride = snk_command_data[99:84];
assign descriptor_error = snk_command_data[107:100];
assign descriptor_early_done_enable = snk_command_data[108];
assign sw_stop_in = snk_command_data[74];
assign sw_reset_in = snk_command_data[75];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
// swap the bytes if big endian is enabled
generate
if (BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign MM_to_ST_adapter_dataout_rearranged[j +8 -1: j] = MM_to_ST_adapter_dataout[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
end
end
else
begin
assign MM_to_ST_adapter_dataout_rearranged = MM_to_ST_adapter_dataout;
end
endgenerate
assign masked_sop = MM_to_ST_adapter_sop & generate_sop_d1;
assign masked_eop = MM_to_ST_adapter_eop & generate_eop_d1;
assign fifo_write_data = {error_d1, channel_d1, masked_sop, masked_eop, ((masked_eop == 1)? MM_to_ST_adapter_empty : {NUMBER_OF_SYMBOLS_LOG2{1'b0}} ), MM_to_ST_adapter_dataout_rearranged};
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before sending them to the data stream
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign src_data[i +SYMBOL_WIDTH -1: i] = fifo_read_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
assign src_empty = (PACKET_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 - 1) : DATA_WIDTH] : 0;
assign src_eop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2] : 0;
assign src_sop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 1] : 0;
assign src_channel = (CHANNEL_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 1): (DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2)] : 0;
assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 2)] : 0;
assign short_first_access_size = BYTE_ENABLE_WIDTH - (address_counter & LSB_MASK);
assign short_last_access_size = length_counter & LSB_MASK;
assign short_first_and_last_access_size = length_counter & LSB_MASK;
/* special case transfer enables and counter increment values (address and length counter)
short_first_access_enable is for transfers that start unaligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (aligned or unaligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
assign short_first_access_enable = ((address_counter & LSB_MASK) != 0) & (first_access == 1) & (first_word_boundary_not_reached_d1 == 0);
assign short_last_access_enable = (first_access == 0) & (length_counter < BYTE_ENABLE_WIDTH);
assign short_first_and_last_access_enable = (first_access == 1) & (first_word_boundary_not_reached_d1 == 1);
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH * master_burstcount;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = length_counter < BYTE_ENABLE_WIDTH; // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
endgenerate
// the burst count will be 1 for all short accesses
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size or master_burstcount)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size;
3'b010: bytes_to_transfer_mux = short_last_access_size;
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH * master_burstcount; // this is the only time master_burstcount can be a value other than 1
endcase
end
always @ (master_readdatavalid or read_complete or pending_reads_counter or master_burstcount)
begin
case ({master_readdatavalid, read_complete})
2'b00: pending_reads_mux = pending_reads_counter; // no read posted and no read data returned
2'b01: pending_reads_mux = (pending_reads_counter + master_burstcount); // read posted and no read data returned
2'b10: pending_reads_mux = (pending_reads_counter - 1'b1); // no read posted but read data returned
2'b11: pending_reads_mux = (pending_reads_counter + master_burstcount - 1'b1); // read posted and read data returned
endcase
end
assign src_valid = (fifo_empty == 0);
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign done = (length_counter == 0); // all reads are posted but the master is not done since there could be reads pending
assign done_strobe = (done == 1) & (done_d1 == 0);
assign fifo_read = (src_valid == 1) & (src_ready == 1);
assign length_sync_reset = (flush == 1) & (pending_reads_counter == 0); // resetting the length counter will trigger the done condition
assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count << 1))); // making sure a full burst can be posted, using 2x maximum_burst_count since the read signal is pipelined and so this signal will be late using maximum_burst_count alone
assign read_complete = (master_read == 1) & (master_waitrequest == 0);
assign address_increment_enable = read_complete;
assign master_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // master always asserts all byte enables and filters the data as it comes in (may lead to destructive reads in some cases)
generate if (DATA_WIDTH > 8)
begin
assign master_address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign master_address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign master_read = master_read_reg & (done == 0); // need to mask the read with done so that it doesn't issue one extra read at the end
assign all_reads_returned = (done == 1) & (pending_reads_counter == 0);
assign all_reads_returned_strobe = (all_reads_returned == 1) & (all_reads_returned_d1 == 0);
// for now the done and early done strobes are the same. Both will be triggered when the last data returns
generate
if (UNALIGNED_ACCESSES_ENABLE == 1) // need to use the delayed strobe since there are two stages of pipelining in the MM to ST adapter
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe_d2, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
else
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
endgenerate
assign set_src_response_valid = (UNALIGNED_ACCESSES_ENABLE == 1)? all_reads_returned_strobe_d2 : // all the reads have returned with MM to ST adapter latency taken into consideration
(early_done_enable_d1 == 1)? done_strobe : all_reads_returned_strobe; // when early done is enabled then the done strobe is sufficient to trigger the next command can enter, otherwise need to wait for the pending reads to return
/****************************** END CONTROL AND COMBINATIONAL SIGNALS *************************************/
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/17/2010
Version 2.7
This read master module is responsible for reading data from memory and writing
the contents out to a streaming source port. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as the state of the master (reset/stop) is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming
2.1 Fixed bugs in the control logic which was causing too many reads to be posted
2.2 Added burst support and renamed the top level module to read master
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Added early done support for non unaligned or non packet based transfers
2.6 Fixed a flow control issue in the pending reads counter and too many reads pending
signal to avoid potential FIFO overflow issues. The read master now requires the
FIFO depth to be 4x the maximum burst count setting.
2.7 Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
src_data,
src_valid,
src_ready,
src_sop,
src_eop,
src_empty,
src_error,
src_channel,
// data path master port
master_address,
master_read,
master_byteenable,
master_readdata,
master_waitrequest,
master_readdatavalid,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter CHANNEL_ENABLE = 0;
parameter CHANNEL_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when the channel enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0; // when enabled stride must be disabled, 1 to enable, 0 to disable
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set maximum_burst_count to 1 (will be automatically done by .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(maximum_burst_count) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value "maximum_burst_count" will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
// when packet data is supported then we need to buffer the empty, eop, sop, error, and channel bits
localparam FIFO_WIDTH = DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2 + ERROR_WIDTH + CHANNEL_WIDTH;
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // default stride distance used when stride is disabled. 1 means increment the address by a word (i.e. sequential transfer)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path source port
output wire [DATA_WIDTH-1:0] src_data;
output wire src_valid;
input src_ready;
output wire src_sop;
output wire src_eop;
output wire [NUMBER_OF_SYMBOLS_LOG2-1:0] src_empty;
output wire [ERROR_WIDTH-1:0] src_error;
output wire [CHANNEL_WIDTH-1:0] src_channel;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_read;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
input [DATA_WIDTH-1:0] master_readdata;
input master_readdatavalid;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal signals
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire [7:0] descriptor_channel;
wire descriptor_generate_sop;
wire descriptor_generate_eop;
wire [7:0] descriptor_error;
wire [7:0] descriptor_programmable_burst_count;
wire descriptor_early_done_enable;
wire sw_stop_in;
wire sw_reset_in;
reg early_done_enable_d1;
reg [ERROR_WIDTH-1:0] error_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg generate_sop_d1;
reg generate_eop_d1;
reg [ADDRESS_WIDTH-1:0] address_counter;
reg [LENGTH_WIDTH-1:0] length_counter;
reg [CHANNEL_WIDTH-1:0] channel_d1;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignment the master starts
reg first_access; // used to determine if the first read is occuring
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
reg [FIFO_DEPTH_LOG2:0] pending_reads_counter;
reg [FIFO_DEPTH_LOG2:0] pending_reads_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire too_many_pending_reads;
wire read_complete; // handy signal for determining when a read has occured and completed
wire address_increment_enable;
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire go;
wire done; // asserted when last read is issued
reg done_d1;
wire done_strobe;
wire all_reads_returned; // asserted when last read returns
reg all_reads_returned_d1;
wire all_reads_returned_strobe;
reg all_reads_returned_strobe_d1;
reg all_reads_returned_strobe_d2; // used to trigger src_response_ready later than when the last read returns since the MM to ST has two pipeline stages
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout;
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout_rearranged;
wire MM_to_ST_adapter_sop;
wire MM_to_ST_adapter_eop;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] MM_to_ST_adapter_empty;
wire masked_sop;
wire masked_eop;
reg flush;
reg stopped;
wire length_sync_reset;
wire set_src_response_valid;
reg master_read_reg;
/********************************************* REGISTERS **************************************************/
// registering descriptor information
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error_d1 <= 0;
generate_sop_d1 <= 0;
generate_eop_d1 <= 0;
channel_d1 <= 0;
stride_d1 <= 0;
programmable_burst_count_d1 <= 0;
early_done_enable_d1 <= 0;
end
else if (go == 1)
begin
error_d1 <= descriptor_error[ERROR_WIDTH-1:0];
generate_sop_d1 <= descriptor_generate_sop;
generate_eop_d1 <= descriptor_generate_eop;
channel_d1 <= descriptor_channel[CHANNEL_WIDTH-1:0];
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
early_done_enable_d1 <= ((UNALIGNED_ACCESSES_ENABLE == 1) | (PACKET_ENABLE == 1))? 0 : descriptor_early_done_enable; // early done cannot be used when unaligned data or packet support is enabled
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first read of a transaction, this will be used to determine what value will be used to increment the counters
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (address_increment_enable == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1)
begin
length_counter <= 0;
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// the pending reads counter is used to determine how many outstanding reads are posted. This will be used to determine
// if more reads can be posted based on the number of unused words in the FIFO.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
pending_reads_counter <= 0;
end
else
begin
pending_reads_counter <= pending_reads_mux;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // master is done coming out of reset (need this to be set high so that done_strobe doesn't fire)
end
else
begin
done_d1 <= done;
end
end
// this is the 'final done' condition, since reads are pipelined need to make sure they have all returned before the master is really done.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_d1 <= 1;
end
else
begin
all_reads_returned_d1 <= all_reads_returned;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
flush <= 0;
end
else
begin
if ((pending_reads_counter == 0) & (flush == 1))
begin
flush <= 0;
end
else if ((sw_reset_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
flush <= 1; // will be used to reset the length counter to 0 and flush out pending reads (by letting them return without buffering them)
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (sw_reset_in == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if ((src_response_ready == 1) & (src_response_valid == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_strobe_d1 <= 0;
all_reads_returned_strobe_d2 <= 0;
end
else
begin
all_reads_returned_strobe_d1 <= all_reads_returned_strobe;
all_reads_returned_strobe_d2 <= all_reads_returned_strobe_d1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (flush == 1)
begin
src_response_valid <= 0;
end
else if (set_src_response_valid == 1) // all the reads have returned with MM to ST adapter latency taken into consideration
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
master_read_reg <= 0;
end
else
begin
if ((done == 0) & (too_many_pending_reads == 0) & (sw_stop_in == 0) & (sw_reset_in == 0))
begin
master_read_reg <= 1;
end
else if ((done == 1) | ((read_complete == 1) & ((too_many_pending_reads == 1) | (sw_stop_in == 1))))
begin
master_read_reg <= 0;
end
end
end
/******************************************* END REGISTERS ************************************************/
/************************************** MODULE INSTANTIATIONS *********************************************/
// This block is pipelined and can't throttle the reads
MM_to_ST_Adapter the_MM_to_ST_adapter (
.clk (clk),
.reset (reset),
.length (descriptor_length[LENGTH_WIDTH-1:0]),
.length_counter (length_counter),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.reads_pending (pending_reads_counter),
.start (go),
.readdata (master_readdata),
.readdatavalid (master_readdatavalid),
.fifo_data (MM_to_ST_adapter_dataout),
.fifo_write (fifo_write),
.fifo_empty (MM_to_ST_adapter_empty),
.fifo_sop (MM_to_ST_adapter_sop),
.fifo_eop (MM_to_ST_adapter_eop)
);
defparam the_MM_to_ST_adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_MM_to_ST_adapter.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_MM_to_ST_adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_MM_to_ST_adapter.BYTE_ADDRESS_WIDTH = BYTE_ENABLE_WIDTH_LOG2;
defparam the_MM_to_ST_adapter.READS_PENDING_WIDTH = FIFO_DEPTH_LOG2 + 1;
defparam the_MM_to_ST_adapter.EMPTY_WIDTH = NUMBER_OF_SYMBOLS_LOG2;
defparam the_MM_to_ST_adapter.PACKET_SUPPORT = PACKET_ENABLE;
defparam the_MM_to_ST_adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
defparam the_MM_to_ST_adapter.FULL_WORD_ACCESS_ONLY = ONLY_FULL_ACCESS_ENABLE;
// buffered sop, eop, empty, data (in that order). sop, eop, and empty are only buffered when packet support is enabled
scfifo the_master_to_st_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used),
.q (fifo_read_data),
.rdreq (fifo_read),
.wrreq (fifo_write)
);
defparam the_master_to_st_fifo.lpm_width = FIFO_WIDTH;
defparam the_master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_master_to_st_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_master_to_st_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.underflow_checking = "OFF";
defparam the_master_to_st_fifo.overflow_checking = "OFF";
// burst block that takes the length and short access enables and forms a burst count based on them. If any of the short access bits are asserted the block will default to a burst count of 1
read_burst_control the_read_burst_control (
.address (master_address),
.length (length_counter),
.maximum_burst_count (maximum_burst_count),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.burst_count (master_burstcount)
);
defparam the_read_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_read_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_read_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_read_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_read_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_read_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/************************************ END MODULE INSTANTIATIONS *******************************************/
/******************************** CONTROL AND COMBINATIONAL SIGNALS ***************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[140:109], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_channel = snk_command_data[71:64];
assign descriptor_generate_sop = snk_command_data[72];
assign descriptor_generate_eop = snk_command_data[73];
assign descriptor_programmable_burst_count = snk_command_data[83:76];
assign descriptor_stride = snk_command_data[99:84];
assign descriptor_error = snk_command_data[107:100];
assign descriptor_early_done_enable = snk_command_data[108];
assign sw_stop_in = snk_command_data[74];
assign sw_reset_in = snk_command_data[75];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
// swap the bytes if big endian is enabled
generate
if (BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign MM_to_ST_adapter_dataout_rearranged[j +8 -1: j] = MM_to_ST_adapter_dataout[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
end
end
else
begin
assign MM_to_ST_adapter_dataout_rearranged = MM_to_ST_adapter_dataout;
end
endgenerate
assign masked_sop = MM_to_ST_adapter_sop & generate_sop_d1;
assign masked_eop = MM_to_ST_adapter_eop & generate_eop_d1;
assign fifo_write_data = {error_d1, channel_d1, masked_sop, masked_eop, ((masked_eop == 1)? MM_to_ST_adapter_empty : {NUMBER_OF_SYMBOLS_LOG2{1'b0}} ), MM_to_ST_adapter_dataout_rearranged};
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before sending them to the data stream
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign src_data[i +SYMBOL_WIDTH -1: i] = fifo_read_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
assign src_empty = (PACKET_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 - 1) : DATA_WIDTH] : 0;
assign src_eop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2] : 0;
assign src_sop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 1] : 0;
assign src_channel = (CHANNEL_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 1): (DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2)] : 0;
assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 2)] : 0;
assign short_first_access_size = BYTE_ENABLE_WIDTH - (address_counter & LSB_MASK);
assign short_last_access_size = length_counter & LSB_MASK;
assign short_first_and_last_access_size = length_counter & LSB_MASK;
/* special case transfer enables and counter increment values (address and length counter)
short_first_access_enable is for transfers that start unaligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (aligned or unaligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
assign short_first_access_enable = ((address_counter & LSB_MASK) != 0) & (first_access == 1) & (first_word_boundary_not_reached_d1 == 0);
assign short_last_access_enable = (first_access == 0) & (length_counter < BYTE_ENABLE_WIDTH);
assign short_first_and_last_access_enable = (first_access == 1) & (first_word_boundary_not_reached_d1 == 1);
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH * master_burstcount;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = length_counter < BYTE_ENABLE_WIDTH; // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
endgenerate
// the burst count will be 1 for all short accesses
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size or master_burstcount)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size;
3'b010: bytes_to_transfer_mux = short_last_access_size;
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH * master_burstcount; // this is the only time master_burstcount can be a value other than 1
endcase
end
always @ (master_readdatavalid or read_complete or pending_reads_counter or master_burstcount)
begin
case ({master_readdatavalid, read_complete})
2'b00: pending_reads_mux = pending_reads_counter; // no read posted and no read data returned
2'b01: pending_reads_mux = (pending_reads_counter + master_burstcount); // read posted and no read data returned
2'b10: pending_reads_mux = (pending_reads_counter - 1'b1); // no read posted but read data returned
2'b11: pending_reads_mux = (pending_reads_counter + master_burstcount - 1'b1); // read posted and read data returned
endcase
end
assign src_valid = (fifo_empty == 0);
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign done = (length_counter == 0); // all reads are posted but the master is not done since there could be reads pending
assign done_strobe = (done == 1) & (done_d1 == 0);
assign fifo_read = (src_valid == 1) & (src_ready == 1);
assign length_sync_reset = (flush == 1) & (pending_reads_counter == 0); // resetting the length counter will trigger the done condition
assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count << 1))); // making sure a full burst can be posted, using 2x maximum_burst_count since the read signal is pipelined and so this signal will be late using maximum_burst_count alone
assign read_complete = (master_read == 1) & (master_waitrequest == 0);
assign address_increment_enable = read_complete;
assign master_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // master always asserts all byte enables and filters the data as it comes in (may lead to destructive reads in some cases)
generate if (DATA_WIDTH > 8)
begin
assign master_address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign master_address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign master_read = master_read_reg & (done == 0); // need to mask the read with done so that it doesn't issue one extra read at the end
assign all_reads_returned = (done == 1) & (pending_reads_counter == 0);
assign all_reads_returned_strobe = (all_reads_returned == 1) & (all_reads_returned_d1 == 0);
// for now the done and early done strobes are the same. Both will be triggered when the last data returns
generate
if (UNALIGNED_ACCESSES_ENABLE == 1) // need to use the delayed strobe since there are two stages of pipelining in the MM to ST adapter
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe_d2, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
else
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
endgenerate
assign set_src_response_valid = (UNALIGNED_ACCESSES_ENABLE == 1)? all_reads_returned_strobe_d2 : // all the reads have returned with MM to ST adapter latency taken into consideration
(early_done_enable_d1 == 1)? done_strobe : all_reads_returned_strobe; // when early done is enabled then the done strobe is sufficient to trigger the next command can enter, otherwise need to wait for the pending reads to return
/****************************** END CONTROL AND COMBINATIONAL SIGNALS *************************************/
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/17/2010
Version 2.7
This read master module is responsible for reading data from memory and writing
the contents out to a streaming source port. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as the state of the master (reset/stop) is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming
2.1 Fixed bugs in the control logic which was causing too many reads to be posted
2.2 Added burst support and renamed the top level module to read master
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Added early done support for non unaligned or non packet based transfers
2.6 Fixed a flow control issue in the pending reads counter and too many reads pending
signal to avoid potential FIFO overflow issues. The read master now requires the
FIFO depth to be 4x the maximum burst count setting.
2.7 Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
src_data,
src_valid,
src_ready,
src_sop,
src_eop,
src_empty,
src_error,
src_channel,
// data path master port
master_address,
master_read,
master_byteenable,
master_readdata,
master_waitrequest,
master_readdatavalid,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter CHANNEL_ENABLE = 0;
parameter CHANNEL_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when the channel enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0; // when enabled stride must be disabled, 1 to enable, 0 to disable
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set maximum_burst_count to 1 (will be automatically done by .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(maximum_burst_count) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value "maximum_burst_count" will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
// when packet data is supported then we need to buffer the empty, eop, sop, error, and channel bits
localparam FIFO_WIDTH = DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2 + ERROR_WIDTH + CHANNEL_WIDTH;
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // default stride distance used when stride is disabled. 1 means increment the address by a word (i.e. sequential transfer)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path source port
output wire [DATA_WIDTH-1:0] src_data;
output wire src_valid;
input src_ready;
output wire src_sop;
output wire src_eop;
output wire [NUMBER_OF_SYMBOLS_LOG2-1:0] src_empty;
output wire [ERROR_WIDTH-1:0] src_error;
output wire [CHANNEL_WIDTH-1:0] src_channel;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_read;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
input [DATA_WIDTH-1:0] master_readdata;
input master_readdatavalid;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal signals
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire [7:0] descriptor_channel;
wire descriptor_generate_sop;
wire descriptor_generate_eop;
wire [7:0] descriptor_error;
wire [7:0] descriptor_programmable_burst_count;
wire descriptor_early_done_enable;
wire sw_stop_in;
wire sw_reset_in;
reg early_done_enable_d1;
reg [ERROR_WIDTH-1:0] error_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg generate_sop_d1;
reg generate_eop_d1;
reg [ADDRESS_WIDTH-1:0] address_counter;
reg [LENGTH_WIDTH-1:0] length_counter;
reg [CHANNEL_WIDTH-1:0] channel_d1;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignment the master starts
reg first_access; // used to determine if the first read is occuring
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
reg [FIFO_DEPTH_LOG2:0] pending_reads_counter;
reg [FIFO_DEPTH_LOG2:0] pending_reads_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire too_many_pending_reads;
wire read_complete; // handy signal for determining when a read has occured and completed
wire address_increment_enable;
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire go;
wire done; // asserted when last read is issued
reg done_d1;
wire done_strobe;
wire all_reads_returned; // asserted when last read returns
reg all_reads_returned_d1;
wire all_reads_returned_strobe;
reg all_reads_returned_strobe_d1;
reg all_reads_returned_strobe_d2; // used to trigger src_response_ready later than when the last read returns since the MM to ST has two pipeline stages
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout;
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout_rearranged;
wire MM_to_ST_adapter_sop;
wire MM_to_ST_adapter_eop;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] MM_to_ST_adapter_empty;
wire masked_sop;
wire masked_eop;
reg flush;
reg stopped;
wire length_sync_reset;
wire set_src_response_valid;
reg master_read_reg;
/********************************************* REGISTERS **************************************************/
// registering descriptor information
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error_d1 <= 0;
generate_sop_d1 <= 0;
generate_eop_d1 <= 0;
channel_d1 <= 0;
stride_d1 <= 0;
programmable_burst_count_d1 <= 0;
early_done_enable_d1 <= 0;
end
else if (go == 1)
begin
error_d1 <= descriptor_error[ERROR_WIDTH-1:0];
generate_sop_d1 <= descriptor_generate_sop;
generate_eop_d1 <= descriptor_generate_eop;
channel_d1 <= descriptor_channel[CHANNEL_WIDTH-1:0];
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
early_done_enable_d1 <= ((UNALIGNED_ACCESSES_ENABLE == 1) | (PACKET_ENABLE == 1))? 0 : descriptor_early_done_enable; // early done cannot be used when unaligned data or packet support is enabled
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first read of a transaction, this will be used to determine what value will be used to increment the counters
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (address_increment_enable == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1)
begin
length_counter <= 0;
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// the pending reads counter is used to determine how many outstanding reads are posted. This will be used to determine
// if more reads can be posted based on the number of unused words in the FIFO.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
pending_reads_counter <= 0;
end
else
begin
pending_reads_counter <= pending_reads_mux;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // master is done coming out of reset (need this to be set high so that done_strobe doesn't fire)
end
else
begin
done_d1 <= done;
end
end
// this is the 'final done' condition, since reads are pipelined need to make sure they have all returned before the master is really done.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_d1 <= 1;
end
else
begin
all_reads_returned_d1 <= all_reads_returned;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
flush <= 0;
end
else
begin
if ((pending_reads_counter == 0) & (flush == 1))
begin
flush <= 0;
end
else if ((sw_reset_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
flush <= 1; // will be used to reset the length counter to 0 and flush out pending reads (by letting them return without buffering them)
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (sw_reset_in == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if ((src_response_ready == 1) & (src_response_valid == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_strobe_d1 <= 0;
all_reads_returned_strobe_d2 <= 0;
end
else
begin
all_reads_returned_strobe_d1 <= all_reads_returned_strobe;
all_reads_returned_strobe_d2 <= all_reads_returned_strobe_d1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (flush == 1)
begin
src_response_valid <= 0;
end
else if (set_src_response_valid == 1) // all the reads have returned with MM to ST adapter latency taken into consideration
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
master_read_reg <= 0;
end
else
begin
if ((done == 0) & (too_many_pending_reads == 0) & (sw_stop_in == 0) & (sw_reset_in == 0))
begin
master_read_reg <= 1;
end
else if ((done == 1) | ((read_complete == 1) & ((too_many_pending_reads == 1) | (sw_stop_in == 1))))
begin
master_read_reg <= 0;
end
end
end
/******************************************* END REGISTERS ************************************************/
/************************************** MODULE INSTANTIATIONS *********************************************/
// This block is pipelined and can't throttle the reads
MM_to_ST_Adapter the_MM_to_ST_adapter (
.clk (clk),
.reset (reset),
.length (descriptor_length[LENGTH_WIDTH-1:0]),
.length_counter (length_counter),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.reads_pending (pending_reads_counter),
.start (go),
.readdata (master_readdata),
.readdatavalid (master_readdatavalid),
.fifo_data (MM_to_ST_adapter_dataout),
.fifo_write (fifo_write),
.fifo_empty (MM_to_ST_adapter_empty),
.fifo_sop (MM_to_ST_adapter_sop),
.fifo_eop (MM_to_ST_adapter_eop)
);
defparam the_MM_to_ST_adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_MM_to_ST_adapter.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_MM_to_ST_adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_MM_to_ST_adapter.BYTE_ADDRESS_WIDTH = BYTE_ENABLE_WIDTH_LOG2;
defparam the_MM_to_ST_adapter.READS_PENDING_WIDTH = FIFO_DEPTH_LOG2 + 1;
defparam the_MM_to_ST_adapter.EMPTY_WIDTH = NUMBER_OF_SYMBOLS_LOG2;
defparam the_MM_to_ST_adapter.PACKET_SUPPORT = PACKET_ENABLE;
defparam the_MM_to_ST_adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
defparam the_MM_to_ST_adapter.FULL_WORD_ACCESS_ONLY = ONLY_FULL_ACCESS_ENABLE;
// buffered sop, eop, empty, data (in that order). sop, eop, and empty are only buffered when packet support is enabled
scfifo the_master_to_st_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used),
.q (fifo_read_data),
.rdreq (fifo_read),
.wrreq (fifo_write)
);
defparam the_master_to_st_fifo.lpm_width = FIFO_WIDTH;
defparam the_master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_master_to_st_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_master_to_st_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.underflow_checking = "OFF";
defparam the_master_to_st_fifo.overflow_checking = "OFF";
// burst block that takes the length and short access enables and forms a burst count based on them. If any of the short access bits are asserted the block will default to a burst count of 1
read_burst_control the_read_burst_control (
.address (master_address),
.length (length_counter),
.maximum_burst_count (maximum_burst_count),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.burst_count (master_burstcount)
);
defparam the_read_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_read_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_read_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_read_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_read_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_read_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/************************************ END MODULE INSTANTIATIONS *******************************************/
/******************************** CONTROL AND COMBINATIONAL SIGNALS ***************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[140:109], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_channel = snk_command_data[71:64];
assign descriptor_generate_sop = snk_command_data[72];
assign descriptor_generate_eop = snk_command_data[73];
assign descriptor_programmable_burst_count = snk_command_data[83:76];
assign descriptor_stride = snk_command_data[99:84];
assign descriptor_error = snk_command_data[107:100];
assign descriptor_early_done_enable = snk_command_data[108];
assign sw_stop_in = snk_command_data[74];
assign sw_reset_in = snk_command_data[75];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
// swap the bytes if big endian is enabled
generate
if (BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign MM_to_ST_adapter_dataout_rearranged[j +8 -1: j] = MM_to_ST_adapter_dataout[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
end
end
else
begin
assign MM_to_ST_adapter_dataout_rearranged = MM_to_ST_adapter_dataout;
end
endgenerate
assign masked_sop = MM_to_ST_adapter_sop & generate_sop_d1;
assign masked_eop = MM_to_ST_adapter_eop & generate_eop_d1;
assign fifo_write_data = {error_d1, channel_d1, masked_sop, masked_eop, ((masked_eop == 1)? MM_to_ST_adapter_empty : {NUMBER_OF_SYMBOLS_LOG2{1'b0}} ), MM_to_ST_adapter_dataout_rearranged};
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before sending them to the data stream
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign src_data[i +SYMBOL_WIDTH -1: i] = fifo_read_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
assign src_empty = (PACKET_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 - 1) : DATA_WIDTH] : 0;
assign src_eop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2] : 0;
assign src_sop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 1] : 0;
assign src_channel = (CHANNEL_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 1): (DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2)] : 0;
assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 2)] : 0;
assign short_first_access_size = BYTE_ENABLE_WIDTH - (address_counter & LSB_MASK);
assign short_last_access_size = length_counter & LSB_MASK;
assign short_first_and_last_access_size = length_counter & LSB_MASK;
/* special case transfer enables and counter increment values (address and length counter)
short_first_access_enable is for transfers that start unaligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (aligned or unaligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
assign short_first_access_enable = ((address_counter & LSB_MASK) != 0) & (first_access == 1) & (first_word_boundary_not_reached_d1 == 0);
assign short_last_access_enable = (first_access == 0) & (length_counter < BYTE_ENABLE_WIDTH);
assign short_first_and_last_access_enable = (first_access == 1) & (first_word_boundary_not_reached_d1 == 1);
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH * master_burstcount;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = length_counter < BYTE_ENABLE_WIDTH; // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
endgenerate
// the burst count will be 1 for all short accesses
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size or master_burstcount)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size;
3'b010: bytes_to_transfer_mux = short_last_access_size;
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH * master_burstcount; // this is the only time master_burstcount can be a value other than 1
endcase
end
always @ (master_readdatavalid or read_complete or pending_reads_counter or master_burstcount)
begin
case ({master_readdatavalid, read_complete})
2'b00: pending_reads_mux = pending_reads_counter; // no read posted and no read data returned
2'b01: pending_reads_mux = (pending_reads_counter + master_burstcount); // read posted and no read data returned
2'b10: pending_reads_mux = (pending_reads_counter - 1'b1); // no read posted but read data returned
2'b11: pending_reads_mux = (pending_reads_counter + master_burstcount - 1'b1); // read posted and read data returned
endcase
end
assign src_valid = (fifo_empty == 0);
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign done = (length_counter == 0); // all reads are posted but the master is not done since there could be reads pending
assign done_strobe = (done == 1) & (done_d1 == 0);
assign fifo_read = (src_valid == 1) & (src_ready == 1);
assign length_sync_reset = (flush == 1) & (pending_reads_counter == 0); // resetting the length counter will trigger the done condition
assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count << 1))); // making sure a full burst can be posted, using 2x maximum_burst_count since the read signal is pipelined and so this signal will be late using maximum_burst_count alone
assign read_complete = (master_read == 1) & (master_waitrequest == 0);
assign address_increment_enable = read_complete;
assign master_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // master always asserts all byte enables and filters the data as it comes in (may lead to destructive reads in some cases)
generate if (DATA_WIDTH > 8)
begin
assign master_address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign master_address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign master_read = master_read_reg & (done == 0); // need to mask the read with done so that it doesn't issue one extra read at the end
assign all_reads_returned = (done == 1) & (pending_reads_counter == 0);
assign all_reads_returned_strobe = (all_reads_returned == 1) & (all_reads_returned_d1 == 0);
// for now the done and early done strobes are the same. Both will be triggered when the last data returns
generate
if (UNALIGNED_ACCESSES_ENABLE == 1) // need to use the delayed strobe since there are two stages of pipelining in the MM to ST adapter
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe_d2, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
else
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
endgenerate
assign set_src_response_valid = (UNALIGNED_ACCESSES_ENABLE == 1)? all_reads_returned_strobe_d2 : // all the reads have returned with MM to ST adapter latency taken into consideration
(early_done_enable_d1 == 1)? done_strobe : all_reads_returned_strobe; // when early done is enabled then the done strobe is sufficient to trigger the next command can enter, otherwise need to wait for the pending reads to return
/****************************** END CONTROL AND COMBINATIONAL SIGNALS *************************************/
endmodule
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule // rx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule // rx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule // rx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: sub32.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module sub32_add_sub_cqa
(
aclr,
clken,
clock,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [0:0] wire_add_sub_cella_11cout;
wire [0:0] wire_add_sub_cella_12cout;
wire [0:0] wire_add_sub_cella_13cout;
wire [0:0] wire_add_sub_cella_14cout;
wire [0:0] wire_add_sub_cella_15cout;
wire [0:0] wire_add_sub_cella_16cout;
wire [0:0] wire_add_sub_cella_17cout;
wire [0:0] wire_add_sub_cella_18cout;
wire [0:0] wire_add_sub_cella_19cout;
wire [0:0] wire_add_sub_cella_20cout;
wire [0:0] wire_add_sub_cella_21cout;
wire [0:0] wire_add_sub_cella_22cout;
wire [0:0] wire_add_sub_cella_23cout;
wire [0:0] wire_add_sub_cella_24cout;
wire [0:0] wire_add_sub_cella_25cout;
wire [0:0] wire_add_sub_cella_26cout;
wire [0:0] wire_add_sub_cella_27cout;
wire [0:0] wire_add_sub_cella_28cout;
wire [0:0] wire_add_sub_cella_29cout;
wire [0:0] wire_add_sub_cella_30cout;
wire [31:0] wire_add_sub_cella_dataa;
wire [31:0] wire_add_sub_cella_datab;
wire [31:0] wire_add_sub_cella_regout;
stratix_lcell add_sub_cella_0
(
.aclr(aclr),
.cin(1'b1),
.clk(clock),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.ena(clken),
.regout(wire_add_sub_cella_regout[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.aclr(aclr),
.cin(wire_add_sub_cella_0cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.ena(clken),
.regout(wire_add_sub_cella_regout[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.aclr(aclr),
.cin(wire_add_sub_cella_1cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.ena(clken),
.regout(wire_add_sub_cella_regout[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.aclr(aclr),
.cin(wire_add_sub_cella_2cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.ena(clken),
.regout(wire_add_sub_cella_regout[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.aclr(aclr),
.cin(wire_add_sub_cella_3cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.ena(clken),
.regout(wire_add_sub_cella_regout[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.aclr(aclr),
.cin(wire_add_sub_cella_4cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.ena(clken),
.regout(wire_add_sub_cella_regout[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.aclr(aclr),
.cin(wire_add_sub_cella_5cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.ena(clken),
.regout(wire_add_sub_cella_regout[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.aclr(aclr),
.cin(wire_add_sub_cella_6cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.ena(clken),
.regout(wire_add_sub_cella_regout[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_8
(
.aclr(aclr),
.cin(wire_add_sub_cella_7cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.ena(clken),
.regout(wire_add_sub_cella_regout[8:8]));
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_9
(
.aclr(aclr),
.cin(wire_add_sub_cella_8cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.ena(clken),
.regout(wire_add_sub_cella_regout[9:9]));
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_10
(
.aclr(aclr),
.cin(wire_add_sub_cella_9cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.ena(clken),
.regout(wire_add_sub_cella_regout[10:10]));
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_11
(
.aclr(aclr),
.cin(wire_add_sub_cella_10cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_11cout[0:0]),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.ena(clken),
.regout(wire_add_sub_cella_regout[11:11]));
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "69b2",
add_sub_cella_11.operation_mode = "arithmetic",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_12
(
.aclr(aclr),
.cin(wire_add_sub_cella_11cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_12cout[0:0]),
.dataa(wire_add_sub_cella_dataa[12:12]),
.datab(wire_add_sub_cella_datab[12:12]),
.ena(clken),
.regout(wire_add_sub_cella_regout[12:12]));
defparam
add_sub_cella_12.cin_used = "true",
add_sub_cella_12.lut_mask = "69b2",
add_sub_cella_12.operation_mode = "arithmetic",
add_sub_cella_12.sum_lutc_input = "cin",
add_sub_cella_12.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_13
(
.aclr(aclr),
.cin(wire_add_sub_cella_12cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_13cout[0:0]),
.dataa(wire_add_sub_cella_dataa[13:13]),
.datab(wire_add_sub_cella_datab[13:13]),
.ena(clken),
.regout(wire_add_sub_cella_regout[13:13]));
defparam
add_sub_cella_13.cin_used = "true",
add_sub_cella_13.lut_mask = "69b2",
add_sub_cella_13.operation_mode = "arithmetic",
add_sub_cella_13.sum_lutc_input = "cin",
add_sub_cella_13.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_14
(
.aclr(aclr),
.cin(wire_add_sub_cella_13cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_14cout[0:0]),
.dataa(wire_add_sub_cella_dataa[14:14]),
.datab(wire_add_sub_cella_datab[14:14]),
.ena(clken),
.regout(wire_add_sub_cella_regout[14:14]));
defparam
add_sub_cella_14.cin_used = "true",
add_sub_cella_14.lut_mask = "69b2",
add_sub_cella_14.operation_mode = "arithmetic",
add_sub_cella_14.sum_lutc_input = "cin",
add_sub_cella_14.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_15
(
.aclr(aclr),
.cin(wire_add_sub_cella_14cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_15cout[0:0]),
.dataa(wire_add_sub_cella_dataa[15:15]),
.datab(wire_add_sub_cella_datab[15:15]),
.ena(clken),
.regout(wire_add_sub_cella_regout[15:15]));
defparam
add_sub_cella_15.cin_used = "true",
add_sub_cella_15.lut_mask = "69b2",
add_sub_cella_15.operation_mode = "arithmetic",
add_sub_cella_15.sum_lutc_input = "cin",
add_sub_cella_15.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_16
(
.aclr(aclr),
.cin(wire_add_sub_cella_15cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_16cout[0:0]),
.dataa(wire_add_sub_cella_dataa[16:16]),
.datab(wire_add_sub_cella_datab[16:16]),
.ena(clken),
.regout(wire_add_sub_cella_regout[16:16]));
defparam
add_sub_cella_16.cin_used = "true",
add_sub_cella_16.lut_mask = "69b2",
add_sub_cella_16.operation_mode = "arithmetic",
add_sub_cella_16.sum_lutc_input = "cin",
add_sub_cella_16.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_17
(
.aclr(aclr),
.cin(wire_add_sub_cella_16cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_17cout[0:0]),
.dataa(wire_add_sub_cella_dataa[17:17]),
.datab(wire_add_sub_cella_datab[17:17]),
.ena(clken),
.regout(wire_add_sub_cella_regout[17:17]));
defparam
add_sub_cella_17.cin_used = "true",
add_sub_cella_17.lut_mask = "69b2",
add_sub_cella_17.operation_mode = "arithmetic",
add_sub_cella_17.sum_lutc_input = "cin",
add_sub_cella_17.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_18
(
.aclr(aclr),
.cin(wire_add_sub_cella_17cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_18cout[0:0]),
.dataa(wire_add_sub_cella_dataa[18:18]),
.datab(wire_add_sub_cella_datab[18:18]),
.ena(clken),
.regout(wire_add_sub_cella_regout[18:18]));
defparam
add_sub_cella_18.cin_used = "true",
add_sub_cella_18.lut_mask = "69b2",
add_sub_cella_18.operation_mode = "arithmetic",
add_sub_cella_18.sum_lutc_input = "cin",
add_sub_cella_18.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_19
(
.aclr(aclr),
.cin(wire_add_sub_cella_18cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_19cout[0:0]),
.dataa(wire_add_sub_cella_dataa[19:19]),
.datab(wire_add_sub_cella_datab[19:19]),
.ena(clken),
.regout(wire_add_sub_cella_regout[19:19]));
defparam
add_sub_cella_19.cin_used = "true",
add_sub_cella_19.lut_mask = "69b2",
add_sub_cella_19.operation_mode = "arithmetic",
add_sub_cella_19.sum_lutc_input = "cin",
add_sub_cella_19.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_20
(
.aclr(aclr),
.cin(wire_add_sub_cella_19cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_20cout[0:0]),
.dataa(wire_add_sub_cella_dataa[20:20]),
.datab(wire_add_sub_cella_datab[20:20]),
.ena(clken),
.regout(wire_add_sub_cella_regout[20:20]));
defparam
add_sub_cella_20.cin_used = "true",
add_sub_cella_20.lut_mask = "69b2",
add_sub_cella_20.operation_mode = "arithmetic",
add_sub_cella_20.sum_lutc_input = "cin",
add_sub_cella_20.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_21
(
.aclr(aclr),
.cin(wire_add_sub_cella_20cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_21cout[0:0]),
.dataa(wire_add_sub_cella_dataa[21:21]),
.datab(wire_add_sub_cella_datab[21:21]),
.ena(clken),
.regout(wire_add_sub_cella_regout[21:21]));
defparam
add_sub_cella_21.cin_used = "true",
add_sub_cella_21.lut_mask = "69b2",
add_sub_cella_21.operation_mode = "arithmetic",
add_sub_cella_21.sum_lutc_input = "cin",
add_sub_cella_21.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_22
(
.aclr(aclr),
.cin(wire_add_sub_cella_21cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_22cout[0:0]),
.dataa(wire_add_sub_cella_dataa[22:22]),
.datab(wire_add_sub_cella_datab[22:22]),
.ena(clken),
.regout(wire_add_sub_cella_regout[22:22]));
defparam
add_sub_cella_22.cin_used = "true",
add_sub_cella_22.lut_mask = "69b2",
add_sub_cella_22.operation_mode = "arithmetic",
add_sub_cella_22.sum_lutc_input = "cin",
add_sub_cella_22.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_23
(
.aclr(aclr),
.cin(wire_add_sub_cella_22cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_23cout[0:0]),
.dataa(wire_add_sub_cella_dataa[23:23]),
.datab(wire_add_sub_cella_datab[23:23]),
.ena(clken),
.regout(wire_add_sub_cella_regout[23:23]));
defparam
add_sub_cella_23.cin_used = "true",
add_sub_cella_23.lut_mask = "69b2",
add_sub_cella_23.operation_mode = "arithmetic",
add_sub_cella_23.sum_lutc_input = "cin",
add_sub_cella_23.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_24
(
.aclr(aclr),
.cin(wire_add_sub_cella_23cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_24cout[0:0]),
.dataa(wire_add_sub_cella_dataa[24:24]),
.datab(wire_add_sub_cella_datab[24:24]),
.ena(clken),
.regout(wire_add_sub_cella_regout[24:24]));
defparam
add_sub_cella_24.cin_used = "true",
add_sub_cella_24.lut_mask = "69b2",
add_sub_cella_24.operation_mode = "arithmetic",
add_sub_cella_24.sum_lutc_input = "cin",
add_sub_cella_24.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_25
(
.aclr(aclr),
.cin(wire_add_sub_cella_24cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_25cout[0:0]),
.dataa(wire_add_sub_cella_dataa[25:25]),
.datab(wire_add_sub_cella_datab[25:25]),
.ena(clken),
.regout(wire_add_sub_cella_regout[25:25]));
defparam
add_sub_cella_25.cin_used = "true",
add_sub_cella_25.lut_mask = "69b2",
add_sub_cella_25.operation_mode = "arithmetic",
add_sub_cella_25.sum_lutc_input = "cin",
add_sub_cella_25.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_26
(
.aclr(aclr),
.cin(wire_add_sub_cella_25cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_26cout[0:0]),
.dataa(wire_add_sub_cella_dataa[26:26]),
.datab(wire_add_sub_cella_datab[26:26]),
.ena(clken),
.regout(wire_add_sub_cella_regout[26:26]));
defparam
add_sub_cella_26.cin_used = "true",
add_sub_cella_26.lut_mask = "69b2",
add_sub_cella_26.operation_mode = "arithmetic",
add_sub_cella_26.sum_lutc_input = "cin",
add_sub_cella_26.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_27
(
.aclr(aclr),
.cin(wire_add_sub_cella_26cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_27cout[0:0]),
.dataa(wire_add_sub_cella_dataa[27:27]),
.datab(wire_add_sub_cella_datab[27:27]),
.ena(clken),
.regout(wire_add_sub_cella_regout[27:27]));
defparam
add_sub_cella_27.cin_used = "true",
add_sub_cella_27.lut_mask = "69b2",
add_sub_cella_27.operation_mode = "arithmetic",
add_sub_cella_27.sum_lutc_input = "cin",
add_sub_cella_27.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_28
(
.aclr(aclr),
.cin(wire_add_sub_cella_27cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_28cout[0:0]),
.dataa(wire_add_sub_cella_dataa[28:28]),
.datab(wire_add_sub_cella_datab[28:28]),
.ena(clken),
.regout(wire_add_sub_cella_regout[28:28]));
defparam
add_sub_cella_28.cin_used = "true",
add_sub_cella_28.lut_mask = "69b2",
add_sub_cella_28.operation_mode = "arithmetic",
add_sub_cella_28.sum_lutc_input = "cin",
add_sub_cella_28.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_29
(
.aclr(aclr),
.cin(wire_add_sub_cella_28cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_29cout[0:0]),
.dataa(wire_add_sub_cella_dataa[29:29]),
.datab(wire_add_sub_cella_datab[29:29]),
.ena(clken),
.regout(wire_add_sub_cella_regout[29:29]));
defparam
add_sub_cella_29.cin_used = "true",
add_sub_cella_29.lut_mask = "69b2",
add_sub_cella_29.operation_mode = "arithmetic",
add_sub_cella_29.sum_lutc_input = "cin",
add_sub_cella_29.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_30
(
.aclr(aclr),
.cin(wire_add_sub_cella_29cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_30cout[0:0]),
.dataa(wire_add_sub_cella_dataa[30:30]),
.datab(wire_add_sub_cella_datab[30:30]),
.ena(clken),
.regout(wire_add_sub_cella_regout[30:30]));
defparam
add_sub_cella_30.cin_used = "true",
add_sub_cella_30.lut_mask = "69b2",
add_sub_cella_30.operation_mode = "arithmetic",
add_sub_cella_30.sum_lutc_input = "cin",
add_sub_cella_30.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_31
(
.aclr(aclr),
.cin(wire_add_sub_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_add_sub_cella_dataa[31:31]),
.datab(wire_add_sub_cella_datab[31:31]),
.ena(clken),
.regout(wire_add_sub_cella_regout[31:31]));
defparam
add_sub_cella_31.cin_used = "true",
add_sub_cella_31.lut_mask = "6969",
add_sub_cella_31.operation_mode = "normal",
add_sub_cella_31.sum_lutc_input = "cin",
add_sub_cella_31.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_regout;
endmodule //sub32_add_sub_cqa
//VALID FILE
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
sub32_add_sub_cqa sub32_add_sub_cqa_component (
.dataa (dataa),
.datab (datab),
.clken (clken),
.aclr (aclr),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: Function NUMERIC "1"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "1"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: sub32.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module sub32_add_sub_cqa
(
aclr,
clken,
clock,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [0:0] wire_add_sub_cella_11cout;
wire [0:0] wire_add_sub_cella_12cout;
wire [0:0] wire_add_sub_cella_13cout;
wire [0:0] wire_add_sub_cella_14cout;
wire [0:0] wire_add_sub_cella_15cout;
wire [0:0] wire_add_sub_cella_16cout;
wire [0:0] wire_add_sub_cella_17cout;
wire [0:0] wire_add_sub_cella_18cout;
wire [0:0] wire_add_sub_cella_19cout;
wire [0:0] wire_add_sub_cella_20cout;
wire [0:0] wire_add_sub_cella_21cout;
wire [0:0] wire_add_sub_cella_22cout;
wire [0:0] wire_add_sub_cella_23cout;
wire [0:0] wire_add_sub_cella_24cout;
wire [0:0] wire_add_sub_cella_25cout;
wire [0:0] wire_add_sub_cella_26cout;
wire [0:0] wire_add_sub_cella_27cout;
wire [0:0] wire_add_sub_cella_28cout;
wire [0:0] wire_add_sub_cella_29cout;
wire [0:0] wire_add_sub_cella_30cout;
wire [31:0] wire_add_sub_cella_dataa;
wire [31:0] wire_add_sub_cella_datab;
wire [31:0] wire_add_sub_cella_regout;
stratix_lcell add_sub_cella_0
(
.aclr(aclr),
.cin(1'b1),
.clk(clock),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.ena(clken),
.regout(wire_add_sub_cella_regout[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.aclr(aclr),
.cin(wire_add_sub_cella_0cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.ena(clken),
.regout(wire_add_sub_cella_regout[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.aclr(aclr),
.cin(wire_add_sub_cella_1cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.ena(clken),
.regout(wire_add_sub_cella_regout[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.aclr(aclr),
.cin(wire_add_sub_cella_2cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.ena(clken),
.regout(wire_add_sub_cella_regout[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.aclr(aclr),
.cin(wire_add_sub_cella_3cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.ena(clken),
.regout(wire_add_sub_cella_regout[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.aclr(aclr),
.cin(wire_add_sub_cella_4cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.ena(clken),
.regout(wire_add_sub_cella_regout[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.aclr(aclr),
.cin(wire_add_sub_cella_5cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.ena(clken),
.regout(wire_add_sub_cella_regout[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.aclr(aclr),
.cin(wire_add_sub_cella_6cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.ena(clken),
.regout(wire_add_sub_cella_regout[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_8
(
.aclr(aclr),
.cin(wire_add_sub_cella_7cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.ena(clken),
.regout(wire_add_sub_cella_regout[8:8]));
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_9
(
.aclr(aclr),
.cin(wire_add_sub_cella_8cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.ena(clken),
.regout(wire_add_sub_cella_regout[9:9]));
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_10
(
.aclr(aclr),
.cin(wire_add_sub_cella_9cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.ena(clken),
.regout(wire_add_sub_cella_regout[10:10]));
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_11
(
.aclr(aclr),
.cin(wire_add_sub_cella_10cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_11cout[0:0]),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.ena(clken),
.regout(wire_add_sub_cella_regout[11:11]));
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "69b2",
add_sub_cella_11.operation_mode = "arithmetic",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_12
(
.aclr(aclr),
.cin(wire_add_sub_cella_11cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_12cout[0:0]),
.dataa(wire_add_sub_cella_dataa[12:12]),
.datab(wire_add_sub_cella_datab[12:12]),
.ena(clken),
.regout(wire_add_sub_cella_regout[12:12]));
defparam
add_sub_cella_12.cin_used = "true",
add_sub_cella_12.lut_mask = "69b2",
add_sub_cella_12.operation_mode = "arithmetic",
add_sub_cella_12.sum_lutc_input = "cin",
add_sub_cella_12.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_13
(
.aclr(aclr),
.cin(wire_add_sub_cella_12cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_13cout[0:0]),
.dataa(wire_add_sub_cella_dataa[13:13]),
.datab(wire_add_sub_cella_datab[13:13]),
.ena(clken),
.regout(wire_add_sub_cella_regout[13:13]));
defparam
add_sub_cella_13.cin_used = "true",
add_sub_cella_13.lut_mask = "69b2",
add_sub_cella_13.operation_mode = "arithmetic",
add_sub_cella_13.sum_lutc_input = "cin",
add_sub_cella_13.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_14
(
.aclr(aclr),
.cin(wire_add_sub_cella_13cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_14cout[0:0]),
.dataa(wire_add_sub_cella_dataa[14:14]),
.datab(wire_add_sub_cella_datab[14:14]),
.ena(clken),
.regout(wire_add_sub_cella_regout[14:14]));
defparam
add_sub_cella_14.cin_used = "true",
add_sub_cella_14.lut_mask = "69b2",
add_sub_cella_14.operation_mode = "arithmetic",
add_sub_cella_14.sum_lutc_input = "cin",
add_sub_cella_14.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_15
(
.aclr(aclr),
.cin(wire_add_sub_cella_14cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_15cout[0:0]),
.dataa(wire_add_sub_cella_dataa[15:15]),
.datab(wire_add_sub_cella_datab[15:15]),
.ena(clken),
.regout(wire_add_sub_cella_regout[15:15]));
defparam
add_sub_cella_15.cin_used = "true",
add_sub_cella_15.lut_mask = "69b2",
add_sub_cella_15.operation_mode = "arithmetic",
add_sub_cella_15.sum_lutc_input = "cin",
add_sub_cella_15.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_16
(
.aclr(aclr),
.cin(wire_add_sub_cella_15cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_16cout[0:0]),
.dataa(wire_add_sub_cella_dataa[16:16]),
.datab(wire_add_sub_cella_datab[16:16]),
.ena(clken),
.regout(wire_add_sub_cella_regout[16:16]));
defparam
add_sub_cella_16.cin_used = "true",
add_sub_cella_16.lut_mask = "69b2",
add_sub_cella_16.operation_mode = "arithmetic",
add_sub_cella_16.sum_lutc_input = "cin",
add_sub_cella_16.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_17
(
.aclr(aclr),
.cin(wire_add_sub_cella_16cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_17cout[0:0]),
.dataa(wire_add_sub_cella_dataa[17:17]),
.datab(wire_add_sub_cella_datab[17:17]),
.ena(clken),
.regout(wire_add_sub_cella_regout[17:17]));
defparam
add_sub_cella_17.cin_used = "true",
add_sub_cella_17.lut_mask = "69b2",
add_sub_cella_17.operation_mode = "arithmetic",
add_sub_cella_17.sum_lutc_input = "cin",
add_sub_cella_17.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_18
(
.aclr(aclr),
.cin(wire_add_sub_cella_17cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_18cout[0:0]),
.dataa(wire_add_sub_cella_dataa[18:18]),
.datab(wire_add_sub_cella_datab[18:18]),
.ena(clken),
.regout(wire_add_sub_cella_regout[18:18]));
defparam
add_sub_cella_18.cin_used = "true",
add_sub_cella_18.lut_mask = "69b2",
add_sub_cella_18.operation_mode = "arithmetic",
add_sub_cella_18.sum_lutc_input = "cin",
add_sub_cella_18.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_19
(
.aclr(aclr),
.cin(wire_add_sub_cella_18cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_19cout[0:0]),
.dataa(wire_add_sub_cella_dataa[19:19]),
.datab(wire_add_sub_cella_datab[19:19]),
.ena(clken),
.regout(wire_add_sub_cella_regout[19:19]));
defparam
add_sub_cella_19.cin_used = "true",
add_sub_cella_19.lut_mask = "69b2",
add_sub_cella_19.operation_mode = "arithmetic",
add_sub_cella_19.sum_lutc_input = "cin",
add_sub_cella_19.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_20
(
.aclr(aclr),
.cin(wire_add_sub_cella_19cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_20cout[0:0]),
.dataa(wire_add_sub_cella_dataa[20:20]),
.datab(wire_add_sub_cella_datab[20:20]),
.ena(clken),
.regout(wire_add_sub_cella_regout[20:20]));
defparam
add_sub_cella_20.cin_used = "true",
add_sub_cella_20.lut_mask = "69b2",
add_sub_cella_20.operation_mode = "arithmetic",
add_sub_cella_20.sum_lutc_input = "cin",
add_sub_cella_20.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_21
(
.aclr(aclr),
.cin(wire_add_sub_cella_20cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_21cout[0:0]),
.dataa(wire_add_sub_cella_dataa[21:21]),
.datab(wire_add_sub_cella_datab[21:21]),
.ena(clken),
.regout(wire_add_sub_cella_regout[21:21]));
defparam
add_sub_cella_21.cin_used = "true",
add_sub_cella_21.lut_mask = "69b2",
add_sub_cella_21.operation_mode = "arithmetic",
add_sub_cella_21.sum_lutc_input = "cin",
add_sub_cella_21.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_22
(
.aclr(aclr),
.cin(wire_add_sub_cella_21cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_22cout[0:0]),
.dataa(wire_add_sub_cella_dataa[22:22]),
.datab(wire_add_sub_cella_datab[22:22]),
.ena(clken),
.regout(wire_add_sub_cella_regout[22:22]));
defparam
add_sub_cella_22.cin_used = "true",
add_sub_cella_22.lut_mask = "69b2",
add_sub_cella_22.operation_mode = "arithmetic",
add_sub_cella_22.sum_lutc_input = "cin",
add_sub_cella_22.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_23
(
.aclr(aclr),
.cin(wire_add_sub_cella_22cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_23cout[0:0]),
.dataa(wire_add_sub_cella_dataa[23:23]),
.datab(wire_add_sub_cella_datab[23:23]),
.ena(clken),
.regout(wire_add_sub_cella_regout[23:23]));
defparam
add_sub_cella_23.cin_used = "true",
add_sub_cella_23.lut_mask = "69b2",
add_sub_cella_23.operation_mode = "arithmetic",
add_sub_cella_23.sum_lutc_input = "cin",
add_sub_cella_23.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_24
(
.aclr(aclr),
.cin(wire_add_sub_cella_23cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_24cout[0:0]),
.dataa(wire_add_sub_cella_dataa[24:24]),
.datab(wire_add_sub_cella_datab[24:24]),
.ena(clken),
.regout(wire_add_sub_cella_regout[24:24]));
defparam
add_sub_cella_24.cin_used = "true",
add_sub_cella_24.lut_mask = "69b2",
add_sub_cella_24.operation_mode = "arithmetic",
add_sub_cella_24.sum_lutc_input = "cin",
add_sub_cella_24.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_25
(
.aclr(aclr),
.cin(wire_add_sub_cella_24cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_25cout[0:0]),
.dataa(wire_add_sub_cella_dataa[25:25]),
.datab(wire_add_sub_cella_datab[25:25]),
.ena(clken),
.regout(wire_add_sub_cella_regout[25:25]));
defparam
add_sub_cella_25.cin_used = "true",
add_sub_cella_25.lut_mask = "69b2",
add_sub_cella_25.operation_mode = "arithmetic",
add_sub_cella_25.sum_lutc_input = "cin",
add_sub_cella_25.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_26
(
.aclr(aclr),
.cin(wire_add_sub_cella_25cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_26cout[0:0]),
.dataa(wire_add_sub_cella_dataa[26:26]),
.datab(wire_add_sub_cella_datab[26:26]),
.ena(clken),
.regout(wire_add_sub_cella_regout[26:26]));
defparam
add_sub_cella_26.cin_used = "true",
add_sub_cella_26.lut_mask = "69b2",
add_sub_cella_26.operation_mode = "arithmetic",
add_sub_cella_26.sum_lutc_input = "cin",
add_sub_cella_26.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_27
(
.aclr(aclr),
.cin(wire_add_sub_cella_26cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_27cout[0:0]),
.dataa(wire_add_sub_cella_dataa[27:27]),
.datab(wire_add_sub_cella_datab[27:27]),
.ena(clken),
.regout(wire_add_sub_cella_regout[27:27]));
defparam
add_sub_cella_27.cin_used = "true",
add_sub_cella_27.lut_mask = "69b2",
add_sub_cella_27.operation_mode = "arithmetic",
add_sub_cella_27.sum_lutc_input = "cin",
add_sub_cella_27.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_28
(
.aclr(aclr),
.cin(wire_add_sub_cella_27cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_28cout[0:0]),
.dataa(wire_add_sub_cella_dataa[28:28]),
.datab(wire_add_sub_cella_datab[28:28]),
.ena(clken),
.regout(wire_add_sub_cella_regout[28:28]));
defparam
add_sub_cella_28.cin_used = "true",
add_sub_cella_28.lut_mask = "69b2",
add_sub_cella_28.operation_mode = "arithmetic",
add_sub_cella_28.sum_lutc_input = "cin",
add_sub_cella_28.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_29
(
.aclr(aclr),
.cin(wire_add_sub_cella_28cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_29cout[0:0]),
.dataa(wire_add_sub_cella_dataa[29:29]),
.datab(wire_add_sub_cella_datab[29:29]),
.ena(clken),
.regout(wire_add_sub_cella_regout[29:29]));
defparam
add_sub_cella_29.cin_used = "true",
add_sub_cella_29.lut_mask = "69b2",
add_sub_cella_29.operation_mode = "arithmetic",
add_sub_cella_29.sum_lutc_input = "cin",
add_sub_cella_29.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_30
(
.aclr(aclr),
.cin(wire_add_sub_cella_29cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_30cout[0:0]),
.dataa(wire_add_sub_cella_dataa[30:30]),
.datab(wire_add_sub_cella_datab[30:30]),
.ena(clken),
.regout(wire_add_sub_cella_regout[30:30]));
defparam
add_sub_cella_30.cin_used = "true",
add_sub_cella_30.lut_mask = "69b2",
add_sub_cella_30.operation_mode = "arithmetic",
add_sub_cella_30.sum_lutc_input = "cin",
add_sub_cella_30.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_31
(
.aclr(aclr),
.cin(wire_add_sub_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_add_sub_cella_dataa[31:31]),
.datab(wire_add_sub_cella_datab[31:31]),
.ena(clken),
.regout(wire_add_sub_cella_regout[31:31]));
defparam
add_sub_cella_31.cin_used = "true",
add_sub_cella_31.lut_mask = "6969",
add_sub_cella_31.operation_mode = "normal",
add_sub_cella_31.sum_lutc_input = "cin",
add_sub_cella_31.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_regout;
endmodule //sub32_add_sub_cqa
//VALID FILE
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
sub32_add_sub_cqa sub32_add_sub_cqa_component (
.dataa (dataa),
.datab (datab),
.clken (clken),
.aclr (aclr),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: Function NUMERIC "1"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "1"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: sub32.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module sub32_add_sub_cqa
(
aclr,
clken,
clock,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [0:0] wire_add_sub_cella_11cout;
wire [0:0] wire_add_sub_cella_12cout;
wire [0:0] wire_add_sub_cella_13cout;
wire [0:0] wire_add_sub_cella_14cout;
wire [0:0] wire_add_sub_cella_15cout;
wire [0:0] wire_add_sub_cella_16cout;
wire [0:0] wire_add_sub_cella_17cout;
wire [0:0] wire_add_sub_cella_18cout;
wire [0:0] wire_add_sub_cella_19cout;
wire [0:0] wire_add_sub_cella_20cout;
wire [0:0] wire_add_sub_cella_21cout;
wire [0:0] wire_add_sub_cella_22cout;
wire [0:0] wire_add_sub_cella_23cout;
wire [0:0] wire_add_sub_cella_24cout;
wire [0:0] wire_add_sub_cella_25cout;
wire [0:0] wire_add_sub_cella_26cout;
wire [0:0] wire_add_sub_cella_27cout;
wire [0:0] wire_add_sub_cella_28cout;
wire [0:0] wire_add_sub_cella_29cout;
wire [0:0] wire_add_sub_cella_30cout;
wire [31:0] wire_add_sub_cella_dataa;
wire [31:0] wire_add_sub_cella_datab;
wire [31:0] wire_add_sub_cella_regout;
stratix_lcell add_sub_cella_0
(
.aclr(aclr),
.cin(1'b1),
.clk(clock),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.ena(clken),
.regout(wire_add_sub_cella_regout[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.aclr(aclr),
.cin(wire_add_sub_cella_0cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.ena(clken),
.regout(wire_add_sub_cella_regout[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.aclr(aclr),
.cin(wire_add_sub_cella_1cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.ena(clken),
.regout(wire_add_sub_cella_regout[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.aclr(aclr),
.cin(wire_add_sub_cella_2cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.ena(clken),
.regout(wire_add_sub_cella_regout[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.aclr(aclr),
.cin(wire_add_sub_cella_3cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.ena(clken),
.regout(wire_add_sub_cella_regout[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.aclr(aclr),
.cin(wire_add_sub_cella_4cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.ena(clken),
.regout(wire_add_sub_cella_regout[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.aclr(aclr),
.cin(wire_add_sub_cella_5cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.ena(clken),
.regout(wire_add_sub_cella_regout[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.aclr(aclr),
.cin(wire_add_sub_cella_6cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.ena(clken),
.regout(wire_add_sub_cella_regout[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_8
(
.aclr(aclr),
.cin(wire_add_sub_cella_7cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.ena(clken),
.regout(wire_add_sub_cella_regout[8:8]));
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_9
(
.aclr(aclr),
.cin(wire_add_sub_cella_8cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.ena(clken),
.regout(wire_add_sub_cella_regout[9:9]));
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_10
(
.aclr(aclr),
.cin(wire_add_sub_cella_9cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.ena(clken),
.regout(wire_add_sub_cella_regout[10:10]));
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_11
(
.aclr(aclr),
.cin(wire_add_sub_cella_10cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_11cout[0:0]),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.ena(clken),
.regout(wire_add_sub_cella_regout[11:11]));
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "69b2",
add_sub_cella_11.operation_mode = "arithmetic",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_12
(
.aclr(aclr),
.cin(wire_add_sub_cella_11cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_12cout[0:0]),
.dataa(wire_add_sub_cella_dataa[12:12]),
.datab(wire_add_sub_cella_datab[12:12]),
.ena(clken),
.regout(wire_add_sub_cella_regout[12:12]));
defparam
add_sub_cella_12.cin_used = "true",
add_sub_cella_12.lut_mask = "69b2",
add_sub_cella_12.operation_mode = "arithmetic",
add_sub_cella_12.sum_lutc_input = "cin",
add_sub_cella_12.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_13
(
.aclr(aclr),
.cin(wire_add_sub_cella_12cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_13cout[0:0]),
.dataa(wire_add_sub_cella_dataa[13:13]),
.datab(wire_add_sub_cella_datab[13:13]),
.ena(clken),
.regout(wire_add_sub_cella_regout[13:13]));
defparam
add_sub_cella_13.cin_used = "true",
add_sub_cella_13.lut_mask = "69b2",
add_sub_cella_13.operation_mode = "arithmetic",
add_sub_cella_13.sum_lutc_input = "cin",
add_sub_cella_13.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_14
(
.aclr(aclr),
.cin(wire_add_sub_cella_13cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_14cout[0:0]),
.dataa(wire_add_sub_cella_dataa[14:14]),
.datab(wire_add_sub_cella_datab[14:14]),
.ena(clken),
.regout(wire_add_sub_cella_regout[14:14]));
defparam
add_sub_cella_14.cin_used = "true",
add_sub_cella_14.lut_mask = "69b2",
add_sub_cella_14.operation_mode = "arithmetic",
add_sub_cella_14.sum_lutc_input = "cin",
add_sub_cella_14.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_15
(
.aclr(aclr),
.cin(wire_add_sub_cella_14cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_15cout[0:0]),
.dataa(wire_add_sub_cella_dataa[15:15]),
.datab(wire_add_sub_cella_datab[15:15]),
.ena(clken),
.regout(wire_add_sub_cella_regout[15:15]));
defparam
add_sub_cella_15.cin_used = "true",
add_sub_cella_15.lut_mask = "69b2",
add_sub_cella_15.operation_mode = "arithmetic",
add_sub_cella_15.sum_lutc_input = "cin",
add_sub_cella_15.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_16
(
.aclr(aclr),
.cin(wire_add_sub_cella_15cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_16cout[0:0]),
.dataa(wire_add_sub_cella_dataa[16:16]),
.datab(wire_add_sub_cella_datab[16:16]),
.ena(clken),
.regout(wire_add_sub_cella_regout[16:16]));
defparam
add_sub_cella_16.cin_used = "true",
add_sub_cella_16.lut_mask = "69b2",
add_sub_cella_16.operation_mode = "arithmetic",
add_sub_cella_16.sum_lutc_input = "cin",
add_sub_cella_16.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_17
(
.aclr(aclr),
.cin(wire_add_sub_cella_16cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_17cout[0:0]),
.dataa(wire_add_sub_cella_dataa[17:17]),
.datab(wire_add_sub_cella_datab[17:17]),
.ena(clken),
.regout(wire_add_sub_cella_regout[17:17]));
defparam
add_sub_cella_17.cin_used = "true",
add_sub_cella_17.lut_mask = "69b2",
add_sub_cella_17.operation_mode = "arithmetic",
add_sub_cella_17.sum_lutc_input = "cin",
add_sub_cella_17.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_18
(
.aclr(aclr),
.cin(wire_add_sub_cella_17cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_18cout[0:0]),
.dataa(wire_add_sub_cella_dataa[18:18]),
.datab(wire_add_sub_cella_datab[18:18]),
.ena(clken),
.regout(wire_add_sub_cella_regout[18:18]));
defparam
add_sub_cella_18.cin_used = "true",
add_sub_cella_18.lut_mask = "69b2",
add_sub_cella_18.operation_mode = "arithmetic",
add_sub_cella_18.sum_lutc_input = "cin",
add_sub_cella_18.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_19
(
.aclr(aclr),
.cin(wire_add_sub_cella_18cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_19cout[0:0]),
.dataa(wire_add_sub_cella_dataa[19:19]),
.datab(wire_add_sub_cella_datab[19:19]),
.ena(clken),
.regout(wire_add_sub_cella_regout[19:19]));
defparam
add_sub_cella_19.cin_used = "true",
add_sub_cella_19.lut_mask = "69b2",
add_sub_cella_19.operation_mode = "arithmetic",
add_sub_cella_19.sum_lutc_input = "cin",
add_sub_cella_19.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_20
(
.aclr(aclr),
.cin(wire_add_sub_cella_19cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_20cout[0:0]),
.dataa(wire_add_sub_cella_dataa[20:20]),
.datab(wire_add_sub_cella_datab[20:20]),
.ena(clken),
.regout(wire_add_sub_cella_regout[20:20]));
defparam
add_sub_cella_20.cin_used = "true",
add_sub_cella_20.lut_mask = "69b2",
add_sub_cella_20.operation_mode = "arithmetic",
add_sub_cella_20.sum_lutc_input = "cin",
add_sub_cella_20.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_21
(
.aclr(aclr),
.cin(wire_add_sub_cella_20cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_21cout[0:0]),
.dataa(wire_add_sub_cella_dataa[21:21]),
.datab(wire_add_sub_cella_datab[21:21]),
.ena(clken),
.regout(wire_add_sub_cella_regout[21:21]));
defparam
add_sub_cella_21.cin_used = "true",
add_sub_cella_21.lut_mask = "69b2",
add_sub_cella_21.operation_mode = "arithmetic",
add_sub_cella_21.sum_lutc_input = "cin",
add_sub_cella_21.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_22
(
.aclr(aclr),
.cin(wire_add_sub_cella_21cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_22cout[0:0]),
.dataa(wire_add_sub_cella_dataa[22:22]),
.datab(wire_add_sub_cella_datab[22:22]),
.ena(clken),
.regout(wire_add_sub_cella_regout[22:22]));
defparam
add_sub_cella_22.cin_used = "true",
add_sub_cella_22.lut_mask = "69b2",
add_sub_cella_22.operation_mode = "arithmetic",
add_sub_cella_22.sum_lutc_input = "cin",
add_sub_cella_22.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_23
(
.aclr(aclr),
.cin(wire_add_sub_cella_22cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_23cout[0:0]),
.dataa(wire_add_sub_cella_dataa[23:23]),
.datab(wire_add_sub_cella_datab[23:23]),
.ena(clken),
.regout(wire_add_sub_cella_regout[23:23]));
defparam
add_sub_cella_23.cin_used = "true",
add_sub_cella_23.lut_mask = "69b2",
add_sub_cella_23.operation_mode = "arithmetic",
add_sub_cella_23.sum_lutc_input = "cin",
add_sub_cella_23.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_24
(
.aclr(aclr),
.cin(wire_add_sub_cella_23cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_24cout[0:0]),
.dataa(wire_add_sub_cella_dataa[24:24]),
.datab(wire_add_sub_cella_datab[24:24]),
.ena(clken),
.regout(wire_add_sub_cella_regout[24:24]));
defparam
add_sub_cella_24.cin_used = "true",
add_sub_cella_24.lut_mask = "69b2",
add_sub_cella_24.operation_mode = "arithmetic",
add_sub_cella_24.sum_lutc_input = "cin",
add_sub_cella_24.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_25
(
.aclr(aclr),
.cin(wire_add_sub_cella_24cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_25cout[0:0]),
.dataa(wire_add_sub_cella_dataa[25:25]),
.datab(wire_add_sub_cella_datab[25:25]),
.ena(clken),
.regout(wire_add_sub_cella_regout[25:25]));
defparam
add_sub_cella_25.cin_used = "true",
add_sub_cella_25.lut_mask = "69b2",
add_sub_cella_25.operation_mode = "arithmetic",
add_sub_cella_25.sum_lutc_input = "cin",
add_sub_cella_25.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_26
(
.aclr(aclr),
.cin(wire_add_sub_cella_25cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_26cout[0:0]),
.dataa(wire_add_sub_cella_dataa[26:26]),
.datab(wire_add_sub_cella_datab[26:26]),
.ena(clken),
.regout(wire_add_sub_cella_regout[26:26]));
defparam
add_sub_cella_26.cin_used = "true",
add_sub_cella_26.lut_mask = "69b2",
add_sub_cella_26.operation_mode = "arithmetic",
add_sub_cella_26.sum_lutc_input = "cin",
add_sub_cella_26.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_27
(
.aclr(aclr),
.cin(wire_add_sub_cella_26cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_27cout[0:0]),
.dataa(wire_add_sub_cella_dataa[27:27]),
.datab(wire_add_sub_cella_datab[27:27]),
.ena(clken),
.regout(wire_add_sub_cella_regout[27:27]));
defparam
add_sub_cella_27.cin_used = "true",
add_sub_cella_27.lut_mask = "69b2",
add_sub_cella_27.operation_mode = "arithmetic",
add_sub_cella_27.sum_lutc_input = "cin",
add_sub_cella_27.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_28
(
.aclr(aclr),
.cin(wire_add_sub_cella_27cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_28cout[0:0]),
.dataa(wire_add_sub_cella_dataa[28:28]),
.datab(wire_add_sub_cella_datab[28:28]),
.ena(clken),
.regout(wire_add_sub_cella_regout[28:28]));
defparam
add_sub_cella_28.cin_used = "true",
add_sub_cella_28.lut_mask = "69b2",
add_sub_cella_28.operation_mode = "arithmetic",
add_sub_cella_28.sum_lutc_input = "cin",
add_sub_cella_28.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_29
(
.aclr(aclr),
.cin(wire_add_sub_cella_28cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_29cout[0:0]),
.dataa(wire_add_sub_cella_dataa[29:29]),
.datab(wire_add_sub_cella_datab[29:29]),
.ena(clken),
.regout(wire_add_sub_cella_regout[29:29]));
defparam
add_sub_cella_29.cin_used = "true",
add_sub_cella_29.lut_mask = "69b2",
add_sub_cella_29.operation_mode = "arithmetic",
add_sub_cella_29.sum_lutc_input = "cin",
add_sub_cella_29.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_30
(
.aclr(aclr),
.cin(wire_add_sub_cella_29cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_30cout[0:0]),
.dataa(wire_add_sub_cella_dataa[30:30]),
.datab(wire_add_sub_cella_datab[30:30]),
.ena(clken),
.regout(wire_add_sub_cella_regout[30:30]));
defparam
add_sub_cella_30.cin_used = "true",
add_sub_cella_30.lut_mask = "69b2",
add_sub_cella_30.operation_mode = "arithmetic",
add_sub_cella_30.sum_lutc_input = "cin",
add_sub_cella_30.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_31
(
.aclr(aclr),
.cin(wire_add_sub_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_add_sub_cella_dataa[31:31]),
.datab(wire_add_sub_cella_datab[31:31]),
.ena(clken),
.regout(wire_add_sub_cella_regout[31:31]));
defparam
add_sub_cella_31.cin_used = "true",
add_sub_cella_31.lut_mask = "6969",
add_sub_cella_31.operation_mode = "normal",
add_sub_cella_31.sum_lutc_input = "cin",
add_sub_cella_31.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_regout;
endmodule //sub32_add_sub_cqa
//VALID FILE
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
sub32_add_sub_cqa sub32_add_sub_cqa_component (
.dataa (dataa),
.datab (datab),
.clken (clken),
.aclr (aclr),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: Function NUMERIC "1"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "1"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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