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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
//
// Example module to create problem.
//
// generate a 64 bit value with bits
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
// all other bits zero.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] HighLogicImm; // From example of example.v
wire [63:0] LogicImm; // From example of example.v
wire [63:0] LowLogicImm; // From example of example.v
// End of automatics
wire [5:0] LowMaskSel_Top = crc[5:0];
wire [5:0] LowMaskSel_Bot = crc[5:0];
wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]};
wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]};
example example (/*AUTOINST*/
// Outputs
.LogicImm (LogicImm[63:0]),
.LowLogicImm (LowLogicImm[63:0]),
.HighLogicImm (HighLogicImm[63:0]),
// Inputs
.LowMaskSel_Top (LowMaskSel_Top[5:0]),
.HighMaskSel_Top (HighMaskSel_Top[5:0]),
.LowMaskSel_Bot (LowMaskSel_Bot[5:0]),
.HighMaskSel_Bot (HighMaskSel_Bot[5:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
LowLogicImm, HighLogicImm, LogicImm);
`endif
if (cyc==0) begin
// Single case
crc <= 8'h0;
sum <= 64'h0;
end
else if (cyc==1) begin
// Setup
crc <= 8'hed;
sum <= 64'h0;
end
else if (cyc<90) begin
sum <= {sum[62:0],sum[63]} ^ LogicImm;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b00111000) $stop;
if (sum !== 64'h58743ffa61e41075) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module example (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [5:0] LowMaskSel_Top, HighMaskSel_Top;
input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
wire [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
end
end
endgenerate
/* verilator lint_on UNSIGNED */
/* verilator lint_on CMPCONST */
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things when transmitting a command to an ISO
// 15693 tag, using 100% modulation only for now.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_tx(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
shallow_modulation
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input shallow_modulation;
// The high-frequency stuff. For now, for testing, just bring out the carrier,
// and allow the ARM to modulate it over the SSP.
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3;
reg pwr_oe4;
always @(ck_1356megb or ssp_dout or shallow_modulation)
begin
if(shallow_modulation)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= ~ssp_dout;
pwr_oe2 <= ~ssp_dout;
pwr_oe3 <= ~ssp_dout;
pwr_oe4 <= 1'b0;
end
else
begin
pwr_hi <= ck_1356megb & ssp_dout;
pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= 1'b0;
end
end
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
// for the synchronous serial port.
reg [6:0] hi_div_by_128;
always @(posedge ck_1356meg)
hi_div_by_128 <= hi_div_by_128 + 1;
assign ssp_clk = hi_div_by_128[6];
reg [2:0] hi_byte_div;
always @(negedge ssp_clk)
hi_byte_div <= hi_byte_div + 1;
assign ssp_frame = (hi_byte_div == 3'b000);
// Implement a hysteresis to give out the received signal on
// ssp_din. Sample at fc.
assign adc_clk = ck_1356meg;
// ADC data appears on the rising edge, so sample it on the falling edge
reg after_hysteresis;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
end
assign ssp_din = after_hysteresis;
assign pwr_lo = 1'b0;
assign dbg = ssp_din;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef verilator // Otherwise need it in every module, including test, but that'll make a mess
timeunit 1ns;
timeprecision 1ns;
`endif
input clk;
integer cyc; initial cyc=1;
supply0 [1:0] low;
supply1 [1:0] high;
reg [7:0] isizedwire;
reg ionewire;
wire oonewire;
wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v
t_inst sub
(
.osizedreg,
.oonewire,
// Inputs
.isizedwire (isizedwire[7:0]),
.*
//.ionewire (ionewire)
);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
ionewire <= 1'b1;
isizedwire <= 8'd8;
end
if (cyc==2) begin
if (low != 2'b00) $stop;
if (high != 2'b11) $stop;
if (oonewire !== 1'b1) $stop;
if (isizedwire !== 8'd8) $stop;
end
if (cyc==3) begin
ionewire <= 1'b0;
isizedwire <= 8'd7;
end
if (cyc==4) begin
if (oonewire !== 1'b0) $stop;
if (isizedwire !== 8'd7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module t_inst
(
output reg [7:0] osizedreg,
output wire oonewire /*verilator public*/,
input [7:0] isizedwire,
input wire ionewire
);
assign oonewire = ionewire;
always @* begin
osizedreg = isizedwire;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg b;
wire vconst1 = 1'b0;
wire vconst2 = !(vconst1);
wire vconst3 = !vconst2;
wire vconst = vconst3;
wire qa;
wire qb;
wire qc;
wire qd;
wire qe;
ta ta (.b(b), .vconst(vconst), .q(qa));
tb tb (.clk(clk), .vconst(vconst), .q(qb));
tc tc (.b(b), .vconst(vconst), .q(qc));
td td (.b(b), .vconst(vconst), .q(qd));
te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$display("%b",{qa,qb,qc,qd,qe});
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
b <= 1'b1;
end
if (cyc==2) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
b <= 1'b0;
end
if (cyc==3) begin
if (qa!=1'b0) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b0) $stop;
b <= 1'b1;
end
if (cyc==4) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b1) $stop;
b <= 1'b0;
end
if (cyc==5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module ta (
input vconst,
input b,
output reg q);
always @ (/*AS*/b or vconst) begin
q = vconst | b;
end
endmodule
module tb (
input vconst,
input clk,
output reg q);
always @ (posedge clk) begin
q <= vconst;
end
endmodule
module tc (
input vconst,
input b,
output reg q);
always @ (posedge vconst) begin
q <= b;
$stop;
end
endmodule
module td (
input vconst,
input b,
output reg q);
always @ (/*AS*/vconst) begin
q = vconst;
end
endmodule
module te (
input clk,
input vconst,
input b,
output reg q);
reg qmid;
always @ (posedge vconst or posedge clk) begin
qmid <= b;
end
always @ (posedge clk or posedge vconst) begin
q <= qmid;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg b;
wire vconst1 = 1'b0;
wire vconst2 = !(vconst1);
wire vconst3 = !vconst2;
wire vconst = vconst3;
wire qa;
wire qb;
wire qc;
wire qd;
wire qe;
ta ta (.b(b), .vconst(vconst), .q(qa));
tb tb (.clk(clk), .vconst(vconst), .q(qb));
tc tc (.b(b), .vconst(vconst), .q(qc));
td td (.b(b), .vconst(vconst), .q(qd));
te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$display("%b",{qa,qb,qc,qd,qe});
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
b <= 1'b1;
end
if (cyc==2) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
b <= 1'b0;
end
if (cyc==3) begin
if (qa!=1'b0) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b0) $stop;
b <= 1'b1;
end
if (cyc==4) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b1) $stop;
b <= 1'b0;
end
if (cyc==5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module ta (
input vconst,
input b,
output reg q);
always @ (/*AS*/b or vconst) begin
q = vconst | b;
end
endmodule
module tb (
input vconst,
input clk,
output reg q);
always @ (posedge clk) begin
q <= vconst;
end
endmodule
module tc (
input vconst,
input b,
output reg q);
always @ (posedge vconst) begin
q <= b;
$stop;
end
endmodule
module td (
input vconst,
input b,
output reg q);
always @ (/*AS*/vconst) begin
q = vconst;
end
endmodule
module te (
input clk,
input vconst,
input b,
output reg q);
reg qmid;
always @ (posedge vconst or posedge clk) begin
qmid <= b;
end
always @ (posedge clk or posedge vconst) begin
q <= qmid;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg a; initial a = 1'b1;
reg b_fc; initial b_fc = 1'b0;
reg b_pc; initial b_pc = 1'b0;
reg b_oh; initial b_oh = 1'b0;
reg b_oc; initial b_oc = 1'b0;
wire a_l = ~a;
wire b_oc_l = ~b_oc;
// Note we must insure that full, parallel, etc, only fire during
// edges (not mid-cycle), and must provide a way to turn them off.
// SystemVerilog provides: $asserton and $assertoff.
// verilator lint_off CASEINCOMPLETE
always @* begin
// Note not all tools support directives on casez's
case ({a,b_fc}) // synopsys full_case
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
priority case ({a,b_fc})
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
end
always @* begin
case (1'b1) // synopsys full_case parallel_case
a: ;
b_pc: ;
endcase
end
`ifdef NOT_YET_VERILATOR // Unsupported
// ambit synthesis one_hot "a, b_oh"
// cadence one_cold "a_l, b_oc_l"
`endif
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==2) begin
a <= 1'b0;
b_fc <= 1'b1;
b_pc <= 1'b1;
b_oh <= 1'b1;
b_oc <= 1'b1;
end
if (cyc==3) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==4) begin
`ifdef FAILING_FULL
b_fc <= 1'b1;
`endif
`ifdef FAILING_PARALLEL
b_pc <= 1'b1;
`endif
`ifdef FAILING_OH
b_oh <= 1'b1;
`endif
`ifdef FAILING_OC
b_oc <= 1'b1;
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
sub sub (.in(crc[23:0]), .out1(out1));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1,
// Inputs
in
);
input [23:0] in;
output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal
parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101;
always @* begin
casez (in[17:16])
2'b00: casez (in[2:0])
3'h0: out1[0] = in[0]^RANDOM[0];
3'h1: out1[0] = in[0]^RANDOM[1];
3'h2: out1[0] = in[0]^RANDOM[2];
3'h3: out1[0] = in[0]^RANDOM[3];
3'h4: out1[0] = in[0]^RANDOM[4];
3'h5: out1[0] = in[0]^RANDOM[5];
3'h6: out1[0] = in[0]^RANDOM[6];
3'h7: out1[0] = in[0]^RANDOM[7];
endcase
2'b01: casez (in[2:0])
3'h0: out1[0] = RANDOM[10];
3'h1: out1[0] = RANDOM[11];
3'h2: out1[0] = RANDOM[12];
3'h3: out1[0] = RANDOM[13];
3'h4: out1[0] = RANDOM[14];
3'h5: out1[0] = RANDOM[15];
3'h6: out1[0] = RANDOM[16];
3'h7: out1[0] = RANDOM[17];
endcase
2'b1?: casez (in[4])
1'b1: casez (in[2:0])
3'h0: out1[0] = RANDOM[20];
3'h1: out1[0] = RANDOM[21];
3'h2: out1[0] = RANDOM[22];
3'h3: out1[0] = RANDOM[23];
3'h4: out1[0] = RANDOM[24];
3'h5: out1[0] = RANDOM[25];
3'h6: out1[0] = RANDOM[26];
3'h7: out1[0] = RANDOM[27];
endcase
1'b0: casez (in[2:0])
3'h0: out1[0] = RANDOM[30];
3'h1: out1[0] = RANDOM[31];
3'h2: out1[0] = RANDOM[32];
3'h3: out1[0] = RANDOM[33];
3'h4: out1[0] = RANDOM[34];
3'h5: out1[0] = RANDOM[35];
3'h6: out1[0] = RANDOM[36];
3'h7: out1[0] = RANDOM[37];
endcase
endcase
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam // synopsys enum En_State
EP_State_IDLE = {3'b000,5'd00},
EP_State_CMDSHIFT0 = {3'b001,5'd00},
EP_State_CMDSHIFT13 = {3'b001,5'd13},
EP_State_CMDSHIFT14 = {3'b001,5'd14},
EP_State_CMDSHIFT15 = {3'b001,5'd15},
EP_State_CMDSHIFT16 = {3'b001,5'd16},
EP_State_DWAIT = {3'b010,5'd00},
EP_State_DSHIFT0 = {3'b100,5'd00},
EP_State_DSHIFT1 = {3'b100,5'd01},
EP_State_DSHIFT15 = {3'b100,5'd15};
reg [7:0] /* synopsys enum En_State */
m_state_xr; // Last command, for debugging
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [7:0] crc;
// Build up assignments
wire [7:0] bitrev;
assign bitrev[7] = crc[0];
assign bitrev[6] = crc[1];
assign bitrev[5] = crc[2];
assign bitrev[4] = crc[3];
assign bitrev[0] = crc[7];
assign bitrev[1] = crc[6];
assign bitrev[2] = crc[5];
assign bitrev[3] = crc[4];
// Build up always assignments
reg [7:0] bitrevb;
always @ (/*AS*/crc) begin
bitrevb[7] = crc[0];
bitrevb[6] = crc[1];
bitrevb[5] = crc[2];
bitrevb[4] = crc[3];
bitrevb[0] = crc[7];
bitrevb[1] = crc[6];
bitrevb[2] = crc[5];
bitrevb[3] = crc[4];
end
// Build up always assignments
reg [7:0] bitrevr;
always @ (posedge clk) begin
bitrevr[7] <= crc[0];
bitrevr[6] <= crc[1];
bitrevr[5] <= crc[2];
bitrevr[4] <= crc[3];
bitrevr[0] <= crc[7];
bitrevr[1] <= crc[6];
bitrevr[2] <= crc[5];
bitrevr[3] <= crc[4];
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
//$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev);
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
crc <= 8'hed;
end
if (cyc==2 && bitrev!=8'hb7) $stop;
if (cyc==3 && bitrev!=8'h5b) $stop;
if (cyc==4 && bitrev!=8'h2d) $stop;
if (cyc==5 && bitrev!=8'h16) $stop;
if (cyc==6 && bitrev!=8'h8b) $stop;
if (cyc==7 && bitrev!=8'hc5) $stop;
if (cyc==8 && bitrev!=8'he2) $stop;
if (cyc==9 && bitrev!=8'hf1) $stop;
if (bitrevb != bitrev) $stop;
if (cyc==3 && bitrevr!=8'hb7) $stop;
if (cyc==4 && bitrevr!=8'h5b) $stop;
if (cyc==5 && bitrevr!=8'h2d) $stop;
if (cyc==6 && bitrevr!=8'h16) $stop;
if (cyc==7 && bitrevr!=8'h8b) $stop;
if (cyc==8 && bitrevr!=8'hc5) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [7:0] crc;
// Build up assignments
wire [7:0] bitrev;
assign bitrev[7] = crc[0];
assign bitrev[6] = crc[1];
assign bitrev[5] = crc[2];
assign bitrev[4] = crc[3];
assign bitrev[0] = crc[7];
assign bitrev[1] = crc[6];
assign bitrev[2] = crc[5];
assign bitrev[3] = crc[4];
// Build up always assignments
reg [7:0] bitrevb;
always @ (/*AS*/crc) begin
bitrevb[7] = crc[0];
bitrevb[6] = crc[1];
bitrevb[5] = crc[2];
bitrevb[4] = crc[3];
bitrevb[0] = crc[7];
bitrevb[1] = crc[6];
bitrevb[2] = crc[5];
bitrevb[3] = crc[4];
end
// Build up always assignments
reg [7:0] bitrevr;
always @ (posedge clk) begin
bitrevr[7] <= crc[0];
bitrevr[6] <= crc[1];
bitrevr[5] <= crc[2];
bitrevr[4] <= crc[3];
bitrevr[0] <= crc[7];
bitrevr[1] <= crc[6];
bitrevr[2] <= crc[5];
bitrevr[3] <= crc[4];
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
//$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev);
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
crc <= 8'hed;
end
if (cyc==2 && bitrev!=8'hb7) $stop;
if (cyc==3 && bitrev!=8'h5b) $stop;
if (cyc==4 && bitrev!=8'h2d) $stop;
if (cyc==5 && bitrev!=8'h16) $stop;
if (cyc==6 && bitrev!=8'h8b) $stop;
if (cyc==7 && bitrev!=8'hc5) $stop;
if (cyc==8 && bitrev!=8'he2) $stop;
if (cyc==9 && bitrev!=8'hf1) $stop;
if (bitrevb != bitrev) $stop;
if (cyc==3 && bitrevr!=8'hb7) $stop;
if (cyc==4 && bitrevr!=8'h5b) $stop;
if (cyc==5 && bitrevr!=8'h2d) $stop;
if (cyc==6 && bitrevr!=8'h16) $stop;
if (cyc==7 && bitrevr!=8'h8b) $stop;
if (cyc==8 && bitrevr!=8'hc5) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_axi_master.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Master port interface.
* It uses AXI3 Master BFM
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_axi_master (
M_RESETN,
M_ARVALID,
M_AWVALID,
M_BREADY,
M_RREADY,
M_WLAST,
M_WVALID,
M_ARID,
M_AWID,
M_WID,
M_ARBURST,
M_ARLOCK,
M_ARSIZE,
M_AWBURST,
M_AWLOCK,
M_AWSIZE,
M_ARPROT,
M_AWPROT,
M_ARADDR,
M_AWADDR,
M_WDATA,
M_ARCACHE,
M_ARLEN,
M_AWCACHE,
M_AWLEN,
M_ARQOS, // not connected to AXI BFM
M_AWQOS, // not connected to AXI BFM
M_WSTRB,
M_ACLK,
M_ARREADY,
M_AWREADY,
M_BVALID,
M_RLAST,
M_RVALID,
M_WREADY,
M_BID,
M_RID,
M_BRESP,
M_RRESP,
M_RDATA
);
parameter enable_this_port = 0;
parameter master_name = "Master";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter ID = 12'hC00;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* IDs for Masters
// l2m1 (CPU000)
12'b11_000_000_00_00
12'b11_010_000_00_00
12'b11_011_000_00_00
12'b11_100_000_00_00
12'b11_101_000_00_00
12'b11_110_000_00_00
12'b11_111_000_00_00
// l2m1 (CPU001)
12'b11_000_001_00_00
12'b11_010_001_00_00
12'b11_011_001_00_00
12'b11_100_001_00_00
12'b11_101_001_00_00
12'b11_110_001_00_00
12'b11_111_001_00_00
*/
input M_RESETN;
output M_ARVALID;
output M_AWVALID;
output M_BREADY;
output M_RREADY;
output M_WLAST;
output M_WVALID;
output [id_bus_width-1:0] M_ARID;
output [id_bus_width-1:0] M_AWID;
output [id_bus_width-1:0] M_WID;
output [axi_brst_type_width-1:0] M_ARBURST;
output [axi_lock_width-1:0] M_ARLOCK;
output [axi_size_width-1:0] M_ARSIZE;
output [axi_brst_type_width-1:0] M_AWBURST;
output [axi_lock_width-1:0] M_AWLOCK;
output [axi_size_width-1:0] M_AWSIZE;
output [axi_prot_width-1:0] M_ARPROT;
output [axi_prot_width-1:0] M_AWPROT;
output [address_bus_width-1:0] M_ARADDR;
output [address_bus_width-1:0] M_AWADDR;
output [data_bus_width-1:0] M_WDATA;
output [axi_cache_width-1:0] M_ARCACHE;
output [axi_len_width-1:0] M_ARLEN;
output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM
output [axi_cache_width-1:0] M_AWCACHE;
output [axi_len_width-1:0] M_AWLEN;
output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM
output [(data_bus_width/8)-1:0] M_WSTRB;
input M_ACLK;
input M_ARREADY;
input M_AWREADY;
input M_BVALID;
input M_RLAST;
input M_RVALID;
input M_WREADY;
input [id_bus_width-1:0] M_BID;
input [id_bus_width-1:0] M_RID;
input [axi_rsp_width-1:0] M_BRESP;
input [axi_rsp_width-1:0] M_RRESP;
input [data_bus_width-1:0] M_RDATA;
wire net_RESETN;
wire net_RVALID;
wire net_BVALID;
reg DEBUG_INFO = 1'b1;
reg STOP_ON_ERROR = 1'b1;
integer use_id_no = 0;
assign M_ARQOS = 'b0;
assign M_AWQOS = 'b0;
assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0;
assign net_RVALID = enable_this_port ? M_RVALID : 1'b0;
assign net_BVALID = enable_this_port ? M_BVALID : 1'b0;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name);
end
end
initial master.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge M_ACLK);
if(!enable_this_port) begin
master.set_channel_level_info(0);
master.set_function_level_info(0);
end
master.RESPONSE_TIMEOUT = 0;
end
cdn_axi3_master_bfm #(master_name,
data_bus_width,
address_bus_width,
id_bus_width,
max_outstanding_transactions,
exclusive_access_supported)
master (.ACLK (M_ACLK),
.ARESETn (net_RESETN), /// confirm this
// Write Address Channel
.AWID (M_AWID),
.AWADDR (M_AWADDR),
.AWLEN (M_AWLEN),
.AWSIZE (M_AWSIZE),
.AWBURST (M_AWBURST),
.AWLOCK (M_AWLOCK),
.AWCACHE (M_AWCACHE),
.AWPROT (M_AWPROT),
.AWVALID (M_AWVALID),
.AWREADY (M_AWREADY),
// Write Data Channel Signals.
.WID (M_WID),
.WDATA (M_WDATA),
.WSTRB (M_WSTRB),
.WLAST (M_WLAST),
.WVALID (M_WVALID),
.WREADY (M_WREADY),
// Write Response Channel Signals.
.BID (M_BID),
.BRESP (M_BRESP),
.BVALID (net_BVALID),
.BREADY (M_BREADY),
// Read Address Channel Signals.
.ARID (M_ARID),
.ARADDR (M_ARADDR),
.ARLEN (M_ARLEN),
.ARSIZE (M_ARSIZE),
.ARBURST (M_ARBURST),
.ARLOCK (M_ARLOCK),
.ARCACHE (M_ARCACHE),
.ARPROT (M_ARPROT),
.ARVALID (M_ARVALID),
.ARREADY (M_ARREADY),
// Read Data Channel Signals.
.RID (M_RID),
.RDATA (M_RDATA),
.RRESP (M_RRESP),
.RLAST (M_RLAST),
.RVALID (net_RVALID),
.RREADY (M_RREADY));
/* Call to BFM APIs */
task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.READ_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,response);
else
master.READ_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST_CONCURRENT(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST_CONCURRENT(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
/* local */
function automatic[id_bus_width-1:0] get_id;
input dummy;
begin
case(use_id_no)
// l2m1 (CPU000)
0 : get_id = 12'b11_000_000_00_00;
1 : get_id = 12'b11_010_000_00_00;
2 : get_id = 12'b11_011_000_00_00;
3 : get_id = 12'b11_100_000_00_00;
4 : get_id = 12'b11_101_000_00_00;
5 : get_id = 12'b11_110_000_00_00;
6 : get_id = 12'b11_111_000_00_00;
// l2m1 (CPU001)
7 : get_id = 12'b11_000_001_00_00;
8 : get_id = 12'b11_010_001_00_00;
9 : get_id = 12'b11_011_001_00_00;
10 : get_id = 12'b11_100_001_00_00;
11 : get_id = 12'b11_101_001_00_00;
12 : get_id = 12'b11_110_001_00_00;
13 : get_id = 12'b11_111_001_00_00;
endcase
if(use_id_no == 13)
use_id_no = 0;
else
use_id_no = use_id_no+1;
end
endfunction
/* Write data from file */
task automatic write_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] wr_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data;
integer bytes;
integer trnsfr_bytes;
integer wr_fd;
integer succ;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
bytes = wr_size;
wresp = 0;
concurrent = $random;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_bytes = (axi_burst_len * data_bus_width/8);
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wr_id = ID;
wr_fd = $fopen(file_name,"r");
while (bytes > 0) begin
repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction
wr_data = wr_data >> data_bus_width;
succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) ..
end
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes >= (axi_burst_len * data_bus_width/8) )
trnsfr_bytes = (axi_burst_len * data_bus_width/8); //
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data to file */
task automatic read_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] rd_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp, rrrsp;
reg [addr_width-1:0] addr;
integer bytes;
integer trnsfr_lngth;
reg [(axi_burst_len*data_bus_width)-1 :0] rd_data;
integer rd_fd;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
rresp = 0;
bytes = rd_size;
rd_id = ID;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rd_fd = $fopen(file_name,"w");
while (bytes > 0) begin
master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp);
repeat(trnsfr_lngth+1) begin
$fdisplayh(rd_fd,rd_data[data_bus_width-1:0]);
rd_data = rd_data >> data_bus_width;
end
addr = addr + (trnsfr_lngth+1)*4;
if(bytes >= (axi_burst_len * data_bus_width/8) )
bytes = bytes - (axi_burst_len * data_bus_width/8); //
else
bytes = 0;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rresp = rresp | rrrsp;
end /// while
response = rresp;
end
end
endtask
/* Write data (used for transfer size <= 128 Bytes */
task automatic write_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] wr_size;
input [(max_transfer_bytes*8)-1:0] w_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [7:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1:0] wr_data;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = wr_size;
wresp = 0;
wr_data = w_data;
concurrent = $random;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
wr_id = ID;
if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address
trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
wr_data = wr_data >> (trnsfr_bytes*8);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data (used for transfer size <= 128 Bytes */
task automatic read_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] rd_size;
output [(max_transfer_bytes*8)-1:0] r_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp,rdrsp;
reg [addr_width-1:0] addr;
reg [max_transfer_bytes_width:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1 : 0] rd_data;
reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data;
integer total_rcvd_bytes;
integer trnsfr_lngth;
integer i;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = rd_size;
rresp = 0;
total_rcvd_bytes = 0;
rd_data = 0;
rd_id = ID;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp);
for(i = 0; i < trnsfr_bytes; i = i+1) begin
rd_data = rd_data >> 8;
rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0];
rcv_rd_data = rcv_rd_data >> 8;
total_rcvd_bytes = total_rcvd_bytes+1;
end
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = 15;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
rresp = rresp | rdrsp;
end /// while
rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8;
r_data = rd_data;
response = rresp;
end
end
endtask
/* Wait Register Update in PL */
/* Issue a series of 1 burst length reads until the expected data pattern is received */
task automatic wait_reg_update;
input [addr_width-1:0] addri;
input [data_width-1:0] datai;
input [data_width-1:0] maski;
input [int_width-1:0] time_interval;
input [int_width-1:0] time_out;
output [data_width-1:0] data_o;
output upd_done;
reg [addr_width-1:0] addr;
reg [data_width-1:0] data_i;
reg [data_width-1:0] mask_i;
integer time_int;
integer timeout;
reg [axi_rsp_width-1:0] rdrsp;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
reg [data_width-1:0] rcv_data;
integer trnsfr_lngth;
reg rd_loop;
reg timed_out;
integer i;
integer cycle_cnt;
begin
addr = addri;
data_i = datai;
mask_i = maski;
time_int = time_interval;
timeout = time_out;
timed_out = 0;
cycle_cnt = 0;
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name);
upd_done = 0;
if(STOP_ON_ERROR) $stop;
end else begin
rd_id = ID;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
trnsfr_lngth = 0;
rd_loop = 1;
fork
begin
while(!timed_out & rd_loop) begin
cycle_cnt = cycle_cnt + 1;
if(cycle_cnt >= timeout) timed_out = 1;
@(posedge M_ACLK);
end
end
begin
while (rd_loop) begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr);
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp);
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data);
if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out)
rd_loop = 0;
else
repeat(time_int) @(posedge M_ACLK);
end /// while
end
join
data_o = rcv_data & ~mask_i;
if(timed_out) begin
$display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else
upd_done = 1;
end
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
// verilator lint_off BLKANDNBLK
reg [31:0] comcnt;
reg [31:0] dlycnt; initial dlycnt=0;
reg [31:0] lastdlycnt; initial lastdlycnt = 0;
reg [31:0] comrun; initial comrun = 0;
reg [31:0] comrunm1;
reg [31:0] dlyrun; initial dlyrun = 0;
reg [31:0] dlyrunm1;
always @ (posedge clk) begin
$write("[%0t] cyc %d\n",$time,cyc);
cyc <= cyc + 1;
if (cyc==2) begin
// Test # of iters
lastdlycnt = 0;
comcnt = 0;
dlycnt <= 0;
end
if (cyc==3) begin
dlyrun <= 5;
dlycnt <= 0;
end
if (cyc==4) begin
comrun = 4;
end
end
always @ (negedge clk) begin
if (cyc==5) begin
$display("%d %d\n", dlycnt, comcnt);
if (dlycnt != 32'd5) $stop;
if (comcnt != 32'd19) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// This forms a "loop" where we keep going through the always till comrun=0
reg runclk; initial runclk = 1'b0;
always @ (/*AS*/comrunm1 or dlycnt) begin
if (lastdlycnt != dlycnt) begin
comrun = 3;
$write ("[%0t] comrun=%0d start\n", $time, comrun);
end
else if (comrun > 0) begin
comrun = comrunm1;
if (comrunm1==1) begin
runclk = 1;
$write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun);
end
else $write ("[%0t] comrun=%0d\n", $time, comrun);
end
lastdlycnt = dlycnt;
end
always @ (/*AS*/comrun) begin
if (comrun!=0) begin
comrunm1 = comrun - 32'd1;
comcnt = comcnt + 32'd1;
$write("[%0t] comcnt=%0d\n",$time,comcnt);
end
end
// This forms a "loop" where we keep going through the always till dlyrun=0
reg runclkrst;
always @ (posedge runclk) begin
runclkrst <= 1;
$write ("[%0t] runclk\n", $time);
if (dlyrun > 0) begin
dlyrun <= dlyrun - 32'd1;
dlycnt <= dlycnt + 32'd1;
$write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1);
end
end
always @* begin
if (runclkrst) begin
$write ("[%0t] runclk reset\n", $time);
runclkrst = 0;
runclk = 0;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
// verilator lint_off BLKANDNBLK
reg [31:0] comcnt;
reg [31:0] dlycnt; initial dlycnt=0;
reg [31:0] lastdlycnt; initial lastdlycnt = 0;
reg [31:0] comrun; initial comrun = 0;
reg [31:0] comrunm1;
reg [31:0] dlyrun; initial dlyrun = 0;
reg [31:0] dlyrunm1;
always @ (posedge clk) begin
$write("[%0t] cyc %d\n",$time,cyc);
cyc <= cyc + 1;
if (cyc==2) begin
// Test # of iters
lastdlycnt = 0;
comcnt = 0;
dlycnt <= 0;
end
if (cyc==3) begin
dlyrun <= 5;
dlycnt <= 0;
end
if (cyc==4) begin
comrun = 4;
end
end
always @ (negedge clk) begin
if (cyc==5) begin
$display("%d %d\n", dlycnt, comcnt);
if (dlycnt != 32'd5) $stop;
if (comcnt != 32'd19) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// This forms a "loop" where we keep going through the always till comrun=0
reg runclk; initial runclk = 1'b0;
always @ (/*AS*/comrunm1 or dlycnt) begin
if (lastdlycnt != dlycnt) begin
comrun = 3;
$write ("[%0t] comrun=%0d start\n", $time, comrun);
end
else if (comrun > 0) begin
comrun = comrunm1;
if (comrunm1==1) begin
runclk = 1;
$write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun);
end
else $write ("[%0t] comrun=%0d\n", $time, comrun);
end
lastdlycnt = dlycnt;
end
always @ (/*AS*/comrun) begin
if (comrun!=0) begin
comrunm1 = comrun - 32'd1;
comcnt = comcnt + 32'd1;
$write("[%0t] comcnt=%0d\n",$time,comcnt);
end
end
// This forms a "loop" where we keep going through the always till dlyrun=0
reg runclkrst;
always @ (posedge runclk) begin
runclkrst <= 1;
$write ("[%0t] runclk\n", $time);
if (dlyrun > 0) begin
dlyrun <= dlyrun - 32'd1;
dlycnt <= dlycnt + 32'd1;
$write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1);
end
end
always @* begin
if (runclkrst) begin
$write ("[%0t] runclk reset\n", $time);
runclkrst = 0;
runclk = 0;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is responsible for accepting 128/256 bit descriptors and
buffering them in descriptor FIFOs. Each bytelane of the descriptor
can be written to individually and writing ot the descriptor 'go' bit
commits the data into the FIFO. Reading that data out of the FIFO
occurs two cycles after the read is asserted as the FIFOs do not support
lookahead mode.
This block must keep local copies of per descriptor information like
the optional sequence number or interrupt masks. When parked mode
is set in the descriptor the same will transfer multiple times when
the descriptor FIFO only contains one descriptor (and this descriptor
will not be popped). Parked mode is useful for video frame buffering.
1.0 - The on-chip memory in the FIFOs are not inferred so there may
be some extra unused bits. In a later Quartus II release the
on-chip memory will be replaced with inferred memory.
1.1 - Shifted all descriptor registers into this block (from the dispatcher
block). Added breakout blocks responsible for re-packing the
information for use by each master.
1.2 - Added the read_early_done_enable bit to the breakout (for debug)
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_buffers (
clk,
reset,
writedata,
write,
byteenable,
waitrequest,
read_command_valid,
read_command_ready,
read_command_data,
read_command_empty,
read_command_full,
read_command_used,
write_command_valid,
write_command_ready,
write_command_data,
write_command_empty,
write_command_full,
write_command_used,
stop_issuing_commands,
stop,
sw_reset,
sequence_number,
transfer_complete_IRQ_mask,
early_termination_IRQ_mask,
error_IRQ_mask
);
parameter MODE = 0;
parameter DATA_WIDTH = 256;
parameter BYTE_ENABLE_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // top level module can figure this out
input clk;
input reset;
input [DATA_WIDTH-1:0] writedata;
input write;
input [BYTE_ENABLE_WIDTH-1:0] byteenable;
output wire waitrequest;
output wire read_command_valid;
input read_command_ready;
output wire [255:0] read_command_data;
output wire read_command_empty;
output wire read_command_full;
output wire [FIFO_DEPTH_LOG2:0] read_command_used;
output wire write_command_valid;
input write_command_ready;
output wire [255:0] write_command_data;
output wire write_command_empty;
output wire write_command_full;
output wire [FIFO_DEPTH_LOG2:0] write_command_used;
input stop_issuing_commands;
input stop;
input sw_reset;
output wire [31:0] sequence_number;
output wire transfer_complete_IRQ_mask;
output wire early_termination_IRQ_mask;
output wire [7:0] error_IRQ_mask;
/* Internal wires and registers */
reg write_command_empty_d1;
reg write_command_empty_d2;
reg read_command_empty_d1;
reg read_command_empty_d2;
wire push_write_fifo;
wire pop_write_fifo;
wire push_read_fifo;
wire pop_read_fifo;
wire go_bit;
wire read_park;
wire read_park_enable; // park is enabled when read_park is enabled and the read FIFO is empty
wire write_park;
wire write_park_enable; // park is enabled when write_park is enabled and the write FIFO is empty
wire [DATA_WIDTH-1:0] write_fifo_output;
wire [DATA_WIDTH-1:0] read_fifo_output;
wire [15:0] write_sequence_number;
reg [15:0] write_sequence_number_d1;
wire [15:0] read_sequence_number;
reg [15:0] read_sequence_number_d1;
wire read_transfer_complete_IRQ_mask;
reg read_transfer_complete_IRQ_mask_d1;
wire write_transfer_complete_IRQ_mask;
reg write_transfer_complete_IRQ_mask_d1;
wire write_early_termination_IRQ_mask;
reg write_early_termination_IRQ_mask_d1;
wire [7:0] write_error_IRQ_mask;
reg [7:0] write_error_IRQ_mask_d1;
wire issue_write_descriptor; // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
wire issue_read_descriptor; // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
/* Unused signals that are provided for debug convenience */
wire [31:0] read_address;
wire [31:0] read_length;
wire [7:0] read_transmit_channel;
wire read_generate_sop;
wire read_generate_eop;
wire [7:0] read_burst_count;
wire [15:0] read_stride;
wire [7:0] read_transmit_error;
wire read_early_done_enable;
wire [31:0] write_address;
wire [31:0] write_length;
wire write_end_on_eop;
wire [7:0] write_burst_count;
wire [15:0] write_stride;
/************************************************* Registers *******************************************************/
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
write_sequence_number_d1 <= 0;
write_transfer_complete_IRQ_mask_d1 <= 0;
write_early_termination_IRQ_mask_d1 <= 0;
write_error_IRQ_mask_d1 <= 0;
end
else if (issue_write_descriptor) // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
begin
write_sequence_number_d1 <= write_sequence_number;
write_transfer_complete_IRQ_mask_d1 <= write_transfer_complete_IRQ_mask;
write_early_termination_IRQ_mask_d1 <= write_early_termination_IRQ_mask;
write_error_IRQ_mask_d1 <= write_error_IRQ_mask;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
read_sequence_number_d1 <= 0;
read_transfer_complete_IRQ_mask_d1 <= 0;
end
else if (issue_read_descriptor) // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
begin
read_sequence_number_d1 <= read_sequence_number;
read_transfer_complete_IRQ_mask_d1 <= read_transfer_complete_IRQ_mask;
end
end
// need to use a delayed valid signal since the commmand buffers have two cycles of latency
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
write_command_empty_d1 <= 0;
write_command_empty_d2 <= 0;
read_command_empty_d1 <= 0;
read_command_empty_d2 <= 0;
end
else
begin
write_command_empty_d1 <= write_command_empty;
write_command_empty_d2 <= write_command_empty_d1;
read_command_empty_d1 <= read_command_empty;
read_command_empty_d2 <= read_command_empty_d1;
end
end
/*********************************************** End Registers *****************************************************/
/****************************************** Module Instantiations **************************************************/
/* the write_signal_break module simply takes the output of the descriptor buffer and reformats the data
* to be sent in the command format needed by the master command port. If new features are added to the
* descriptor format then add it to this block. This block also provides the descriptor information
* using a naming convention isn't of bit indexes in a 256 bit wide command signal.
*/
write_signal_breakout the_write_signal_breakout (
.write_command_data_in (write_fifo_output),
.write_command_data_out (write_command_data),
.write_address (write_address),
.write_length (write_length),
.write_park (write_park),
.write_end_on_eop (write_end_on_eop),
.write_transfer_complete_IRQ_mask (write_transfer_complete_IRQ_mask),
.write_early_termination_IRQ_mask (write_early_termination_IRQ_mask),
.write_error_IRQ_mask (write_error_IRQ_mask),
.write_burst_count (write_burst_count),
.write_stride (write_stride),
.write_sequence_number (write_sequence_number),
.write_stop (stop),
.write_sw_reset (sw_reset)
);
defparam the_write_signal_breakout.DATA_WIDTH = DATA_WIDTH;
/* the read_signal_break module simply takes the output of the descriptor buffer and reformats the data
* to be sent in the command format needed by the master command port. If new features are added to the
* descriptor format then add it to this block. This block also provides the descriptor information
* using a naming convention isn't of bit indexes in a 256 bit wide command signal.
*/
read_signal_breakout the_read_signal_breakout (
.read_command_data_in (read_fifo_output),
.read_command_data_out (read_command_data),
.read_address (read_address),
.read_length (read_length),
.read_transmit_channel (read_transmit_channel),
.read_generate_sop (read_generate_sop),
.read_generate_eop (read_generate_eop),
.read_park (read_park),
.read_transfer_complete_IRQ_mask (read_transfer_complete_IRQ_mask),
.read_burst_count (read_burst_count),
.read_stride (read_stride),
.read_sequence_number (read_sequence_number),
.read_transmit_error (read_transmit_error),
.read_early_done_enable (read_early_done_enable),
.read_stop (stop),
.read_sw_reset (sw_reset)
);
defparam the_read_signal_breakout.DATA_WIDTH = DATA_WIDTH;
// Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
// This differs from scfifo which commits the data any time the write signal is asserted.
fifo_with_byteenables the_read_command_FIFO (
.clk (clk),
.areset (reset),
.sreset (sw_reset),
.write_data (writedata),
.write_byteenables (byteenable),
.write (write),
.push (push_read_fifo),
.read_data (read_fifo_output),
.pop (pop_read_fifo),
.used (read_command_used), // this is a 'true used' signal with the full bit accounted for
.full (read_command_full),
.empty (read_command_empty)
);
defparam the_read_command_FIFO.DATA_WIDTH = DATA_WIDTH; // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
defparam the_read_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
defparam the_read_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam the_read_command_FIFO.LATENCY = 2;
// Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
// This differs from scfifo which commits the data any time the write signal is asserted.
fifo_with_byteenables the_write_command_FIFO (
.clk (clk),
.areset (reset),
.sreset (sw_reset),
.write_data (writedata),
.write_byteenables (byteenable),
.write (write),
.push (push_write_fifo),
.read_data (write_fifo_output),
.pop (pop_write_fifo),
.used (write_command_used), // this is a 'true used' signal with the full bit accounted for
.full (write_command_full),
.empty (write_command_empty)
);
defparam the_write_command_FIFO.DATA_WIDTH = DATA_WIDTH; // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
defparam the_write_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
defparam the_write_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam the_write_command_FIFO.LATENCY = 2;
/**************************************** End Module Instantiations ************************************************/
/****************************************** Combinational Signals **************************************************/
generate // all unnecessary signals and drivers will be optimized away
if (MODE == 0) // MM-->MM
begin
assign waitrequest = (read_command_full == 1) | (write_command_full == 1);
// information for the CSR or response blocks to use
assign sequence_number = {write_sequence_number_d1, read_sequence_number_d1};
assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = 1'b0;
assign error_IRQ_mask = 8'h00;
// read buffer flow control
assign push_read_fifo = go_bit;
assign read_park_enable = (read_park == 1) & (read_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0); // don't want to pop the fifo if we are in parked mode
// write buffer flow control
assign push_write_fifo = go_bit;
assign write_park_enable = (write_park == 1) & (write_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0); // don't want to pop the fifo if we are in parked mode
end
else if (MODE == 1) // MM-->ST
begin
// information for the CSR or response blocks to use
assign sequence_number = {16'h0000, read_sequence_number_d1};
assign transfer_complete_IRQ_mask = read_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = 1'b0;
assign error_IRQ_mask = 8'h00;
assign waitrequest = (read_command_full == 1);
// read buffer flow control
assign push_read_fifo = go_bit;
assign read_park_enable = (read_park == 1) & (read_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0); // don't want to pop the fifo if we are in parked mode
// write buffer flow control
assign push_write_fifo = 0;
assign write_park_enable = 0;
assign write_command_valid = 0;
assign issue_write_descriptor = 0;
assign pop_write_fifo = 0;
end
else // ST-->MM
begin
// information for the CSR or response blocks to use
assign sequence_number = {write_sequence_number_d1, 16'h0000};
assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = write_early_termination_IRQ_mask_d1;
assign error_IRQ_mask = write_error_IRQ_mask_d1;
assign waitrequest = (write_command_full == 1);
// read buffer flow control
assign push_read_fifo = 0;
assign read_park_enable = 0;
assign read_command_valid = 0;
assign issue_read_descriptor = 0;
assign pop_read_fifo = 0;
// write buffer flow control
assign push_write_fifo = go_bit;
assign write_park_enable = (write_park == 1) & (write_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0); // don't want to pop the fifo if we are in parked mode
end
endgenerate
generate // go bit is in a different location depending on the width of the slave port
if (DATA_WIDTH == 256)
begin
assign go_bit = (writedata[255] == 1) & (write == 1) & (byteenable[31] == 1) & (waitrequest == 0);
end
else
begin
assign go_bit = (writedata[127] == 1) & (write == 1) & (byteenable[15] == 1) & (waitrequest == 0);
end
endgenerate
/**************************************** End Combinational Signals ************************************************/
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/23/2009
Version 2.1
This logic recieves Avalon Memory Mapped read data and translates it into
the Avalon Streaming format. The ST format requires all data to be packed
until the final transfer when packet support is enabled. As a result when
you enable unaligned acceses the data from two sucessive reads must be
combined to form a single word of data. If you disable packet support
and unaligned access support this block will synthesize into wires.
This block does not provide any read throttling as it simply acts as a format
adapter between the read master port and the read master FIFO. All throttling
should be provided by the read master to prevent overflow. Since this logic
sits on the MM side of the FIFO the bytes are in 'little endian' format and
will get swapped around on the other side of the FIFO (symbol size can be adjusted
there too).
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address and length signals
instead to determine how much out of alignment the master begins.
2.1 Changed the extra last access logic to be based on the descriptor address
and length as apposed to the counter values. Created a new 'length_counter'
input to determine when the last read has arrived.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module MM_to_ST_Adapter (
clk,
reset,
length,
length_counter,
address,
reads_pending,
start,
readdata,
readdatavalid,
fifo_data,
fifo_write,
fifo_empty,
fifo_sop,
fifo_eop
);
parameter DATA_WIDTH = 32; // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses)
parameter LENGTH_WIDTH = 32;
parameter ADDRESS_WIDTH = 32;
parameter BYTE_ADDRESS_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter READS_PENDING_WIDTH = 5;
parameter EMPTY_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter PACKET_SUPPORT = 1; // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded
// only set one of these at a time
parameter UNALIGNED_ACCESS_ENABLE = 1; // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY')
parameter FULL_WORD_ACCESS_ONLY = 0; // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary).
input clk;
input reset;
input [LENGTH_WIDTH-1:0] length;
input [LENGTH_WIDTH-1:0] length_counter;
input [ADDRESS_WIDTH-1:0] address;
input [READS_PENDING_WIDTH-1:0] reads_pending;
input start; // one cycle strobe at the start of a transfer used to capture bytes_to_transfer
input [DATA_WIDTH-1:0] readdata;
input readdatavalid;
output wire [DATA_WIDTH-1:0] fifo_data;
output wire fifo_write;
output wire [EMPTY_WIDTH-1:0] fifo_empty;
output wire fifo_sop;
output wire fifo_eop;
// internal registers and wires
reg [DATA_WIDTH-1:0] readdata_d1;
reg readdatavalid_d1;
wire [DATA_WIDTH-1:0] data_in; // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled
wire valid_in; // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled
reg valid_in_d1;
wire [DATA_WIDTH-1:0] barrelshifter_A; // shifted current read data
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1; // shifted previously read data
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
wire extra_access_enable;
reg extra_access;
wire last_unaligned_fifo_write;
reg first_access_seen;
reg second_access_seen;
wire first_access_seen_rising_edge;
wire second_access_seen_rising_edge;
reg [BYTE_ADDRESS_WIDTH-1:0] byte_address;
reg [EMPTY_WIDTH-1:0] last_empty; // only the last word written into the FIFO can have empty bytes
reg start_and_end_same_cycle; // when the amount of data to transfer is only a full word or less
generate
if (UNALIGNED_ACCESS_ENABLE == 1) // unaligned so using a pipelined input
begin
assign data_in = readdata_d1;
assign valid_in = readdatavalid_d1;
end
else
begin
assign data_in = readdata; // no barrelshifters in this case so pipelining is not necessary
assign valid_in = readdatavalid;
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else
begin
if (readdatavalid == 1)
begin
readdata_d1 <= readdata;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdatavalid_d1 <= 0;
valid_in_d1 <= 0;
end
else
begin
readdatavalid_d1 <= readdatavalid;
valid_in_d1 <= valid_in; // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (valid_in == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access_seen <= 0;
end
else
begin
if (start == 1)
begin
first_access_seen <= 0;
end
else if (valid_in == 1)
begin
first_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
second_access_seen <= 0;
end
else
begin
if (start == 1)
begin
second_access_seen <= 0;
end
else if ((first_access_seen == 1) & (valid_in == 1))
begin
second_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
byte_address <= 0;
end
else if (start == 1)
begin
byte_address <= address[BYTE_ADDRESS_WIDTH-1:0];
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
last_empty <= 0;
end
else if (start == 1)
begin
last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}; // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
extra_access <= 0;
end
else if (start == 1)
begin
extra_access <= extra_access_enable; // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only)
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_and_end_same_cycle <= 0;
end
else if (start == 1)
begin
start_and_end_same_cycle <= (length <= (DATA_WIDTH/8));
end
end
/* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word.
Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered. This allows both barrelshifters
to be logically OR'ed together to form a single packed word. Shifter A is used to shift the current read data towards the upper bytes of the
combined word (since those are the upper addresses of the combined word). Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains
the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word).
*/
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset));
assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset);
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[byte_address]; // upper portion of the packed word
assign barrelshifter_B = barrelshifter_input_B[byte_address]; // lower portion of the packed word (will be pipelined so it will be the previous word read by the master)
assign combined_word = (barrelshifter_A | barrelshifter_B_d1); // barrelshifters shift in zeros so we can just OR the words together here to create a packed word
assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0);
assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0);
assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0]; // enable when empty >= byte address
/* Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses
is enabled. The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases
when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write.
In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write
to the FIFO will immediately follow the last read.
*/
assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) &
( ((extra_access == 0) & (valid_in == 1)) | // don't need a pipeline flush
((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0)) ); // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined)
// This block should be optimized down depending on the packet support or access type settings. In the case where packet support is off
// and only full accesses are used this block should become zero logic elements.
generate
if (PACKET_SUPPORT == 1)
begin
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1));
assign fifo_eop = last_unaligned_fifo_write;
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
else
begin
assign fifo_sop = first_access_seen_rising_edge;
assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1); // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined
if (FULL_WORD_ACCESS_ONLY == 1)
begin
assign fifo_empty = 0; // full accesses so no empty symbols throughout the transfer
end
else
begin
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
end
end
else
begin
assign fifo_eop = 0;
assign fifo_sop = 0;
assign fifo_empty = 0;
end
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_data = combined_word;
assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1)); // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed
end
else
begin // don't need to pipeline since the data will not go through the barrel shifters
assign fifo_data = data_in; // don't need to barrelshift when aligned accesses are used
assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/23/2009
Version 2.1
This logic recieves Avalon Memory Mapped read data and translates it into
the Avalon Streaming format. The ST format requires all data to be packed
until the final transfer when packet support is enabled. As a result when
you enable unaligned acceses the data from two sucessive reads must be
combined to form a single word of data. If you disable packet support
and unaligned access support this block will synthesize into wires.
This block does not provide any read throttling as it simply acts as a format
adapter between the read master port and the read master FIFO. All throttling
should be provided by the read master to prevent overflow. Since this logic
sits on the MM side of the FIFO the bytes are in 'little endian' format and
will get swapped around on the other side of the FIFO (symbol size can be adjusted
there too).
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address and length signals
instead to determine how much out of alignment the master begins.
2.1 Changed the extra last access logic to be based on the descriptor address
and length as apposed to the counter values. Created a new 'length_counter'
input to determine when the last read has arrived.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module MM_to_ST_Adapter (
clk,
reset,
length,
length_counter,
address,
reads_pending,
start,
readdata,
readdatavalid,
fifo_data,
fifo_write,
fifo_empty,
fifo_sop,
fifo_eop
);
parameter DATA_WIDTH = 32; // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses)
parameter LENGTH_WIDTH = 32;
parameter ADDRESS_WIDTH = 32;
parameter BYTE_ADDRESS_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter READS_PENDING_WIDTH = 5;
parameter EMPTY_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter PACKET_SUPPORT = 1; // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded
// only set one of these at a time
parameter UNALIGNED_ACCESS_ENABLE = 1; // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY')
parameter FULL_WORD_ACCESS_ONLY = 0; // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary).
input clk;
input reset;
input [LENGTH_WIDTH-1:0] length;
input [LENGTH_WIDTH-1:0] length_counter;
input [ADDRESS_WIDTH-1:0] address;
input [READS_PENDING_WIDTH-1:0] reads_pending;
input start; // one cycle strobe at the start of a transfer used to capture bytes_to_transfer
input [DATA_WIDTH-1:0] readdata;
input readdatavalid;
output wire [DATA_WIDTH-1:0] fifo_data;
output wire fifo_write;
output wire [EMPTY_WIDTH-1:0] fifo_empty;
output wire fifo_sop;
output wire fifo_eop;
// internal registers and wires
reg [DATA_WIDTH-1:0] readdata_d1;
reg readdatavalid_d1;
wire [DATA_WIDTH-1:0] data_in; // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled
wire valid_in; // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled
reg valid_in_d1;
wire [DATA_WIDTH-1:0] barrelshifter_A; // shifted current read data
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1; // shifted previously read data
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
wire extra_access_enable;
reg extra_access;
wire last_unaligned_fifo_write;
reg first_access_seen;
reg second_access_seen;
wire first_access_seen_rising_edge;
wire second_access_seen_rising_edge;
reg [BYTE_ADDRESS_WIDTH-1:0] byte_address;
reg [EMPTY_WIDTH-1:0] last_empty; // only the last word written into the FIFO can have empty bytes
reg start_and_end_same_cycle; // when the amount of data to transfer is only a full word or less
generate
if (UNALIGNED_ACCESS_ENABLE == 1) // unaligned so using a pipelined input
begin
assign data_in = readdata_d1;
assign valid_in = readdatavalid_d1;
end
else
begin
assign data_in = readdata; // no barrelshifters in this case so pipelining is not necessary
assign valid_in = readdatavalid;
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else
begin
if (readdatavalid == 1)
begin
readdata_d1 <= readdata;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdatavalid_d1 <= 0;
valid_in_d1 <= 0;
end
else
begin
readdatavalid_d1 <= readdatavalid;
valid_in_d1 <= valid_in; // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (valid_in == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access_seen <= 0;
end
else
begin
if (start == 1)
begin
first_access_seen <= 0;
end
else if (valid_in == 1)
begin
first_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
second_access_seen <= 0;
end
else
begin
if (start == 1)
begin
second_access_seen <= 0;
end
else if ((first_access_seen == 1) & (valid_in == 1))
begin
second_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
byte_address <= 0;
end
else if (start == 1)
begin
byte_address <= address[BYTE_ADDRESS_WIDTH-1:0];
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
last_empty <= 0;
end
else if (start == 1)
begin
last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}; // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
extra_access <= 0;
end
else if (start == 1)
begin
extra_access <= extra_access_enable; // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only)
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_and_end_same_cycle <= 0;
end
else if (start == 1)
begin
start_and_end_same_cycle <= (length <= (DATA_WIDTH/8));
end
end
/* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word.
Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered. This allows both barrelshifters
to be logically OR'ed together to form a single packed word. Shifter A is used to shift the current read data towards the upper bytes of the
combined word (since those are the upper addresses of the combined word). Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains
the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word).
*/
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset));
assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset);
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[byte_address]; // upper portion of the packed word
assign barrelshifter_B = barrelshifter_input_B[byte_address]; // lower portion of the packed word (will be pipelined so it will be the previous word read by the master)
assign combined_word = (barrelshifter_A | barrelshifter_B_d1); // barrelshifters shift in zeros so we can just OR the words together here to create a packed word
assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0);
assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0);
assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0]; // enable when empty >= byte address
/* Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses
is enabled. The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases
when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write.
In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write
to the FIFO will immediately follow the last read.
*/
assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) &
( ((extra_access == 0) & (valid_in == 1)) | // don't need a pipeline flush
((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0)) ); // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined)
// This block should be optimized down depending on the packet support or access type settings. In the case where packet support is off
// and only full accesses are used this block should become zero logic elements.
generate
if (PACKET_SUPPORT == 1)
begin
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1));
assign fifo_eop = last_unaligned_fifo_write;
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
else
begin
assign fifo_sop = first_access_seen_rising_edge;
assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1); // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined
if (FULL_WORD_ACCESS_ONLY == 1)
begin
assign fifo_empty = 0; // full accesses so no empty symbols throughout the transfer
end
else
begin
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
end
end
else
begin
assign fifo_eop = 0;
assign fifo_sop = 0;
assign fifo_empty = 0;
end
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_data = combined_word;
assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1)); // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed
end
else
begin // don't need to pipeline since the data will not go through the barrel shifters
assign fifo_data = data_in; // don't need to barrelshift when aligned accesses are used
assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory
end
endgenerate
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Low latency FIFO
// One cycle latency from all inputs to all outputs
// Storage implemented in registers, not memory.
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for(i = 0; i < DEPTH; i++)
begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for(i = 0; i < DEPTH-1; i++)
begin : data_reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[i] <= {WIDTH{1'b0}};
else
data[i] <= data_hold[i] ? data[i] :
data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[DEPTH-1] <= {WIDTH{1'b0}};
else
data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end
else
begin
wptr <= wptr_hold ? wptr :
wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign data_out = data[0];
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Low latency FIFO
// One cycle latency from all inputs to all outputs
// Storage implemented in registers, not memory.
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for(i = 0; i < DEPTH; i++)
begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for(i = 0; i < DEPTH-1; i++)
begin : data_reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[i] <= {WIDTH{1'b0}};
else
data[i] <= data_hold[i] ? data[i] :
data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[DEPTH-1] <= {WIDTH{1'b0}};
else
data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end
else
begin
wptr <= wptr_hold ? wptr :
wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign data_out = data[0];
endmodule
|
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
// Register snoop data first
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
// 1) Fifo to store snooped accesses from host
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
// Overflow piggy backed onto MSB of stream. Since overflow guarantees
// there is something to be read out, we can be sure that this will reach
// the cache.
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule
|
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
// Register snoop data first
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
// 1) Fifo to store snooped accesses from host
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
// Overflow piggy backed onto MSB of stream. Since overflow guarantees
// there is something to be read out, we can be sure that this will reach
// the cache.
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/21/2009
Version 1.3
This logic recieves a potentially unsupported byte enable combination and
breaks it down into supported byte enable combinations to the fabric.
For example if a 64-bit write master wants to write
to addresses 0x1 and beyond, this maps to address 0x0 with byte enables
"11111110" asserted. This does not contain a power of two of neighbooring
asserted bits. Instead this block will convert this into three writes
all of which are supported: "00000010", "00001100", and "11110000". When
this block breaks a transfer down it asserts stall so that the rest of the
master logic will keep the outputs constant.
Revision History:
1.0 Initial version - Used a word distance to calculate which lanes to enable.
1.1 Re-encoded version - Uses byte enables directly to calculate which lanes
to enable. This allows byte enables in the middle
of a word to be supported as well such as '0110'.
1.2 Bug fix to include the waitrequest for state transitions when the byte
enable width is greater than 2.
1.3 Added support for 64 and 128-bit byte enables (for 512/1024 bit data paths)
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module byte_enable_generator (
clk,
reset,
// master side
write_in,
byteenable_in,
waitrequest_out,
// fabric side
byteenable_out,
waitrequest_in
);
parameter BYTEENABLE_WIDTH = 4; // valid byteenable widths are 1, 2, 4, 8, 16, 32, 64, and 128
input clk;
input reset;
input write_in; // will enable state machine logic
input [BYTEENABLE_WIDTH-1:0] byteenable_in; // byteenables from master which contain unsupported groupings of byte lanes to be converted
output wire waitrequest_out; // used to stall the master when fabric asserts waitrequest or access needs to be broken down
output wire [BYTEENABLE_WIDTH-1:0] byteenable_out; // supported byte enables to the fabric
input waitrequest_in; // waitrequest from the fabric
generate
if (BYTEENABLE_WIDTH == 1) // for completeness...
begin
assign byteenable_out = byteenable_in;
assign waitrequest_out = waitrequest_in;
end
else if (BYTEENABLE_WIDTH == 2)
begin
sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM ( // pass through for the most part like the 1 bit case, has it's own module since the 4 bit module uses it
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 4)
begin
thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 8)
begin
sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 16)
begin
one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 32)
begin
two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 64)
begin
five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 128)
begin
one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
endgenerate
endmodule
module one_thousand_twenty_four_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [127:0] byteenable_in;
output wire waitrequest_out;
output wire [127:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[63:0] != 0);
assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[127:64] != 0);
assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[63:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[63:0]),
.waitrequest_in (waitrequest_in)
);
five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[127:64]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[127:64]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module five_hundred_twelve_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [63:0] byteenable_in;
output wire waitrequest_out;
output wire [63:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[31:0] != 0);
assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[63:32] != 0);
assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[31:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[31:0]),
.waitrequest_in (waitrequest_in)
);
two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[63:32]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[63:32]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module two_hundred_fifty_six_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [31:0] byteenable_in;
output wire waitrequest_out;
output wire [31:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[15:0] != 0);
assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF);
assign partial_upper_half_transfer = (byteenable_in[31:16] != 0);
assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[15:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[15:0]),
.waitrequest_in (waitrequest_in)
);
one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[31:16]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[31:16]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module one_hundred_twenty_eight_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [15:0] byteenable_in;
output wire waitrequest_out;
output wire [15:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[7:0] != 0);
assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF);
assign partial_upper_half_transfer = (byteenable_in[15:8] != 0);
assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[7:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[7:0]),
.waitrequest_in (waitrequest_in)
);
sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[15:8]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[15:8]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module sixty_four_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [7:0] byteenable_in;
output wire waitrequest_out;
output wire [7:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[3:0] != 0);
assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF);
assign partial_upper_half_transfer = (byteenable_in[7:4] != 0);
assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[3:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[3:0]),
.waitrequest_in (waitrequest_in)
);
thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[7:4]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[7:4]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module thirty_two_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [3:0] byteenable_in;
output wire waitrequest_out;
output wire [3:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[1:0] != 0);
assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3);
assign partial_upper_half_transfer = (byteenable_in[3:2] != 0);
assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM (
.write_in (lower_enable),
.byteenable_in (byteenable_in[1:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[1:0]),
.waitrequest_in (waitrequest_in)
);
sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM (
.write_in (upper_enable),
.byteenable_in (byteenable_in[3:2]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[3:2]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
/**************************************************************************************************
Fundament byte enable state machine for which 32, 64, 128, 256, 512, and 1024 bit byte enable
statemachines will use to operate on groups of two byte enables.
***************************************************************************************************/
module sixteen_bit_byteenable_FSM (
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input write_in;
input [1:0] byteenable_in;
output wire waitrequest_out;
output wire [1:0] byteenable_out;
input waitrequest_in;
assign byteenable_out = byteenable_in & {2{write_in}}; // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled
assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1); // transfer always completes on the first cycle unless waitrequest is asserted
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/21/2009
Version 1.3
This logic recieves a potentially unsupported byte enable combination and
breaks it down into supported byte enable combinations to the fabric.
For example if a 64-bit write master wants to write
to addresses 0x1 and beyond, this maps to address 0x0 with byte enables
"11111110" asserted. This does not contain a power of two of neighbooring
asserted bits. Instead this block will convert this into three writes
all of which are supported: "00000010", "00001100", and "11110000". When
this block breaks a transfer down it asserts stall so that the rest of the
master logic will keep the outputs constant.
Revision History:
1.0 Initial version - Used a word distance to calculate which lanes to enable.
1.1 Re-encoded version - Uses byte enables directly to calculate which lanes
to enable. This allows byte enables in the middle
of a word to be supported as well such as '0110'.
1.2 Bug fix to include the waitrequest for state transitions when the byte
enable width is greater than 2.
1.3 Added support for 64 and 128-bit byte enables (for 512/1024 bit data paths)
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module byte_enable_generator (
clk,
reset,
// master side
write_in,
byteenable_in,
waitrequest_out,
// fabric side
byteenable_out,
waitrequest_in
);
parameter BYTEENABLE_WIDTH = 4; // valid byteenable widths are 1, 2, 4, 8, 16, 32, 64, and 128
input clk;
input reset;
input write_in; // will enable state machine logic
input [BYTEENABLE_WIDTH-1:0] byteenable_in; // byteenables from master which contain unsupported groupings of byte lanes to be converted
output wire waitrequest_out; // used to stall the master when fabric asserts waitrequest or access needs to be broken down
output wire [BYTEENABLE_WIDTH-1:0] byteenable_out; // supported byte enables to the fabric
input waitrequest_in; // waitrequest from the fabric
generate
if (BYTEENABLE_WIDTH == 1) // for completeness...
begin
assign byteenable_out = byteenable_in;
assign waitrequest_out = waitrequest_in;
end
else if (BYTEENABLE_WIDTH == 2)
begin
sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM ( // pass through for the most part like the 1 bit case, has it's own module since the 4 bit module uses it
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 4)
begin
thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 8)
begin
sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 16)
begin
one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 32)
begin
two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 64)
begin
five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 128)
begin
one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
endgenerate
endmodule
module one_thousand_twenty_four_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [127:0] byteenable_in;
output wire waitrequest_out;
output wire [127:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[63:0] != 0);
assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[127:64] != 0);
assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[63:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[63:0]),
.waitrequest_in (waitrequest_in)
);
five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[127:64]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[127:64]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module five_hundred_twelve_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [63:0] byteenable_in;
output wire waitrequest_out;
output wire [63:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[31:0] != 0);
assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[63:32] != 0);
assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[31:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[31:0]),
.waitrequest_in (waitrequest_in)
);
two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[63:32]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[63:32]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module two_hundred_fifty_six_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [31:0] byteenable_in;
output wire waitrequest_out;
output wire [31:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[15:0] != 0);
assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF);
assign partial_upper_half_transfer = (byteenable_in[31:16] != 0);
assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[15:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[15:0]),
.waitrequest_in (waitrequest_in)
);
one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[31:16]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[31:16]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module one_hundred_twenty_eight_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [15:0] byteenable_in;
output wire waitrequest_out;
output wire [15:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[7:0] != 0);
assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF);
assign partial_upper_half_transfer = (byteenable_in[15:8] != 0);
assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[7:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[7:0]),
.waitrequest_in (waitrequest_in)
);
sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[15:8]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[15:8]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module sixty_four_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [7:0] byteenable_in;
output wire waitrequest_out;
output wire [7:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[3:0] != 0);
assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF);
assign partial_upper_half_transfer = (byteenable_in[7:4] != 0);
assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[3:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[3:0]),
.waitrequest_in (waitrequest_in)
);
thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[7:4]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[7:4]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module thirty_two_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [3:0] byteenable_in;
output wire waitrequest_out;
output wire [3:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[1:0] != 0);
assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3);
assign partial_upper_half_transfer = (byteenable_in[3:2] != 0);
assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM (
.write_in (lower_enable),
.byteenable_in (byteenable_in[1:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[1:0]),
.waitrequest_in (waitrequest_in)
);
sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM (
.write_in (upper_enable),
.byteenable_in (byteenable_in[3:2]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[3:2]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
/**************************************************************************************************
Fundament byte enable state machine for which 32, 64, 128, 256, 512, and 1024 bit byte enable
statemachines will use to operate on groups of two byte enables.
***************************************************************************************************/
module sixteen_bit_byteenable_FSM (
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input write_in;
input [1:0] byteenable_in;
output wire waitrequest_out;
output wire [1:0] byteenable_out;
input waitrequest_in;
assign byteenable_out = byteenable_in & {2{write_in}}; // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled
assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1); // transfer always completes on the first cycle unless waitrequest is asserted
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/21/2009
Version 1.3
This logic recieves a potentially unsupported byte enable combination and
breaks it down into supported byte enable combinations to the fabric.
For example if a 64-bit write master wants to write
to addresses 0x1 and beyond, this maps to address 0x0 with byte enables
"11111110" asserted. This does not contain a power of two of neighbooring
asserted bits. Instead this block will convert this into three writes
all of which are supported: "00000010", "00001100", and "11110000". When
this block breaks a transfer down it asserts stall so that the rest of the
master logic will keep the outputs constant.
Revision History:
1.0 Initial version - Used a word distance to calculate which lanes to enable.
1.1 Re-encoded version - Uses byte enables directly to calculate which lanes
to enable. This allows byte enables in the middle
of a word to be supported as well such as '0110'.
1.2 Bug fix to include the waitrequest for state transitions when the byte
enable width is greater than 2.
1.3 Added support for 64 and 128-bit byte enables (for 512/1024 bit data paths)
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module byte_enable_generator (
clk,
reset,
// master side
write_in,
byteenable_in,
waitrequest_out,
// fabric side
byteenable_out,
waitrequest_in
);
parameter BYTEENABLE_WIDTH = 4; // valid byteenable widths are 1, 2, 4, 8, 16, 32, 64, and 128
input clk;
input reset;
input write_in; // will enable state machine logic
input [BYTEENABLE_WIDTH-1:0] byteenable_in; // byteenables from master which contain unsupported groupings of byte lanes to be converted
output wire waitrequest_out; // used to stall the master when fabric asserts waitrequest or access needs to be broken down
output wire [BYTEENABLE_WIDTH-1:0] byteenable_out; // supported byte enables to the fabric
input waitrequest_in; // waitrequest from the fabric
generate
if (BYTEENABLE_WIDTH == 1) // for completeness...
begin
assign byteenable_out = byteenable_in;
assign waitrequest_out = waitrequest_in;
end
else if (BYTEENABLE_WIDTH == 2)
begin
sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM ( // pass through for the most part like the 1 bit case, has it's own module since the 4 bit module uses it
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 4)
begin
thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 8)
begin
sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 16)
begin
one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 32)
begin
two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM(
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 64)
begin
five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
else if (BYTEENABLE_WIDTH == 128)
begin
one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (write_in),
.byteenable_in (byteenable_in),
.waitrequest_out (waitrequest_out),
.byteenable_out (byteenable_out),
.waitrequest_in (waitrequest_in)
);
end
endgenerate
endmodule
module one_thousand_twenty_four_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [127:0] byteenable_in;
output wire waitrequest_out;
output wire [127:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[63:0] != 0);
assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[127:64] != 0);
assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[63:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[63:0]),
.waitrequest_in (waitrequest_in)
);
five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[127:64]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[127:64]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module five_hundred_twelve_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [63:0] byteenable_in;
output wire waitrequest_out;
output wire [63:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[31:0] != 0);
assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[63:32] != 0);
assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[31:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[31:0]),
.waitrequest_in (waitrequest_in)
);
two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[63:32]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[63:32]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module two_hundred_fifty_six_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [31:0] byteenable_in;
output wire waitrequest_out;
output wire [31:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[15:0] != 0);
assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF);
assign partial_upper_half_transfer = (byteenable_in[31:16] != 0);
assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[15:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[15:0]),
.waitrequest_in (waitrequest_in)
);
one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[31:16]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[31:16]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module one_hundred_twenty_eight_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [15:0] byteenable_in;
output wire waitrequest_out;
output wire [15:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[7:0] != 0);
assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF);
assign partial_upper_half_transfer = (byteenable_in[15:8] != 0);
assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[7:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[7:0]),
.waitrequest_in (waitrequest_in)
);
sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[15:8]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[15:8]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module sixty_four_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [7:0] byteenable_in;
output wire waitrequest_out;
output wire [7:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[3:0] != 0);
assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF);
assign partial_upper_half_transfer = (byteenable_in[7:4] != 0);
assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (lower_enable),
.byteenable_in (byteenable_in[3:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[3:0]),
.waitrequest_in (waitrequest_in)
);
thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM (
.clk (clk),
.reset (reset),
.write_in (upper_enable),
.byteenable_in (byteenable_in[7:4]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[7:4]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
module thirty_two_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [3:0] byteenable_in;
output wire waitrequest_out;
output wire [3:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
state_bit <= 0;
end
else
begin
if (transfer_done == 1)
begin
state_bit <= 0;
end
else if (advance_to_next_state == 1)
begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[1:0] != 0);
assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3);
assign partial_upper_half_transfer = (byteenable_in[3:2] != 0);
assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM (
.write_in (lower_enable),
.byteenable_in (byteenable_in[1:0]),
.waitrequest_out (lower_stall),
.byteenable_out (byteenable_out[1:0]),
.waitrequest_in (waitrequest_in)
);
sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM (
.write_in (upper_enable),
.byteenable_in (byteenable_in[3:2]),
.waitrequest_out (upper_stall),
.byteenable_out (byteenable_out[3:2]),
.waitrequest_in (waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
/**************************************************************************************************
Fundament byte enable state machine for which 32, 64, 128, 256, 512, and 1024 bit byte enable
statemachines will use to operate on groups of two byte enables.
***************************************************************************************************/
module sixteen_bit_byteenable_FSM (
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input write_in;
input [1:0] byteenable_in;
output wire waitrequest_out;
output wire [1:0] byteenable_out;
input waitrequest_in;
assign byteenable_out = byteenable_in & {2{write_in}}; // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled
assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1); // transfer always completes on the first cycle unless waitrequest is asserted
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized 16/32 word deep FIFO.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_0_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule
|
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
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