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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_a888_one_0_H_
#define _bd_a888_one_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class bd_a888_one_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_a888_one_0 (sc_core::sc_module_name name);
};
#endif
|
#include <systemc.h>
#include "SYSTEM.h"
|
#ifndef MEMORY_TLM_HPP
#define MEMORY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../src/img_target.cpp"
#include "address_map.hpp"
//Extended Unification TLM
struct memory_tlm : public img_target
{
memory_tlm(sc_module_name name) : img_target((std::string(name) + "_target").c_str()) {
mem_array = new unsigned char[MEMORY_SIZE];
#ifdef DISABLE_MEM_DEBUG
this->use_prints = false;
#endif //DISABLE_MEM_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_write(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
unsigned char* mem_array;
sc_uint<64> mem_data;
sc_uint<24> mem_address;
sc_uint<1> mem_we;
};
#endif // MEMORY_TLM_HPP
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _acorn128_dec_onebyte_HH_
#define _acorn128_dec_onebyte_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit.h"
#include "acorn128_dec_onebyte_AXILiteS_s_axi.h"
namespace ap_rtl {
template<unsigned int C_S_AXI_AXILITES_ADDR_WIDTH = 11,
unsigned int C_S_AXI_AXILITES_DATA_WIDTH = 32>
struct acorn128_dec_onebyte : public sc_module {
// Port declarations 20
sc_in< sc_logic > s_axi_AXILiteS_AWVALID;
sc_out< sc_logic > s_axi_AXILiteS_AWREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_ADDR_WIDTH> > s_axi_AXILiteS_AWADDR;
sc_in< sc_logic > s_axi_AXILiteS_WVALID;
sc_out< sc_logic > s_axi_AXILiteS_WREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH> > s_axi_AXILiteS_WDATA;
sc_in< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH/8> > s_axi_AXILiteS_WSTRB;
sc_in< sc_logic > s_axi_AXILiteS_ARVALID;
sc_out< sc_logic > s_axi_AXILiteS_ARREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_ADDR_WIDTH> > s_axi_AXILiteS_ARADDR;
sc_out< sc_logic > s_axi_AXILiteS_RVALID;
sc_in< sc_logic > s_axi_AXILiteS_RREADY;
sc_out< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH> > s_axi_AXILiteS_RDATA;
sc_out< sc_lv<2> > s_axi_AXILiteS_RRESP;
sc_out< sc_logic > s_axi_AXILiteS_BVALID;
sc_in< sc_logic > s_axi_AXILiteS_BREADY;
sc_out< sc_lv<2> > s_axi_AXILiteS_BRESP;
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_out< sc_logic > interrupt;
// Module declarations
acorn128_dec_onebyte(sc_module_name name);
SC_HAS_PROCESS(acorn128_dec_onebyte);
~acorn128_dec_onebyte();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
acorn128_dec_onebyte_AXILiteS_s_axi<C_S_AXI_AXILITES_ADDR_WIDTH,C_S_AXI_AXILITES_DATA_WIDTH>* acorn128_dec_onebyte_AXILiteS_s_axi_U;
acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit* grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_logic > ap_start;
sc_signal< sc_logic > ap_done;
sc_signal< sc_logic > ap_idle;
sc_signal< sc_lv<16> > ap_CS_fsm;
sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0;
sc_signal< bool > ap_sig_bdd_57;
sc_signal< sc_logic > ap_ready;
sc_signal< sc_lv<9> > state_address0;
sc_signal< sc_logic > state_ce0;
sc_signal< sc_logic > state_we0;
sc_signal< sc_lv<8> > state_d0;
sc_signal< sc_lv<8> > state_q0;
sc_signal< sc_lv<8> > plaintextbyte;
sc_signal< sc_lv<8> > ciphertextbyte;
sc_signal< sc_lv<8> > ksbyte;
sc_signal< sc_lv<8> > cabyte;
sc_signal< sc_lv<8> > cbbyte;
sc_signal< sc_lv<32> > ap_return;
sc_signal< sc_logic > acorn128_dec_onebyte_AXILiteS_s_axi_U_ap_dummy_ce;
sc_signal< sc_lv<1> > tmp_fu_82_p1;
sc_signal< sc_lv<1> > tmp_reg_265;
sc_signal< sc_lv<1> > tmp_1_fu_87_p1;
sc_signal< sc_lv<1> > tmp_1_reg_270;
sc_signal< sc_lv<1> > tmp_2_fu_92_p1;
sc_signal< sc_lv<1> > tmp_2_reg_275;
sc_signal< sc_lv<1> > tmp_3_reg_280;
sc_signal< sc_lv<1> > tmp_4_reg_285;
sc_signal< sc_lv<1> > tmp_5_reg_290;
sc_signal< sc_lv<1> > tmp_6_reg_295;
sc_signal< sc_lv<1> > tmp_7_reg_300;
sc_signal< sc_lv<1> > tmp_8_reg_305;
sc_signal< sc_lv<1> > tmp_9_reg_310;
sc_signal< sc_lv<1> > tmp_10_reg_315;
sc_signal< sc_lv<1> > tmp_11_reg_320;
sc_signal< sc_lv<1> > tmp_12_reg_325;
sc_signal< sc_lv<1> > tmp_13_reg_330;
sc_signal< sc_lv<1> > tmp_14_reg_335;
sc_signal< sc_lv<1> > tmp_15_reg_340;
sc_signal< sc_lv<1> > tmp_16_reg_345;
sc_signal< sc_lv<1> > tmp_17_reg_350;
sc_signal< sc_lv<1> > tmp_18_reg_355;
sc_signal< sc_lv<1> > tmp_19_reg_360;
sc_signal< sc_lv<1> > tmp_20_reg_365;
sc_signal< sc_lv<1> > tmp_21_reg_370;
sc_signal< sc_lv<1> > tmp_22_reg_375;
sc_signal< sc_lv<1> > tmp_23_reg_380;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ap_start;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ap_done;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ap_idle;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ap_ready;
sc_signal< sc_lv<9> > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_state_address0;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_state_ce0;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_state_we0;
sc_signal< sc_lv<8> > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_state_d0;
sc_signal< sc_lv<8> > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_state_q0;
sc_signal< sc_lv<1> > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ciphertextbit;
sc_signal< sc_lv<1> > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ca;
sc_signal< sc_lv<1> > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_cb;
sc_signal< sc_logic > grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ap_start_ap_start_reg;
sc_signal< sc_logic > ap_sig_cseq_ST_st3_fsm_2;
sc_signal< bool > ap_sig_bdd_162;
sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4;
sc_signal< bool > ap_sig_bdd_170;
sc_signal< sc_logic > ap_sig_cseq_ST_st7_fsm_6;
sc_signal< bool > ap_sig_bdd_178;
sc_signal< sc_logic > ap_sig_cseq_ST_st9_fsm_8;
sc_signal< bool > ap_sig_bdd_186;
sc_signal< sc_logic > ap_sig_cseq_ST_st11_fsm_10;
sc_signal< bool > ap_sig_bdd_194;
sc_signal< sc_logic > ap_sig_cseq_ST_st13_fsm_12;
sc_signal< bool > ap_sig_bdd_202;
sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14;
sc_signal< bool > ap_sig_bdd_210;
sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1;
sc_signal< bool > ap_sig_bdd_218;
sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3;
sc_signal< bool > ap_sig_bdd_225;
sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5;
sc_signal< bool > ap_sig_bdd_233;
sc_signal< sc_logic > ap_sig_cseq_ST_st8_fsm_7;
sc_signal< bool > ap_sig_bdd_241;
sc_signal< sc_logic > ap_sig_cseq_ST_st10_fsm_9;
sc_signal< bool > ap_sig_bdd_249;
sc_signal< sc_logic > ap_sig_cseq_ST_st12_fsm_11;
sc_signal< bool > ap_sig_bdd_257;
sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13;
sc_signal< bool > ap_sig_bdd_265;
sc_signal< sc_logic > ap_sig_cseq_ST_st16_fsm_15;
sc_signal< bool > ap_sig_bdd_273;
sc_signal< sc_lv<16> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<16> ap_ST_st1_fsm_0;
static const sc_lv<16> ap_ST_st2_fsm_1;
static const sc_lv<16> ap_ST_st3_fsm_2;
static const sc_lv<16> ap_ST_st4_fsm_3;
static const sc_lv<16> ap_ST_st5_fsm_4;
static const sc_lv<16> ap_ST_st6_fsm_5;
static const sc_lv<16> ap_ST_st7_fsm_6;
static const sc_lv<16> ap_ST_st8_fsm_7;
static const sc_lv<16> ap_ST_st9_fsm_8;
static const sc_lv<16> ap_ST_st10_fsm_9;
static const sc_lv<16> ap_ST_st11_fsm_10;
static const sc_lv<16> ap_ST_st12_fsm_11;
static const sc_lv<16> ap_ST_st13_fsm_12;
static const sc_lv<16> ap_ST_st14_fsm_13;
static const sc_lv<16> ap_ST_st15_fsm_14;
static const sc_lv<16> ap_ST_st16_fsm_15;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const int C_DATA_WIDTH;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_F;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_acorn128_dec_onebyte_AXILiteS_s_axi_U_ap_dummy_ce();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_return();
void thread_ap_rst_n_inv();
void thread_ap_sig_bdd_162();
void thread_ap_sig_bdd_170();
void thread_ap_sig_bdd_178();
void thread_ap_sig_bdd_186();
void thread_ap_sig_bdd_194();
void thread_ap_sig_bdd_202();
void thread_ap_sig_bdd_210();
void thread_ap_sig_bdd_218();
void thread_ap_sig_bdd_225();
void thread_ap_sig_bdd_233();
void thread_ap_sig_bdd_241();
void thread_ap_sig_bdd_249();
void thread_ap_sig_bdd_257();
void thread_ap_sig_bdd_265();
void thread_ap_sig_bdd_273();
void thread_ap_sig_bdd_57();
void thread_ap_sig_cseq_ST_st10_fsm_9();
void thread_ap_sig_cseq_ST_st11_fsm_10();
void thread_ap_sig_cseq_ST_st12_fsm_11();
void thread_ap_sig_cseq_ST_st13_fsm_12();
void thread_ap_sig_cseq_ST_st14_fsm_13();
void thread_ap_sig_cseq_ST_st15_fsm_14();
void thread_ap_sig_cseq_ST_st16_fsm_15();
void thread_ap_sig_cseq_ST_st1_fsm_0();
void thread_ap_sig_cseq_ST_st2_fsm_1();
void thread_ap_sig_cseq_ST_st3_fsm_2();
void thread_ap_sig_cseq_ST_st4_fsm_3();
void thread_ap_sig_cseq_ST_st5_fsm_4();
void thread_ap_sig_cseq_ST_st6_fsm_5();
void thread_ap_sig_cseq_ST_st7_fsm_6();
void thread_ap_sig_cseq_ST_st8_fsm_7();
void thread_ap_sig_cseq_ST_st9_fsm_8();
void thread_grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ap_start();
void thread_grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ca();
void thread_grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_cb();
void thread_grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_ciphertextbit();
void thread_grp_acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_fu_73_state_q0();
void thread_state_address0();
void thread_state_ce0();
void thread_state_d0();
void thread_state_we0();
void thread_tmp_1_fu_87_p1();
void thread_tmp_2_fu_92_p1();
void thread_tmp_fu_82_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_484d_one_0_H_
#define _bd_484d_one_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class bd_484d_one_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_484d_one_0 (sc_core::sc_module_name name);
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _acorn128_enc_onebyte_Encrypt_StateUpdate128_1bit_HH_
#define _acorn128_enc_onebyte_Encrypt_StateUpdate128_1bit_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct acorn128_enc_onebyte_Encrypt_StateUpdate128_1bit : public sc_module {
// Port declarations 14
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<9> > state_address0;
sc_out< sc_logic > state_ce0;
sc_out< sc_logic > state_we0;
sc_out< sc_lv<8> > state_d0;
sc_in< sc_lv<8> > state_q0;
sc_in< sc_lv<1> > plaintextbit;
sc_in< sc_lv<1> > ca;
sc_in< sc_lv<1> > cb;
// Module declarations
acorn128_enc_onebyte_Encrypt_StateUpdate128_1bit(sc_module_name name);
SC_HAS_PROCESS(acorn128_enc_onebyte_Encrypt_StateUpdate128_1bit);
~acorn128_enc_onebyte_Encrypt_StateUpdate128_1bit();
sc_trace_file* mVcdFile;
sc_signal< sc_lv<23> > ap_CS_fsm;
sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0;
sc_signal< bool > ap_sig_bdd_41;
sc_signal< sc_lv<8> > reg_256;
sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1;
sc_signal< bool > ap_sig_bdd_62;
sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4;
sc_signal< bool > ap_sig_bdd_69;
sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5;
sc_signal< bool > ap_sig_bdd_77;
sc_signal< sc_logic > ap_sig_cseq_ST_st10_fsm_9;
sc_signal< bool > ap_sig_bdd_85;
sc_signal< sc_logic > ap_sig_cseq_ST_st12_fsm_11;
sc_signal< bool > ap_sig_bdd_93;
sc_signal< sc_lv<8> > reg_260;
sc_signal< sc_logic > ap_sig_cseq_ST_st3_fsm_2;
sc_signal< bool > ap_sig_bdd_102;
sc_signal< sc_logic > ap_sig_cseq_ST_st7_fsm_6;
sc_signal< bool > ap_sig_bdd_109;
sc_signal< sc_lv<8> > reg_264;
sc_signal< sc_logic > ap_sig_cseq_ST_st8_fsm_7;
sc_signal< bool > ap_sig_bdd_118;
sc_signal< sc_logic > ap_sig_cseq_ST_st11_fsm_10;
sc_signal< bool > ap_sig_bdd_125;
sc_signal< sc_logic > ap_sig_cseq_ST_st13_fsm_12;
sc_signal< bool > ap_sig_bdd_133;
sc_signal< sc_lv<8> > reg_268;
sc_signal< sc_logic > ap_sig_cseq_ST_st9_fsm_8;
sc_signal< bool > ap_sig_bdd_142;
sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13;
sc_signal< bool > ap_sig_bdd_149;
sc_signal< sc_lv<1> > tmp_24_fu_278_p1;
sc_signal< sc_lv<1> > tmp_24_reg_528;
sc_signal< sc_lv<9> > state_addr_2_gep_fu_91_p3;
sc_signal< sc_lv<9> > state_addr_2_reg_533;
sc_signal< sc_lv<9> > state_addr_3_gep_fu_100_p3;
sc_signal< sc_lv<9> > state_addr_3_reg_538;
sc_signal< sc_lv<8> > grp_fu_272_p2;
sc_signal< sc_lv<8> > tmp1_reg_543;
sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3;
sc_signal< bool > ap_sig_bdd_170;
sc_signal< sc_lv<1> > tmp_25_fu_282_p1;
sc_signal< sc_lv<1> > tmp_25_reg_553;
sc_signal< sc_lv<9> > state_addr_5_gep_fu_118_p3;
sc_signal< sc_lv<9> > state_addr_5_reg_558;
sc_signal< sc_lv<8> > tmp_s_fu_286_p2;
sc_signal< sc_lv<8> > tmp_s_reg_563;
sc_signal< sc_lv<8> > x_assign_1_fu_297_p2;
sc_signal< sc_lv<8> > x_assign_1_reg_568;
sc_signal< sc_lv<1> > tmp_26_fu_303_p1;
sc_signal< sc_lv<1> > tmp_26_reg_573;
sc_signal< sc_lv<9> > state_addr_7_gep_fu_136_p3;
sc_signal< sc_lv<9> > state_addr_7_reg_584;
sc_signal< sc_lv<1> > tmp_28_fu_307_p1;
sc_signal< sc_lv<1> > tmp_28_reg_594;
sc_signal< sc_lv<9> > state_addr_9_gep_fu_154_p3;
sc_signal< sc_lv<9> > state_addr_9_reg_599;
sc_signal< sc_lv<8> > tmp3_fu_311_p2;
sc_signal< sc_lv<8> > tmp3_reg_604;
sc_signal< sc_lv<8> > tmp_3_fu_323_p2;
sc_signal< sc_lv<8> > tmp_3_reg_609;
sc_signal< sc_lv<1> > tmp_29_fu_329_p1;
sc_signal< sc_lv<1> > tmp_29_reg_614;
sc_signal< sc_lv<9> > state_addr_11_gep_fu_172_p3;
sc_signal< sc_lv<9> > state_addr_11_reg_624;
sc_signal< sc_lv<1> > tmp_fu_352_p2;
sc_signal< sc_lv<1> > tmp_reg_629;
sc_signal< sc_lv<8> > tmp_5_fu_358_p2;
sc_signal< sc_lv<8> > tmp_5_reg_634;
sc_signal< sc_lv<8> > z_assign_fu_364_p2;
sc_signal< sc_lv<8> > z_assign_reg_655;
sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14;
sc_signal< bool > ap_sig_bdd_221;
sc_signal< sc_lv<8> > y_assign_fu_379_p2;
sc_signal< sc_lv<8> > y_assign_reg_660;
sc_signal< sc_lv<1> > tmp_i_i_fu_426_p2;
sc_signal< sc_lv<1> > tmp_i_i_reg_665;
sc_signal< sc_lv<8> > tmp_1_i_i_fu_438_p2;
sc_signal< sc_lv<8> > tmp_1_i_i_reg_675;
sc_signal< sc_logic > ap_sig_cseq_ST_st16_fsm_15;
sc_signal< bool > ap_sig_bdd_236;
sc_signal< sc_lv<8> > tmp_2_i_i_fu_444_p2;
sc_signal< sc_lv<8> > tmp_2_i_i_reg_680;
sc_signal< sc_logic > ap_sig_cseq_ST_st21_fsm_20;
sc_signal< bool > ap_sig_bdd_247;
sc_signal< sc_lv<1> > tmp_1_i_fu_450_p2;
sc_signal< sc_lv<1> > tmp_1_i_reg_690;
sc_signal< sc_lv<1> > tmp_2_i_fu_455_p2;
sc_signal< sc_lv<1> > tmp_2_i_reg_695;
sc_signal< sc_lv<9> > j_1_fu_466_p2;
sc_signal< sc_lv<9> > j_1_reg_703;
sc_signal< sc_logic > ap_sig_cseq_ST_st22_fsm_21;
sc_signal< bool > ap_sig_bdd_260;
sc_signal< sc_lv<1> > exitcond_fu_460_p2;
sc_signal< sc_lv<9> > j_reg_243;
sc_signal< sc_logic > ap_sig_cseq_ST_st23_fsm_22;
sc_signal< bool > ap_sig_bdd_276;
sc_signal< sc_lv<64> > tmp_6_fu_472_p1;
sc_signal< sc_lv<64> > tmp_7_fu_518_p1;
sc_signal< sc_logic > ap_sig_cseq_ST_st17_fsm_16;
sc_signal< bool > ap_sig_bdd_321;
sc_signal< sc_logic > ap_sig_cseq_ST_st18_fsm_17;
sc_signal< bool > ap_sig_bdd_329;
sc_signal< sc_logic > ap_sig_cseq_ST_st19_fsm_18;
sc_signal< bool > ap_sig_bdd_337;
sc_signal< sc_logic > ap_sig_cseq_ST_st20_fsm_19;
sc_signal< bool > ap_sig_bdd_345;
sc_signal< sc_lv<8> > tmp_4_fu_511_p2;
sc_signal< sc_lv<8> > tmp2_fu_291_p2;
sc_signal< sc_lv<8> > tmp4_fu_317_p2;
sc_signal< sc_lv<1> > tmp_30_fu_333_p1;
sc_signal< sc_lv<1> > tmp_4_i_i_i_fu_341_p2;
sc_signal< sc_lv<1> > tmp_i9_i_i_fu_337_p2;
sc_signal< sc_lv<1> > tmp_5_i_i_i_fu_346_p2;
sc_signal< sc_lv<8> > tmp6_fu_373_p2;
sc_signal< sc_lv<1> > tmp_27_fu_369_p1;
sc_signal< sc_lv<1> > tmp_31_fu_385_p1;
sc_signal< sc_lv<1> > tmp_i_i_i_fu_393_p2;
sc_signal< sc_lv<1> > tmp_32_fu_389_p1;
sc_signal< sc_lv<1> > tmp_2_i_i_i_fu_404_p2;
sc_signal< sc_lv<1> > tmp8_fu_410_p2;
sc_signal< sc_lv<1> > tmp_1_i_i_i_fu_399_p2;
sc_signal< sc_lv<1> > tmp9_fu_421_p2;
sc_signal< sc_lv<1> > tmp7_fu_416_p2;
sc_signal< sc_lv<8> > tmp_i_i_2_fu_432_p2;
sc_signal< sc_lv<8> > tmp12_fu_482_p2;
sc_signal< sc_lv<8> > tmp10_fu_477_p2;
sc_signal< sc_lv<1> > tmp13_fu_492_p2;
sc_signal< sc_lv<1> > tmp15_fu_496_p2;
sc_signal< sc_lv<1> > tmp14_fu_501_p2;
sc_signal< sc_lv<8> > tmp14_cast_fu_507_p1;
sc_signal< sc_lv<8> > tmp11_fu_486_p2;
sc_signal< sc_lv<23> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<23> ap_ST_st1_fsm_0;
static const sc_lv<23> ap_ST_st2_fsm_1;
static const sc_lv<23> ap_ST_st3_fsm_2;
static const sc_lv<23> ap_ST_st4_fsm_3;
static const sc_lv<23> ap_ST_st5_fsm_4;
static const sc_lv<23> ap_ST_st6_fsm_5;
static const sc_lv<23> ap_ST_st7_fsm_6;
static const sc_lv<23> ap_ST_st8_fsm_7;
static const sc_lv<23> ap_ST_st9_fsm_8;
static const sc_lv<23> ap_ST_st10_fsm_9;
static const sc_lv<23> ap_ST_st11_fsm_10;
static const sc_lv<23> ap_ST_st12_fsm_11;
static const sc_lv<23> ap_ST_st13_fsm_12;
static const sc_lv<23> ap_ST_st14_fsm_13;
static const sc_lv<23> ap_ST_st15_fsm_14;
static const sc_lv<23> ap_ST_st16_fsm_15;
static const sc_lv<23> ap_ST_st17_fsm_16;
static const sc_lv<23> ap_ST_st18_fsm_17;
static const sc_lv<23> ap_ST_st19_fsm_18;
static const sc_lv<23> ap_ST_st20_fsm_19;
static const sc_lv<23> ap_ST_st21_fsm_20;
static const sc_lv<23> ap_ST_st22_fsm_21;
static const sc_lv<23> ap_ST_st23_fsm_22;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<9> ap_const_lv9_0;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<64> ap_const_lv64_EB;
static const sc_lv<64> ap_const_lv64_E6;
static const sc_lv<64> ap_const_lv64_121;
static const sc_lv<64> ap_const_lv64_C4;
static const sc_lv<64> ap_const_lv64_C1;
static const sc_lv<64> ap_const_lv64_A0;
static const sc_lv<64> ap_const_lv64_9A;
static const sc_lv<64> ap_const_lv64_6F;
static const sc_lv<64> ap_const_lv64_6B;
static const sc_lv<64> ap_const_lv64_42;
static const sc_lv<64> ap_const_lv64_3D;
static const sc_lv<64> ap_const_lv64_17;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<64> ap_const_lv64_C;
static const sc_lv<64> ap_const_lv64_F4;
static const sc_lv<64> ap_const_lv64_124;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_12;
static const sc_lv<32> ap_const_lv32_13;
static const sc_lv<9> ap_const_lv9_124;
static const sc_lv<9> ap_const_lv9_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_sig_bdd_102();
void thread_ap_sig_bdd_109();
void thread_ap_sig_bdd_118();
void thread_ap_sig_bdd_125();
void thread_ap_sig_bdd_133();
void thread_ap_sig_bdd_142();
void thread_ap_sig_bdd_149();
void thread_ap_sig_bdd_170();
void thread_ap_sig_bdd_221();
void thread_ap_sig_bdd_236();
void thread_ap_sig_bdd_247();
void thread_ap_sig_bdd_260();
void thread_ap_sig_bdd_276();
void thread_ap_sig_bdd_321();
void thread_ap_sig_bdd_329();
void thread_ap_sig_bdd_337();
void thread_ap_sig_bdd_345();
void thread_ap_sig_bdd_41();
void thread_ap_sig_bdd_62();
void thread_ap_sig_bdd_69();
void thread_ap_sig_bdd_77();
void thread_ap_sig_bdd_85();
void thread_ap_sig_bdd_93();
void thread_ap_sig_cseq_ST_st10_fsm_9();
void thread_ap_sig_cseq_ST_st11_fsm_10();
void thread_ap_sig_cseq_ST_st12_fsm_11();
void thread_ap_sig_cseq_ST_st13_fsm_12();
void thread_ap_sig_cseq_ST_st14_fsm_13();
void thread_ap_sig_cseq_ST_st15_fsm_14();
void thread_ap_sig_cseq_ST_st16_fsm_15();
void thread_ap_sig_cseq_ST_st17_fsm_16();
void thread_ap_sig_cseq_ST_st18_fsm_17();
void thread_ap_sig_cseq_ST_st19_fsm_18();
void thread_ap_sig_cseq_ST_st1_fsm_0();
void thread_ap_sig_cseq_ST_st20_fsm_19();
void thread_ap_sig_cseq_ST_st21_fsm_20();
void thread_ap_sig_cseq_ST_st22_fsm_21();
void thread_ap_sig_cseq_ST_st23_fsm_22();
void thread_ap_sig_cseq_ST_st2_fsm_1();
void thread_ap_sig_cseq_ST_st3_fsm_2();
void thread_ap_sig_cseq_ST_st4_fsm_3();
void thread_ap_sig_cseq_ST_st5_fsm_4();
void thread_ap_sig_cseq_ST_st6_fsm_5();
void thread_ap_sig_cseq_ST_st7_fsm_6();
void thread_ap_sig_cseq_ST_st8_fsm_7();
void thread_ap_sig_cseq_ST_st9_fsm_8();
void thread_exitcond_fu_460_p2();
void thread_grp_fu_272_p2();
void thread_j_1_fu_466_p2();
void thread_state_addr_11_gep_fu_172_p3();
void thread_state_addr_2_gep_fu_91_p3();
void thread_state_addr_3_gep_fu_100_p3();
void thread_state_addr_5_gep_fu_118_p3();
void thread_state_addr_7_gep_fu_136_p3();
void thread_state_addr_9_gep_fu_154_p3();
void thread_state_address0();
void thread_state_ce0();
void thread_state_d0();
void thread_state_we0();
void thread_tmp10_fu_477_p2();
void thread_tmp11_fu_486_p2();
void thread_tmp12_fu_482_p2();
void thread_tmp13_fu_492_p2();
void thread_tmp14_cast_fu_507_p1();
void thread_tmp14_fu_501_p2();
void thread_tmp15_fu_496_p2();
void thread_tmp2_fu_291_p2();
void thread_tmp3_fu_311_p2();
void thread_tmp4_fu_317_p2();
void thread_tmp6_fu_373_p2();
void thread_tmp7_fu_416_p2();
void thread_tmp8_fu_410_p2();
void thread_tmp9_fu_421_p2();
void thread_tmp_1_i_fu_450_p2();
void thread_tmp_1_i_i_fu_438_p2();
void thread_tmp_1_i_i_i_fu_399_p2();
void thread_tmp_24_fu_278_p1();
void thread_tmp_25_fu_282_p1();
void thread_tmp_26_fu_303_p1();
void thread_tmp_27_fu_369_p1();
void thread_tmp_28_fu_307_p1();
void thread_tmp_29_fu_329_p1();
void thread_tmp_2_i_fu_455_p2();
void thread_tmp_2_i_i_fu_444_p2();
void thread_tmp_2_i_i_i_fu_404_p2();
void thread_tmp_30_fu_333_p1();
void thread_tmp_31_fu_385_p1();
void thread_tmp_32_fu_389_p1();
void thread_tmp_3_fu_323_p2();
void thread_tmp_4_fu_511_p2();
void thread_tmp_4_i_i_i_fu_341_p2();
void thread_tmp_5_fu_358_p2();
void thread_tmp_5_i_i_i_fu_346_p2();
void thread_tmp_6_fu_472_p1();
void thread_tmp_7_fu_518_p1();
void thread_tmp_fu_352_p2();
void thread_tmp_i9_i_i_fu_337_p2();
void thread_tmp_i_i_2_fu_432_p2();
void thread_tmp_i_i_fu_426_p2();
void thread_tmp_i_i_i_fu_393_p2();
void thread_tmp_s_fu_286_p2();
void thread_x_assign_1_fu_297_p2();
void thread_y_assign_fu_379_p2();
void thread_z_assign_fu_364_p2();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_13_H_
#define _design_1_xlconstant_0_13_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_13 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_13 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
#ifndef __PE_H__
#define __PE_H__
#include <list>
#include <iostream>
#include <iterator>
#include <map>
#include "Request.h"
#include "common.h"
#include "systemc.h"
#include "readIF.h"
#include "writeIF.h"
class pe : public sc_module{
SC_HAS_PROCESS(pe);
public:
sc_in<bool> peClk;
// signals for read memory
sc_in<float> readDin0;
sc_in<bool> readValid0;
sc_out<bool> readEna0;
sc_out<long> readAddr0;
sc_out<int> readLength0;
sc_in<float> readDin1;
sc_in<bool> readValid1;
sc_out<bool> readEna1;
sc_out<long> readAddr1;
sc_out<int> readLength1;
// signals for write memory
sc_out<float> writeDout;
sc_out<bool> writeValid;
sc_out<bool> writeEna;
sc_out<long> writeAddr;
sc_out<int> writeLength;
sc_in<bool> writeComplete;
sc_out<bool> computeDone;
int peIdx;
pe(sc_module_name _name, int _peIdx, int _peClkCycle);
~pe(){};
void sigInit();
private:
std::vector<std::list<float>> queues;
int peClkCycle;
// Registers for sending
int resLenVec0;
int availBufferVec0;
int resLenVec1;
int availBufferVec1;
int resLenVec;
int readCounter0;
int readCounter1;
int writeCounter;
int localCounter;
int writeReqCounter;
int writeReqNum;
bool allWriteReqSent;
void init();
void readVec0();
void readVec1();
void writeVec();
void vecAdd();
void statusMonitor();
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _system_xlconstant_0_0_H_
#define _system_xlconstant_0_0_H_
#include "xlconstant_v1_1.h"
#include "systemc.h"
class system_xlconstant_0_0 : public sc_module {
public:
xlconstant_v1_1_5<1,0> mod;
sc_out< sc_bv<1> > dout;
system_xlconstant_0_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
//
// Created by ludwig on 14.11.17.
//
#ifndef PROJECT_DECODER_H
#define PROJECT_DECODER_H
#include "systemc.h"
#include "Interfaces.h"
#include "CPU_Interfaces.h"
#include "Utilities.h"
#include "Defines.h"
class Decoder : public sc_module {
public:
SC_HAS_PROCESS(Decoder);
Decoder(sc_module_name name) :
CtlToDec_port("CtlToDec_port"),
DecToCtl_port("DecToCtl_port"),
encoded_instr(0),
rec(false),
imm_i(0),
imm_s(0),
imm_b(0),
imm_u(0),
imm_j(0),
imm_i_sext(0),
imm_i_shamt(0),
imm_b_1(0),
imm_b_2(0),
imm_b_sext_0(0),
imm_j_1(0),
imm_j_2(0),
imm_j_3(0),
opcode(0),
funct3(0),
funct7(0){
SC_THREAD(run);
}
// Ports
slave_out<DecodedInstr> DecToCtl_port;
slave_in<unsigned int> CtlToDec_port;
// Variables
unsigned int encoded_instr;
DecodedInstr decoded_instr;
bool rec;
unsigned int imm_i;
unsigned int imm_s;
unsigned int imm_b;
unsigned int imm_u;
unsigned int imm_j;
unsigned int imm_i_sext;
unsigned int imm_i_shamt;
unsigned int imm_b_1;
unsigned int imm_b_2;
unsigned int imm_b_sext_0;
unsigned int imm_j_1;
unsigned int imm_j_2;
unsigned int imm_j_3;
unsigned int opcode;
unsigned int funct3;
unsigned int funct7;
// Thread
void run();
};
void Decoder::run() {
while (true) {
// Wait for next instruction
rec = CtlToDec_port->nb_read(encoded_instr);
// New Instruction received;
if (rec) {
//Cpath
decoded_instr.instrType = InstrTypeOld::Unknown;
decoded_instr.encType = Error_Type;
opcode = Sub(encoded_instr, 6, 0);
funct3 = Sub(encoded_instr, 14, 12);
funct7 = Sub(encoded_instr, 31, 25);
// for all instructions:
decoded_instr.rs1_addr = Sub(encoded_instr, RS1_MSB, RS1_LSB);
decoded_instr.rs2_addr = Sub(encoded_instr, RS2_MSB, RS2_LSB);
decoded_instr.rd_addr = Sub(encoded_instr, RD_MSB, RD_LSB);
///////////////////////////////////////
//Instruction Type: Register-Immediate
///////////////////////////////////////
if (opcode == 0x13) {
//Sign extension
imm_i = Sub(encoded_instr, 31, 20);
if (Sub(imm_i, 11, 11) == 1) {
imm_i_sext = Cat(Fill(20), 20, imm_i, 12);
} else {
imm_i_sext = imm_i;
}
// I type encoding
decoded_instr.encType = I;
// immediate sign extended
decoded_instr.imm = imm_i_sext; // for slli,srli,srai reassigned to shamt
//Func3 Type
if (funct3 == 0x0) {
decoded_instr.instrType = InstrTypeOld::addI;
} else if (funct3 == 0x7) {
decoded_instr.instrType = InstrTypeOld::andI;
} else if (funct3 == 0x6) {
decoded_instr.instrType = InstrTypeOld::orI;
} else if (funct3 == 0x4) {
decoded_instr.instrType = InstrTypeOld::xorI;
} else if (funct3 == 0x2) {
decoded_instr.instrType = InstrTypeOld::sltI;
} else if (funct3 == 0x3) {
decoded_instr.instrType = InstrTypeOld::sltIu;
} else if (funct3 == 0x1) {
decoded_instr.instrType = InstrTypeOld::sllI;
imm_i_shamt = Sub(encoded_instr, 24, 20);
decoded_instr.imm = imm_i_shamt;
} else if (funct3 == 0x5) {
imm_i_shamt = Sub(encoded_instr, 24, 20);
if (funct7 == 0) {
decoded_instr.instrType = InstrTypeOld::srlI;
decoded_instr.imm = imm_i_shamt;
} else if (funct7 == 32) {
decoded_instr.instrType = InstrTypeOld::sraI;
decoded_instr.imm = imm_i_shamt;
}
}
}
///////////////////////////////////////
//Instruction Type: Register-Register
///////////////////////////////////////
else if (opcode == 0x33) {
// R type encoding
decoded_instr.encType = R;
// not used
decoded_instr.imm = 0;
//Func3 Type
if (funct3 == 0x0) {
if (funct7 == 0) decoded_instr.instrType = InstrTypeOld::add;
if (funct7 == 32) decoded_instr.instrType = InstrTypeOld::sub;
} else if (funct3 == 0x01) {
decoded_instr.instrType = InstrTypeOld::sll_Instr;
} else if (funct3 == 0x02) {
decoded_instr.instrType = InstrTypeOld::slt;
} else if (funct3 == 0x03) {
decoded_instr.instrType = InstrTypeOld::sltu;
} else if (funct3 == 0x04) {
decoded_instr.instrType = InstrTypeOld::Xor_Instr;
} else if (funct3 == 0x05) {
if (funct7 == 0) decoded_instr.instrType = InstrTypeOld::srl_Instr;
if (funct7 == 32) decoded_instr.instrType = InstrTypeOld::sra_Instr;
} else if (funct3 == 0x06) {
decoded_instr.instrType = InstrTypeOld::Or_Instr;
} else if (funct3 == 0x07) {
decoded_instr.instrType = InstrTypeOld::And_Instr;
}
}
///////////////////////////////////////
//Instruction Type: Conditional branch
///////////////////////////////////////
else if (opcode == 0x63) {
// 12 bit B immediate encodes signed offsets in multiples of 2 !!!!!
//Compute immediate
imm_b_1 = Cat(Sub(encoded_instr, 31, 31), 1, Sub(encoded_instr, 7, 7), 1);
imm_b_2 = Cat(Sub(encoded_instr, 30, 25), 6, Sub(encoded_instr, 11, 8), 4);
imm_b = Cat(imm_b_1, 2, imm_b_2, 10);
if (Sub(imm_b, 11, 11) == 1) {
imm_b_sext_0 = Cat(Fill(19), 19, imm_b, 12);
} else {
imm_b_sext_0 = imm_b;
}
imm_b = Cat(imm_b_sext_0, 31, 0, 1);
// B type encoding
decoded_instr.encType = B;
// always
decoded_instr.imm = imm_b;
//Func3 Type
if (funct3 == 0x0) {
decoded_instr.instrType = InstrTypeOld::beq;
} else if (funct3 == 0x01) {
decoded_instr.instrType = InstrTypeOld::bne;
} else if (funct3 == 0x04) {
decoded_instr.instrType = InstrTypeOld::blt;
} else if (funct3 == 0x05) {
decoded_instr.instrType = InstrTypeOld::bge;
} else if (funct3 == 0x06) {
decoded_instr.instrType = InstrTypeOld::bltu;
} else if (funct3 == 0x07) {
decoded_instr.instrType = InstrTypeOld::bgeu;
}
}
///////////////////////////////////////
//Instruction Type: Load
///////////////////////////////////////
else if (opcode == 0x03) {
//Compute immediate
imm_i = Sub(encoded_instr, 31, 20);
//Sign extension
if (Sub(imm_i, 11, 11) == 1) {
imm_i_sext = Cat(Fill(20), 20, imm_i, 12);
} else imm_i_sext = imm_i;
// I type encoding
decoded_instr.encType = I;
// immediate sign extended
decoded_instr.imm = imm_i_sext;
//Func3 Type
if (funct3 == 0x0) {
decoded_instr.instrType = InstrTypeOld::lb;
} else if (funct3 == 0x01) {
decoded_instr.instrType = InstrTypeOld::lh;
} else if (funct3 == 0x02) {
decoded_instr.instrType = InstrTypeOld::lw;
} else if (funct3 == 0x04) {
decoded_instr.instrType = InstrTypeOld::lbu;
} else if (funct3 == 0x05) {
decoded_instr.instrType = InstrTypeOld::lhu;
}
}
///////////////////////////////////////
//Instruction Type: Jumps
///////////////////////////////////////
else if (opcode == 0x37) {
imm_u = Sub(encoded_instr, 31, 12);
//FIXME: is the 12-bit shift done here or in the ALU ? For now here.
imm_u = Cat(imm_u, 20, 0, 12);
decoded_instr.imm = imm_u;
// U type encoding
decoded_instr.encType = U;
decoded_instr.instrType = InstrTypeOld::lui;
} else if (opcode == 0x17) {
imm_u = Sub(encoded_instr, 31, 12);
//FIXME: is the 12-bit shift done here or in the ALU ? For now here.
imm_u = Cat(imm_u, 20, 0, 12);
decoded_instr.imm = imm_u;
// U type encoding
decoded_instr.encType = U;
decoded_instr.instrType = InstrTypeOld::auipc;
} else if (opcode == 0x6F) {
imm_j_1 = Cat(Sub(encoded_instr, 31, 31), 1, Sub(encoded_instr, 19, 12), 8);
imm_j_2 = Cat(Sub(encoded_instr, 20, 20), 1, Sub(encoded_instr, 30, 21), 10);
imm_j_3 = Cat(imm_j_2, 11, 0, 1);
imm_j = Cat(imm_j_1, 9, imm_j_3, 12);
//Sign extension
if (Sub(encoded_instr, 31, 31) == 1) {
imm_j = Cat(Fill(11), 11, imm_j, 21);
}
decoded_instr.imm = imm_j;
// J type encoding
decoded_instr.encType = J;
decoded_instr.instrType = InstrTypeOld::jal;
} else if (opcode == 0x67) {
imm_i = Sub(encoded_instr, 31, 20);
//Sign extension
if (Sub(imm_i, 11, 11) == 1) {
imm_i = Cat(Fill(20), 20, imm_i, 12);
}
decoded_instr.imm = imm_i;
// I type encoding
decoded_instr.encType = I;
decoded_instr.instrType = InstrTypeOld::jalr;
}
///////////////////////////////////////
//Instruction Type: Store
///////////////////////////////////////
else if (opcode == 0x23) {
imm_s = Cat(Sub(encoded_instr, 31, 25), 7, Sub(encoded_instr, 11, 7), 5);
//Sign extend
if (Sub(imm_s, 11, 11) == 1) {
imm_s = Cat(Fill(20), 20, imm_s, 12);
}
// always for stores (s type)
decoded_instr.imm = imm_s;
// S type encoding
decoded_instr.encType = S;
if (funct3 == 0) {
decoded_instr.instrType = InstrTypeOld::sb;
} else if (funct3 == 1) {
decoded_instr.instrType = InstrTypeOld::sh;
} else if (funct3 == 2) {
decoded_instr.instrType = InstrTypeOld::sw;
}
}
}
/*
// Temporarily deal like this with unknown instructions
if (decoded_instr.instrType == InstrTypeOld::Unknown) {
std::cout << "@Dec: Unknown instruction... Terminating!" << std::endl;
exit(0);
}
#ifndef NDEBUG
cout << "@Dec: Decoding instr 0x" << hex << encoded_instr << ", InstrType = "
<< stringInstrType(decoded_instr.instrType) << endl;
cout << "@Dec: Immediate = 0x" << hex << decoded_instr.imm << "(hex) = "
<< dec << decoded_instr.imm << " (dec)" << endl;
#endif
*/
// Notify the CPU with the decoded instruction
DecToCtl_port->nb_write(decoded_instr);
}
}
#endif //PROJECT_DECODER_H
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef __ZYNQ_UTLRA_PS_E_TLM_H__
#define __ZYNQ_ULTRA_PS_E_TLM_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include <vector>
#include "genattr.h"
#include "xilinx_zynqmp.h"
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: zynq_ultra_ps_e_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynqmp qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynqmp from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynqmp wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynqmp wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class zynq_ultra_ps_e_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> maxihpm0_fpd_aclk;
sc_core::sc_in<bool> maxihpm1_fpd_aclk;
sc_core::sc_in<sc_dt::sc_bv<95> > emio_gpio_i;
sc_core::sc_out<sc_dt::sc_bv<95> > emio_gpio_o;
sc_core::sc_out<sc_dt::sc_bv<95> > emio_gpio_t;
sc_core::sc_in<bool> emio_spi0_sclk_i;
sc_core::sc_out<bool> emio_spi0_sclk_o;
sc_core::sc_out<bool> emio_spi0_sclk_t;
sc_core::sc_in<bool> emio_spi0_m_i;
sc_core::sc_out<bool> emio_spi0_m_o;
sc_core::sc_out<bool> emio_spi0_mo_t;
sc_core::sc_in<bool> emio_spi0_s_i;
sc_core::sc_out<bool> emio_spi0_s_o;
sc_core::sc_out<bool> emio_spi0_so_t;
sc_core::sc_in<bool> emio_spi0_ss_i_n;
sc_core::sc_out<bool> emio_spi0_ss_o_n;
sc_core::sc_out<bool> emio_spi0_ss1_o_n;
sc_core::sc_out<bool> emio_spi0_ss_n_t;
sc_core::sc_in<bool> emio_spi1_sclk_i;
sc_core::sc_out<bool> emio_spi1_sclk_o;
sc_core::sc_out<bool> emio_spi1_sclk_t;
sc_core::sc_in<bool> emio_spi1_m_i;
sc_core::sc_out<bool> emio_spi1_m_o;
sc_core::sc_out<bool> emio_spi1_mo_t;
sc_core::sc_in<bool> emio_spi1_s_i;
sc_core::sc_out<bool> emio_spi1_s_o;
sc_core::sc_out<bool> emio_spi1_so_t;
sc_core::sc_in<bool> emio_spi1_ss_i_n;
sc_core::sc_out<bool> emio_spi1_ss_o_n;
sc_core::sc_out<bool> emio_spi1_ss1_o_n;
sc_core::sc_out<bool> emio_spi1_ss_n_t;
sc_core::sc_in<sc_dt::sc_bv<1> > pl_ps_irq0;
sc_core::sc_out<bool> pl_resetn0;
sc_core::sc_out<bool> pl_clk0;
// Xtlm aximm slave sockets are delcared here. these XTLM sockets will hierachically bound with
// slave sockets defined in vivado generated wrapper.
// Xtlm aximm master socket/s is/are delcared here. these XTLM sockets will hierachically bound with
// master sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_rd_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM1_FPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM1_FPD_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of ZynqUltraScale+ IP propogated from Vivado
zynq_ultra_ps_e_tlm (sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~zynq_ultra_ps_e_tlm ();
SC_HAS_PROCESS( zynq_ultra_ps_e_tlm );
private:
//zynqmp tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynqmp* m_zynqmp_tlm_model;
// Array of Xtlm2tlm Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of zynq_ultra_ps_e_tlm and tlm simple initiator
// socket with xilinx_zynqmp's target socket
// Array of size 9
xtlm::xaximm_xtlm2tlm **m_xtlm2tlm;
// Array of tlm2xtlm Bridges
// Converts tlm transactions to xtlm transactions
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynqmp's simple target socket
// Array of size 3
xtlm::xaximm_tlm2xtlm **m_tlm2xtlm;
// sc_clocks for generating pl clocks
// output pins pl_clk0..3 are drived by these clocks
sc_core::sc_clock pl_clk0_clk;
//Method which is sentive to pl_clk0_clk sc_clock object
//pl_clk0 pin written based on pl_clk0_clk clock value
void trigger_pl_clk0_pin();
void pl_ps_irq0_method();
//pl_resetn0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void pl_resetn0_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_5356_one_0_H_
#define _bd_5356_one_0_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class bd_5356_one_0 : public sc_module {
public:
xlconstant_v1_1_6<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_5356_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
#include <pthread.h>
#include <systemc.h>
#include "sc_main.h"
#include "sc_run.h"
//#include "sc_config.h"
#include "sc_qt_adaptor.h"
//#include "sc_rst.h"
//#include "sc_clk.h"
//#include "sc_mux.h"
//#include "sc_tri.h"
//#include "sc_terminals.h"
//#include "sc_gates.h"
//#include "sc_gates_pv.h"
//#include "sc_reg.h"
//#include "sc_arith.h"
/* ????? what is this?
template <bool CLKEDGE = DEFAULT_CLKEDGE, flexinterface_t FLEXINT = DEFAULT_FLEXINT>
class U1block : public SyscFlexInt<CLKEDGE, FLEXINT>
{
public:
typedef sc_lv<32> data_t;
typedef sc_lv<1> sel_t;
// --------------------- Ports ---------------------
// Provided by base module scFlexModuleT
// sc_in_clk clock{"clock"}; // Clock input (FLEXINT: custom active edge)
// sc_in<rst_t> reset{"reset"}; // Asynchronous reset input (FLEXINT: possibly unmapped, custom active level)
// sc_in<ena_t> enable{"enable"}; // Synchronous enable input (FLEXINT: possibly unmapped, custom active level)
sc_out<data_t> q{"q"}; // Data output
sc_in<data_t> load{"load"}; // Load value (when mux selection = 1, d = load)
sc_in<data_t> incr{"incr"}; // Incr value (when mux selection = 0, d = q + incr)
sc_in<sel_t> sel{"sel"}; // Mux selection value
typedef SyscFlexInt<CLKEDGE, FLEXINT> BASE_MODULE;
typedef U1block<CLKEDGE, FLEXINT> SC_CURRENT_USER_MODULE;
private:
SyscMux<2,1,1,,1,1> u3;
SyscReg<32,CLKEDGE,FLEXINT> u2;
SyscAdd<2,32> a1;
sc_signal<sc_lv<32>> wire1{"u3.d0,a1.y"};
sc_signal<sc_lv<32>> wire2{"u3.y,u2.d"};
public:
U1block(::sc_core::sc_module_name name): SyscFlexInt<CLKEDGE,FLEXINT>(name)
, u3("u3"), u2("u2"), a1("a1")
{
u3.d[0]->bind(wire1);
u3.d[1]->bind(load);
u3.sel(sel);
u3.y(wire2);
a1.d[0]->bind(u2.q);
a1.d[1]->bind(incr);
a1.y(wire1);
u2.d.bind(wire2);
u2.reset.bind(BASE_MODULE::reset);
u2.clock.bind(BASE_MODULE::clock);
u2.q.bind(q);
}
};
*/
/*
* Create a separate thread to execute this code, the original systemc's main() code.
* @code return sc_core::sc_elab_and_sim(argc, argv); @endcode
*/
void *scSimMain(void *args)
{
(void)args;
scQtAdaptor ADAPTOR("QT<->SC_bridge");
sc_setRunResult(sc_core::sc_elab_and_sim(0, nullptr));
return nullptr;
}
int sc_main (int argc, char *argv[])
{
return 0;
}
/*
* Create design and run the simulation
(void)argc;
(void)argv;
// Inputs
//SyscIn<1> clk(1, 1, 0, SC_LOGIC_0, "clk");
sc_clock clk("clk");
//SyscIn<1> rst(4, 4, 0, SC_LOGIC_0, "rst");
sc_signal<sc_lv<1>> rst("rst");
//SyscIn<1> sel(2, 2, 0, SC_LOGIC_0, "sel");
sc_signal<sc_lv<1>> sel("sel");
//SyscIn<32> incr(4, 4, 0, SC_LOGIC_0, "incr");
sc_signal<sc_lv<32>> incr("incr");
//SyscIn<1> sel2(4, 4, 0, SC_LOGIC_0, "sel2");
sc_signal<sc_lv<1>> load("load");
//SyscIn<32> load(4, 4, 0, SC_LOGIC_0, "load");
sc_signal<sc_lv<32>> val("val");
// Outputs
//SyscOut<32> y("y");
sc_signal<sc_lv<32>> y("y");
// Components
SyscCnt<32, DEFAULT_CLKEDGE, RST_HIGH_NO_ENA> u4("u4");
SyscMux_pv<2,32,1> u5("u5");
U1block<true, RST_HIGH_NO_ENA> u1("u1");
// Additional wires
sc_signal<sc_lv<32>> wire1("u5.d0,u4.q");
sc_signal<sc_lv<32>> wire2("u5.d1,u1.q");
// Wiring/binding
u4.reset(rst);
u4.clock(clk);
u4.q(wire1);
u5.map(prefix, index, wire);
u5.sel(sel);
u5.d[0](wire1);
u5.d[1](wire2);
u5.y(y);
u1.sel(load);
u1.incr(incr);
u1.load(val);
u1.reset(rst);
u1.clock(clk);
u1.q(wire2);
sc_start(); // Run forever
return 0;
}
*/
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> I2C0_SDA_I;
sc_core::sc_out<bool> I2C0_SDA_O;
sc_core::sc_out<bool> I2C0_SDA_T;
sc_core::sc_in<bool> I2C0_SCL_I;
sc_core::sc_out<bool> I2C0_SCL_O;
sc_core::sc_out<bool> I2C0_SCL_T;
sc_core::sc_in<bool> SDIO0_WP;
sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
sc_core::sc_in<sc_dt::sc_bv<3> > IRQ_F2P;
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
void IRQ_F2P_method();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _CvtColor_1_HH_
#define _CvtColor_1_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "image_filter_mul_bkb.h"
#include "image_filter_mac_cud.h"
#include "image_filter_mac_dEe.h"
namespace ap_rtl {
struct CvtColor_1 : public sc_module {
// Port declarations 25
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<32> > p_src_rows_V_dout;
sc_in< sc_logic > p_src_rows_V_empty_n;
sc_out< sc_logic > p_src_rows_V_read;
sc_in< sc_lv<32> > p_src_cols_V_dout;
sc_in< sc_logic > p_src_cols_V_empty_n;
sc_out< sc_logic > p_src_cols_V_read;
sc_in< sc_lv<8> > p_src_data_stream_0_V_dout;
sc_in< sc_logic > p_src_data_stream_0_V_empty_n;
sc_out< sc_logic > p_src_data_stream_0_V_read;
sc_in< sc_lv<8> > p_src_data_stream_1_V_dout;
sc_in< sc_logic > p_src_data_stream_1_V_empty_n;
sc_out< sc_logic > p_src_data_stream_1_V_read;
sc_in< sc_lv<8> > p_src_data_stream_2_V_dout;
sc_in< sc_logic > p_src_data_stream_2_V_empty_n;
sc_out< sc_logic > p_src_data_stream_2_V_read;
sc_out< sc_lv<8> > p_dst_data_stream_V_din;
sc_in< sc_logic > p_dst_data_stream_V_full_n;
sc_out< sc_logic > p_dst_data_stream_V_write;
// Module declarations
CvtColor_1(sc_module_name name);
SC_HAS_PROCESS(CvtColor_1);
~CvtColor_1();
sc_trace_file* mVcdFile;
image_filter_mul_bkb<1,1,8,22,29>* image_filter_mul_bkb_U23;
image_filter_mac_cud<1,1,8,20,29,29>* image_filter_mac_cud_U24;
image_filter_mac_dEe<1,1,8,23,29,30>* image_filter_mac_dEe_U25;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > p_src_rows_V_blk_n;
sc_signal< sc_logic > p_src_cols_V_blk_n;
sc_signal< sc_logic > p_src_data_stream_0_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<1> > tmp_2_i_reg_362;
sc_signal< sc_logic > p_src_data_stream_1_V_blk_n;
sc_signal< sc_logic > p_src_data_stream_2_V_blk_n;
sc_signal< sc_logic > p_dst_data_stream_V_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_lv<1> > tmp_2_i_reg_362_pp0_iter3_reg;
sc_signal< sc_lv<31> > j_i_reg_206;
sc_signal< sc_lv<32> > cols_reg_343;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<32> > rows_reg_348;
sc_signal< sc_lv<1> > tmp_i_fu_221_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<31> > i_fu_226_p2;
sc_signal< sc_lv<31> > i_reg_357;
sc_signal< sc_lv<1> > tmp_2_i_fu_236_p2;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > tmp_2_i_reg_362_pp0_iter1_reg;
sc_signal< sc_lv<1> > tmp_2_i_reg_362_pp0_iter2_reg;
sc_signal< sc_lv<31> > j_fu_241_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<8> > tmp_6_reg_371;
sc_signal< sc_lv<8> > tmp_6_reg_371_pp0_iter2_reg;
sc_signal< sc_lv<8> > tmp_7_reg_376;
sc_signal< sc_lv<8> > tmp_7_reg_376_pp0_iter2_reg;
sc_signal< sc_lv<8> > tmp_8_reg_381;
sc_signal< sc_lv<29> > r_V_4_i_i_fu_319_p2;
sc_signal< sc_lv<29> > r_V_4_i_i_reg_386;
sc_signal< sc_lv<30> > grp_fu_333_p3;
sc_signal< sc_lv<30> > r_V_1_reg_391;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_lv<8> > p_Val2_3_reg_396;
sc_signal< sc_lv<1> > tmp_reg_401;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state3;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_lv<31> > i_i_reg_195;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<32> > i_cast_i_fu_217_p1;
sc_signal< sc_lv<32> > j_cast_i_fu_232_p1;
sc_signal< sc_lv<29> > grp_fu_325_p3;
sc_signal< sc_lv<8> > tmp_6_i_i_i_i_fu_275_p1;
sc_signal< sc_lv<8> > p_Val2_4_fu_285_p2;
sc_signal< sc_lv<1> > tmp_3_fu_278_p3;
sc_signal< sc_lv<1> > tmp_4_fu_290_p3;
sc_signal< sc_lv<1> > p_Result_2_i_i_i_i_1_fu_298_p2;
sc_signal< sc_lv<1> > not_carry_fu_304_p2;
sc_signal< sc_lv<8> > r_V_4_i_i_fu_319_p0;
sc_signal< sc_lv<22> > r_V_4_i_i_fu_319_p1;
sc_signal< sc_lv<8> > grp_fu_325_p0;
sc_signal< sc_lv<20> > grp_fu_325_p1;
sc_signal< sc_lv<8> > grp_fu_333_p0;
sc_signal< sc_lv<23> > grp_fu_333_p1;
sc_signal< sc_lv<29> > grp_fu_333_p2;
sc_signal< sc_lv<4> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_lv<28> > grp_fu_325_p00;
sc_signal< sc_lv<30> > grp_fu_333_p00;
sc_signal< sc_lv<30> > grp_fu_333_p20;
sc_signal< sc_lv<29> > r_V_4_i_i_fu_319_p00;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_pp0_stage0;
static const sc_lv<4> ap_ST_fsm_state8;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_2;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<31> ap_const_lv31_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<31> ap_const_lv31_1;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<32> ap_const_lv32_1D;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<29> ap_const_lv29_1322D0;
static const sc_lv<28> ap_const_lv28_74BC6;
static const sc_lv<30> ap_const_lv30_259168;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state8();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state3_pp0_stage0_iter0();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_block_state5_pp0_stage0_iter2();
void thread_ap_block_state6_pp0_stage0_iter3();
void thread_ap_block_state7_pp0_stage0_iter4();
void thread_ap_condition_pp0_exit_iter0_state3();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_ready();
void thread_grp_fu_325_p0();
void thread_grp_fu_325_p00();
void thread_grp_fu_325_p1();
void thread_grp_fu_333_p0();
void thread_grp_fu_333_p00();
void thread_grp_fu_333_p1();
void thread_grp_fu_333_p2();
void thread_grp_fu_333_p20();
void thread_i_cast_i_fu_217_p1();
void thread_i_fu_226_p2();
void thread_j_cast_i_fu_232_p1();
void thread_j_fu_241_p2();
void thread_not_carry_fu_304_p2();
void thread_p_Result_2_i_i_i_i_1_fu_298_p2();
void thread_p_Val2_4_fu_285_p2();
void thread_p_dst_data_stream_V_blk_n();
void thread_p_dst_data_stream_V_din();
void thread_p_dst_data_stream_V_write();
void thread_p_src_cols_V_blk_n();
void thread_p_src_cols_V_read();
void thread_p_src_data_stream_0_V_blk_n();
void thread_p_src_data_stream_0_V_read();
void thread_p_src_data_stream_1_V_blk_n();
void thread_p_src_data_stream_1_V_read();
void thread_p_src_data_stream_2_V_blk_n();
void thread_p_src_data_stream_2_V_read();
void thread_p_src_rows_V_blk_n();
void thread_p_src_rows_V_read();
void thread_r_V_4_i_i_fu_319_p0();
void thread_r_V_4_i_i_fu_319_p00();
void thread_r_V_4_i_i_fu_319_p1();
void thread_tmp_2_i_fu_236_p2();
void thread_tmp_3_fu_278_p3();
void thread_tmp_4_fu_290_p3();
void thread_tmp_6_i_i_i_i_fu_275_p1();
void thread_tmp_i_fu_221_p2();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _aes16_bidir_HH_
#define _aes16_bidir_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "KeyExpansion.h"
#include "AES_CTR_xcrypt_buffe.h"
#include "aes16_bidir_mux_42_32_1_1.h"
#include "AES_CTR_xcrypt_buffe_buffer.h"
#include "AES_CTR_xcrypt_buffe_x.h"
#include "aes16_bidir_p_iv.h"
#include "aes16_bidir_ctx_RoundKey.h"
namespace ap_rtl {
struct aes16_bidir : public sc_module {
// Port declarations 34
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<32> > key_0;
sc_in< sc_lv<32> > key_1;
sc_in< sc_lv<32> > key_2;
sc_in< sc_lv<32> > key_3;
sc_in< sc_lv<32> > inout_0_i;
sc_out< sc_lv<32> > inout_0_o;
sc_out< sc_logic > inout_0_o_ap_vld;
sc_in< sc_lv<32> > inout_1_i;
sc_out< sc_lv<32> > inout_1_o;
sc_out< sc_logic > inout_1_o_ap_vld;
sc_in< sc_lv<32> > inout_2_i;
sc_out< sc_lv<32> > inout_2_o;
sc_out< sc_logic > inout_2_o_ap_vld;
sc_in< sc_lv<32> > inout_3_i;
sc_out< sc_lv<32> > inout_3_o;
sc_out< sc_logic > inout_3_o_ap_vld;
sc_in< sc_lv<32> > iv_0_i;
sc_out< sc_lv<32> > iv_0_o;
sc_out< sc_logic > iv_0_o_ap_vld;
sc_in< sc_lv<32> > iv_1_i;
sc_out< sc_lv<32> > iv_1_o;
sc_out< sc_logic > iv_1_o_ap_vld;
sc_in< sc_lv<32> > iv_2_i;
sc_out< sc_lv<32> > iv_2_o;
sc_out< sc_logic > iv_2_o_ap_vld;
sc_in< sc_lv<32> > iv_3_i;
sc_out< sc_lv<32> > iv_3_o;
sc_out< sc_logic > iv_3_o_ap_vld;
// Module declarations
aes16_bidir(sc_module_name name);
SC_HAS_PROCESS(aes16_bidir);
~aes16_bidir();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
AES_CTR_xcrypt_buffe_buffer* p_key_U;
AES_CTR_xcrypt_buffe_x* p_text_U;
aes16_bidir_p_iv* p_iv_U;
aes16_bidir_ctx_RoundKey* ctx_RoundKey_U;
AES_CTR_xcrypt_buffe_buffer* ctx_Iv_U;
KeyExpansion* grp_KeyExpansion_fu_394;
AES_CTR_xcrypt_buffe* grp_AES_CTR_xcrypt_buffe_fu_402;
aes16_bidir_mux_42_32_1_1<1,1,32,32,32,32,2,32>* aes16_bidir_mux_42_32_1_1_U15;
aes16_bidir_mux_42_32_1_1<1,1,32,32,32,32,2,32>* aes16_bidir_mux_42_32_1_1_U16;
aes16_bidir_mux_42_32_1_1<1,1,32,32,32,32,2,32>* aes16_bidir_mux_42_32_1_1_U17;
sc_signal< sc_lv<10> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<3> > i_2_fu_417_p2;
sc_signal< sc_lv<3> > i_2_reg_663;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<32> > tmp_fu_427_p6;
sc_signal< sc_lv<32> > tmp_reg_668;
sc_signal< sc_lv<1> > icmp_ln23_fu_411_p2;
sc_signal< sc_lv<4> > shl_ln25_1_fu_441_p3;
sc_signal< sc_lv<4> > shl_ln25_1_reg_673;
sc_signal< sc_lv<32> > tmp_1_fu_449_p6;
sc_signal< sc_lv<32> > tmp_1_reg_678;
sc_signal< sc_lv<32> > tmp_2_fu_463_p6;
sc_signal< sc_lv<32> > tmp_2_reg_683;
sc_signal< sc_lv<3> > k_1_fu_487_p2;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<5> > k_fu_557_p2;
sc_signal< sc_lv<5> > k_reg_699;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<64> > zext_ln249_fu_563_p1;
sc_signal< sc_lv<64> > zext_ln249_reg_704;
sc_signal< sc_lv<1> > icmp_ln249_fu_551_p2;
sc_signal< sc_lv<3> > i_fu_574_p2;
sc_signal< sc_lv<3> > i_reg_717;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<2> > trunc_ln55_fu_580_p1;
sc_signal< sc_lv<2> > trunc_ln55_reg_722;
sc_signal< sc_lv<1> > icmp_ln54_fu_568_p2;
sc_signal< sc_lv<4> > shl_ln1_fu_584_p3;
sc_signal< sc_lv<4> > shl_ln1_reg_726;
sc_signal< sc_lv<8> > p_text_q0;
sc_signal< sc_lv<8> > p_text_load_reg_752;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_lv<8> > p_text_q1;
sc_signal< sc_lv<8> > p_text_load_1_reg_757;
sc_signal< sc_lv<8> > ctx_Iv_q0;
sc_signal< sc_lv<8> > ctx_Iv_load_reg_772;
sc_signal< sc_lv<8> > ctx_Iv_q1;
sc_signal< sc_lv<8> > ctx_Iv_load_1_reg_777;
sc_signal< sc_lv<4> > p_key_address0;
sc_signal< sc_logic > p_key_ce0;
sc_signal< sc_logic > p_key_we0;
sc_signal< sc_lv<8> > p_key_d0;
sc_signal< sc_lv<8> > p_key_q0;
sc_signal< sc_logic > p_key_ce1;
sc_signal< sc_lv<8> > p_key_q1;
sc_signal< sc_lv<4> > p_text_address0;
sc_signal< sc_logic > p_text_ce0;
sc_signal< sc_logic > p_text_we0;
sc_signal< sc_lv<8> > p_text_d0;
sc_signal< sc_lv<4> > p_text_address1;
sc_signal< sc_logic > p_text_ce1;
sc_signal< sc_logic > p_text_we1;
sc_signal< sc_lv<4> > p_iv_address0;
sc_signal< sc_logic > p_iv_ce0;
sc_signal< sc_logic > p_iv_we0;
sc_signal< sc_lv<8> > p_iv_d0;
sc_signal< sc_lv<8> > p_iv_q0;
sc_signal< sc_lv<8> > ctx_RoundKey_address0;
sc_signal< sc_logic > ctx_RoundKey_ce0;
sc_signal< sc_logic > ctx_RoundKey_we0;
sc_signal< sc_lv<8> > ctx_RoundKey_q0;
sc_signal< sc_lv<8> > ctx_RoundKey_address1;
sc_signal< sc_logic > ctx_RoundKey_ce1;
sc_signal< sc_logic > ctx_RoundKey_we1;
sc_signal< sc_lv<8> > ctx_RoundKey_q1;
sc_signal< sc_lv<4> > ctx_Iv_address0;
sc_signal< sc_logic > ctx_Iv_ce0;
sc_signal< sc_logic > ctx_Iv_we0;
sc_signal< sc_lv<8> > ctx_Iv_d0;
sc_signal< sc_lv<4> > ctx_Iv_address1;
sc_signal< sc_logic > ctx_Iv_ce1;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_ap_start;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_ap_done;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_ap_idle;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_ap_ready;
sc_signal< sc_lv<8> > grp_KeyExpansion_fu_394_RoundKey_address0;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_RoundKey_ce0;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_RoundKey_we0;
sc_signal< sc_lv<8> > grp_KeyExpansion_fu_394_RoundKey_d0;
sc_signal< sc_lv<8> > grp_KeyExpansion_fu_394_RoundKey_address1;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_RoundKey_ce1;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_RoundKey_we1;
sc_signal< sc_lv<8> > grp_KeyExpansion_fu_394_RoundKey_d1;
sc_signal< sc_lv<4> > grp_KeyExpansion_fu_394_Key_address0;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_Key_ce0;
sc_signal< sc_lv<4> > grp_KeyExpansion_fu_394_Key_address1;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_Key_ce1;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ap_start;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ap_done;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ap_idle;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ap_ready;
sc_signal< sc_lv<8> > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_RoundKey_address0;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_RoundKey_ce0;
sc_signal< sc_lv<8> > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_RoundKey_address1;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_RoundKey_ce1;
sc_signal< sc_lv<4> > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_Iv_address0;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_Iv_ce0;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_Iv_we0;
sc_signal< sc_lv<8> > grp_AES_CTR_xcrypt_buffe_fu_402_ctx_Iv_d0;
sc_signal< sc_lv<4> > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_address0;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_ce0;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_we0;
sc_signal< sc_lv<8> > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_d0;
sc_signal< sc_lv<4> > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_address1;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_ce1;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_we1;
sc_signal< sc_lv<8> > grp_AES_CTR_xcrypt_buffe_fu_402_buf_r_d1;
sc_signal< sc_lv<3> > i_0_reg_350;
sc_signal< sc_lv<1> > icmp_ln24_fu_481_p2;
sc_signal< sc_lv<3> > k_0_reg_361;
sc_signal< sc_lv<5> > k_0_i_reg_372;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<3> > i_1_reg_383;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_logic > grp_KeyExpansion_fu_394_ap_start_reg;
sc_signal< sc_logic > grp_AES_CTR_xcrypt_buffe_fu_402_ap_start_reg;
sc_signal< sc_lv<64> > zext_ln25_fu_524_p1;
sc_signal< sc_lv<64> > zext_ln55_fu_598_p1;
sc_signal< sc_lv<64> > zext_ln55_1_fu_610_p1;
sc_signal< sc_lv<64> > zext_ln55_2_fu_621_p1;
sc_signal< sc_lv<64> > zext_ln55_3_fu_627_p1;
sc_signal< sc_lv<32> > or_ln55_5_fu_632_p5;
sc_signal< sc_lv<32> > or_ln59_2_fu_646_p5;
sc_signal< sc_lv<8> > trunc_ln26_fu_536_p1;
sc_signal< sc_lv<2> > trunc_ln25_fu_423_p1;
sc_signal< sc_lv<2> > trunc_ln25_1_fu_493_p1;
sc_signal< sc_lv<5> > shl_ln_fu_497_p3;
sc_signal< sc_lv<32> > zext_ln25_1_fu_505_p1;
sc_signal< sc_lv<32> > lshr_ln25_fu_509_p2;
sc_signal< sc_lv<4> > zext_ln24_fu_477_p1;
sc_signal< sc_lv<4> > add_ln25_fu_519_p2;
sc_signal< sc_lv<32> > lshr_ln26_fu_531_p2;
sc_signal< sc_lv<32> > lshr_ln27_fu_541_p2;
sc_signal< sc_lv<4> > or_ln55_fu_592_p2;
sc_signal< sc_lv<4> > or_ln55_1_fu_604_p2;
sc_signal< sc_lv<4> > or_ln55_2_fu_616_p2;
sc_signal< sc_lv<10> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<10> ap_ST_fsm_state1;
static const sc_lv<10> ap_ST_fsm_state2;
static const sc_lv<10> ap_ST_fsm_state3;
static const sc_lv<10> ap_ST_fsm_state4;
static const sc_lv<10> ap_ST_fsm_state5;
static const sc_lv<10> ap_ST_fsm_state6;
static const sc_lv<10> ap_ST_fsm_state7;
static const sc_lv<10> ap_ST_fsm_state8;
static const sc_lv<10> ap_ST_fsm_state9;
static const sc_lv<10> ap_ST_fsm_state10;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<5> ap_const_lv5_10;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<4> ap_const_lv4_3;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<4> ap_const_lv4_1;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln25_fu_519_p2();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state9();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ctx_Iv_address0();
void thread_ctx_Iv_address1();
void thread_ctx_Iv_ce0();
void thread_ctx_Iv_ce1();
void thread_ctx_Iv_d0();
void thread_ctx_Iv_we0();
void thread_ctx_RoundKey_address0();
void thread_ctx_RoundKey_address1();
void thread_ctx_RoundKey_ce0();
void thread_ctx_RoundKey_ce1();
void thread_ctx_RoundKey_we0();
void thread_ctx_RoundKey_we1();
void thread_grp_AES_CTR_xcrypt_buffe_fu_402_ap_start();
void thread_grp_KeyExpansion_fu_394_ap_start();
void thread_i_2_fu_417_p2();
void thread_i_fu_574_p2();
void thread_icmp_ln23_fu_411_p2();
void thread_icmp_ln249_fu_551_p2();
void thread_icmp_ln24_fu_481_p2();
void thread_icmp_ln54_fu_568_p2();
void thread_inout_0_o();
void thread_inout_0_o_ap_vld();
void thread_inout_1_o();
void thread_inout_1_o_ap_vld();
void thread_inout_2_o();
void thread_inout_2_o_ap_vld();
void thread_inout_3_o();
void thread_inout_3_o_ap_vld();
void thread_iv_0_o();
void thread_iv_0_o_ap_vld();
void thread_iv_1_o();
void thread_iv_1_o_ap_vld();
void thread_iv_2_o();
void thread_iv_2_o_ap_vld();
void thread_iv_3_o();
void thread_iv_3_o_ap_vld();
void thread_k_1_fu_487_p2();
void thread_k_fu_557_p2();
void thread_lshr_ln25_fu_509_p2();
void thread_lshr_ln26_fu_531_p2();
void thread_lshr_ln27_fu_541_p2();
void thread_or_ln55_1_fu_604_p2();
void thread_or_ln55_2_fu_616_p2();
void thread_or_ln55_5_fu_632_p5();
void thread_or_ln55_fu_592_p2();
void thread_or_ln59_2_fu_646_p5();
void thread_p_iv_address0();
void thread_p_iv_ce0();
void thread_p_iv_d0();
void thread_p_iv_we0();
void thread_p_key_address0();
void thread_p_key_ce0();
void thread_p_key_ce1();
void thread_p_key_d0();
void thread_p_key_we0();
void thread_p_text_address0();
void thread_p_text_address1();
void thread_p_text_ce0();
void thread_p_text_ce1();
void thread_p_text_d0();
void thread_p_text_we0();
void thread_p_text_we1();
void thread_shl_ln1_fu_584_p3();
void thread_shl_ln25_1_fu_441_p3();
void thread_shl_ln_fu_497_p3();
void thread_trunc_ln25_1_fu_493_p1();
void thread_trunc_ln25_fu_423_p1();
void thread_trunc_ln26_fu_536_p1();
void thread_trunc_ln55_fu_580_p1();
void thread_zext_ln249_fu_563_p1();
void thread_zext_ln24_fu_477_p1();
void thread_zext_ln25_1_fu_505_p1();
void thread_zext_ln25_fu_524_p1();
void thread_zext_ln55_1_fu_610_p1();
void thread_zext_ln55_2_fu_621_p1();
void thread_zext_ln55_3_fu_627_p1();
void thread_zext_ln55_fu_598_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include <systemc.h>
//#if __RTL_SIMULATION__
//#include "cnn_rtl_wrapper.h"
//#else
//#include "hwcore/cnn/cnn.h"
//#endif
#include "hwcore/cnn/cnn.h"
#include "hwcore/hf/helperlib.h"
#include "hwcore/pipes/pipes.h"
#if __RTL_SIMULATION__
//#include "DMA_performance_tester_rtl_wrapper.h"
//#else
//#include "DMA_generic_performance_tester.hpp"
#endif
SC_MODULE(mon_CNN) {
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
reset.write(false);
for (int i = 0; i < 20; i++)
wait();
int counter = 1;
int last_count = 1;
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
sc_fixed<DATA_W, DATA_P> Y_golden[16 * 16];
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16; b++) {
sc_fixed<DATA_W, DATA_P> tmp = 0;
for (int wi = 0; wi < 16; wi++) {
tmp += Win[wi + (b * 16)] * Xin[(a * 16) + wi];
}
Y_golden[(a * 16) + b] = tmp;
}
}
sc_fixed<DATA_W, DATA_P> Y[16 * 16];
hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> tmp;
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16 / OUTPUT_BW_N; b++) {
tmp = data_in.read();
sc_fixed<DATA_W, DATA_P> data_in[OUTPUT_BW_N];
tmp.getDataFixed<DATA_W, DATA_P, OUTPUT_BW_N>(data_in);
for (int i = 0; i < OUTPUT_BW_N; i++) {
Y[(a * 16) + (b * OUTPUT_BW_N) + i] = data_in[i];
HLS_DEBUG(1, 1, 0, "got knew value: ")
std::cout << " |--> " << data_in[i].to_float() << " index nr: " << counter << " tlast? "
<< tmp.tlast.to_int() << std::endl
<< std::flush;
counter++;
}
}
}
bool ok = true;
if (tmp.tlast.to_int() != 1) {
ok = false;
std::cout << "error - missing tlast!!!" << std::endl << std::flush;
}
for (int i = 0; i < 16 * 16; i++) {
std::cout << "[ " << i << " ] Y = " << Y[i].to_float() << std::endl
<< std::flush; // " == Y_golden = " << Y_golden[i].to_float() << std::endl << std::flush;
/* if(Y[i]!=Y_golden[i])
{
std::cout << "error not equal!!!" << std::endl << std::flush;
ok = false;
}*/
}
HLS_DEBUG(1, 1, 0, "Simulation done");
if (!ok) {
HLS_DEBUG(1, 1, 0, "Simulation done - with errors!!!");
}
sc_stop();
}
};
SC_MODULE(wave_CNN) {
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl_depth;
sc_out<sc_uint<16 + 1> > ctrl_stride;
sc_out<sc_uint<16 + 1> > ctrl_replay;
sc_out<sc_uint<1 + 1> > ctrl_channel;
sc_out<sc_uint<16 + 1> > ctrl_row_N;
sc_in<sc_uint<1> > ready;
template <class interface, typename T> void do_cmd(interface & itf, T value) {
while (ready.read() == 0) {
wait();
}
itf.write((value << 1) | 0b01);
while (ready.read() == 1) {
wait();
}
while (ready.read() == 0) {
wait();
}
itf.write(0);
wait();
}
SC_CTOR_DEFAULT(wave_CNN) {
SC_CTHREAD(wave_thread, clk.pos());
SC_CTHREAD(sending_ctrls, clk.pos());
}
void sending_ctrls() {
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 20; i++)
wait();
ctrl_channel.write(0);
ctrl_row_N.write(0);
weight_ctrl.write(0);
// data_ctrl.write(0);
do_cmd(ctrl_channel, 0);
do_cmd(ctrl_row_N, 16 / INPUT_BW_N);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
do_cmd(ctrl_depth, 1);
do_cmd(ctrl_replay, 1);
do_cmd(ctrl_stride, 0);
do_cmd(ctrl_row_size_pkg, 1024);
do_cmd(ctrl_window_size, 1);
for (int a = 0; a < 16; a++) {
do_cmd(ctrl_channel, 1);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
// do_cmd(data_ctrl,hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
}
while (true) {
wait();
}
}
void wave_thread() {
// sending dummy weights.
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 15; i++)
wait();
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
HLS_DEBUG(1, 1, 0, "sending data -- weights!----------------------");
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int a = 0; a < (16 * 16) / INPUT_BW_N; a++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Win[a * INPUT_BW_N]);
tmp.setKeep();
if (a == ((16 * 16) / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
// sending input data
HLS_DEBUG(1, 1, 0, "sending data -- Input!----------------------");
for (int a = 0; a < 16; a++) {
for (int i = 0; i < 16 / INPUT_BW_N; i++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Xin[(i * INPUT_BW_N) + (a * 16)]);
tmp.setKeep();
if (a == (16) - 1 && i == (16 / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending Input data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending Input data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
}
/*HLS_DEBUG(1,1,0,"sending data -- Firing!----------------------");
data_ctrl.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);*/
while (true) {
wait();
}
}
};
SC_MODULE(tb_CNN) {
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_signal<sc_uint<16 + 1> > ctrl_window_size;
sc_signal<sc_uint<16 + 1> > ctrl_depth;
sc_signal<sc_uint<16 + 1> > ctrl_stride;
sc_signal<sc_uint<16 + 1> > ctrl_replay;
sc_signal<sc_uint<1 + 1> > ctrl_channel;
sc_signal<sc_uint<16 + 1> > ctrl_row_N;
sc_signal<sc_uint<1> > ready;
// sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
::cnn cnn_u1;
// hwcore::cnn::top_cnn<16,8,1,1,16,16> cnn_u1;
sc_fifo<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > u1_2_mon;
mon_CNN mon;
sc_trace_file *tracePtr;
SC_CTOR_DEFAULT(tb_CNN) : SC_INST(wave), SC_INST(cnn_u1), SC_INST(mon), clk("clk", sc_time(10, SC_NS)) {
SC_MODULE_LINK(wave);
SC_MODULE_LINK(mon);
SC_MODULE_LINK(cnn_u1);
wave.ctrl_row_size_pkg(ctrl_row_size_pkg);
wave.ctrl_window_size(ctrl_window_size);
wave.ctrl_depth(ctrl_depth);
wave.ctrl_stride(ctrl_stride);
wave.ctrl_replay(ctrl_replay);
wave.ready(ready);
wave.data_out(wave_2_u1);
// wave.data_ctrl(data_ctrl);
wave.weight_ctrl(weight_ctrl);
wave.ctrl_row_N(ctrl_row_N);
wave.ctrl_channel(ctrl_channel);
cnn_u1.ready(ready);
cnn_u1.ctrl_row_size_pkg(ctrl_row_size_pkg);
cnn_u1.ctrl_window_size(ctrl_window_size);
cnn_u1.ctrl_depth(ctrl_depth);
cnn_u1.ctrl_stride(ctrl_stride);
cnn_u1.ctrl_replay(ctrl_replay);
cnn_u1.ctrl_row_N(ctrl_row_N);
cnn_u1.weight_ctrls(weight_ctrl);
// cnn_u1.data_ctrls(data_ctrl);
cnn_u1.ctrl_channel(ctrl_channel);
cnn_u1.data_sink(wave_2_u1);
cnn_u1.data_source(u1_2_mon);
mon.data_in(u1_2_mon);
tracePtr = sc_create_vcd_trace_file("tb_CNN");
trace(tracePtr);
}
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
SC_TRACE_ADD_MODULE(wave_2_u1);
SC_TRACE_ADD_MODULE(data_ctrl);
SC_TRACE_ADD_MODULE(weight_ctrl);
SC_TRACE_ADD_MODULE(ctrl_row_N);
SC_TRACE_ADD_MODULE(ctrl_channel);
SC_TRACE_ADD_MODULE(cnn_u1);
SC_TRACE_ADD_MODULE(u1_2_mon);
}
virtual ~tb_CNN() { sc_close_vcd_trace_file(tracePtr); }
};
/*{
#define SC_FIFO_IN_TRANSACTOR_ADD_SIGNALS(portName,width,if_type)\
sc_signal<if_type > dma_sink_dout;\
sc_signal< sc_logic > portName##_read;\
sc_signal< sc_logic > portName##_empty_n;\
sc_signal< sc_lv<width> > portName##_0_dout\
sc_signal< sc_logic > portName##_0_read;\
sc_signal< sc_lv<1> > portName##_1_dout;\
sc_signal< sc_logic > portName##_1_read;\
sc_signal< sc_lv<width/8> > portName##_2_dout;
#define SC_FIFO_IN_TRANSACTOR_ADD(inst,portName,id)\
inst.portName##_##id##_empty_n(portName##_empty_n);\
inst.portName##_##id##_read(portName##_read);\
inst.portName##_##id##_dout(portName##_dout_0);
#define SC_FIFO_IN_TRANSACTOR_CREATE(inst,portName, width, if_type, fifo) \
SC_FIFO_in_transactor<0, if_type >* portName##_inFifo_tr = new SC_FIFO_in_transactor<0, if_type
>(#portName"_inFifo_tr", AESL_ResetType::active_high_sync);\
portName##_inFifo_tr->rst(reset);\
portName##_inFifo_tr->FifoIn(fifo);\
portName##_inFifo_tr->clock(clk);\
portName##_inFifo_tr->if_empty_n(portName##_empty_n);\
portName##_inFifo_tr->if_read(portName##_read);\
portName##_inFifo_tr->if_dout(portName##_dout);\
SC_FIFO_IN_TRANSACTOR_ADD(cnn_u1,data_sink,0);\
SC_FIFO_IN_TRANSACTOR_ADD(cnn_u1,data_sink,1);\
SC_FIFO_IN_TRANSACTOR_ADD(cnn_u1,data_sink,2);\
portName##_dout_0.write((sc_lv<width>)(portName##_dout.read().data));\
portName##_dout_1.write((sc_lv<1>)(portName##_dout.read().tlast));\
portName##_dout_2.write((sc_lv<width/8>)(portName##_dout.read().tkeep));
}*/
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_before_axismixer_xlconstant_3_0_H_
#define _design_1_before_axismixer_xlconstant_3_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class design_1_before_axismixer_xlconstant_3_0 : public sc_module {
public:
xlconstant_v1_1_7<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_before_axismixer_xlconstant_3_0 (sc_core::sc_module_name name);
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Loop_Xpose_Col_Outer_HH_
#define _Loop_Xpose_Col_Outer_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Loop_Xpose_Col_Outer : public sc_module {
// Port declarations 14
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<6> > col_outbuf_i_address0;
sc_out< sc_logic > col_outbuf_i_ce0;
sc_in< sc_lv<16> > col_outbuf_i_q0;
sc_out< sc_lv<6> > buf_2d_out_address0;
sc_out< sc_logic > buf_2d_out_ce0;
sc_out< sc_logic > buf_2d_out_we0;
sc_out< sc_lv<16> > buf_2d_out_d0;
// Module declarations
Loop_Xpose_Col_Outer(sc_module_name name);
SC_HAS_PROCESS(Loop_Xpose_Col_Outer);
~Loop_Xpose_Col_Outer();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<3> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<7> > indvar_flatten_reg_73;
sc_signal< sc_lv<4> > j_1_i_reg_84;
sc_signal< sc_lv<4> > i_3_i_reg_95;
sc_signal< sc_lv<1> > icmp_ln92_fu_106_p2;
sc_signal< sc_lv<1> > icmp_ln92_reg_204;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< bool > ap_block_state2_pp0_stage0_iter0;
sc_signal< bool > ap_block_state3_pp0_stage0_iter1;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<7> > add_ln92_fu_112_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<4> > select_ln95_fu_130_p3;
sc_signal< sc_lv<4> > select_ln95_reg_213;
sc_signal< sc_lv<4> > select_ln95_1_fu_138_p3;
sc_signal< sc_lv<4> > select_ln95_1_reg_218;
sc_signal< sc_lv<4> > i_fu_173_p2;
sc_signal< bool > ap_block_state1;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< sc_lv<4> > ap_phi_mux_j_1_i_phi_fu_88_p4;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<64> > zext_ln95_4_fu_168_p1;
sc_signal< sc_lv<64> > zext_ln95_5_fu_199_p1;
sc_signal< sc_lv<1> > icmp_ln94_fu_124_p2;
sc_signal< sc_lv<4> > j_fu_118_p2;
sc_signal< sc_lv<7> > tmp_3_fu_150_p3;
sc_signal< sc_lv<8> > zext_ln95_fu_146_p1;
sc_signal< sc_lv<8> > zext_ln95_3_fu_158_p1;
sc_signal< sc_lv<8> > add_ln95_fu_162_p2;
sc_signal< sc_lv<7> > tmp_fu_179_p3;
sc_signal< sc_lv<8> > zext_ln95_2_fu_190_p1;
sc_signal< sc_lv<8> > zext_ln95_1_fu_186_p1;
sc_signal< sc_lv<8> > add_ln95_1_fu_193_p2;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<3> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<3> ap_ST_fsm_state1;
static const sc_lv<3> ap_ST_fsm_pp0_stage0;
static const sc_lv<3> ap_ST_fsm_state4;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_1;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<7> ap_const_lv7_0;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<7> ap_const_lv7_40;
static const sc_lv<7> ap_const_lv7_1;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<4> ap_const_lv4_8;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<32> ap_const_lv32_2;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln92_fu_112_p2();
void thread_add_ln95_1_fu_193_p2();
void thread_add_ln95_fu_162_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state4();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state2_pp0_stage0_iter0();
void thread_ap_block_state3_pp0_stage0_iter1();
void thread_ap_condition_pp0_exit_iter0_state2();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_phi_mux_j_1_i_phi_fu_88_p4();
void thread_ap_ready();
void thread_buf_2d_out_address0();
void thread_buf_2d_out_ce0();
void thread_buf_2d_out_d0();
void thread_buf_2d_out_we0();
void thread_col_outbuf_i_address0();
void thread_col_outbuf_i_ce0();
void thread_i_fu_173_p2();
void thread_icmp_ln92_fu_106_p2();
void thread_icmp_ln94_fu_124_p2();
void thread_j_fu_118_p2();
void thread_select_ln95_1_fu_138_p3();
void thread_select_ln95_fu_130_p3();
void thread_tmp_3_fu_150_p3();
void thread_tmp_fu_179_p3();
void thread_zext_ln95_1_fu_186_p1();
void thread_zext_ln95_2_fu_190_p1();
void thread_zext_ln95_3_fu_158_p1();
void thread_zext_ln95_4_fu_168_p1();
void thread_zext_ln95_5_fu_199_p1();
void thread_zext_ln95_fu_146_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_CAN_BRIDGE_H
#define VCML_CAN_BRIDGE_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
#include "vcml/core/module.h"
#include "vcml/core/model.h"
#include "vcml/properties/property.h"
#include "vcml/protocols/can.h"
#include "vcml/models/can/backend.h"
namespace vcml {
namespace can {
class backend;
class bridge : public module, public can_host
{
private:
size_t m_next_id;
unordered_map<size_t, backend*> m_dynamic_backends;
vector<backend*> m_backends;
mutable mutex m_mtx;
queue<can_frame> m_rx;
sc_event m_ev;
bool cmd_create_backend(const vector<string>& args, ostream& os);
bool cmd_destroy_backend(const vector<string>& args, ostream& os);
bool cmd_list_backends(const vector<string>& args, ostream& os);
virtual void can_receive(can_frame& frame) override;
void can_transmit();
static unordered_map<string, bridge*>& bridges();
public:
property<string> backends;
can_initiator_socket can_tx;
can_target_socket can_rx;
bridge(const sc_module_name& nm);
virtual ~bridge();
VCML_KIND(can::bridge);
void send_to_host(const can_frame& frame);
void send_to_guest(can_frame frame);
void attach(backend* b);
void detach(backend* b);
size_t create_backend(const string& type);
bool destroy_backend(size_t id);
static bridge* find(const string& name);
static vector<bridge*> all();
template <typename T>
void connect(T& device) {
can_tx.bind(device.can_rx);
device.can_tx.bind(can_rx);
}
};
} // namespace can
} // namespace vcml
#endif
|
#include "systemc.h"
#include <bitset>
#include "../cnm_base.h"
SC_MODULE(cu_monitor) {
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logic> ACT; // DRAM activate command
// sc_in<sc_logic> RSTB; //
sc_in<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_in<sc_lv<64> > DQ; // Data input from DRAM controller (output makes no sense
sc_in<sc_lv<32> > instr; // Instruction input from CRF
sc_in<sc_lv<32> > pc_out; // PC to the CRF
sc_in<sc_lv<GRF_WIDTH> > data_out; // Data to the RFs
// CRF Control
sc_in<sc_logic> crf_wr_en; //Enables writing of a received instruction
sc_in<sc_lv<32> > crf_wr_addr; //Index for writing the received instructions from processor
// SRF Control
sc_in<sc_lv<32> > srf_rd_addr; // Index read
sc_in<sc_logic> srf_rd_a_nm; // Signals if reading from SRF_A (high) or SRF_M (low)
sc_in<sc_logic> srf_wr_en; // Enable writing
sc_in<sc_lv<32> > srf_wr_addr; // Index the address to be written
sc_in<sc_logic> srf_wr_a_nm; // Signals if writing to SRF_A (high) or SRF_M (low)
sc_in<sc_lv<8> > srf_wr_from; // Index the MUX for input data
// GRF_A Control
sc_in<sc_lv<32> > grfa_rd_addr1; // Index read at port 1
sc_in<sc_lv<32> > grfa_rd_addr2; // Index read at port 2
sc_in<sc_logic> grfa_wr_en; // Enables writing
sc_in<sc_logic> grfa_relu_en; // Enable ReLU for the MOV instruction
sc_in<sc_lv<32> > grfa_wr_addr; // Index the address to be written
sc_in<sc_lv<8> > grfa_wr_from; // Index the MUX for input data
// GRF_B Control
sc_in<sc_lv<32> > grfb_rd_addr1; // Index read at port 1
sc_in<sc_lv<32> > grfb_rd_addr2; // Index read at port 2
sc_in<sc_logic> grfb_wr_en; // Enables writing
sc_in<sc_logic> grfb_relu_en; // Enable ReLU for the MOV instruction
sc_in<sc_lv<32> > grfb_wr_addr; // Index the address to be written
sc_in<sc_lv<8> > grfb_wr_from; // Index the MUX for input data
// FPU Control
sc_in<sc_logic> fpu_mult_en; // Signals that a multiplication computation step should be performed
sc_in<sc_logic> fpu_add_en; // Signals that an addition computation step should be performed
sc_in<sc_lv<8> > fpu_mult_in1_sel; // Selects input 1 for multiplication
sc_in<sc_lv<8> > fpu_mult_in2_sel; // Selects input 2 for multiplication
sc_in<sc_lv<8> > fpu_add_in1_sel; // Selects input 1 for addition
sc_in<sc_lv<8> > fpu_add_in2_sel; // Selects input 2 for addition
sc_in<sc_logic> fpu_out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#else
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> RD; // DRAM read command
sc_in<bool> WR; // DRAM write command
sc_in<bool> ACT; // DRAM activate command
// sc_in<bool> RSTB; //
sc_in<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<bool> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_in<uint64_t> DQ; // Data input from DRAM controller (output makes no sense
sc_in<uint32_t> instr; // Instruction input from CRF
sc_in<uint> pc_out; // PC to the CRF
sc_in<sc_biguint<GRF_WIDTH> > data_out; // Data to the RFs
// CRF Control
sc_in<bool> crf_wr_en; // Enables writing of a received instruction
sc_in<uint> crf_wr_addr; // Index for writing the received instructions from processor
// SRF Control
sc_in<uint> srf_rd_addr; // Index read
sc_in<bool> srf_rd_a_nm; // Signals if reading from SRF_A (high) or SRF_M (low)
sc_in<bool> srf_wr_en; // Enable writing
sc_in<uint> srf_wr_addr; // Index the address to be written
sc_in<bool> srf_wr_a_nm; // Signals if writing to SRF_A (high) or SRF_M (low)
sc_in<uint8_t> srf_wr_from; // Index the MUX for input data
// GRF_A Control
sc_in<uint> grfa_rd_addr1; // Index read at port 1
sc_in<uint> grfa_rd_addr2; // Index read at port 2
sc_in<bool> grfa_wr_en; // Enables writing
sc_in<bool> grfa_relu_en; // Enable ReLU for the MOV instruction
sc_in<uint> grfa_wr_addr; // Index the address to be written
sc_in<uint8_t> grfa_wr_from; // Index the MUX for input data
// GRF_B Control
sc_in<uint> grfb_rd_addr1; // Index read at port 1
sc_in<uint> grfb_rd_addr2; // Index read at port 2
sc_in<bool> grfb_wr_en; // Enables writing
sc_in<bool> grfb_relu_en; // Enable ReLU for the MOV instruction
sc_in<uint> grfb_wr_addr; // Index the address to be written
sc_in<uint8_t> grfb_wr_from; // Index the MUX for input data
// FPU Control
sc_in<bool> fpu_mult_en; // Signals that a multiplication computation step should be performed
sc_in<bool> fpu_add_en; // Signals that an addition computation step should be performed
sc_in<uint8_t> fpu_mult_in1_sel; // Selects input 1 for multiplication
sc_in<uint8_t> fpu_mult_in2_sel; // Selects input 2 for multiplication
sc_in<uint8_t> fpu_add_in1_sel; // Selects input 1 for addition
sc_in<uint8_t> fpu_add_in2_sel; // Selects input 2 for addition
sc_in<bool> fpu_out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#endif
// Internal events
// Internal variables and signals for checking
SC_CTOR(cu_monitor) {
SC_THREAD(monitor_thread);
sensitive << clk.pos() << rst.neg();
}
void monitor_thread(); // Outputs the behavior for the first SIMD rail, and automatically checks the functionality
// void mirror_thread(); // Mirror FPU behavior for checking its functionality
// void out_mirror_thread(); // Mirror FPU output for checking functionality
};
|
#ifndef IP_ULTRA96V2_VALTEST_ZYNQ_ULTRA_PS_E_0_0_H_
#define IP_ULTRA96V2_VALTEST_ZYNQ_ULTRA_PS_E_0_0_H_
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_H
#include "systemc.h"
#endif
class zynq_ultra_ps_e_tlm;
class ultra96v2_valtest_zynq_ultra_ps_e_0_0 : public sc_module
{
public:
ultra96v2_valtest_zynq_ultra_ps_e_0_0(const sc_module_name& nm);
virtual ~ultra96v2_valtest_zynq_ultra_ps_e_0_0();
public: // module pin-to-pin RTL interface
sc_in< bool > maxihpm0_fpd_aclk;
sc_out< sc_bv<16> > maxigp0_awid;
sc_out< sc_bv<40> > maxigp0_awaddr;
sc_out< sc_bv<8> > maxigp0_awlen;
sc_out< sc_bv<3> > maxigp0_awsize;
sc_out< sc_bv<2> > maxigp0_awburst;
sc_out< bool > maxigp0_awlock;
sc_out< sc_bv<4> > maxigp0_awcache;
sc_out< sc_bv<3> > maxigp0_awprot;
sc_out< bool > maxigp0_awvalid;
sc_out< sc_bv<16> > maxigp0_awuser;
sc_in< bool > maxigp0_awready;
sc_out< sc_bv<128> > maxigp0_wdata;
sc_out< sc_bv<16> > maxigp0_wstrb;
sc_out< bool > maxigp0_wlast;
sc_out< bool > maxigp0_wvalid;
sc_in< bool > maxigp0_wready;
sc_in< sc_bv<16> > maxigp0_bid;
sc_in< sc_bv<2> > maxigp0_bresp;
sc_in< bool > maxigp0_bvalid;
sc_out< bool > maxigp0_bready;
sc_out< sc_bv<16> > maxigp0_arid;
sc_out< sc_bv<40> > maxigp0_araddr;
sc_out< sc_bv<8> > maxigp0_arlen;
sc_out< sc_bv<3> > maxigp0_arsize;
sc_out< sc_bv<2> > maxigp0_arburst;
sc_out< bool > maxigp0_arlock;
sc_out< sc_bv<4> > maxigp0_arcache;
sc_out< sc_bv<3> > maxigp0_arprot;
sc_out< bool > maxigp0_arvalid;
sc_out< sc_bv<16> > maxigp0_aruser;
sc_in< bool > maxigp0_arready;
sc_in< sc_bv<16> > maxigp0_rid;
sc_in< sc_bv<128> > maxigp0_rdata;
sc_in< sc_bv<2> > maxigp0_rresp;
sc_in< bool > maxigp0_rlast;
sc_in< bool > maxigp0_rvalid;
sc_out< bool > maxigp0_rready;
sc_out< sc_bv<4> > maxigp0_awqos;
sc_out< sc_bv<4> > maxigp0_arqos;
sc_in< bool > maxihpm1_fpd_aclk;
sc_out< sc_bv<16> > maxigp1_awid;
sc_out< sc_bv<40> > maxigp1_awaddr;
sc_out< sc_bv<8> > maxigp1_awlen;
sc_out< sc_bv<3> > maxigp1_awsize;
sc_out< sc_bv<2> > maxigp1_awburst;
sc_out< bool > maxigp1_awlock;
sc_out< sc_bv<4> > maxigp1_awcache;
sc_out< sc_bv<3> > maxigp1_awprot;
sc_out< bool > maxigp1_awvalid;
sc_out< sc_bv<16> > maxigp1_awuser;
sc_in< bool > maxigp1_awready;
sc_out< sc_bv<128> > maxigp1_wdata;
sc_out< sc_bv<16> > maxigp1_wstrb;
sc_out< bool > maxigp1_wlast;
sc_out< bool > maxigp1_wvalid;
sc_in< bool > maxigp1_wready;
sc_in< sc_bv<16> > maxigp1_bid;
sc_in< sc_bv<2> > maxigp1_bresp;
sc_in< bool > maxigp1_bvalid;
sc_out< bool > maxigp1_bready;
sc_out< sc_bv<16> > maxigp1_arid;
sc_out< sc_bv<40> > maxigp1_araddr;
sc_out< sc_bv<8> > maxigp1_arlen;
sc_out< sc_bv<3> > maxigp1_arsize;
sc_out< sc_bv<2> > maxigp1_arburst;
sc_out< bool > maxigp1_arlock;
sc_out< sc_bv<4> > maxigp1_arcache;
sc_out< sc_bv<3> > maxigp1_arprot;
sc_out< bool > maxigp1_arvalid;
sc_out< sc_bv<16> > maxigp1_aruser;
sc_in< bool > maxigp1_arready;
sc_in< sc_bv<16> > maxigp1_rid;
sc_in< sc_bv<128> > maxigp1_rdata;
sc_in< sc_bv<2> > maxigp1_rresp;
sc_in< bool > maxigp1_rlast;
sc_in< bool > maxigp1_rvalid;
sc_out< bool > maxigp1_rready;
sc_out< sc_bv<4> > maxigp1_awqos;
sc_out< sc_bv<4> > maxigp1_arqos;
sc_in< sc_bv<1> > emio_gpio_i;
sc_out< sc_bv<1> > emio_gpio_o;
sc_out< sc_bv<1> > emio_gpio_t;
sc_in< bool > emio_uart0_ctsn;
sc_out< bool > emio_uart0_rtsn;
sc_in< bool > emio_uart0_dsrn;
sc_in< bool > emio_uart0_dcdn;
sc_in< bool > emio_uart0_rin;
sc_out< bool > emio_uart0_dtrn;
sc_in< sc_bv<1> > pl_ps_irq0;
sc_out< bool > pl_resetn0;
sc_out< bool > pl_clk0;
public: // module socket-to-socket TLM interface
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_rd_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM1_FPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM1_FPD_rd_socket;
protected:
virtual void before_end_of_elaboration();
private:
ultra96v2_valtest_zynq_ultra_ps_e_0_0(const ultra96v2_valtest_zynq_ultra_ps_e_0_0&);
const ultra96v2_valtest_zynq_ultra_ps_e_0_0& operator=(const ultra96v2_valtest_zynq_ultra_ps_e_0_0&);
zynq_ultra_ps_e_tlm* mp_impl;
xtlm::xaximm_xtlm2pin_t<128,40,16,16,1,1,16,1>* mp_M_AXI_HPM0_FPD_transactor;
sc_signal< bool > m_M_AXI_HPM0_FPD_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<128,40,16,16,1,1,16,1>* mp_M_AXI_HPM1_FPD_transactor;
sc_signal< bool > m_M_AXI_HPM1_FPD_transactor_rst_signal;
};
#endif // IP_ULTRA96V2_VALTEST_ZYNQ_ULTRA_PS_E_0_0_H_
|
// Copyright 1991-2014 Mentor Graphics Corporation
// All Rights Reserved.
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
// OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
#ifndef INCLUDED_CONTROL
#define INCLUDED_CONTROL
#include <systemc.h>
class control : public sc_module
{
public:
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_uint<9> > ramadrs;
sc_out<bool> oeenable;
sc_out<bool> txc;
sc_out<bool> outstrobe;
// Class methods
void incrementer();
void enable_gen();
void outstrobe_gen();
// Constructor
SC_CTOR(control)
: clock("clock"),
reset("reset"),
ramadrs("ramadrs"),
oeenable("oeenable"),
txc("txc"),
outstrobe("outstrobe")
{
SC_METHOD(incrementer);
sensitive << clock.pos();
dont_initialize();
SC_METHOD(enable_gen);
sensitive << clock.pos();
dont_initialize();
SC_METHOD(outstrobe_gen);
sensitive << ramadrs;
dont_initialize();
}
// Empty Destructor
~control()
{
}
};
//
// This process increments the ram address.
//
inline void control::incrementer()
{
if (reset.read() == 0)
ramadrs.write(0);
else
ramadrs.write(ramadrs.read() + 1);
}
//
// This process generates the output enable signal.
//
inline void control::enable_gen()
{
if (reset.read() == 0)
oeenable.write(0);
else
{
if (ramadrs.read().range(4, 0) == 0)
oeenable.write(1);
else
oeenable.write(0);
}
}
//
// This process generates the outstrobe and the txc data line.
//
inline void control::outstrobe_gen()
{
bool x = 1;
for (int i = 4; i < 9; i++)
x &= (bool)ramadrs.read()[i];
outstrobe.write(x);
txc.write((bool)ramadrs.read()[4]);
}
#endif
|
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux8) {
sc_in <bool> sel;
sc_in <sc_int<8>> in0;
sc_in <sc_int<8>> in1;
sc_out <sc_int<8>> out;
/*
** module global variables
*/
SC_CTOR (Mux8){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
void process () {
if(!sel.read()){
out.write(in0.read());
}
else{
out.write(in1.read());
}
}
};
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: SC Consumer
//
// Topic: Description
//
// A simple SC consumer TLM model that prints received transactions (of type
// ~tlm_generic_payload~ and sends them out its ~ap~ analysis port.
//
// This example uses the ~simple_target_socket~, a derivative of the TLM
// core class, ~tlm_target_socket~. Unlike the ~tlm_target_socket~, the simple
// socket does not require the module to inherit and implement all four
// target socket interface methods. Instead, you only need to register the
// interfaces you actually implement, ~b_transport~ in this case. This is what
// makes these sockets simple, flexible, and convenient.
//
// While trivial in functionality, the model demonstrates use of TLM ports
// to facilitate external communication.
//
// - Users of the model are not coupled to its internal implementation, using
// only the provided TLM port and socket to communicate.
//
// - The model itself does not refer to anything outside its encapsulated
// implementation. It does not know nor care about what might
// be driving its ~in~ socket or who might be listening on its ~ap~
// analysis port.
//-----------------------------------------------------------------------------
// (inline source)
#include <string>
#include <iomanip>
using std::string;
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace tlm;
#include "simple_target_socket.h"
using tlm_utils::simple_target_socket;
class consumer : public sc_module
{
public:
simple_target_socket<consumer> in; // defaults to tlm_gp
tlm_analysis_port<tlm_generic_payload> ap;
consumer(sc_module_name nm) : in("in"), ap("ap")
{
in.register_b_transport(this, &consumer::b_transport);
}
virtual void b_transport(tlm_generic_payload &gp, sc_time &t) {
char unsigned *data;
int len;
len = gp.get_data_length();
data = gp.get_data_ptr();
cout << sc_time_stamp() << " [CONSUMER/GP/RECV] ";
cout << "cmd:" << gp.get_command()
<< " addr:" << hex << gp.get_address() << " data:{ ";
for (int i=0; i<len; i++)
cout << hex << (int)*(data+i) << " ";
cout << "}" << endl;
wait(t);
t = SC_ZERO_TIME;
ap.write(gp);
}
};
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
/****************************************************************************
*
* This file contains the dut_type_wrapper module
* for use in the verilog verification wrapper dut_vlwrapper.v
* It creats an instance of the dut module and has threads
* for converting the BEH ports to RTL level ports on the wrapper.
*
****************************************************************************/
#ifndef _DUT_TYPE_WRAP_INCLUDED_
#define _DUT_TYPE_WRAP_INCLUDED_
#include <systemc.h>
#include "dut.h"
// Declaration of wrapper with RTL level ports
SC_MODULE(dut_type_wrapper)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
sc_signal< input_t > din_data;
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
void thread_din_data();
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
};
#endif /* */
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Sobel_HH_
#define _Sobel_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Filter2D.h"
namespace ap_rtl {
struct Sobel : public sc_module {
// Port declarations 13
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<8> > p_src_data_stream_V_dout;
sc_in< sc_logic > p_src_data_stream_V_empty_n;
sc_out< sc_logic > p_src_data_stream_V_read;
sc_out< sc_lv<8> > p_dst_data_stream_V_din;
sc_in< sc_logic > p_dst_data_stream_V_full_n;
sc_out< sc_logic > p_dst_data_stream_V_write;
sc_signal< sc_lv<2> > ap_var_for_const0;
sc_signal< sc_lv<2> > ap_var_for_const1;
sc_signal< sc_lv<3> > ap_var_for_const2;
sc_signal< sc_lv<4> > ap_var_for_const3;
sc_signal< sc_lv<2> > ap_var_for_const4;
sc_signal< sc_lv<3> > ap_var_for_const5;
// Module declarations
Sobel(sc_module_name name);
SC_HAS_PROCESS(Sobel);
~Sobel();
sc_trace_file* mVcdFile;
Filter2D* grp_Filter2D_fu_52;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<2> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_start;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_done;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_idle;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_ready;
sc_signal< sc_logic > grp_Filter2D_fu_52_p_src_data_stream_V_read;
sc_signal< sc_lv<8> > grp_Filter2D_fu_52_p_dst_data_stream_V_din;
sc_signal< sc_logic > grp_Filter2D_fu_52_p_dst_data_stream_V_write;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_start_reg;
sc_signal< bool > ap_block_state1_ignore_call2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<2> > ap_NS_fsm;
sc_signal< bool > ap_block_state1;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<2> ap_ST_fsm_state1;
static const sc_lv<2> ap_ST_fsm_state2;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<3> ap_const_lv3_6;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<3> ap_const_lv3_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_var_for_const2();
void thread_ap_var_for_const3();
void thread_ap_var_for_const4();
void thread_ap_var_for_const5();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_block_state1();
void thread_ap_block_state1_ignore_call2();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_grp_Filter2D_fu_52_ap_start();
void thread_p_dst_data_stream_V_din();
void thread_p_dst_data_stream_V_write();
void thread_p_src_data_stream_V_read();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_2_0_H_
#define _icyradio_GND_2_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_2_0 : public sc_module {
public:
xlconstant_v1_1_8<1,0> mod;
sc_out< sc_bv<1> > dout;
icyradio_GND_2_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> I2C0_SDA_I;
sc_core::sc_out<bool> I2C0_SDA_O;
sc_core::sc_out<bool> I2C0_SDA_T;
sc_core::sc_in<bool> I2C0_SCL_I;
sc_core::sc_out<bool> I2C0_SCL_O;
sc_core::sc_out<bool> I2C0_SCL_T;
sc_core::sc_out<bool> TTC0_WAVE0_OUT;
sc_core::sc_out<bool> TTC0_WAVE1_OUT;
sc_core::sc_out<bool> TTC0_WAVE2_OUT;
sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
sc_core::sc_out<sc_dt::sc_bv<2> > DMA0_DATYPE;
sc_core::sc_out<bool> DMA0_DAVALID;
sc_core::sc_out<bool> DMA0_DRREADY;
sc_core::sc_out<sc_dt::sc_bv<2> > DMA1_DATYPE;
sc_core::sc_out<bool> DMA1_DAVALID;
sc_core::sc_out<bool> DMA1_DRREADY;
sc_core::sc_in<bool> DMA0_ACLK;
sc_core::sc_in<bool> DMA0_DAREADY;
sc_core::sc_in<bool> DMA0_DRLAST;
sc_core::sc_in<bool> DMA0_DRVALID;
sc_core::sc_in<bool> DMA1_ACLK;
sc_core::sc_in<bool> DMA1_DAREADY;
sc_core::sc_in<bool> DMA1_DRLAST;
sc_core::sc_in<bool> DMA1_DRVALID;
sc_core::sc_in<sc_dt::sc_bv<2> > DMA0_DRTYPE;
sc_core::sc_in<sc_dt::sc_bv<2> > DMA1_DRTYPE;
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> I2C0_SDA_I;
sc_core::sc_out<bool> I2C0_SDA_O;
sc_core::sc_out<bool> I2C0_SDA_T;
sc_core::sc_in<bool> I2C0_SCL_I;
sc_core::sc_out<bool> I2C0_SCL_O;
sc_core::sc_out<bool> I2C0_SCL_T;
sc_core::sc_out<bool> TTC0_WAVE0_OUT;
sc_core::sc_out<bool> TTC0_WAVE1_OUT;
sc_core::sc_out<bool> TTC0_WAVE2_OUT;
sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
sc_core::sc_out<sc_dt::sc_bv<2> > DMA0_DATYPE;
sc_core::sc_out<bool> DMA0_DAVALID;
sc_core::sc_out<bool> DMA0_DRREADY;
sc_core::sc_out<sc_dt::sc_bv<2> > DMA1_DATYPE;
sc_core::sc_out<bool> DMA1_DAVALID;
sc_core::sc_out<bool> DMA1_DRREADY;
sc_core::sc_in<bool> DMA0_ACLK;
sc_core::sc_in<bool> DMA0_DAREADY;
sc_core::sc_in<bool> DMA0_DRLAST;
sc_core::sc_in<bool> DMA0_DRVALID;
sc_core::sc_in<bool> DMA1_ACLK;
sc_core::sc_in<bool> DMA1_DAREADY;
sc_core::sc_in<bool> DMA1_DRLAST;
sc_core::sc_in<bool> DMA1_DRVALID;
sc_core::sc_in<sc_dt::sc_bv<2> > DMA0_DRTYPE;
sc_core::sc_in<sc_dt::sc_bv<2> > DMA1_DRTYPE;
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_a888_one_0_H_
#define _bd_a888_one_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class bd_a888_one_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_a888_one_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_a888_one_0_H_
#define _bd_a888_one_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class bd_a888_one_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_a888_one_0 (sc_core::sc_module_name name);
};
#endif
|
#include <systemc.h>
#include <systemc-ams.h>
#include <config.hpp>
SCA_TDF_MODULE(Power_bus){
//Rate 1ms
//Input Port
sca_tdf::sca_in <double> core_current;
sca_tdf::sca_in <double> core_voltage;
sca_tdf::sca_in <double> voltage_sensors[NUM_SENSORS];
sca_tdf::sca_in <double> current_sensors[NUM_SENSORS];
#if NUM_SOURCES>0
sca_tdf::sca_in <double> current_sources[NUM_SOURCES];
#endif
#if NUM_BATTERIES>0
sca_tdf::sca_out <double> current_batteries[NUM_BATTERIES];
#endif
SCA_CTOR(Power_bus):
core_current("Current_of_CPU"),
core_voltage("Voltage_of_CPU")
{}
void set_attributes();
void initialize();
void processing();
private:
double total_current = 0;
Power_bus(){}
};
|
#ifndef SOBEL_EDGE_DETECTOR_TLM_HPP
#define SOBEL_EDGE_DETECTOR_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "sobel_edge_detector_lt_model.hpp"
#include "img_target.hpp"
//Extended Unification TLM
struct sobel_edge_detector_tlm : public Edge_Detector, public img_target
{
SC_CTOR(sobel_edge_detector_tlm): Edge_Detector(Edge_Detector::name()), img_target(img_target::name()) {
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data);
virtual void do_when_write_transaction(unsigned char*& data);
};
#endif // SOBEL_EDGE_DETECTOR_TLM_HPP
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_fifo.cpp -- SystemC 2.0 Performance Modeling Example.
This example is derived from the design presented within
"An Introduction to System Level Modeling in SystemC 2.0"
By Stuart Swan, Cadence Design Systems.
Available at www.accellera.org
The system being modeled has a producer block that
sends characters to a consumer block via a fifo.
The fifo will suspend the producer or consumer as
necessary to insure all characters are reliably
delivered.
The consumer block will consume exactly one
character every 100 ns unless it is suspended
waiting for input from the fifo.
The producer block produces between one and
19 characters every 1000 ns unless it is
suspended waiting to write to the fifo.
On average, the producer block produces
one character every 100 ns (unless suspended by
the fifo) since a random linear distribution is
used for the character count.
If the fifo size is sufficiently large, the average
transfer time per character will approach 100 ns
since the producer and consumer will rarely be
blocked. However, as the fifo size decreases,
the average transfer time will increase because
the producer will sometimes be suspended when
it writes (due to a full fifo) and the consumer
will sometimes be suspended when it reads
(due to an empty fifo).
The fifo size can be set via a command line argument
when running this program. By default, the fifo size
is 10. When the design is simulated, one hundred
thousand characters are transferred from the
producer to the consumer and then performance
statistics are displayed.
Using this system level model, determine the size
of the fifo needed to sustain:
A) An average transfer time of 110 ns per character
B) An average transfer time of 105 ns per character
Hint: The answer to (A) is between 10 and 20.
Original Author: Stuart Swan, Cadence Design Systems, 2001-06-18
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
class write_if : virtual public sc_interface
{
public:
virtual void write(char) = 0;
virtual void reset() = 0;
};
class read_if : virtual public sc_interface
{
public:
virtual void read(char &) = 0;
virtual int num_available() = 0;
};
class fifo : public sc_channel, public write_if, public read_if
{
public:
fifo(sc_module_name name, int size_) : sc_channel(name), size(size_)
{
data = new char[size];
num_elements = first = 0;
num_read = max_used = average = 0;
last_time = SC_ZERO_TIME;
}
~fifo()
{
delete[] data;
cout << endl << "Fifo size is: " << size << endl;
cout << "Average fifo fill depth: " <<
double(average) / num_read << endl;
cout << "Maximum fifo fill depth: " << max_used << endl;
cout << "Average transfer time per character: "
<< last_time / num_read << endl;
cout << "Total characters transferred: " << num_read << endl;
cout << "Total time: " << last_time << endl;
}
void write(char c) {
if (num_elements == size)
wait(read_event);
data[(first + num_elements) % size] = c;
++ num_elements;
write_event.notify();
}
void read(char &c){
last_time = sc_time_stamp();
if (num_elements == 0)
wait(write_event);
compute_stats();
c = data[first];
-- num_elements;
first = (first + 1) % size;
read_event.notify();
}
void reset() { num_elements = first = 0; }
int num_available() { return num_elements;}
private:
char *data;
int num_elements, first;
sc_event write_event, read_event;
int size, num_read, max_used, average;
sc_time last_time;
void compute_stats()
{
average += num_elements;
if (num_elements > max_used)
max_used = num_elements;
++num_read;
}
};
class producer : public sc_module
{
public:
sc_port<write_if> out;
SC_HAS_PROCESS(producer);
producer(sc_module_name name) : sc_module(name)
{
SC_THREAD(main);
}
void main()
{
const char *str =
"Visit www.accellera.org and see what SystemC can do for you today!\n";
const char *p = str;
int total = 100000;
while (true)
{
int i = 1 + int(19.0 * rand() / RAND_MAX); // 1 <= i <= 19
while (--i >= 0)
{
out->write(*p++);
if (!*p) p = str;
-- total;
}
if (total <= 0)
break;
wait(1000, SC_NS);
}
}
};
class consumer : public sc_module
{
public:
sc_port<read_if> in;
SC_HAS_PROCESS(consumer);
consumer(sc_module_name name) : sc_module(name)
{
SC_THREAD(main);
}
void main()
{
char c;
while (true) {
in->read(c);
wait(100, SC_NS);
}
}
};
class top : public sc_module
{
public:
fifo fifo_inst;
producer prod_inst;
consumer cons_inst;
top(sc_module_name name, int size) :
sc_module(name) ,
fifo_inst("Fifo1", size) ,
prod_inst("Producer1") ,
cons_inst("Consumer1")
{
prod_inst.out(fifo_inst);
cons_inst.in(fifo_inst);
}
};
int sc_main (int argc , char *argv[])
{
int size = 10;
if (argc > 1)
size = atoi(argv[1]);
if (size < 1)
size = 1;
if (size > 100000)
size = 100000;
top top1("Top1", size);
sc_start();
return 0;
}
|
/*
* readwrite_if.hpp
*
* Created on: Jun 14, 2014
* Author: Pimenta
*/
#ifndef READWRITE_IF_HPP_
#define READWRITE_IF_HPP_
// lib
#include <systemc.h>
struct readwrite_if : public sc_module, public sc_interface {
protected:
uint32_t start_addr;
public:
readwrite_if(uint32_t start_addr);
uint32_t start_address();
virtual uint32_t size() = 0;
virtual void read(uint32_t src, uint32_t bytes, void* dst) = 0;
virtual void write(uint32_t dst, uint32_t bytes, void* src) = 0;
};
#endif /* READWRITE_IF_HPP_ */
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include <systemc.h>
#include "hwcore/cnn/cnn.h"
#include "hwcore/pipes/pipes.h"
#include "hwcore/hf/helperlib.h"
using namespace hwcore;
SC_MODULE(cpu_sim)
{
sc_fifo_out<pipes::sc_data_stream_t<16*32> > dma_out;
sc_fifo_in<pipes::sc_data_stream_t<16*32> > dma_in;
//sc_out<uint32_t>
};
SC_MODULE(tb_cnn_top)
{
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > cpu_sim_2_u1_dma;
cnn::top_cnn<> cnn_u1;
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > u1_2_cpu_sim_dma;
};
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include <systemc.h>
//#if __RTL_SIMULATION__
//#include "cnn_rtl_wrapper.h"
//#else
//#include "hwcore/cnn/cnn.h"
//#endif
#include "hwcore/cnn/cnn.h"
#include "hwcore/hf/helperlib.h"
#include "hwcore/pipes/pipes.h"
#if __RTL_SIMULATION__
//#include "DMA_performance_tester_rtl_wrapper.h"
//#else
//#include "DMA_generic_performance_tester.hpp"
#endif
SC_MODULE(mon_CNN) {
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
reset.write(false);
for (int i = 0; i < 20; i++)
wait();
int counter = 1;
int last_count = 1;
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
sc_fixed<DATA_W, DATA_P> Y_golden[16 * 16];
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16; b++) {
sc_fixed<DATA_W, DATA_P> tmp = 0;
for (int wi = 0; wi < 16; wi++) {
tmp += Win[wi + (b * 16)] * Xin[(a * 16) + wi];
}
Y_golden[(a * 16) + b] = tmp;
}
}
sc_fixed<DATA_W, DATA_P> Y[16 * 16];
hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> tmp;
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16 / OUTPUT_BW_N; b++) {
tmp = data_in.read();
sc_fixed<DATA_W, DATA_P> data_in[OUTPUT_BW_N];
tmp.getDataFixed<DATA_W, DATA_P, OUTPUT_BW_N>(data_in);
for (int i = 0; i < OUTPUT_BW_N; i++) {
Y[(a * 16) + (b * OUTPUT_BW_N) + i] = data_in[i];
HLS_DEBUG(1, 1, 0, "got knew value: ")
std::cout << " |--> " << data_in[i].to_float() << " index nr: " << counter << " tlast? "
<< tmp.tlast.to_int() << std::endl
<< std::flush;
counter++;
}
}
}
bool ok = true;
if (tmp.tlast.to_int() != 1) {
ok = false;
std::cout << "error - missing tlast!!!" << std::endl << std::flush;
}
for (int i = 0; i < 16 * 16; i++) {
std::cout << "[ " << i << " ] Y = " << Y[i].to_float() << std::endl
<< std::flush; // " == Y_golden = " << Y_golden[i].to_float() << std::endl << std::flush;
/* if(Y[i]!=Y_golden[i])
{
std::cout << "error not equal!!!" << std::endl << std::flush;
ok = false;
}*/
}
HLS_DEBUG(1, 1, 0, "Simulation done");
if (!ok) {
HLS_DEBUG(1, 1, 0, "Simulation done - with errors!!!");
}
sc_stop();
}
};
SC_MODULE(wave_CNN) {
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl_depth;
sc_out<sc_uint<16 + 1> > ctrl_stride;
sc_out<sc_uint<16 + 1> > ctrl_replay;
sc_out<sc_uint<1 + 1> > ctrl_channel;
sc_out<sc_uint<16 + 1> > ctrl_row_N;
sc_in<sc_uint<1> > ready;
template <class interface, typename T> void do_cmd(interface & itf, T value) {
while (ready.read() == 0) {
wait();
}
itf.write((value << 1) | 0b01);
while (ready.read() == 1) {
wait();
}
while (ready.read() == 0) {
wait();
}
itf.write(0);
wait();
}
SC_CTOR_DEFAULT(wave_CNN) {
SC_CTHREAD(wave_thread, clk.pos());
SC_CTHREAD(sending_ctrls, clk.pos());
}
void sending_ctrls() {
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 20; i++)
wait();
ctrl_channel.write(0);
ctrl_row_N.write(0);
weight_ctrl.write(0);
// data_ctrl.write(0);
do_cmd(ctrl_channel, 0);
do_cmd(ctrl_row_N, 16 / INPUT_BW_N);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
do_cmd(ctrl_depth, 1);
do_cmd(ctrl_replay, 1);
do_cmd(ctrl_stride, 0);
do_cmd(ctrl_row_size_pkg, 1024);
do_cmd(ctrl_window_size, 1);
for (int a = 0; a < 16; a++) {
do_cmd(ctrl_channel, 1);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
// do_cmd(data_ctrl,hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
}
while (true) {
wait();
}
}
void wave_thread() {
// sending dummy weights.
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 15; i++)
wait();
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
HLS_DEBUG(1, 1, 0, "sending data -- weights!----------------------");
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int a = 0; a < (16 * 16) / INPUT_BW_N; a++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Win[a * INPUT_BW_N]);
tmp.setKeep();
if (a == ((16 * 16) / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
// sending input data
HLS_DEBUG(1, 1, 0, "sending data -- Input!----------------------");
for (int a = 0; a < 16; a++) {
for (int i = 0; i < 16 / INPUT_BW_N; i++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Xin[(i * INPUT_BW_N) + (a * 16)]);
tmp.setKeep();
if (a == (16) - 1 && i == (16 / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending Input data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending Input data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
}
/*HLS_DEBUG(1,1,0,"sending data -- Firing!----------------------");
data_ctrl.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);*/
while (true) {
wait();
}
}
};
SC_MODULE(tb_CNN) {
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_signal<sc_uint<16 + 1> > ctrl_window_size;
sc_signal<sc_uint<16 + 1> > ctrl_depth;
sc_signal<sc_uint<16 + 1> > ctrl_stride;
sc_signal<sc_uint<16 + 1> > ctrl_replay;
sc_signal<sc_uint<1 + 1> > ctrl_channel;
sc_signal<sc_uint<16 + 1> > ctrl_row_N;
sc_signal<sc_uint<1> > ready;
// sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
::cnn cnn_u1;
// hwcore::cnn::top_cnn<16,8,1,1,16,16> cnn_u1;
sc_fifo<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > u1_2_mon;
mon_CNN mon;
sc_trace_file *tracePtr;
SC_CTOR_DEFAULT(tb_CNN) : SC_INST(wave), SC_INST(cnn_u1), SC_INST(mon), clk("clk", sc_time(10, SC_NS)) {
SC_MODULE_LINK(wave);
SC_MODULE_LINK(mon);
SC_MODULE_LINK(cnn_u1);
wave.ctrl_row_size_pkg(ctrl_row_size_pkg);
wave.ctrl_window_size(ctrl_window_size);
wave.ctrl_depth(ctrl_depth);
wave.ctrl_stride(ctrl_stride);
wave.ctrl_replay(ctrl_replay);
wave.ready(ready);
wave.data_out(wave_2_u1);
// wave.data_ctrl(data_ctrl);
wave.weight_ctrl(weight_ctrl);
wave.ctrl_row_N(ctrl_row_N);
wave.ctrl_channel(ctrl_channel);
cnn_u1.ready(ready);
cnn_u1.ctrl_row_size_pkg(ctrl_row_size_pkg);
cnn_u1.ctrl_window_size(ctrl_window_size);
cnn_u1.ctrl_depth(ctrl_depth);
cnn_u1.ctrl_stride(ctrl_stride);
cnn_u1.ctrl_replay(ctrl_replay);
cnn_u1.ctrl_row_N(ctrl_row_N);
cnn_u1.weight_ctrls(weight_ctrl);
// cnn_u1.data_ctrls(data_ctrl);
cnn_u1.ctrl_channel(ctrl_channel);
cnn_u1.data_sink(wave_2_u1);
cnn_u1.data_source(u1_2_mon);
mon.data_in(u1_2_mon);
tracePtr = sc_create_vcd_trace_file("tb_CNN");
trace(tracePtr);
}
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
SC_TRACE_ADD_MODULE(wave_2_u1);
SC_TRACE_ADD_MODULE(data_ctrl);
SC_TRACE_ADD_MODULE(weight_ctrl);
SC_TRACE_ADD_MODULE(ctrl_row_N);
SC_TRACE_ADD_MODULE(ctrl_channel);
SC_TRACE_ADD_MODULE(cnn_u1);
SC_TRACE_ADD_MODULE(u1_2_mon);
}
virtual ~tb_CNN() { sc_close_vcd_trace_file(tracePtr); }
};
/*{
#define SC_FIFO_IN_TRANSACTOR_ADD_SIGNALS(portName,width,if_type)\
sc_signal<if_type > dma_sink_dout;\
sc_signal< sc_logic > portName##_read;\
sc_signal< sc_logic > portName##_empty_n;\
sc_signal< sc_lv<width> > portName##_0_dout\
sc_signal< sc_logic > portName##_0_read;\
sc_signal< sc_lv<1> > portName##_1_dout;\
sc_signal< sc_logic > portName##_1_read;\
sc_signal< sc_lv<width/8> > portName##_2_dout;
#define SC_FIFO_IN_TRANSACTOR_ADD(inst,portName,id)\
inst.portName##_##id##_empty_n(portName##_empty_n);\
inst.portName##_##id##_read(portName##_read);\
inst.portName##_##id##_dout(portName##_dout_0);
#define SC_FIFO_IN_TRANSACTOR_CREATE(inst,portName, width, if_type, fifo) \
SC_FIFO_in_transactor<0, if_type >* portName##_inFifo_tr = new SC_FIFO_in_transactor<0, if_type
>(#portName"_inFifo_tr", AESL_ResetType::active_high_sync);\
portName##_inFifo_tr->rst(reset);\
portName##_inFifo_tr->FifoIn(fifo);\
portName##_inFifo_tr->clock(clk);\
portName##_inFifo_tr->if_empty_n(portName##_empty_n);\
portName##_inFifo_tr->if_read(portName##_read);\
portName##_inFifo_tr->if_dout(portName##_dout);\
SC_FIFO_IN_TRANSACTOR_ADD(cnn_u1,data_sink,0);\
SC_FIFO_IN_TRANSACTOR_ADD(cnn_u1,data_sink,1);\
SC_FIFO_IN_TRANSACTOR_ADD(cnn_u1,data_sink,2);\
portName##_dout_0.write((sc_lv<width>)(portName##_dout.read().data));\
portName##_dout_1.write((sc_lv<1>)(portName##_dout.read().tlast));\
portName##_dout_2.write((sc_lv<width/8>)(portName##_dout.read().tkeep));
}*/
|
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*! \file Interconnect.hpp
\brief Primary IPA header file
*/
#ifndef __INTERCONNECT_H__
#define __INTERCONNECT_H__
#include <systemc.h>
#include <nvhls_connections.h>
#include <nvhls_message.h>
#ifndef __SYNTHESIS__
#include <boost/format.hpp>
#include <boost/algorithm/string/replace.hpp>
#include <boost/functional/hash.hpp>
#include <typeinfo>
#endif
#include <boost/preprocessor/facilities/overload.hpp>
// Channel type class.
#include "InterconnectChannels.hpp"
// Include more global type settings.
// Needed before defining CRTP mix-in's
#include "InterconnectTypeConfig.hpp"
// Annotate and others depend on this
#include "InterconnectPre.hpp"
// Include our own annotation class
#include "InterconnectAnnotate.hpp"
// CRTP Mix-in
#include "InterconnectHandlerFixed.hpp"
#include "InterconnectHandlerFlit.hpp"
/*! \def ic_header(s)
\brief Required include macro header.
\param s Should always be set to "INTERCONNECT_GEN"
Only use at the top of the *** file:
\code
#include ic_header(INTERCONNECT_GEN)
\endcode
*/
#define ic_header(s) __ic_str(s)
#define __ic_str(s) #s
////////////////////////////////////////////////////////////////////////////////////////////////////////
// Interconnect macros
////////////////////////////////////////////////////////////////////////////////////////////////////////
//// Defer resolution, to be used with __COUNTER__ so we get unique names.
#define __IC_MACRO_DEFERED2(x) x
#define __IC_MACRO_DEFERED(x) __IC_MACRO_DEFERED2(x)
//// Configuration-related macros
/*!
\def IC_BEGIN_INTERCONNECTS
\brief Close the interconnect object declarations.
*/
#define IC_BEGIN_INTERCONNECTS struct interconnects {
/*!
\def IC_ADD_INTERCONNECT(x)
\brief Declare an interconnect with name \a x.
\param x identifier for new interconnect
*/
#define IC_ADD_INTERCONNECT(x) \
struct x { \
enum { ic_id = __IC_MACRO_DEFERED(__COUNTER__) }; \
};
/*!
\def IC_END_INTERCONNECTS
\brief Close the interconnect object declarations.
*/
#define IC_END_INTERCONNECTS \
} \
;
// +1 below so that it can never be 0
/*!
\def IC_BEGIN_DEST_MAPS
\brief Declare custom destination index maps
\par For now, custom maps are unsupported, but these macros are still required
to create the global map:
\code
IC_BEGIN_DEST_MAPS
IC_END_DEST_MAPS
\endcode
*/
#define IC_BEGIN_DEST_MAPS \
struct maps { \
struct global { \
enum { map_id = 0 }; \
};
#define IC_ADD_DEST_MAP(x) \
struct x { \
enum { map_id = (__IC_MACRO_DEFERED(__COUNTER__) + 1) }; \
};
/*!
\def IC_END_DEST_MAPS
\brief End declarations custom destination index maps
\par For now, custom maps are unsupported, but these macros are still required
to create the global map:
\code
IC_BEGIN_DEST_MAPS
IC_END_DEST_MAPS
\endcode
*/
#define IC_END_DEST_MAPS \
} \
;
/*!
\def IC_BEGIN_PARTITION_TYPES
\brief Begin list of declared partitions for IPA.
*/
#define IC_BEGIN_PARTITION_TYPES struct parts {
/*!
\def IC_BEGIN_PARTITION(x)
\brief Declare a partition with name \a x.
\param x identifier for new partition
*/
#define IC_BEGIN_PARTITION(x) \
struct x { \
enum { part_id = __COUNTER__ }; \
static constexpr const char *name = #x; \
struct ports {
//#define IC_ADD_PORT(x) struct x { enum { port_id =
//__IC_MACRO_DEFERED(__COUNTER__) }; };
/*!
\def IC_END_PARTITION
\brief Close the interconnect partition declarations.
*/
#define IC_END_PARTITION \
} \
; \
} \
;
/*!
\def IC_END_PARTITION_TYPES
\brief End list of declared partitions for IPA.
*/
#define IC_END_PARTITION_TYPES \
} \
;
/*!
\def IC_BEGIN_MESSAGE_TYPES
\brief Begin list of declared message types for IPA.
*/
#define IC_BEGIN_MESSAGE_TYPES struct msgs {
#define IC_ADD_MESSAGE_TYPE_3(x, d, z) \
struct x { \
enum { \
msg_id = __IC_MACRO_DEFERED(__COUNTER__), \
map_id = maps::z::map_id \
}; \
typedef d data_t; \
static constexpr const char *name = #x; \
};
#define IC_ADD_MESSAGE_TYPE_2(msg_type, msg_data) \
IC_ADD_MESSAGE_TYPE_3(msg_type, msg_data, global)
/*!
\def IC_ADD_MESSAGE_TYPE(...)
\brief Declare a new message type.
\param x User-specified identifier for message type
\param d Payload (class or primitive) for message type
\param map_id Optional parameter for custom destination map (currently
unsupported)
*/
#define IC_ADD_MESSAGE_TYPE(...) \
BOOST_PP_OVERLOAD(IC_ADD_MESSAGE_TYPE_, __VA_ARGS__)(__VA_ARGS__)
#define IC_ADD_MESSAGE_TYPE_FLIT(x, d, z) \
struct x { \
enum { \
msg_id = __IC_MACRO_DEFERED(__COUNTER__), \
map_id = maps::z::map_id \
}; \
typedef d router_t; \
static constexpr const char *name = #x; \
};
/*!
\def IC_END_MESSAGE_TYPES
\brief End list of declared message types for IPA.
*/
#define IC_END_MESSAGE_TYPES \
} \
;
// Dest Map
// Currently not supported
#define IC_DEST_MAP(x) interconnect_config::maps::x::map_id
#define IC_PORT_MAP_SET_IDX(x, y, z) \
ic_interface.set_map_port_idx(IC_DEST_MAP(x), y, z)
///////////////////////////////////////////////////////////////////////////////
//// Top-level macros
///////////////////////////////////////////////////////////////////////////////
/*!
\def IC_HAS_INTERCONNECT(x)
\brief Used within a top-level sc_module class declaration to indicate it
contains interconnect \a x.
\param x User-specified identifier for interconnect
*/
#define IC_HAS_INTERCONNECT(x) \
typedef interconnect::Interconnect< \
interconnect_config::interconnects::x::ic_id> interconnect_t; \
interconnect_t ic
/*!
\def IC_PART_BIND(inst, part_id)
\brief Bind partition instance \a inst and designate it as partition id \a
part_id for interconnect object \at ic
\par Used within the constructor of the top-level sc_module containing the
interconnect as specified with IC_HAS_INTERCONNECT.
\param inst partition instance
\param part_id user-specified partition ID used as the destination ID by
messsage sources to address this instance partition
*/
#define IC_PART_BIND(inst, part_id) \
interconnect::do_interconnect_to_interface_bind<__IC_MACRO_DEFERED( \
__COUNTER__)>(ic, (inst).ic_interface, inst, part_id)
/*!
\def IC_AT_PART_BIND(ic, inst, part_id)
\brief Bind partition instance \a inst and designate it as partition id \a
part_id for interconnect object \at ic
\par Under normal circumstances, IC_PART_BIND should be used instead, and
called directly within the constructor of the top-level sc_module containing
the interconnect.
However, this macro can be useful if the interconnect object sits elsewhere in
the hierarchy, but may not be as well supported for interconect generation.
\param ic interconnect object
\param inst partition instance
\param part_id user-specified partition ID used as the destination ID by
messsage sources to address this instance partition
*/
#define IC_AT_PART_BIND(ic, inst, part_id) \
interconnect::do_interconnect_to_interface_bind<__IC_MACRO_DEFERED( \
__COUNTER__)>(ic, (inst).ic_interface, inst, part_id)
///////////////////////////////////////////////////////////////////////////////
//// Partition-level macros
///////////////////////////////////////////////////////////////////////////////
// Interface declaration
/*!
\def IC_HAS_INTERFACE(x)
\brief Used within a unit-level sc_module class declaration to indicate it
contains an interface to bind to an interconnect.
\param x User-specified identifier for partition
*/
#define IC_HAS_INTERFACE(x) \
typedef interconnect_config::parts::x part_info; \
typedef interconnect::InterconnectInterface<part_info> ic_interface_t; \
ic_interface_t ic_interface
// IC_MESSAGE ports
#define IC_PORT_BIND_1(port) \
ic_interface.Bind<__IC_MACRO_DEFERED(__COUNTER__)>(port, 0)
#define IC_PORT_BIND_2(port, port_id) \
ic_interface.Bind<__IC_MACRO_DEFERED(__COUNTER__)>(port, port_id)
/*!
\def IC_PORT_BIND(port,port_id)
\brief Bind a port of a lower level module within hierarchy
\par For binding a port of the current-level of hierarchy, use IC_PIN_BIND
instead.
\param port Port instance to bind
\param port_id Optional user-specified port_id for sharing multiple message
types on the unit; currently unsupported
*/
#define IC_PORT_BIND(...) \
BOOST_PP_OVERLOAD(IC_PORT_BIND_, __VA_ARGS__)(__VA_ARGS__)
#define IC_PIN_BIND_1(port) IC_PORT_BIND(interconnect::new_port_pin2(port)->pin)
#define IC_PIN_BIND_2(port, port_id) \
IC_PORT_BIND(interconnect::new_port_pin2(port)->pin, port_id)
/*!
\def IC_PIN_BIND(port,port_id)
\brief Bind a port of current level module within hierarchy
\par For binding a port of the lower level of hierarchy, use IC_PORT_BIND
instead.
\param port Port instance to bind
\param port_id Optional user-specified port_id for sharing multiple message
types on the unit; currently unsupported
*/
#define IC_PIN_BIND(...) \
BOOST_PP_OVERLOAD(IC_PIN_BIND_, __VA_ARGS__)(__VA_ARGS__)
/// Flit ports
#define IC_AT_PORT_BIND_FLIT_3(ic, msg_type, port) \
ic.BindFlit<interconnect_config::msgs::msg_type>(port);
#define IC_AT_PORT_BIND_FLIT_4(ic, msg_type, port, custom_id) \
ic.BindFlit<interconnect_config::msgs::msg_type>(port, custom_id);
#define IC_AT_PORT_BIND_FLIT(...) \
BOOST_PP_OVERLOAD(IC_AT_PORT_BIND_FLIT_, __VA_ARGS__)(__VA_ARGS__)
#define IC_AT_PIN_BIND_FLIT_3(ic, msg_type, port) \
IC_AT_PORT_BIND_FLIT(ic, msg_type, interconnect::new_port_pin2(port)->pin)
#define IC_AT_PIN_BIND_FLIT_4(ic, msg_type, port, custom_id) \
IC_AT_PORT_BIND_FLIT(ic, msg_type, interconnect::new_port_pin2(port)->pin, \
custom_id)
#define IC_AT_PIN_BIND_FLIT(...) \
BOOST_PP_OVERLOAD(IC_AT_PIN_BIND_FLIT_, __VA_ARGS__)(__VA_ARGS__)
#define IC_PORT_BIND_FLIT(...) IC_AT_PORT_BIND_FLIT(ic, __VA_ARGS__)
#define IC_PIN_BIND_FLIT(...) IC_AT_PIN_BIND_FLIT(ic, __VA_ARGS__)
// To add additional port id's to a destination port
// Note: we don't use this in the bind3 version, since bind3 can accomodate in
// and out ports, and no way ot differentiate
#define IC_AT_PORT_ID_FLIT(ic, msg_type, port, custom_id) \
ic.config_dest_map_idx_flit(interconnect_config::msgs::msg_type::map_id, \
custom_id, port)
#define IC_PORT_ID_FLIT(...) IC_AT_PORT_ID_FLIT(ic, __VA_ARGS__)
///////////////////////////////////////////////////////////////////////////////
//// Message-level macros
///////////////////////////////////////////////////////////////////////////////
// IC_PORT_ID is currently unused
#define IC_PORT_ID(y) part_info::ports::y::port_id
/*!
\def IC_MESSAGE(x)
\brief Create new message of message type \a x
\param x message type identifier
*/
#define IC_MESSAGE(x) typename interconnect::Msg<interconnect_config::msgs::x>
// If the values can change at runtime e.g. from jtag.
#define IC_TO_DYNAMIC_1(part_id) interconnect::Destination(part_id, 0)
#define IC_TO_DYNAMIC_2(part_id, port_id) \
interconnect::Destination(part_id, port_id)
#define IC_TO_DYNAMIC(...) \
BOOST_PP_OVERLOAD(IC_TO_DYNAMIC_, __VA_ARGS__)(__VA_ARGS__)
// If the values are fixed/constant
#define IC_TO_CONST_1(part_id) interconnect::Destination(part_id, 0)
#define IC_TO_CONST_2(part_id, port_id) \
interconnect::Destination(part_id, port_id)
#define IC_TO_CONST(...) \
BOOST_PP_OVERLOAD(IC_TO_CONST_, __VA_ARGS__)(__VA_ARGS__)
/*!
\def IC_TO(part_id,port_id)
\brief Send a message to partition instance with id \a part_id
\param part_id destination user-specified partition id
\param port_id optional user-specified port_id; currently unsupported
*/
#define IC_TO(...) IC_TO_CONST(__VA_ARGS__)
///////////////////////////////////////////////////////////////////////////////
//// Legacy/testbench macros
///////////////////////////////////////////////////////////////////////////////
//// Legacy port bind for when we can't or don't want to use IC_INTERFACE
#define IC_AT_LEGACY_PORT_BIND_5(ic, msg_type, port, part_id, port_id) \
ic.Bind(port); \
ic.add_to_dest_directory(port, part_id, port_id)
#define IC_AT_LEGACY_PORT_BIND_4(ic, msg_type, port, part_id) \
ic.Bind(port); \
ic.add_to_dest_directory(port, part_id)
#define IC_AT_LEGACY_PORT_BIND_3(ic, msg_type, port) ic.Bind(port);
#define IC_AT_LEGACY_PORT_BIND(...) \
BOOST_PP_OVERLOAD(IC_AT_LEGACY_PORT_BIND_, __VA_ARGS__)(__VA_ARGS__)
#define IC_AT_LEGACY_DISTRIBUTED_PORT_BIND_5(ic, msg_type, port, part_id, \
port_id) \
ic.Bind(port); \
ic.add_to_dest_directory(port, part_id, port_id, true)
#define IC_AT_LEGACY_DISTRIBUTED_PORT_BIND_4(ic, msg_type, port, part_id) \
ic.Bind(port); \
ic.add_to_dest_directory(port, part_id, 0, true)
#define IC_AT_LEGACY_DISTRIBUTED_PORT_BIND_3(ic, msg_type, port) ic.Bind(port);
#define IC_AT_LEGACY_DISTRIBUTED_PORT_BIND(...) \
BOOST_PP_OVERLOAD(IC_AT_LEGACY_DISTRIBUTED_PORT_BIND_, __VA_ARGS__)(__VA_ARGS__)
#define IC_LEGACY_PORT_BIND(...) IC_AT_LEGACY_PORT_BIND(ic, __VA_ARGS__)
#define IC_LEGACY_DISTRIBUTED_PORT_BIND(...) \
IC_AT_LEGACY_DISTRIBUTED_PORT_BIND(ic, __VA_ARGS__)
////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __SYNTHESIS__
namespace interconnect {
/*!
\brief Message instance class
Do not instantiate directly, instead use the `#IC_MESSAGE(x)` macro
\tparam MSG_TYPE identifier for message type
*/
template <typename MSG_TYPE>
class Msg : public nvhls_message {
static const MSG_ID_t MSG_ID = MSG_TYPE::msg_id;
typedef typename MSG_TYPE::data_t data_t;
public:
/*!
\brief Payload data
*/
data_t msg;
/*!
\brief Destination mask for this message
*/
sc_lv<interconnect::MaxDestCount> dest_bits;
public:
//// Constructor-Destructor
/*!
\brief Default constructor
*/
Msg<MSG_TYPE>() { dest_bits = 0; }
/*!
\brief Constructor to initialize from payload data
*/
Msg<MSG_TYPE>(const data_t &m) {
dest_bits = 0;
set_msg(m);
}
//// Operators
/*!
\brief Set payload of message
*/
Msg<MSG_TYPE> &operator=(const data_t &m) {
set_msg(m);
return *this;
}
/*!
\brief Set message destination, destination id should be used through
#IC_TO(part_id,port_id) macro
*/
Msg<MSG_TYPE> &operator<<(const Destination &dest) {
auto tuple_idx =
std::make_tuple(dest.part_id, MSG_TYPE::msg_id, dest.port_id);
if (interconnect::get_ICManager().dest_directory.find(tuple_idx) ==
interconnect::get_ICManager().dest_directory.end()) {
cout << dec << "Couldn't find destination part_id=" << dest.part_id
<< ", msg_id=" << MSG_TYPE::msg_id << ", port_id=" << dest.port_id
<< endl;
NVHLS_ASSERT(0);
}
add_route(
interconnect::get_ICManager().dest_directory[tuple_idx].get_next(), 0);
return *this;
}
//// Setter-Getter
/*!
\brief Set message payload
*/
void set_msg(const data_t &m) { msg = m; }
/*!
\brief Get message payload
*/
data_t get_msg() { return msg; }
/*!
\brief Get message payload through cast
*/
operator data_t() { return get_msg(); }
/*!
\brief Set destination for message
*/
template <typename interconnect_t, typename route_t>
void set_route(interconnect_t &ic, route_t *route) {
dest_bits = 0;
for (typename route_t::iterator it = route->begin(); it != route->end();
++it) {
add_route(ic.find_dest_idx(*it));
}
}
// Conversion to generic type
template <unsigned int MaxDataWidth, unsigned int MaxDestCount>
operator InterconnectMessageSCLV<MaxDataWidth, MaxDestCount>() {
assert(MaxDestCount == interconnect::MaxDestCount);
assert(Wrapped<data_t>::width <= MaxDataWidth);
InterconnectMessageSCLV<MaxDataWidth, MaxDestCount> new_im;
new_im.set_msg(msg);
new_im.dest_bits = dest_bits;
return new_im;
}
template <unsigned int MaxDataWidth, unsigned int MaxDestCount>
explicit Msg<MSG_TYPE>(
const InterconnectMessageSCLV<MaxDataWidth, MaxDestCount> &im) {
assert(MaxDestCount == interconnect::MaxDestCount);
assert(Wrapped<data_t>::width <= MaxDataWidth);
im.get_msg(msg);
dest_bits = im.dest_bits;
}
template <unsigned int MaxDataWidth, unsigned int MaxDestCount>
Msg<MSG_TYPE> &operator=(
const InterconnectMessageSCLV<MaxDataWidth, MaxDestCount> &im) {
assert(MaxDestCount == interconnect::MaxDestCount);
assert(Wrapped<data_t>::width <= MaxDataWidth);
im.get_msg(msg);
dest_bits = im.dest_bits;
return *this;
}
//// Route Operators
void add_route(const unsigned int &dest_idx,
const unsigned int &dest_map_idx = 0) {
unsigned int real_dest_idx;
real_dest_idx = interconnect::get_real_dest_idx<void>(
*interconnect::get_ICManager().registered_ic[0], dest_idx,
dest_map_idx);
dest_bits[real_dest_idx] = 1;
}
void clear_route() { dest_bits = 0; }
//// Marshall support
enum { width = Wrapped<data_t>::width + interconnect::MaxDestCount };
template <unsigned int Size>
void Marshall(Marshaller<Size> &m) {
m &msg;
m &dest_bits;
}
};
template <typename IM_t>
struct GenericDestHandlerIface {
public:
typename Connections::InBlocking<IM_t> *im_ptr;
};
template <typename IM_t>
struct GenericSrcHandlerIface {
public:
typename Connections::OutBlocking<IM_t> *im_ptr;
};
template <typename IM_t, typename MSG_TYPE>
class ICMFromSpecialized : public sc_module,
public Connections::Blocking_abs,
public GenericSrcHandlerIface<IM_t> {
SC_HAS_PROCESS(ICMFromSpecialized);
static const interconnect::MSG_ID_t MSG_ID = MSG_TYPE::msg_id;
public:
Connections::OutBlocking<IM_t> im;
Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p;
sc_signal<sc_lv<Wrapped<interconnect::Msg<MSG_TYPE> >::width> > int_msg;
sc_signal<bool> int_rdy;
sc_signal<bool> int_val;
explicit ICMFromSpecialized(
Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p_)
: sc_module(sc_module_name(s
|
c_gen_unique_name("im_from_specific")))
// ,ic(ic_)
,
im(sc_gen_unique_name("im")),
p(p_),
int_msg("int_msg"),
int_rdy("int_rdy"),
int_val("int_val") {
// Pass up to handler interface
this->im_ptr = &im;
p._DATNAME_(int_msg);
p._RDYNAME_(int_rdy);
p._VLDNAME_(int_val);
#ifdef CONNECTIONS_SIM_ONLY
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << p._DATNAME_ << p._VLDNAME_ << im._RDYNAME_;
im.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = int_val.read();
// Set val and msg respectively
im._VLDNAME_.write(is_val);
int_rdy.write(im._RDYNAME_.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
// Convert msg
Marshaller<Wrapped<interconnect::Msg<MSG_TYPE> >::width> marshaller(
int_msg.read());
Wrapped<interconnect::Msg<MSG_TYPE> > result;
result.Marshall(marshaller);
// Create the InterconnectMessage
IM_t im_msg;
interconnect::Msg<MSG_TYPE> m = result.val;
im_msg = m;
// Convert back to Marshall'd form
Marshaller<Wrapped<IM_t>::width> im_marshaller;
Wrapped<IM_t> im_wm(im_msg);
im_wm.Marshall(im_marshaller);
im._DATNAME_.write(im_marshaller.GetResult());
}
}
}; // class ICMNewToOld
template <typename IM_t, typename MSG_TYPE>
class ICMToSpecialized : public sc_module,
public Connections::Blocking_abs,
public GenericDestHandlerIface<IM_t> {
SC_HAS_PROCESS(ICMToSpecialized);
static const interconnect::MSG_ID_t MSG_ID = MSG_TYPE::msg_id;
public:
Connections::InBlocking<IM_t> im;
Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p;
sc_signal<sc_lv<Wrapped<interconnect::Msg<MSG_TYPE> >::width> > int_msg;
sc_signal<bool> int_rdy;
sc_signal<bool> int_val;
explicit ICMToSpecialized(
Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p_)
: sc_module(sc_module_name(sc_gen_unique_name("icm_to_specialized"))),
// ic(ic_),
im(sc_gen_unique_name("im")),
p(p_),
int_msg("int_msg"),
int_rdy("int_rdy"),
int_val("int_val") {
// Pass up to handler interface
this->im_ptr = &im;
p._DATNAME_(int_msg);
p._RDYNAME_(int_rdy);
p._VLDNAME_(int_val);
#ifdef CONNECTIONS_SIM_ONLY
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << im._DATNAME_ << im._VLDNAME_ << p._RDYNAME_;
im.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = im._VLDNAME_.read();
// Set val and msg respectively
int_val.write(is_val);
im._RDYNAME_.write(int_rdy.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
// Convert msg from bits
Marshaller<Wrapped<IM_t>::width> im_marshaller(im._DATNAME_.read());
Wrapped<IM_t> im_result;
im_result.Marshall(im_marshaller);
IM_t im_msg = im_result.val;
// Convert msg to bits and write
Marshaller<Wrapped<interconnect::Msg<MSG_TYPE> >::width> marshaller;
interconnect::Msg<MSG_TYPE> m(im_msg);
Wrapped<interconnect::Msg<MSG_TYPE> > wm(m);
wm.Marshall(marshaller);
int_msg.write(marshaller.GetResult());
}
}
}; // classFixedDestHandler
};
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////////
namespace interconnect {
#ifdef CONNECTIONS_SIM_ONLY
// Pointer based message passing
template <typename IM>
class InterconnectBase
: public sc_module,
public InterconnectHandlerFixed<InterconnectBase<IM>, IM>,
public InterconnectHandlerFlit<InterconnectBase<IM>, IM> {
SC_HAS_PROCESS(InterconnectBase);
protected:
// Declarations
class Route;
public:
typedef IM IM_t;
typedef Route route_t;
// These are now pushed down into a separate class, so that Handler classse
// can access these without templatization. Is there a better way to do this?
typedef typename InterconnectTypeConfig<IM>::IM_src_t IM_src_t;
typedef typename InterconnectTypeConfig<IM>::IM_dest_t IM_dest_t;
typedef typename InterconnectTypeConfig<IM>::IM_chan_t IM_chan_t;
typedef typename InterconnectTypeConfig<IM>::IM_chanlink_t IM_chanlink_t;
typedef typename InterconnectTypeConfig<IM>::srcs_t srcs_t;
typedef typename InterconnectTypeConfig<IM>::dests_t dests_t;
typedef
typename InterconnectTypeConfig<IM>::channels_begin_t channels_begin_t;
typedef typename InterconnectTypeConfig<IM>::channels_middle_inner_t
channels_middle_inner_t;
typedef
typename InterconnectTypeConfig<IM>::channels_middle_t channels_middle_t;
typedef typename InterconnectTypeConfig<IM>::channels_end_t channels_end_t;
typedef typename InterconnectTypeConfig<IM>::srcs_typeid_t srcs_typeid_t;
typedef typename InterconnectTypeConfig<IM>::dests_typeid_t dests_typeid_t;
typedef typename InterconnectTypeConfig<IM>::srcs_user_typeid_t
srcs_user_typeid_t;
typedef typename InterconnectTypeConfig<IM>::dests_user_typeid_t
dests_user_typeid_t;
typedef typename InterconnectTypeConfig<IM>::srcs_width_t srcs_width_t;
typedef typename InterconnectTypeConfig<IM>::dests_width_t dests_width_t;
typedef
typename InterconnectTypeConfig<IM>::channels_valid_pairs_reverse_inner_t
channels_valid_pairs_reverse_inner_t;
typedef typename InterconnectTypeConfig<IM>::channels_valid_pairs_reverse_t
channels_valid_pairs_reverse_t;
typedef typename InterconnectTypeConfig<IM>::idx_t idx_t;
typedef typename InterconnectTypeConfig<IM>::dest_map_idx_t dest_map_idx_t;
typedef typename InterconnectTypeConfig<IM>::dest_maps_t dest_maps_t;
typedef typename InterconnectTypeConfig<IM>::dest_maps_idx_vec_t
dest_maps_idx_vec_t;
typedef typename InterconnectTypeConfig<IM>::cycles_count_t cycles_count_t;
typedef typename InterconnectTypeConfig<IM>::cycle_count_channel_t
cycle_count_channel_t;
const unsigned int ic_id;
public:
std::map<IM_src_t *, Connections::Blocking_abs *> srcs_block_abs;
std::map<IM_dest_t *, Connections::Blocking_abs *> dests_block_abs;
protected:
// Vectors of ports
srcs_t srcs;
dests_t dests;
srcs_t disabled_srcs;
dests_t disabled_dests;
std::vector<std::tuple<Connections::Blocking_abs *,
Connections::Blocking_abs *> > disabled_pairs;
std::map<IM_src_t *, std::string> srcs_names;
std::map<IM_dest_t *, std::string> dests_names;
// Maps of channels
channels_begin_t channels_begin;
public:
channels_middle_t channels_middle;
protected:
channels_end_t channels_end;
channels_valid_pairs_reverse_t channels_valid_pairs_reverse;
public:
// Tracking to find valid combinations of channels
srcs_typeid_t srcs_typeid;
dests_typeid_t dests_typeid;
srcs_user_typeid_t srcs_user_typeid;
dests_user_typeid_t dests_user_typeid;
std::map<unsigned int, const char *> msg_names; // key = msg_id
std::map<unsigned int, const char *> part_names; // key = part_type_id
std::map<unsigned int, unsigned int>
part_to_part_type; // key = user_part_Id, value = part_type_id
std::map<unsigned int, const char *>
part_inst_names; // key = user_part_Id, value is part_name
std::map<unsigned int, std::map<unsigned int, std::set<unsigned int> > >
part_msgs_srcs; // key = part_type_id, set is msg ids
std::map<unsigned int, std::map<unsigned int, std::set<unsigned int> > >
part_msgs_dests; // key = part_type_id, set is msg ids
srcs_width_t srcs_width;
dests_width_t dests_width;
protected:
// Instrumentation
cycles_count_t cycle_count_total;
cycle_count_channel_t cycle_count_channel;
public:
// Ports
sc_in_clk clk;
sc_in<bool> rst;
////////////////////////////////////////////////////////////////////////////////////////////////
// Constructors
InterconnectBase(const unsigned int &ic_id_)
: sc_module(sc_module_name(sc_gen_unique_name("interconnect"))),
clk(sc_gen_unique_name("clk")),
rst(sc_gen_unique_name("rst")),
ic_id(ic_id_) {
SC_CTHREAD(run, clk.pos());
async_reset_signal_is(rst, false);
}
explicit InterconnectBase(const char *name, const unsigned int &ic_id_)
: sc_module(sc_module_name(name)),
clk(sc_gen_unique_name("clk")),
rst(sc_gen_unique_name("rst")),
ic_id(ic_id_) {
SC_CTHREAD(run, clk.pos());
async_reset_signal_is(rst, false);
}
////////////////////////////////////////////////////////////////////////////////////////////////
// Run loop
void run() {
cycle_count_total = 0;
wait();
while (1) {
cycle_count_total++;
wait();
}
}
////////////////////////////////////////////////////////////////////////////////////////////////
// Channel binding
template <typename T>
void Bind(IM_src_t &p) {
Bind(p, Wrapped<T>::width, typeid(T).name());
}
template <typename T>
void Bind(IM_dest_t &p) {
Bind(p, Wrapped<T>::width, typeid(T).name());
}
void Bind(IM_src_t &p, unsigned int type_width, const char *type_name) {
srcs.push_back(&p);
std::string port_name = p._VLDNAME_.name();
if (port_name.substr(port_name.length() - 4, 4) == "_" _VLDNAMESTR_) {
port_name.erase(port_name.length() - 4, 4);
}
set_src_name(&p, port_name);
boost::hash<const char *> typeid_hash;
srcs_typeid[&p] = typeid_hash(type_name);
srcs_width[&p] = type_width;
}
void Bind(IM_dest_t &p, unsigned int type_width, const char *type_name) {
dests.push_back(&p);
std::string port_name = p._VLDNAME_.name();
if (port_name.substr(port_name.length() - 4, 4) == "_" _VLDNAMESTR_) {
port_name.erase(port_name.length() - 4, 4);
}
set_dest_name(&p, port_name);
boost::hash<const char *> typeid_hash;
dests_typeid[&p] = typeid_hash(type_name);
dests_width[&p] = type_width;
}
template <typename T>
void Bind(IM_dest_t &p, unsigned int userid, const char *msg_name) {
Bind<T>(p);
dests_user_typeid[&p] = userid;
msg_names[userid] = msg_name;
}
template <typename T>
void Bind(IM_src_t &p, unsigned int userid, const char *msg_name) {
Bind<T>(p);
srcs_user_typeid[&p] = userid;
msg_names[userid] = msg_name;
}
void Bind(IM_dest_t &p, unsigned int userid, unsigned int type_width,
const char *type_name, const char *msg_name) {
Bind(p, type_width, type_name);
dests_user_typeid[&p] = userid;
msg_names[userid] = msg_name;
}
void Bind(IM_src_t &p, unsigned int userid, unsigned int type_width,
const char *type_name, const char *msg_name) {
Bind(p, type_width, type_name);
srcs_user_typeid[&p] = userid;
msg_names[userid] = msg_name;
}
////////////////////////////////////////////////////////////////////////////
// New IC_MESSAGE
struct GenericDestHandlerIface {
public:
typename InterconnectBase<IM>::IM_dest_t *im_ptr;
};
struct GenericSrcHandlerIface {
public:
typename InterconnectBase<IM>::IM_src_t *im_ptr;
};
std::map<Connections::Blocking_abs *, GenericDestHandlerIface *>
generic_iface_dests;
std::map<Connections::Blocking_abs *, GenericSrcHandlerIface *>
generic_iface_srcs;
template <typename MSG_TYPE>
class ICMFromSpecialized : public sc_module,
public Connections::Blocking_abs,
public GenericSrcHandlerIface {
SC_HAS_PROCESS(ICMFromSpecialized);
public:
typedef InterconnectBase<IM> interconnect_t;
interconnect_t ⁣
typename interconnect_t::IM_src_t im;
Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p;
sc_signal<sc_lv<Wrapped<interconnect::Msg<MSG_TYPE> >::width> > int_msg;
sc_signal<bool> int_rdy;
sc_signal<bool> int_val;
explicit ICMFromSpecialized(
interconnect_t &ic_,
Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p_)
: sc_module(sc_module_name(sc_gen_unique_name("im_from_specific"))),
ic(ic_),
im(sc_gen_unique_name("im")),
p(p_),
int_msg("int_msg"),
int_rdy("int_rdy"),
int_val("int_val") {
// Pass up to handler interface
this->im_ptr = &im;
p._DATNAME_(int_msg);
p._RDYNAME_(int_rdy);
p._VLDNAME_(int_val);
#ifdef CONNECTIONS_SIM_ONLY
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << p._DATNAME_ << p._VLDNAME_ << im._RDYNAME_;
im.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = int_val.read();
// Set val and msg respectively
im._VLDNAME_.write(is_val);
int_rdy.write(im._RDYNAME_.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
// Convert msg
Marshaller<Wrapped<interconnect::Msg<MSG_TYPE> >::width> marshaller(
int_msg.read());
Wrapped<interconnect::Msg<MSG_TYPE> > result;
result.Marshall(marshaller);
// Create the InterconnectMessage
typename interconnect_t::IM_t im_msg;
interconnect::Msg<MSG_TYPE> m = result.val;
im_msg = m;
// Convert back to Marshall'd form
Marshaller<Wrapped<typename interconnect_t::IM_t>::width> im_marshaller;
Wrapped<typename interconnect_t::IM_t> im_wm(im_msg);
im_wm.Marshall(im_marshaller);
im._DATNAME_.write(im_marshaller.GetResult());
}
}
}; // class ICMFromSpecialized
template <typename MSG_TYPE>
class ICMToSpecialized : public sc_module,
public Connections::Blocking_abs,
public GenericDestHandlerIface {
SC_HAS_PROCESS(ICMToSpecialized);
static const interconnect::MSG_ID_t MSG_ID = MSG_TYPE::msg_id;
public:
typedef InterconnectBase<IM> interconnect_t;
interconnect_t ⁣
typename interconnect_t::IM_dest_t im;
Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p;
sc_signal<sc_lv<Wrapped<interconnect::Msg<MSG_TYPE> >::width> > int_msg;
sc_signal<bool> int_rdy;
sc_signal<bool> int_val;
explicit ICMToSpecialized(
interconnect_t &ic_,
Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p_)
: sc_module(sc_module_name(sc_gen_unique_name("icm_to_specialized"))),
ic(ic_),
im(sc_gen_unique_name("im")),
p(p_),
int_msg("int_msg"),
int_rdy("int_rdy"),
int_val("int_val") {
// Pass up to handler interface
this->im_ptr = &im;
p._DATNAME_(int_msg);
p._RDYNAME_(int_rdy);
p._VLDNAME_(int_val);
#ifdef CONNECTIONS_SIM_ONLY
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << im._DATNAME_ << im._VLDNAME_ << p._RDYNAME_;
im.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = im._VLDNAME_.read();
// Set val and msg respectively
int_val.write(is_val);
im._RDYNAME_.write(int_rdy.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
// Convert msg from bits
Marshaller<Wrapped<typename interconnect_t::IM_t>::width> im_marshaller(
im._DATNAME_.read());
Wrapped<typename interconnect_t::IM_t> im_result;
im_result.Marshall(im_marshaller);
typename interconnect_t::IM_t im_msg = im_result.val;
// Convert msg to bits and write
Marshaller<Wrapped<interconnect::Msg<MSG_TYPE> >::width> marshaller;
interconnect::Msg<MSG_TYPE> m(im_msg);
Wrapped<interconnect::Msg<MSG_TYPE> > wm(m);
wm.Marshall(marshaller);
int_msg.write(marshaller.GetResult());
}
}
}; // ICMToSpecialized
template <typename MSG_TYPE>
void Bind(Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p) {
ICMFromSpecialized<MSG_TYPE> *is =
new ICMFromSpecialized<MSG_TYPE>(*this, p);
Bind<typename MSG_TYPE::data_t>(is->im, MSG_TYPE::msg_id, MSG_TYPE::name);
std::string port_name = p._VLDNAME_.name();
if (port_name.substr(port_name.length() - 4, 4) == "_" _VLDNAMESTR_) {
port_name.erase(port_name.length() - 4, 4);
}
set_src_name(&is->im, port_name);
generic_iface_srcs[&p] = is;
msg_names[MSG_TYPE::msg_id] = MSG_TYPE::name;
}
template <typename MSG_TYPE>
void Bind(Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p) {
ICMToSpecialized<MSG_TYPE> *ij = new ICMToSpecialized<MSG_TYPE>(*this, p);
Bind<typename MSG_TYPE::data_t>(ij->im, MSG_TYPE::msg_id, MSG_TYPE::name);
std::string port_name = p._VLDNAME_.name();
if (port_name.substr(port_name.length() - 4, 4) == "_" _VLDNAMESTR_) {
port_name.erase(port_name.length() - 4, 4);
}
set_dest_name(&ij->im, port_name);
generic_iface_dests[&p] = ij;
msg_names[MSG_TYPE::msg_id] = MSG_TYPE::name;
}
template <typename T, typename MSG_TYPE>
void Bind(Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p,
unsigned int userid) {
assert(userid == MSG_TYPE::msg_id);
Bind(p);
}
template <typename T, typename MSG_TYPE>
void Bind(Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p,
unsigned int userid) {
assert(userid == MSG_TYPE::msg_id);
Bind(p);
}
template <typename MSG_TYPE>
void config_dest_map_idx(
dest_map_idx_t dest_map_idx, idx_t dest_idx,
Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p) {
config_dest_map_idx(
dest_map_idx, dest_idx,
*(generic_iface_dests[(Connections::Blocking_abs *)&p]->im_ptr));
}
////////////////////////////////////////////////////////////////////////////
// Disable a source or dest port. Still binds and resets it,
// but otherwise disabled it for sending or receiving.
// Useful when there are additional ports that need to be bound
// but will be unused (edges of an array, testbench, etc).
void disable_port(IM_dest_t &p) { disabled_dests.push_back(&p); }
void disable_port(IM_src_t &p) { disabled_srcs.push_back(&p); }
void disable_pair_of_ports(Connections::Blocking_abs &p1,
Connections::Blocking_abs &p2) {
disabled_pairs.push_back(std::make_tuple(&p1, &p2));
}
template <typename MSG_TYPE>
void disable_port(Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p) {
disabled_dests.push_back(
generic_iface_dests[(Connections::Blocking_abs *)&p]->im_ptr);
}
template <typename MSG_TYPE>
void disable_port(Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p) {
disabled_srcs.push_back(
generic_iface_srcs[(Connections::Blocking_abs *)&p]->im_ptr);
}
////////////////////////////////////////////////////////////////////////////////////////////////
// Modifiers
idx_t find_src_idx(IM_src_t *p) {
unsigned long i = 0;
for (typename srcs_t::iterator it_src = srcs.begin(); it_src != srcs.end();
++it_src, ++i) {
if ((*it_src) == p) {
return i;
}
}
return -1;
}
idx_t find_dest_idx(IM_dest_t *p) {
unsigned long i = 0;
for (typename dests_t::iterator it_dest = dests.begin();
it_dest != dests.end(); ++it_dest, ++i) {
if ((*it_dest) == p) {
return i;
}
}
return -1;
}
IM_src_t *get_src_from_idx(idx_t src_idx) {
NVHLS_ASSERT_MSG(src_idx != -1, "Source index is not found");
NVHLS_ASSERT_MSG(src_idx < get_src_size(),
"Source index exc
|
eeds number of sources");
return srcs[src_idx];
}
idx_t get_real_dest_idx(idx_t dest_idx, dest_map_idx_t dest_map_idx = 0) {
idx_t real_dest_idx;
if (dest_map_idx == 0) {
real_dest_idx = dest_idx;
} else {
// Assert that dest_map_idx map exists
NVHLS_ASSERT_MSG(
std::find(dest_maps_idx_vec.begin(), dest_maps_idx_vec.end(),
dest_map_idx) != dest_maps_idx_vec.end(),
"Destination map not found!");
// Assert that the dest_idx exists in that map.
NVHLS_ASSERT_MSG(dest_maps[dest_map_idx].find(dest_idx) !=
dest_maps[dest_map_idx].end(),
"Interconnect coundn't find dest_idx in dest_map_idx.");
// Get the real idx
real_dest_idx = dest_maps[dest_map_idx][dest_idx];
}
return real_dest_idx;
}
IM_dest_t *get_dest_from_idx(idx_t dest_idx,
dest_map_idx_t dest_map_idx = 0) {
idx_t real_dest_idx;
real_dest_idx = get_real_dest_idx(dest_idx, dest_map_idx);
NVHLS_ASSERT_MSG(real_dest_idx != -1,
"Real dest index is -1, indicating not found!");
NVHLS_ASSERT_MSG(real_dest_idx < get_dest_size(),
"Real dest index exceeds number of dests in design!");
return dests[real_dest_idx];
}
void set_src_name(IM_src_t *p, std::string &s) { srcs_names[p] = s; }
void set_dest_name(IM_dest_t *p, std::string &s) { dests_names[p] = s; }
std::string get_src_name(IM_src_t *p) { return srcs_names[p]; }
std::string get_dest_name(IM_dest_t *p) { return dests_names[p]; }
unsigned int get_src_size() { return srcs.size(); }
unsigned int get_dest_size() { return dests.size(); }
////////////////////////////////////////////////////////////////////////////////////////////////
// Route creation
dest_maps_t dest_maps;
dest_maps_idx_vec_t dest_maps_idx_vec;
dest_map_idx_t create_dest_map() {
// Seed starting value
dest_map_idx_t dest_map_idx = 1;
// Find lowest integer not in dest_maps.
sort(dest_maps_idx_vec.begin(), dest_maps_idx_vec.end());
for (typename dest_maps_idx_vec_t::iterator it = dest_maps_idx_vec.begin();
it != dest_maps_idx_vec.end(); ++it) {
if ((*it) >= dest_map_idx) {
if ((*it) == dest_map_idx)
dest_map_idx++; // Found it
else
break; // current value will work
}
}
create_dest_map(dest_map_idx);
return dest_map_idx;
}
dest_map_idx_t create_dest_map(dest_map_idx_t dest_map_idx,
const bool &allow_existing = false) {
NVHLS_ASSERT(dest_map_idx != 0);
if (allow_existing &&
std::find(dest_maps_idx_vec.begin(), dest_maps_idx_vec.end(),
dest_map_idx) != dest_maps_idx_vec.end()) {
return dest_map_idx;
}
NVHLS_ASSERT(std::find(dest_maps_idx_vec.begin(), dest_maps_idx_vec.end(),
dest_map_idx) == dest_maps_idx_vec.end());
dest_maps_idx_vec.push_back(dest_map_idx);
return dest_map_idx;
}
void config_dest_map_idx(dest_map_idx_t dest_map_idx, idx_t dest_idx,
idx_t real_dest_idx) {
NVHLS_ASSERT_MSG(dest_map_idx != 0,
"The default dest_map_idx=0 is fixed, and cannot be "
"manually assigned. Use a dest_map_idx > 0.");
NVHLS_ASSERT_MSG(
std::find(dest_maps_idx_vec.begin(), dest_maps_idx_vec.end(),
dest_map_idx) != dest_maps_idx_vec.end(),
"Couldn't find dest_map_idx!");
dest_maps[dest_map_idx][dest_idx] = real_dest_idx;
}
void config_dest_map_idx(dest_map_idx_t dest_map_idx, idx_t dest_idx,
IM_dest_t &p) {
config_dest_map_idx(dest_map_idx, dest_idx, this->find_dest_idx(&p));
}
void add_to_dest_directory(IM_dest_t &p, unsigned int part_id,
unsigned int msg_id, unsigned int port_id = 0,
bool allow_duplicate = false) {
auto tuple_idx = std::make_tuple(part_id, msg_id, port_id);
if (!allow_duplicate) {
NVHLS_ASSERT_MSG(
interconnect::get_ICManager().dest_directory.find(tuple_idx) ==
interconnect::get_ICManager().dest_directory.end(),
"Already have a destination matching that index");
}
interconnect::get_ICManager().dest_directory[tuple_idx].add(
this->find_dest_idx(&p));
}
template <typename MSG_TYPE>
void add_to_dest_directory(
Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p,
unsigned int part_id, unsigned int port_id = 0,
bool allow_duplicate = false) {
add_to_dest_directory(*generic_iface_dests[&p]->im_ptr, part_id,
MSG_TYPE::msg_id, port_id, allow_duplicate);
}
route_t *create_route() { return new Route(*this); }
////////////////////////////////////////////////////////////////////////////////////////////////
// Helpers
// Sets w to smallest width that is >= min_w. Returns false if no min width is
// found.
template <typename T>
bool ports_min_width(T &ref, unsigned int &w, unsigned int min_w = 0) {
bool found = false;
for (typename T::iterator it_ref = ref.begin(); it_ref != ref.end();
++it_ref) {
if (it_ref->second >= min_w && (it_ref->second < w || !found)) {
w = it_ref->second;
found = true;
}
}
return found;
}
bool srcs_and_dests_min_width(unsigned int &w, unsigned int min_w = 0) {
return ports_min_width(srcs_width, w, min_w) ||
ports_min_width(dests_width, w, min_w);
}
void pretty_print() {
cout << std::string(100, '#') << endl;
unsigned int current_port_width;
bool port_width_found = srcs_and_dests_min_width(current_port_width);
while (port_width_found) {
cout << "# " << dec << current_port_width << "-bit Ports" << endl;
cout << "## Sources" << endl;
for (typename srcs_t::iterator it_src = srcs.begin();
it_src != srcs.end(); ++it_src) {
if (srcs_width[*it_src] == current_port_width) {
if (find(disabled_srcs.begin(), disabled_srcs.end(), *it_src) !=
disabled_srcs.end()) {
cout << " - " << get_src_name(*it_src) << " is disabled." << endl;
} else if (srcs_user_typeid.find(*it_src) != srcs_user_typeid.end()) {
cout << " - " << get_src_name(*it_src)
<< " (user typeid = " << srcs_user_typeid[*it_src]
<< ") connects to "
<< num_compatible_channels_from_src(*it_src)
<< " destinations." << endl;
} else {
cout << " - " << get_src_name(*it_src) << " connects to "
<< num_compatible_channels_from_src(*it_src)
<< " destinations." << endl;
}
}
}
cout << endl;
cout << "## Destinations" << endl;
for (typename dests_t::iterator it_dest = dests.begin();
it_dest != dests.end(); ++it_dest) {
if (dests_width[*it_dest] == current_port_width) {
if (find(disabled_dests.begin(), disabled_dests.end(), *it_dest) !=
disabled_dests.end()) {
cout << " - " << get_dest_name(*it_dest) << " is disabled."
<< endl;
} else if (dests_user_typeid.find(*it_dest) !=
dests_user_typeid.end()) {
cout << " - " << get_dest_name(*it_dest)
<< " (user typeid = " << dests_user_typeid[*it_dest]
<< ") connects from "
<< num_compatible_channels_to_dest(*it_dest) << " sources."
<< endl;
} else {
cout << " - " << get_dest_name(*it_dest) << " connects from "
<< num_compatible_channels_to_dest(*it_dest) << " sources."
<< endl;
}
}
}
cout << endl;
cout << endl;
// update
port_width_found =
srcs_and_dests_min_width(current_port_width, current_port_width + 1);
}
cout << "# Summary" << endl;
cout << "Source Count = " << get_src_size() << endl;
cout << "Destination Count = " << get_dest_size() << endl;
cout << std::string(100, '#') << endl;
cout << endl;
}
void print_statistics(bool include_no_traffic = false) {
cout << std::string(100, '#') << endl;
cout << "# Traffic Summary" << endl;
unsigned int current_port_width;
bool port_width_found = srcs_and_dests_min_width(current_port_width);
while (port_width_found) {
bool found_one = false;
cout << "# " << dec << current_port_width << "-bit Ports" << endl;
cout << endl;
for (typename channels_middle_t::iterator it_src =
channels_middle.begin();
it_src != channels_middle.end(); ++it_src) {
for (typename channels_middle_inner_t::iterator it_dest =
it_src->second.begin();
it_dest != it_src->second.end(); ++it_dest) {
if (srcs_width[it_src->first] == current_port_width) {
NVHLS_ASSERT_MSG(
dests_width[it_dest->first] == current_port_width,
"Src and dest widths should match, but they don't!");
if (cycle_count_channel[it_src->first][it_dest->first]
.to_uint64() == 0) {
if (include_no_traffic) {
cout << "Src = " << get_src_name(it_src->first)
<< "Dest = " << get_dest_name(it_dest->first)
<< ", NO TRAFFIC" << endl;
found_one = true;
}
} else {
cout << " - " << get_src_name(it_src->first) << " --> "
<< get_dest_name(it_dest->first) << ", messages = " << dec
<< cycle_count_channel[it_src->first][it_dest->first]
.to_uint64()
<< " ("
<< boost::format("%2.f%%") %
(100.0 *
cycle_count_channel[it_src->first][it_dest->first]
.to_uint64() /
cycle_count_total.to_uint64())
<< ")" << endl;
found_one = true;
}
}
}
}
if (found_one == false) {
cout << " (none with non-zero message counts)" << endl;
}
cout << endl;
// update
port_width_found =
srcs_and_dests_min_width(current_port_width, current_port_width + 1);
}
cout << endl
<< "Total cycles was: " << cycle_count_total.to_uint64() << endl;
cout << std::string(100, '#') << endl;
cout << endl;
}
protected:
// Unsupported in this code-- implement in future
void enable_fixed_bypass(IM_src_t &s, IM_dest_t &d) {
// Remove channels_middle
NVHLS_ASSERT(0);
}
void before_end_of_elaboration() {
for (typename srcs_t::iterator it_src = srcs.begin(); it_src != srcs.end();
++it_src) {
for (typename dests_t::iterator it_dest = dests.begin();
it_dest != dests.end(); ++it_dest) {
if (is_compatible_channels_pre_elab(*it_src, *it_dest)) {
// Generate the name
std::string new_channel_name =
get_src_name(*it_src) + "__to__" + get_dest_name(*it_dest);
boost::replace_all(new_channel_name, ".", "_");
// Create the new channel object
IM_chanlink_t *new_channel =
new IM_chanlink_t(new_channel_name.c_str());
std::string src_name_str = get_src_name(*it_src);
char *src_name_new = new char[src_name_str.size() + 1];
strcpy(src_name_new, src_name_str.c_str());
new_channel->in_str = src_name_new;
std::string dest_name_str = get_dest_name(*it_dest);
char *dest_name_new = new char[dest_name_str.size() + 1];
strcpy(dest_name_new, dest_name_str.c_str());
new_channel->out_str = dest_name_new;
// Add it to channels_middle
channels_middle[(*it_src)][(*it_dest)] = new_channel;
// Add it to reverse channels
channels_valid_pairs_reverse[(*it_dest)].push_back(*it_src);
}
}
}
// Source read channels
for (typename srcs_t::iterator it_src = srcs.begin(); it_src != srcs.end();
++it_src) {
// Create new channel
IM_chan_t *new_channel =
new IM_chan_t(sc_gen_unique_name("new_channel_src"));
channels_begin[(*it_src)] = new_channel;
// Bind it and disable annotation
(*it_src)->Bind(*new_channel);
new_channel->disable_annotate();
// Create a new input arbitration object, depending on size
if (num_compatible_channels_from_src(*it_src) == 1) {
// Special bypass
new InputBypass(*this, (*it_src),
channels_middle[*it_src].begin()->first, channels_begin,
channels_middle, channels_end);
} else {
// Otherwise the normal input decode module
InputDecoder *i_dec = new InputDecoder(*this, (*it_src), channels_begin,
channels_middle, channels_end);
i_dec->clk(clk);
i_dec->rst(rst);
}
}
// Destination write channels
for (typename dests_t::iterator it_dest = dests.begin();
it_dest != dests.end(); ++it_dest) {
// Create new channel
IM_chan_t *new_channel =
new IM_chan_t(sc_gen_unique_name("new_channel_dest"));
channels_end[(*it_dest)] = new_channel;
// Bind it and disable annotation
(*it_dest)->Bind(*new_channel);
new_channel->disable_annotate();
// Create a new output arbitration object
if (num_compatible_channels_to_dest(*it_dest) == 1) {
OutputBypass *o_bypass =
new OutputBypass(*this, (*it_dest),
*(channels_valid_pairs_reverse[*it_dest].begin()),
channels_begin, channels_middle, channels_end,
channels_valid_pairs_reverse, cycle_count_channel);
o_bypass->clk(clk);
o_bypass->rst(rst);
} else {
OutputArbiter *o_arb = new OutputArbiter(
*this, (*it_dest), channels_begin, channels_middle, channels_end,
channels_valid_pairs_reverse, cycle_count_channel);
o_arb->clk(clk);
o_arb->rst(rst);
}
}
const char *BUILD_PREFIX = std::getenv("BUILD");
std::string interconnect_dir = "interconnect";
if (BUILD_PREFIX) {
interconnect_dir += std::string("_") + std::string(BUILD_PREFIX);
BUILD_PREFIX = "";
} else {
BUILD_PREFIX = "";
}
// Write out latency here.
const char *nvhls_elab_only = std::getenv("NVHLS_ELAB_ONLY");
if (nvhls_elab_only && std::string(nvhls_elab_only) == "1") {
interconnect::save_connectivity(*this, *this, BUILD_PREFIX,
interconnect_dir);
cout << "Info: Elaboration only run. Quiting..." << endl;
sc_stop();
} else {
interconnect::annotate_design(*this, *this, BUILD_PREFIX,
interconnect_dir, interconnect_dir);
}
}
bool is_compatible_channels_pre_elab(IM_src_t *src, IM_dest_t *dest) {
bool src_exists = (srcs_typeid.find(src) != srcs_typeid.end());
bool dest_exists = (dests_typeid.find(dest) != dests_typeid.end());
bool src_disabled = find(disabled_srcs.begin(), disabled_srcs.end(), src) !=
disabled_srcs.end();
bool dest_disabled = find(disabled_dests.begin(), disabled_dests.end(),
dest) != disabled_dests.end();
// investigate why ModuleArray fails this assertion. Probably need to
// populate. srcs_block_abs/dests_block_abs with other Bind()
// Disabling for now.
// Connections::Blocking_abs *src_port_block_abs = srcs_block_abs[src];
// Connections::Blocking_abs *dest_port_block_abs = dests_block_abs[dest];
// assert(src_port_block_abs && dest_port_block_abs);
// bool pair_disabled = find(disabled_pairs.begin(), disabled_pairs.end(),
// std::make_tuple(src_port_block_abs, dest_port_block_abs))
// != disabled_pairs.end();
bool pair_disabled = false;
bool src_has_user_typeid =
(srcs_user_typeid.find(src) != srcs_user_typeid.end());
bool dest_has_user_typeid =
(dests_user_typeid.find(dest) != dests_user_typeid.end());
if (!(src_exists && dest_exists)) {
if (!src_exists)
CDCOUT("Warning: Interconnect bound source port "
<< get_src_name(src) << " doesn't have an assigned type."
<< endl,
interconnect::kDebugLevel);
if (!dest_exists)
CDCOUT("Warning: Interconnect bound destination port "
<< get_dest_name(dest) << " doesn't have an assigned type."
<< endl,
interconnect::kDebugLevel);
return true;
}
// Fail conditions
if (src_disabled || dest_disabled || pair_disabled) {
return false;
}
if (src_has_user_typeid != dest_has_user_typeid) {
return false;
}
if (src_has_user_typeid && dest_has_user_typeid &&
(srcs_user_typeid[src] != dests_user_typeid[dest])) {
return false;
}
if (!src_has_user_typeid ||
!dest_has_user_typeid) { // HERE adding in this condition.
if (srcs_typeid[src] != dests_typeid[dest]) {
return false;
}
}
// Pass condition
return true;
}
bool is_compatible_channels(IM_src_t *src, IM_dest_t *dest) {
typename channels_middle_t::iterator it_dest = channels_middle.find(src);
return (it_dest != channels_middle.end()) &&
it_dest->second.find(dest) != it_dest->second.end();
}
unsigned int num_compatible_channels_from_src(IM_src_t *p) {
return (channels_middle.find(p) == channels_middle.end())
? 0
: channels_middle[p].size();
}
unsigned int num_compatible_channels_to_dest(IM_dest_t *p) {
return (channels_valid_pairs_reverse.find(p) ==
channels_valid_pairs_reverse.end())
? 0
: channels_valid_pairs_reverse[p].size();
}
////////////////////////////////////////////////////////////////////////////////
// Route
class Route {
public:
typedef std::vector<IM_dest_t *> route_vec_t;
typedef typename route_vec_t::iterator iterator;
protected:
InterconnectBase<IM> ⁣
route_vec_t route_vec;
public:
Route(InterconnectBase<IM> &ic_) : ic(ic_) {}
void add_dest(idx_t dest_idx, dest_map_idx_t dest_map_idx = 0) {
route_vec.push_back(ic.get_dest_from_idx(dest_idx, dest_map_idx));
}
iterator begin() { return route_vec.begin(); }
iterator end() { return route_vec.end(); }
int size() { return route_vec.size(); }
};
////////////////////////////////////////////////////////////////////////////////
// InputDecoder
class InputDecoder : public sc_module, public Connections::Blocking_abs {
SC_HAS_PROCESS(InputDecoder);
protected:
InterconnectBase<IM> ⁣
IM_src_t *p;
channels_begin_t &channels_begin;
channels_middle_t &channels_middle;
channels_end_t &channels_end;
public:
sc_in_clk clk;
sc_in<bool> rst;
explicit InputDecoder(InterconnectBase<IM> &ic_, IM_src_t *p_,
channels_begin_t &channels_begin_,
channels_middle_t &channels_middle_,
channels_end_t &channels_end_)
: sc_module(sc_module_name(sc_gen_unique_name("input_decoder"))),
ic(ic_),
p(p_),
channels_begin(channels_begin_),
channels_middle(channels_middle_),
channels_end(channels_end_),
clk(sc_gen_unique_name("cl
|
k")),
rst(sc_gen_unique_name("rst")) {
SC_CTHREAD(input_dec_run, clk.pos());
async_reset_signal_is(rst, false);
}
void input_dec_run() {
IM data;
// Reset input
channels_begin[p]->ResetRead();
// Check if we have valid outputs.
switch (ic.num_compatible_channels_from_src(p)) {
case 0:
CDCOUT("Info: Source port "
<< ic.get_src_name(p)
<< " doesn't have any valid destinations. Disabling "
"thread for "
"this source port in the interconnect modeler."
<< endl,
interconnect::kDebugLevel);
return;
}
// Reset outputs.
for (typename channels_middle_inner_t::iterator it_dest =
channels_middle[p].begin();
it_dest != channels_middle[p].end(); ++it_dest) {
it_dest->second->ResetWrite();
}
while (1) {
wait();
IM data;
if (channels_begin[p]->PopNB(data)) {
data.set_src_idx(ic, p);
typename IM::multicast_t multicast_dests = data.get_multicast(ic);
for (typename IM::multicast_t::iterator it = multicast_dests.begin();
it != multicast_dests.end(); ++it) {
NVHLS_ASSERT_MSG(ic.is_compatible_channels(p, (*it)),
"Interconnect received a source mesage to an "
"invalid or incompatible destination.");
channels_middle[p][(*it)]->Push(data);
}
}
}
}
}; // end class InputDecoder
////////////////////////////////////////////////////////////////////////////////
// InputBypass
class InputBypass : public sc_module, public Connections::Blocking_abs {
SC_HAS_PROCESS(InputBypass);
protected:
InterconnectBase<IM> ⁣
IM_src_t *p;
IM_dest_t *q;
channels_begin_t &channels_begin;
channels_middle_t &channels_middle;
channels_end_t &channels_end;
public:
explicit InputBypass(InterconnectBase<IM> &ic_, IM_src_t *p_, IM_dest_t *q_,
channels_begin_t &channels_begin_,
channels_middle_t &channels_middle_,
channels_end_t &channels_end_)
: sc_module(sc_module_name(sc_gen_unique_name("input_bypass"))),
ic(ic_),
p(p_),
q(q_),
channels_begin(channels_begin_),
channels_middle(channels_middle_),
channels_end(channels_end_) {
CDCOUT("Info: Source port "
<< ic.get_src_name(p)
<< " only has one valid destination. Adding a bypass to this "
"source port in the interconnect modeler."
<< endl,
interconnect::kDebugLevel);
#ifdef CONNECTIONS_SIM_ONLY
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << channels_begin[p]->_DATNAMEOUT_
<< channels_begin[p]->_VLDNAMEOUT_
<< channels_middle[p][q]->_RDYNAMEIN_;
channels_begin[p]->out_bound = true;
channels_middle[p][q]->in_bound = true;
#endif
}
void do_bypass() {
bool is_val = channels_begin[p]->_VLDNAMEOUT_.read();
// Set val and msg respectively
channels_middle[p][q]->_VLDNAMEIN_.write(is_val);
channels_begin[p]->_RDYNAMEOUT_.write(channels_middle[p][q]->_RDYNAMEIN_.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
channels_middle[p][q]->_DATNAMEIN_.write(channels_begin[p]->_DATNAMEOUT_.read());
}
}
}; // end class InputBypass
// OutputArbiter
class OutputArbiter : public sc_module, public Connections::Blocking_abs {
SC_HAS_PROCESS(OutputArbiter);
protected:
InterconnectBase<IM> ⁣
IM_dest_t *p;
channels_begin_t &channels_begin;
channels_middle_t &channels_middle;
channels_end_t &channels_end;
channels_valid_pairs_reverse_t &channels_valid_pairs_reverse;
cycle_count_channel_t &cycle_count_channel;
public:
sc_in_clk clk;
sc_in<bool> rst;
explicit OutputArbiter(
InterconnectBase<IM> &ic_, IM_dest_t *p_,
channels_begin_t &channels_begin_, channels_middle_t &channels_middle_,
channels_end_t &channels_end_,
channels_valid_pairs_reverse_t &channels_valid_pairs_reverse_,
cycle_count_channel_t &cycle_count_channel_)
: sc_module(sc_module_name(sc_gen_unique_name("output_arbiter"))),
ic(ic_),
p(p_),
channels_begin(channels_begin_),
channels_middle(channels_middle_),
channels_end(channels_end_),
channels_valid_pairs_reverse(channels_valid_pairs_reverse_),
cycle_count_channel(cycle_count_channel_),
clk(sc_gen_unique_name("clk")),
rst(sc_gen_unique_name("rst")) {
SC_CTHREAD(output_arb_run, clk.pos());
async_reset_signal_is(rst, false);
}
void output_arb_run() {
IM data;
// Reset output
channels_end[p]->ResetWrite();
// Check if we have valid inputs.
switch (ic.num_compatible_channels_to_dest(p)) {
case 0:
CDCOUT("Info: Destination port "
<< ic.get_dest_name(p)
<< " doesn't have any valid sources. Disabling thread for "
"this "
"destination port in the interconnect modeler."
<< endl,
interconnect::kDebugLevel);
return;
case 1:
CDCOUT("Warning: FIXME Optimization Destination port "
<< ic.get_dest_name(p)
<< " only has one source, could optimize." << endl,
interconnect::kDebugLevel);
break;
}
for (typename channels_valid_pairs_reverse_inner_t::iterator it_src =
channels_valid_pairs_reverse[p].begin();
it_src != channels_valid_pairs_reverse[p].end(); ++it_src) {
channels_middle[*it_src][p]->ResetRead();
cycle_count_channel[*it_src][p] = 0;
}
// Start round robin at beginning.
typename channels_valid_pairs_reverse_inner_t::iterator
last_grant_it_src_begin = channels_valid_pairs_reverse[p].begin();
typename channels_valid_pairs_reverse_inner_t::iterator
last_grant_it_src_end = channels_valid_pairs_reverse[p].end();
typename channels_valid_pairs_reverse_inner_t::iterator
last_grant_it_src = last_grant_it_src_begin;
while (1) {
wait();
typename channels_valid_pairs_reverse_inner_t::iterator it_src =
last_grant_it_src;
do {
if (channels_middle[*it_src][p]->PopNB(data)) {
channels_end[p]->Push(data); // Push
cycle_count_channel[*it_src][p]++; // Monitor
last_grant_it_src = it_src; // Update
}
if (++it_src == last_grant_it_src_end) {
it_src = last_grant_it_src_begin;
}
} while (it_src != last_grant_it_src);
} // while(1)
}
}; // end class OutputArbiter
// OutputBypass
class OutputBypass : public sc_module, public Connections::Blocking_abs {
SC_HAS_PROCESS(OutputBypass);
protected:
InterconnectBase<IM> ⁣
IM_dest_t *p;
IM_src_t *q;
channels_begin_t &channels_begin;
channels_middle_t &channels_middle;
channels_end_t &channels_end;
channels_valid_pairs_reverse_t &channels_valid_pairs_reverse;
cycle_count_channel_t &cycle_count_channel;
public:
sc_in_clk clk;
sc_in<bool> rst;
explicit OutputBypass(
InterconnectBase<IM> &ic_, IM_dest_t *p_, IM_src_t *q_,
channels_begin_t &channels_begin_, channels_middle_t &channels_middle_,
channels_end_t &channels_end_,
channels_valid_pairs_reverse_t &channels_valid_pairs_reverse_,
cycle_count_channel_t &cycle_count_channel_)
: sc_module(sc_module_name(sc_gen_unique_name("output_arb"))),
ic(ic_),
p(p_),
q(q_),
channels_begin(channels_begin_),
channels_middle(channels_middle_),
channels_end(channels_end_),
channels_valid_pairs_reverse(channels_valid_pairs_reverse_),
cycle_count_channel(cycle_count_channel_),
clk(sc_gen_unique_name("clk")),
rst(sc_gen_unique_name("rst")) {
CDCOUT("Info: Destination port "
<< ic.get_dest_name(p)
<< " only has one valid source. Adding a bypass to this "
"destination port in the interconnect modeler."
<< endl,
interconnect::kDebugLevel);
#ifdef CONNECTIONS_SIM_ONLY
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << channels_middle[q][p]->_DATNAMEOUT_
<< channels_middle[q][p]->_VLDNAMEOUT_
<< channels_end[p]->_RDYNAMEIN_;
channels_end[p]->in_bound = true;
channels_middle[q][p]->out_bound = true;
#endif
SC_CTHREAD(output_bypass_run, clk.pos());
async_reset_signal_is(rst, false);
}
void do_bypass() {
bool is_val = channels_middle[q][p]->_VLDNAMEOUT_.read();
// Set val and msg respectively
channels_end[p]->_VLDNAMEIN_.write(is_val);
channels_middle[q][p]->_RDYNAMEOUT_.write(channels_end[p]->_RDYNAMEIN_.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
channels_end[p]->_DATNAMEIN_.write(channels_middle[q][p]->_DATNAMEOUT_.read());
}
}
void output_bypass_run() {
cycle_count_channel[q][p] = 0;
while (1) {
wait();
if (channels_end[p]->_VLDNAMEIN_.read() && channels_end[p]->_RDYNAMEIN_.read())
cycle_count_channel[q][p]++; // Monitor
} // while(1)
}
}; // end class OutputBypass
}; // end class InterconnectBase
template <unsigned int IC_ID>
class Interconnect : public InterconnectBase<interconnect::IM_t> {
public:
Interconnect() : InterconnectBase<interconnect::IM_t>(IC_ID) {
// Register with static vector of interconnect objects.
// Ensure that only one matches the IC_ID.
if (interconnect::get_ICManager().registered_ic.find(IC_ID) !=
interconnect::get_ICManager().registered_ic.end()) {
NVHLS_ASSERT_MSG(0,
"An interconnect with this IC_ID is already registered");
}
interconnect::get_ICManager().registered_ic[IC_ID] = this;
}
explicit Interconnect(const char *name)
: InterconnectBase<interconnect::IM_t>(name, IC_ID) {
// Register with static vector of interconnect objects.
// Ensure that only one matches the IC_ID.
if (interconnect::get_ICManager().registered_ic.find(IC_ID) !=
interconnect::get_ICManager().registered_ic.end()) {
NVHLS_ASSERT_MSG(0,
"An interconnect with this IC_ID is already registered");
}
interconnect::get_ICManager().registered_ic[IC_ID] = this;
}
};
template <unsigned int MaxDataWidth, unsigned int MaxDestCount>
class InterconnectMessageSCLV : public nvhls_message {
public:
typedef InterconnectBase<InterconnectMessageSCLV<MaxDataWidth, MaxDestCount> >
interconnect_t;
typedef typename interconnect_t::route_t route_t;
typedef std::vector<typename interconnect_t::IM_dest_t *> multicast_t;
// For marshaller
enum {
width = Wrapped<sc_lv<MaxDataWidth> >::width +
Wrapped<typename interconnect_t::idx_t>::width +
Wrapped<sc_lv<MaxDestCount> >::width
};
protected:
sc_lv<MaxDataWidth> msg_bits;
typename interconnect_t::idx_t src_idx;
public:
sc_lv<MaxDestCount> dest_bits;
// Need to provide default constructor to be compatible with use as a Message
InterconnectMessageSCLV() : msg_bits(0), src_idx(-1), dest_bits(0) {}
template <unsigned int Size>
void Marshall(Marshaller<Size> &m) {
m &msg_bits;
m &src_idx;
m &dest_bits;
}
////////////////////////////////////////////////////////////////////////////////
// Getters and Setters
////////////////////
// Message
template <typename Message>
void set_msg(interconnect_t &ic, Message &msg_) {
set_msg(msg_);
}
template <typename Message>
void set_msg(Message &msg_) {
// Ensure sized appropriately.
NVHLS_ASSERT(Wrapped<Message>::width <= MaxDataWidth);
// Convert from Message to general sc_lv type
Marshaller<Wrapped<Message>::width> marshaller;
Wrapped<Message> wm(msg_);
wm.Marshall(marshaller);
msg_bits.range(Wrapped<Message>::width - 1, 0) = marshaller.GetResult();
}
template <typename Message>
void get_msg(interconnect_t &ic, Message &m_) const {
get_msg(m_);
}
template <typename Message>
void get_msg(Message &m_) const {
// Ensure sized appropriately.
NVHLS_ASSERT(Wrapped<Message>::width <= MaxDataWidth);
// Convert from general sc_lv type to Message
sc_lv<Wrapped<Message>::width> mbits;
mbits = msg_bits.range(Wrapped<Message>::width - 1, 0);
Marshaller<Wrapped<Message>::width> marshaller(mbits);
Wrapped<Message> result;
result.Marshall(marshaller);
m_ = result.val;
}
////////////////////
// Source
void set_src_idx(interconnect_t &ic, typename interconnect_t::IM_src_t *p) {
src_idx = ic.find_src_idx(p);
}
typename interconnect_t::IM_src_t *get_src_from_idx(interconnect_t &ic) {
return ic.get_src_from_idx(src_idx);
}
////////////////////
// Destination
// get_route() to replace this
multicast_t get_multicast(interconnect_t &ic) {
multicast_t a;
// Ensure sized appropriately
NVHLS_ASSERT(ic.get_dest_size() <= MaxDestCount);
for (unsigned int i = 0; i < ic.get_dest_size(); i++) {
if (dest_bits[i] == 1) {
a.push_back(ic.get_dest_from_idx(i));
}
}
return a;
}
void set_route(interconnect_t &ic, route_t *route) {
dest_bits = 0;
for (typename route_t::iterator it = route->begin(); it != route->end();
++it) {
dest_bits[ic.find_dest_idx(*it)] = 1;
}
}
bool does_support_multicast() { return true; }
};
#endif // ifdef CONNECTIONS_SIM_ONLY
template <typename Message>
class OutPortPin : public sc_module {
SC_HAS_PROCESS(OutPortPin);
public:
Connections::OutBlocking<Message> &port;
Connections::InBlocking<Message> pin;
explicit OutPortPin(Connections::OutBlocking<Message> &port_)
: sc_module(sc_module_name(sc_gen_unique_name("out_port_to_in_pin"))),
port(port_) {
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << pin._DATNAME_ << pin._VLDNAME_ << port._RDYNAME_;
#ifdef CONNECTIONS_SIM_ONLY
port.disable_spawn();
pin.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = pin._VLDNAME_.read();
// Set val and msg respectively
port._VLDNAME_.write(is_val);
pin._RDYNAME_.write(port._RDYNAME_.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
port._DATNAME_.write(pin._DATNAME_.read());
}
}
}; // class OutPortPin
template <typename Message>
class InPortPin : public sc_module {
SC_HAS_PROCESS(InPortPin);
public:
Connections::InBlocking<Message> &port;
Connections::OutBlocking<Message> pin;
explicit InPortPin(Connections::InBlocking<Message> &port_)
: sc_module(sc_module_name(sc_gen_unique_name("in_port_to_out_pin"))),
port(port_) {
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << port._DATNAME_ << port._VLDNAME_ << pin._RDYNAME_;
#ifdef CONNECTIONS_SIM_ONLY
port.disable_spawn();
pin.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = port._VLDNAME_.read();
// Set val and msg respectively
pin._VLDNAME_.write(is_val);
port._RDYNAME_.write(pin._RDYNAME_.read());
// Only convert if is_val (to prevent X's)
if (is_val) {
pin._DATNAME_.write(port._DATNAME_.read());
}
}
}; // class InPortPin
template <typename Message>
class OutPortPin2 : public sc_module {
SC_HAS_PROCESS(OutPortPin2);
public:
Connections::OutBlocking<Message> port;
Connections::InBlocking<Message> pin;
explicit OutPortPin2()
: sc_module(sc_module_name(sc_gen_unique_name("out_port_to_in_pin"))) {
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << pin._DATNAME_ << pin._VLDNAME_ << port._RDYNAME_;
#ifdef CONNECTIONS_SIM_ONLY
port.disable_spawn();
pin.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = pin._VLDNAME_.read();
// Set val and msg respectively
port._VLDNAME_.write(is_val);
pin._RDYNAME_.write(port._RDYNAME_.read());
// Only convert if is_val (to prevent X's)
#ifndef __SYNTHESIS__
if (is_val) {
#endif
port._DATNAME_.write(pin._DATNAME_.read());
#ifndef __SYNTHESIS__
}
#endif
}
}; // class OutPortPin2
template <typename Message>
class InPortPin2 : public sc_module {
SC_HAS_PROCESS(InPortPin2);
public:
Connections::InBlocking<Message> port;
Connections::OutBlocking<Message> pin;
explicit InPortPin2()
: sc_module(sc_module_name(sc_gen_unique_name("in_port_to_out_pin"))) {
// SC_METHOD(do_bypass);
declare_method_process(do_bypass_handle, sc_gen_unique_name("do_bypass"),
SC_CURRENT_USER_MODULE, do_bypass);
this->sensitive << port._DATNAME_ << port._VLDNAME_ << pin._RDYNAME_;
#ifdef CONNECTIONS_SIM_ONLY
port.disable_spawn();
pin.disable_spawn();
#endif
}
void do_bypass() {
bool is_val = port._VLDNAME_.read();
// Set val and msg respectively
pin._VLDNAME_.write(is_val);
port._RDYNAME_.write(pin._RDYNAME_.read());
// Only convert if is_val (to prevent X's)
#ifndef __SYNTHESIS__
if (is_val) {
#endif
pin._DATNAME_.write(port._DATNAME_.read());
#ifndef __SYNTHESIS__
}
#endif
}
}; // class InPortPin2
template <typename Message>
InPortPin<Message> *new_port_pin(Connections::InBlocking<Message> &port_) {
return new InPortPin<Message>(port_);
}
template <typename Message>
OutPortPin<Message> *new_port_pin(Connections::OutBlocking<Message> &port_) {
return new OutPortPin<Message>(port_);
}
template <typename Message>
InPortPin2<Message> *new_port_pin2(Connections::InBlocking<Message> &port_) {
auto *port_pin = new InPortPin2<Message>();
port_pin->port(port_);
return port_pin;
}
template <typename Message>
OutPortPin2<Message> *new_port_pin2(Connections::OutBlocking<Message> &port_) {
auto *port_pin = new OutPortPin2<Message>();
port_pin->port(port_);
return port_pin;
}
};
#ifndef __SYNTHESIS__
namespace interconnect {
template <typename PART_TYPE,
Connections::connections_port_t PortType = AUTO_PORT>
class InterconnectInterface {
public:
sc_in_clk clk;
sc_in<bool> rst;
// IC_t *parent_ic;
InterconnectBase<IM_t> *parent_ic;
unsigned int part_id;
bool is_bound;
std::map<Connections::Blocking_abs *, GenericDestHandlerIface<IM_t> *>
generic_iface_dests;
std::map<Connections::Blocking_abs *, MSG_ID_t> msg_id_dests;
std::map<Connections::Blocking_abs *, unsigned int> port_id_dests;
std::map<Connections::Blocking_abs *, std::string> port_name_dests;
std::map<Connections::Blocking_a
|
bs *, width_t> type_width_dests;
std::map<Connections::Blocking_abs *, const char *> type_name_dests;
std::map<Connections::Blocking_abs *, const char *> msg_name_dests;
std::map<Connections::Blocking_abs *, GenericSrcHandlerIface<IM_t> *>
generic_iface_srcs;
std::map<Connections::Blocking_abs *, MSG_ID_t> msg_id_srcs;
std::map<Connections::Blocking_abs *, unsigned int> port_id_srcs;
std::map<Connections::Blocking_abs *, std::string> port_name_srcs;
std::map<Connections::Blocking_abs *, width_t> type_width_srcs;
std::map<Connections::Blocking_abs *, const char *> type_name_srcs;
std::map<Connections::Blocking_abs *, const char *> msg_name_srcs;
#ifdef CONNECTIONS_SIM_ONLY
InterconnectInterface() : clk("clk"), rst("rst"), is_bound(false) {}
explicit InterconnectInterface(const char *name)
: clk("clk"), rst("rst"), is_bound(false) {}
template <unsigned int BIND_ID, typename MSG_TYPE>
void Bind(Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p,
unsigned int port_id) {
ICMToSpecialized<IM_t, MSG_TYPE> *ij =
new ICMToSpecialized<IM_t, MSG_TYPE>(p);
std::string port_name = p._VLDNAME_.name();
if (port_name.substr(port_name.length() - 4, 4) == "_" _VLDNAMESTR_) {
port_name.erase(port_name.length() - 4, 4);
}
generic_iface_dests[&p] = ij;
msg_id_dests[&p] = MSG_TYPE::msg_id;
port_id_dests[&p] = port_id;
port_name_dests[&p] = port_name;
type_width_dests[&p] = Wrapped<typename MSG_TYPE::data_t>::width;
type_name_dests[&p] = typeid(typename MSG_TYPE::data_t).name();
msg_name_dests[&p] = MSG_TYPE::name;
if (is_bound) {
Bind2_Dest(&p, msg_id_dests[&p], port_id_dests[&p], msg_name_dests[&p]);
}
}
template <unsigned int BIND_ID, typename MSG_TYPE>
void Bind(Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p,
unsigned int port_id) {
ICMFromSpecialized<IM_t, MSG_TYPE> *is =
new ICMFromSpecialized<IM_t, MSG_TYPE>(p);
std::string port_name = p._VLDNAME_.name();
if (port_name.substr(port_name.length() - 4, 4) == "_" _VLDNAMESTR_) {
port_name.erase(port_name.length() - 4, 4);
}
generic_iface_srcs[&p] = is;
msg_id_srcs[&p] = MSG_TYPE::msg_id;
port_id_srcs[&p] = port_id;
port_name_srcs[&p] = port_name;
type_width_srcs[&p] = Wrapped<typename MSG_TYPE::data_t>::width;
type_name_srcs[&p] = typeid(typename MSG_TYPE::data_t).name();
msg_name_srcs[&p] = MSG_TYPE::name;
if (is_bound) {
Bind2_Src(&p, msg_id_srcs[&p], port_id_srcs[&p], msg_name_srcs[&p]);
}
}
template <unsigned int IC_ID>
void do_parent_bind(Interconnect<IC_ID> &ic, const sc_object &parent,
const unsigned int &part_id_) {
assert(!is_bound);
parent_ic = ⁣
part_id = part_id_;
is_bound = true;
ic.part_names[PART_TYPE::part_id] = PART_TYPE::name;
ic.part_to_part_type[part_id_] = PART_TYPE::part_id;
ic.part_inst_names[part_id_] = parent.name();
NVHLS_ASSERT(parent.name());
for (std::map<Connections::Blocking_abs *, MSG_ID_t>::iterator it =
msg_id_dests.begin();
it != msg_id_dests.end(); ++it) {
// Bind
Bind2_Dest(it->first, it->second, port_id_dests[it->first],
msg_name_dests[it->first]);
ic.part_msgs_dests[PART_TYPE::part_id][it->second].insert(
port_id_dests[it->first]);
}
for (std::map<Connections::Blocking_abs *, MSG_ID_t>::iterator it =
msg_id_srcs.begin();
it != msg_id_srcs.end(); ++it) {
Bind2_Src(it->first, it->second, port_id_srcs[it->first],
msg_name_srcs[it->first]);
ic.part_msgs_srcs[PART_TYPE::part_id][it->second].insert(
port_id_srcs[it->first]);
}
}
protected:
void Bind2_Dest(Connections::Blocking_abs *p, unsigned int msg_id,
unsigned int port_id, const char *msg_name) {
parent_ic->Bind(*generic_iface_dests[p]->im_ptr, msg_id_dests[p],
type_width_dests[p], type_name_dests[p], msg_name);
parent_ic->set_dest_name(generic_iface_dests[p]->im_ptr,
port_name_dests[p]);
parent_ic->add_to_dest_directory(*generic_iface_dests[p]->im_ptr, part_id,
msg_id, port_id);
parent_ic->dests_block_abs[generic_iface_dests[p]->im_ptr] = p;
}
void Bind2_Src(Connections::Blocking_abs *p, unsigned int msg_id,
unsigned int port_id, const char *msg_name) {
parent_ic->Bind(*generic_iface_srcs[p]->im_ptr, msg_id_srcs[p],
type_width_srcs[p], type_name_srcs[p], msg_name);
parent_ic->set_src_name(generic_iface_srcs[p]->im_ptr, port_name_srcs[p]);
parent_ic->srcs_block_abs[generic_iface_srcs[p]->im_ptr] = p;
}
public:
#else
InterconnectInterface() {
NVHLS_ASSERT_MSG(0, "Need an HLS compatible InterconnectInterface!");
}
template <unsigned int PORT_ID, typename MSG_TYPE>
void Bind(Connections::InBlocking<interconnect::Msg<MSG_TYPE> > &p_) {
NVHLS_ASSERT(0);
}
template <unsigned int PORT_ID, typename MSG_TYPE>
void Bind(Connections::OutBlocking<interconnect::Msg<MSG_TYPE> > &p_) {
NVHLS_ASSERT(0);
}
#endif
};
// Enable bottom-up (versus top-down) binding.
// template <unsigned int BIND_ID, unsigned int IC_ID, unsigned int PART_TYPE,
// Connections::connections_port_t IfacePortType>
template <unsigned int BIND_ID, unsigned int IC_ID, typename PART_TYPE,
Connections::connections_port_t IfacePortType>
void do_interconnect_to_interface_bind(
Interconnect<IC_ID> &ic,
interconnect::InterconnectInterface<PART_TYPE, IfacePortType> &ic_interface,
const sc_object &parent, const unsigned int &part_id) {
ic_interface.do_parent_bind(ic, parent, part_id);
}
template <class Dummy>
unsigned int get_real_dest_idx(InterconnectBase<IM_t> &ic,
const unsigned int &dest_idx,
const unsigned int &dest_map_idx) {
return ic.get_real_dest_idx(dest_idx, dest_map_idx);
}
};
#else
namespace interconnect {
template <typename PART_TYPE,
Connections::connections_port_t PortType = AUTO_PORT>
class InterconnectInterface {};
};
#endif
#endif // #ifdef __INTERCONNECT_H__
|
/* Copyright 2017 Columbia University, SLD Group */
//
// system.h - Robert Margelli
// Top-level model header file.
// Instantiates the CPU, TB, IMEM, DMEM.
//
#ifndef SYSTEM_H_INCLUDED
#define SYSTEM_H_INCLUDED
#include <systemc.h>
#include "cynw_flex_channels.h"
#include "hl5_datatypes.hpp"
#include "defines.hpp"
#include "globals.hpp"
#include "hl5_wrap.h"
#include "tb.hpp"
SC_MODULE(TOP)
{
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool > main_start;
// sc_signal < bool > main_end;
// Instruction counters
sc_signal < long int > icount;
sc_signal < long int > j_icount;
sc_signal < long int > b_icount;
sc_signal < long int > m_icount;
sc_signal < long int > o_icount;
// Cache modeled as arryas
sc_uint<XLEN> imem[ICACHE_SIZE];
sc_uint<XLEN> dmem[DCACHE_SIZE];
/* The testbench, DUT, IMEM and DMEM modules. */
tb *m_tb;
hl5_wrapper *m_dut;
SC_CTOR(TOP)
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
{
m_tb = new tb("tb", imem, dmem);
m_dut = new hl5_wrapper("dut", imem, dmem);
// Connect the design module
m_dut->clk(clk);
m_dut->rst(cpu_rst);
m_dut->entry_point(entry_point);
m_dut->program_end(program_end);
m_dut->fetch_en(fetch_en);
// m_dut->main_start(main_start);
// m_dut->main_end(main_end);
m_dut->icount(icount);
m_dut->j_icount(j_icount);
m_dut->b_icount(b_icount);
m_dut->m_icount(m_icount);
m_dut->o_icount(o_icount);
// Connect the testbench
m_tb->clk(clk);
m_tb->rst(rst);
m_tb->cpu_rst(cpu_rst);
m_tb->entry_point(entry_point);
m_tb->program_end(program_end);
m_tb->fetch_en(fetch_en);
// m_tb->main_start(main_start);
// m_tb->main_end(main_end);
m_tb->icount(icount);
m_tb->j_icount(j_icount);
m_tb->b_icount(b_icount);
m_tb->m_icount(m_icount);
m_tb->o_icount(o_icount);
}
~TOP()
{
delete m_tb;
delete m_dut;
delete imem;
delete dmem;
}
};
#endif // SYSTEM_H_INCLUDED
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, fossati@elet.polimi.it, fossati.l@gmail.com
*
\***************************************************************************/
#ifndef PROFINFO_HPP
#define PROFINFO_HPP
#include <string>
#include <systemc.h>
namespace trap{
///Represents all the profiling data which can be
///associated with a single assembly instruction
struct ProfInstruction{
///Name of the assembly instruction (MOV, ADD ...)
std::string name;
///Number of times this instruction is called
unsigned long long numCalls;
///Total number of instructions executed
static unsigned long long numTotalCalls;
///Total time spent in executing the instruction
sc_time time;
///dump these information to a string, in the command separated values (CVS) format
std::string printCsv();
///Prints the description of the informations which describe an instruction, in the command separated values (CVS) format
static std::string printCsvHeader();
///Prints the summary of all the executed instructions, in the command separated values (CVS) format
static std::string printCsvSummary();
///Empty constructor, performs the initialization of the statistics
ProfInstruction();
};
///Represents all the profiling data which can be
///associated with a single function
struct ProfFunction{
///Address of the function
unsigned int address;
///Name of the function
std::string name;
///Number of times this function is called
unsigned long long numCalls;
///Total number of function calls
static unsigned long long numTotalCalls;
///The number of assembly instructions executed in total inside the function
unsigned long long totalNumInstr;
///The number of assembly instructions executed exclusively inside the function
unsigned long long exclNumInstr;
///Total time spent in the function
sc_time totalTime;
///Time spent exclusively in the function
sc_time exclTime;
///Used to coorectly keep track of the increment of the time, instruction count, etc.
///in recursive functions
bool alreadyExamined;
///dump these information to a string, in the command separated values (CVS) format
std::string printCsv();
///Prints the description of the informations which describe a function, in the command separated values (CVS) format
static std::string printCsvHeader();
///Empty constructor, performs the initialization of the statistics
ProfFunction();
};
}
#endif
|
/* Copyright 2017 Columbia University, SLD Group */
//
// execute.h - Robert Margelli
// execute stage header file.
//
// Division algorithm for DIV, DIVU, REM, REMU instructions. Division by zero
// and overflow semantics are compliant with the RISC-V specs (page 32).
//
#include <systemc.h>
#include "cynw_flex_channels.h"
#include "defines.hpp"
#include "globals.hpp"
#include "hl5_datatypes.hpp"
#include "syn_directives.hpp"
#ifndef __EXECUTE__H
#define __EXECUTE__H
#define BIT(_N) (1 << _N)
// Signed division quotient and remainder struct.
struct div_res_t{
sc_int<XLEN> quotient;
sc_int<XLEN> remainder;
};
// Unsigned division quotient and remainder struct.
struct u_div_res_t{
sc_uint<XLEN> quotient;
sc_uint<XLEN> remainder;
};
SC_MODULE(execute)
{
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_imm_s(sc_bv<12> imm); // Sign extend the S-type immediate field.
sc_bv<XLEN> zero_ext_zimm(sc_bv<ZIMM_SIZE> zimm); // Zero extend the zimm field for CSRRxI instructions.
sc_uint<CSR_IDX_LEN> get_csr_index(sc_bv<CSR_ADDR> csr_addr); // Get csr index given the 12-bit CSR address.
void set_csr_value(sc_uint<CSR_IDX_LEN> csr_index, sc_bv<XLEN> rs1, sc_uint<LOG2_CSR_OP_NUM> operation, sc_bv<2> rw_permission); // Perform requested CSR operation (write/set/clear).
// Divider functions
u_div_res_t udiv_func(sc_uint<XLEN> num, sc_uint<XLEN> den);
div_res_t div_func(sc_int<XLEN> num, sc_int<XLEN> den);
// Constructor
SC_CTOR(execute)
: din("din")
, dout("dout")
, fwd_exe("fwd_exe")
, clk("clk")
, rst("rst")
{
SC_CTHREAD(execute_th, clk.pos());
reset_signal_is(rst, false);
SC_CTHREAD(perf_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
HLS_FLATTEN_ARRAY(csr);
}
// Member variables
de_out_t input;
exe_out_t output;
sc_uint<XLEN> csr[CSR_NUM]; // Control and status registers.
};
#endif
|
#include <systemc.h>
#include <systemc-ams.h>
#include <config.hpp>
#include <core.hpp>
#define V_CORE ${vref}
SCA_TDF_MODULE(Core_power)
{
Core* core;
//Data from Functional Instance
sca_tdf::sc_in <double> func_signal;
//Data to Power Bus
sca_tdf::sca_out <double> voltage_state;
sca_tdf::sca_out <double> current_state;
//sca_tdf::sc_out <int> power_to_therm;
SCA_CTOR(Core_power):
func_signal("State_of_Power_From_Functional"),
voltage_state("Voltage_trace_to_Power_Bus"),
current_state("Current_trace_to_Power_Bus")
{}
void set_attributes();
void initialize();
void processing();
Core_power(){}
};
|
#include <systemc.h>
#include <systemc-ams.h>
#include <config.hpp>
SCA_TDF_MODULE(Power_bus){
//Rate 1ms
//Input Port
sca_tdf::sca_in <double> core_current;
sca_tdf::sca_in <double> core_voltage;
sca_tdf::sca_in <double> voltage_sensors[NUM_SENSORS];
sca_tdf::sca_in <double> current_sensors[NUM_SENSORS];
#if NUM_SOURCES>0
sca_tdf::sca_in <double> current_sources[NUM_SOURCES];
#endif
#if NUM_BATTERIES>0
sca_tdf::sca_out <double> current_batteries[NUM_BATTERIES];
#endif
SCA_CTOR(Power_bus):
core_current("Current_of_CPU"),
core_voltage("Voltage_of_CPU")
{}
void set_attributes();
void initialize();
void processing();
private:
double total_current = 0;
Power_bus(){}
};
|
#include <systemc.h>
#include <systemc-ams.h>
#include <config.hpp>
#include <core.hpp>
#define V_CORE ${vref}
SCA_TDF_MODULE(Core_power)
{
Core* core;
//Data from Functional Instance
sca_tdf::sc_in <double> func_signal;
//Data to Power Bus
sca_tdf::sca_out <double> voltage_state;
sca_tdf::sca_out <double> current_state;
//sca_tdf::sc_out <int> power_to_therm;
SCA_CTOR(Core_power):
func_signal("State_of_Power_From_Functional"),
voltage_state("Voltage_trace_to_Power_Bus"),
current_state("Current_trace_to_Power_Bus")
{}
void set_attributes();
void initialize();
void processing();
Core_power(){}
};
|
#include <systemc.h>
#include "freertos/portmacro.h"
#include "espintr.h"
#include "rom/ets_sys.h"
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num) {
espintrptr->alloc(cpu_no, model_num, intr_num);
}
void ets_isr_unmask(unsigned int mask) {
int cpu=xPortGetCoreID();
espintrptr->setintrmask(mask, cpu);
}
void ets_isr_mask(unsigned int mask) {
int cpu=xPortGetCoreID();
espintrptr->clrintrmask(mask, cpu);
}
|
#ifndef IPS_FILTER_TLM_CPP
#define IPS_FILTER_TLM_CPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "ips_filter_tlm.hpp"
#include "common_func.hpp"
#include "important_defines.hpp"
void ips_filter_tlm::do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address)
{
this->img_result = *(Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::result_ptr);
*data = (unsigned char) this->img_result;
//memcpy(data, Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::result_ptr, sizeof(IPS_OUT_TYPE_TB));
}
void ips_filter_tlm::do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address)
{
IPS_OUT_TYPE_TB* result = new IPS_OUT_TYPE_TB;
IPS_IN_TYPE_TB* img_window = new IPS_IN_TYPE_TB[3 * 3];
//dbgprint("[DEBUG]: data: %0d, address %0d, data_length %0d, size of char %0d", *data, address, data_length, sizeof(char));
this->img_window[address] = (IPS_IN_TYPE_TB) *data;
//dbgprint("[DEBUG]: img_window data: %0f", this->img_window[address]);
if (address == 8) {
filter(this->img_window, result);
}
}
#endif // IPS_FILTER_TLM_CPP
|
/* Copyright 2017 Columbia University, SLD Group */
//
// tb.h - Robert Margelli
// Testbench header file.
//
#ifndef __TB__H
#define __TB__H
#include <time.h>
#include <systemc.h>
#include "cynw_flex_channels.h"
#include <esc.h>
#include "hl5_datatypes.hpp"
#include "globals.hpp"
#include "defines.hpp"
SC_MODULE(tb)
{
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
// sc_in < bool > main_start;
// sc_in < bool > main_end;
// Instruction counters
sc_in < long int > icount;
sc_in < long int > j_icount;
sc_in < long int > b_icount;
sc_in < long int > m_icount;
sc_in < long int > o_icount;
sc_uint<XLEN> *imem;
sc_uint<XLEN> *dmem;
SC_HAS_PROCESS(tb);
tb(sc_module_name name, sc_uint<XLEN> imem[ICACHE_SIZE], sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, icount("icount")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, imem(imem)
, dmem(dmem)
{
SC_CTHREAD(source, clk.pos());
reset_signal_is(rst, 0);
SC_CTHREAD(sink, clk.pos());
reset_signal_is(rst, 0);
}
void source();
void sink();
double exec_start;
// double exec_main_start;
};
#endif
|
#ifndef RGB2GRAY_TLM_HPP
#define RGB2GRAY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "rgb2gray_pv_model.hpp"
#include "../src/img_target.cpp"
//Extended Unification TLM
struct rgb2gray_tlm : public Rgb2Gray, public img_target
{
rgb2gray_tlm(sc_module_name name) : Rgb2Gray((std::string(name) + "_HW_block").c_str()), img_target((std::string(name) + "_target").c_str()) {
#ifdef DISABLE_RGB_DEBUG
this->use_prints = false;
#endif //DISABLE_RGB_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // RGB2GRAY_TLM_HPP
|
#pragma once
#include "hwcore/cnn/pe.h"
#include <systemc.h>
#define debug_cout std::cout << "[" << sc_time_stamp().to_string() << "] - " << __FILE__ << " - "
template <int W, int P, int N> SC_MODULE(tb_pe) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W + 1 * W>::interface_T interface_W_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_out_T;
sc_clock clk;
sc_in<bool> iclk;
sc_signal<bool> reset;
hwcore::cnn::PE<W, P, N> pe;
sc_fifo<interface_T> xin; // in
sc_fifo<interface_W_T> win;
sc_fifo<interface_out_T> dout; // out
sc_fifo<sc_uint<16> > ctrl_acf; // out
SC_CTOR(tb_pe) : clk("clock", sc_time(10, SC_NS)), pe("pe"), xin(1), dout(1), win(1), ctrl_acf(1) {
iclk(clk);
pe.clk(clk);
pe.reset(reset);
pe.Win(win);
pe.Xin(xin);
pe.dout(dout);
pe.ctrl_acf(ctrl_acf);
SC_CTHREAD(waveform, iclk.pos());
SC_CTHREAD(monitor, iclk.pos());
}
int func(int a, int b) {
int tmpSum = (a << 16) + (b << 16);
return tmpSum;
}
void waveform() {
debug_cout << " - [waveform start]" << std::endl;
interface_W_T Wtmp_out;
interface_T Xtmp_out;
interface_T tmp_out;
reset.write(1);
for (int i = 0; i < 5; i++)
wait();
reset.write(0);
int size = 5;
int repeat = 7;
for (int r = 0; r < repeat; r++) {
ctrl_acf.write(0 | (hwcore::hf::ufixed2bv<15, 1>(1.0).to_uint() << 1));
for (int a = 0; a < size; a++) {
for (int b = 0; b < size; b++) {
Xtmp_out.data = func(a, b);
Xtmp_out.setKeep();
Xtmp_out.tlast = (a == size - 1 && b == size - 1 ? 1 : 0);
Wtmp_out.data = ((2 << 16) << 32) | (0 << 16);
Wtmp_out.setKeep();
Wtmp_out.tlast = (a == size - 1 && b == size - 1 ? 1 : 0);
debug_cout << "(waveform)[r]=[" << r << "],[a,b]=[" << a << "," << b << "][data]=[" << func(a, b)
<< "]" << std::endl;
xin.write(Xtmp_out);
win.write(Wtmp_out);
}
}
tmp_out.setEOP();
Wtmp_out.setEOP();
xin.write(tmp_out);
win.write(Wtmp_out);
// dout.write(tmp_out);
debug_cout << "(waveform)[EOP]" << std::endl;
wait();
}
Xtmp_out.data = 2 << 29;
Xtmp_out.setKeep();
Wtmp_out.data = (4 << 16) << 32;
Wtmp_out.setKeep();
ctrl_acf.write(1 | (hwcore::hf::ufixed2bv<15, 1>(1.0).to_uint() << 1)); // use ReLU
for (int i = 0; i < 20; i++) {
Wtmp_out.tlast = (i == 20 - 1 ? 1 : 0);
Xtmp_out.tlast = Wtmp_out.tlast;
xin.write(Xtmp_out);
win.write(Wtmp_out);
}
tmp_out.setEOP();
Wtmp_out.setEOP();
xin.write(tmp_out);
win.write(Wtmp_out);
debug_cout << " - [waveform done]" << std::endl;
while (true) {
wait();
}
}
void monitor() {
debug_cout << " - [waveform monitor]" << std::endl;
sc_int<W> tmp[2];
interface_out_T tmp_in;
int size = 5;
int repeat = 7;
for (int r = 0; r < repeat; r++) {
dout.read(tmp_in);
tmp_in.template getData<sc_int, W, 1>(tmp);
debug_cout << "(monitor)[r]=[" << r << "],[data]=[" << tmp[0].to_int() << "]<=>[expected][" << (200 << 16)
<< "]" << std::endl;
sc_assert((200 << 16) == tmp[0].to_int());
dout.read(tmp_in);
sc_assert(tmp_in.EOP());
debug_cout << "(monitor)[r]=[" << r << "] looking for EOP" << std::endl;
}
dout.read(tmp_in);
sc_assert(!tmp_in.EOP());
for (int i = 0; i < W; i++) {
if (i == W - 1)
sc_assert(tmp_in.data[i] == 0);
else
sc_assert(tmp_in.data[i] == 1);
}
sc_stop();
while (true) {
wait();
}
}
void monitor_vec() {}
};
|
#include <config.hpp>
#include <core.hpp>
#include <systemc.h>
SC_MODULE(Sensor_${sensor_name}_functional)
{
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory};
};
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, fossati@elet.polimi.it, fossati.l@gmail.com
*
\***************************************************************************/
#ifndef MEMORYLT_HPP
#define MEMORYLT_HPP
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_target_socket.h>
#include <boost/lexical_cast.hpp>
#include <string>
#include <trap_utils.hpp>
namespace trap{
template<unsigned int N_INITIATORS, unsigned int sockSize> class MemoryLT: public sc_module{
public:
tlm_utils::simple_target_socket<MemoryLT, sockSize> * socket[N_INITIATORS];
MemoryLT(sc_module_name name, unsigned int size, sc_time latency = SC_ZERO_TIME) :
sc_module(name), size(size), latency(latency){
for(int i = 0; i < N_INITIATORS; i++){
this->socket[i] = new tlm_utils::simple_target_socket<MemoryLT, sockSize>(("mem_socket_" + boost::lexical_cast<std::string>(i)).c_str());
this->socket[i]->register_b_transport(this, &MemoryLT::b_transport);
this->socket[i]->register_get_direct_mem_ptr(this, &MemoryLT::get_direct_mem_ptr);
this->socket[i]->register_transport_dbg(this, &MemoryLT::transport_dbg);
}
// Reset memory
this->mem = new unsigned char[this->size];
memset(this->mem, 0, size);
end_module();
}
~MemoryLT(){
delete this->mem;
for(int i = 0; i < N_INITIATORS; i++){
delete this->socket[i];
}
}
void b_transport(tlm::tlm_generic_payload& trans, sc_time& delay){
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
unsigned char* byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
if(adr > this->size){
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
std::cerr << "Error requesting address " << std::showbase << std::hex << adr << std::dec << std::endl;
return;
}
if(byt != 0){
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
return;
}
if(cmd == tlm::TLM_READ_COMMAND){
memcpy(ptr, &this->mem[adr], len);
}
else if(cmd == tlm::TLM_WRITE_COMMAND){
memcpy(&this->mem[adr], ptr, len);
}
// Use temporal decoupling: add memory latency to delay argument
delay += this->latency;
trans.set_dmi_allowed(true);
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
// TLM-2 DMI method
bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans, tlm::tlm_dmi& dmi_data){
// Allow read and write access
dmi_data.allow_read_write();
// Set other details of DMI region
dmi_data.set_dmi_ptr(this->mem);
dmi_data.set_start_address(0);
dmi_data.set_end_address(this->size);
dmi_data.set_read_latency(this->latency);
dmi_data.set_write_latency(this->latency);
return true;
}
// TLM-2 debug transaction method
unsigned int transport_dbg(tlm::tlm_generic_payload& trans){
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
// Calculate the number of bytes to be actually copied
unsigned int num_bytes = (len < this->size - adr) ? len : this->size - adr;
if(cmd == tlm::TLM_READ_COMMAND)
memcpy(ptr, &this->mem[adr], num_bytes);
else if(cmd == tlm::TLM_WRITE_COMMAND)
memcpy(&this->mem[adr], ptr, num_bytes);
return num_bytes;
}
//Method used to directly write a word into memory; it is mainly used to load the
//application program into memory
inline void write_byte_dbg(const unsigned int & address, const unsigned char & datum) throw(){
if(address >= this->size){
THROW_ERROR("Address " << std::hex << std::showbase << address << " out of memory");
}
this->mem[address] = datum;
}
private:
const sc_time latency;
unsigned int size;
unsigned char * mem;
};
};
#endif
|
#ifndef PROCESSING_ENGINE_HPP
#define PROCESSING_ENGINE_HPP
#include <systemc.h>
#include "verbose.hpp"
SC_MODULE(processing_engine_module)
{
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_function;
// PROCESS
void process(void);
// UTIL
float sigmoid(float input);
float relu(float input);
float softmax(float input);
SC_CTOR(processing_engine_module)
{
state_length = 0;
state_activation_function = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset,true);
}
};
#endif
|
#ifdef EDGE_DETECTOR_AT_EN
#ifndef SOBEL_EDGE_DETECTOR_HPP
#define SOBEL_EDGE_DETECTOR_HPP
#include <systemc.h>
#include "address_map.hpp"
SC_MODULE(Edge_Detector)
{
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1}};
const sc_int<16> sobelGradientY[3][3] = {{-1, -2, -1},
{ 0, 0, 0},
{ 1, 2, 1}};
sc_int<16> localWindow[3][3];
sc_int<16> resultSobelGradientX;
sc_int<16> resultSobelGradientY;
sc_int<16> localMultX[3][3];
sc_int<16> localMultY[3][3];
sc_event gotLocalWindow;
sc_event rd_t, wr_t;
sc_event mult_x, mult_y, sum_x, sum_y;
SC_CTOR(Edge_Detector)
{
SC_THREAD(wr);
SC_THREAD(rd);
SC_THREAD(compute_sobel_gradient_x);
SC_THREAD(compute_sobel_gradient_y);
SC_THREAD(perform_mult_gradient_x);
SC_THREAD(perform_mult_gradient_y);
SC_THREAD(perform_sum_gradient_x);
SC_THREAD(perform_sum_gradient_y);
}
virtual void write();
virtual void read();
virtual void wr();
void rd();
void compute_sobel_gradient_x();
void compute_sobel_gradient_y();
void perform_mult_gradient_x();
void perform_mult_gradient_y();
void perform_sum_gradient_x();
void perform_sum_gradient_y();
};
#endif // SOBEL_EDGE_DETECTOR_HPP
#endif // EDGE_DETECTOR_AT_EN
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, fossati@elet.polimi.it, fossati.l@gmail.com
*
\***************************************************************************/
/**
* This file contains the methods necessary to communicate with GDB in
* order to debug software running on simulators. Source code takes inspiration
* from the linux kernel (sparc-stub.c) and from ac_gdb.H in the ArchC sources
* In order to debug the remote protocol (as a help in the development of this
* stub, issue the "set debug remote 1" command in GDB)
* "set remotelogfile file" logs all the remote communication on the specified file
*/
//// **** TODO: it seeems that watchpoints are completely ignored ... :-(
//// **** TODO: sometimes segmentation fault when GDB is closed while the program is
//still running; it seems there is a race condition with the GDB thread...
#ifndef GDBSTUB_HPP
#define GDBSTUB_HPP
#include <csignal>
#ifndef SIGTRAP
#define SIGTRAP 5
#endif
#ifndef SIGQUIT
#define SIGQUIT 3
#endif
#include <systemc.h>
#include <vector>
#include "trap_utils.hpp"
#include "ABIIf.hpp"
#include "ToolsIf.hpp"
#include "instructionBase.hpp"
#include "BreakpointManager.hpp"
#include "WatchpointManager.hpp"
#include "GDBConnectionManager.hpp"
#include <boost/thread/thread.hpp>
#include <boost/thread/xtime.hpp>
#include <boost/thread/condition.hpp>
#include <boost/thread/mutex.hpp>
#include <boost/lexical_cast.hpp>
#include <boost/algorithm/string.hpp>
#include <boost/circular_buffer.hpp>
namespace trap{
template<class issueWidth> class GDBStub : public ToolsIf<issueWidth>, public MemoryToolsIf<issueWidth>, public sc_module{
public:
bool simulationPaused;
private:
enum stopType {BREAK_stop=0, WATCH_stop, STEP_stop, SEG_stop, TIMEOUT_stop, PAUSED_stop, UNK_stop};
///Thread used to send and receive responses with the GDB debugger
struct GDBThread{
GDBStub<issueWidth> &gdbStub;
GDBThread(GDBStub<issueWidth> &gdbStub) : gdbStub(gdbStub){}
void operator()(){
while(!gdbStub.isKilled){
if(gdbStub.connManager.checkInterrupt()){
gdbStub.step = 2;
}
else{
//An Error happened: First of all I have to perform some cleanup
if(!gdbStub.isKilled){
boost::mutex::scoped_lock lk(gdbStub.cleanupMutex);
gdbStub.breakManager.clearAllBreaks();
gdbStub.watchManager.clearAllWatchs();
gdbStub.step = 0;
gdbStub.isConnected = false;
}
break;
}
}
}
};
///Manages connection among the GDB target stub (this class) and
///the GDB debugger
GDBConnectionManager connManager;
///Interface for communication with the internal processor's structure
ABIIf<issueWidth> &processorInstance;
///Handles the breakpoints which have been set in the system
BreakpointManager<issueWidth> breakManager;
///Handles the watchpoints which have been set in the system
WatchpointManager<issueWidth> watchManager;
///Determines whether the processor has to halt as a consequence of a
///step command
unsigned int step;
///Keeps track of the last breakpoint encountered by this processor
Breakpoint<issueWidth> * breakReached;
///Keeps track of the last watchpoint encountered by this processor
Watchpoint<issueWidth> * watchReached;
///Specifies whether the breakpoints are enabled or not
bool breakEnabled;
///Specifies whether the watchpoints are enabled or not
bool watchEnabled;
///Specifies whether GDB server side killed the simulation
bool isKilled;
///In case we decided to run the simulation only for a limited ammount of time
///this variable contains that time
double timeToGo;
///In case we decided to jump onwards or backwards for a specified ammount of time,
///this variable contains that time
double timeToJump;
///In case the simulation is run only for a specified ammount of time, this variable
///contains the simulation time at that start time
double simStartTime;
///Specifies that we have to stop because a timeout was encountered
bool timeout;
///Event used to manage execution for a specified ammount of time
sc_event pauseEvent;
///Condition used to stop processor execution until simulation is restarted
boost::condition gdbPausedEvent;
///Mutex used to access the condition
boost::mutex global_mutex;
///Sepecifies if GDB is connected to this stub or not
bool isConnected;
///Specifies that the first run is being made
bool firstRun;
///Mutex controlling the cleanup of GDB status
boost::mutex cleanupMutex;
/********************************************************************/
///Checks if a breakpoint is present at the current address and
///in case it halts execution
#ifndef NDEBUG
inline void checkBreakpoint(const issueWidth &address){
#else
inline void checkBreakpoint(const issueWidth &address) throw(){
#endif
if(this->breakEnabled && this->breakManager.hasBreakpoint(address)){
this->breakReached = this->breakManager.getBreakPoint(address);
#ifndef NDEBUG
if(this->breakReached == NULL){
THROW_EXCEPTION("I stopped because of a breakpoint, but no breakpoint was found");
}
#endif
this->setStopped(BREAK_stop);
}
}
///If true, the system is in the step mode and, as such, execution
///needs to be stopped
inline bool goingToBreak(const issueWidth &address) const throw(){
return this->breakEnabled && this->breakManager.hasBreakpoint(address);
}
///Checks if execution must be stopped because of a step command
inline void checkStep() throw(){
if(this->step == 1){
this->step++;
}
else if(this->step == 2){
this->step = 0;
if(this->timeout){
this->timeout = false;
this->setStopped(TIMEOUT_stop);
}
else{
this->setStopped(STEP_stop);
}
}
}
///If true, the system is in the step mode and, as such, execution
///needs to be stopped
inline bool goingToStep() const throw(){
return this->step == 2;
}
///Starts the thread which will manage the connection with the
///GDB debugger
void startThread(){
GDBThread thread(*this);
boost::thread th(thread);
}
///This method is called when we need asynchronously halt the
///execution of the processor this instance of the stub is
///connected to; it is usually used when a processor is halted
///and it has to communicated to the other processor that they have
///to halt too; note that this method halts SystemC execution and
///it also starts new threads (one for each processor) which will
///deal with communication with the stub; when a continue or
///step signal is met, then the receving thread is killed. When
///all the threads are killed execution can be resumed (this means
///that all GDBs pressed the resume button)
///This method is also called at the beginning of the simulation by
///the first processor which starts execution
void setStopped(stopType stopReason = UNK_stop){
//saving current simulation time
double curSimTime = sc_time_stamp().to_double();
//Now I have to behave differently depending on whether database support is enabled or not
//if it is enabled I do not stop simulation, while if it is not enabled I have to stop simulation in
//order to be able to inspect the content of the processor - memory - etc...
//Computing the next simulation time instant
if(this->timeToGo > 0){
this->timeToGo -= (curSimTime - this->simStartTime);
if(this->timeToGo < 0)
this->timeToGo = 0;
this->simStartTime = curSimTime;
}
//Disabling break and watch points
this->breakEnabled = false;
this->watchEnabled = false;
this->awakeGDB(stopReason);
//pausing simulation
while(this->waitForRequest())
;
}
///Sends a TRAP message to GDB so that it is awaken
void awakeGDB(stopType stopReason = UNK_stop){
switch(stopReason){
case STEP_stop:{
GDBResponse response;
response.type = GDBResponse::S_rsp;
response.payload = SIGTRAP;
this->connManager.sendResponse(response);
break;}
case BREAK_stop:{
#ifndef NDEBUG
if(this->breakReached == NULL){
THROW_EXCEPTION("I stopped because of a breakpoint, but it is NULL");
}
#endif
GDBResponse response;
response.type = GDBResponse::S_rsp;
response.payload = SIGTRAP;
this->connManager.sendResponse(response);
break;}
case WATCH_stop:{
#ifndef NDEBUG
if(this->watchReached == NULL){
THROW_EXCEPTION("I stopped because of a breakpoint, but it is NULL");
}
#endif
GDBResponse response;
response.type = GDBResponse::T_rsp;
response.payload = SIGTRAP;
std::pair<std::string, unsigned int> info;
info.second = this->watchReached->address;
switch(this->watchReached->type){
case Watchpoint<issueWidth>::WRITE_watch:
info.first = "watch";
break;
case Watchpoint<issueWidth>::READ_watch:
info.first = "rwatch";
break;
case Watchpoint<issueWidth>::ACCESS_watch:
info.first = "awatch";
break;
default:
info.first = "none";
break;
}
response.size = sizeof(issueWidth);
response.info.push_back(info);
this->connManager.sendResponse(response);
break;}
case SEG_stop:{
//An error has occurred during processor execution (illelgal instruction, reading out of memory, ...);
GDBResponse response;
response.type = GDBResponse::S_rsp;
response.payload = SIGILL;
this->connManager.sendResponse(response);
break;}
case TIMEOUT_stop:{
//the simulation time specified has elapsed, so simulation halted
GDBResponse resp;
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Specified Simulation time completed - Current simulation time: " + sc_time_stamp().to_string() + " (ps)\n";
this->connManager.sendResponse(resp);
this->connManager.sendInterrupt();
break;}
case PAUSED_stop:{
//the simulation time specified has elapsed, so simulation halted
GDBResponse resp;
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Simulation Paused - Current simulation time: " + sc_time_stamp().to_string() + " (ps)\n";
this->connManager.sendResponse(resp);
this->connManager.sendInterrupt();
break;}
default:
this->connManager.sendInterrupt();
break;
}
}
///Signals to the GDB debugger that simulation ended; the error variable specifies
///if the program ended with an error
void signalProgramEnd(bool error = false){
if(!this->isKilled || error){
GDBResponse response;
//Now I just print a message to the GDB console signaling the user that the program is ending
if(error){
//I start anyway by signaling an error
GDBResponse rsp;
rsp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(rsp);
}
response.type = GDBResponse::OUTPUT_rsp;
if(error){
response.message = "\nProgram Ended With an Error\n";
}
else
response.message = "\nProgram Correctly Ended\n";
this->connManager.sendResponse(response);
//Now I really communicate to GDB that the program ended
response.type = GDBResponse::W_rsp;
if(error)
response.payload = SIGABRT;
else{
extern int exitValue;
response.payload = exitValue;
}
this->connManager.sendResponse(response);
}
}
///Waits for an incoming request by the GDB debugger and, once it
///has been received, it routes it to the appropriate handler
///Returns whether we must be listening for other incoming data or not
bool waitForRequest(){
this->simulationPaused = true;
GDBRequest req = connManager.processRequest();
this->simulationPaused = false;
switch(req.type){
case GDBRequest::QUEST_req:
//? request: it asks the target the reason why it halted
return this->reqStopReason();
break;
case GDBRequest::EXCL_req:
// ! request: it asks if extended mode is supported
return this->emptyAction(req);
break;
case GDBRequest::c_req:
//c request: Continue command
return this->cont(req.address);
break;
case GDBRequest::C_req:
//C request: Continue with signal command, currently not supported
return this->emptyAction(req);
break;
case GDBRequest::D_req:
//D request: disconnection from the remote target
return this->detach(req);
break;
case GDBRequest::g_req:
//g request: read general register
return this->readRegisters();
break;
case GDBRequest::G_req:
//G request: write general register
return this->writeRegisters(req);
break;
case GDBRequest::H_req:
//H request: multithreading stuff, not currently supported
return this->emptyAction(req);
break;
case GDBRequest::i_req:
//i request: single clock cycle step; currently it is not supported
//since it requires advancing systemc by a specified ammont of
//time equal to the clock cycle (or one of its multiple) and I still
//have to think how to know the clock cycle of the processor and
//how to awake again all the processors after simulation stopped again
return this->emptyAction(req);
break;
case GDBRequest::I_req:
//i request: signal and single clock cycle step
return this->emptyAction(req);
break;
case GDBRequest::k_req:
//i request: kill application: I simply call the sc_stop method
return this->killApp();
break;
case GDBRequest::m_req:
//m request: read memory
return this->readMemory(req);
break;
case GDBRequest::M_req:
// case GDBRequest::X_req:
//M request: write memory
return this->writeMemory(req);
break;
case GDBRequest::p_req:
//p request: register read
return this->readRegister(req);
break;
case GDBRequest::P_req:
//P request: register write
return this->writeRegister(req);
break;
case GDBRequest::q_req:
//q request: generic query
return this->genericQuery(req);
break;
case GDBRequest::s_req:
//s request: single step
return this->doStep(req.address);
break;
case GDBRequest::S_req:
//S request: single step with signal
return this->emptyAction(req);
break;
case GDBRequest::t_req:
//t request: backward search: currently not supported
return this->emptyAction(req);
break;
case GDBRequest::T_req:
//T request: thread stuff: currently not supported
return this->emptyAction(req);
break;
case GDBRequest::v_req:{
//Note that I support only the vCont packets; in particular, the only
//supported actions are continue and stop
std::size_t foundCont = req.command.find("Cont");
if(foundCont == std::string::npos){
return this->emptyAction(req);
}
if(req.command.find_last_of('?') == (req.command.size() - 1)){
// Query of the supported commands: I support only the
// c, and s commands
return this->vContQuery(req);
}
else{
req.command = req.command.substr(foundCont + 5);
std::vector<std::string> lineElements;
boost::split( lineElements, req.command, boost::is_any_of(";"));
// Actual continue/step command; note that I should have only
// one element in the vCont command (since only one thread is supported)
if(lineElements.size() != 1){
GDBResponse resp;
resp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(resp);
return t
|
rue;
}
// Here I check whether I have to issue a continue or a step command
if(lineElements[0][0] == 'c'){
return this->cont();
}
else if(lineElements[0][0] == 's'){
return this->doStep();
}
else{
GDBResponse resp;
resp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(resp);
return true;
}
}
break;}
case GDBRequest::z_req:
//z request: breakpoint/watch removal
return this->removeBreakWatch(req);
break;
case GDBRequest::Z_req:
//z request: breakpoint/watch addition
return this->addBreakWatch(req);
break;
case GDBRequest::INTR_req:
//received an iterrupt from GDB: I pause simulation and signal GDB that I stopped
return this->recvIntr();
break;
case GDBRequest::ERROR_req:
this->isConnected = false;
this->resumeExecution();
this->breakEnabled = false;
this->watchEnabled = false;
return false;
break;
default:
return this->emptyAction(req);
break;
}
}
///Method used to resume execution after GDB has issued
///the continue or step signal
void resumeExecution(){
//I'm going to restart execution, so I can again re-enable watch and break points
this->breakEnabled = true;
this->watchEnabled = true;
this->simStartTime = sc_time_stamp().to_double();
if(this->timeToGo > 0){
this->pauseEvent.notify(sc_time(this->timeToGo, SC_PS));
}
}
/** Here start all the methods to handle the different GDB requests **/
///It does nothing, it simply sends an empty string back to the
///GDB debugger
bool emptyAction(GDBRequest &req){
GDBResponse resp;
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
this->connManager.sendResponse(resp);
return true;
}
/// Queries the supported vCont commands; only the c and s commands
/// are supported
bool vContQuery(GDBRequest &req){
GDBResponse resp;
resp.type = GDBResponse::CONT_rsp;
resp.data.push_back('c');
resp.data.push_back('s');
this->connManager.sendResponse(resp);
return true;
}
///Asks for the reason why the processor is stopped
bool reqStopReason(){
this->awakeGDB();
return true;
}
///Reads the value of a register;
bool readRegister(GDBRequest &req){
GDBResponse rsp;
rsp.type = GDBResponse::REG_READ_rsp;
try{
if(req.reg < this->processorInstance.nGDBRegs()){
issueWidth regContent = this->processorInstance.readGDBReg(req.reg);
this->valueToBytes(rsp.data, regContent);
}
else{
this->valueToBytes(rsp.data, 0);
}
}
catch(...){
this->valueToBytes(rsp.data, 0);
}
this->connManager.sendResponse(rsp);
return true;
}
///Reads the value of a memory location
bool readMemory(GDBRequest &req){
GDBResponse rsp;
rsp.type = GDBResponse::MEM_READ_rsp;
for(unsigned int i = 0; i < req.length; i++){
try{
unsigned char memContent = this->processorInstance.readCharMem(req.address + i);
this->valueToBytes(rsp.data, memContent);
}
catch(...){
std::cerr << "GDB Stub: error in reading memory at address " << std::hex << std::showbase << req.address + i << std::endl;
this->valueToBytes(rsp.data, 0);
}
}
this->connManager.sendResponse(rsp);
return true;
}
bool cont(unsigned int address = 0){
if(address != 0){
this->processorInstance.setPC(address);
}
//Now, I have to restart SystemC, since the processor
//has to go on; note that actually SystemC restarts only
//after all the gdbs has issued some kind of start command
//(either a continue, a step ...)
this->resumeExecution();
return false;
}
bool detach(GDBRequest &req){
boost::mutex::scoped_lock lk(this->cleanupMutex);
//First of all I have to perform some cleanup
this->breakManager.clearAllBreaks();
this->watchManager.clearAllWatchs();
this->step = 0;
this->isConnected = false;
//Finally I can send a positive response
GDBResponse resp;
resp.type = GDBResponse::OK_rsp;
this->connManager.sendResponse(resp);
this->resumeExecution();
this->breakEnabled = false;
this->watchEnabled = false;
return false;
}
bool readRegisters(){
//I have to read all the general purpose registers and
//send their content back to GDB
GDBResponse resp;
resp.type = GDBResponse::REG_READ_rsp;
for(unsigned int i = 0; i < this->processorInstance.nGDBRegs(); i++){
try{
issueWidth regContent = this->processorInstance.readGDBReg(i);
this->valueToBytes(resp.data, regContent);
}
catch(...){
this->valueToBytes(resp.data, 0);
}
}
this->connManager.sendResponse(resp);
return true;
}
bool writeRegisters(GDBRequest &req){
std::vector<issueWidth> regContent;
this->bytesToValue(req.data, regContent);
typename std::vector<issueWidth>::iterator dataIter, dataEnd;
bool error = false;
unsigned int i = 0;
for(dataIter = regContent.begin(), dataEnd = regContent.end();
dataIter != dataEnd; dataIter++){
try{
this->processorInstance.setGDBReg(*dataIter, i);
}
catch(...){
error = true;
}
i++;
}
GDBResponse resp;
if(i != (unsigned int)this->processorInstance.nGDBRegs() || error)
resp.type = GDBResponse::ERROR_rsp;
else
resp.type = GDBResponse::OK_rsp;
this->connManager.sendResponse(resp);
return true;
}
bool writeMemory(GDBRequest &req){
bool error = false;
unsigned int bytes = 0;
std::vector<unsigned char>::iterator dataIter, dataEnd;
for(dataIter = req.data.begin(), dataEnd = req.data.end(); dataIter != dataEnd; dataIter++){
try{
this->processorInstance.writeCharMem(req.address + bytes, *dataIter);
bytes++;
}
catch(...){
std::cerr << "Error in writing in memory " << std::hex << std::showbase << (unsigned int)*dataIter << " at address " << std::hex << std::showbase << req.address + bytes << std::endl;
error = true;
break;
}
}
GDBResponse resp;
resp.type = GDBResponse::OK_rsp;
if(bytes != (unsigned int)req.length || error){
resp.type = GDBResponse::ERROR_rsp;
}
this->connManager.sendResponse(resp);
return true;
}
bool writeRegister(GDBRequest &req){
GDBResponse rsp;
if(req.reg <= this->processorInstance.nGDBRegs()){
try{
this->processorInstance.setGDBReg(req.value, req.reg);
rsp.type = GDBResponse::OK_rsp;
}
catch(...){
rsp.type = GDBResponse::ERROR_rsp;
}
}
else{
rsp.type = GDBResponse::ERROR_rsp;
}
this->connManager.sendResponse(rsp);
return true;
}
bool killApp(){
std::cerr << std::endl << "Killing the program according to GDB request" << std::endl << std::endl;
this->isKilled = true;
sc_stop();
wait();
return true;
}
bool doStep(unsigned int address = 0){
if(address != 0){
this->processorInstance.setPC(address);
}
this->step = 1;
this->resumeExecution();
return false;
}
bool recvIntr(){
boost::mutex::scoped_lock lk(this->cleanupMutex);
this->breakManager.clearAllBreaks();
this->watchManager.clearAllWatchs();
this->step = 0;
this->isConnected = false;
return true;
}
bool addBreakWatch(GDBRequest &req){
GDBResponse resp;
switch(req.value){
case 0:
case 1:
if(this->breakManager.addBreakpoint(Breakpoint<issueWidth>::HW_break, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
case 2:
if(this->watchManager.addWatchpoint(Watchpoint<issueWidth>::WRITE_watch, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
case 3:
if(this->watchManager.addWatchpoint(Watchpoint<issueWidth>::READ_watch, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
case 4:
if(this->watchManager.addWatchpoint(Watchpoint<issueWidth>::ACCESS_watch, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
default:
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
break;
}
this->connManager.sendResponse(resp);
return true;
}
bool removeBreakWatch(GDBRequest &req){
GDBResponse resp;
if(this->breakManager.removeBreakpoint(req.address) or this->watchManager.removeWatchpoint(req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(resp);
return true;
}
//Note that to add additional custom commands you simply have to extend the following chain of
//if clauses
bool genericQuery(GDBRequest &req){
//I have to determine the query packet; in case it is Rcmd I deal with it
GDBResponse resp;
if(req.command != "Rcmd"){
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
}
else{
//lets see which is the custom command being sent
std::string::size_type spacePos = req.extension.find(' ');
std::string custComm;
if(spacePos == std::string::npos)
custComm = req.extension;
else
custComm = req.extension.substr(0, spacePos);
if(custComm == "go"){
//Ok, finally I got the right command: lets see for
//how many nanoseconds I have to execute the continue
this->timeToGo = boost::lexical_cast<double>(req.extension.substr(spacePos + 1))*1e3;
if(this->timeToGo < 0){
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Please specify a positive offset";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
this->timeToGo = 0;
}
else
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "go_abs"){
//This command specify to go up to a specified simulation time; the time is specified in nanoseconds
this->timeToGo = boost::lexical_cast<double>(req.extension.substr(spacePos + 1))*1e3 - sc_time_stamp().to_double();
if(this->timeToGo < 0){
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Please specify a positive offset";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
this->timeToGo = 0;
}
else{
resp.type = GDBResponse::OK_rsp;
}
}
else if(custComm == "status"){
//Returns the current status of the STUB
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Current simulation time: " + boost::lexical_cast<std::string>((sc_time_stamp().to_default_time_units())/(sc_time(1, \
SC_US).to_default_time_units())) + " (us)\n";
if(this->timeToGo != 0)
resp.message += "Simulating for : " + boost::lexical_cast<std::string>(this->timeToGo) + " Nanoseconds\n";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "time"){
//This command is simply a query to know the current simulation time
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Current simulation time: " + boost::lexical_cast<std::string>((sc_time_stamp().to_default_time_units())/(sc_time(1, \
SC_US).to_default_time_units())) + " (us)\n";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "hist"){
//Now I have to print the last n executed instructions; lets first get such number n
resp.type = GDBResponse::OUTPUT_rsp;
#ifndef ENABLE_HISTORY
resp.message = "\nInstruction History not enabled at compile time: please reconfigure the project with the --enable-history option\n\n";
#else
unsigned int histLen = 0;
try{
histLen = boost::lexical_cast<unsigned int>(req.extension.substr(spacePos + 1));
}
catch(...){
resp.message = "\nPlease specify a correct history length\n\n";
}
if(histLen > 1000){
resp.message = "\nAt maximum 1000 instructions are kept in the history\n\n";
}
// Lets now print the history
boost::circular_buffer<HistoryInstrType> & historyQueue = processorInstance.getInstructionHistory();
std::vector<std::string> histVec;
boost::circular_buffer<HistoryInstrType>::const_reverse_iterator beg, end;
unsigned int histRead = 0;
for(histRead = 0, beg = historyQueue.rbegin(), end = historyQueue.rend(); beg != end && histRead < histLen; beg++, histRead++){
histVec.push_back(beg->toStr());
}
resp.message += "\nAddress\t\tname\t\t\tmnemonic\t\tcycle\n\n";
std::vector<std::string>::const_reverse_iterator histVecBeg, histVecEnd;
unsigned int sentLines = 0;
for(histVecBeg = histVec.rbegin(), histVecEnd = histVec.rend(); histVecBeg != histVecEnd; histVecBeg++){
resp.message += *histVecBeg + "\n";
sentLines++;
if(sentLines == 5){
sentLines = 0;
this->connManager.sendResponse(resp);
resp.message = "";
}
}
#endif
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "help"){
//This command is simply a query to know the current simulation time
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Help about the custom GDB commands available for TRAP generated simulators:\n";
resp.message += " monitor help: prints the current message\n";
resp.message += " monitor time: returns the current simulation time\n";
resp.message += " monitor status: returns the status of the simulation\n";
this->connManager.sendResponse(resp);
resp.message = " monitor hist n: prints the last n (up to a maximum of 1000) instructions\n";
resp.message += " monitor go n: after the \'continue\' command is given, it simulates for n (ns) starting from the current time\n";
resp.message += " monitor go_abs n: after the \'continue\' command is given, it simulates up to instant n (ns)\n";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else{
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
}
}
this->connManager.sendResponse(resp);
return true;
}
///Separates the bytes which form an integer value and puts them
///into an array of bytes
template <class ValueType> void valueToBytes(std::vector<char> &byteHolder, ValueType value, bool ConvertEndian = true){
if(this->processorInstance.matchEndian() || !ConvertEndian){
for(unsigned int i = 0; i < sizeof(ValueType); i++){
byteHolder.push_back((char)((value & (0x0FF << 8*i)) >> 8*i));
}
}
else{
for(int i = sizeof(ValueType) - 1; i >= 0; i--){
byteHolder.push_back((char)((value & (0x0FF << 8*i)) >> 8*i));
}
}
}
///Converts a vector of bytes into a vector of integer values
void bytesToValue(std::vector<unsigned char> &byteHolder, std::vector<issueWidth> &values){
for(unsigned int i = 0; i < byteHolder.size(); i += sizeof(issueWidth)){
issueWidth buf = 0;
for(unsigned int k = 0; k < sizeof(issueWidth); k++){
buf |= (byteHolder[i + k] << 8*k);
}
values.push_back(buf);
}
}
public:
SC_HAS_PROCESS(GDBStub);
GDBStub(ABIIf<issueWidth> &processorInstance) :
sc_module(sc_module_name("debugger")), connManager(processorInstance.matchEndian()), processorInstance(processorInstance),
step(0), breakReached(NULL), breakEnabled(true), watchEnabled(true), isKilled(false), timeout(false), isConnected(false),
timeToGo(0), timeToJump(0), simStartTime(0), firstRun(true), simulationPaused(false){
SC_METHOD(pauseMethod);
sensitive << this->pauseEvent;
dont_initialize();
end_module();
}
///Method used to pause simulation
void pauseMethod(){
this->step = 2;
this->timeout = true;
}
///Overloading of the end_of_simulation method; it can be used to execute methods
///at the end of the simulation
void end_of_simulation(){
if(this->isConnected){
this->isKilled = false;
this->signalProgramEnd();
this->isKilled = true;
}
}
///Starts the connection with the GDB client
void initialize(unsigned int port = 1500){
this->connManager.initialize(port);
this->isConnected = true;
//Now I have to listen for incoming GDB messages; this will
//be done in a new thread.
this->startThread();
}
///Method called at eve
|
ry cycle from the processor's main loop
bool newIssue(const issueWidth &curPC, const InstructionBase *curInstr) throw(){
if(!this->firstRun){
this->checkStep();
this->checkBreakpoint(curPC);
}
else{
this->firstRun = false;
this->breakEnabled = false;
this->watchEnabled = false;
while(this->waitForRequest())
;
}
return false;
}
///The debugger needs the pipeline to be empty only in case it is going to be stopped
///because, for exmple, we hitted a breakpoint or we are in step mode
bool emptyPipeline(const issueWidth &curPC) const throw(){
return !this->firstRun && (this->goingToStep() || this->goingToBreak(curPC));
}
///Method called whenever a particular address is written into memory
#ifndef NDEBUG
inline void notifyAddress(issueWidth address, unsigned int size) throw(){
#else
inline void notifyAddress(issueWidth address, unsigned int size){
#endif
if(this->watchEnabled && this->watchManager.hasWatchpoint(address, size)){
this->watchReached = this->watchManager.getWatchPoint(address, size);
#ifndef NDEBUG
if(this->watchReached == NULL){
THROW_EXCEPTION("I stopped because of a watchpoint, but no watchpoint was found");
}
#endif
this->setStopped(WATCH_stop);
}
}
};
};
#endif
|
#ifndef IPS_FILTER_AT_MODEL_HPP
#define IPS_FILTER_AT_MODEL_HPP
#ifdef IPS_DEBUG_EN
#include <iostream>
#endif // IPS_DEBUG_ENi
#ifdef IPS_DUMP_EN
#include <sstream>
#endif // IPS_DUMP_EN
#include <systemc.h>
/**
* @brief Filter module.
* It takes care of filtering a image/kernel using a median filter or an
* equivalent convolution like:
* | 1/N^2 ... 1/N^2 | | img(row - N/2, col - N/2) ... img(row + N/2, col + N/2) |
* img(row, col) = | ... ... .... | * | ... ... ... |
* | 1/N^2 ... 1/N^2 | | img(row + N/2, col - N/2) ... img(row + N/2, col + N/2) |
*
* @tparam IN - data type of the inputs
* @tparam OUT - data type of the outputs
* @tparam N - size of the kernel
*/
template <typename IN = sc_uint<8>, typename OUT = sc_uint<8>, uint8_t N = 3>
SC_MODULE(Filter)
{
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
sc_in<IN* > img_window;
sc_out<OUT > result;
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter();
};
/**
* @brief Execute the image filtering
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::exec_filter()
{
size_t i;
size_t j;
OUT result_tmp;
while (true)
{
// Wait to peform the convolution
wait(this->event);
// Default value for the result depending on the output datatype
result_tmp = static_cast<OUT >(0);
// Getting the image window to filter
IN* img_window_tmp = this->img_window.read();
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
result_tmp += this->kernel[i * N + j] * static_cast<OUT >(img_window_tmp[i * N + j]);
this->result.write(result_tmp);
}
}
/**
* @brief Filtering image
*
* @param img_window - image window to filter
* @param result - resultant pixel
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::filter()
{
this->event.notify(DELAY_TIME, SC_NS);
}
/**
* @brief Initializes a kernel of N x N with default value of 1 / (N^2)
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::init()
{
// Init a kernel of N x N with default value of 1 / (N * N)
this->kernel = new OUT[N * N];
std::fill_n(this->kernel, N * N, static_cast<OUT >(1) / static_cast<OUT >(N * N));
#ifdef IPS_DEBUG_EN
// Print the initialized kernel
SC_REPORT_INFO(this->name(), "init result");
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
std::cout << "[" << this->kernel[i * N + j] << "]";
#ifdef IPS_DUMP_EN
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
#endif // IPS_DUMP_EN
}
std::cout << std::endl;
}
#else
#ifdef IPS_DUMP_EN
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
}
}
#endif // IPS_DUMP_EN
#endif // IPS_DEBUG_EN
}
#endif // IPS_FILTER_AT_MODEL_HPP
|
#ifndef IPS_FILTER_LT_MODEL_HPP
#define IPS_FILTER_LT_MODEL_HPP
#ifdef IPS_DEBUG_EN
#include <iostream>
#endif // IPS_DEBUG_ENi
#ifdef IPS_DUMP_EN
#include <sstream>
#endif // IPS_DUMP_EN
#include <systemc.h>
#define IPS_FILTER_KERNEL_SIZE 3
#define DELAY_TIME (IPS_FILTER_KERNEL_SIZE * IPS_FILTER_KERNEL_SIZE * 1) + 4 + 2 + 1
/**
* @brief Filter module.
* It takes care of filtering a image/kernel using a median filter or an
* equivalent convolution like:
* | 1/N^2 ... 1/N^2 | | img(row - N/2, col - N/2) ... img(row + N/2, col + N/2) |
* img(row, col) = | ... ... .... | * | ... ... ... |
* | 1/N^2 ... 1/N^2 | | img(row + N/2, col - N/2) ... img(row + N/2, col + N/2) |
*
* @tparam IN - data type of the inputs
* @tparam OUT - data type of the outputs
* @tparam N - size of the kernel
*/
template <typename IN = sc_uint<8>, typename OUT = sc_uint<8>, uint8_t N = 3>
SC_MODULE(Filter)
{
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
};
/**
* @brief Execute the image filtering
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::exec_filter()
{
size_t i;
size_t j;
while (true)
{
// Wait to peform the convolution
wait(this->event);
// Default value for the result depending on the output datatype
*(this->result_ptr) = static_cast<OUT >(0);
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
*(this->result_ptr) += this->kernel[i * N + j] * this->img_window_tmp[i * N + j];
}
}
/**
* @brief Filtering image
*
* @param img_window - image window to filter
* @param result - resultant pixel
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::filter(IN* img_window, OUT* result)
{
size_t i;
size_t j;
// Default value for the result depending on the output datatype
this->result_ptr = result;
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
this->img_window_tmp[i * N + j] = static_cast<OUT >(img_window[i * N + j]);
this->event.notify(DELAY_TIME, SC_NS);
}
/**
* @brief Initializes a kernel of N x N with default value of 1 / (N^2)
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::init()
{
// Init a kernel of N x N with default value of 1 / (N * N)
this->kernel = new OUT[N * N];
std::fill_n(this->kernel, N * N, static_cast<OUT >(1) / static_cast<OUT > (N * N));
// Init image window of N x N with default value of 1 / (N * N)
this->img_window_tmp = new OUT[N * N];
#ifdef IPS_DEBUG_EN
// Print the initialized kernel
SC_REPORT_INFO(this->name(), "init result");
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
std::cout << "[" << this->kernel[i * N + j] << "]";
#ifdef IPS_DUMP_EN
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
#endif // IPS_DUMP_EN
}
std::cout << std::endl;
}
#else
#ifdef IPS_DUMP_EN
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
}
}
#endif // IPS_DUMP_EN
#endif // IPS_DEBUG_EN
}
#endif // IPS_FILTER_LT_MODEL_HPP
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: vittoriano.muttillo@guest.univaq.it *
* marco.santic@guest.univaq.it *
* luigi.pomante@univaq.it *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#include <systemc.h>
#include "../mainsystem.h"
#include <math.h>
#define cD_04_ANN_INPUTS 2 // Number of inputs
#define cD_04_ANN_OUTPUTS 1 // Number of outputs
//-----------------------------------------------------------------------------
// Physical constants
//-----------------------------------------------------------------------------
static double cD_04_I_0 = 77.3 ; // [A] Nominal current
static double cD_04_T_0 = 298.15 ; // [K] Ambient temperature
static double cD_04_R_0 = 0.01 ; // [Ω] Data-sheet R_DS_On (Drain-Source resistance in the On State)
static double cD_04_V_0 = 47.2 ; // [V] Nominal voltage
static double cD_04_Alpha = 0.002 ; // [Ω/K] Temperature coefficient of Drain-Source resistance in the On State
static double cD_04_ThermalConstant = 0.75 ;
static double cD_04_Tau = 0.02 ; // [s] Sampling period
//-----------------------------------------------------------------------------
// Status descriptors
//-----------------------------------------------------------------------------
typedef struct cD_04_DEVICE // Descriptor of the state of the device
{
double t ; // Operating temperature
double r ; // Operating Drain-Source resistance in the On State
double i ; // Operating current
double v ; // Operating voltage
double time_Ex ;
int fault ;
} cD_04_DEVICE;
static cD_04_DEVICE cD_04_device;
//-----------------------------------------------------------------------------
// Mnemonics to access the array that contains the sampled data
//-----------------------------------------------------------------------------
#define cD_04_SAMPLE_LEN 3 // Array of SAMPLE_LEN elements
#define cD_04_I_INDEX 0 // Current
#define cD_04_V_INDEX 1 // Voltage
#define cD_04_TIME_INDEX 2 // Time
///-----------------------------------------------------------------------------
// Forward references
//-----------------------------------------------------------------------------
static int cD_04_initDescriptors(cD_04_DEVICE device) ;
//static void getSample(int index, double sample[SAMPLE_LEN]) ;
static void cD_04_cleanData(int index, double sample[cD_04_SAMPLE_LEN]) ;
static double cD_04_extractFeatures(double tPrev, double iPrev, double iNow, double rPrev) ;
static void cD_04_normalize(int index, double x[cD_04_ANN_INPUTS]) ;
static double cD_04_degradationModel(double tNow) ;
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
int cD_04_initDescriptors(cD_04_DEVICE device)
{HEPSY_S(cleanData_04_id)
// for (int i = 0; i < NUM_DEV; i++)
// {
HEPSY_S(cleanData_04_id) device.t = cD_04_T_0 ; // Operating temperature = Ambient temperature
HEPSY_S(cleanData_04_id) device.r = cD_04_R_0 ; // Operating R_DS_On = Data-sheet R_DS_On
// printf("Init %d \n",i);
// }
HEPSY_S(cleanData_04_id) return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void cD_04_cleanData(int index, double sample[cD_04_SAMPLE_LEN])
{HEPSY_S(cleanData_04_id)
// the parameter "index" could be useful to retrieve the characteristics of the device
HEPSY_S(cleanData_04_id) if ( sample[cD_04_I_INDEX] < 0 )
{HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) sample[cD_04_I_INDEX] = 0 ;
HEPSY_S(cleanData_04_id) }
else if ( sample[cD_04_I_INDEX] > (2.0 * cD_04_I_0) )
{HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) sample[cD_04_I_INDEX] = (2.0 * cD_04_I_0) ;
// Postcondition: (0 <= sample[I_INDEX] <= 2.0*I_0)
HEPSY_S(cleanData_04_id) }
HEPSY_S(cleanData_04_id) if( sample[cD_04_V_INDEX] < 0 )
{HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) sample[cD_04_V_INDEX] = 0 ;
HEPSY_S(cleanData_04_id)}
else if ( sample[cD_04_V_INDEX] > (2.0 * cD_04_V_0 ) )
{HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) sample[cD_04_V_INDEX] = (2.0 * cD_04_V_0) ;
// Postcondition: (0 <= sample[V_INDEX] <= 2.0*V_0)
HEPSY_S(cleanData_04_id)}
}
//-----------------------------------------------------------------------------
// Input:
// - tPrev = temperature at previous step
// - iPrev = current at previous step
// - iNow = current at this step
// - rPrev = resistance at the previous step
// Return:
// - The new temperature
// Very simple model:
// - one constant for dissipation and heat capacity
// - temperature considered constant during the step
//-----------------------------------------------------------------------------
double cD_04_extractFeatures(double tPrev, double iPrev, double iNow, double rPrev)
{HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) double t ; // Temperature
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) double i = 0.5*(iPrev + iNow); // Average current
// printf("cD_04_extractFeatures tPrev=%f\n",tPrev);
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) t = tPrev + // Previous temperature
rPrev * (i * i) * cD_04_Tau - // Heat generated: P = I·R^2
cD_04_ThermalConstant * (tPrev - cD_04_T_0) * cD_04_Tau ; // Dissipation and heat capacity
HEPSY_S(cleanData_04_id) return( t );
}
//-----------------------------------------------------------------------------
// Input:
// - tNow: temperature at this step
// Return:
// - the resistance
// The model isn't realistic because the even the simpler law is exponential
//-----------------------------------------------------------------------------
double cD_04_degradationModel(double tNow)
{HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) double r ;
//r = R_0 + Alpha * tNow ;
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id)
HEPSY_S(cleanData_04_id) r = cD_04_R_0 * ( 2 - exp(-cD_04_Alpha*tNow) );
HEPSY_S(cleanData_04_id) return( r );
}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void cD_04_normalize(int index, double sample[cD_04_ANN_INPUTS])
{
double i ; double v ;
// Precondition: (0 <= sample[I_INDEX] <= 2*I_0) && (0 <= sample[V_INDEX] <= 2*V_0)
i = sample[cD_04_I_INDEX] <= cD_04_I_0 ? 0.0 : 1.0;
v = sample[cD_04_V_INDEX] <= cD_04_V_0 ? 0.0 : 1.0;
// Postcondition: (i in {0.0, 1.0}) and (v in {0.0, 1.0})
sample[cD_04_I_INDEX] = i ;
sample[cD_04_V_INDEX] = v ;
}
void mainsystem::cleanData_04_main()
{
// datatype for channels
sampleTimCord_cleanData_xx_payload sampleTimCord_cleanData_xx_payload_var;
cleanData_xx_ann_xx_payload cleanData_xx_ann_xx_payload_var;
//device var
uint8_t dev;
//step var
uint16_t step;
// ex_time (for extractFeatures...)
double ex_time;
//samples i and v
double sample_i;
double sample_v;
//var for samples, to re-use cleanData()
double cD_04_sample[cD_04_SAMPLE_LEN] ;
double x[cD_04_ANN_INPUTS + cD_04_ANN_OUTPUTS] ;
// NOTE: commented, should be changed param by ref...
//cD_04_initDescriptors(cD_04_device);
HEPSY_S(cleanData_04_id) cD_04_device.t = cD_04_T_0 ; // Operating temperature = Ambient temperature
HEPSY_S(cleanData_04_id) cD_04_device.r = cD_04_R_0 ; // Operating R_DS_On = Data-sheet R_DS_On
// ### added for time related dynamics
//static double cD_04_Tau = 0.02 ; // [s] Sampling period
HEPSY_S(cleanData_04_id) double cD_04_last_sample_time = 0;
//implementation
HEPSY_S(cleanData_04_id) while(1)
{HEPSY_S(cleanData_04_id)
// content
HEPSY_S(cleanData_04_id) sampleTimCord_cleanData_xx_payload_var = sampleTimCord_cleanData_04_channel->read();
HEPSY_S(cleanData_04_id) dev = sampleTimCord_cleanData_xx_payload_var.dev;
HEPSY_S(cleanData_04_id) step = sampleTimCord_cleanData_xx_payload_var.step;
HEPSY_S(cleanData_04_id) ex_time = sampleTimCord_cleanData_xx_payload_var.ex_time;
HEPSY_S(cleanData_04_id) sample_i = sampleTimCord_cleanData_xx_payload_var.sample_i;
HEPSY_S(cleanData_04_id) sample_v = sampleTimCord_cleanData_xx_payload_var.sample_v;
// cout << "cleanData_04 rcv \t dev: " << dev
// <<"\t step: " << step
// <<"\t time_ex:" << ex_time
// <<"\t i:" << sample_i
// <<"\t v:" << sample_v
// << endl;
// reconstruct sample
HEPSY_S(cleanData_04_id) cD_04_sample[cD_04_I_INDEX] = sample_i;
HEPSY_S(cleanData_04_id) cD_04_sample[cD_04_V_INDEX] = sample_v;
HEPSY_S(cleanData_04_id) cD_04_sample[cD_04_TIME_INDEX] = ex_time;
// ### C L E A N D A T A (0 <= I <= 2.0*I_0) and (0 <= V <= 2.0*V_0)
HEPSY_S(cleanData_04_id) cD_04_cleanData(dev, cD_04_sample) ;
HEPSY_S(cleanData_04_id) cD_04_device.time_Ex = cD_04_sample[cD_04_TIME_INDEX] ;
HEPSY_S(cleanData_04_id) cD_04_device.i = cD_04_sample[cD_04_I_INDEX] ;
HEPSY_S(cleanData_04_id) cD_04_device.v = cD_04_sample[cD_04_V_INDEX] ;
// ### added for time related dynamics
//static double cD_04_Tau = 0.02 ; // [s] Sampling period
HEPSY_S(cleanData_04_id) cD_04_Tau = ex_time - cD_04_last_sample_time;
HEPSY_S(cleanData_04_id) cD_04_last_sample_time = ex_time;
// ### F E A T U R E S E X T R A C T I O N (compute the temperature)
HEPSY_S(cleanData_04_id) cD_04_device.t = cD_04_extractFeatures( cD_04_device.t, // Previous temperature
cD_04_device.i, // Previous current
cD_04_sample[cD_04_I_INDEX], // Current at this step
cD_04_device.r) ; // Previous resistance
// ### D E G R A D A T I O N M O D E L (compute R_DS_On)
HEPSY_S(cleanData_04_id) cD_04_device.r = cD_04_degradationModel(cD_04_device.t) ;
// ### N O R M A L I Z E: (x[0] in {0.0, 1.0}) and (x[1] in {0.0, 1.0})
HEPSY_S(cleanData_04_id) x[0] = cD_04_device.i ;
HEPSY_S(cleanData_04_id) x[1] = cD_04_device.v ;
HEPSY_S(cleanData_04_id) cD_04_normalize(dev, x) ;
// // ### P R E D I C T (simple XOR)
// if ( annRun(index, x) != EXIT_SUCCESS ){
//prepare out data payload
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.dev = dev;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.step = step;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.ex_time = ex_time;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.device_i = cD_04_device.i;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.device_v = cD_04_device.v;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.device_t = cD_04_device.t;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.device_r = cD_04_device.r;
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.x_0 = x[0];
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.x_1 = x[1];
HEPSY_S(cleanData_04_id) cleanData_xx_ann_xx_payload_var.x_2 = x[2];
HEPSY_S(cleanData_04_id) cleanData_04_ann_04_channel->write(cleanData_xx_ann_xx_payload_var);
HEPSY_P(cleanData_04_id)
}
}
//END
|
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a stub needed for the generated interconnect, so that downstream flow
// and simulation knows where to look for it.
#ifndef GROUT_0_H
#define GROUT_0_H
#include <systemc.h>
#include <nvhls_connections.h>
#include <nvhls_packet.h>
#include <interconnect/Interconnect.hpp>
#include "interconnect_config.hpp"
#if defined(INTERCONNECT_GEN)
#include ic_header(INTERCONNECT_GEN)
#endif // if defined(INTERCONNECT_GEN)
#endif
|
#include <config.hpp>
#include <core.hpp>
#include <systemc.h>
SC_MODULE(Sensor_${sensor_name}_functional)
{
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory};
};
|
#ifndef IPS_VGA_TLM_HPP
#define IPS_VGA_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "common_func.hpp"
#include "important_defines.hpp"
#include "vga.hpp"
#include "../src/img_target.cpp"
// Extended Unification TLM
struct vga_tlm
: public vga<
IPS_BITS,
IPS_H_ACTIVE, IPS_H_FP, IPS_H_SYNC_PULSE, IPS_H_BP,
IPS_V_ACTIVE, IPS_V_FP, IPS_V_SYNC_PULSE, IPS_V_BP
>, public img_target
{
protected:
unsigned char* tmp_img;
public:
vga_tlm(sc_module_name name, bool use_prints_)
: vga<
IPS_BITS,
IPS_H_ACTIVE, IPS_H_FP, IPS_H_SYNC_PULSE, IPS_H_BP,
IPS_V_ACTIVE, IPS_V_FP, IPS_V_SYNC_PULSE, IPS_V_BP>((std::string(name) + "_HW_block").c_str()),
img_target((std::string(name) + "_target").c_str())
{
this->use_prints = use_prints_;
checkprintenableimgtar(use_prints);
set_mem_attributes(IMG_INPUT_ADDRESS_LO, IMG_INPUT_SIZE+IMG_INPUT_START_SIZE+IMG_INPUT_DONE_SIZE);
}
// Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char *&data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char *&data, unsigned int data_length, sc_dt::uint64 address);
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
unsigned char *return_mem_ptr();
};
#endif // IPS_VGA_TLM_HPP
|
#ifndef IMG_TRANSMITER_HPP
#define IMG_TRANSMITER_HPP
#include <systemc.h>
#include "address_map.hpp"
SC_MODULE(img_transmiter)
{
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_TRANSMITER_HPP
|
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (DCT) of the 8x8 image.
* 3. Each transformed 8x8 block is divided by a quantization value for each block entry.
* 4. Each quantized 8x8 block is reordered by a Zig-Zag sequence into a array of size 64.
* *5. Entropy compression by variable length encoding (huffman). Used to maximize compression. Not implemented here.
*/
#define PI 3.1415926535897932384626433832795
#define BLOCK_ROWS 8
#define BLOCK_COLS 8
SC_MODULE(jpg_output)
{
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99}};
int zigzag_index[64] = {// zigzag table
0, 1, 5, 6, 14, 15, 27, 28,
2, 4, 7, 13, 16, 26, 29, 42,
3, 8, 12, 17, 25, 30, 41, 43,
9, 11, 18, 24, 31, 40, 44, 53,
10, 19, 23, 32, 39, 45, 52, 54,
20, 22, 33, 38, 46, 51, 55, 60,
21, 34, 37, 47, 50, 56, 59, 61,
35, 36, 48, 49, 57, 58, 62, 63};
// Constructor for compressor
SC_HAS_PROCESS(jpg_output);
jpg_output(sc_module_name jpg_compressor, int im_rows = 480, int im_cols = 640) : sc_module(jpg_compressor)
{
if (im_rows % BLOCK_ROWS == 0)
{
image_rows = im_rows;
}
else
{
image_rows = (im_rows / BLOCK_ROWS + 1) * BLOCK_ROWS;
}
if (im_cols % BLOCK_COLS == 0)
{
image_cols = im_cols;
}
else
{
image_cols = (im_cols / BLOCK_COLS + 1) * BLOCK_COLS;
}
image = new double[image_rows * image_cols];
// initialize the image matrix to avoid nan
for (int i = 0; i < (image_rows * image_cols); i++)
{
image[i] = 0;
}
} // End of Constructor
//------------Code Starts Here-------------------------
void input_pixel(int pixel_value, int row, int col)
{
double *i_row = &image[row * image_cols];
i_row[col] = double(pixel_value);
}
void output_pixel(int *Pixel, int row, int col)
{
double *i_row = &image[row * image_cols];
*Pixel = int(i_row[col]);
}
void output_byte(signed char *element, int index)
{
element[index] = image[index];
}
void jpeg_compression(int *output_size)
{
// Level shift
for (int i = 0; i < (image_rows * image_cols); i++)
{
image[i] = image[i] - 128;
}
int number_of_blocks = image_rows * image_cols / (BLOCK_ROWS * BLOCK_COLS);
#ifndef USING_TLM_TB_EN
int block_output[number_of_blocks][BLOCK_ROWS * BLOCK_COLS] = {0};
int block_output_size[number_of_blocks] = {0};
#else
int **block_output = new int *[number_of_blocks];
int *block_output_size = new int[number_of_blocks];
for (int i = 0; i < number_of_blocks; i++)
{
block_output[i] = new int[BLOCK_ROWS * BLOCK_COLS];
}
for (int i = 0; i < number_of_blocks; i++)
{
block_output_size[i] = 0;
for (int j = 0; j < BLOCK_ROWS * BLOCK_COLS; j++)
{
block_output[i][j] = 0;
}
}
#endif // USING_TLM_TB_EN
int block_counter = 0;
*output_size = 0;
for (int row = 0; row < image_rows; row += BLOCK_ROWS)
{
for (int col = 0; col < image_cols; col += BLOCK_COLS)
{
// Divided the image in 8×8 blocks
dct(row, col);
quantization(row, col);
zigzag(row, col, &block_output_size[block_counter], block_output[block_counter]);
*output_size += block_output_size[block_counter] + 1;
block_counter++;
}
}
int output_counter = 0;
for (int block_index = 0; block_index < number_of_blocks; block_index++)
{
for (int out_index = 0; out_index < block_output_size[block_index]; out_index++)
{
image[output_counter] = block_output[block_index][out_index];
output_counter++;
}
image[output_counter] = eob;
output_counter++;
}
#ifdef USING_TLM_TB_EN
for (int i = 0; i < number_of_blocks; i++)
{
delete[] block_output[i];
}
delete[] block_output;
delete[] block_output_size;
#endif // USING_TLM_TB_EN
}
void dct(int row_offset, int col_offset)
{
double cos_table[BLOCK_ROWS][BLOCK_COLS];
// make the cosine table
for (int row = 0; row < BLOCK_ROWS; row++)
{
for (int col = 0; col < BLOCK_COLS; col++)
{
cos_table[row][col] = cos((((2 * row) + 1) * col * PI) / 16);
}
}
double temp = 0.0;
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
// i_row[col] = cos_table[row-row_offset][col-col_offset];
temp = 0.0;
for (int x = 0; x < 8; x++)
{
double *x_row = &image[(x + row_offset) * image_cols];
for (int y = 0; y < 8; y++)
{
temp += x_row[y + col_offset] * cos_table[x][row - row_offset] * cos_table[y][col - col_offset];
}
}
if ((row - row_offset == 0) && (col - col_offset == 0))
{
temp /= 8.0;
}
else if (((row - row_offset == 0) && (col - col_offset != 0)) || ((row - row_offset != 0) && (col - col_offset == 0)))
{
temp /= (4.0 * sqrt(2.0));
}
else
{
temp /= 4.0;
}
i_row[col] = temp;
}
}
}
void quantization(int row_offset, int col_offset)
{
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
i_row[col] = round(i_row[col] / quantificator[row - row_offset][col - col_offset]);
}
}
}
void zigzag(int row_offset, int col_offset, int *block_output_size, int *block_output)
{
int index_last_non_zero_value = 0;
// index to last non-zero in a block zigzag array
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
int temp_index = zigzag_index[(row - row_offset) * 8 + (col - col_offset)];
block_output[temp_index] = i_row[col];
if (i_row[col] != 0 && temp_index > index_last_non_zero_value)
{
index_last_non_zero_value = temp_index + 1;
}
}
}
*block_output_size = index_last_non_zero_value;
}
};
|
#ifndef IMG_RECEIVER_TLM_HPP
#define IMG_RECEIVER_TLM_HPP
#include <systemc.h>
#include "img_receiver.hpp"
#include "../src/img_target.cpp"
#include "address_map.hpp"
struct img_receiver_tlm: public img_receiver, public img_target
{
img_receiver_tlm(sc_module_name name) : img_receiver((std::string(name) + "_receiver").c_str()), img_target((std::string(name) + "_target").c_str()) {
set_mem_attributes(IMG_INPUT_ADDRESS_LO, IMG_INPUT_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_RECEIVER_TLM_HPP
|
#ifdef EDGE_DETECTOR_LT_EN
#ifndef SOBEL_EDGE_DETECTOR_HPP
#define SOBEL_EDGE_DETECTOR_HPP
#include <systemc.h>
SC_MODULE(Edge_Detector)
{
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1}};
const int sobelGradientY[3][3] = {{-1, -2, -1},
{ 0, 0, 0},
{ 1, 2, 1}};
int resultSobelGradientX;
int resultSobelGradientY;
sc_event gotLocalWindow, finishedSobelGradientX, finishedSobelGradientY;
SC_CTOR(Edge_Detector)
{
SC_THREAD(compute_sobel_gradient_x);
SC_THREAD(compute_sobel_gradient_y);
}
void set_local_window(int window[3][3]);
void compute_sobel_gradient_x();
void compute_sobel_gradient_y();
int obtain_sobel_gradient_x();
int obtain_sobel_gradient_y();
};
#endif // SOBEL_EDGE_DETECTOR_HPP
#endif // EDGE_DETECTOR_LT_EN
|
#ifndef IMG_RECEIVER_TLM_HPP
#define IMG_RECEIVER_TLM_HPP
#include <systemc.h>
#include "img_receiver.hpp"
#include "../src/img_target.cpp"
#include "address_map.hpp"
struct img_receiver_tlm: public img_receiver, public img_target
{
SC_CTOR(img_receiver_tlm): img_receiver(img_receiver::name()), img_target(img_target::name()) {
set_mem_attributes(IMG_INPUT_ADDRESS_LO, IMG_INPUT_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_RECEIVER_TLM_HPP
|
#ifndef IPS_FILTER_LT_MODEL_HPP
#define IPS_FILTER_LT_MODEL_HPP
#ifdef IPS_DEBUG_EN
#include <iostream>
#endif // IPS_DEBUG_ENi
#ifdef IPS_DUMP_EN
#include <sstream>
#endif // IPS_DUMP_EN
#include <systemc.h>
#ifdef USING_TLM_TB_EN
#include "ips_filter_defines.hpp"
#endif // USING_TLM_TB_EN
/**
* @brief Filter module.
* It takes care of filtering a image/kernel using a median filter or an
* equivalent convolution like:
* | 1/N^2 ... 1/N^2 | | img(row - N/2, col - N/2) ... img(row + N/2, col + N/2) |
* img(row, col) = | ... ... .... | * | ... ... ... |
* | 1/N^2 ... 1/N^2 | | img(row + N/2, col - N/2) ... img(row + N/2, col + N/2) |
*
* @tparam IN - data type of the inputs
* @tparam OUT - data type of the outputs
* @tparam N - size of the kernel
*/
template <typename IN = sc_uint<8>, typename OUT = sc_uint<8>, uint8_t N = 3>
SC_MODULE(Filter)
{
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
};
/**
* @brief Execute the image filtering
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::exec_filter()
{
size_t i;
size_t j;
while (true)
{
// Wait to peform the convolution
wait(this->event);
// Default value for the result depending on the output datatype
*(this->result_ptr) = static_cast<OUT >(0);
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
*(this->result_ptr) += this->kernel[i * N + j] * this->img_window_tmp[i * N + j];
}
}
/**
* @brief Filtering image
*
* @param img_window - image window to filter
* @param result - resultant pixel
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::filter(IN* img_window, OUT* result)
{
size_t i;
size_t j;
// Default value for the result depending on the output datatype
this->result_ptr = result;
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
this->img_window_tmp[i * N + j] = static_cast<OUT >(img_window[i * N + j]);
this->event.notify(DELAY_TIME, SC_NS);
}
/**
* @brief Initializes a kernel of N x N with default value of 1 / (N^2)
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::init()
{
// Init a kernel of N x N with default value of 1 / (N * N)
this->kernel = new OUT[N * N];
std::fill_n(this->kernel, N * N, static_cast<OUT >(1) / static_cast<OUT > (N * N));
// Init image window of N x N with default value of 1 / (N * N)
this->img_window_tmp = new OUT[N * N];
#ifdef IPS_DEBUG_EN
// Print the initialized kernel
SC_REPORT_INFO(this->name(), "init result");
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
std::cout << "[" << this->kernel[i * N + j] << "]";
#ifdef IPS_DUMP_EN
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
#endif // IPS_DUMP_EN
}
std::cout << std::endl;
}
#else
#ifdef IPS_DUMP_EN
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
}
}
#endif // IPS_DUMP_EN
#endif // IPS_DEBUG_EN
}
#endif // IPS_FILTER_LT_MODEL_HPP
|
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (DCT) of the 8x8 image.
* 3. Each transformed 8x8 block is divided by a quantization value for each block entry.
* 4. Each quantized 8x8 block is reordered by a Zig-Zag sequence into a array of size 64.
* *5. Entropy compression by variable length encoding (huffman). Used to maximize compression. Not implemented here.
*/
#define PI 3.1415926535897932384626433832795
#define BLOCK_ROWS 8
#define BLOCK_COLS 8
SC_MODULE (jpg_output) {
//-----------Internal variables-------------------
//const int Block_rows = 8;
//const int Block_cols = 8;
double* image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
//input variables
int pixel_value = 0;
int row = 0;
int col = 0;
//output variables
signed char *element;
int index = 0;
//compression variables
int *output_size = 0;
int quantificator[8][8] = { // quantization table
{16,11,10,16,24,40,51,61},
{12,12,14,19,26,58,60,55},
{14,13,16,24,40,57,69,56},
{14,17,22,29,51,87,80,62},
{18,22,37,56,68,109,103,77},
{24,35,55,64,81,104,113,92},
{49,64,78,87,103,121,120,101},
{72,92,95,98,112,100,103,99}};
int zigzag_index[64]={ // zigzag table
0,1,5,6,14,15,27,28,
2,4,7,13,16,26,29,42,
3,8,12,17,25,30,41,43,
9,11,18,24,31,40,44,53,
10,19,23,32,39,45,52,54,
20,22,33,38,46,51,55,60,
21,34,37,47,50,56,59,61,
35,36,48,49,57,58,62,63};
sc_event input_event, output_event, compression_event;
// Constructor for compressor
SC_HAS_PROCESS(jpg_output);
jpg_output(sc_module_name jpg_compressor, int im_rows = 480, int im_cols = 640): sc_module(jpg_compressor){
if(im_rows%BLOCK_ROWS==0) {image_rows=im_rows;}
else {image_rows=(im_rows/BLOCK_ROWS+1)*BLOCK_ROWS;}
if(im_cols%BLOCK_COLS==0) {image_cols=im_cols;}
else {image_cols=(im_cols/BLOCK_COLS+1)*BLOCK_COLS;}
image = new double[image_rows*image_cols];
//initialize the image matrix to avoid nan
for(int i=0; i<(image_rows*image_cols);i++){
image[i]=0;
}
SC_THREAD(input_operation);
SC_THREAD(output_operation);
SC_THREAD(compression_operation);
} // End of Constructor
//------------Code Starts Here-------------------------
void input_pixel(int pixel_value_local, int row_local, int col_local) {
pixel_value = pixel_value_local;
row = row_local;
col = col_local;
input_event.notify(8, SC_NS);
}
void input_operation(){
while(true) {
wait(output_event);
double* i_row = &image[row * image_cols];
i_row[col] = double(pixel_value);
}
}
//void OutputPixel(int *Pixel, int row, int col) {
// double* i_row = &image[row * image_cols];
// *Pixel = int(i_row[col]);
//}
void output_byte(signed char *element_local, int index_local) {
element = element_local;
index = index_local;
output_event.notify(8, SC_NS);
}
void output_operation(){
while(true) {
wait(output_event);
element[index] = image[index];
}
}
void jpeg_compression(int *output_size_local) {
output_size = output_size_local;
compression_event.notify(9000, SC_NS);
}
void compression_operation() {
while(true) {
wait(compression_event);
//Level shift
for(int i=0; i<(image_rows*image_cols);i++){
image[i]=image[i]-128;
}
int number_of_blocks = image_rows*image_cols/(BLOCK_ROWS*BLOCK_COLS);
int block_output[number_of_blocks][BLOCK_ROWS*BLOCK_COLS] = {0};
int block_output_size[number_of_blocks] = {0};
int block_counter = 0;
*output_size = 0;
for(int row=0; row<image_rows; row+=BLOCK_ROWS) {
double* i_row = &image[row * image_cols];
for(int col=0; col<image_cols; col+=BLOCK_COLS) { //Divided the image in 8×8 blocks
dct(row,col);
quantization(row,col);
zigzag(row,col,&block_output_size[block_counter],block_output[block_counter]);
*output_size += block_output_size[block_counter]+1;
block_counter++;
}
}
int output_counter = 0;
for(int block_index=0;block_index<number_of_blocks;block_index++){
for(int out_index=0; out_index<block_output_size[block_index];out_index++){
image[output_counter]=block_output[block_index][out_index];
output_counter++;
}
image[output_counter]=eob;
output_counter++;
}
}
}
void dct(int row_offset, int col_offset) {
double cos_table[BLOCK_ROWS][BLOCK_COLS];
for (int row = 0; row < BLOCK_ROWS; row++) //make the cosine table
{
for (int col = 0; col < BLOCK_COLS; col++) {
cos_table[row][col] = cos((((2*row)+1)*col*PI)/16);
}
}
double temp = 0.0;
for(int row=row_offset; row<row_offset+BLOCK_ROWS; row++)
{
double* i_row = &image[row * image_cols];
for(int col=col_offset; col<col_offset+BLOCK_COLS; col++) {
//i_row[col] = cos_table[row-row_offset][col-col_offset];
temp = 0.0;
for (int x = 0; x < 8; x++){
double* x_row = &image[(x+row_offset) * image_cols];
for (int y = 0; y < 8; y++) {
temp += x_row[y+col_offset] * cos_table[x][row-row_offset] * cos_table[y][col-col_offset];
}
}
if ((row-row_offset == 0) && (col-col_offset == 0)) {
temp /= 8.0;
}
else if (((row-row_offset == 0) && (col-col_offset != 0)) || ((row-row_offset != 0) && (col-col_offset == 0))){
temp /= (4.0*sqrt(2.0));
}
else {
temp /= 4.0;
}
i_row[col] = temp;
}
}
}
void quantization(int row_offset, int col_offset) {
for(int row=row_offset; row<row_offset+BLOCK_ROWS; row++)
{
double* i_row = &image[row * image_cols];
for(int col=col_offset; col<col_offset+BLOCK_COLS; col++) {
i_row[col] = round(i_row[col]/quantificator[row-row_offset][col-col_offset]);
}
}
}
void zigzag(int row_offset, int col_offset, int *block_output_size, int *block_output) {
int index_last_non_zero_value = 0; // index to last non-zero in a block zigzag array
for(int row=row_offset; row<row_offset+BLOCK_ROWS; row++)
{
double* i_row = &image[row * image_cols];
for(int col=col_offset; col<col_offset+BLOCK_COLS; col++) {
int temp_index = zigzag_index[(row-row_offset)*8+(col-col_offset)];
block_output[temp_index]=i_row[col];
if(i_row[col] !=0 && temp_index>index_last_non_zero_value) {index_last_non_zero_value = temp_index+1;}
}
}
*block_output_size = index_last_non_zero_value;
}
};
|
#include <systemc.h>
//
// Example which is using switch statement to create multiplexer
//
// .. hwt-autodoc::
//
SC_MODULE(SwitchStmHwModule) {
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.read());
break;
}
case sc_uint<3>("0b001"): {
out.write(b.read());
break;
}
case sc_uint<3>("0b010"): {
out.write(c.read());
break;
}
default:
out.write(sc_uint<1>("0b0"));
}
}
SC_CTOR(SwitchStmHwModule) {
SC_METHOD(assig_process_out);
sensitive << a << b << c << sel;
// connect ports
}
};
|
#ifndef IPS_FILTER_TLM_HPP
#define IPS_FILTER_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include "ips_filter_lt_model.hpp"
#include "../src/img_target.cpp"
#include "important_defines.hpp"
//Extended Unification TLM
struct ips_filter_tlm : public Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>, public img_target
{
SC_CTOR(ips_filter_tlm): Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>(Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::name()), img_target(img_target::name()) {
set_mem_attributes(IMG_FILTER_KERNEL_ADDRESS_LO, IMG_FILTER_KERNEL_SIZE+IMG_FILTER_OUTPUT_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
IPS_IN_TYPE_TB img_window[IPS_FILTER_KERNEL_SIZE * IPS_FILTER_KERNEL_SIZE];
IPS_OUT_TYPE_TB img_result;
};
#endif // IPS_FILTER_TLM_HPP
|
#ifndef MEMORY_TLM_HPP
#define MEMORY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../src/img_target.cpp"
#include "address_map.hpp"
//Extended Unification TLM
struct memory_tlm : public img_target
{
memory_tlm(sc_module_name name) : img_target((std::string(name) + "_target").c_str()) {
mem_array = new unsigned char[MEMORY_SIZE];
#ifdef DISABLE_MEM_DEBUG
this->use_prints = false;
#endif //DISABLE_MEM_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_write(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
unsigned char* mem_array;
sc_uint<64> mem_data;
sc_uint<24> mem_address;
sc_uint<1> mem_we;
};
#endif // MEMORY_TLM_HPP
|
#ifdef EDGE_DETECTOR_LT_EN
#ifndef SOBEL_EDGE_DETECTOR_HPP
#define SOBEL_EDGE_DETECTOR_HPP
#include <systemc.h>
SC_MODULE(Edge_Detector)
{
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1}};
const int sobelGradientY[3][3] = {{-1, -2, -1},
{ 0, 0, 0},
{ 1, 2, 1}};
int resultSobelGradientX;
int resultSobelGradientY;
sc_event gotLocalWindow, finishedSobelGradientX, finishedSobelGradientY;
SC_CTOR(Edge_Detector)
{
SC_THREAD(compute_sobel_gradient_x);
SC_THREAD(compute_sobel_gradient_y);
}
void set_local_window(int window[3][3]);
void compute_sobel_gradient_x();
void compute_sobel_gradient_y();
int obtain_sobel_gradient_x();
int obtain_sobel_gradient_y();
};
#endif // SOBEL_EDGE_DETECTOR_HPP
#endif // EDGE_DETECTOR_LT_EN
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, fossati@elet.polimi.it, fossati.l@gmail.com
*
\***************************************************************************/
#ifndef SPARSE_MEMORYAT_HPP
#define SPARSE_MEMORYAT_HPP
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <boost/lexical_cast.hpp>
#include <string>
#include <cstring>
#include <map>
#include <trap_utils.hpp>
DECLARE_EXTENDED_PHASE(internal_ph);
namespace trap{
template<unsigned int N_INITIATORS, unsigned int sockSize> class SparseMemoryAT: public sc_module{
public:
tlm_utils::simple_target_socket_tagged<SparseMemoryAT, sockSize> * socket[N_INITIATORS];
SparseMemoryAT(sc_module_name name, unsigned int size, sc_time latency = SC_ZERO_TIME) :
sc_module(name), size(size), latency(latency), transId(0),
transactionInProgress(false), m_peq(this, &SparseMemoryAT::peq_cb){
for(int i = 0; i < N_INITIATORS; i++){
this->socket[i] = new tlm_utils::simple_target_socket_tagged<SparseMemoryAT, sockSize>(("mem_socket_" + boost::lexical_cast<std::string>(i)).c_str());
this->socket[i]->register_nb_transport_fw(this, &SparseMemoryAT::nb_transport_fw, i);
this->socket[i]->register_transport_dbg(this, &SparseMemoryAT::transport_dbg, i);
}
// Reset memory
end_module();
}
~SparseMemoryAT(){
for(int i = 0; i < N_INITIATORS; i++){
delete this->socket[i];
}
}
// TLM-2 non-blocking transport method
tlm::tlm_sync_enum nb_transport_fw(int tag, tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay){
sc_dt::uint64 adr = trans.get_address();
unsigned int len = trans.get_data_length();
unsigned char* byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
// Obliged to check the transaction attributes for unsupported features
// and to generate the appropriate error response
if (byt != 0){
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
return tlm::TLM_COMPLETED;
}
// Now queue the transaction until the annotated time has elapsed
if(phase == tlm::BEGIN_REQ){
while(this->transactionInProgress){
//std::cerr << "waiting for transactionInProgress" << std::endl;
wait(this->transactionCompleted);
}
//std::cerr << "there are no transactionInProgress" << std::endl;
this->transactionInProgress = true;
}
this->transId = tag;
m_peq.notify(trans, phase, delay);
trans.set_response_status(tlm::TLM_OK_RESPONSE);
return tlm::TLM_ACCEPTED;
}
void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase){
tlm::tlm_sync_enum status;
sc_time delay;
switch (phase){
case tlm::BEGIN_REQ:
status = send_end_req(trans);
break;
case tlm::END_RESP:
//std::cerr << "tlm::END_RESP in memory peq_cb" << std::endl;
this->transactionInProgress = false;
this->transactionCompleted.notify();
break;
case tlm::END_REQ:
case tlm::BEGIN_RESP:
SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by target");
break;
default:
if (phase == internal_ph){
// Execute the read or write commands
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if(cmd == tlm::TLM_READ_COMMAND){
for(int i = 0; i < len; i++, ptr++)
*ptr = this->mem[adr + i];
}
else if(cmd == tlm::TLM_WRITE_COMMAND){
for(int i = 0; i < len; i++, ptr++)
this->mem[adr + i] = *ptr;
}
trans.set_response_status(tlm::TLM_OK_RESPONSE);
// Target must honor BEGIN_RESP/END_RESP exclusion rule
// i.e. must not send BEGIN_RESP until receiving previous END_RESP or BEGIN_REQ
send_response(trans);
//std::cerr << "Memory reading address in memory " << std::hex << std::showbase << adr << std::endl;
}
break;
}
}
tlm::tlm_sync_enum send_end_req(tlm::tlm_generic_payload& trans){
tlm::tlm_sync_enum status;
tlm::tlm_phase bw_phase;
tlm::tlm_phase int_phase = internal_ph;
// Queue the acceptance and the response with the appropriate latency
bw_phase = tlm::END_REQ;
sc_time zeroDelay = SC_ZERO_TIME;
status = (*(this->socket[transId]))->nb_transport_bw(trans, bw_phase, zeroDelay);
if (status == tlm::TLM_COMPLETED){
// Transaction aborted by the initiator
// (TLM_UPDATED cannot occur at this point in the base protocol, so need not be checked)
trans.release();
return status;
}
// Queue internal event to mark beginning of response
m_peq.notify( trans, int_phase, this->latency );
return status;
}
void send_response(tlm::tlm_generic_payload& trans){
tlm::tlm_sync_enum status;
tlm::tlm_phase bw_phase;
bw_phase = tlm::BEGIN_RESP;
sc_time zeroDelay = SC_ZERO_TIME;
status = (*(this->socket[transId]))->nb_transport_bw(trans, bw_phase, zeroDelay);
//std::cerr << "response status " << status << std::endl;
if (status == tlm::TLM_UPDATED){
// The timing annotation must be honored
m_peq.notify(trans, bw_phase, SC_ZERO_TIME);
}
else if (status == tlm::TLM_COMPLETED){
// The initiator has terminated the transaction
trans.release();
}
}
// TLM-2 debug transaction method
unsigned int transport_dbg(int tag, tlm::tlm_generic_payload& trans){
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if(cmd == tlm::TLM_READ_COMMAND){
for(int i = 0; i < len; i++, ptr++)
*ptr = this->mem[adr + i];
}
else if(cmd == tlm::TLM_WRITE_COMMAND){
for(int i = 0; i < len; i++, ptr++)
this->mem[adr + i] = *ptr;
}
return len;
}
//Method used to directly write a word into memory; it is mainly used to load the
//application program into memory
inline void write_byte_dbg(const unsigned int & address, const unsigned char & datum) throw(){
this->mem[address] = datum;
}
private:
const sc_time latency;
unsigned int size;
std::map<unsigned int, unsigned char> mem;
int transId;
bool transactionInProgress;
sc_event transactionCompleted;
tlm_utils::peq_with_cb_and_phase<SparseMemoryAT> m_peq;
};
};
#endif
|
#include <systemc.h>
#include <systemc-ams.h>
#include <config.hpp>
#define ${sensor_name}_VREF ${vref}
SCA_TDF_MODULE(Sensor_${sensor_name}_power)
{
//Data from Functional Instance
sca_tdf::sc_in <int> func_signal;
//Data to Power Bus
sca_tdf::sca_out <double> voltage_state;
sca_tdf::sca_out <double> current_state;
SCA_CTOR(Sensor_${sensor_name}_power):
func_signal("State_of_Power_From_Functional"),
voltage_state("Voltage_trace_to_Power_Bus"),
current_state("Current_trace_to_Power_Bus")
{}
void set_attributes();
void initialize();
void processing();
Sensor_${sensor_name}_power(){}
};
|
// Copyright (c) 2011-2021 Columbia University, System Level Design Group
// SPDX-License-Identifier: Apache-2.0
#ifndef __GEMM_ACCELERATOR_CONF_INFO_HPP__
#define __GEMM_ACCELERATOR_CONF_INFO_HPP__
#include <systemc.h>
//
// Configuration parameters for the accelerator.
//
class conf_info_t
{
public:
//
// constructors
//
conf_info_t()
{
/* <<--ctor-->> */
this->gemm_m = 64;
this->gemm_n = 64;
this->gemm_k = 64;
}
conf_info_t(
/* <<--ctor-args-->> */
int32_t gemm_m,
int32_t gemm_n,
int32_t gemm_k
)
{
/* <<--ctor-custom-->> */
this->gemm_m = gemm_m;
this->gemm_n = gemm_n;
this->gemm_k = gemm_k;
}
// equals operator
inline bool operator==(const conf_info_t &rhs) const
{
/* <<--eq-->> */
if (gemm_m != rhs.gemm_m) return false;
if (gemm_n != rhs.gemm_n) return false;
if (gemm_k != rhs.gemm_k) return false;
return true;
}
// assignment operator
inline conf_info_t& operator=(const conf_info_t& other)
{
/* <<--assign-->> */
gemm_m = other.gemm_m;
gemm_n = other.gemm_n;
gemm_k = other.gemm_k;
return *this;
}
// VCD dumping function
friend void sc_trace(sc_trace_file *tf, const conf_info_t &v, const std::string &NAME)
{}
// redirection operator
friend ostream& operator << (ostream& os, conf_info_t const &conf_info)
{
os << "{";
/* <<--print-->> */
os << "gemm_m = " << conf_info.gemm_m << ", ";
os << "gemm_n = " << conf_info.gemm_n << ", ";
os << "gemm_k = " << conf_info.gemm_k << "";
os << "}";
return os;
}
/* <<--params-->> */
int32_t gemm_m;
int32_t gemm_n;
int32_t gemm_k;
};
#endif // __GEMM_ACCELERATOR_CONF_INFO_HPP__
|
#ifdef RGB2GRAY_PV_EN
#ifndef RGB2GRAY_HPP
#define RGB2GRAY_HPP
#include <systemc.h>
SC_MODULE(Rgb2Gray)
{
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
};
#endif // RGB2GRAY_HPP
#endif // RGB2GRAY_PV_EN
|
/* Copyright 2017 Columbia University, SLD Group */
// memwb.h - Robert Margelli
// memory+writeback stage header file.
#ifndef __MEMWB__H
#define __MEMWB__H
#include <systemc.h>
#include "cynw_flex_channels.h"
#include "defines.hpp"
#include "globals.hpp"
#include "syn_directives.hpp"
#include "hl5_datatypes.hpp"
SC_MODULE(memwb)
{
// FlexChannel initiators
get_initiator< exe_out_t > din;
put_initiator< mem_out_t > dout;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Enable fetch
sc_in<bool> fetch_en; // Used to synchronize writeback with fetch at reset.
// Instruction cache pointer to external memory
sc_uint<XLEN> *dmem;
// Thread prototype
void memwb_th(void);
// Function prototypes.
sc_bv<XLEN> ext_sign_byte(sc_bv<BYTE> read_data); // Sign extend byte read from memory. For LB
sc_bv<XLEN> ext_unsign_byte(sc_bv<BYTE> read_data); // Zero extend byte read from memory. For LBU
sc_bv<XLEN> ext_sign_halfword(sc_bv<BYTE*2> read_data); // Sign extend half-word read from memory. For LH
sc_bv<XLEN> ext_unsign_halfword(sc_bv<BYTE*2> read_data); // Zero extend half-word read from memory. For LHU
// Constructor
SC_HAS_PROCESS(memwb);
memwb(sc_module_name name, sc_uint<XLEN> _dmem[DCACHE_SIZE])
: din("din")
, dout("dout")
, clk("clk")
, rst("rst")
, fetch_en("fetch_en")
, dmem(_dmem)
{
SC_CTHREAD(memwb_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
MAP_DCACHE;
}
// Member variables
exe_out_t input;
mem_out_t output;
sc_bv<DATA_SIZE> mem_dout; // Temporarily stores the value read from memory with a load instruction
};
#endif
|
#include <iostream>
#include <systemc.h>
int run_simple_simulation(unsigned long int stack);
|
#include<systemc.h>
#include<vector>
#include "interfaces.hpp"
#include<nana/gui/widgets/listbox.hpp>
using std::vector;
class instruction_queue: public sc_module
{
public:
sc_port<read_if> in;
sc_port<write_if_f> out;
SC_HAS_PROCESS(instruction_queue);
instruction_queue(sc_module_name name, vector<string> inst_q, nana::listbox &instr);
void main();
private:
unsigned int pc;
vector<string> instruct_queue;
nana::listbox &instructions;
};
|
/*
Problem 3 Design
*/
#include<systemc.h>
SC_MODULE(communicationInterface) {
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
};
void communicationInterface::validateData() {
cout<<"@ "<<sc_time_stamp()<<"----------Start validateData---------"<<endl;
if(reset.read() == false || clear.read() == true) {
payloadOut.write(0);
countOut.write(0);
errorOut.write(0);
return;
}
sc_uint<4> header = inData.read().range(11 , 8) , payload = inData.read().range(7 , 4);
sc_uint<1> parity = inData.read().range(0 , 0);
sc_uint<2> parityCheck = 0;
if(header == 1) {
payloadOut.write(payload);
countOut.write(countOut.read() + 1);
}
while(payload) {
parityCheck++;
payload &= payload - 1;
}
errorOut.write(errorOut.read() + (parityCheck%2 && parity ? 1 : 0));
}
|
// Copyright (c) 2011-2024 Columbia University, System Level Design Group
// SPDX-License-Identifier: MIT
#ifndef __ESP_SYSTEMC_HPP__
#define __ESP_SYSTEMC_HPP__
// Fixed point
#if defined(SC_FIXED_POINT) || defined(SC_FIXED_POINT_FAST)
// Using SystemC fixed point
#define SC_INCLUDE_FX
#include <systemc.h>
#else
// Using cynw fixed point (default)
#include <systemc.h>
#include <cynw_fixed.h>
#endif
// Channels
#ifdef __CARGO__
// Using CARGO flex channels
#include <flex_channels.hpp>
#else
// Using cynw flex channels (default)
#include <cynw_flex_channels.h>
#endif
#endif // __ESP_SYSTEMC_HPP__
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, fossati@elet.polimi.it, fossati.l@gmail.com
*
\***************************************************************************/
#ifndef MEMORYAT_HPP
#define MEMORYAT_HPP
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <boost/lexical_cast.hpp>
#include <string>
#include <cstring>
#include <trap_utils.hpp>
DECLARE_EXTENDED_PHASE(internal_ph);
namespace trap{
template<unsigned int N_INITIATORS, unsigned int sockSize> class MemoryAT: public sc_module{
public:
tlm_utils::simple_target_socket_tagged<MemoryAT, sockSize> * socket[N_INITIATORS];
MemoryAT(sc_module_name name, unsigned int size, sc_time latency = SC_ZERO_TIME) :
sc_module(name), size(size), latency(latency), transId(0),
transactionInProgress(false), m_peq(this, &MemoryAT::peq_cb){
for(int i = 0; i < N_INITIATORS; i++){
this->socket[i] = new tlm_utils::simple_target_socket_tagged<MemoryAT, sockSize>(("mem_socket_" + boost::lexical_cast<std::string>(i)).c_str());
this->socket[i]->register_nb_transport_fw(this, &MemoryAT::nb_transport_fw, i);
this->socket[i]->register_transport_dbg(this, &MemoryAT::transport_dbg, i);
}
// Reset memory
this->mem = new unsigned char[size];
memset(this->mem, 0, size);
end_module();
}
~MemoryAT(){
delete this->mem;
for(int i = 0; i < N_INITIATORS; i++){
delete this->socket[i];
}
}
// TLM-2 non-blocking transport method
tlm::tlm_sync_enum nb_transport_fw(int tag, tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay){
sc_dt::uint64 adr = trans.get_address();
unsigned int len = trans.get_data_length();
unsigned char* byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
// Obliged to check the transaction attributes for unsupported features
// and to generate the appropriate error response
if (byt != 0){
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
return tlm::TLM_COMPLETED;
}
if(adr > this->size){
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
std::cerr << "Error requesting address " << std::showbase << std::hex << adr << std::dec << std::endl;
return tlm::TLM_COMPLETED;
}
// Now queue the transaction until the annotated time has elapsed
if(phase == tlm::BEGIN_REQ){
while(this->transactionInProgress){
//std::cerr << "waiting for transactionInProgress" << std::endl;
wait(this->transactionCompleted);
}
//std::cerr << "there are no transactionInProgress" << std::endl;
this->transactionInProgress = true;
}
this->transId = tag;
m_peq.notify(trans, phase, delay);
trans.set_response_status(tlm::TLM_OK_RESPONSE);
return tlm::TLM_ACCEPTED;
}
void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase){
tlm::tlm_sync_enum status;
sc_time delay;
switch (phase){
case tlm::BEGIN_REQ:
status = send_end_req(trans);
break;
case tlm::END_RESP:
//std::cerr << "tlm::END_RESP in memory peq_cb" << std::endl;
this->transactionInProgress = false;
this->transactionCompleted.notify();
break;
case tlm::END_REQ:
case tlm::BEGIN_RESP:
SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by target");
break;
default:
if (phase == internal_ph){
// Execute the read or write commands
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if (cmd == tlm::TLM_READ_COMMAND){
memcpy(ptr, &mem[adr], len);
}
else if(cmd == tlm::TLM_WRITE_COMMAND){
memcpy(&mem[adr], ptr, len);
}
trans.set_response_status(tlm::TLM_OK_RESPONSE);
// Target must honor BEGIN_RESP/END_RESP exclusion rule
// i.e. must not send BEGIN_RESP until receiving previous END_RESP or BEGIN_REQ
send_response(trans);
//std::cerr << "Memory reading address in memory " << std::hex << std::showbase << adr << std::endl;
}
break;
}
}
tlm::tlm_sync_enum send_end_req(tlm::tlm_generic_payload& trans){
tlm::tlm_sync_enum status;
tlm::tlm_phase bw_phase;
tlm::tlm_phase int_phase = internal_ph;
// Queue the acceptance and the response with the appropriate latency
bw_phase = tlm::END_REQ;
sc_time zeroDelay = SC_ZERO_TIME;
status = (*(this->socket[transId]))->nb_transport_bw(trans, bw_phase, zeroDelay);
if (status == tlm::TLM_COMPLETED){
// Transaction aborted by the initiator
// (TLM_UPDATED cannot occur at this point in the base protocol, so need not be checked)
trans.release();
return status;
}
// Queue internal event to mark beginning of response
m_peq.notify( trans, int_phase, this->latency );
return status;
}
void send_response(tlm::tlm_generic_payload& trans){
tlm::tlm_sync_enum status;
tlm::tlm_phase bw_phase;
bw_phase = tlm::BEGIN_RESP;
sc_time zeroDelay = SC_ZERO_TIME;
status = (*(this->socket[transId]))->nb_transport_bw(trans, bw_phase, zeroDelay);
//std::cerr << "response status " << status << std::endl;
if (status == tlm::TLM_UPDATED){
// The timing annotation must be honored
m_peq.notify(trans, bw_phase, SC_ZERO_TIME);
}
else if (status == tlm::TLM_COMPLETED){
// The initiator has terminated the transaction
trans.release();
}
}
// TLM-2 debug transaction method
unsigned int transport_dbg(int tag, tlm::tlm_generic_payload& trans){
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
// Calculate the number of bytes to be actually copied
unsigned int num_bytes = (len < this->size - adr) ? len : this->size - adr;
if(cmd == tlm::TLM_READ_COMMAND){
memcpy(ptr, &mem[adr], num_bytes);
}
else if(cmd == tlm::TLM_WRITE_COMMAND){
memcpy(&mem[adr], ptr, num_bytes);
}
return num_bytes;
}
//Method used to directly write a word into memory; it is mainly used to load the
//application program into memory
inline void write_byte_dbg(const unsigned int & address, const unsigned char & datum) throw(){
if(address >= this->size){
THROW_ERROR("Address " << std::hex << std::showbase << address << " out of memory");
}
this->mem[address] = datum;
}
private:
const sc_time latency;
unsigned int size;
unsigned char * mem;
int transId;
bool transactionInProgress;
sc_event transactionCompleted;
tlm_utils::peq_with_cb_and_phase<MemoryAT> m_peq;
};
};
#endif
|
#include <systemc.h>
#include <config.hpp>
SC_MODULE(Functional_bus){
//Input Port
sc_core::sc_in <unsigned int> request_address;
sc_core::sc_in <uint8_t*> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <unsigned int> request_size;
sc_core::sc_in <uint8_t*> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_core::sc_out <uint8_t*> request_value;
sc_core::sc_out <bool> request_go;
sc_core::sc_out <int> idx_sensor;
sc_core::sc_out <unsigned int> address_out_sensor[NUM_SENSORS];
sc_core::sc_out <uint8_t*> data_out_sensor[NUM_SENSORS];
sc_core::sc_out <unsigned int> size_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> flag_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> ready_sensor[NUM_SENSORS];
SC_CTOR(Functional_bus):
request_address("Address_from_Master_to_Bus"),
request_data("Data_from_Master_to_Bus"),
flag_from_core("Flag_from_Master_to_Bus"),
request_ready("Ready_from_Master_to_Bus"),
request_value("Data_from_Bus_to_Master"),
request_go("Go_from_Bus_to_Master"),
idx_sensor("selected_sensor_from_request")
{
SC_THREAD(processing_data);
sensitive << request_ready;
for (int i = 0; i < NUM_SENSORS; i++){
sensitive << go_sensors[i];
}
}
void processing_data();
void response();
private:
int selected_sensor = 0;
Functional_bus(){}
};
|
#include <systemc.h>
#include <config.hpp>
SC_MODULE(Functional_bus){
//Input Port
sc_core::sc_in <int> request_address;
sc_core::sc_in <int> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <int> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_core::sc_out <int> request_value;
sc_core::sc_out <bool> request_go;
sc_core::sc_out <int> address_out_sensor[NUM_SENSORS];
sc_core::sc_out <int> data_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> flag_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> ready_sensor[NUM_SENSORS];
SC_CTOR(Functional_bus):
request_address("Address_from_Master_to_Bus"),
request_data("Data_from_Master_to_Bus"),
flag_from_core("Flag_from_Master_to_Bus"),
request_ready("Ready_from_Master_to_Bus"),
request_value("Data_from_Bus_to_Master"),
request_go("Go_from_Bus_to_Master")
{
SC_THREAD(processing_data);
sensitive << request_ready;
for (int i = 0; i < NUM_SENSORS; i++){
sensitive << go_sensors[i];
}
}
void processing_data();
void response();
void Set_Go(bool flag);
void Set_Slave(int address, bool flag);
private:
int selected_slave = 0;
Functional_bus(){}
};
|
#ifndef IMG_TRANSMITER_TLM_HPP
#define IMG_TRANSMITER_TLM_HPP
#include <systemc.h>
#include "img_transmiter.hpp"
#include "../src/img_target.cpp"
#include "address_map.hpp"
struct img_transmiter_tlm: public img_transmiter, public img_target
{
SC_CTOR(img_transmiter_tlm): img_transmiter(img_transmiter::name()), img_target(img_target::name()) {
set_mem_attributes(IMG_OUTPUT_ADDRESS_LO, IMG_OUTPUT_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_TRANSMITER_TLM_HPP
|
#ifndef IPS_SEQ_ITEM_AMS_HPP
#define IPS_SEQ_ITEM_AMS_HPP
#define int64 systemc_int64
#define uint64 systemc_uint64
#include <systemc.h>
#include <systemc-ams.h>
#undef int64
#undef uint64
#define int64 opencv_int64
#define uint64 opencv_uint64
#include <opencv2/opencv.hpp>
#undef int64
#undef uint64
// Image path
#define IPS_IMG_PATH_TB "../../tools/datagen/src/imgs/car_rgb_noisy_image.jpg"
/**
* @brief This class is used to generate the data for the AMS test
*
* @tparam N - the number of output bits of the digital pixel
* @tparam H_ACTIVE - output horizontal active video pixels
* @tparam H_FP - wait after the display period before the sync
* horizontal pulse
* @tparam H_SYNC_PULSE - assert HSYNC
* @tparam H_BP - wait after the sync horizontal pulse before starting
* the next display period
* @tparam V_ACTIVE - output vertical active video pixels
* @tparam V_FP - wait after the display period before the sync
* vertical pulse
* @tparam V_SYNC_PULSE - assert VSYNC
* @tparam V_BP - wait after the sync vertical pulse before starting
* the next display period
*/
template <
unsigned int N = 8,
unsigned int H_ACTIVE = 640,
unsigned int H_FP = 16,
unsigned int H_SYNC_PULSE = 96,
unsigned int H_BP = 48,
unsigned int V_ACTIVE = 480,
unsigned int V_FP = 10,
unsigned int V_SYNC_PULSE = 2,
unsigned int V_BP = 33
>
SC_MODULE(seq_item_ams)
{
protected:
cv::Mat tx_img;
public:
// Input clock
sc_core::sc_in<bool> clk;
// Counters
sc_core::sc_in<unsigned int> hcount;
sc_core::sc_in<unsigned int> vcount;
// Output pixel
sc_core::sc_out<sc_uint<N> > o_red;
sc_core::sc_out<sc_uint<N> > o_green;
sc_core::sc_out<sc_uint<N> > o_blue;
SC_CTOR(seq_item_ams)
{
// Read image
const std::string img_path = IPS_IMG_PATH_TB;
cv::Mat read_img = cv::imread(img_path, cv::IMREAD_COLOR);
// CV_8UC3 Type: 8-bit unsigned, 3 channels (e.g., for a color image)
read_img.convertTo(this->tx_img, CV_8UC3);
#ifdef IPS_DEBUG_EN
std::cout << "Loading image: " << img_path << std::endl;
#endif // IPS_DEBUG_EN
// Check if the image is loaded successfully
if (this->tx_img.empty())
{
std::cerr << "Error: Could not open or find the image!" << std::endl;
exit(EXIT_FAILURE);
}
#ifdef IPS_DEBUG_EN
std::cout << "TX image info: ";
std::cout << "rows = " << this->tx_img.rows;
std::cout << " cols = " << this->tx_img.cols;
std::cout << " channels = " << this->tx_img.channels() << std::endl;
#endif // IPS_DEBUG_EN
SC_METHOD(run);
sensitive << clk.pos();
}
void run()
{
if (this->clk.read())
{
const int IMG_ROW = static_cast<int>(this->vcount.read()) - (V_SYNC_PULSE + V_BP);
const int IMG_COL = static_cast<int>(this->hcount.read()) - (H_SYNC_PULSE + H_BP);
#ifdef IPS_DEBUG_EN
std::cout << "TX image: ";
std::cout << "row = " << IMG_ROW;
std::cout << " col = " << IMG_COL;
#endif // IPS_DEBUG_EN
if ((IMG_ROW < 0) || (IMG_COL < 0) || (IMG_ROW >= static_cast<int>(V_ACTIVE)) || (IMG_COL >= static_cast<int>(H_ACTIVE)))
{
this->o_red.write(0);
this->o_green.write(0);
this->o_blue.write(0);
#ifdef IPS_DEBUG_EN
std::cout << " dpixel = (0,0,0) " << std::endl;
#endif // IPS_DEBUG_EN
}
else
{
cv::Vec3b pixel = tx_img.at<cv::Vec3b>(IMG_ROW, IMG_COL, 0);
this->o_red.write(static_cast<sc_uint<8>>(pixel[0]));
this->o_green.write(static_cast<sc_uint<8>>(pixel[1]));
this->o_blue.write(static_cast<sc_uint<8>>(pixel[2]));
#ifdef IPS_DEBUG_EN
std::cout << " ipixel = (" << static_cast<int>(pixel[0]) << ","
<< static_cast<int>(pixel[1]) << "," << static_cast<int>(pixel[2])
<< ")" << std::endl;
#endif // IPS_DEBUG_EN
}
}
}
};
#endif // IPS_SEQ_ITEM_AMS_HPP
|
#ifndef IPS_FILTER_TLM_HPP
#define IPS_FILTER_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "ips_filter_lt_model.hpp"
#include "../src/img_target.cpp"
#include "important_defines.hpp"
//Extended Unification TLM
struct ips_filter_tlm : public Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>, public img_target
{
ips_filter_tlm(sc_module_name name) : Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>((std::string(name) + "_HW_block").c_str()), img_target((std::string(name) + "_target").c_str()) {
#ifdef DISABLE_FILTER_DEBUG
this->use_prints = false;
#endif //DISABLE_FILTER_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
IPS_IN_TYPE_TB img_window[IPS_FILTER_KERNEL_SIZE * IPS_FILTER_KERNEL_SIZE];
IPS_OUT_TYPE_TB img_result;
};
#endif // IPS_FILTER_TLM_HPP
|
#ifndef PACKET_GENERATOR_TLM_HPP
#define PACKET_GENERATOR_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <systemc-ams.h>
#include "packetGenerator.h"
#include "../src/img_target.cpp"
#include "address_map.hpp"
//Extended Unification TLM
struct packetGenerator_tlm : public packetGenerator, public img_target
{
packetGenerator_tlm(sc_module_name name, bool use_prints_, sca_core::sca_time sample_time) : packetGenerator((std::string(name) + "_AMS_HW_block").c_str(), sample_time), img_target((std::string(name) + "_target").c_str()), tmp_data_length(0) {
tmp_data = new unsigned char[IMG_OUTPUT_SIZE];
set_mem_attributes(IMG_OUTPUT_ADDRESS_LO, IMG_OUTPUT_SIZE+IMG_OUTPUT_SIZE_SIZE+IMG_OUTPUT_DONE_SIZE+IMG_OUTPUT_STATUS_SIZE);
use_prints = use_prints_;
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
unsigned int tmp_data_length;
unsigned char* tmp_data;
};
#endif // PACKET_GENERATOR_TLM_HPP
|
//-----------------------------------------------------
//Module: Image Unification (PV) Header
//By: Roger Morales Monge
//Description: Programmer's View Model of unification
//process for two images (magnitude)
//-----------------------------------------------------
#ifdef IMG_UNIFICATE_PV_EN
#ifndef IMG_UNIFICATE_HPP
#define IMG_UNIFICATE_HPP
#include <systemc.h>
#include <math.h>
SC_MODULE (img_unification_module) {
//-----------Internal Variables-----------
unsigned char x_pixel, y_pixel;
unsigned char *unificated_pixel;
//-----------Constructor-----------
SC_CTOR(img_unification_module) {
} // End of Constructor
//------------Methods------------
void unificate_pixel(int x_pixel, int y_pixel, unsigned char * unificated_pixel);
void unificate_img(unsigned char *x_img, unsigned char *y_img, unsigned char *unificated_img, int img_size, int channels);
int norm(int a, int b);
};
#endif //IMG_UNIFICATE_HPP
#endif //IMG_UNIFICATE_PV_EN
|
#ifndef IMG_SAVER_TLM_HPP
#define IMG_SAVER_TLM_HPP
#include <systemc.h>
#include "../src/img_target.cpp"
#include "address_map.hpp"
struct img_saver_tlm: public img_target
{
img_saver_tlm(sc_module_name name) : img_target((std::string(name) + "_target").c_str()) {
set_mem_attributes(IMG_SAVER_ID_ADDRESS_LO, IMG_SAVER_ID_SIZE+IMG_SAVER_START_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
int local_id;
unsigned char *img_input_ptr;
unsigned char *img_inprocess_a_ptr;
unsigned char *img_inprocess_b_ptr;
unsigned char *img_inprocess_c_ptr;
unsigned char *img_inprocess_d_ptr;
unsigned char *img_output_ptr;
unsigned char *img_output_dec_ptr;
};
#endif // IMG_SAVER_TLM_HPP
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: vittoriano.muttillo@guest.univaq.it *
* marco.santic@guest.univaq.it *
* luigi.pomante@univaq.it *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
/*
* SystemManager.cpp
*
* Created on: 07 ott 2016
* Author: daniele
*/
#include <systemc.h>
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <string.h>
#include "tl.h"
#include "pugixml.hpp"
#include "SystemManager.h"
using namespace std;
using namespace pugi;
////////////////////////////
// SBM INDEPENDENT
////////////////////////////
// Constructor
SystemManager::SystemManager()
{
VPS = generateProcessInstances();
VCH = generateChannelInstances();
VBB = generateBBInstances();
VPL = generatePhysicalLinkInstances();
mappingPS();
mappingCH();
}
// Fill process data structure VPS from xml file (application.xml)
vector<Process> SystemManager:: generateProcessInstances(){
vector<Process> vps2;
int exp_id = 0;
int processId;
pugi::xml_document doc;
pugi::xml_parse_result result = doc.load_file(APPLICATION);
xml_node instancesPS2 = doc.child("instancesPS");
for (pugi::xml_node xn_process = instancesPS2.first_child(); !xn_process.empty(); xn_process = xn_process.next_sibling()){
Process pi;
// Process Name
pi.setName(xn_process.child_value("name"));
// Process id
processId = atoi((char*) xn_process.child_value("id"));
pi.setId(processId);
// Process Priority
pi.setPriority(atoi((char*) xn_process.child_value("priority")));
// Process Criticality
pi.setCriticality(atoi((char*) xn_process.child_value("criticality")));
// Process eqGate (HW size)
xml_node eqGate = xn_process.child("eqGate");
pi.setEqGate((float)eqGate.attribute("value").as_int());
// Process dataType
pi.setDataType(atoi((char*) xn_process.child_value("dataType")));
// Process MemSize (SW Size)
xml_node memSize = xn_process.child("memSize");
xml_node codeSize = memSize.child("codeSize");
for (pugi::xml_node processorModel = codeSize.child("processorModel"); processorModel; processorModel = processorModel.next_sibling()) {
pi.setCodeSize( processorModel.attribute("name").as_string(), processorModel.attribute("value").as_int() );
}
xml_node dataSize = memSize.child("dataSize");
for (pugi::xml_node processorModel = dataSize.child("processorModel"); processorModel; processorModel = processorModel.next_sibling()) {
pi.setDataSize( processorModel.attribute("name").as_string(), processorModel.attribute("value").as_int() );
}
// Process Affinity
xml_node affinity = xn_process.child("affinity");
for (pugi::xml_node processorType = affinity.child("processorType"); processorType; processorType = processorType.next_sibling()) {
string processorType_name = processorType.attribute("name").as_string();
float affinity_value = processorType.attribute("value").as_float();
pi.setAffinity(processorType_name, affinity_value);
}
// Process Concurrency
xml_node concurrency = xn_process.child("concurrency");
for (pugi::xml_node xn_cprocessId = concurrency.child("processId"); xn_cprocessId; xn_cprocessId = xn_cprocessId.next_sibling()) {
unsigned int process_id_n = xn_cprocessId.attribute("id").as_int();
float process_concurrency_value = xn_cprocessId.attribute("value").as_float();
pi.setConcurrency(process_id_n, process_concurrency_value);
}
// Process Load
xml_node load = xn_process.child("load");
for (pugi::xml_node processorId = load.child("processorId"); processorId; processorId = processorId.next_sibling()) {
unsigned int processor_id_n = processorId.attribute("id").as_int();
float process_load_value = processorId.attribute("value").as_float();
pi.setLoad(processor_id_n, process_load_value);
}
// Process time (init)
pi.processTime = sc_time(0, SC_MS);
// Process energy (init)
pi.setEnergy(0);
// Process Communication
// TO DO
if(processId == exp_id){
vps2.push_back(pi);
exp_id++;
} else {
cout << "XML for application is corrupted\n";
exit(11);
}
}
if(exp_id != NPS){
cout << "XML for application is corrupted (NPS)\n";
exit(11);
}
doc.reset();
return vps2;
}
// Fill channel data structure VCH from xml file
vector<Channel> SystemManager:: generateChannelInstances()
{
vector<Channel> vch;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file(APPLICATION);
xml_node instancesLL = myDoc.child("instancesLL");
//channel parameters
xml_node_iterator seqChannel_it;
for (seqChannel_it=instancesLL.begin(); seqChannel_it!=instancesLL.end(); ++seqChannel_it){
xml_node_iterator channel_node_it = seqChannel_it->begin();
Channel ch;
char* temp;
// CH-NAME
string name = channel_node_it->child_value();
ch.setName(name);
// CH-ID
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int id = atoi(temp);
ch.setId(id);
// writer ID
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int w_id = atoi(temp);
ch.setW_id(w_id);
// reader ID
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int r_id = atoi(temp);
ch.setR_id(r_id);
// CH-width (logical width)
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int width = atoi(temp);
ch.setWidth(width);
ch.setNum(0);
vch.push_back(ch);
}
return vch;
}
/*
* for a given processID, increments the profiling variable
* (the number of "loops" executed by the process)
*/
void SystemManager::PS_Profiling(int processId)
{
VPS[processId].profiling++;
}
// Check if a process is allocated on a SPP
bool SystemManager::checkSPP(int processId)
{
return VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType() == "SPP";
}
// Return a subset of allocationPS by considering only processes mapped to BB with ID equal to bb_unit_id
vector<int> SystemManager::getAllocationPS_BB(int bb_id)
{
vector<int> pu_alloc;
for (unsigned int j = 2; j < allocationPS_BB.size(); j++) // 0 and 1 are the testbench
{
if (allocationPS_BB[j] == bb_id) pu_alloc.push_back(j);
}
return pu_alloc;
}
///// UPDATE XML Concurrency and Communication
void SystemManager::deleteConcXmlConCom()
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML Delete result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
xml_node processes = instancesPS.child("process");
for (int i = 0; i < NPS; i++){
xml_node concom = processes.child("concurrency");
for (pugi::xml_node processorId = concom.child("processId"); processorId; processorId = processorId.next_sibling()) {
concom.remove_child(processorId);
}
xml_node concom2 = processes.child("comunication");
for (pugi::xml_node processorId = concom2.child("rec"); processorId; processorId = processorId.next_sibling()) {
concom2.remove_child(processorId);
}
processes = processes.next_sibling();
}
xml_node instancesCH = myDoc.child("instancesLL");
xml_node processesCH = instancesCH.child("logical_link");
for (int i = 0; i < NCH; i++){
xml_node concom3 = processesCH.child("concurrency");
for (pugi::xml_node processorId = concom3.child("channelId"); processorId; processorId = processorId.next_sibling()) {
concom3.remove_child(processorId);
}
processesCH = processesCH.next_sibling();
}
myDoc.save_file("./XML/application.xml");
cout << endl;
}
void SystemManager::updateXmlConCom(float matrixCONC_PS_N[NPS][NPS], unsigned int matrixCOM[NPS][NPS], float matrixCONC_CH_N[NCH][NCH])
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
for (xml_node_iterator seqProcess_it = instancesPS.begin(); seqProcess_it != instancesPS.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_value("id"));
if (seqProcess_it->child("concurrency")){
pugi::xml_node concurrency = seqProcess_it->child("concurrency");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node conc_it = concurrency.append_child("processId");
conc_it.append_attribute("id").set_value(i);
conc_it.append_attribute("value").set_value(matrixCONC_PS_N[Id][i]);
}
}
}
else{
pugi::xml_node concurrency = seqProcess_it->append_child("concurrency");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node conc_it = concurrency.append_child("processId");
conc_it.append_attribute("id").set_value(i);
conc_it.append_attribute("value").set_value(matrixCONC_PS_N[Id][i]);
}
}
}
}
//method 2: use object/node structure
pugi::xml_node instancesCOM = myDoc.child("instancesPS");
for (pugi::xml_node_iterator seqProcess_it = instancesCOM.begin(); seqProcess_it != instancesCOM.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_value("id"));
if (seqProcess_it->child("comunication")){
pugi::xml_node comunication = seqProcess_it->child("comunication");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node com_it = comunication.append_child("rec");
com_it.append_attribute("idRec").set_value(i);
com_it.append_attribute("value").set_value(matrixCOM[Id][i]);
}
}
}
else{
pugi::xml_node comunication = seqProcess_it->append_child("comunication");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node com_it = comunication.append_child("rec");
com_it.append_attribute("idRec").set_value(i);
com_it.append_attribute("value").set_value(matrixCOM[Id][i]);
}
}
}
}
pugi::xml_node instancesLL = myDoc.child("instancesLL");
for (xml_node_iterator seqLink_it = instancesLL.begin(); seqLink_it != instancesLL.end(); ++seqLink_it){
int Id = atoi(seqLink_it->child_value("id"));
if (seqLink_it->child("concurrency")){
pugi::xml_node concurrencyL = seqLink_it->child("concurrency");
for (int i = 0; i<NCH; i++){
if (i != Id){
pugi::xml_node concL_it = concurrencyL.append_child("channelId");
concL_it.append_attribute("id").set_value(i);
concL_it.append_attribute("value").set_value(matrixCONC_CH_N[Id][i]);
}
}
}
else{
pugi::xml_node concurrencyL = seqLink_it->append_child("concurrency");
for (int i = 0; i<NCH; i++){
if (i != Id){
pugi::xml_node concL_it = concurrencyL.append_child("channelId");
concL_it.append_attribute("id").set_value(i);
concL_it.append_attribute("value").set_value(matrixCONC_CH_N[Id][i]);
}
}
}
}
cout << "Saving result: " << myDoc.save_file("./XML/application.xml") << endl;
myDoc.reset();
cout << endl;
}
#if defined(_TIMING_ENERGY_)
// Fill VBB data structure from xml file (instancesTL.xml)
vector<BasicBlock> SystemManager::generateBBInstances(){
/*****************************
* LOAD BASIC BLOCKS
*****************************/
char* temp;
vector<BasicBlock> vbb;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file("./XML/instancesTL.xml");
xml_node instancesBB = myDoc.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
xml_node_iterator BB_it = seqBB_it->begin();
BasicBlock bb;
//BB-ID
int id = atoi(BB_it->child_value());
bb.setId(id);
//BB-NAME
BB_it++;
string BBname = BB_it->child_value();
bb.setName(BBname);
//BB-TYPE
BB_it++;
string type = BB_it->child_value();
bb.setType(type);
// PROCESSING UNIT
BB_it++;
vector<ProcessingUnit> vpu;
for(xml_node child = seqBB_it->child("processingUnit");child;child= child.next_sibling("processingUnit")){
xml_node_iterator pu_it = child.begin();
ProcessingUnit pu;
//PU-NAME
string puName = pu_it->child_value();
pu.setName(puName);
//PU-ID
pu_it++;
int idPU = atoi(pu_it->child_value());
pu.setId(idPU);
//Processor Type
pu_it++;
string puType = pu_it->child_value();
pu.setProcessorType(puType);
// PU-cost
pu_it++;
float idCost = (float) atof(pu_it->child_value());
pu.setCost(idCost);
//PU-ISA
pu_it++;
string puISA = pu_it->child_value();
pu.setISA(puISA);
// PU-Frequency (MHz)
pu_it++;
float idFreq = (float) atof(pu_it->child_value());
pu.setFrequency(idFreq);
// PU-CC4CS
float** array = new float*[5];
//Int8
pu_it++;
float idCC4CSminint8 = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxint8 = (float) atof(pu_it->child_value());
//Int16
pu_it++;
float idCC4CSminint16 = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxint16 = (float) atof(pu_it->child_value());
//Int32
pu_it++;
float idCC4CSminint32 = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxint32 = (float) atof(pu_it->child_value());
//Float
pu_it++;
float idCC4CSminfloat = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxfloat = (float) atof(pu_it->child_value());
//Tot
pu_it++;
float idCC4CSmin = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmax = (float) atof(pu_it->child_value());
array[0] = new float[2];
array[0][0] = idCC4CSminint8;
array[0][1] = idCC4CSmaxint8;
array[1] = new float[2];
array[1][0] = idCC4CSminint16;
array[1][1] = idCC4CSmaxint16;
array[2] = new float[2];
array[2][0] = idCC4CSminint32;
array[2][1] = idCC4CSmaxint32;
array[3] = new float[2];
array[3][0] = idCC4CSminfloat;
array[3][1] = idCC4CSmaxfloat;
array[4] = new float[2];
array[4][0] = idCC4CSmin;
array[4][1] = idCC4CSmax;
pu.setCC4S(array);
// PU-Power (W)
pu_it++;
float idPow = (float) atof(pu_it->child_value());
pu.setPower(idPow);
// PU-MIPS
pu_it++;
float idMIPS = (float) atof(pu_it->child_value());
pu.setMIPS(idMIPS);
// PU-I4CS
pu_it++;
float idI4CSmin = (float) atof(pu_it->child_value());
pu.setI4CSmin(idI4CSmin);
pu_it++;
float idI4CSmax = (float) atof(pu_it->child_value());
pu.setI4CSmax(idI4CSmax);
// PU-Vdd (V)
pu_it++;
float idVdd = (float)atof(pu_it->child_value());
pu.setVdd(idVdd);
// PU-Idd (A)
pu_it++;
float idIdd = (float)atof(pu_it->child_value());
pu.setIdd(idIdd);
// PU-overheadCS (us)
pu_it++;
float idOver = (float)atof(pu_it->child_value());
pu.setOverheadCS(sc_time((int)idOver, SC_US));
vpu.push_back(pu);
}
// LOACL MEMORY
bb.setProcessor(vpu);
BB_it++;
xml_node instancesLM = seqBB_it->child("localMemory");
xml_node_iterator lm_it = instancesLM.begin();
//CODE SIZE
int lmCodeSize = (int)atof(lm_it->child_value());
bb.setCodeSize(lmCodeSize);
//DATA SIZE
lm_it++;
int lmDataSize = (int)atof(lm_it->child_value());
bb.setDataSize(lmDataSize);
//eQG
lm_it++;
temp = (char*)lm_it->child_value();
int lmEqG = (int)atof(temp);
bb.setEqG(lmEqG);
// Comunication
BB_it++;
xml_node instancesCU = seqBB_it->child("communicationUnit");
xml_node_iterator cu_it = instancesCU.begin();
// TO DO
// Free Running time
BB_it++;
xml_node instancesFRT = seqBB_it->child("loadEstimation");
xml_node_iterator frt_it = instancesFRT.begin();
float lmFreeRunningTime = frt_it->attribute("value").as_float();
bb.setFRT(lmFreeRunningTime);
vbb.push_back(bb);
}
return vbb;
}
#else
/*
This method generates a dummy instance of a basic block.
Each BB contains more than one processing unit inside.
*/
vector<BasicBlock> SystemManager::generateBBInstances(){
vector<BasicBlock> vbb;
for (int i = 0; i < NBB; i++){
BasicBlock bb;
//BB-ID
bb.setId(i);
//BB-NAME
bb.setName("dummy");
//BB-TYPE
bb.setType("dummy");
// PROCESSING UNIT
vector<ProcessingUnit> vpu;
for (int j = 0; j < 4; j++){ // each block contains at most 4 pu
ProcessingUnit pu;
//PU-NAME
pu.setName("dummy");
//PU-ID
int idPU = j;
pu.setId(idPU);
//Processor Type
pu.setProcessorType("dummy");
//// PU-cost
//pu.setCost(0);
//PU-ISA
pu.setISA("dummy");
// PU-Frequency (MHz)
pu.setFrequency(0);
// PU-CC4CS
float** array = new float*[5]; //TODO: eliminare **?
//Int8
float idCC4CSminint8 = 0;
float idCC4CSmaxint8 = 0;
//Int16
float idCC4CSminint16 = 0;
float idCC4CSmaxint16 = 0;
//Int32
float idCC4CSminint32 = 0;
float idCC4CSmaxint32 = 0;
//Float
float idCC4CSminfloat = 0;
float idCC4CSmaxfloat = 0;
//Tot
float idCC4CSmin = 0;
float idCC4CSmax = 0;
//TODO: ciclo con tutti 0!
array[0] = new float[2];
array[0][0] = idCC4CSminint8;
array[0][1] = idCC4CSmaxint8;
array[1] = new float[2];
array[1][0] = idCC4CSminint16;
array[1][1] = idCC4CSmaxint16;
array[2] = new float[2];
array[2][0] = idCC4CSminint32;
array[2][1] = idCC4CSmaxint32;
array[3] = new float[2];
array[3][0] = idCC4CSminfloat;
array[3][1] = idCC4CSmaxfloat;
array[4] = new float[2];
array[4][0] = idCC4CSmin;
array[4][1] = idCC4CSmax;
pu.setCC4S(array);
// PU-Power (W)
pu.setPower(0);
// PU-MIPS
float idMIPS = 0;
pu.setMIPS(idMIPS);
// PU-I4CS
fl
|
oat idI4CSmin = 0;
pu.setI4CSmin(idI4CSmin);
float idI4CSmax = 0;
pu.setI4CSmax(idI4CSmax);
// PU-Vdd (V)
float idVdd = 0;
pu.setVdd(idVdd);
// PU-Idd (A)
float idIdd = 0;
pu.setIdd(idIdd);
// PU-overheadCS (us)
float idOver = 0;
pu.setOverheadCS(sc_time((int)idOver, SC_US));
vpu.push_back(pu);
}
bb.setProcessor(vpu);
// LOCAL MEMORY
//CODE SIZE
bb.setCodeSize(0);
//DATA SIZE
bb.setDataSize(0);
//eQG
bb.setEqG(0);
// Free Running time
float lmFreeRunningTime = 0;
bb.setFRT(lmFreeRunningTime);
vbb.push_back(bb);
}
return vbb;
}
#endif
#if defined(_TIMING_ENERGY_)
// Fill link data structure VPL from xml file (instancesTL.xml)
vector<PhysicalLink> SystemManager:: generatePhysicalLinkInstances()
{
vector<PhysicalLink> VPL;
PhysicalLink l;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file("./XML/instancesTL.xml");
xml_node instancesPL = myDoc.child("instancesPL");
//link parameters
xml_node_iterator seqLink_it;
for (seqLink_it=instancesPL.begin(); seqLink_it!=instancesPL.end(); ++seqLink_it){
xml_node_iterator link_node_it = seqLink_it->begin();
char* temp;
// Link NAME
string name = link_node_it->child_value();
l.setName(name);
// Link ID
link_node_it++;
temp = (char*) link_node_it->child_value();
unsigned int id = atoi(temp);
l.setId(id);
// Link PHYSICAL WIDTH
link_node_it++;
temp = (char*) link_node_it->child_value();
unsigned int physical_width = atoi(temp);
l.setPhysicalWidth(physical_width);
// Link TCOMM
link_node_it++;
temp = (char*) link_node_it->child_value();
float tc = (float) atof(temp);
sc_time tcomm(tc, SC_MS);
l.setTcomm(tcomm);
// Link TACOMM
link_node_it++;
temp = (char*) link_node_it->child_value();
float tac = (float) atof(temp);
sc_time tacomm(tac, SC_MS);
l.setTAcomm(tacomm);
// Link BANDWIDTH
link_node_it++;
temp = (char*) link_node_it->child_value();
unsigned int bandwidth = atoi(temp);
l.setBandwidth(bandwidth);
// Link a2 (coefficient needed to compute energy of the communication)
link_node_it++;
temp = (char*) link_node_it->child_value();
float a2 = (float) atof(temp);
l.seta2(a2);
// Link a1 (coefficient needed to compute energy of the communication)
link_node_it++;
temp = (char*) link_node_it->child_value();
float a1 = (float) atof(temp);
l.seta1(a1);
VPL.push_back(l);
}
return VPL;
}
#else
vector<PhysicalLink> SystemManager::generatePhysicalLinkInstances()
{
vector<PhysicalLink> VPL;
for (int i = 0; i < NPL; i++){
PhysicalLink pl;
pl.setId(i);
pl.setName("dummy");
pl.physical_width=1; // width of the physical link
pl.tcomm=sc_time(0, SC_MS); // LP: (bandwidth / phisycal_widht = 1/sec=hz (inverto)) ( per 1000) (non sforare i 5 ms)
pl.tacomm=sc_time(0, SC_MS); // LP: tcomm * K (es:K=1)
pl.bandwidth=0; // bandwidth in bit/s
pl.a2=0; // a2 coefficient of energy curve
pl.a1=0; // a1 coefficient of energy curve
VPL.push_back(pl);
}
return VPL;
}
#endif
#if defined(_TIMING_ENERGY_)
// Fill allocationPS data structure from xml file
void SystemManager:: mappingPS()
{
int exp_id = 0;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file(MAPPING_PS_BB);
xml_node mapping = myDoc.child("mapping");
//mapping parameters (process to processor)
xml_node_iterator mapping_it;
for (mapping_it=mapping.begin(); mapping_it!=mapping.end(); ++mapping_it){
xml_node_iterator child_mapping_it = mapping_it->begin();
int processId = child_mapping_it->attribute("PSid").as_int();
//string processorName = child_mapping_it->attribute("PRname").as_string();
string bbName = child_mapping_it->attribute("BBname").as_string();
int bbId = child_mapping_it->attribute("value").as_int();
int processingunitID = child_mapping_it->attribute("PUid").as_int(); //added **************
int partitionID = child_mapping_it->attribute("PTid").as_int(); //added **************
if(processId == exp_id){
allocationPS_BB.push_back(bbId);
exp_id++;
} else {
cout << "XML for allocation is corrupted\n";
exit(11);
}
}
}
#else
void SystemManager::mappingPS(){
for (int j = 0; j<NPS; j++){
int bbId = 0;
allocationPS_BB.push_back(bbId);
}
}
#endif
#if defined(_TIMING_ENERGY_)
// Fill allocationCH_PL data structure from xml file
void SystemManager::mappingCH()
{
int exp_id = 0;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file(MAPPING_LC_PL);
xml_node mapping = myDoc.child("mapping");
//mapping parameters (channel to link)
xml_node_iterator mapping_it;
for (mapping_it=mapping.begin(); mapping_it!=mapping.end(); ++mapping_it){
xml_node_iterator child_mapping_it = mapping_it->begin();
int channelId = child_mapping_it->attribute("CHid").as_int();
string linkName = child_mapping_it->attribute("Lname").as_string();
int linkId = child_mapping_it->attribute("value").as_int();
if(channelId == exp_id){
allocationCH_PL.push_back(linkId);
exp_id++;
} else {
cout << "XML for allocation is corrupted\n";
exit(11);
}
}
}
#else
void SystemManager::mappingCH(){
for (int j = 0; j < NCH; j++){
int linkId = 0;
allocationCH_PL.push_back(linkId);
}
}
#endif
///// OTHER METHODS ////////
// Evaluate the simulated time for the execution of a statement
/*
* for a given processID, returns the simulated time
* (the time needed by processor, for the allocated process, to
* to execute a statement)
*/
sc_time SystemManager:: updateSimulatedTime(int processId)
{
// Id representing process dominant datatype
int dataType = VPS[processId].getDataType();
//*********************VPU WAS CHANGED IN VBB**********************
float CC4Smin = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
float CC4Smax = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][1]; // Average/max number of clock cycles needed by the PU to execute a C statement
// Affinity-based interpolation and round up of CC4CSaff
unsigned int CC4Saff = (unsigned int) ceil(CC4Smin + ((CC4Smax-CC4Smin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType()))));
float frequency = VBB[allocationPS_BB[processId]].getProcessors()[0].getFrequency(); // Frequency of the processor (MHz)
sc_time value((CC4Saff/(frequency*1000)), SC_MS); // Average time (ms) needed to execute a C statement
return value;
}
// The computation depends on the value setted for energyComputation (EPI or EPC)
float SystemManager:: updateEstimatedEnergy(int processId)
{
float J4CS;
float P;
if(energyComputation == "EPC") {
// EPC --> J4CS = CC4CSaff * EPC = CC4CSaff * (P/f)
// Id representing process dominant datatype
int dataType = VPS[processId].getDataType();
//I HAVE TO ADD A LOOP IN ORDER TO TAKE THE PARAMETERS OF EACH PROCESSOR (?) **********************
float CC4Smin = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
//float CC4Smin = VBB[allocationPS_BB[processId]].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
//float CC4Smax = VBB[allocationPS_BB[processId]].getCC4S()[dataType][1];
float CC4Smax = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][1];// Average/max number of clock cycles needed by the PU to execute a C statement
// Affinity-based interpolation
float CC4Saff = CC4Smin + ((CC4Smax-CC4Smin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType())));
if(this->checkSPP(processId)) {
// if the process is on a SPP (HW) --> P = Vdd * Idd (V*A = W)
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getVdd() * VBB[allocationPS_BB[processId]].getProcessors()[0].getIdd();
} else {
// if the process is on a GPP/DSP (SW) --> P (W)
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getPower();
}
// EPC = P/f (W/MHz = uJ)
float EPC = P / VBB[allocationPS_BB[processId]].getProcessors()[0].getFrequency();
J4CS = CC4Saff * EPC; // uJ
} else {
// EPI
if(this->checkSPP(processId)) {
// if the process is on a SPP (HW) --> J4CS = CC4CSaff * P * (1/f)
// Id representing process dominant datatype
int dataType = VPS[processId].getDataType();
float CC4Smin = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
float CC4Smax = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][1]; // Average/max number of clock cycles needed by the PU to execute a C statement
// Affinity-based interpolation
float CC4Saff = CC4Smin + ((CC4Smax-CC4Smin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType())));
// P = Vdd * Idd (V*A = W)
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getVdd() * VBB[allocationPS_BB[processId]].getProcessors()[0].getIdd();
J4CS = CC4Saff * (P / VBB[allocationPS_BB[processId]].getProcessors()[0].getFrequency()); // uJ
} else {
// if the process is on a GPP/DSP (SW) --> J4CS = I4CSaff * EPI = I4CSaff * (P/MIPS)
float I4CSmin = VBB[allocationPS_BB[processId]].getProcessors()[0].getI4CSmin(); // Average/min number of assembly instructions to execute a C statement
float I4CSmax = VBB[allocationPS_BB[processId]].getProcessors()[0].getI4CSmax(); // Average/max number of assembly instructions to execute a C statement
// Affinity-based interpolation
float I4CSaff = I4CSmin + ((I4CSmax-I4CSmin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType())));
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getPower(); // Watt
// EPI = P/MIPS (uJ/instr)
float EPI = P / VBB[allocationPS_BB[processId]].getProcessors()[0].getMIPS();
J4CS = I4CSaff * EPI; // uJ
}
}
return J4CS;
}
// Increase processTime for each statement
void SystemManager:: increaseSimulatedTime(int processId)
{
VPS[processId].processTime += updateSimulatedTime(processId); // Cumulated sum of the statement execution time
}
// Increase energy for each statement
void SystemManager:: increaseEstimatedEnergy(int processId)
{
VPS[processId].energy += updateEstimatedEnergy(processId); // Cumulated sum of the statement execution energy
}
// Increase processTime for the wait of the timers
void SystemManager::increaseTimer(int processId, sc_time delta)
{
VPS[processId].processTime += delta; // Cumulated sum of the statement execution time
}
// Energy XML Updates
void SystemManager::deleteConcXmlEnergy(){
char* temp;
int Id;
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML Delete result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
xml_node processes = instancesPS.child("process");
for(int i = 0; i < NPS; i++){
temp = (char*) processes.child_value("id");
Id = atoi(temp); //id process
xml_node energy = processes.child("energy");
for (pugi::xml_node processorId = energy.child("processorId"); processorId; processorId = processorId.next_sibling()) {
unsigned int processor_id_n = processorId.attribute("id").as_int();//
float process_load_value = processorId.attribute("value").as_float();//
if(allocationPS_BB[Id] == processor_id_n){
energy.remove_child(processorId);
}
}
processes = processes.next_sibling();
}
myDoc.save_file("./XML/application.xml");
cout<<endl;
/////////////////////////////////////
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
pugi::xml_node instancesBB = myDoc2.child("instancesBB");
xml_node basicBlock = instancesBB.child("basicBlock");
for(int i = 0; i < NBB; i++){
temp = (char*) basicBlock.child_value("id");
Id = atoi(temp); //id process
xml_node energyEst = basicBlock.child("energyEstimation");
for (pugi::xml_node energyTOT = energyEst.child("energyTOT"); energyTOT; energyTOT = energyTOT.next_sibling()) {
unsigned int processor_id_n = energyTOT.attribute("id").as_int();//
float energy_value = energyTOT.attribute("value").as_float();//
if(Id == allocationPS_BB[2]){
energyEst.remove_child(energyTOT);
}
}
basicBlock = basicBlock.next_sibling();
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
cout<<endl;
}
void SystemManager:: updateXmlEnergy()
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
/////////////////////// ENERGY //////////////////////////////
pugi::xml_node instancesPS2 = myDoc.child("instancesPS");
float sumEnergyTot=0;
for (xml_node_iterator seqProcess_it2=instancesPS2.begin(); seqProcess_it2!=instancesPS2.end(); ++seqProcess_it2){
int Id = atoi(seqProcess_it2->child_value("id"));
if(seqProcess_it2->child("energy")){
pugi::xml_node energy = seqProcess_it2->child("energy");
pugi::xml_node energy_it = energy.append_child("processorId");
energy_it.append_attribute("id").set_value(allocationPS_BB[Id]);
energy_it.append_attribute("value").set_value(VPS[Id].getEnergy());
}else{
pugi::xml_node energy = seqProcess_it2->append_child("energy");
pugi::xml_node energy_it = energy.append_child("processorId");
energy_it.append_attribute("id").set_value(allocationPS_BB[Id]);
energy_it.append_attribute("value").set_value(VPS[Id].getEnergy());
}
sumEnergyTot+=VPS[Id].getEnergy();
}
cout << "Saving result: " << myDoc.save_file("./XML/application.xml") << endl;
myDoc.reset();
cout<<endl;
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
xml_node instancesBB = myDoc2.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
int Id = atoi(seqBB_it->child_value("id"));
///////////////////// ENERGY ////////////////////////
if(Id == allocationPS_BB[2]){
if(seqBB_it->child("energyEstimation")){
pugi::xml_node energyEstimation = seqBB_it->child("energyEstimation");
xml_node entot_node = energyEstimation.append_child("energyTOT");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
entot_node.append_attribute("value").set_value(sumEnergyTot);
}else{
pugi::xml_node energyEstimation = seqBB_it->append_child("energyEstimation");
xml_node entot_node = energyEstimation.append_child("energyTOT");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
entot_node.append_attribute("value").set_value(sumEnergyTot);
}
}
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl;
}
// Load Metrics
sc_time SystemManager::getFRT(){
return this->FRT;
}
void SystemManager::setFRT(sc_time x){
FRT = x;
}
float* SystemManager:: loadEst(sc_time FRT_n){
for(unsigned i =2; i<VPS.size(); i++){
FRL[i] = (float) ((VPS[i].processTime/VPS[i].profiling)/(FRT_n/VPS[i].profiling)); //
}
return FRL;
}
float* SystemManager:: getFRL(){
return this->FRL;
}
// Load XML Updates
void SystemManager::deleteConcXmlLoad(){
char* temp;
int Id;
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML Delete result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
xml_node processes = instancesPS.child("process");
for(int i = 0; i < NPS; i++){
temp = (char*) processes.child_value("id");
Id = atoi(temp); //id process
xml_node load = processes.child("load");
for (pugi::xml_node processorId = load.child("processorId"); processorId; processorId = processorId.next_sibling()) {
unsigned int processor_id_n = processorId.attribute("id").as_int();//
float process_load_value = processorId.attribute("value").as_float();//
if(allocationPS_BB[Id] == processor_id_n){
load.remove_child(processorId);
}
}
/* xml_node WCET = processes.child("WCET");
for (pugi::xml_node processorId = WCET.child("processorId"); processorId; processorId = processorId.next_sibling()) {
WCET.remove_child(processorId);
}
xml_node Period = processes.child("Period");
for (pugi::xml_node processorId = Period.child("processorId"); processorId; processorId = processorId.next_sibling()) {
Period.remove_child(processorId);
}
xml_node Deadline = processes.child("Deadline");
for (pugi::xml_node processorId = Deadline.child("processorId"); processorId; processorId = processorId.next_sibling()) {
Deadline.remove_child(processorId);
} */
processes = processes.next_sibling();
}
myDoc.save_file("./XML/application.xml");
cout<<endl;
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
pugi::xml_node instancesBB = myDoc2.child("instancesBB");
xml_node basicBlock = instancesBB.child("basicBlock");
for(int i = 0; i < NBB; i++){
temp = (char*) basicBlock.child_value("id");
Id = atoi(temp); //id process
xml_node loadEst = basicBlock.child("loadEstimation");
for (pugi::xml_node loadTOT = loadEst.child("FreeRunningTime"); loadTOT; loadTOT = loadTOT.next_sibling()) {
unsigned int processor_id_n = loadTOT.attribute("id").as_int();//
float energy_value = loadTOT.attribute("value").as_float();//
if(Id == allocationPS_BB[2]){
loadEst.remove_child(loadTOT);
}
}
basicBlock = basicBlock.next_sibling();
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl;
}
void SystemManager:: updateXmlLoad()
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
for (xml_node_iterator seqProcess_it=instancesPS.begin(); seqProcess_it!=instancesPS.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_value("id"));
///////////////////// LOAD ////////////////////////////
if(seqProcess_it->child("load")){
pugi::xml_node load = seqProcess_it->child("load");
pugi::xml_node load_it = load.append_child("processorId");
load_it.append_attribute("id").set_value(allocationPS_BB[Id]);
load_it.append_attribute("value").set_value(FRL[Id]);
}else{
pugi::xml_node load = seqProcess_it->append_child("load");
pugi::xml_node load_it = load.append_child("processorId");
load_it.append_attribute("id").set_value(allocationPS_BB[Id]);
load_it.append_attribute("value").set_value(FRL[Id]);
}
}
/////////////////////// WCET //////////////////////////////
////method 2: use
|
object/node structure
//pugi::xml_node instancesPS2 = myDoc.child("instancesPS");
//for (pugi::xml_node_iterator seqProcess_it=instancesPS2.begin(); seqProcess_it!=instancesPS2.end(); ++seqProcess_it){
// int Id = atoi(seqProcess_it->child_value("id"));
//
// if(seqProcess_it->child("WCET")){
// pugi::xml_node comunication = seqProcess_it->child("WCET");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node wcet_it = comunication.append_child("processorId");
// double wcet_task = (VPS[Id].processTime.to_seconds());
// wcet_it.append_attribute("id").set_value(i);
// wcet_it.append_attribute("value").set_value((wcet_task/VPS[Id].profiling)*1000000.0);
// }
// }
// }else{
// pugi::xml_node WCET = seqProcess_it->append_child("WCET");
// for (int i=0; i<VPU.size(); i++){
// if(i!=Id){
// pugi::xml_node wcet_it = WCET.append_child("processorId");
// double wcet_task = (VPS[Id].processTime.to_seconds());
// wcet_it.append_attribute("id").set_value(i);
// wcet_it.append_attribute("value").set_value((wcet_task/VPS[Id].profiling)*1000000.0);
// }
// }
// }
//}
/////////////////////// PERIOD //////////////////////////////
//pugi::xml_node instancesPS3 = myDoc.child("instancesPS");
//for (xml_node_iterator seqLink_it=instancesPS3.begin(); seqLink_it!=instancesPS3.end(); ++seqLink_it){
// int Id = atoi(seqLink_it->child_value("id"));
//
// if(seqLink_it->child("Period")){
// pugi::xml_node Period = seqLink_it->child("Period");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node period_it = Period.append_child("processorId");
// period_it.append_attribute("id").set_value(i);
// double period_value = (FRT.to_seconds());
// period_it.append_attribute("value").set_value((period_value/VPS[Id].profiling)*1000000.0);
// }
// }
// }else{
// pugi::xml_node Period = seqLink_it->append_child("Period");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node period_it = Period.append_child("processorId");
// period_it.append_attribute("id").set_value(i);
// double period_value = (FRT.to_seconds());
// period_it.append_attribute("value").set_value((period_value/VPS[Id].profiling)*1000000.0);
// }
// }
// }
//}
///////////////////////// DEADLINE //////////////////////////////
// pugi::xml_node instancesPS4 = myDoc.child("instancesPS");
//for (xml_node_iterator seqLink_it=instancesPS4.begin(); seqLink_it!=instancesPS4.end(); ++seqLink_it){
// int Id = atoi(seqLink_it->child_value("id"));
// if(seqLink_it->child("Deadline")){
// pugi::xml_node Deadline = seqLink_it->child("Deadline");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node dead_it = Deadline.append_child("processorId");
// dead_it.append_attribute("id").set_value(i);
// double deadline_value = (FRT.to_seconds());
// double dead_tot = (deadline_value/VPS[Id].profiling)*1000000.0;
// cout<<"VPS["<<Id<<"].profiling --> "<<VPS[Id].profiling<<endl;
// dead_it.append_attribute("value").set_value(dead_tot);
// }
// }
// }else{
// pugi::xml_node Deadline = seqLink_it->append_child("Deadline");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node dead_it = Deadline.append_child("processorId");
// dead_it.append_attribute("id").set_value(i);
// double deadline_value = (FRT.to_seconds());
// double dead_tot = (deadline_value/VPS[Id].profiling)*1000000.0;
// dead_it.append_attribute("value").set_value(dead_tot);
// }
// }
// }
//}
cout << "Saving result: " << myDoc.save_file("./XML/application.xml") << endl;
myDoc.reset();
cout<<endl;
/* pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
xml_node instancesBB = myDoc2.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
int Id = atoi(seqBB_it->child_value("id"));
///////////////////// LOAD ////////////////////////////
if(seqBB_it->child("loadEstimation")){
pugi::xml_node loadEstimation = seqBB_it->child("loadEstimation");
xml_node frl_node = loadEstimation.child("FreeRunningTime");
if(!(allocationPS_BB[Id] != Id))
{
sc_time local_frt = FRT;
//frl_node.attribute("value")=(local_frt.to_double()*1000); //another solution for the number conversion
frl_node.attribute("value")=(local_frt.to_seconds()*1000);
}
}else{
pugi::xml_node loadEstimation = seqBB_it->append_child("loadEstimation");
xml_node frl_node = loadEstimation.append_child("FreeRunningTime");
if(allocationPS_BB[Id] == Id)
{
sc_time local_frt = FRT;
//frl_node.attribute("value")=(local_frt.to_double()*1000); //another solution for the number conversion
frl_node.attribute("value")=(local_frt.to_seconds()*1000);
}
}
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl; */
///////////////////////////////////////////////////
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
xml_node instancesBB = myDoc2.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
int Id = atoi(seqBB_it->child_value("id"));
///////////////////// ENERGY ////////////////////////
if(Id == allocationPS_BB[2]){
if(seqBB_it->child("loadEstimation")){
pugi::xml_node energyEstimation = seqBB_it->child("loadEstimation");
xml_node entot_node = energyEstimation.append_child("FreeRunningTime");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
sc_time local_frt = FRT;
entot_node.append_attribute("value").set_value(local_frt.to_seconds()*1000);
}else{
pugi::xml_node energyEstimation = seqBB_it->append_child("energyEstimation");
xml_node entot_node = energyEstimation.append_child("energyTOT");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
sc_time local_frt = FRT;
entot_node.append_attribute("value").set_value(local_frt.to_seconds()*1000);
}
}
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl;
}
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#include <systemc.h>
#include <systemc-ams.h>
#include <config.hpp>
#define ${sensor_name}_VREF ${vref}
SCA_TDF_MODULE(Sensor_${sensor_name}_power)
{
//Data from Functional Instance
sca_tdf::sc_in <int> func_signal;
//Data to Power Bus
sca_tdf::sca_out <double> voltage_state;
sca_tdf::sca_out <double> current_state;
SCA_CTOR(Sensor_${sensor_name}_power):
func_signal("State_of_Power_From_Functional"),
voltage_state("Voltage_trace_to_Power_Bus"),
current_state("Current_trace_to_Power_Bus")
{}
void set_attributes();
void initialize();
void processing();
Sensor_${sensor_name}_power(){}
};
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