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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_10_H_
#define _design_1_xlconstant_0_10_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_10 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_10 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
/*
* Copyright EPFL 2021
* Rafael Medina Morillas
*
* Description of a generic 3 port (2 read, 1 write) register file.
*
*/
#ifndef RF_THREEPORT_H_
#define RF_THREEPORT_H_
#include "systemc.h"
template<class T, uint size>
class rf_threeport: public sc_module {
public:
sc_in_clk clk;
sc_in<bool> rst;
sc_in<uint> rd_addr1; // Index read
sc_in<uint> rd_addr2; // Index read
sc_out<T> rd_port1; // Read port
sc_out<T> rd_port2; // Read port
sc_in<bool> wr_en; // Enable writing
sc_in<uint> wr_addr; // Index the address to be written
sc_in<T> wr_port; // Write port
//Internal signals and variables
sc_signal<T> reg[size]; // Register file contents
SC_CTOR(rf_threeport) {
SC_METHOD(read_method);
sensitive << rd_addr1 << rd_addr2;
for (uint i = 0; i < size; i++)
sensitive << reg[i];
SC_THREAD(write_update_thread);
sensitive << clk.pos();
async_reset_signal_is(rst, false);
for (uint i = 0; i < size; i++)
reg[i] = (T) 0;
}
// Shows the indexed contents for reading
void read_method() {
if (rd_addr1->read() < size)
rd_port1->write(reg[rd_addr1->read()]);
else
rd_port1->write((T) 0);
if (rd_addr2->read() < size)
rd_port2->write(reg[rd_addr2->read()]);
else
rd_port2->write((T) 0);
}
// Write to the RF
void write_update_thread() {
// Reset behaviour
for (uint i = 0; i < size; i++) {
reg[i] = (T) 0;
}
wait();
// Clocked behaviour
while (1) {
if (wr_en->read() && wr_addr->read() < size) {
reg[wr_addr->read()] = wr_port;
}
wait();
}
}
};
#endif /* RF_THREEPORT_H_ */
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_pdp.h
#ifndef _NV_NVDLA_PDP_H_
#define _NV_NVDLA_PDP_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "nvdla_dma_wr_req_iface.h"
#include "systemc.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_pdp_base.h"
#include "pdp_reg_model.h"
#include "pdp_rdma_reg_model.h"
#include "NvdlaDataFormatConvertor.h"
#define PDP_RDMA_TRANSACTION_SIZE_GRANULARITY 32
#define PDP_RDMA_BUFFER_CMOD_ENTRY_GRANULARITY 4
#define PDP_WDMA_BUFFER_SIZE 256
#define PDP_CVT_OUT_BIT_WIDTH 16
#define PDP_CVT_OUT_NUMBER 8
#define PDP_GROUP_SIZE_IN_BYTE 32
#define MAX_MEM_TRANSACTION_SIZE 256
#define KERNEL_PER_GROUP_INT8 32
#define KERNEL_PER_GROUP_INT16 16
#define KERNEL_PER_GROUP_FP16 16
#define KERNEL_PER_GROUP_SIZE 32
#define SDP2PDP_ELEMENT_NUM 8
#define SDP2PDP_ELEMENT_BIT_WIDTH 16
#define PDP_WRITE_DMA_SUB_TRANSACTION_SIZE 64
#define DATA_FORMAT_IS_INT8 0
#define DATA_FORMAT_IS_INT16 1
#define DATA_FORMAT_IS_FP16 2
#define ELEMENT_SIZE_INT8 1
#define ELEMENT_SIZE_INT16 2
#define ELEMENT_SIZE_FP16 2
#define ELEMENT_PER_ATOM_INT8 32
#define ELEMENT_PER_ATOM_INT16 16
#define ELEMENT_PER_ATOM_FP16 16
#define TAG_CMD 0
#define TAG_DATA 1
#define ATOM_CUBE_SIZE 32
#define PDP_RDMA_BUFFER_TOTAL_SIZE 32*8192
#define PDP_RDMA_BUFFER_ENTRY_SIZE ATOM_CUBE_SIZE
#define PDP_RDMA_BUFFER_ENTRY_NUM PDP_RDMA_BUFFER_TOTAL_SIZE/PDP_RDMA_BUFFER_ENTRY_SIZE
#define SDP2PDP_PAYLOAD_SIZE 32
#define SDP2PDP_PAYLOAD_ELEMENT_NUM 16
#define SDP2PDP_FIFO_ENTRY_NUM 16 // ATOM_CUBE_SIZE/SDP2PDP_PAYLOAD_SIZE
#define PDP_LINE_BUFFER_INT8_ELEMENT_NUM 8*1024
#define PDP_LINE_BUFFER_INT16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_FP16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_PHYSICAL_BUFFER_NUM 8
#define PDP_LINE_BUFFER_SIZE (PDP_LINE_BUFFER_INT8_ELEMENT_NUM*2)
#define PDP_LINE_BUFFER_ENTRY_NUM (PDP_LINE_BUFFER_SIZE)/(ATOM_CUBE_SIZE*2) //Each atom consumes 64Bytes
#define POOLING_FLYING_MODE_ON_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING
#define POOLING_FLYING_MODE_OFF_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING
#define POOLING_METHOD_AVE NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE
#define POOLING_METHOD_MAX NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX
#define POOLING_METHOD_MIN NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN
#define DATA_TYPE_IS_INT 0
#define DATA_TYPE_IS_FLOAT 1
#define PDP_MAX_PADDING_SIZE 7
// class NvdlaDataFormatConvertor;
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// class container_payload_wrapper {
// public:
// uint8_t *data;
// uint8_t data_num;
// };
//
// std::ostream& operator<<(std::ostream& out, const container_payload_wrapper& obj) {
// return out << "Just to fool compiler" << endl;
// }
//
// std::ostream& operator<<(std::ostream& out, const nvdla_container_number_8_bit_width_16_t& obj) {
// return out << "Just to fool compiler" << endl;
// }
class pdp_ack_info {
public:
bool is_mc;
uint8_t group_id;
};
class NV_NVDLA_pdp:
public NV_NVDLA_pdp_base, // ports
private pdp_reg_model, // pdp register accessing
private pdp_rdma_reg_model // pdp_rdma
{
public:
SC_HAS_PROCESS(NV_NVDLA_pdp);
NV_NVDLA_pdp( sc_module_name module_name );
~NV_NVDLA_pdp();
// CSB request transport implementation shall in generated code
void csb2pdp_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void csb2pdp_rdma_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void sdp2pdp_b_transport(int ID, nvdla_sdp2pdp_t* payload, sc_core::sc_time& delay);
void mcif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
// void pdp2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
// void pdp_rdma2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
private:
// Payloads
nvdla_dma_wr_req_t *dma_wr_req_cmd_payload_;
nvdla_dma_wr_req_t *dma_wr_req_data_payload_;
nvdla_dma_rd_req_t *dma_rd_req_payload_;
// Delay
sc_core::sc_time dma_delay_;
sc_core::sc_time csb_delay_;
sc_core::sc_time b_transport_delay_;
// Events
// PDP config evaluation is done
sc_event event_pdp_config_evaluation_done;
// Receiving data from sdp
sc_event event_got_conv_data;
// Functional logic have fetched data from RDMA buffer
sc_event event_functional_logic_got_data;
sc_event rdma_read_event;
sc_event rdma_write_event;
// For PDP hardware layer kickoff and end
sc_event pdp_rdma_kickoff_;
sc_event pdp_rdma_done_;
sc_event pdp_kickoff_;
sc_event pdp_done_;
sc_core::sc_fifo<uint8_t> *line_buffer_usage_free_[PDP_LINE_BUFFER_ENTRY_NUM];
sc_core::sc_fifo<uint8_t> *line_buffer_usage_available_;
// sc_event *line_buffer_usage_free_read_event;
// sc_event *line_buffer_usage_free_write_event;
// sc_mutex line_buffer_data_ready_;
// uint32_t line_buffer_data_num_;
sc_core::sc_fifo<uint8_t> *line_buffer_ready_[PDP_LINE_BUFFER_ENTRY_NUM];
// Evaluated configs based on register config
uint32_t pdp_rdma_operation_mode_;
uint32_t pdp_operation_mode_;
bool pdp_ready_to_receive_data_;
// Temperal and intermedia signals
bool is_there_ongoing_csb2pdp_response_;
bool is_there_ongoing_csb2pdp_rdma_response_;
// Variables needs to be added to register
// uint8_t pdp_rdma_kernel_stride_width_;
// uint8_t pdp_rdma_kernel_width_;
// uint8_t pdp_rdma_pad_width_;
uint32_t pdp_cvt_offset_input_;
uint16_t pdp_cvt_scale_input_;
uint8_t pdp_cvt_truncate_lsb_input_;
uint8_t pdp_cvt_truncate_msb_input_;
sc_core::sc_fifo <uint8_t *> *spd2pdp_fifo_;
sc_core::sc_fifo <uint8_t *> *rdma_buffer_;
sc_core::sc_fifo <uint8_t *> *wdma_buffer_;
sc_core::sc_fifo <pdp_ack_info *> *pdp_ack_fifo_;
sc_event pdp_mc_ack_;
sc_event pdp_cv_ack_;
bool is_mc_ack_done_;
bool is_cv_ack_done_;
// RDMA buffer index
uint32_t rdma_buffer_write_idx_;
uint32_t rdma_buffer_read_idx_;
// WDMA buffer index
uint32_t wdma_buffer_write_idx_;
uint32_t wdma_buffer_read_idx_;
// Data buffers
// # Shared line buffer, each entry stores one int8 element
// In HW, its size is 8KB. In CMOD, it's 16KB. The num of entries are same as HW, however each entry size is 16B, not 8B for precision in arithmetic.
uint16_t line_buffer_[PDP_LINE_BUFFER_INT8_ELEMENT_NUM];
uint16_t line_operation_buffer_[8*ELEMENT_PER_ATOM_INT8];
// Function declaration
// # Threads
void PdpRdmaConsumerThread();
void PdpConsumerThread();
void PoolingStage0SequenceThread ();
void PoolingStage1SequenceThread ();
void PdpRdmaSequenceThread ();
void PdpWdmaSequenceThread ();
void PdpIntrThread();
void WriteResponseThreadMc();
void WriteResponseThreadCv();
// # Config evaluation
void PdpRdmaConfigEvaluation(CNVDLA_PDP_RDMA_REGSET *register_group_ptr);
void PdpConfigEvaluation(CNVDLA_PDP_REGSET *register_group_ptr);
// # Hardware layer execution trigger
void PdpRdmaHardwareLayerExecutionTrigger();
void PdpHardwareLayerExecutionTrigger();
// # Operation
void OperationModePdpRdmaCommon();
void OperationModePdpCommon();
void RdmaSequenceCommon(uint64_t src_base_addr, uint32_t cube_in_width);
// void RdmaSequence8Bto8B();
// void RdmaSequence16Bto16B();
// void RdmaSequence8Bto16B();
void RdmaSequence16Bto8B();
// Pooling function
void PoolingStage0SequenceCommon(uint32_t cube_in_width, uint32_t pad_left, uint32_t pad_right, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
void PoolingStage0Sequence8Bto8B();
void PoolingStage0Sequence16Bto16B();
void PoolingStage1SequenceCommon(uint32_t cube_out_width, uint32_t acc_subcube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
void PoolingStage1Sequence8Bto8B();
void PoolingStage1Sequence16Bto16B();
// void WdmaSequenceCommon();
void WdmaSequenceCommon(uint64_t dst_base_addr, uint32_t cube_out_width, bool split_last);
// # Functional functions
// Send DMA read request
void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay);
// void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay, uint8_t src_ram_type);
// Extract DMA read response payload
void ExtractDmaPayload(nvdla_dma_rd_rsp_t* payload);
// Send DMA write request
void SendDmaWriteRequest(nvdla_dma_wr_req_t* payload, sc_time& delay, bool ack_required = false);
void SendDmaWriteRequest(uint64_t payload_addr, uint32_t payload_size, uint32_t payload_atom_num, bool ack_required = false);
// template <typename T>
// void FetchInputData (uint8_t * atomic_cube);
uint8_t * FetchInputData ();
template <typename T_IN, typename T_OUT, typename T_PAD>
void PoolingStage0Calc (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t cube_out_width_idx, uint32_t cube_out_height_idx, uint32_t surface, uint32_t cube_in_height, uint32_t kernel_height_iter, uint32_t kernel_height, uint32_t cube_in_height_iter, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
template <typename T_OUT, typename T_IN>
void PoolingStage1Calc (T_OUT * atomic_data_out, T_IN * line_buffer_ptr, uint32_t width, uint32_t height, uint32_t surface, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
template <typename T_IN, typename T_OUT, typename T_PAD>
void LineOperation (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t kernel_width_iter, uint32_t kernel_width, uint32_t cube_in_width_iter, uint32_t cube_in_width, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t pad_left);
// ## Reset
void Reset();
void WaitUntilRdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilRdmaBufferAvailableSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferAvailableSizeGreaterThan(uint32_t num);
void PdpSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void PdpRdmaSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
bool IsFirstElement(uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsLastElement(uint32_t cube_in_width, uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsContributeToANewLine(uint32_t cube_in_height_iter, uint32_t kernel_height_iter);
template <typename T_IN, typename T_OUT>
void int_sign_extend(T_IN original_value, uint8_t sign_bit_idx, uint8_t extended_bit_num, T_OUT *return_value);
void reset_stats_regs();
void update_stats_regs();
uint32_t nan_input_num;
uint32_t inf_input_num;
uint32_t nan_output_num;
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_pdp * NV_NVDLA_pdpCon(sc_module_name module_name);
#endif
|
#include <systemc.h>
SC_MODULE( or_gate )
{
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
};
int sc_main( int argc, char * argv[] )
{
sc_signal<bool> s1;
sc_signal<bool> s2;
sc_signal<bool> s3;
s1.write(true);
s2.write(false);
s3.write(true);
or_gate gate("or_gate");
gate.a(s1);
gate.b(s2);
gate.c(s3);
// gate.or_process();
gate.test_process();
return 0;
}
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_pdp.h
#ifndef _NV_NVDLA_PDP_H_
#define _NV_NVDLA_PDP_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "nvdla_dma_wr_req_iface.h"
#include "systemc.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_pdp_base.h"
#include "pdp_reg_model.h"
#include "pdp_rdma_reg_model.h"
#include "NvdlaDataFormatConvertor.h"
#define PDP_RDMA_TRANSACTION_SIZE_GRANULARITY 32
#define PDP_RDMA_BUFFER_CMOD_ENTRY_GRANULARITY 4
#define PDP_WDMA_BUFFER_SIZE 256
#define PDP_CVT_OUT_BIT_WIDTH 16
#define PDP_CVT_OUT_NUMBER 8
#define PDP_GROUP_SIZE_IN_BYTE 32
#define MAX_MEM_TRANSACTION_SIZE 256
#define KERNEL_PER_GROUP_INT8 32
#define KERNEL_PER_GROUP_INT16 16
#define KERNEL_PER_GROUP_FP16 16
#define KERNEL_PER_GROUP_SIZE 32
#define SDP2PDP_ELEMENT_NUM 8
#define SDP2PDP_ELEMENT_BIT_WIDTH 16
#define PDP_WRITE_DMA_SUB_TRANSACTION_SIZE 64
#define DATA_FORMAT_IS_INT8 0
#define DATA_FORMAT_IS_INT16 1
#define DATA_FORMAT_IS_FP16 2
#define ELEMENT_SIZE_INT8 1
#define ELEMENT_SIZE_INT16 2
#define ELEMENT_SIZE_FP16 2
#define ELEMENT_PER_ATOM_INT8 32
#define ELEMENT_PER_ATOM_INT16 16
#define ELEMENT_PER_ATOM_FP16 16
#define TAG_CMD 0
#define TAG_DATA 1
#define ATOM_CUBE_SIZE 32
#define PDP_RDMA_BUFFER_TOTAL_SIZE 32*8192
#define PDP_RDMA_BUFFER_ENTRY_SIZE ATOM_CUBE_SIZE
#define PDP_RDMA_BUFFER_ENTRY_NUM PDP_RDMA_BUFFER_TOTAL_SIZE/PDP_RDMA_BUFFER_ENTRY_SIZE
#define SDP2PDP_PAYLOAD_SIZE 32
#define SDP2PDP_PAYLOAD_ELEMENT_NUM 16
#define SDP2PDP_FIFO_ENTRY_NUM 16 // ATOM_CUBE_SIZE/SDP2PDP_PAYLOAD_SIZE
#define PDP_LINE_BUFFER_INT8_ELEMENT_NUM 8*1024
#define PDP_LINE_BUFFER_INT16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_FP16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_PHYSICAL_BUFFER_NUM 8
#define PDP_LINE_BUFFER_SIZE (PDP_LINE_BUFFER_INT8_ELEMENT_NUM*2)
#define PDP_LINE_BUFFER_ENTRY_NUM (PDP_LINE_BUFFER_SIZE)/(ATOM_CUBE_SIZE*2) //Each atom consumes 64Bytes
#define POOLING_FLYING_MODE_ON_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING
#define POOLING_FLYING_MODE_OFF_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING
#define POOLING_METHOD_AVE NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE
#define POOLING_METHOD_MAX NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX
#define POOLING_METHOD_MIN NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN
#define DATA_TYPE_IS_INT 0
#define DATA_TYPE_IS_FLOAT 1
#define PDP_MAX_PADDING_SIZE 7
// class NvdlaDataFormatConvertor;
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// class container_payload_wrapper {
// public:
// uint8_t *data;
// uint8_t data_num;
// };
//
// std::ostream& operator<<(std::ostream& out, const container_payload_wrapper& obj) {
// return out << "Just to fool compiler" << endl;
// }
//
// std::ostream& operator<<(std::ostream& out, const nvdla_container_number_8_bit_width_16_t& obj) {
// return out << "Just to fool compiler" << endl;
// }
class pdp_ack_info {
public:
bool is_mc;
uint8_t group_id;
};
class NV_NVDLA_pdp:
public NV_NVDLA_pdp_base, // ports
private pdp_reg_model, // pdp register accessing
private pdp_rdma_reg_model // pdp_rdma
{
public:
SC_HAS_PROCESS(NV_NVDLA_pdp);
NV_NVDLA_pdp( sc_module_name module_name );
~NV_NVDLA_pdp();
// CSB request transport implementation shall in generated code
void csb2pdp_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void csb2pdp_rdma_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void sdp2pdp_b_transport(int ID, nvdla_sdp2pdp_t* payload, sc_core::sc_time& delay);
void mcif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
// void pdp2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
// void pdp_rdma2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
private:
// Payloads
nvdla_dma_wr_req_t *dma_wr_req_cmd_payload_;
nvdla_dma_wr_req_t *dma_wr_req_data_payload_;
nvdla_dma_rd_req_t *dma_rd_req_payload_;
// Delay
sc_core::sc_time dma_delay_;
sc_core::sc_time csb_delay_;
sc_core::sc_time b_transport_delay_;
// Events
// PDP config evaluation is done
sc_event event_pdp_config_evaluation_done;
// Receiving data from sdp
sc_event event_got_conv_data;
// Functional logic have fetched data from RDMA buffer
sc_event event_functional_logic_got_data;
sc_event rdma_read_event;
sc_event rdma_write_event;
// For PDP hardware layer kickoff and end
sc_event pdp_rdma_kickoff_;
sc_event pdp_rdma_done_;
sc_event pdp_kickoff_;
sc_event pdp_done_;
sc_core::sc_fifo<uint8_t> *line_buffer_usage_free_[PDP_LINE_BUFFER_ENTRY_NUM];
sc_core::sc_fifo<uint8_t> *line_buffer_usage_available_;
// sc_event *line_buffer_usage_free_read_event;
// sc_event *line_buffer_usage_free_write_event;
// sc_mutex line_buffer_data_ready_;
// uint32_t line_buffer_data_num_;
sc_core::sc_fifo<uint8_t> *line_buffer_ready_[PDP_LINE_BUFFER_ENTRY_NUM];
// Evaluated configs based on register config
uint32_t pdp_rdma_operation_mode_;
uint32_t pdp_operation_mode_;
bool pdp_ready_to_receive_data_;
// Temperal and intermedia signals
bool is_there_ongoing_csb2pdp_response_;
bool is_there_ongoing_csb2pdp_rdma_response_;
// Variables needs to be added to register
// uint8_t pdp_rdma_kernel_stride_width_;
// uint8_t pdp_rdma_kernel_width_;
// uint8_t pdp_rdma_pad_width_;
uint32_t pdp_cvt_offset_input_;
uint16_t pdp_cvt_scale_input_;
uint8_t pdp_cvt_truncate_lsb_input_;
uint8_t pdp_cvt_truncate_msb_input_;
sc_core::sc_fifo <uint8_t *> *spd2pdp_fifo_;
sc_core::sc_fifo <uint8_t *> *rdma_buffer_;
sc_core::sc_fifo <uint8_t *> *wdma_buffer_;
sc_core::sc_fifo <pdp_ack_info *> *pdp_ack_fifo_;
sc_event pdp_mc_ack_;
sc_event pdp_cv_ack_;
bool is_mc_ack_done_;
bool is_cv_ack_done_;
// RDMA buffer index
uint32_t rdma_buffer_write_idx_;
uint32_t rdma_buffer_read_idx_;
// WDMA buffer index
uint32_t wdma_buffer_write_idx_;
uint32_t wdma_buffer_read_idx_;
// Data buffers
// # Shared line buffer, each entry stores one int8 element
// In HW, its size is 8KB. In CMOD, it's 16KB. The num of entries are same as HW, however each entry size is 16B, not 8B for precision in arithmetic.
uint16_t line_buffer_[PDP_LINE_BUFFER_INT8_ELEMENT_NUM];
uint16_t line_operation_buffer_[8*ELEMENT_PER_ATOM_INT8];
// Function declaration
// # Threads
void PdpRdmaConsumerThread();
void PdpConsumerThread();
void PoolingStage0SequenceThread ();
void PoolingStage1SequenceThread ();
void PdpRdmaSequenceThread ();
void PdpWdmaSequenceThread ();
void PdpIntrThread();
void WriteResponseThreadMc();
void WriteResponseThreadCv();
// # Config evaluation
void PdpRdmaConfigEvaluation(CNVDLA_PDP_RDMA_REGSET *register_group_ptr);
void PdpConfigEvaluation(CNVDLA_PDP_REGSET *register_group_ptr);
// # Hardware layer execution trigger
void PdpRdmaHardwareLayerExecutionTrigger();
void PdpHardwareLayerExecutionTrigger();
// # Operation
void OperationModePdpRdmaCommon();
void OperationModePdpCommon();
void RdmaSequenceCommon(uint64_t src_base_addr, uint32_t cube_in_width);
// void RdmaSequence8Bto8B();
// void RdmaSequence16Bto16B();
// void RdmaSequence8Bto16B();
void RdmaSequence16Bto8B();
// Pooling function
void PoolingStage0SequenceCommon(uint32_t cube_in_width, uint32_t pad_left, uint32_t pad_right, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
void PoolingStage0Sequence8Bto8B();
void PoolingStage0Sequence16Bto16B();
void PoolingStage1SequenceCommon(uint32_t cube_out_width, uint32_t acc_subcube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
void PoolingStage1Sequence8Bto8B();
void PoolingStage1Sequence16Bto16B();
// void WdmaSequenceCommon();
void WdmaSequenceCommon(uint64_t dst_base_addr, uint32_t cube_out_width, bool split_last);
// # Functional functions
// Send DMA read request
void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay);
// void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay, uint8_t src_ram_type);
// Extract DMA read response payload
void ExtractDmaPayload(nvdla_dma_rd_rsp_t* payload);
// Send DMA write request
void SendDmaWriteRequest(nvdla_dma_wr_req_t* payload, sc_time& delay, bool ack_required = false);
void SendDmaWriteRequest(uint64_t payload_addr, uint32_t payload_size, uint32_t payload_atom_num, bool ack_required = false);
// template <typename T>
// void FetchInputData (uint8_t * atomic_cube);
uint8_t * FetchInputData ();
template <typename T_IN, typename T_OUT, typename T_PAD>
void PoolingStage0Calc (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t cube_out_width_idx, uint32_t cube_out_height_idx, uint32_t surface, uint32_t cube_in_height, uint32_t kernel_height_iter, uint32_t kernel_height, uint32_t cube_in_height_iter, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
template <typename T_OUT, typename T_IN>
void PoolingStage1Calc (T_OUT * atomic_data_out, T_IN * line_buffer_ptr, uint32_t width, uint32_t height, uint32_t surface, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
template <typename T_IN, typename T_OUT, typename T_PAD>
void LineOperation (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t kernel_width_iter, uint32_t kernel_width, uint32_t cube_in_width_iter, uint32_t cube_in_width, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t pad_left);
// ## Reset
void Reset();
void WaitUntilRdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilRdmaBufferAvailableSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferAvailableSizeGreaterThan(uint32_t num);
void PdpSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void PdpRdmaSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
bool IsFirstElement(uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsLastElement(uint32_t cube_in_width, uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsContributeToANewLine(uint32_t cube_in_height_iter, uint32_t kernel_height_iter);
template <typename T_IN, typename T_OUT>
void int_sign_extend(T_IN original_value, uint8_t sign_bit_idx, uint8_t extended_bit_num, T_OUT *return_value);
void reset_stats_regs();
void update_stats_regs();
uint32_t nan_input_num;
uint32_t inf_input_num;
uint32_t nan_output_num;
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_pdp * NV_NVDLA_pdpCon(sc_module_name module_name);
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _dct_HH_
#define _dct_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "read_data.h"
#include "Loop_Row_DCT_Loop_pr.h"
#include "Loop_Xpose_Row_Outer.h"
#include "Loop_Col_DCT_Loop_pr.h"
#include "Loop_Xpose_Col_Outer.h"
#include "write_data.h"
#include "dct_row_outbuf_i.h"
#include "dct_col_inbuf_0.h"
namespace ap_rtl {
struct dct : public sc_module {
// Port declarations 26
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_out< sc_lv<6> > input_r_address0;
sc_out< sc_logic > input_r_ce0;
sc_out< sc_lv<16> > input_r_d0;
sc_in< sc_lv<16> > input_r_q0;
sc_out< sc_logic > input_r_we0;
sc_out< sc_lv<6> > input_r_address1;
sc_out< sc_logic > input_r_ce1;
sc_out< sc_lv<16> > input_r_d1;
sc_in< sc_lv<16> > input_r_q1;
sc_out< sc_logic > input_r_we1;
sc_out< sc_lv<6> > output_r_address0;
sc_out< sc_logic > output_r_ce0;
sc_out< sc_lv<16> > output_r_d0;
sc_in< sc_lv<16> > output_r_q0;
sc_out< sc_logic > output_r_we0;
sc_out< sc_lv<6> > output_r_address1;
sc_out< sc_logic > output_r_ce1;
sc_out< sc_lv<16> > output_r_d1;
sc_in< sc_lv<16> > output_r_q1;
sc_out< sc_logic > output_r_we1;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > ap_idle;
sc_signal< sc_logic > ap_var_for_const2;
sc_signal< sc_logic > ap_var_for_const0;
sc_signal< sc_lv<16> > ap_var_for_const1;
// Module declarations
dct(sc_module_name name);
SC_HAS_PROCESS(dct);
~dct();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
dct_row_outbuf_i* row_outbuf_i_U;
dct_row_outbuf_i* col_outbuf_i_U;
dct_col_inbuf_0* col_inbuf_0_U;
dct_col_inbuf_0* col_inbuf_1_U;
dct_col_inbuf_0* col_inbuf_2_U;
dct_col_inbuf_0* col_inbuf_3_U;
dct_col_inbuf_0* col_inbuf_4_U;
dct_col_inbuf_0* col_inbuf_5_U;
dct_col_inbuf_0* col_inbuf_6_U;
dct_col_inbuf_0* col_inbuf_7_U;
dct_col_inbuf_0* buf_2d_in_0_U;
dct_col_inbuf_0* buf_2d_in_1_U;
dct_col_inbuf_0* buf_2d_in_2_U;
dct_col_inbuf_0* buf_2d_in_3_U;
dct_col_inbuf_0* buf_2d_in_4_U;
dct_col_inbuf_0* buf_2d_in_5_U;
dct_col_inbuf_0* buf_2d_in_6_U;
dct_col_inbuf_0* buf_2d_in_7_U;
dct_row_outbuf_i* buf_2d_out_U;
read_data* read_data_U0;
Loop_Row_DCT_Loop_pr* Loop_Row_DCT_Loop_pr_U0;
Loop_Xpose_Row_Outer* Loop_Xpose_Row_Outer_U0;
Loop_Col_DCT_Loop_pr* Loop_Col_DCT_Loop_pr_U0;
Loop_Xpose_Col_Outer* Loop_Xpose_Col_Outer_U0;
write_data* write_data_U0;
sc_signal< sc_lv<16> > row_outbuf_i_i_q0;
sc_signal< sc_lv<16> > row_outbuf_i_t_q0;
sc_signal< sc_lv<16> > col_outbuf_i_i_q0;
sc_signal< sc_lv<16> > col_outbuf_i_t_q0;
sc_signal< sc_lv<16> > col_inbuf_0_i_q0;
sc_signal< sc_lv<16> > col_inbuf_0_t_q0;
sc_signal< sc_lv<16> > col_inbuf_1_i_q0;
sc_signal< sc_lv<16> > col_inbuf_1_t_q0;
sc_signal< sc_lv<16> > col_inbuf_2_i_q0;
sc_signal< sc_lv<16> > col_inbuf_2_t_q0;
sc_signal< sc_lv<16> > col_inbuf_3_i_q0;
sc_signal< sc_lv<16> > col_inbuf_3_t_q0;
sc_signal< sc_lv<16> > col_inbuf_4_i_q0;
sc_signal< sc_lv<16> > col_inbuf_4_t_q0;
sc_signal< sc_lv<16> > col_inbuf_5_i_q0;
sc_signal< sc_lv<16> > col_inbuf_5_t_q0;
sc_signal< sc_lv<16> > col_inbuf_6_i_q0;
sc_signal< sc_lv<16> > col_inbuf_6_t_q0;
sc_signal< sc_lv<16> > col_inbuf_7_i_q0;
sc_signal< sc_lv<16> > col_inbuf_7_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_0_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_0_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_1_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_1_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_2_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_2_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_3_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_3_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_4_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_4_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_5_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_5_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_6_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_6_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_7_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_7_t_q0;
sc_signal< sc_lv<16> > buf_2d_out_i_q0;
sc_signal< sc_lv<16> > buf_2d_out_t_q0;
sc_signal< sc_logic > read_data_U0_ap_start;
sc_signal< sc_logic > read_data_U0_ap_done;
sc_signal< sc_logic > read_data_U0_ap_continue;
sc_signal< sc_logic > read_data_U0_ap_idle;
sc_signal< sc_logic > read_data_U0_ap_ready;
sc_signal< sc_lv<6> > read_data_U0_input_r_address0;
sc_signal< sc_logic > read_data_U0_input_r_ce0;
sc_signal< sc_lv<3> > read_data_U0_buf_0_address0;
sc_signal< sc_logic > read_data_U0_buf_0_ce0;
sc_signal< sc_logic > read_data_U0_buf_0_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_0_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_1_address0;
sc_signal< sc_logic > read_data_U0_buf_1_ce0;
sc_signal< sc_logic > read_data_U0_buf_1_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_1_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_2_address0;
sc_signal< sc_logic > read_data_U0_buf_2_ce0;
sc_signal< sc_logic > read_data_U0_buf_2_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_2_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_3_address0;
sc_signal< sc_logic > read_data_U0_buf_3_ce0;
sc_signal< sc_logic > read_data_U0_buf_3_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_3_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_4_address0;
sc_signal< sc_logic > read_data_U0_buf_4_ce0;
sc_signal< sc_logic > read_data_U0_buf_4_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_4_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_5_address0;
sc_signal< sc_logic > read_data_U0_buf_5_ce0;
sc_signal< sc_logic > read_data_U0_buf_5_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_5_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_6_address0;
sc_signal< sc_logic > read_data_U0_buf_6_ce0;
sc_signal< sc_logic > read_data_U0_buf_6_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_6_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_7_address0;
sc_signal< sc_logic > read_data_U0_buf_7_ce0;
sc_signal< sc_logic > read_data_U0_buf_7_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_7_d0;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_7;
sc_signal< sc_logic > read_data_U0_buf_7_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_7;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_7;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_6;
sc_signal< sc_logic > read_data_U0_buf_6_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_6;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_6;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_5;
sc_signal< sc_logic > read_data_U0_buf_5_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_5;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_5;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_4;
sc_signal< sc_logic > read_data_U0_buf_4_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_4;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_4;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_3;
sc_signal< sc_logic > read_data_U0_buf_3_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_3;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_3;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_2;
sc_signal< sc_logic > read_data_U0_buf_2_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_2;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_2;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_1;
sc_signal< sc_logic > read_data_U0_buf_1_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_1;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_1;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_0;
sc_signal< sc_logic > read_data_U0_buf_0_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_0;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_start;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_done;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_continue;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_idle;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_ready;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_0_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_0_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_1_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_1_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_2_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_2_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_3_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_3_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_4_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_4_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_5_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_5_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_6_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_6_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_7_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_7_ce0;
sc_signal< sc_lv<6> > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_ce0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_we0;
sc_signal< sc_lv<16> > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_d0;
sc_signal< sc_logic > ap_channel_done_row_outbuf_i;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_full_n;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_start;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_done;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_continue;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_idle;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_ready;
sc_signal< sc_lv<6> > Loop_Xpose_Row_Outer_U0_row_outbuf_i_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_row_outbuf_i_ce0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_0_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_0_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_0_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_0_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_1_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_1_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_1_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_1_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_2_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_2_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_2_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_2_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_3_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_3_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_3_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_3_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_4_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_4_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_4_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_4_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_5_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_5_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_5_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_5_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_6_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_6_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_6_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_6_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_7_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_7_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_7_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_7_d0;
sc_signal< sc_logic > ap_channel_done_col_inbuf_7;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_7_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_7;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_7;
sc_signal< sc_logic > ap_channel_done_col_inbuf_6;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_6_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_6;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_6;
sc_signal< sc_logic > ap_channel_done_col_inbuf_5;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_5_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_5;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_5;
sc_signal< sc_logic > ap_channel_done_col_inbuf_4;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_4_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_4;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_4;
sc_signal< sc_logic > ap_channel_done_col_inbuf_3;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_3_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_3;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_3;
sc_signal< sc_logic > ap_channel_done_col_inbuf_2;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_2_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_2;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_2;
sc_signal< sc_logic > ap_channel_done_col_inbuf_1;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_1_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_1;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_1;
sc_signal< sc_logic > ap_channel_done_col_inbuf_0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_0_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_0;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_start;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_done;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_continue;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_idle;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_ready;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_0_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_0_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_1_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_1_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_2_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_2_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_3_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_3_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_4_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_4_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_5_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_5_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_6_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_6_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_7_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_7_ce0;
sc_signal< sc_lv<6> > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_ce0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_we0;
sc_signal< sc_lv<16> > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_d0;
sc_signal< sc_logic > ap_channel_done_col_outbuf_i;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_full_n;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_start;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_done;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_continue;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_idle;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_ready;
sc_signal< sc_lv<6> > Loop_Xpose_Col_Outer_U0_col_outbuf_i_address0;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_col_outbuf_i_ce0;
sc_signal< sc_lv<6> > Loop_Xpose_Col_Outer_U0_buf_2d_out_address0;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_buf_2d_out_ce0;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_buf_2d_out_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Col_Outer_U0_buf_2d_out_d0;
sc_signal< sc_logic > ap_channel_done_buf_2d_out;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_buf_2d_out_full_n;
sc_signal< sc_logic > write_data_U0_ap_start;
sc_signal< sc_logic > write_data_U0_ap_done;
sc_signal< sc_logic > write_data_U0_ap_continue;
sc_signal< sc_logic > write_data_U0_ap_idle;
sc_signal< sc_logic > write_data_U0_ap_ready;
sc_signal< sc_lv<6> > write_data_U0_buf_r_address0;
sc_signal< sc_logic > write_data_U0_buf_r_ce0;
sc_signal< sc_lv<6> > write_data_U0_output_r_address0;
sc_signal< sc_logic > write_data_U0_output_r_ce0;
sc_signal< sc_logic > write_data_U0_output_r_we0;
sc_signal< sc_lv<16> > write_data_U0_output_r_d0;
sc_signal< sc_logic > ap_sync_continue;
sc_signal< sc_logic > buf_2d_in_0_i_full_n;
sc_signal< sc_logic > buf_2d_in_0_t_empty_n;
sc_signal< sc_logic > buf_2d_in_1_i_full_n;
sc_signal< sc_logic > buf_2d_in_1_t_empty_n;
sc_signal< sc_logic > buf_2d_in_2_i_full_n;
sc_signal< sc_logic > buf_2d_in_2_t_empty_n;
sc_signal< sc_logic > buf_2d_in_3_i_full_n;
sc_signal< sc_logic > buf_2d_in_3_t_empty_n;
sc_signal< sc_logic > buf_2d_in_4_i_full_n;
sc_signal< sc_logic > buf_2d_in_4_t_empty_n;
sc_signal< sc_logic > buf_2d_in_5_i_full_n;
sc_signal< sc_logic > buf_2d_in_5_t_empty_n;
sc_signal< sc_logic > buf_2d_in_6_i_full_n;
sc_signal< sc_logic > buf_2d_in_6_t_empty_n;
sc_signal< sc_logic > buf_2d_in_7_i_full_n;
sc_signal< sc_logic > buf_2d_in_7_t_empty_n;
sc_signal< sc_logic > row_outbuf_i_i_full_n;
sc_signal< sc_logic > row_outbuf_i_t_empty_n;
sc_signal< sc_logic > col_inbuf_0_i_full_n;
sc_signal< sc_logic > col_inbuf_0_t_empty_n;
sc_signal< sc_logic > col_inbuf_1_i_full_n;
sc_signal< sc_logic > col_inbuf_1_t_empty_n;
sc_signal< sc_logic > col_inbuf_2_i_full_n;
sc_signal< sc_logic > col_inbuf_2_t_empty_n;
sc_signal< sc_logic > col_inbuf_3_i_full_n;
sc_signal< sc_logic > col_inbuf_3_t_empty_n;
sc_signal< sc_logic > col_inbuf_4_i_full_n;
sc_signal< sc_logic > col_inbuf_4_t_empty_n;
sc_signal< sc_logic > col_inbuf_5_i_full_n;
sc_signal< sc_logic > col_inbuf_5_t_empty_n;
sc_signal< sc_logic > col_inbuf_6_i_full_n;
sc_signal< sc_logic > col_inbuf_6_t_empty_n;
sc_signal< sc_logic > col_inbuf_7_i_full_n;
sc_signal< sc_logic > col_inbuf_7_t_empty_n;
sc_signal< sc_logic > col_outbuf_i_i_full_n;
sc_signal< sc_logic > col_outbuf_i_t_empty_n;
sc_signal< sc_logic > buf_2d_out_i_full_n;
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sc_signal< sc_logic > buf_2d_out_t_empty_n;
sc_signal< sc_logic > ap_sync_done;
sc_signal< sc_logic > ap_sync_ready;
sc_signal< sc_logic > read_data_U0_start_full_n;
sc_signal< sc_logic > read_data_U0_start_write;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_start_full_n;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_start_write;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_start_full_n;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_start_write;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_start_full_n;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_start_write;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_start_full_n;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_start_write;
sc_signal< sc_logic > write_data_U0_start_full_n;
sc_signal< sc_logic > write_data_U0_start_write;
static const sc_logic ap_const_logic_1;
static const sc_lv<6> ap_const_lv6_0;
static const sc_logic ap_const_logic_0;
static const sc_lv<16> ap_const_lv16_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_var_for_const2();
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_clk_no_reset_();
void thread_Loop_Col_DCT_Loop_pr_U0_ap_continue();
void thread_Loop_Col_DCT_Loop_pr_U0_ap_start();
void thread_Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_full_n();
void thread_Loop_Col_DCT_Loop_pr_U0_start_full_n();
void thread_Loop_Col_DCT_Loop_pr_U0_start_write();
void thread_Loop_Row_DCT_Loop_pr_U0_ap_continue();
void thread_Loop_Row_DCT_Loop_pr_U0_ap_start();
void thread_Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_full_n();
void thread_Loop_Row_DCT_Loop_pr_U0_start_full_n();
void thread_Loop_Row_DCT_Loop_pr_U0_start_write();
void thread_Loop_Xpose_Col_Outer_U0_ap_continue();
void thread_Loop_Xpose_Col_Outer_U0_ap_start();
void thread_Loop_Xpose_Col_Outer_U0_buf_2d_out_full_n();
void thread_Loop_Xpose_Col_Outer_U0_start_full_n();
void thread_Loop_Xpose_Col_Outer_U0_start_write();
void thread_Loop_Xpose_Row_Outer_U0_ap_continue();
void thread_Loop_Xpose_Row_Outer_U0_ap_start();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_0_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_1_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_2_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_3_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_4_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_5_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_6_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_7_full_n();
void thread_Loop_Xpose_Row_Outer_U0_start_full_n();
void thread_Loop_Xpose_Row_Outer_U0_start_write();
void thread_ap_channel_done_buf_2d_in_0();
void thread_ap_channel_done_buf_2d_in_1();
void thread_ap_channel_done_buf_2d_in_2();
void thread_ap_channel_done_buf_2d_in_3();
void thread_ap_channel_done_buf_2d_in_4();
void thread_ap_channel_done_buf_2d_in_5();
void thread_ap_channel_done_buf_2d_in_6();
void thread_ap_channel_done_buf_2d_in_7();
void thread_ap_channel_done_buf_2d_out();
void thread_ap_channel_done_col_inbuf_0();
void thread_ap_channel_done_col_inbuf_1();
void thread_ap_channel_done_col_inbuf_2();
void thread_ap_channel_done_col_inbuf_3();
void thread_ap_channel_done_col_inbuf_4();
void thread_ap_channel_done_col_inbuf_5();
void thread_ap_channel_done_col_inbuf_6();
void thread_ap_channel_done_col_inbuf_7();
void thread_ap_channel_done_col_outbuf_i();
void thread_ap_channel_done_row_outbuf_i();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_sync_channel_write_buf_2d_in_0();
void thread_ap_sync_channel_write_buf_2d_in_1();
void thread_ap_sync_channel_write_buf_2d_in_2();
void thread_ap_sync_channel_write_buf_2d_in_3();
void thread_ap_sync_channel_write_buf_2d_in_4();
void thread_ap_sync_channel_write_buf_2d_in_5();
void thread_ap_sync_channel_write_buf_2d_in_6();
void thread_ap_sync_channel_write_buf_2d_in_7();
void thread_ap_sync_channel_write_col_inbuf_0();
void thread_ap_sync_channel_write_col_inbuf_1();
void thread_ap_sync_channel_write_col_inbuf_2();
void thread_ap_sync_channel_write_col_inbuf_3();
void thread_ap_sync_channel_write_col_inbuf_4();
void thread_ap_sync_channel_write_col_inbuf_5();
void thread_ap_sync_channel_write_col_inbuf_6();
void thread_ap_sync_channel_write_col_inbuf_7();
void thread_ap_sync_continue();
void thread_ap_sync_done();
void thread_ap_sync_ready();
void thread_input_r_address0();
void thread_input_r_address1();
void thread_input_r_ce0();
void thread_input_r_ce1();
void thread_input_r_d0();
void thread_input_r_d1();
void thread_input_r_we0();
void thread_input_r_we1();
void thread_output_r_address0();
void thread_output_r_address1();
void thread_output_r_ce0();
void thread_output_r_ce1();
void thread_output_r_d0();
void thread_output_r_d1();
void thread_output_r_we0();
void thread_output_r_we1();
void thread_read_data_U0_ap_continue();
void thread_read_data_U0_ap_start();
void thread_read_data_U0_buf_0_full_n();
void thread_read_data_U0_buf_1_full_n();
void thread_read_data_U0_buf_2_full_n();
void thread_read_data_U0_buf_3_full_n();
void thread_read_data_U0_buf_4_full_n();
void thread_read_data_U0_buf_5_full_n();
void thread_read_data_U0_buf_6_full_n();
void thread_read_data_U0_buf_7_full_n();
void thread_read_data_U0_start_full_n();
void thread_read_data_U0_start_write();
void thread_write_data_U0_ap_continue();
void thread_write_data_U0_ap_start();
void thread_write_data_U0_start_full_n();
void thread_write_data_U0_start_write();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
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/******************************************************
* Architecture Module header file. *
* This file is automatically generated by ArchC *
* WITHOUT WARRANTY OF ANY KIND, either express *
* or implied. *
* For more information on ArchC, please visit: *
* http://www.archc.org *
* *
* The ArchC Team *
* Computer Systems Laboratory (LSC) *
* IC-UNICAMP *
* http://www.lsc.ic.unicamp.br *
******************************************************/
#ifndef _MIPS_H
#define _MIPS_H
#include "systemc.h"
#include "ac_module.H"
#include "ac_utils.H"
#include "mips_parms.H"
#include "mips_arch.H"
#include "mips_isa.H"
#include "mips_syscall.H"
class mips: public ac_module, public mips_arch {
private:
typedef cache_item<mips_parms::AC_DEC_FIELD_NUMBER> cache_item_t;
typedef ac_instr<mips_parms::AC_DEC_FIELD_NUMBER> ac_instr_t;
public:
unsigned bhv_pc;
bool has_delayed_load;
char* delayed_load_program;
mips_parms::mips_isa ISA;
cache_item_t* DEC_CACHE;
unsigned id;
bool start_up;
unsigned* instr_dec;
ac_instr_t* instr_vec;
//!Behavior execution method.
void behavior();
SC_HAS_PROCESS( mips );
//!Constructor.
mips( sc_module_name name_ ): ac_module(name_), mips_arch(), ISA(*this) {
SC_THREAD( behavior );
bhv_pc = 0;
has_delayed_load = false;
start_up=1;
id = 1;
}
void init_dec_cache() {
DEC_CACHE = (cache_item_t*) calloc(sizeof(cache_item_t),dec_cache_size);
}
unsigned get_ac_pc();
void set_ac_pc( unsigned int value );
virtual void PrintStat();
void init(int ac, char* av[]);
void init();
void load(char* program);
void delayed_load(char* program);
void stop(int status = 0);
virtual ~mips() {};
};
#endif //_MIPS_H
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// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_csb_master.h
#ifndef _NV_NVDLA_CSB_MASTER_H_
#define _NV_NVDLA_CSB_MASTER_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "NV_MSDEC_xx2csb_wr_erpt_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_csb_master_base.h"
#define GLB_BASE 0x0
#define GEC_BASE 0x1000
#define MCIF_BASE 0x2000
#define CVIF_BASE 0x3000
#define BDMA_BASE 0x4000
#define CDMA_BASE 0x5000
#define CSC_BASE 0x6000
#define CMAC_A_BASE 0x7000
#define CMAC_B_BASE 0x8000
#define CACC_BASE 0x9000
#define SDP_RDMA_BASE 0xa000
#define SDP_BASE 0xb000
#define PDP_RDMA_BASE 0xc000
#define PDP_BASE 0xd000
#define CDP_RDMA_BASE 0xe000
#define CDP_BASE 0xf000
#define RBK_BASE 0x10000
SCSIM_NAMESPACE_START(cmod)
// Forward declaration on NESS generated wrapper
// class NV_NVDLA_csb_master_base;
class NV_NVDLA_csb_master:public NV_NVDLA_csb_master_base {
public:
NV_NVDLA_csb_master( sc_module_name module_name );
~NV_NVDLA_csb_master();
// Socket function declaration
// FIXME, hack for csb2nvdla write response initial socket
tlm::tlm_generic_payload csb2nvdla_wr_hack_bp;
NV_MSDEC_xx2csb_wr_erpt_t csb2nvdla_wr_hack_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csb_master, 32, tlm::tlm_base_protocol_types, 0, sc_core::SC_ONE_OR_MORE_BOUND> csb2nvdla_wr_hack;
virtual void csb2nvdla_wr_hack_b_transport(NV_MSDEC_xx2csb_wr_erpt_t* payload, sc_time& delay);
// nvdla2csb request target socket
virtual void nvdla2csb_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
// CSB2NVDLA_CORE_Clients sockets
void glb2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void gec2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void mcif2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cvif2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void bdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void csc2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cmac_a2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cmac_b2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cacc2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void sdp_rdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void sdp2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void pdp_rdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void pdp2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cdp_rdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cdp2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void rbk2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
private:
uint32_t serving_client_id;
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_csb_master * NV_NVDLA_csb_masterCon(sc_module_name module_name);
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_csb_master.h
#ifndef _NV_NVDLA_CSB_MASTER_H_
#define _NV_NVDLA_CSB_MASTER_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "NV_MSDEC_xx2csb_wr_erpt_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_csb_master_base.h"
#define GLB_BASE 0x0
#define GEC_BASE 0x1000
#define MCIF_BASE 0x2000
#define CVIF_BASE 0x3000
#define BDMA_BASE 0x4000
#define CDMA_BASE 0x5000
#define CSC_BASE 0x6000
#define CMAC_A_BASE 0x7000
#define CMAC_B_BASE 0x8000
#define CACC_BASE 0x9000
#define SDP_RDMA_BASE 0xa000
#define SDP_BASE 0xb000
#define PDP_RDMA_BASE 0xc000
#define PDP_BASE 0xd000
#define CDP_RDMA_BASE 0xe000
#define CDP_BASE 0xf000
#define RBK_BASE 0x10000
SCSIM_NAMESPACE_START(cmod)
// Forward declaration on NESS generated wrapper
// class NV_NVDLA_csb_master_base;
class NV_NVDLA_csb_master:public NV_NVDLA_csb_master_base {
public:
NV_NVDLA_csb_master( sc_module_name module_name );
~NV_NVDLA_csb_master();
// Socket function declaration
// FIXME, hack for csb2nvdla write response initial socket
tlm::tlm_generic_payload csb2nvdla_wr_hack_bp;
NV_MSDEC_xx2csb_wr_erpt_t csb2nvdla_wr_hack_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csb_master, 32, tlm::tlm_base_protocol_types, 0, sc_core::SC_ONE_OR_MORE_BOUND> csb2nvdla_wr_hack;
virtual void csb2nvdla_wr_hack_b_transport(NV_MSDEC_xx2csb_wr_erpt_t* payload, sc_time& delay);
// nvdla2csb request target socket
virtual void nvdla2csb_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
// CSB2NVDLA_CORE_Clients sockets
void glb2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void gec2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void mcif2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cvif2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void bdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void csc2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cmac_a2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cmac_b2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cacc2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void sdp_rdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void sdp2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void pdp_rdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void pdp2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cdp_rdma2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void cdp2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
void rbk2csb_resp_b_transport(int ID, nvdla_xx2csb_resp_t* payload, sc_time& delay);
private:
uint32_t serving_client_id;
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_csb_master * NV_NVDLA_csb_masterCon(sc_module_name module_name);
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _Mayo_keygen_Ground32_0_H_
#define _Mayo_keygen_Ground32_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class Mayo_keygen_Ground32_0 : public sc_module {
public:
xlconstant_v1_1_7<32,0x00000000> mod;
sc_out< sc_bv<32> > dout;
Mayo_keygen_Ground32_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_18_0_H_
#define _icyradio_GND_18_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_18_0 : public sc_module {
public:
xlconstant_v1_1_8<1,0> mod;
sc_out< sc_bv<1> > dout;
icyradio_GND_18_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _Mayo_keygen_no_zynq_Ground0_0_H_
#define _Mayo_keygen_no_zynq_Ground0_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class Mayo_keygen_no_zynq_Ground0_0 : public sc_module {
public:
xlconstant_v1_1_7<1,0> mod;
sc_out< sc_bv<1> > dout;
Mayo_keygen_no_zynq_Ground0_0 (sc_core::sc_module_name name);
};
#endif
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: UVMC Command API
//
// This section describes the API for accessing and controlling UVM simulation
// in SystemVerilog from SystemC (or C or C++). To use, the SV side must have
// called the ~uvmc_init~, which starts a background process that receives and
// processes incoming commands.
//
// The UVM Connect library provides an SystemC API for accessing SystemVeilog
// UVM during simulation. With this API users can:
//
// - Wait for a UVM to reach a given simulation phase
// - Raise and drop objections
// - Set and get UVM configuration
// - Send UVM report messages
// - Set type and instance overrides in the UVM factory
// - Print UVM component topology
//
// While most commands are compatible with C, a few functions take object
// arguments or block on sc_events. Therefore, SystemC is currently the only
// practical source language for using the UVM Command API. Future releases may
// separate the subset of C-compatible functions into a separate shared library
// that would not require linking in SystemC.
//
// The following may appear in a future release, based on demand
//
// - Callbacks on phase and objection activity
// - Receive UVM report messages, i.e. SC-side acts as report catcher or server
// - Integration with SystemCs sc_report_handler facility
// - Print factory contents, config db contents, and other UVM information
// - Separate command layer into SC, C++, and C-accessible components; i.e.
// not require SystemC for non-SystemC-dependent functions
//
// The following sections provide details and examples for each command in the
// UVM Command API. To enable access to the UVM command layer, you must call
// the uvmc_cmd_init function from an initial block in a top-level module as in
// the following example:
//
// SystemVerilog:
//
//| module sv_main;
//|
//| import uvm_pkg::*;
//| import uvmc_pkg::*;
//|
//| initial begin
//| uvmc_cmd_init();
//| run_test();
//| end
//|
//| endmodule
//
// SystemC-side calls to the UVM Command API will block until SystemVerilog has
// finished elaboration and the uvmc_cmd_init function has been called. Because
// any call to the UVM Command layer may block, calls must be made from within
// thread processes.
//
// All code provided in the UVM Command descriptions that follow are SystemC
// unless stated otherwise.
#ifndef UVMC_COMMANDS_H
#define UVMC_COMMANDS_H
#include "svdpi.h"
#include <string>
#include <map>
#include <vector>
#include <iomanip>
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace sc_dt;
using namespace tlm;
using std::string;
using std::map;
using std::vector;
using sc_core::sc_semaphore;
#include "uvmc_common.h"
#include "uvmc_convert.h"
extern "C" {
//------------------------------------------------------------------------------
// Group: Enumeration Constants
//
// The following enumeration constants are used in various UVM Commands:
//------------------------------------------------------------------------------
// Enum: uvmc_phase_state
//
// The state of a UVM phase
//
// UVM_PHASE_DORMANT - Phase has not started yet
// UVM_PHASE_STARTED - Phase has started
// UVM_PHASE_EXECUTING - Phase is executing
// UVM_PHASE_READY_TO_END - Phase is ready to end
// UVM_PHASE_ENDED - Phase has ended
// UVM_PHASE_DONE - Phase has completed
//
enum uvmc_phase_state {
UVM_PHASE_DORMANT = 1,
UVM_PHASE_SCHEDULED = 2,
UVM_PHASE_SYNCING = 4,
UVM_PHASE_STARTED = 8,
UVM_PHASE_EXECUTING = 16,
UVM_PHASE_READY_TO_END = 32,
UVM_PHASE_ENDED = 64,
UVM_PHASE_CLEANUP = 128,
UVM_PHASE_DONE = 256,
UVM_PHASE_JUMPING = 512
};
// Enum: uvmc_report_severity
//
// The severity of a report
//
// UVM_INFO - Informative message. Verbosity settings affect whether
// they are printed.
// UVM_WARNING - Warning. Not affected by verbosity settings.
// UVM_ERROR - Error. Error counter incremented by default. Not affected
// by verbosity settings.
// UVM_FATAL - Unrecoverable error. SV simulation will end immediately.
//
enum uvmc_report_severity {
UVM_INFO,
UVM_WARNING,
UVM_ERROR,
UVM_FATAL
};
// Enum: uvmc_report_verbosity
//
// The verbosity level assigned to UVM_INFO reports
//
// UVM_NONE - report will always be issued (unaffected by
// verbosity level)
// UVM_LOW - report is issued at low verbosity setting and higher
// UVM_MEDIUM - report is issued at medium verbosity and higher
// UVM_HIGH - report is issued at high verbosity and higher
// UVM_FULL - report is issued only when verbosity is set to full
//
enum uvmc_report_verbosity {
UVM_NONE = 0,
UVM_LOW = 100,
UVM_MEDIUM = 200,
UVM_HIGH = 300,
UVM_FULL = 400
};
// Enum: uvmc_wait_op
//
// The relational operator to apply in <uvmc_wait_for_phase> calls
//
// UVM_LT - Wait until UVM is before the given phase
// UVM_LTE - Wait until UVM is before or at the given phase
// UVM_NE - Wait until UVM is not at the given phase
// UVM_EQ - Wait until UVM is at the given phase
// UVM_GT - Wait until UVM is after the given phase
// UVM_GTE - Wait until UVM is at or after the given phase
//
enum uvmc_wait_op {
UVM_LT,
UVM_LTE,
UVM_NE,
UVM_EQ,
UVM_GT,
UVM_GTE
};
void wait_sv_ready();
} // extern "C"
//------------------------------------------------------------------------------
// UVM COMMANDS
extern "C" {
// Internal API (SV DPI Export Functions)
void UVMC_print_topology(const char* context="", int depth=-1);
bool UVMC_report_enabled (const char* context,
int verbosity,
int severity,
const char* id);
void UVMC_set_report_verbosity(int level,
const char* context,
bool recurse=0);
void UVMC_report (int severity,
const char* id,
const char* message,
int verbosity,
const char* context,
const char* filename,
int line);
// up to 64 bits
void UVMC_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
void UVMC_set_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, const bits_t *value);
void UVMC_set_config_string (const char* context, const char* inst_name,
const char* field_name, const char* value);
bool UVMC_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 *value);
bool UVMC_get_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, bits_t* bits);
bool UVMC_get_config_string (const char* context, const char* inst_name,
const char* field_name, const char** value);
void UVMC_raise_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_drop_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_print_factory (int all_types=1);
void UVMC_set_factory_inst_override
(const char* original_type_name,
const char* override_type_name,
const char* full_inst_path);
void UVMC_set_factory_type_override (const char* original_type_name,
const char* override_type_name,
bool replace=1);
void UVMC_debug_factory_create (const char* requested_type,
const char* context="");
void UVMC_find_factory_override (const char* requested_type,
const char* context,
const char** override_type_name);
int UVMC_wait_for_phase_request(const char *phase, int state, int op);
void UVMC_get_uvm_version(unsigned int *major, unsigned int *minor, char **fix);
bool SV2C_phase_notification(int id);
bool SV2C_sv_ready();
void uvmc_set_scope(); // internal
} // extern "C"
extern "C" {
//------------------------------------------------------------------------------
// Group: Topology
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_topology
//
// Prints the current UVM testbench topology.
//
// If called prior to UVM completing the build phase,
// the topology will be incomplete.
//
// Arguments:
//
// context - The hierarchical path of the component from which to start printing
// topology. If unspecified, topology printing will begin at
// uvm_top. Multiple components can be specified by using glob
// wildcards (* and ?), e.g. "top.env.*.driver". You can also specify
// a POSIX extended regular expression by enclosing the contxt in
// forward slashes, e.g. "/a[hp]b/". Default: "" (uvm_top)
//
// depth - The number of levels of hierarchy to print. If not specified,
// all levels of hierarchy starting from the given context are printed.
// Default: -1 (recurse all children)
//------------------------------------------------------------------------------
//
void uvmc_print_topology (const char *context="", int depth=-1);
//------------------------------------------------------------------------------
// Group: Reporting
//
// The reporting API provides the ability to issue UVM reports, set verbosity,
// and other reporting features.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_report_enabled
//
// Returns true if a report at the specified verbosity, severity, and id would
// be emitted if made within the specified component contxt.
//
// The primary purpose of this command is to determine whether a report has a
// chance of being emitted before incurring the high run-time overhead of
// formatting the string message.
//
// A report at severity UVM_INFO is ignored if its verbosity is greater than
// the verbosity configured for the component in which it is issued. Reports at
// other severities are not affected by verbosity settings.
//
// If the action of a report with the specified severity and id is configured
// as UVM_NO_ACTION within the specified component contxt.
//
// Filtration by any registered report_catchers is not considered.
//
// Arguments:
//
// verbosity - The uvmc_report_verbosity of the hypothetical report.
//
// severity - The <uvmc_report_severity> of the hypothetical report.
// Default: UVM_INFO.
//
// id - The identifier string of the hypothetical report. Must be an
// exact match. If not specified, then uvmc_report_enabled checks
// only if UVM_NO_ACTION is the configured action for the given
// severity at the specified context. Default: "" (unspecified)
//
// context - The hierarchical path of the component that would issue the
// hypothetical report. If not specified, the context is global,
// i.e. uvm_top. Reports not issued by components come from uvm_top.
// Default: "" (unspecified)
//
// Example:
//
//| if (uvmc_report_enabled(UVM_HIGH, UVM_INFO, "PRINT_TRANS") {
//| string detailed_msg;
//| ...prepare message string here...
//| uvmc_report(UVM_INFO, "PRINT_TRANS", detailed_msg, UVM_HIGH);
//| }
//------------------------------------------------------------------------------
//
bool uvmc_report_enabled (int verbosity,
int severity=UVM_INFO,
const char* id="",
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_set_report_verbosity
//
// Sets the run-time verbosity level for all UVM_INFO-severity reports issued
// by the component(s) at the specified context. Any report from the component
// context whose verbosity exceeds this maximum will be ignored.
//
// Reports issued by SC via uvmc_report are affected only by the verbosity level
// setting for the global context, i.e. context="". To have finer-grained
// control over SC-issued reports, register a uvm_report_catcher with uvm_top.
//
// Arguments:
//
// level - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component. Multiple components can be
// specified by using glob wildcards * and ?, e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// recurse - If true, sets the verbosity of all descendents of the component(s)
// matching context. Default:false
//
// Examples:
//
// Set global UVM report verbosity to maximum (FULL) output:
//
// | uvmc_set_report_verbosity(UVM_FULL);
//
// Disable all filterable INFO reports for the top.env.agent1.driver,
// but none of its children:
//
// | uvmc_set_report_verbosity(UVM_NONE, "top.env.agent1.driver");
//
// Set report verbosity for all components to UVM_LOW, except for the
// troublemaker component, which gets UVM_HIGH verbosity:
//
// | uvmc_set_report_verbosity(UVM_LOW, true);
// | uvmc_set_report_verbosity(UVM_HIGH, "top.env.troublemaker");
//
// In the last example, the recursion flag is set to false, so all of
// troublemaker's children, if any, will remain at UVM_LOW verbosity.
//------------------------------------------------------------------------------
void uvmc_set_report_verbosity (int level,
const char* context="",
bool recurse=0);
//------------------------------------------------------------------------------
// Function: uvmc_report
//
// Send a report to UVM for processing, subject to possible filtering by
// verbosity, action, and active report catchers.
//
// See uvmc_report_enabled to learn how a report may be filtered.
//
// The UVM report mechanism is used instead of $display and other ad hoc
// approaches to ensure consistent output and to control whether a report is
// issued and what if any actions are taken when it is issued. All reporting
// methods have the same arguments, except a verbosity level is applied to
// UVM_INFO-severity reports.
//
// Arguments:
//
// severity - The report severity: specify either UVM_INFO, UVM_WARNING,
// UVM_ERROR, or UVM_FATAL. Required argument.
//
// id - The report id string, used for identification and targeted
// filtering. See context description for details on how the
// report's id affects filtering. Required argument.
//
// message - The message body, pre-formatted if necessary to a single string.
// Required.
//
// verbosity - The verbosity level indicating an INFO report's relative detail.
// Ignored for warning, error, and fatal reports. Specify UVM_NONE,
// UVM_LOW, UVM_MEDIUM, UVM_HIGH, or UVM_FULL. Default: UVM_MEDIUM.
//
// context - The hierarchical path of the SC-side component issuing the
// report. The context string appears as the hierarchical name in
// the report on the SV side, but it does not play a role in report
// filtering in all cases. All SC-side reports are issued from the
// global context in UVM, i.e. uvm_top. To apply filter settings,
// make them from that context, e.g. uvm_top.set_report_id_action().
// With the context fixed, only the report's id can be used to
// uniquely identify the SC report to filter. Report catchers,
// however, are passed the report's context and so can filter based
// on both SC context and id. Default: "" (unspecified)
//
// filename - The optional filename from which the report was issued. Use
// __FILE__. If specified, the filename will be displayed as part
// of the report. Default: "" (unspecified)
//
// line - The optional line number within filename from which the report
// was issued. Use __LINE__. If specified, the line number will be
// displayed as part of the report. Default: 0 (unspecified)
//
// Examples:
//
// Send a global (uvm_top-sourced) info report of medium verbosity to UVM:
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready");
//
// Issue the same report, this time with low verbosity a filename and line number.
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready",
// | UVM_LOW, "", __FILE__, __LINE__);
//
// UVM_LOW verbosity does not mean lower output. On the contrary, reports with
// UVM_LOW verbosity are printed if the run-time verbosity setting is anything
// but UVM_NONE. Reports issued with UVM_NONE verbosity cannot be filtered by
// the run-time verbosity setting.
//
// The next example sends a WARNING and INFO report from an SC-side producer
// component. In SV, we disable the warning by setting the action for its
// effective ID to UVM_NO_ACTION. We also set the verbosity threshold for INFO
// messages with the effective ID to UVM_NONE. This causes the INFO report to
// be filtered, as the run-time verbosity for reports of that particular ID are
// now much lower than the reports stated verbosity level (UVM_HIGH).
//
//| class producer : public sc_module {
//| ...
//| void run_thread() {
//| ...
//| uvmc_report(UVM_WARNING, "TransEvent",
//| "Generated error transaction.",, this.name());
//| ...
//| uvmc_report(UVM_INFO, "TransEvent",
//| "Transaction complete.", UVM_HIGH, this.name());
//| ...
//| }
//| };
//
// To filter SC-sourced reports on the SV side:
//
//| uvm_top.set_report_id_action("TransEvent@top/prod",UVM_NO_ACTION);
//| uvm_top.set_report_id_verbosity("TransEvent@top/prod",UVM_NONE);
//| uvm_top.set_report_id_verbosity("TransDump",UVM_NONE);
//
|
// The last statement disables all reports to the global context (uvm_top)
// having the ID "TransDump". Note that it is currently not possible to
// set filters for reports for several contexts at once using wildcards. Also,
// the hierarchical separator for SC may be configurable in your simulator, and
// thus could affect the context provided to these commands.
//------------------------------------------------------------------------------
void uvmc_report (int severity,
const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_info
//
// Equivalent to <uvmc_report> (UVM_INFO, ...)
void uvmc_report_info (const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_warning
//
// Equivalent to <uvmc_report> (UVM_WARNING, ...)
void uvmc_report_warning (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_error
//
// Equivalent to <uvmc_report> (UVM_ERROR, ...)
void uvmc_report_error (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_fatal
//
// Equivalent to <uvmc_report> (UVM_FATAL, ...)
void uvmc_report_fatal (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
//------------------------------------------------------------------------------
// Topic: Report Macros
//
// Convenience macros to <uvmc_report>.
// See <uvmc_report> for details on macro arguments.
//
// | UVMC_INFO (ID, message, verbosity, context)
// | UVMC_WARNING (ID, message, context)
// | UVMC_ERROR (ID, message, context)
// | UVMC_FATAL (ID, message, context)
//
//
// Before sending the report, the macros first call <uvmc_report_enabled> to
// avoid sending the report at all if its verbosity or action would prevent
// it from reaching the report server. If the report is enabled, then
// <uvmc_report> is called with the filename and line number arguments
// provided for you.
//
// Invocations of these macros must be terminated with semicolons, which is
// in keeping with the SystemC convention established for the ~SC_REPORT~
// macros. Future releases may provide a UVMC sc_report_handler that you
// can use to redirect all SC_REPORTs to UVM.
//
// Example:
//
//| UVMC_ERROR("SC_TOP/NO_CFG","Missing required config object", name());
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Group: Phasing
//
// An API that provides access UVM's phase state and the objection objects used
// to control phase progression.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_wait_for_phase
//
// Wait for a UVM phase to reach a certain state.
//
// The call must be made from a SystemC process thread that is either statically
// declared via SC_THREAD or dynamically started via sc_spawn. If the latter,
// you must include the following define on the sccom command
// line: -DSC_INCLUDE_DYNAMIC_PROCESSES.
//
// Arguments:
//
// phase - The name of the phase to wait on. The built-in phase names are, in
// order of execution: build, connect, end_of_elaboration,
// start_of_simulation, run, extract, check, report. The fine-grained
// run-time phases, which run in parallel with the run phase, are, in
// order: pre_reset, reset, post_reset, pre_configure, configure,
// post_configure, pre_main, main, post_main, pre_shutdown, shutdown,
// and post_shutdown.
//
// state - The state to wait on. A phase may transition through
// ~UVM_PHASE_JUMPING~ instead of UVM_PHASE_READY_TO_END if its
// execution had been preempted by a phase jump operation. Phases
// execute in the following state order:
//
// | UVM_PHASE_STARTED
// | UVM_PHASE_EXECUTING
// | UVM_PHASE_READY_TO_END | UVM_PHASE_JUMPING
// | UVM_PHASE_ENDED
// | UVM_PHASE_DONE
//
// condition - The state condition to wait for. When state is
// ~UVM_PHASE_JUMPING~, ~condition~ must be UVM_EQ. Default is
// ~UVM_EQ~. Valid values are:
//
// | UVM_LT - Phase is before the given state.
// | UVM_LTE - Phase is before or at the given state.
// | UVM_EQ - Phase is at the given state.
// | UVM_GTE - Phase is at or after the given state.
// | UVM_GT - Phase is after the given state.
// | UVM_NE - Phase is not at the given state.
//
//
// Examples:
//
// The following example shows how to spawn threads that correspond to UVM's
// phases. Here, the ~run_phase~ method executes during the UVM's run phase.
// As any UVM component executing the run phase would do, the SC component's
// ~run_phase~ process prevents the UVM (SV-side) run phase from ending until
// it is finished by calling <uvmc_drop_objection>.
//
//| SC_MODULE(top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top) {
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| };
//|
//| void async_reset() {
//| if (run_proc != null && run_proc.valid())
//| run_proc.reset(SC_INCLUDE_DESCENDANTS);
//| }
//|
//| void run_phase() {
//| uvmc_wait_for_phase("run",UVM_PHASE_STARTED,UVM_EQ);
//| uvmc_raise_objection("run","","SC run_phase executing");
//| ...
//| uvmc_drop_objection("run","","SC run_phase finished");
//| }
//| };
//
// If ~async_reset~ is called, the run_proc process and all descendants are
// killed, then run_proc is restarted. The run_proc calls run_phase again,
// which first waits for the UVM to reach the run_phase before resuming
// its work.
//------------------------------------------------------------------------------
void uvmc_wait_for_phase(const char *phase,
uvmc_phase_state state,
uvmc_wait_op op=UVM_EQ);
//------------------------------------------------------------------------------
// Function: uvmc_raise_objection
void uvmc_raise_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
// Function: uvmc_drop_objection
//
// Raise or drop an objection to ending the specified phase on behalf of the
// component at a given context. Raises can be made before the actual phase is
// executing. However, drops that move the objection count to zero must be
// avoided until the phase is actually executing, else the all-dropped
// condition will occur prematurely. Typical usage includes calling
// <uvmc_wait_for_phase>.
// Arguments:
//
// name - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component on whose behalf the
// specified objection is raised or dropped. Wildcards or regular
// expressions are not allowed. The context must exactly match an
// existing component's hierarchical name. Default: "" (uvm_top)
//
// description - The reason for raising or dropping the objection. This string
// is passed in all callbacks and printed when objection tracing is
// turned on. Default: ""
//
// count - The number of objections to raise or drop. Default: 1
//
// Examples:
//
// The following routine will force the specified UVM task phase to last at
// minimum number of nanoseconds, assuming SystemC and SystemVerilog are
// operating on the same timescale.
//
//| void set_min_phase_duration(const char* ph_name, sc_time min_time) {
//| uvmc_wait_for_phase(ph_name, UVM_PHASE_STARTED);
//| uvmc_raise_objection(ph_name,"","Forcing minimum run time");
//| wait(min_time);
//| uvmc_drop_objection(ph_name,"","Phase met minimum run time");
//| }
//
// Use directly as a blocking call, or use in non-blocking fashion with
// sc_spawn/sc_bind:
//
//| sc_spawn(sc_bind(&top:set_min_phase_duration, // <--func pointer
//| this,"run",sc_time(100,SC_NS)),"min_run_time");
//------------------------------------------------------------------------------
void uvmc_drop_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
//------------------------------------------------------------------------------
// Group: Factory
//
// This API provides access to UVM's object and component factory.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_factory
//
// Prints the state of the UVM factory, including registered types, instance
// overrides, and type overrides.
//
// Arguments:
//
// all_types - When all_types is 0, only type and instance overrides are
// displayed. When all_types is 1 (default), all registered
// user-defined types are printed as well, provided they have type
// names associated with them. (Parameterized types usually do not.)
// When all_types is 2, all UVM types (prefixed with uvm_) are
// included in the list of registered types.
//
// Examples:
//
// Print all type and instance overrides in the factory.
//
//| uvmc_print_factory(0);
//
// Print all type and instance overrides, plus all registered user-defined
// types.
//
//| uvmc_print_factory(1);
//
// Print all type and instance overrides, plus all registered types, including
// UVM types.
//
//| uvmc_print_factory(2);
//------------------------------------------------------------------------------
void uvmc_print_factory (int all_types=1);
//------------------------------------------------------------------------------
// Function: uvmc_set_factory_type_override
void uvmc_set_factory_type_override (const char* original_type,
const char* override_type,
bool replace=1);
// Function: uvmc_set_factory_inst_override
//
// Set a type or instance override. Instance overrides take precedence over
// type overrides. All specified types must have been registered with the
// factory.
//
// Arguments:
//
// requested_type - The name of the requested type.
//
// override_type - The name of the override type. Must be an extension of the
// requested_type.
//
// context - The hierarchical path of the component. Multiple components
// can be specified by using glob wildcards (* and ?), e.g.
// "top.env.*.driver". You can also specify a POSIX extended
// regular expression by enclosing the context string in
// forward slashes, e.g. "/a[hp]b/".
//
// replace - If true, replace any existing type override. Default: true
//
// Examples:
//
// The following sets an instance override in the UVM factory. Any component
// whose inst path matches the glob expression "e.*" that requests an object
// of type scoreboard_base (i.e. scoreboard_base:type_id::create) will instead
// get an object of type scoreboard.
//
//| uvmc_set_factory_inst_override("scoreboard_base","scoreboard","e.*");
//
// The following sets a type override in the UVM factory. Any component whose
// hierarchical path matches the glob expression "e.*" that requests an
// object of type producer_base (i.e. producer_base:type_id::create) will
// instead get an object of type producer.
//
//| uvmc_set_factory_type_override("producer_base","producer");
//
// The following sets an override chain. Given any request for an atype, a
// ctype object is returned, except for the component with hierarchical name
// "e.prod", which will get a dtype.
//
//| uvmc_set_factory_type_override("atype","btype");
//| uvmc_set_factory_type_override("btype","ctype");
//| uvmc_set_factory_inst_override("ctype","dtype","e.prod");
//------------------------------------------------------------------------------
void uvmc_set_factory_inst_override (const char* original_type,
const char* override_type,
const char* context);
//------------------------------------------------------------------------------
// Function: uvmc_debug_factory_create
//
// Display detailed information about the object type the UVM factory would
// create given a requested type and context, listing each override that was
// applied to arrive at the result.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the object to be created, which is a
// concatenation of the parent's hierarchical name with the
// name of the object being created. Wildcards or regular
// expressions are not allowed. The context must exactly match
// an existing component's hierarchical name, or can be the
// empty string to specify global context.
//
// Example:
//
// The following example answers the question: If the component at
// hierarchical path ~env.agent1.scoreboard~ requested an object of type
// scoreboard_base, what are all the applicable overrides, and which of
// those were applied to arrive at the result?
//
//| uvmc_debug_factory_create("scoreboard_base","env.agent1.scoreboard");
//------------------------------------------------------------------------------
void uvmc_debug_factory_create (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_find_factory_override
//
// Returns the type name of the type that would be created by the factory given
// the requested type and context.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the component that would make the
// request. Wildcards or regular expressions are not allowed.
// The context must exactly match an existing component's
// hierarchical name, or can be the empty string to specify
// global context.
//
// Examples:
//
// The following examples assume all types, A through D, have been registered
// with the UVM factory. Given the following overrides:
//
//| uvmc_set_type_override("B","C");
//| uvmc_set_type_override("A","B");
//| uvmc_set_inst_override("D", "C", "top.env.agent1.*");
//
// The following will display "C":
//
//| $display(uvmc_find_factory_override("A"));
//
// The following will display "D":
//
//| $display(uvmc_find_factory_override("A", "top.env.agent1.driver"));
//
// The returned string can be used in subsequent calls to
// <uvmc_set_factory_type_override> and <uvmc_set_factory_inst_override>.
//------------------------------------------------------------------------------
string uvmc_find_factory_override (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Group: set_config
//------------------------------------------------------------------------------
//
// Creates or updates a configuration setting for a field at a specified
// hierarchical context.
//
// These functions establish configuration settings, storing them as resource
// entries in the resource database for later lookup by get_config calls. They
// do not directly affect the field values being targeted. As the component
// hierarchy is being constructed during UVM's build phase, components
// spring into existence and establish their context. Once its context is
// known, each component can call get_config to retrieve any configuration
// settings that apply to it.
//
// The context is specified as the concatenation of two arguments, context and
// inst_name, which are separated by a "." if both context and inst_name are
// not empty. Both context and inst_name may be glob style or regular
// expression style expressions.
//
// The name of the configuration parameter is specified by the ~field_name~
// argument.
//
// The semantic of the set methods is different when UVM is in the build phase
// versus any other phase. If a set call is made during the build phase, the
// context determines precedence in the database. A set call from a higher
// level in the hierarchy (e.g. mytop.test1) has precedence over a set call to
// the same field from a lower level (e.g. mytop.test1.env.agent). Set calls
// made at the same level of hierarchy have equal precedence, so each set call
// overwrites the field value from a previous set call.
//
// After the build phase, all set calls have the same precedence regardless of
// their hierarchical context. Each set call overwrites the value of the
// previous call.
//
// Arguments:
//
// type_name - For uvmc_set_config_object only. Specifies the type name of the
// equivalent object to set in SV. UVM Connect will utilize the
// factory to allocate an object of this type and unpack the
// serialized value into it. Parameterized classes are not
// supported.
//
// context - The hierarchical path of the component, or the empty string,
// which specifies uvm_top. Multiple components can be specified
// by using glob wildcards (* and ?), e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// inst_name - The instance path of the object being configured, relative to
// the specified context(s). Can contain wildcards or be a
// regular expression.
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it.
// Use of the converter convenience macros is acceptable for
// meeting this requirement.
//
// Examples:
//
// The following example sets the configuration object field at path
// "e.prod.trans" to the tr instance, which is type uvm_tlm_generic_payload.
//
//| uvmc_set_config_object("uvm_tlm_generic_payload","e.prod","","trans", tr);
//
// The next example sets the string property at hierarchical path
// "e.prod.message" to "Hello from SystemC!".
//
//| uvmc_set_config_string ("e.prod", "", "message", "Hello from SystemC!");
//
// The next example sets the integral property at hierarchical path
// "e.prod.start_addr" to hex 0x1234.
//
//| uvmc_set_config_int ("e.prod", "", "start_addr", 0x1234);
//--------------------------
|
----------------------------------------------------
// Function: uvmc_set_config_int
//
// Set an integral configuration value
//
void uvmc_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
// Function: uvmc_set_config_string
//
// Set a string configuration value
//
void uvmc_set_config_string (const char* context, const char* inst_name,
const char* field_name, const string& value);
} // extern "C"
namespace uvmc {
// Function: uvmc_set_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
CVRT::do_pack(value,packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
// Function: uvmc_set_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
uvmc_converter<T>::do_pack(value,*packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
} // namespace uvmc
extern "C" {
//------------------------------------------------------------------------------
// Group: get_config
//------------------------------------------------------------------------------
//
// Gets a configuration field ~value~ at a specified hierarchical ~context~.
// Returns true if successful, false if a configuration setting could not be
// found at the given ~context~. If false, the ~value~ reference is unmodified.
//
// The ~context~ specifies the starting point for a search for a configuration
// setting for the field made at that level of hierarchy or higher. The
// ~inst_name~ is an explicit instance name relative to context and may be an
// empty string if ~context~ is the full context that the configuration
// setting applies to.
//
// The ~context~ and ~inst_name~ strings must be simple strings--no wildcards
// or regular expressions.
//
// See the section on <set_config> for the semantics
// that apply when setting configuration.
//
// Arguments:
//
// type_name - For <uvmc_get_config_object> only. Specifies the type name
// of the equivalent object to retrieve in SV. UVM Connect
// will check that the object retrieved from the configuration
// database matches this type name. If a match, the object is
// serialized (packed) and returned across the language
// boundary. Once on this side, the object data is unpacked
// into the object passed by reference via the value argument.
// Parameterized classes are not supported.
//
// context - The hierarchical path of the component on whose behalf the
// specified configuration is being retrieved. Wildcards or
// regular expressions are not allowed. The context must
// exactly match an existing component's hierarchical name,
// or be the empty string, which specifies uvm_top.
//
// inst_name - The instance path of the object being configured, relative
// to the specified context(s).
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it. Use
// of the converter convenience macros is acceptable for meeting
// this requirement. The equivalent class in SV must be based
// on uvm_object and registered with the UVM factory, i.e.
// contain a `uvm_object_utils macro invocation.
//
// Examples:
//
// The following example retrieves the uvm_tlm_generic_payload configuration
// property at hierarchical path "e.prod.trans" into tr2.
//
//| uvmc_get_config_object("uvm_tlm_generic_payload","e","prod","trans", tr2);
//
// The context specification is split between the context and inst_name
// arguments. Unlike setting configuration, there is no semantic difference
// between the context and inst_name properties. When getting configuration,
// the full context is always the concatenation of the context, ".", and
// inst_name. The transaction tr2 will effectively become a copy of the
// object used to set the configuration property.
//
// The next example retrieves the string property at hierarchical path
// "e.prod.message" into local variable str.
//
//| uvmc_get_config_string ("e", "prod", "message", str);
//
// The following example retrieves the integral property at hierarchical path
// "e.prod.start_addr" into the local variable, saddr.
//
//| uvmc_get_config_int ("e.prod", "", "start_addr", saddr);
//------------------------------------------------------------------------------
// Function: uvmc_get_config_int
//
// Set an integral configuration value.
//
bool uvmc_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 &value);
// Function: uvmc_get_config_string
//
// Set a string configuration value.
//
bool uvmc_get_config_string (const char* context, const char* inst_name,
const char* field_name, string &value);
} // extern "C"
namespace uvmc {
// Function: uvmc_get_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
CVRT::do_unpack(value,packer);
return 1;
}
return 0;
}
// Function: uvmc_get_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
uvmc_converter<T>::do_unpack(value,*packer);
return 1;
}
return 0;
}
} // namespace uvmc
#endif // UVMC_COMMANDS_H
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_10_H_
#define _design_1_xlconstant_0_10_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_10 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_10 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (ALU) {
sc_in <sc_int<8>> in1; // A
sc_in <sc_int<8>> in2; // B
sc_in <bool> c; // Carry Out // in this project, this signal is always 1
// ALUOP // has 5 bits by merging: opselect (4bits) and first LSB bit of opcode (1bit)
sc_in <sc_uint<5>> aluop;
sc_in <sc_uint<3>> sa; // Shift Amount
sc_out <sc_int<8>> out; // Output
/*
** module global variables
*/
//
SC_CTOR (ALU){
SC_METHOD (process);
sensitive << in1 << in2 << aluop;
}
void process () {
sc_int<8> a = in1.read();
sc_int<8> b = in2.read();
bool cin = c.read();
sc_uint<5> op = aluop.read();
sc_uint<3> sh = sa.read();
switch (op){
case 0b00000 :
out.write(a);
break;
case 0b00001 :
out.write(++a);
break;
case 0b00010 :
out.write(a+b);
break;
case 0b00011 :
out.write(a+b+cin);
break;
case 0b00100 :
out.write(a-b);
break;
case 0b00101 :
out.write(a-b-cin);
break;
case 0b00110 :
out.write(--a);
break;
case 0b00111 :
out.write(b);
break;
case 0b01000 :
case 0b01001 :
out.write(a&b);
break;
case 0b01010 :
case 0b01011 :
out.write(a|b);
break;
case 0b01100 :
case 0b01101 :
out.write(a^b);
break;
case 0b01110 :
case 0b01111 :
out.write(~a);
break;
case 0b10000 :
case 0b10001 :
case 0b10010 :
case 0b10011 :
case 0b10100 :
case 0b10101 :
case 0b10110 :
case 0b10111 :
out.write(a>>sh);
break;
default:
out.write(a<<sh);
break;
}
}
};
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_10_H_
#define _design_1_xlconstant_0_10_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_10 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_10 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_10_H_
#define _design_1_xlconstant_0_10_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_10 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_10 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_10_H_
#define _design_1_xlconstant_0_10_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_10 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_10 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../river_cfg.h"
#include "../types_river.h"
namespace debugger {
SC_MODULE(ic_dport) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// DMI connection
sc_in<sc_uint<CFG_LOG2_CPU_MAX>> i_hartsel; // Selected hart index
sc_in<bool> i_haltreq;
sc_in<bool> i_resumereq;
sc_in<bool> i_resethaltreq; // Halt core after reset request
sc_in<bool> i_hartreset; // Reset currently selected hart
sc_in<bool> i_dport_req_valid; // Debug access from DSU is valid
sc_in<sc_uint<DPortReq_Total>> i_dport_req_type; // Debug access types
sc_in<sc_uint<RISCV_ARCH>> i_dport_addr; // Register index
sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Write value
sc_in<sc_uint<3>> i_dport_size; // 0=1B;1=2B;2=4B;3=8B;4=128B
sc_out<bool> o_dport_req_ready; // Response is ready
sc_in<bool> i_dport_resp_ready; // ready to accept response
sc_out<bool> o_dport_resp_valid; // Response is valid
sc_out<bool> o_dport_resp_error; // Something goes wrong
sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Response value or error code
// To Cores cluster
sc_vector<sc_out<dport_in_type>> o_dporti;
sc_vector<sc_in<dport_out_type>> i_dporto;
void comb();
void registers();
SC_HAS_PROCESS(ic_dport);
ic_dport(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const uint8_t ALL_CPU_MASK = ((1 << CFG_CPU_MAX) - 1);
struct ic_dport_registers {
sc_signal<sc_uint<CFG_LOG2_CPU_MAX>> hartsel;
} v, r;
void ic_dport_r_reset(ic_dport_registers &iv) {
iv.hartsel = 0;
}
};
} // namespace debugger
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_PROTOCOLS_GPIO_H
#define VCML_PROTOCOLS_GPIO_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
#include "vcml/core/module.h"
#include "vcml/protocols/base.h"
namespace vcml {
typedef size_t gpio_vector;
enum gpio_vectors : gpio_vector {
GPIO_NO_VECTOR = SIZE_MAX,
};
struct gpio_payload {
gpio_vector vector;
bool state;
};
ostream& operator<<(ostream& os, const gpio_payload& gpio);
class gpio_fw_transport_if : public sc_core::sc_interface
{
public:
typedef gpio_payload protocol_types;
virtual void gpio_transport(gpio_payload& tx) = 0;
};
class gpio_bw_transport_if : public sc_core::sc_interface
{
public:
typedef gpio_payload protocol_types;
};
class gpio_base_initiator_socket;
class gpio_base_target_socket;
class gpio_initiator_socket;
class gpio_target_socket;
class gpio_initiator_stub;
class gpio_target_stub;
class gpio_initiator_adapter;
class gpio_target_adapter;
class gpio_host
{
public:
gpio_host() = default;
virtual ~gpio_host() = default;
virtual void gpio_transport(const gpio_target_socket&, gpio_payload&) = 0;
};
typedef multi_initiator_socket<gpio_fw_transport_if, gpio_bw_transport_if>
gpio_base_initiator_socket_b;
typedef multi_target_socket<gpio_fw_transport_if, gpio_bw_transport_if>
gpio_base_target_socket_b;
class gpio_base_initiator_socket : public gpio_base_initiator_socket_b
{
private:
gpio_target_stub* m_stub;
gpio_target_adapter* m_adapter;
public:
gpio_base_initiator_socket(const char*, address_space = VCML_AS_DEFAULT);
virtual ~gpio_base_initiator_socket();
VCML_KIND(gpio_base_initiator_socket);
using gpio_base_initiator_socket_b::bind;
virtual void bind(gpio_base_target_socket& socket);
virtual void bind(sc_signal_inout_if<bool>& signal);
bool is_adapted() const { return m_adapter != nullptr; }
bool is_stubbed() const { return m_stub != nullptr; }
void stub();
};
class gpio_base_target_socket : public gpio_base_target_socket_b
{
private:
gpio_initiator_stub* m_stub;
gpio_initiator_adapter* m_adapter;
public:
gpio_base_target_socket(const char*, address_space = VCML_AS_DEFAULT);
virtual ~gpio_base_target_socket();
VCML_KIND(gpio_base_target_socket);
using gpio_base_target_socket_b::bind;
virtual void bind(gpio_base_initiator_socket& other);
virtual void bind(sc_signal_inout_if<bool>& signal);
virtual void complete_binding(gpio_base_initiator_socket& socket) {}
bool is_adapted() const { return m_adapter != nullptr; }
bool is_stubbed() const { return m_stub != nullptr; }
void stub();
};
using gpio_base_initiator_array = socket_array<gpio_base_initiator_socket>;
using gpio_base_target_array = socket_array<gpio_base_target_socket>;
class gpio_initiator_socket : public gpio_base_initiator_socket
{
public:
struct gpio_state_tracker : gpio_payload {
gpio_initiator_socket* parent;
bool read() const { return state; }
void write(bool val);
bool operator=(bool val);
bool operator|=(bool val);
bool operator&=(bool val);
bool operator^=(bool val);
operator bool() const { return read(); }
};
gpio_initiator_socket(const char* n, address_space a = VCML_AS_DEFAULT);
virtual ~gpio_initiator_socket();
VCML_KIND(gpio_initiator_socket);
const sc_event& default_event();
bool read(gpio_vector vector = GPIO_NO_VECTOR) const;
operator bool() const { return read(GPIO_NO_VECTOR); }
void write(bool state, gpio_vector vector = GPIO_NO_VECTOR);
void raise(gpio_vector vector = GPIO_NO_VECTOR);
void lower(gpio_vector vector = GPIO_NO_VECTOR);
void pulse(gpio_vector vector = GPIO_NO_VECTOR);
gpio_initiator_socket& operator=(bool set);
gpio_initiator_socket& operator|=(bool set);
gpio_initiator_socket& operator&=(bool set);
gpio_initiator_socket& operator^=(bool set);
gpio_state_tracker& operator[](gpio_vector vector);
private:
gpio_host* m_host;
sc_event* m_event;
unordered_map<gpio_vector, gpio_state_tracker> m_state;
struct gpio_bw_transport : public gpio_bw_transport_if {
mutable gpio_initiator_socket* socket;
gpio_bw_transport(gpio_initiator_socket* s):
gpio_bw_transport_if(), socket(s) {}
virtual const sc_event& default_event() const override {
return socket->default_event();
}
} m_transport;
void gpio_transport(gpio_payload& tx);
};
class gpio_target_socket : public gpio_base_target_socket
{
public:
gpio_target_socket(const char* nm, address_space as = VCML_AS_DEFAULT);
virtual ~gpio_target_socket();
VCML_KIND(gpio_target_socket);
using gpio_base_target_socket::bind;
virtual void bind(base_type& other) override;
virtual void complete_binding(gpio_base_initiator_socket& socket) override;
const sc_event& default_event();
bool read(gpio_vector vector = GPIO_NO_VECTOR) const;
bool operator[](gpio_vector vector) const { return read(vector); }
operator bool() const { return read(GPIO_NO_VECTOR); }
bool operator==(const gpio_target_socket& o) const;
bool operator!=(const gpio_target_socket& o) const;
private:
gpio_host* m_host;
sc_event* m_event;
unordered_map<gpio_vector, bool> m_state;
gpio_base_initiator_socket* m_initiator;
vector<gpio_base_target_socket*> m_targets;
struct gpio_fw_transport : public gpio_fw_transport_if {
mutable gpio_target_socket* socket;
gpio_fw_transport(gpio_target_socket* s):
gpio_fw_transport_if(), socket(s) {}
virtual void gpio_transport(gpio_payload& tx) override {
socket->gpio_transport_internal(tx);
}
virtual const sc_event& default_event() const override {
return socket->default_event();
}
} m_transport;
void gpio_transport_internal(gpio_payload& gpio);
protected:
virtual void gpio_transport(gpio_payload& gpio);
};
using gpio_initiator_array = socket_array<gpio_initiator_socket>;
using gpio_target_array = socket_array<gpio_target_socket>;
class gpio_initiator_stub : private gpio_bw_transport_if
{
public:
gpio_base_initiator_socket gpio_out;
gpio_initiator_stub(const char* nm);
virtual ~gpio_initiator_stub() = default;
};
class gpio_target_stub : private gpio_fw_transport_if
{
private:
virtual void gpio_transport(gpio_payload& tx) override;
public:
gpio_base_target_socket gpio_in;
gpio_target_stub(const char* nm);
virtual ~gpio_target_stub() = default;
};
class gpio_initiator_adapter : public module
{
public:
sc_in<bool> in;
gpio_initiator_socket out;
gpio_initiator_adapter(const sc_module_name& nm);
virtual ~gpio_initiator_adapter() = default;
VCML_KIND(gpio_initiator_adapter);
private:
void update();
};
class gpio_target_adapter : public module, public gpio_host
{
public:
gpio_target_socket in;
sc_out<bool> out;
gpio_target_adapter(const sc_module_name& nm);
virtual ~gpio_target_adapter() = default;
VCML_KIND(gpio_target_adapter);
private:
sc_event m_trigger;
void update();
virtual void gpio_transport(const gpio_target_socket& socket,
gpio_payload& tx) override;
};
gpio_base_initiator_socket& gpio_initiator(const sc_object& parent,
const string& port);
gpio_base_initiator_socket& gpio_initiator(const sc_object& parent,
const string& port, size_t idx);
gpio_base_target_socket& gpio_target(const sc_object& parent,
const string& port);
gpio_base_target_socket& gpio_target(const sc_object& parent,
const string& port, size_t idx);
void gpio_stub(const sc_object& obj, const string& port);
void gpio_stub(const sc_object& obj, const string& port, size_t idx);
void gpio_bind(const sc_object& obj1, const string& port1,
const sc_object& obj2, const string& port2);
void gpio_bind(const sc_object& obj1, const string& port1,
const sc_object& obj2, const string& port2, size_t idx2);
void gpio_bind(const sc_object& obj1, const string& port1, size_t idx1,
const sc_object& obj2, const string& port2);
void gpio_bind(const sc_object& obj1, const string& port1, size_t idx1,
const sc_object& obj2, const string& port2, size_t idx2);
void gpio_bind(const sc_object& obj, const string& port,
sc_signal_inout_if<bool>& sig);
void gpio_bind(const sc_object& obj, const string& port, size_t idx,
sc_signal_inout_if<bool>& sig);
} // namespace vcml
#endif
|
#pragma once
#include <systemc.h>
#include <unordered_map>
#include "../../UTIL/debug_util.h"
#define RAM_SIZE 6000 //0xFFFF FFFF -> max size
SC_MODULE(RAM)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
sc_in<bool> WE_I;
sc_in<sc_uint<2>> MEM_SIZE;
sc_out<sc_uint<32>> DAT_O;
//signals
sc_signal<sc_uint<4>> current_state;
sc_signal<sc_uint<4>> future_state;
std::unordered_map<int,int>* RAM_REGISTERS;
void init_mem(std::unordered_map<int,int>*);
void reponse();
void trace(sc_trace_file*);
SC_CTOR(RAM)
{
SC_METHOD(reponse);
sensitive << CLK.neg();
}
};
|
#ifndef TESTBENCH_VBASE_H
#define TESTBENCH_VBASE_H
#include <systemc.h>
#include "verilated.h"
#include "verilated_vcd_sc.h"
#define verilator_trace_enable(vcd_filename, dut) \
if (waves_enabled()) \
{ \
Verilated::traceEverOn(true); \
VerilatedVcdC *v_vcd = new VerilatedVcdC; \
sc_core::sc_time delay_us; \
if (waves_delayed(delay_us)) \
dut->trace_enable (v_vcd, delay_us); \
else \
dut->trace_enable (v_vcd); \
v_vcd->open (vcd_filename); \
this->m_verilate_vcd = v_vcd; \
}
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
class testbench_vbase: public sc_module
{
public:
sc_in <bool> clk;
sc_in <bool> rst;
virtual void set_testcase(int tc) { }
virtual void set_delays(bool en) { }
virtual void set_iterations(int iterations) { }
virtual void set_argcv(int argc, char* argv[]) { }
virtual void process(void) { while (1) wait(); }
virtual void monitor(void) { while (1) wait(); }
SC_HAS_PROCESS(testbench_vbase);
testbench_vbase(sc_module_name name): sc_module(name)
{
SC_CTHREAD(process, clk);
SC_CTHREAD(monitor, clk);
}
virtual void add_trace(sc_trace_file * fp, std::string prefix) { }
virtual void abort(void)
{
cout << "TB: Aborted at " << sc_time_stamp() << endl;
if (m_verilate_vcd)
{
m_verilate_vcd->flush();
m_verilate_vcd->close();
m_verilate_vcd = NULL;
}
}
bool waves_enabled(void)
{
char *s = getenv("ENABLE_WAVES");
if (s && !strcmp(s, "no"))
return false;
else
return true;
}
bool waves_delayed(sc_core::sc_time &delay)
{
char *s = getenv("WAVES_DELAY_US");
if (s != NULL)
{
uint32_t us = strtoul(s, NULL, 0);
printf("WAVES: Delay start until %duS\n", us);
delay = sc_core::sc_time(us, SC_US);
return true;
}
else
return false;
}
std::string getenv_str(std::string name, std::string defval)
{
char *s = getenv(name.c_str());
if (!s || (s && !strcmp(s, "")))
return defval;
else
return std::string(s);
}
protected:
VerilatedVcdC *m_verilate_vcd;
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _convolve_kernel_HH_
#define _convolve_kernel_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "aesl_mux_load_7_3_x_s.h"
#include "aesl_mux_load_5_3_x_s.h"
#include "convolve_kernel_fbkb.h"
#include "convolve_kernel_fcud.h"
namespace ap_rtl {
struct convolve_kernel : public sc_module {
// Port declarations 97
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<32> > bufw_0_Addr_A;
sc_out< sc_logic > bufw_0_EN_A;
sc_out< sc_lv<4> > bufw_0_WEN_A;
sc_out< sc_lv<32> > bufw_0_Din_A;
sc_in< sc_lv<32> > bufw_0_Dout_A;
sc_out< sc_logic > bufw_0_Clk_A;
sc_out< sc_logic > bufw_0_Rst_A;
sc_out< sc_lv<32> > bufw_1_Addr_A;
sc_out< sc_logic > bufw_1_EN_A;
sc_out< sc_lv<4> > bufw_1_WEN_A;
sc_out< sc_lv<32> > bufw_1_Din_A;
sc_in< sc_lv<32> > bufw_1_Dout_A;
sc_out< sc_logic > bufw_1_Clk_A;
sc_out< sc_logic > bufw_1_Rst_A;
sc_out< sc_lv<32> > bufw_2_Addr_A;
sc_out< sc_logic > bufw_2_EN_A;
sc_out< sc_lv<4> > bufw_2_WEN_A;
sc_out< sc_lv<32> > bufw_2_Din_A;
sc_in< sc_lv<32> > bufw_2_Dout_A;
sc_out< sc_logic > bufw_2_Clk_A;
sc_out< sc_logic > bufw_2_Rst_A;
sc_out< sc_lv<32> > bufw_3_Addr_A;
sc_out< sc_logic > bufw_3_EN_A;
sc_out< sc_lv<4> > bufw_3_WEN_A;
sc_out< sc_lv<32> > bufw_3_Din_A;
sc_in< sc_lv<32> > bufw_3_Dout_A;
sc_out< sc_logic > bufw_3_Clk_A;
sc_out< sc_logic > bufw_3_Rst_A;
sc_out< sc_lv<32> > bufw_4_Addr_A;
sc_out< sc_logic > bufw_4_EN_A;
sc_out< sc_lv<4> > bufw_4_WEN_A;
sc_out< sc_lv<32> > bufw_4_Din_A;
sc_in< sc_lv<32> > bufw_4_Dout_A;
sc_out< sc_logic > bufw_4_Clk_A;
sc_out< sc_logic > bufw_4_Rst_A;
sc_out< sc_lv<32> > bufi_0_Addr_A;
sc_out< sc_logic > bufi_0_EN_A;
sc_out< sc_lv<4> > bufi_0_WEN_A;
sc_out< sc_lv<32> > bufi_0_Din_A;
sc_in< sc_lv<32> > bufi_0_Dout_A;
sc_out< sc_logic > bufi_0_Clk_A;
sc_out< sc_logic > bufi_0_Rst_A;
sc_out< sc_lv<32> > bufi_1_Addr_A;
sc_out< sc_logic > bufi_1_EN_A;
sc_out< sc_lv<4> > bufi_1_WEN_A;
sc_out< sc_lv<32> > bufi_1_Din_A;
sc_in< sc_lv<32> > bufi_1_Dout_A;
sc_out< sc_logic > bufi_1_Clk_A;
sc_out< sc_logic > bufi_1_Rst_A;
sc_out< sc_lv<32> > bufi_2_Addr_A;
sc_out< sc_logic > bufi_2_EN_A;
sc_out< sc_lv<4> > bufi_2_WEN_A;
sc_out< sc_lv<32> > bufi_2_Din_A;
sc_in< sc_lv<32> > bufi_2_Dout_A;
sc_out< sc_logic > bufi_2_Clk_A;
sc_out< sc_logic > bufi_2_Rst_A;
sc_out< sc_lv<32> > bufi_3_Addr_A;
sc_out< sc_logic > bufi_3_EN_A;
sc_out< sc_lv<4> > bufi_3_WEN_A;
sc_out< sc_lv<32> > bufi_3_Din_A;
sc_in< sc_lv<32> > bufi_3_Dout_A;
sc_out< sc_logic > bufi_3_Clk_A;
sc_out< sc_logic > bufi_3_Rst_A;
sc_out< sc_lv<32> > bufi_4_Addr_A;
sc_out< sc_logic > bufi_4_EN_A;
sc_out< sc_lv<4> > bufi_4_WEN_A;
sc_out< sc_lv<32> > bufi_4_Din_A;
sc_in< sc_lv<32> > bufi_4_Dout_A;
sc_out< sc_logic > bufi_4_Clk_A;
sc_out< sc_logic > bufi_4_Rst_A;
sc_out< sc_lv<32> > bufi_5_Addr_A;
sc_out< sc_logic > bufi_5_EN_A;
sc_out< sc_lv<4> > bufi_5_WEN_A;
sc_out< sc_lv<32> > bufi_5_Din_A;
sc_in< sc_lv<32> > bufi_5_Dout_A;
sc_out< sc_logic > bufi_5_Clk_A;
sc_out< sc_logic > bufi_5_Rst_A;
sc_out< sc_lv<32> > bufi_6_Addr_A;
sc_out< sc_logic > bufi_6_EN_A;
sc_out< sc_lv<4> > bufi_6_WEN_A;
sc_out< sc_lv<32> > bufi_6_Din_A;
sc_in< sc_lv<32> > bufi_6_Dout_A;
sc_out< sc_logic > bufi_6_Clk_A;
sc_out< sc_logic > bufi_6_Rst_A;
sc_out< sc_lv<32> > bufo_Addr_A;
sc_out< sc_logic > bufo_EN_A;
sc_out< sc_lv<4> > bufo_WEN_A;
sc_out< sc_lv<32> > bufo_Din_A;
sc_in< sc_lv<32> > bufo_Dout_A;
sc_out< sc_logic > bufo_Clk_A;
sc_out< sc_logic > bufo_Rst_A;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
convolve_kernel(sc_module_name name);
SC_HAS_PROCESS(convolve_kernel);
~convolve_kernel();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
aesl_mux_load_7_3_x_s* grp_aesl_mux_load_7_3_x_s_fu_316;
aesl_mux_load_5_3_x_s* grp_aesl_mux_load_5_3_x_s_fu_337;
convolve_kernel_fbkb<1,9,32,32,32>* convolve_kernel_fbkb_U7;
convolve_kernel_fcud<1,5,32,32,32>* convolve_kernel_fcud_U8;
sc_signal< sc_lv<51> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<3> > p_4_reg_294;
sc_signal< sc_lv<32> > temp1_reg_306;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_ap_return;
sc_signal< sc_lv<32> > reg_371;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage5;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< bool > ap_block_state15_pp0_stage5_iter0;
sc_signal< bool > ap_block_state55_pp0_stage5_iter1;
sc_signal< bool > ap_block_pp0_stage5_flag00011001;
sc_signal< sc_lv<1> > tmp_3_reg_912;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage10;
sc_signal< bool > ap_block_state20_pp0_stage10_iter0;
sc_signal< bool > ap_block_state60_pp0_stage10_iter1;
sc_signal< bool > ap_block_pp0_stage10_flag00011001;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage15;
sc_signal< bool > ap_block_state25_pp0_stage15_iter0;
sc_signal< bool > ap_block_pp0_stage15_flag00011001;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage20;
sc_signal< bool > ap_block_state30_pp0_stage20_iter0;
sc_signal< bool > ap_block_pp0_stage20_flag00011001;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage25;
sc_signal< bool > ap_block_state35_pp0_stage25_iter0;
sc_signal< bool > ap_block_pp0_stage25_flag00011001;
sc_signal< sc_lv<32> > grp_fu_367_p2;
sc_signal< sc_lv<32> > reg_376;
sc_signal< sc_lv<32> > reg_381;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage30;
sc_signal< bool > ap_block_state40_pp0_stage30_iter0;
sc_signal< bool > ap_block_pp0_stage30_flag00011001;
sc_signal< sc_lv<32> > grp_fu_361_p2;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage19;
sc_signal< bool > ap_block_state29_pp0_stage19_iter0;
sc_signal< bool > ap_block_pp0_stage19_flag00011001;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage27;
sc_signal< bool > ap_block_state37_pp0_stage27_iter0;
sc_signal< bool > ap_block_pp0_stage27_flag00011001;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage35;
sc_signal< bool > ap_block_state45_pp0_stage35_iter0;
sc_signal< bool > ap_block_pp0_stage35_flag00011001;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage3;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_state13_pp0_stage3_iter0;
sc_signal< bool > ap_block_state53_pp0_stage3_iter1;
sc_signal< bool > ap_block_pp0_stage3_flag00011001;
sc_signal< sc_lv<1> > ap_reg_pp0_iter1_tmp_3_reg_912;
sc_signal< sc_lv<7> > indvar_flatten_next2_fu_397_p2;
sc_signal< sc_lv<7> > indvar_flatten_next2_reg_767;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<1> > exitcond_flatten_fu_403_p2;
sc_signal< sc_lv<1> > exitcond_flatten_reg_772;
sc_signal< sc_lv<1> > exitcond_flatten2_fu_391_p2;
sc_signal< sc_lv<1> > exitcond_flatten1_fu_409_p2;
sc_signal< sc_lv<1> > exitcond_flatten1_reg_783;
sc_signal< sc_lv<1> > exitcond_flatten_mid_fu_432_p2;
sc_signal< sc_lv<1> > exitcond_flatten_mid_reg_789;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > tmp_8_mid1_fu_447_p2;
sc_signal< sc_lv<1> > tmp_8_mid1_reg_796;
sc_signal< sc_lv<2> > p_1_mid_fu_453_p3;
sc_signal< sc_lv<2> > p_1_mid_reg_802;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<1> > tmp_2_fu_460_p2;
sc_signal< sc_lv<1> > tmp_2_reg_808;
sc_signal< sc_lv<2> > p_2_mid_fu_464_p3;
sc_signal< sc_lv<2> > p_2_mid_reg_813;
sc_signal< sc_lv<2> > tmp_4_mid2_fu_477_p3;
sc_signal< sc_lv<2> > tmp_4_mid2_reg_819;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<2> > p_3_mid2_fu_497_p3;
sc_signal< sc_lv<2> > p_3_mid2_reg_827;
sc_signal< sc_lv<2> > tmp_7_mid2_fu_505_p3;
sc_signal< sc_lv<2> > tmp_7_mid2_reg_837;
sc_signal< sc_lv<6> > tmp_11_fu_540_p1;
sc_signal< sc_lv<6> > tmp_11_reg_844;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<4> > tmp_12_fu_544_p1;
sc_signal< sc_lv<4> > tmp_12_reg_849;
sc_signal< sc_lv<5> > bufo_addr_reg_854;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<2> > tmp_1_mid2_v_fu_580_p3;
sc_signal< sc_lv<2> > tmp_1_mid2_v_reg_859;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<6> > tmp_1_fu_601_p2;
sc_signal< sc_lv<6> > tmp_1_reg_868;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_lv<3> > tmp_7_cast_mid2_cast_fu_607_p1;
sc_signal< sc_lv<3> > tmp_7_cast_mid2_cast_reg_873;
sc_signal< sc_lv<3> > tmp_12_48_t_fu_610_p3;
sc_signal< sc_lv<3> > tmp_12_48_t_reg_883;
sc_signal< sc_lv<1> > sel_tmp_fu_617_p2;
sc_signal< sc_lv<1> > sel_tmp_reg_888;
sc_signal< sc_lv<1> > sel_tmp2_fu_622_p2;
sc_signal< sc_lv<1> > sel_tmp2_reg_896;
sc_signal< sc_lv<1> > sel_tmp4_fu_627_p2;
sc_signal< sc_lv<1> > sel_tmp4_reg_904;
sc_signal< sc_lv<1> > tmp_3_fu_632_p2;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< bool > ap_block_state10_pp0_stage0_iter0;
sc_signal< bool > ap_block_state50_pp0_stage0_iter1;
sc_signal< bool > ap_block_pp0_stage0_flag00011001;
sc_signal< sc_lv<3> > i_V_fu_638_p2;
sc_signal< sc_lv<3> > i_V_reg_916;
sc_signal< sc_lv<3> > tmp_9_fu_644_p2;
sc_signal< sc_lv<3> > tmp_9_reg_921;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage1;
sc_signal< bool > ap_block_state11_pp0_stage1_iter0;
sc_signal< bool > ap_block_state51_pp0_stage1_iter1;
sc_signal< bool > ap_block_pp0_stage1_flag00011001;
sc_signal< sc_lv<6> > tmp_16_fu_652_p2;
sc_signal< sc_lv<6> > tmp_16_reg_927;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage2;
sc_signal< bool > ap_block_state12_pp0_stage2_iter0;
sc_signal< bool > ap_block_state52_pp0_stage2_iter1;
sc_signal< bool > ap_block_pp0_stage2_flag00011001;
sc_signal< sc_lv<32> > bufi_3_load_reg_967;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage4;
sc_signal< bool > ap_block_state14_pp0_stage4_iter0;
sc_signal< bool > ap_block_state54_pp0_stage4_iter1;
sc_signal< bool > ap_block_pp0_stage4_flag00011001;
sc_signal< sc_lv<32> > bufi_0_load_reg_975;
sc_signal< sc_lv<32> > bufi_1_load_reg_980;
sc_signal< sc_lv<32> > bufi_2_load_reg_986;
sc_signal< sc_lv<32> > bufi_4_load_reg_993;
sc_signal< sc_lv<32> > bufi_5_load_reg_1000;
sc_signal< sc_lv<32> > bufi_6_load_reg_1006;
sc_signal< sc_lv<32> > bufi_load_0_phi_fu_678_p3;
sc_signal< sc_lv<32> > bufi_load_0_phi_reg_1011;
sc_signal< sc_lv<32> > bufi_load_1_phi_fu_695_p3;
sc_signal< sc_lv<32> > bufi_load_1_phi_reg_1016;
sc_signal< sc_lv<32> > bufi_load_2_phi_fu_712_p3;
sc_signal< sc_lv<32> > bufi_load_2_phi_reg_1021;
sc_signal< sc_lv<32> > bufi_load_3_phi_fu_729_p3;
sc_signal< sc_lv<32> > bufi_load_3_phi_reg_1026;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_ap_return;
sc_signal< sc_lv<32> > tmp_22_reg_1031;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage9;
sc_signal< bool > ap_block_state19_pp0_stage9_iter0;
sc_signal< bool > ap_block_state59_pp0_stage9_iter1;
sc_signal< bool > ap_block_pp0_stage9_flag00011001;
sc_signal< sc_lv<32> > tmp_13_3_reg_1036;
sc_signal< sc_lv<32> > temp_2_4_reg_1041;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage11;
sc_signal< bool > ap_block_state21_pp0_stage11_iter0;
sc_signal< bool > ap_block_state61_pp0_stage11_iter1;
sc_signal< bool > ap_block_pp0_stage11_flag00011001;
sc_signal< sc_lv<2> > col_b_V_fu_735_p2;
sc_signal< sc_lv<2> > col_b_V_reg_1047;
sc_signal< sc_logic > ap_CS_fsm_state63;
sc_signal< sc_lv<4> > indvar_flatten_op_fu_740_p2;
sc_signal< sc_lv<4> > indvar_flatten_op_reg_1052;
sc_signal< sc_lv<6> > indvar_flatten15_op_fu_746_p2;
sc_signal< sc_lv<6> > indvar_flatten15_op_reg_1057;
sc_signal< sc_lv<4> > indvar_flatten_next_fu_752_p3;
sc_signal< sc_logic > ap_CS_fsm_state64;
sc_signal< sc_lv<6> > indvar_flatten_next1_fu_758_p3;
sc_signal< bool > ap_block_pp0_stage0_flag00011011;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state10;
sc_signal< bool > ap_block_state49_pp0_stage39_iter0;
sc_signal< bool > ap_block_pp0_stage39_flag00011011;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage39;
sc_signal< bool > ap_block_state22_pp0_stage12_iter0;
sc_signal< bool > ap_block_state62_pp0_stage12_iter1;
sc_signal< bool > ap_block_pp0_stage12_flag00011011;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage12;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_ap_start;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_ap_done;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_ap_idle;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_ap_ready;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_2_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_3_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_4_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_5_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_6_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_7_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_7_3_x_s_fu_316_empty_8_Din_A;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_ap_start;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_ap_done;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_ap_idle;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_ap_ready;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_11_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_12_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_13_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_14_Din_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Addr_A;
sc_signal< sc_logic > grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_EN_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_WEN_A;
sc_signal< sc_lv<32> > grp_aesl_mux_load_5_3_x_s_fu_337_empty_15_Din_A;
sc_signal< sc_lv<4> > grp_aesl_mux_load_5_3_x_s_fu_337_empty;
sc_signal< sc_lv<7> > indvar_flatten1_reg_211;
sc_signal< sc_lv<2> > p_s_reg_222;
sc_signal< sc_lv<6> > indvar_flatten2_reg_234;
sc_signal< sc_lv<2> > p_1_reg_246;
sc_signal< sc_lv<4> > indvar_flatten_reg_258;
sc_signal< sc_lv<2> > p_2_reg_270;
sc_signal< sc_lv<2> > p_3_reg_282;
sc_signal< sc_lv<3> > p_4_phi_fu_298_p4;
sc_signal< bool > ap_block_pp0_stage0_flag00000000;
sc_signal< sc_lv<32> > temp1_phi_fu_309_p4;
sc_signal< bool > ap_block_pp0_stage11_flag00000000;
sc_signal< sc_logic > ap_reg_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage6;
sc_signal< bool > ap_block_state16_pp0_stage6_iter0;
sc_signal< bool > ap_block_state56_pp0_stage6_iter1;
sc_signal< bool > ap_block_pp0_stage6_flag00011001;
sc_signal< bool > ap_block_pp0_stage6_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage7;
sc_signal< bool > ap_block_state17_pp0_stage7_iter0;
sc_signal< bool > ap_block_state57_pp0_stage7_iter1;
sc_signal< bool > ap_block_pp0_stage7_flag00011001;
sc_signal< bool > ap_block_pp0_stage7_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage8;
sc_signal< bool > ap_block_state18_pp0_stage8_iter0;
sc_signal< bool > ap_block_state58_pp0_stage8_iter1;
sc_signal< bool > ap_block_pp0_stage8_flag00011001;
sc_signal< bool > ap_block_pp0_stage8_flag00000000;
sc_signal< bool > ap_block_pp0_stage5_flag00000000;
sc_signal< sc_logic > ap_reg_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start;
sc_signal< bool > ap_block_pp0_stage3_flag00000000;
sc_signal< bool > ap_block_pp0_stage4_flag00000000;
sc_signal< bool > ap_block_pp0_stage9_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage13;
sc_signal< bool > ap_block_state23_pp0_stage13_iter0;
sc_signal< bool > ap_block_pp0_stage13_flag00011001;
sc_signal< bool > ap_block_pp0_stage13_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage14;
sc_signal< bool > ap_block_state24_pp0_stage14_iter0;
sc_signal< bool > ap_block_pp0_stage14_flag00011001;
sc_signal< bool > ap_block_pp0_stage14_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage18;
sc_signal< bool > ap_block_state28_pp0_stage18_iter0;
sc_signal< bool > ap_block_pp0_stage18_flag00011001;
sc_signal< bool > ap_block_pp0_stage18_flag00000000;
sc_signal< bool > ap_block_pp0_stage19_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage23;
sc_signal< bool > ap_block_state33_pp0_stage23_iter0;
sc_signal< bool > ap_block_pp0_stage23_flag00011001;
sc_signal< bool > ap_block_pp0_stage23_flag00000000;
sc_signal< sc_logic
|
> ap_CS_fsm_pp0_stage24;
sc_signal< bool > ap_block_state34_pp0_stage24_iter0;
sc_signal< bool > ap_block_pp0_stage24_flag00011001;
sc_signal< bool > ap_block_pp0_stage24_flag00000000;
sc_signal< bool > ap_block_pp0_stage1_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage16;
sc_signal< bool > ap_block_pp0_stage16_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage21;
sc_signal< bool > ap_block_pp0_stage21_flag00000000;
sc_signal< sc_lv<32> > tmp_18_cast_fu_569_p1;
sc_signal< sc_lv<32> > tmp_20_cast_fu_657_p1;
sc_signal< sc_lv<32> > bufo_Addr_A_orig;
sc_signal< bool > ap_block_pp0_stage12_flag00011001;
sc_signal< bool > ap_block_pp0_stage12_flag00000000;
sc_signal< sc_lv<32> > bufi_3_Addr_A_orig;
sc_signal< sc_lv<32> > bufi_0_Addr_A_orig;
sc_signal< sc_lv<32> > bufi_1_Addr_A_orig;
sc_signal< sc_lv<32> > bufi_2_Addr_A_orig;
sc_signal< sc_lv<32> > bufi_4_Addr_A_orig;
sc_signal< sc_lv<32> > bufi_5_Addr_A_orig;
sc_signal< sc_lv<32> > bufi_6_Addr_A_orig;
sc_signal< sc_lv<32> > grp_fu_361_p0;
sc_signal< sc_lv<32> > grp_fu_361_p1;
sc_signal< bool > ap_block_pp0_stage27_flag00000000;
sc_signal< bool > ap_block_pp0_stage35_flag00000000;
sc_signal< sc_lv<32> > grp_fu_367_p1;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage26;
sc_signal< bool > ap_block_pp0_stage26_flag00000000;
sc_signal< sc_lv<1> > tmp_s_fu_420_p2;
sc_signal< sc_lv<1> > not_exitcond_flatten_fu_415_p2;
sc_signal< sc_lv<1> > exitcond_flatten_not_fu_437_p2;
sc_signal< sc_lv<1> > tmp_8_mid_fu_426_p2;
sc_signal< sc_lv<1> > not_exitcond_flatten_1_fu_442_p2;
sc_signal< sc_lv<2> > to_b_V_fu_472_p2;
sc_signal< sc_lv<1> > tmp_5_fu_488_p2;
sc_signal< sc_lv<1> > tmp_7_fu_492_p2;
sc_signal< sc_lv<2> > row_b_V_fu_483_p2;
sc_signal< sc_lv<4> > tmp_4_fu_514_p3;
sc_signal< sc_lv<32> > p_shl8_fu_521_p1;
sc_signal< sc_lv<32> > tmp_4_mid2_cast_fu_511_p1;
sc_signal< sc_lv<32> > tmp_7_mid2_cast_fu_531_p1;
sc_signal< sc_lv<32> > tmp_6_fu_525_p2;
sc_signal< sc_lv<32> > tmp_8_fu_534_p2;
sc_signal< sc_lv<6> > p_shl_cast_fu_548_p3;
sc_signal< sc_lv<6> > tmp_cast_fu_560_p1;
sc_signal< sc_lv<6> > tmp_14_fu_555_p2;
sc_signal< sc_lv<6> > tmp_15_fu_563_p2;
sc_signal< sc_lv<2> > ti_b_V_fu_574_p2;
sc_signal< sc_lv<5> > tmp_fu_590_p3;
sc_signal< sc_lv<6> > p_shl9_cast_fu_597_p1;
sc_signal< sc_lv<6> > tmp_1_mid2_cast_fu_587_p1;
sc_signal< bool > ap_block_pp0_stage2_flag00000000;
sc_signal< sc_lv<6> > tmp_9_cast_cast_fu_649_p1;
sc_signal< sc_lv<32> > sel_tmp1_fu_667_p3;
sc_signal< sc_lv<32> > sel_tmp3_fu_672_p3;
sc_signal< sc_lv<32> > sel_tmp7_fu_684_p3;
sc_signal< sc_lv<32> > sel_tmp9_fu_689_p3;
sc_signal< sc_lv<32> > sel_tmp5_fu_701_p3;
sc_signal< sc_lv<32> > sel_tmp6_fu_706_p3;
sc_signal< sc_lv<32> > sel_tmp8_fu_718_p3;
sc_signal< sc_lv<32> > sel_tmp10_fu_723_p3;
sc_signal< sc_lv<51> > ap_NS_fsm;
sc_signal< bool > ap_block_pp0_stage1_flag00011011;
sc_signal< bool > ap_block_pp0_stage2_flag00011011;
sc_signal< bool > ap_block_pp0_stage3_flag00011011;
sc_signal< bool > ap_block_pp0_stage4_flag00011011;
sc_signal< bool > ap_block_pp0_stage5_flag00011011;
sc_signal< bool > ap_block_pp0_stage6_flag00011011;
sc_signal< bool > ap_block_pp0_stage7_flag00011011;
sc_signal< bool > ap_block_pp0_stage8_flag00011011;
sc_signal< bool > ap_block_pp0_stage9_flag00011011;
sc_signal< bool > ap_block_pp0_stage10_flag00011011;
sc_signal< bool > ap_block_pp0_stage11_flag00011011;
sc_signal< bool > ap_block_pp0_stage13_flag00011011;
sc_signal< bool > ap_block_pp0_stage14_flag00011011;
sc_signal< bool > ap_block_pp0_stage15_flag00011011;
sc_signal< bool > ap_block_state26_pp0_stage16_iter0;
sc_signal< bool > ap_block_pp0_stage16_flag00011011;
sc_signal< bool > ap_block_pp0_stage16_flag00011001;
sc_signal< bool > ap_block_state27_pp0_stage17_iter0;
sc_signal< bool > ap_block_pp0_stage17_flag00011011;
sc_signal< bool > ap_block_pp0_stage17_flag00011001;
sc_signal< bool > ap_block_pp0_stage18_flag00011011;
sc_signal< bool > ap_block_pp0_stage19_flag00011011;
sc_signal< bool > ap_block_pp0_stage20_flag00011011;
sc_signal< bool > ap_block_state31_pp0_stage21_iter0;
sc_signal< bool > ap_block_pp0_stage21_flag00011011;
sc_signal< bool > ap_block_pp0_stage21_flag00011001;
sc_signal< bool > ap_block_state32_pp0_stage22_iter0;
sc_signal< bool > ap_block_pp0_stage22_flag00011011;
sc_signal< bool > ap_block_pp0_stage22_flag00011001;
sc_signal< bool > ap_block_pp0_stage23_flag00011011;
sc_signal< bool > ap_block_pp0_stage24_flag00011011;
sc_signal< bool > ap_block_pp0_stage25_flag00011011;
sc_signal< bool > ap_block_state36_pp0_stage26_iter0;
sc_signal< bool > ap_block_pp0_stage26_flag00011011;
sc_signal< bool > ap_block_pp0_stage26_flag00011001;
sc_signal< bool > ap_block_pp0_stage27_flag00011011;
sc_signal< bool > ap_block_state38_pp0_stage28_iter0;
sc_signal< bool > ap_block_pp0_stage28_flag00011011;
sc_signal< bool > ap_block_pp0_stage28_flag00011001;
sc_signal< bool > ap_block_state39_pp0_stage29_iter0;
sc_signal< bool > ap_block_pp0_stage29_flag00011011;
sc_signal< bool > ap_block_pp0_stage29_flag00011001;
sc_signal< bool > ap_block_pp0_stage30_flag00011011;
sc_signal< bool > ap_block_state41_pp0_stage31_iter0;
sc_signal< bool > ap_block_pp0_stage31_flag00011011;
sc_signal< bool > ap_block_pp0_stage31_flag00011001;
sc_signal< bool > ap_block_state42_pp0_stage32_iter0;
sc_signal< bool > ap_block_pp0_stage32_flag00011011;
sc_signal< bool > ap_block_pp0_stage32_flag00011001;
sc_signal< bool > ap_block_state43_pp0_stage33_iter0;
sc_signal< bool > ap_block_pp0_stage33_flag00011011;
sc_signal< bool > ap_block_pp0_stage33_flag00011001;
sc_signal< bool > ap_block_state44_pp0_stage34_iter0;
sc_signal< bool > ap_block_pp0_stage34_flag00011011;
sc_signal< bool > ap_block_pp0_stage34_flag00011001;
sc_signal< bool > ap_block_pp0_stage35_flag00011011;
sc_signal< bool > ap_block_state46_pp0_stage36_iter0;
sc_signal< bool > ap_block_pp0_stage36_flag00011011;
sc_signal< bool > ap_block_pp0_stage36_flag00011001;
sc_signal< bool > ap_block_state47_pp0_stage37_iter0;
sc_signal< bool > ap_block_pp0_stage37_flag00011011;
sc_signal< bool > ap_block_pp0_stage37_flag00011001;
sc_signal< bool > ap_block_state48_pp0_stage38_iter0;
sc_signal< bool > ap_block_pp0_stage38_flag00011011;
sc_signal< bool > ap_block_pp0_stage38_flag00011001;
sc_signal< bool > ap_block_pp0_stage39_flag00011001;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<51> ap_ST_fsm_state1;
static const sc_lv<51> ap_ST_fsm_state2;
static const sc_lv<51> ap_ST_fsm_state3;
static const sc_lv<51> ap_ST_fsm_state4;
static const sc_lv<51> ap_ST_fsm_state5;
static const sc_lv<51> ap_ST_fsm_state6;
static const sc_lv<51> ap_ST_fsm_state7;
static const sc_lv<51> ap_ST_fsm_state8;
static const sc_lv<51> ap_ST_fsm_state9;
static const sc_lv<51> ap_ST_fsm_pp0_stage0;
static const sc_lv<51> ap_ST_fsm_pp0_stage1;
static const sc_lv<51> ap_ST_fsm_pp0_stage2;
static const sc_lv<51> ap_ST_fsm_pp0_stage3;
static const sc_lv<51> ap_ST_fsm_pp0_stage4;
static const sc_lv<51> ap_ST_fsm_pp0_stage5;
static const sc_lv<51> ap_ST_fsm_pp0_stage6;
static const sc_lv<51> ap_ST_fsm_pp0_stage7;
static const sc_lv<51> ap_ST_fsm_pp0_stage8;
static const sc_lv<51> ap_ST_fsm_pp0_stage9;
static const sc_lv<51> ap_ST_fsm_pp0_stage10;
static const sc_lv<51> ap_ST_fsm_pp0_stage11;
static const sc_lv<51> ap_ST_fsm_pp0_stage12;
static const sc_lv<51> ap_ST_fsm_pp0_stage13;
static const sc_lv<51> ap_ST_fsm_pp0_stage14;
static const sc_lv<51> ap_ST_fsm_pp0_stage15;
static const sc_lv<51> ap_ST_fsm_pp0_stage16;
static const sc_lv<51> ap_ST_fsm_pp0_stage17;
static const sc_lv<51> ap_ST_fsm_pp0_stage18;
static const sc_lv<51> ap_ST_fsm_pp0_stage19;
static const sc_lv<51> ap_ST_fsm_pp0_stage20;
static const sc_lv<51> ap_ST_fsm_pp0_stage21;
static const sc_lv<51> ap_ST_fsm_pp0_stage22;
static const sc_lv<51> ap_ST_fsm_pp0_stage23;
static const sc_lv<51> ap_ST_fsm_pp0_stage24;
static const sc_lv<51> ap_ST_fsm_pp0_stage25;
static const sc_lv<51> ap_ST_fsm_pp0_stage26;
static const sc_lv<51> ap_ST_fsm_pp0_stage27;
static const sc_lv<51> ap_ST_fsm_pp0_stage28;
static const sc_lv<51> ap_ST_fsm_pp0_stage29;
static const sc_lv<51> ap_ST_fsm_pp0_stage30;
static const sc_lv<51> ap_ST_fsm_pp0_stage31;
static const sc_lv<51> ap_ST_fsm_pp0_stage32;
static const sc_lv<51> ap_ST_fsm_pp0_stage33;
static const sc_lv<51> ap_ST_fsm_pp0_stage34;
static const sc_lv<51> ap_ST_fsm_pp0_stage35;
static const sc_lv<51> ap_ST_fsm_pp0_stage36;
static const sc_lv<51> ap_ST_fsm_pp0_stage37;
static const sc_lv<51> ap_ST_fsm_pp0_stage38;
static const sc_lv<51> ap_ST_fsm_pp0_stage39;
static const sc_lv<51> ap_ST_fsm_state63;
static const sc_lv<51> ap_ST_fsm_state64;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_E;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_13;
static const sc_lv<32> ap_const_lv32_18;
static const sc_lv<32> ap_const_lv32_1D;
static const sc_lv<32> ap_const_lv32_22;
static const sc_lv<32> ap_const_lv32_27;
static const sc_lv<32> ap_const_lv32_1C;
static const sc_lv<32> ap_const_lv32_24;
static const sc_lv<32> ap_const_lv32_2C;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_12;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<32> ap_const_lv32_31;
static const sc_lv<32> ap_const_lv32_32;
static const sc_lv<32> ap_const_lv32_30;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<7> ap_const_lv7_0;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<32> ap_const_lv32_17;
static const sc_lv<32> ap_const_lv32_1B;
static const sc_lv<32> ap_const_lv32_20;
static const sc_lv<32> ap_const_lv32_21;
static const sc_lv<32> ap_const_lv32_19;
static const sc_lv<32> ap_const_lv32_1E;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<4> ap_const_lv4_3;
static const sc_lv<4> ap_const_lv4_4;
static const sc_lv<4> ap_const_lv4_F;
static const sc_lv<32> ap_const_lv32_23;
static const sc_lv<7> ap_const_lv7_51;
static const sc_lv<7> ap_const_lv7_1;
static const sc_lv<6> ap_const_lv6_1B;
static const sc_lv<4> ap_const_lv4_9;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<3> ap_const_lv3_5;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<6> ap_const_lv6_1;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_pp0_stage1();
void thread_ap_CS_fsm_pp0_stage10();
void thread_ap_CS_fsm_pp0_stage11();
void thread_ap_CS_fsm_pp0_stage12();
void thread_ap_CS_fsm_pp0_stage13();
void thread_ap_CS_fsm_pp0_stage14();
void thread_ap_CS_fsm_pp0_stage15();
void thread_ap_CS_fsm_pp0_stage16();
void thread_ap_CS_fsm_pp0_stage18();
void thread_ap_CS_fsm_pp0_stage19();
void thread_ap_CS_fsm_pp0_stage2();
void thread_ap_CS_fsm_pp0_stage20();
void thread_ap_CS_fsm_pp0_stage21();
void thread_ap_CS_fsm_pp0_stage23();
void thread_ap_CS_fsm_pp0_stage24();
void thread_ap_CS_fsm_pp0_stage25();
void thread_ap_CS_fsm_pp0_stage26();
void thread_ap_CS_fsm_pp0_stage27();
void thread_ap_CS_fsm_pp0_stage3();
void thread_ap_CS_fsm_pp0_stage30();
void thread_ap_CS_fsm_pp0_stage35();
void thread_ap_CS_fsm_pp0_stage39();
void thread_ap_CS_fsm_pp0_stage4();
void thread_ap_CS_fsm_pp0_stage5();
void thread_ap_CS_fsm_pp0_stage6();
void thread_ap_CS_fsm_pp0_stage7();
void thread_ap_CS_fsm_pp0_stage8();
void thread_ap_CS_fsm_pp0_stage9();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state63();
void thread_ap_CS_fsm_state64();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state9();
void thread_ap_block_pp0_stage0_flag00000000();
void thread_ap_block_pp0_stage0_flag00011001();
void thread_ap_block_pp0_stage0_flag00011011();
void thread_ap_block_pp0_stage10_flag00011001();
void thread_ap_block_pp0_stage10_flag00011011();
void thread_ap_block_pp0_stage11_flag00000000();
void thread_ap_block_pp0_stage11_flag00011001();
void thread_ap_block_pp0_stage11_flag00011011();
void thread_ap_block_pp0_stage12_flag00000000();
void thread_ap_block_pp0_stage12_flag00011001();
void thread_ap_block_pp0_stage12_flag00011011();
void thread_ap_block_pp0_stage13_flag00000000();
void thread_ap_block_pp0_stage13_flag00011001();
void thread_ap_block_pp0_stage13_flag00011011();
void thread_ap_block_pp0_stage14_flag00000000();
void thread_ap_block_pp0_stage14_flag00011001();
void thread_ap_block_pp0_stage14_flag00011011();
void thread_ap_block_pp0_stage15_flag00011001();
void thread_ap_block_pp0_stage15_flag00011011();
void thread_ap_block_pp0_stage16_flag00000000();
void thread_ap_block_pp0_stage16_flag00011001();
void thread_ap_block_pp0_stage16_flag00011011();
void thread_ap_block_pp0_stage17_flag00011001();
void thread_ap_block_pp0_stage17_flag00011011();
void thread_ap_block_pp0_stage18_flag00000000();
void thread_ap_block_pp0_stage18_flag00011001();
void thread_ap_block_pp0_stage18_flag00011011();
void thread_ap_block_pp0_stage19_flag00000000();
void thread_ap_block_pp0_stage19_flag00011001();
void thread_ap_block_pp0_stage19_flag00011011();
void thread_ap_block_pp0_stage1_flag00000000();
void thread_ap_block_pp0_stage1_flag00011001();
void thread_ap_block_pp0_stage1_flag00011011();
void thread_ap_block_pp0_stage20_flag00011001();
void thread_ap_block_pp0_stage20_flag00011011();
void thread_ap_block_pp0_stage21_flag00000000();
void thread_ap_block_pp0_stage21_flag00011001();
void thread_ap_block_pp0_stage21_flag00011011();
void thread_ap_block_pp0_stage22_flag00011001();
void thread_ap_block_pp0_stage22_flag00011011();
void thread_ap_block_pp0_stage23_flag00000000();
void thread_ap_block_pp0_stage23_flag00011001();
void thread_ap_block_pp0_stage23_flag00011011();
void thread_ap_block_pp0_stage24_flag00000000();
void thread_ap_block_pp0_stage24_flag00011001();
void thread_ap_block_pp0_stage24_flag00011011();
void thread_ap_block_pp0_stage25_flag00011001();
void thread_ap_block_pp0_stage25_flag00011011();
void thread_ap_block_pp0_stage26_flag00000000();
void thread_ap_block_pp0_stage26_flag00011001();
void thread_ap_block_pp0_stage26_flag00011011();
void thread_ap_block_pp0_stage27_flag00000000();
void thread_ap_block_pp0_stage27_flag00011001();
void thread_ap_block_pp0_stage27_flag00011011();
void thread_ap_block_pp0_stage28_flag00011001();
void thread_ap_block_pp0_stage28_flag00011011();
void thread_ap_block_pp0_stage29_flag00011001();
void thread_ap_block_pp0_stage29_flag00011011();
void thread_ap_block_pp0_stage2_flag00000000();
void thread_ap_block_pp0_stage2_flag00011001();
void thread_ap_block_pp0_stage2_flag00011011();
void thread_ap_block_pp0_stage30_flag00011001();
void thread_ap_block_pp0_stage30_flag00011011();
void thread_ap_block_pp0_stage31_flag00011001();
void thread_ap_block_pp0_stage31_flag00011011();
void thread_ap_block_pp0_stage32_flag00011001();
void thread_ap_block_pp0_stage32_flag00011011();
void thread_ap_block_pp0_stage33_flag00011001();
void thread_ap_block_pp0_stage33_flag00011011();
void thread_ap_block_pp0_stage34_flag00011001();
void thread_ap_block_pp0_stage34_flag00011011();
void thread_ap_block_pp0_stage35_flag00000000();
void thread_ap_block_pp0_stage35_flag00011001();
void thread_ap_block_pp0_stage35_flag00011011();
void thread_ap_block_pp0_stage36_flag00011001();
void thread_ap_block_pp0_stage36_flag00011011();
void thread_ap_block_pp0_stage37_flag00011001();
void thread_ap_block_pp0_stage37_flag00011011();
void thread_ap_block_pp0_stage38_flag00011001();
void thread_ap_block_pp0_stage38_flag00011011();
void thread_ap_block_pp0_stage39_flag00011001();
void thread_ap_block_pp0_stage39_flag00011011();
void thread_ap_block_pp0_stage3_flag00000000();
void thread_ap_block_pp0_stage3_flag00011001();
void thread_ap_block_pp0_stage3_flag00011011();
void thread_ap_block_pp0_stage4_flag00000000();
void thread_ap_block_pp0_stage4_flag00011001();
void thread_ap_block_pp0_stage4_flag00011011();
void thread_ap_block_pp0_stage5_flag00000000();
void thread_ap_block_pp0_stage5_flag00011001();
void thread_ap_block_pp0_stage5_flag00011011();
void thread_ap_block_pp0_stage6_flag00000000();
void thread_ap_block_pp0_stage6_flag00011001();
void thread_ap_block_pp0_stage6_flag00011011();
void thread_ap_block_pp0_stage7_flag00000000();
void thread_ap_block_pp0_stage7_flag00011001();
void thread_ap_block_pp0_stage7_flag00011011();
void thread_ap_block_pp0_stage8_flag00000000();
void thread_ap_block_pp0_stage8_flag00011001();
void thread_ap_block_pp0_stage8_flag00011011();
void thread_ap_block_pp0_stage9_flag00000000();
void thread_ap_block_pp0_stage9_flag00011001();
void thread_ap_block_pp0_stage9_flag00011011();
void thread_ap_block_state10_pp0_stage0_iter0();
void thread_ap_block_state11_pp0_stage1_iter0();
void thread_ap_block_state12_pp0_stage2_iter0();
void thread_ap_block_state13_pp0_stage3_iter0();
void thread_ap_block_state14_pp0_stage4_iter0();
void thread_ap_block_state15_pp0_stage5_iter0();
void thread_ap_block_state16_pp0_stage6_iter0();
void thread_ap_block_state17_pp0_stage7_iter0();
void thread_ap_block_state18_pp0_stage8_iter0();
void thread_ap_block_state19_pp0_stage9_iter0();
void thread_ap_block_state20_pp0_stage10_iter0();
void thread_ap_block_state21_pp0_stage11_iter0();
void thread_ap_bloc
|
k_state22_pp0_stage12_iter0();
void thread_ap_block_state23_pp0_stage13_iter0();
void thread_ap_block_state24_pp0_stage14_iter0();
void thread_ap_block_state25_pp0_stage15_iter0();
void thread_ap_block_state26_pp0_stage16_iter0();
void thread_ap_block_state27_pp0_stage17_iter0();
void thread_ap_block_state28_pp0_stage18_iter0();
void thread_ap_block_state29_pp0_stage19_iter0();
void thread_ap_block_state30_pp0_stage20_iter0();
void thread_ap_block_state31_pp0_stage21_iter0();
void thread_ap_block_state32_pp0_stage22_iter0();
void thread_ap_block_state33_pp0_stage23_iter0();
void thread_ap_block_state34_pp0_stage24_iter0();
void thread_ap_block_state35_pp0_stage25_iter0();
void thread_ap_block_state36_pp0_stage26_iter0();
void thread_ap_block_state37_pp0_stage27_iter0();
void thread_ap_block_state38_pp0_stage28_iter0();
void thread_ap_block_state39_pp0_stage29_iter0();
void thread_ap_block_state40_pp0_stage30_iter0();
void thread_ap_block_state41_pp0_stage31_iter0();
void thread_ap_block_state42_pp0_stage32_iter0();
void thread_ap_block_state43_pp0_stage33_iter0();
void thread_ap_block_state44_pp0_stage34_iter0();
void thread_ap_block_state45_pp0_stage35_iter0();
void thread_ap_block_state46_pp0_stage36_iter0();
void thread_ap_block_state47_pp0_stage37_iter0();
void thread_ap_block_state48_pp0_stage38_iter0();
void thread_ap_block_state49_pp0_stage39_iter0();
void thread_ap_block_state50_pp0_stage0_iter1();
void thread_ap_block_state51_pp0_stage1_iter1();
void thread_ap_block_state52_pp0_stage2_iter1();
void thread_ap_block_state53_pp0_stage3_iter1();
void thread_ap_block_state54_pp0_stage4_iter1();
void thread_ap_block_state55_pp0_stage5_iter1();
void thread_ap_block_state56_pp0_stage6_iter1();
void thread_ap_block_state57_pp0_stage7_iter1();
void thread_ap_block_state58_pp0_stage8_iter1();
void thread_ap_block_state59_pp0_stage9_iter1();
void thread_ap_block_state60_pp0_stage10_iter1();
void thread_ap_block_state61_pp0_stage11_iter1();
void thread_ap_block_state62_pp0_stage12_iter1();
void thread_ap_condition_pp0_exit_iter0_state10();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_ready();
void thread_bufi_0_Addr_A();
void thread_bufi_0_Addr_A_orig();
void thread_bufi_0_Clk_A();
void thread_bufi_0_Din_A();
void thread_bufi_0_EN_A();
void thread_bufi_0_Rst_A();
void thread_bufi_0_WEN_A();
void thread_bufi_1_Addr_A();
void thread_bufi_1_Addr_A_orig();
void thread_bufi_1_Clk_A();
void thread_bufi_1_Din_A();
void thread_bufi_1_EN_A();
void thread_bufi_1_Rst_A();
void thread_bufi_1_WEN_A();
void thread_bufi_2_Addr_A();
void thread_bufi_2_Addr_A_orig();
void thread_bufi_2_Clk_A();
void thread_bufi_2_Din_A();
void thread_bufi_2_EN_A();
void thread_bufi_2_Rst_A();
void thread_bufi_2_WEN_A();
void thread_bufi_3_Addr_A();
void thread_bufi_3_Addr_A_orig();
void thread_bufi_3_Clk_A();
void thread_bufi_3_Din_A();
void thread_bufi_3_EN_A();
void thread_bufi_3_Rst_A();
void thread_bufi_3_WEN_A();
void thread_bufi_4_Addr_A();
void thread_bufi_4_Addr_A_orig();
void thread_bufi_4_Clk_A();
void thread_bufi_4_Din_A();
void thread_bufi_4_EN_A();
void thread_bufi_4_Rst_A();
void thread_bufi_4_WEN_A();
void thread_bufi_5_Addr_A();
void thread_bufi_5_Addr_A_orig();
void thread_bufi_5_Clk_A();
void thread_bufi_5_Din_A();
void thread_bufi_5_EN_A();
void thread_bufi_5_Rst_A();
void thread_bufi_5_WEN_A();
void thread_bufi_6_Addr_A();
void thread_bufi_6_Addr_A_orig();
void thread_bufi_6_Clk_A();
void thread_bufi_6_Din_A();
void thread_bufi_6_EN_A();
void thread_bufi_6_Rst_A();
void thread_bufi_6_WEN_A();
void thread_bufi_load_0_phi_fu_678_p3();
void thread_bufi_load_1_phi_fu_695_p3();
void thread_bufi_load_2_phi_fu_712_p3();
void thread_bufi_load_3_phi_fu_729_p3();
void thread_bufo_Addr_A();
void thread_bufo_Addr_A_orig();
void thread_bufo_Clk_A();
void thread_bufo_Din_A();
void thread_bufo_EN_A();
void thread_bufo_Rst_A();
void thread_bufo_WEN_A();
void thread_bufw_0_Addr_A();
void thread_bufw_0_Clk_A();
void thread_bufw_0_Din_A();
void thread_bufw_0_EN_A();
void thread_bufw_0_Rst_A();
void thread_bufw_0_WEN_A();
void thread_bufw_1_Addr_A();
void thread_bufw_1_Clk_A();
void thread_bufw_1_Din_A();
void thread_bufw_1_EN_A();
void thread_bufw_1_Rst_A();
void thread_bufw_1_WEN_A();
void thread_bufw_2_Addr_A();
void thread_bufw_2_Clk_A();
void thread_bufw_2_Din_A();
void thread_bufw_2_EN_A();
void thread_bufw_2_Rst_A();
void thread_bufw_2_WEN_A();
void thread_bufw_3_Addr_A();
void thread_bufw_3_Clk_A();
void thread_bufw_3_Din_A();
void thread_bufw_3_EN_A();
void thread_bufw_3_Rst_A();
void thread_bufw_3_WEN_A();
void thread_bufw_4_Addr_A();
void thread_bufw_4_Clk_A();
void thread_bufw_4_Din_A();
void thread_bufw_4_EN_A();
void thread_bufw_4_Rst_A();
void thread_bufw_4_WEN_A();
void thread_col_b_V_fu_735_p2();
void thread_exitcond_flatten1_fu_409_p2();
void thread_exitcond_flatten2_fu_391_p2();
void thread_exitcond_flatten_fu_403_p2();
void thread_exitcond_flatten_mid_fu_432_p2();
void thread_exitcond_flatten_not_fu_437_p2();
void thread_grp_aesl_mux_load_5_3_x_s_fu_337_ap_start();
void thread_grp_aesl_mux_load_5_3_x_s_fu_337_empty();
void thread_grp_aesl_mux_load_7_3_x_s_fu_316_ap_start();
void thread_grp_fu_361_p0();
void thread_grp_fu_361_p1();
void thread_grp_fu_367_p1();
void thread_i_V_fu_638_p2();
void thread_indvar_flatten15_op_fu_746_p2();
void thread_indvar_flatten_next1_fu_758_p3();
void thread_indvar_flatten_next2_fu_397_p2();
void thread_indvar_flatten_next_fu_752_p3();
void thread_indvar_flatten_op_fu_740_p2();
void thread_not_exitcond_flatten_1_fu_442_p2();
void thread_not_exitcond_flatten_fu_415_p2();
void thread_p_1_mid_fu_453_p3();
void thread_p_2_mid_fu_464_p3();
void thread_p_3_mid2_fu_497_p3();
void thread_p_4_phi_fu_298_p4();
void thread_p_shl8_fu_521_p1();
void thread_p_shl9_cast_fu_597_p1();
void thread_p_shl_cast_fu_548_p3();
void thread_row_b_V_fu_483_p2();
void thread_sel_tmp10_fu_723_p3();
void thread_sel_tmp1_fu_667_p3();
void thread_sel_tmp2_fu_622_p2();
void thread_sel_tmp3_fu_672_p3();
void thread_sel_tmp4_fu_627_p2();
void thread_sel_tmp5_fu_701_p3();
void thread_sel_tmp6_fu_706_p3();
void thread_sel_tmp7_fu_684_p3();
void thread_sel_tmp8_fu_718_p3();
void thread_sel_tmp9_fu_689_p3();
void thread_sel_tmp_fu_617_p2();
void thread_temp1_phi_fu_309_p4();
void thread_ti_b_V_fu_574_p2();
void thread_tmp_11_fu_540_p1();
void thread_tmp_12_48_t_fu_610_p3();
void thread_tmp_12_fu_544_p1();
void thread_tmp_14_fu_555_p2();
void thread_tmp_15_fu_563_p2();
void thread_tmp_16_fu_652_p2();
void thread_tmp_18_cast_fu_569_p1();
void thread_tmp_1_fu_601_p2();
void thread_tmp_1_mid2_cast_fu_587_p1();
void thread_tmp_1_mid2_v_fu_580_p3();
void thread_tmp_20_cast_fu_657_p1();
void thread_tmp_2_fu_460_p2();
void thread_tmp_3_fu_632_p2();
void thread_tmp_4_fu_514_p3();
void thread_tmp_4_mid2_cast_fu_511_p1();
void thread_tmp_4_mid2_fu_477_p3();
void thread_tmp_5_fu_488_p2();
void thread_tmp_6_fu_525_p2();
void thread_tmp_7_cast_mid2_cast_fu_607_p1();
void thread_tmp_7_fu_492_p2();
void thread_tmp_7_mid2_cast_fu_531_p1();
void thread_tmp_7_mid2_fu_505_p3();
void thread_tmp_8_fu_534_p2();
void thread_tmp_8_mid1_fu_447_p2();
void thread_tmp_8_mid_fu_426_p2();
void thread_tmp_9_cast_cast_fu_649_p1();
void thread_tmp_9_fu_644_p2();
void thread_tmp_cast_fu_560_p1();
void thread_tmp_fu_590_p3();
void thread_tmp_s_fu_420_p2();
void thread_to_b_V_fu_472_p2();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _doCorner_HH_
#define _doCorner_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "AXIvideo2Mat.h"
#include "rgb2gray.h"
#include "FAST_t_opr.h"
#include "Dilate.h"
#include "PaintMask.h"
#include "Mat2AXIvideo.h"
#include "fifo_w8_d2_A.h"
#include "fifo_w8_d20000_A.h"
#include "start_for_rgb2grapcA.h"
#include "start_for_FAST_t_qcK.h"
#include "start_for_PaintMarcU.h"
#include "start_for_Dilate_U0.h"
#include "start_for_Mat2AXIsc4.h"
#include "doCorner_CTRL_BUS_s_axi.h"
namespace ap_rtl {
template<unsigned int C_S_AXI_CTRL_BUS_ADDR_WIDTH = 4,
unsigned int C_S_AXI_CTRL_BUS_DATA_WIDTH = 32>
struct doCorner : public sc_module {
// Port declarations 38
sc_in< sc_logic > s_axi_CTRL_BUS_AWVALID;
sc_out< sc_logic > s_axi_CTRL_BUS_AWREADY;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_ADDR_WIDTH> > s_axi_CTRL_BUS_AWADDR;
sc_in< sc_logic > s_axi_CTRL_BUS_WVALID;
sc_out< sc_logic > s_axi_CTRL_BUS_WREADY;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_DATA_WIDTH> > s_axi_CTRL_BUS_WDATA;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_DATA_WIDTH/8> > s_axi_CTRL_BUS_WSTRB;
sc_in< sc_logic > s_axi_CTRL_BUS_ARVALID;
sc_out< sc_logic > s_axi_CTRL_BUS_ARREADY;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_ADDR_WIDTH> > s_axi_CTRL_BUS_ARADDR;
sc_out< sc_logic > s_axi_CTRL_BUS_RVALID;
sc_in< sc_logic > s_axi_CTRL_BUS_RREADY;
sc_out< sc_uint<C_S_AXI_CTRL_BUS_DATA_WIDTH> > s_axi_CTRL_BUS_RDATA;
sc_out< sc_lv<2> > s_axi_CTRL_BUS_RRESP;
sc_out< sc_logic > s_axi_CTRL_BUS_BVALID;
sc_in< sc_logic > s_axi_CTRL_BUS_BREADY;
sc_out< sc_lv<2> > s_axi_CTRL_BUS_BRESP;
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_out< sc_logic > interrupt;
sc_in< sc_lv<24> > inStream_TDATA;
sc_in< sc_lv<3> > inStream_TKEEP;
sc_in< sc_lv<3> > inStream_TSTRB;
sc_in< sc_lv<1> > inStream_TUSER;
sc_in< sc_lv<1> > inStream_TLAST;
sc_in< sc_lv<1> > inStream_TID;
sc_in< sc_lv<1> > inStream_TDEST;
sc_out< sc_lv<24> > outStream_TDATA;
sc_out< sc_lv<3> > outStream_TKEEP;
sc_out< sc_lv<3> > outStream_TSTRB;
sc_out< sc_lv<1> > outStream_TUSER;
sc_out< sc_lv<1> > outStream_TLAST;
sc_out< sc_lv<1> > outStream_TID;
sc_out< sc_lv<1> > outStream_TDEST;
sc_in< sc_logic > inStream_TVALID;
sc_out< sc_logic > inStream_TREADY;
sc_out< sc_logic > outStream_TVALID;
sc_in< sc_logic > outStream_TREADY;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
doCorner(sc_module_name name);
SC_HAS_PROCESS(doCorner);
~doCorner();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
doCorner_CTRL_BUS_s_axi<C_S_AXI_CTRL_BUS_ADDR_WIDTH,C_S_AXI_CTRL_BUS_DATA_WIDTH>* doCorner_CTRL_BUS_s_axi_U;
AXIvideo2Mat* AXIvideo2Mat_U0;
rgb2gray* rgb2gray_U0;
FAST_t_opr* FAST_t_opr_U0;
Dilate* Dilate_U0;
PaintMask* PaintMask_U0;
Mat2AXIvideo* Mat2AXIvideo_U0;
fifo_w8_d2_A* img_0_data_stream_0_U;
fifo_w8_d2_A* img_0_data_stream_1_U;
fifo_w8_d2_A* img_0_data_stream_2_U;
fifo_w8_d20000_A* img_1_data_stream_0_U;
fifo_w8_d20000_A* img_1_data_stream_1_U;
fifo_w8_d20000_A* img_1_data_stream_2_U;
fifo_w8_d2_A* img_2_data_stream_0_U;
fifo_w8_d2_A* mask_data_stream_0_s_U;
fifo_w8_d2_A* dmask_data_stream_0_U;
fifo_w8_d2_A* img_3_data_stream_0_U;
fifo_w8_d2_A* img_3_data_stream_1_U;
fifo_w8_d2_A* img_3_data_stream_2_U;
start_for_rgb2grapcA* start_for_rgb2grapcA_U;
start_for_FAST_t_qcK* start_for_FAST_t_qcK_U;
start_for_PaintMarcU* start_for_PaintMarcU_U;
start_for_Dilate_U0* start_for_Dilate_U0_U;
start_for_Mat2AXIsc4* start_for_Mat2AXIsc4_U;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_logic > ap_start;
sc_signal< sc_logic > ap_ready;
sc_signal< sc_logic > ap_done;
sc_signal< sc_logic > ap_idle;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_start;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_done;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_continue;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_idle;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_ready;
sc_signal< sc_logic > AXIvideo2Mat_U0_start_out;
sc_signal< sc_logic > AXIvideo2Mat_U0_start_write;
sc_signal< sc_logic > AXIvideo2Mat_U0_inStream_TREADY;
sc_signal< sc_lv<8> > AXIvideo2Mat_U0_img_data_stream_0_V_din;
sc_signal< sc_logic > AXIvideo2Mat_U0_img_data_stream_0_V_write;
sc_signal< sc_lv<8> > AXIvideo2Mat_U0_img_data_stream_1_V_din;
sc_signal< sc_logic > AXIvideo2Mat_U0_img_data_stream_1_V_write;
sc_signal< sc_lv<8> > AXIvideo2Mat_U0_img_data_stream_2_V_din;
sc_signal< sc_logic > AXIvideo2Mat_U0_img_data_stream_2_V_write;
sc_signal< sc_logic > rgb2gray_U0_ap_start;
sc_signal< sc_logic > rgb2gray_U0_start_full_n;
sc_signal< sc_logic > rgb2gray_U0_ap_done;
sc_signal< sc_logic > rgb2gray_U0_ap_continue;
sc_signal< sc_logic > rgb2gray_U0_ap_idle;
sc_signal< sc_logic > rgb2gray_U0_ap_ready;
sc_signal< sc_logic > rgb2gray_U0_start_out;
sc_signal< sc_logic > rgb2gray_U0_start_write;
sc_signal< sc_logic > rgb2gray_U0_imgIn_data_stream_0_V_read;
sc_signal< sc_logic > rgb2gray_U0_imgIn_data_stream_1_V_read;
sc_signal< sc_logic > rgb2gray_U0_imgIn_data_stream_2_V_read;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_3C_data_stream_0_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_3C_data_stream_0_V_write;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_3C_data_stream_1_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_3C_data_stream_1_V_write;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_3C_data_stream_2_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_3C_data_stream_2_V_write;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_1C_data_stream_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_1C_data_stream_V_write;
sc_signal< sc_logic > FAST_t_opr_U0_ap_start;
sc_signal< sc_logic > FAST_t_opr_U0_ap_done;
sc_signal< sc_logic > FAST_t_opr_U0_ap_continue;
sc_signal< sc_logic > FAST_t_opr_U0_ap_idle;
sc_signal< sc_logic > FAST_t_opr_U0_ap_ready;
sc_signal< sc_logic > FAST_t_opr_U0_start_out;
sc_signal< sc_logic > FAST_t_opr_U0_start_write;
sc_signal< sc_logic > FAST_t_opr_U0_p_src_data_stream_V_read;
sc_signal< sc_lv<8> > FAST_t_opr_U0_p_mask_data_stream_V_din;
sc_signal< sc_logic > FAST_t_opr_U0_p_mask_data_stream_V_write;
sc_signal< sc_logic > Dilate_U0_ap_start;
sc_signal< sc_logic > Dilate_U0_ap_done;
sc_signal< sc_logic > Dilate_U0_ap_continue;
sc_signal< sc_logic > Dilate_U0_ap_idle;
sc_signal< sc_logic > Dilate_U0_ap_ready;
sc_signal< sc_logic > Dilate_U0_p_src_data_stream_V_read;
sc_signal< sc_lv<8> > Dilate_U0_p_dst_data_stream_V_din;
sc_signal< sc_logic > Dilate_U0_p_dst_data_stream_V_write;
sc_signal< sc_logic > PaintMask_U0_ap_start;
sc_signal< sc_logic > PaintMask_U0_ap_done;
sc_signal< sc_logic > PaintMask_U0_ap_continue;
sc_signal< sc_logic > PaintMask_U0_ap_idle;
sc_signal< sc_logic > PaintMask_U0_ap_ready;
sc_signal< sc_logic > PaintMask_U0_start_out;
sc_signal< sc_logic > PaintMask_U0_start_write;
sc_signal< sc_logic > PaintMask_U0_p_src_data_stream_0_V_read;
sc_signal< sc_logic > PaintMask_U0_p_src_data_stream_1_V_read;
sc_signal< sc_logic > PaintMask_U0_p_src_data_stream_2_V_read;
sc_signal< sc_logic > PaintMask_U0_p_mask_data_stream_V_read;
sc_signal< sc_lv<8> > PaintMask_U0_p_dst_data_stream_0_V_din;
sc_signal< sc_logic > PaintMask_U0_p_dst_data_stream_0_V_write;
sc_signal< sc_lv<8> > PaintMask_U0_p_dst_data_stream_1_V_din;
sc_signal< sc_logic > PaintMask_U0_p_dst_data_stream_1_V_write;
sc_signal< sc_lv<8> > PaintMask_U0_p_dst_data_stream_2_V_din;
sc_signal< sc_logic > PaintMask_U0_p_dst_data_stream_2_V_write;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_start;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_done;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_continue;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_idle;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_ready;
sc_signal< sc_logic > Mat2AXIvideo_U0_img_data_stream_0_V_read;
sc_signal< sc_logic > Mat2AXIvideo_U0_img_data_stream_1_V_read;
sc_signal< sc_logic > Mat2AXIvideo_U0_img_data_stream_2_V_read;
sc_signal< sc_lv<24> > Mat2AXIvideo_U0_outStream_TDATA;
sc_signal< sc_logic > Mat2AXIvideo_U0_outStream_TVALID;
sc_signal< sc_lv<3> > Mat2AXIvideo_U0_outStream_TKEEP;
sc_signal< sc_lv<3> > Mat2AXIvideo_U0_outStream_TSTRB;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TUSER;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TLAST;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TID;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TDEST;
sc_signal< sc_logic > ap_sync_continue;
sc_signal< sc_logic > img_0_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_0_data_stream_0_dout;
sc_signal< sc_logic > img_0_data_stream_0_empty_n;
sc_signal< sc_logic > img_0_data_stream_1_full_n;
sc_signal< sc_lv<8> > img_0_data_stream_1_dout;
sc_signal< sc_logic > img_0_data_stream_1_empty_n;
sc_signal< sc_logic > img_0_data_stream_2_full_n;
sc_signal< sc_lv<8> > img_0_data_stream_2_dout;
sc_signal< sc_logic > img_0_data_stream_2_empty_n;
sc_signal< sc_logic > img_1_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_1_data_stream_0_dout;
sc_signal< sc_logic > img_1_data_stream_0_empty_n;
sc_signal< sc_logic > img_1_data_stream_1_full_n;
sc_signal< sc_lv<8> > img_1_data_stream_1_dout;
sc_signal< sc_logic > img_1_data_stream_1_empty_n;
sc_signal< sc_logic > img_1_data_stream_2_full_n;
sc_signal< sc_lv<8> > img_1_data_stream_2_dout;
sc_signal< sc_logic > img_1_data_stream_2_empty_n;
sc_signal< sc_logic > img_2_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_2_data_stream_0_dout;
sc_signal< sc_logic > img_2_data_stream_0_empty_n;
sc_signal< sc_logic > mask_data_stream_0_s_full_n;
sc_signal< sc_lv<8> > mask_data_stream_0_s_dout;
sc_signal< sc_logic > mask_data_stream_0_s_empty_n;
sc_signal< sc_logic > dmask_data_stream_0_full_n;
sc_signal< sc_lv<8> > dmask_data_stream_0_dout;
sc_signal< sc_logic > dmask_data_stream_0_empty_n;
sc_signal< sc_logic > img_3_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_3_data_stream_0_dout;
sc_signal< sc_logic > img_3_data_stream_0_empty_n;
sc_signal< sc_logic > img_3_data_stream_1_full_n;
sc_signal< sc_lv<8> > img_3_data_stream_1_dout;
sc_signal< sc_logic > img_3_data_stream_1_empty_n;
sc_signal< sc_logic > img_3_data_stream_2_full_n;
sc_signal< sc_lv<8> > img_3_data_stream_2_dout;
sc_signal< sc_logic > img_3_data_stream_2_empty_n;
sc_signal< sc_logic > ap_sync_done;
sc_signal< sc_logic > ap_sync_ready;
sc_signal< sc_lv<1> > start_for_rgb2gray_U0_din;
sc_signal< sc_logic > start_for_rgb2gray_U0_full_n;
sc_signal< sc_lv<1> > start_for_rgb2gray_U0_dout;
sc_signal< sc_logic > start_for_rgb2gray_U0_empty_n;
sc_signal< sc_lv<1> > start_for_FAST_t_opr_U0_din;
sc_signal< sc_logic > start_for_FAST_t_opr_U0_full_n;
sc_signal< sc_lv<1> > start_for_FAST_t_opr_U0_dout;
sc_signal< sc_logic > start_for_FAST_t_opr_U0_empty_n;
sc_signal< sc_lv<1> > start_for_PaintMask_U0_din;
sc_signal< sc_logic > start_for_PaintMask_U0_full_n;
sc_signal< sc_lv<1> > start_for_PaintMask_U0_dout;
sc_signal< sc_logic > start_for_PaintMask_U0_empty_n;
sc_signal< sc_lv<1> > start_for_Dilate_U0_din;
sc_signal< sc_logic > start_for_Dilate_U0_full_n;
sc_signal< sc_lv<1> > start_for_Dilate_U0_dout;
sc_signal< sc_logic > start_for_Dilate_U0_empty_n;
sc_signal< sc_logic > Dilate_U0_start_full_n;
sc_signal< sc_logic > Dilate_U0_start_write;
sc_signal< sc_lv<1> > start_for_Mat2AXIvideo_U0_din;
sc_signal< sc_logic > start_for_Mat2AXIvideo_U0_full_n;
sc_signal< sc_lv<1> > start_for_Mat2AXIvideo_U0_dout;
sc_signal< sc_logic > start_for_Mat2AXIvideo_U0_empty_n;
sc_signal< sc_logic > Mat2AXIvideo_U0_start_full_n;
sc_signal< sc_logic > Mat2AXIvideo_U0_start_write;
static const int C_S_AXI_DATA_WIDTH;
static const int C_S_AXI_WSTRB_WIDTH;
static const int C_S_AXI_ADDR_WIDTH;
static const sc_logic ap_const_logic_1;
static const sc_lv<24> ap_const_lv24_0;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_logic ap_const_logic_0;
// Thread declarations
void thread_ap_var_for_const0();
void thread_AXIvideo2Mat_U0_ap_continue();
void thread_AXIvideo2Mat_U0_ap_start();
void thread_Dilate_U0_ap_continue();
void thread_Dilate_U0_ap_start();
void thread_Dilate_U0_start_full_n();
void thread_Dilate_U0_start_write();
void thread_FAST_t_opr_U0_ap_continue();
void thread_FAST_t_opr_U0_ap_start();
void thread_Mat2AXIvideo_U0_ap_continue();
void thread_Mat2AXIvideo_U0_ap_start();
void thread_Mat2AXIvideo_U0_start_full_n();
void thread_Mat2AXIvideo_U0_start_write();
void thread_PaintMask_U0_ap_continue();
void thread_PaintMask_U0_ap_start();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_rst_n_inv();
void thread_ap_sync_continue();
void thread_ap_sync_done();
void thread_ap_sync_ready();
void thread_inStream_TREADY();
void thread_outStream_TDATA();
void thread_outStream_TDEST();
void thread_outStream_TID();
void thread_outStream_TKEEP();
void thread_outStream_TLAST();
void thread_outStream_TSTRB();
void thread_outStream_TUSER();
void thread_outStream_TVALID();
void thread_rgb2gray_U0_ap_continue();
void thread_rgb2gray_U0_ap_start();
void thread_rgb2gray_U0_start_full_n();
void thread_start_for_Dilate_U0_din();
void thread_start_for_FAST_t_opr_U0_din();
void thread_start_for_Mat2AXIvideo_U0_din();
void thread_start_for_PaintMask_U0_din();
void thread_start_for_rgb2gray_U0_din();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
#include "systemc.h"
#include "../cnm_base.h"
class pch_driver: public sc_module {
public:
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> RD; // DRAM read command
sc_out<sc_logic> WR; // DRAM write command
sc_out<sc_logic> ACT; // DRAM activate command
// sc_out<sc_logic> RSTB; //
sc_out<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_out<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_out<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_out<sc_lv<DQ_BITS> > DQ; // Data input from DRAM controller (output makes no sense)
sc_out<sc_lv<GRF_WIDTH> > even_in[CORES_PER_PCH]; // Direct data in/out to the even banks
sc_out<sc_lv<GRF_WIDTH> > odd_in[CORES_PER_PCH]; // Direct data in/out to the odd banks
sc_in<sc_lv<GRF_WIDTH> > even_out[CORES_PER_PCH];// Direct data in/out to the even banks
sc_in<sc_lv<GRF_WIDTH> > odd_out[CORES_PER_PCH]; // Direct data in/out to the odd banks
#else
sc_out<bool> rst;
sc_out<bool> RD; // DRAM read command
sc_out<bool> WR; // DRAM write command
sc_out<bool> ACT; // DRAM activate command
// sc_out<bool> RSTB; //
sc_out<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<bool> pim_mode; // Signals if the PIM mode is enabled
sc_out<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_out<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_out<sc_uint<DQ_BITS> > DQ; // Data input from DRAM controller (output makes no sense)
sc_inout_rv<GRF_WIDTH> even_buses[CORES_PER_PCH]; // Direct data in/out to the even banks
sc_inout_rv<GRF_WIDTH> odd_buses[CORES_PER_PCH]; // Direct data in/out to the odd banks
#endif
std::string filename;
SC_HAS_PROCESS(pch_driver);
pch_driver(sc_module_name name_, std::string filename_) : sc_module(name_), filename(filename_) {
SC_THREAD(driver_thread);
}
void driver_thread();
};
|
#include <systemc.h>
class sc_mutexx : public sc_prim_channel
{
public:
sc_event _free;
bool _locked;
// blocks until mutex could be locked
void lock()
{
while( _locked ) {
wait( _free );
}
_locked = true;
}
// returns false if mutex could not be locked
bool trylock()
{
if( _locked )
return false;
else
return true;
}
// unlocks mutex
void unlock()
{
_locked = false;
_free.notify();
}
// constructor
sc_mutexx(){
// _locked = false;
}
};
|
#ifndef TESTBENCH_H
#define TESTBENCH_H
#include <systemc.h>
#include <iostream>
using namespace std;
template <class DataType>
class Testbench : public sc_module
{
private:
void test()
{
print();
en_out = 1;
data_out = 1234;
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
sc_stop();
}
void print()
{
cout << clk_in.read() << " | "
<< en_out.read() << " |\n";
}
public:
sc_in<bool> clk_in;
sc_out<bool> en_out;
sc_out<DataType> data_out;
sc_in<DataType> data_in;
SC_CTOR(Testbench)
{
cout << "Pipe_1 | Pipe_2 | Pipe_3 | Tiempo | Enable |\n";
cout << "------------------------------------------------------------|\n";
SC_THREAD(test);
sensitive << clk_in;
}
};
#endif//TESTBENCH_H
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _memcachedPipeline_splitter_HH_
#define _memcachedPipeline_splitter_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct memcachedPipeline_splitter : public sc_module {
// Port declarations 16
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<256> > hashTable2splitter_V_dout;
sc_in< sc_logic > hashTable2splitter_V_empty_n;
sc_out< sc_logic > hashTable2splitter_V_read;
sc_out< sc_lv<256> > splitter2valueStoreFlash_V_din;
sc_in< sc_logic > splitter2valueStoreFlash_V_full_n;
sc_out< sc_logic > splitter2valueStoreFlash_V_write;
sc_out< sc_lv<256> > splitter2valueStoreDram_V_din;
sc_in< sc_logic > splitter2valueStoreDram_V_full_n;
sc_out< sc_logic > splitter2valueStoreDram_V_write;
// Module declarations
memcachedPipeline_splitter(sc_module_name name);
SC_HAS_PROCESS(memcachedPipeline_splitter);
~memcachedPipeline_splitter();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_sig_cseq_ST_pp0_stg0_fsm_0;
sc_signal< bool > ap_sig_bdd_20;
sc_signal< sc_logic > ap_reg_ppiten_pp0_it0;
sc_signal< sc_logic > ap_reg_ppiten_pp0_it1;
sc_signal< sc_logic > ap_reg_ppiten_pp0_it2;
sc_signal< sc_lv<1> > tmp_nbreadreq_fu_128_p3;
sc_signal< bool > ap_sig_bdd_52;
sc_signal< sc_lv<1> > tmp_reg_278;
sc_signal< sc_lv<1> > ap_reg_ppstg_tmp_reg_278_pp0_it1;
sc_signal< sc_lv<1> > is_validFlag_loc_reg_168;
sc_signal< sc_lv<1> > dramOrFlash_V_loc_reg_180;
sc_signal< bool > ap_sig_bdd_81;
sc_signal< sc_lv<1> > is_validFlag;
sc_signal< sc_lv<1> > dramOrFlash_V;
sc_signal< sc_lv<256> > tmp112_reg_282;
sc_signal< sc_lv<256> > ap_reg_ppstg_tmp112_reg_282_pp0_it1;
sc_signal< sc_lv<1> > tmp_SOP_V_fu_212_p3;
sc_signal< sc_lv<1> > tmp_SOP_V_reg_289;
sc_signal< sc_lv<1> > not_s_fu_230_p2;
sc_signal< sc_lv<1> > not_s_reg_293;
sc_signal< sc_lv<1> > ap_reg_phiprechg_is_validFlag_flag_reg_156pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_is_validFlag_flag_reg_156pp0_it1;
sc_signal< sc_lv<1> > is_validFlag_flag_phi_fu_160_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_is_validFlag_loc_reg_168pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_is_validFlag_loc_reg_168pp0_it1;
sc_signal< sc_lv<1> > is_validFlag_loc_phi_fu_172_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_dramOrFlash_V_loc_reg_180pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_dramOrFlash_V_loc_reg_180pp0_it1;
sc_signal< sc_lv<1> > p_is_validFlag_flag_fu_258_p2;
sc_signal< sc_lv<1> > ap_reg_phiprechg_is_validFlag_flag_2_reg_190pp0_it1;
sc_signal< sc_lv<1> > is_validFlag_flag_2_phi_fu_193_p4;
sc_signal< sc_lv<1> > not_din_EOP_V_assign_load_2_ne_fu_265_p2;
sc_signal< sc_lv<1> > ap_reg_phiprechg_is_validFlag_new_2_reg_201pp0_it1;
sc_signal< sc_lv<1> > is_validFlag_new_2_phi_fu_204_p4;
sc_signal< sc_lv<32> > p_Result_s_fu_220_p4;
sc_signal< sc_lv<1> > tmp_2_fu_251_p3;
sc_signal< sc_lv<1> > ap_NS_fsm;
sc_signal< sc_logic > ap_sig_pprstidle_pp0;
sc_signal< bool > ap_sig_bdd_112;
sc_signal< bool > ap_sig_bdd_88;
sc_signal< bool > ap_sig_bdd_123;
sc_signal< bool > ap_sig_bdd_117;
sc_signal< bool > ap_sig_bdd_160;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_pp0_stg0_fsm_0;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_7C;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_27;
static const sc_lv<32> ap_const_lv32_801;
static const sc_lv<32> ap_const_lv32_7F;
static const sc_lv<256> ap_const_lv256_lc_1;
static const bool ap_true;
// Thread declarations
void thread_ap_clk_pos_reset_();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_reg_phiprechg_dramOrFlash_V_loc_reg_180pp0_it0();
void thread_ap_reg_phiprechg_is_validFlag_flag_2_reg_190pp0_it1();
void thread_ap_reg_phiprechg_is_validFlag_flag_reg_156pp0_it0();
void thread_ap_reg_phiprechg_is_validFlag_loc_reg_168pp0_it0();
void thread_ap_reg_phiprechg_is_validFlag_new_2_reg_201pp0_it1();
void thread_ap_reg_ppiten_pp0_it0();
void thread_ap_sig_bdd_112();
void thread_ap_sig_bdd_117();
void thread_ap_sig_bdd_123();
void thread_ap_sig_bdd_160();
void thread_ap_sig_bdd_20();
void thread_ap_sig_bdd_52();
void thread_ap_sig_bdd_81();
void thread_ap_sig_bdd_88();
void thread_ap_sig_cseq_ST_pp0_stg0_fsm_0();
void thread_ap_sig_pprstidle_pp0();
void thread_hashTable2splitter_V_read();
void thread_is_validFlag_flag_2_phi_fu_193_p4();
void thread_is_validFlag_flag_phi_fu_160_p4();
void thread_is_validFlag_loc_phi_fu_172_p4();
void thread_is_validFlag_new_2_phi_fu_204_p4();
void thread_not_din_EOP_V_assign_load_2_ne_fu_265_p2();
void thread_not_s_fu_230_p2();
void thread_p_Result_s_fu_220_p4();
void thread_p_is_validFlag_flag_fu_258_p2();
void thread_splitter2valueStoreDram_V_din();
void thread_splitter2valueStoreDram_V_write();
void thread_splitter2valueStoreFlash_V_din();
void thread_splitter2valueStoreFlash_V_write();
void thread_tmp_2_fu_251_p3();
void thread_tmp_SOP_V_fu_212_p3();
void thread_tmp_nbreadreq_fu_128_p3();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_e620_one_0_H_
#define _bd_e620_one_0_H_
#include "xlconstant_v1_1_5.h"
#include "systemc.h"
class bd_e620_one_0 : public sc_module {
public:
xlconstant_v1_1_5<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_e620_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_13_0_H_
#define _icyradio_GND_13_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_13_0 : public sc_module {
public:
xlconstant_v1_1_8<32,0> mod;
sc_out< sc_bv<32> > dout;
icyradio_GND_13_0 (sc_core::sc_module_name name);
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Ext_KWTA64k_HH_
#define _Ext_KWTA64k_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Ext_KWTA64k_mux_5mb6.h"
#include "Ext_KWTA64k_mux_5ncg.h"
#include "Ext_KWTA64k_mux_5ocq.h"
#include "Ext_KWTA64k_maintbkb.h"
#include "Ext_KWTA64k_heap_cud.h"
#include "Ext_KWTA64k_grouphbi.h"
#include "Ext_KWTA64k_groupibs.h"
#include "Ext_KWTA64k_shiftjbC.h"
#include "Ext_KWTA64k_mark_kbM.h"
#include "Ext_KWTA64k_extralbW.h"
namespace ap_rtl {
struct Ext_KWTA64k : public sc_module {
// Port declarations 30
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<32> > alloc_size;
sc_in< sc_logic > alloc_size_ap_vld;
sc_out< sc_logic > alloc_size_ap_ack;
sc_in< sc_lv<32> > alloc_free_target;
sc_in< sc_logic > alloc_free_target_ap_vld;
sc_out< sc_logic > alloc_free_target_ap_ack;
sc_out< sc_lv<32> > alloc_addr;
sc_out< sc_logic > alloc_addr_ap_vld;
sc_in< sc_logic > alloc_addr_ap_ack;
sc_in< sc_lv<8> > alloc_cmd;
sc_in< sc_logic > alloc_cmd_ap_vld;
sc_out< sc_logic > alloc_cmd_ap_ack;
sc_out< sc_lv<8> > com_port_layer_V;
sc_out< sc_logic > com_port_layer_V_ap_vld;
sc_in< sc_logic > com_port_layer_V_ap_ack;
sc_out< sc_lv<16> > com_port_target_V;
sc_out< sc_logic > com_port_target_V_ap_vld;
sc_in< sc_logic > com_port_target_V_ap_ack;
sc_in< sc_lv<16> > com_port_allocated_addr_V;
sc_in< sc_logic > com_port_allocated_addr_V_ap_vld;
sc_out< sc_logic > com_port_allocated_addr_V_ap_ack;
sc_out< sc_lv<8> > com_port_cmd;
sc_out< sc_logic > com_port_cmd_ap_vld;
sc_in< sc_logic > com_port_cmd_ap_ack;
// Module declarations
Ext_KWTA64k(sc_module_name name);
SC_HAS_PROCESS(Ext_KWTA64k);
~Ext_KWTA64k();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
Ext_KWTA64k_maintbkb* maintain_mask_V_U;
Ext_KWTA64k_heap_cud* heap_tree_V_0_U;
Ext_KWTA64k_heap_cud* heap_tree_V_1_U;
Ext_KWTA64k_heap_cud* heap_tree_V_2_U;
Ext_KWTA64k_heap_cud* heap_tree_V_3_U;
Ext_KWTA64k_heap_cud* heap_tree_V_4_U;
Ext_KWTA64k_grouphbi* group_tree_V_U;
Ext_KWTA64k_groupibs* group_tree_mask_V_U;
Ext_KWTA64k_shiftjbC* shift_constant_V_U;
Ext_KWTA64k_mark_kbM* mark_mask_V_U;
Ext_KWTA64k_extralbW* extra_mask_V_U;
Ext_KWTA64k_mux_5mb6<1,1,32,32,32,32,32,16,32>* Ext_KWTA64k_mux_5mb6_U1;
Ext_KWTA64k_mux_5ncg<1,1,32,32,32,32,32,20,32>* Ext_KWTA64k_mux_5ncg_U2;
Ext_KWTA64k_mux_5mb6<1,1,32,32,32,32,32,16,32>* Ext_KWTA64k_mux_5mb6_U3;
Ext_KWTA64k_mux_5ocq<1,1,32,32,32,32,32,33,32>* Ext_KWTA64k_mux_5ocq_U4;
Ext_KWTA64k_mux_5mb6<1,1,32,32,32,32,32,16,32>* Ext_KWTA64k_mux_5mb6_U5;
sc_signal< sc_lv<63> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<3> > maintain_mask_V_address0;
sc_signal< sc_logic > maintain_mask_V_ce0;
sc_signal< sc_lv<33> > maintain_mask_V_q0;
sc_signal< sc_lv<64> > top_heap_V_0;
sc_signal< sc_lv<64> > top_heap_V_1;
sc_signal< sc_lv<64> > top_heap_V_2;
sc_signal< sc_lv<64> > top_heap_V_3;
sc_signal< sc_lv<64> > top_heap_V_4;
sc_signal< sc_lv<6> > heap_tree_V_0_address0;
sc_signal< sc_logic > heap_tree_V_0_ce0;
sc_signal< sc_logic > heap_tree_V_0_we0;
sc_signal< sc_lv<32> > heap_tree_V_0_d0;
sc_signal< sc_lv<32> > heap_tree_V_0_q0;
sc_signal< sc_lv<6> > heap_tree_V_1_address0;
sc_signal< sc_logic > heap_tree_V_1_ce0;
sc_signal< sc_logic > heap_tree_V_1_we0;
sc_signal< sc_lv<32> > heap_tree_V_1_d0;
sc_signal< sc_lv<32> > heap_tree_V_1_q0;
sc_signal< sc_lv<6> > heap_tree_V_2_address0;
sc_signal< sc_logic > heap_tree_V_2_ce0;
sc_signal< sc_logic > heap_tree_V_2_we0;
sc_signal< sc_lv<32> > heap_tree_V_2_d0;
sc_signal< sc_lv<32> > heap_tree_V_2_q0;
sc_signal< sc_lv<6> > heap_tree_V_3_address0;
sc_signal< sc_logic > heap_tree_V_3_ce0;
sc_signal< sc_logic > heap_tree_V_3_we0;
sc_signal< sc_lv<32> > heap_tree_V_3_d0;
sc_signal< sc_lv<32> > heap_tree_V_3_q0;
sc_signal< sc_lv<6> > heap_tree_V_4_address0;
sc_signal< sc_logic > heap_tree_V_4_ce0;
sc_signal< sc_logic > heap_tree_V_4_we0;
sc_signal< sc_lv<32> > heap_tree_V_4_d0;
sc_signal< sc_lv<32> > heap_tree_V_4_q0;
sc_signal< sc_lv<11> > group_tree_V_address0;
sc_signal< sc_logic > group_tree_V_ce0;
sc_signal< sc_logic > group_tree_V_we0;
sc_signal< sc_lv<64> > group_tree_V_d0;
sc_signal< sc_lv<64> > group_tree_V_q0;
sc_signal< sc_lv<3> > group_tree_mask_V_address0;
sc_signal< sc_logic > group_tree_mask_V_ce0;
sc_signal< sc_lv<31> > group_tree_mask_V_q0;
sc_signal< sc_lv<3> > shift_constant_V_address0;
sc_signal< sc_logic > shift_constant_V_ce0;
sc_signal< sc_lv<5> > shift_constant_V_q0;
sc_signal< sc_lv<7> > mark_mask_V_address0;
sc_signal< sc_logic > mark_mask_V_ce0;
sc_signal< sc_lv<62> > mark_mask_V_q0;
sc_signal< sc_lv<3> > extra_mask_V_address0;
sc_signal< sc_logic > extra_mask_V_ce0;
sc_signal< sc_lv<5> > extra_mask_V_q0;
sc_signal< sc_logic > alloc_size_blk_n;
sc_signal< sc_logic > alloc_free_target_blk_n;
sc_signal< sc_logic > alloc_addr_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state52;
sc_signal< sc_lv<1> > tmp_46_fu_4786_p3;
sc_signal< sc_logic > ap_CS_fsm_state38;
sc_signal< sc_lv<1> > or_cond_101_fu_3986_p2;
sc_signal< sc_logic > ap_CS_fsm_state42;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<1> > tmp_9_fu_2458_p2;
sc_signal< sc_lv<1> > tmp_5_fu_2463_p2;
sc_signal< sc_logic > alloc_cmd_blk_n;
sc_signal< sc_logic > com_port_layer_V_blk_n;
sc_signal< sc_lv<1> > grp_fu_2243_p2;
sc_signal< sc_logic > ap_CS_fsm_state18;
sc_signal< sc_lv<1> > tmp_5_reg_5301;
sc_signal< sc_lv<1> > tmp_11_reg_5305;
sc_signal< sc_lv<1> > tmp_73_reg_5608;
sc_signal< sc_logic > com_port_target_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state43;
sc_signal< sc_logic > ap_CS_fsm_state19;
sc_signal< sc_logic > com_port_allocated_addr_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state51;
sc_signal< sc_logic > com_port_cmd_blk_n;
sc_signal< sc_lv<5> > grp_fu_2249_p2;
sc_signal< sc_lv<5> > reg_2290;
sc_signal< sc_logic > ap_sig_ioackin_alloc_addr_ap_ack;
sc_signal< bool > ap_predicate_op142_write_state4;
sc_signal< sc_logic > ap_sig_ioackin_com_port_cmd_ap_ack;
sc_signal< bool > ap_predicate_op152_write_state4;
sc_signal< sc_logic > ap_sig_ioackin_com_port_layer_V_ap_ack;
sc_signal< bool > ap_predicate_op177_write_state4;
sc_signal< bool > ap_block_state4_io;
sc_signal< sc_logic > ap_CS_fsm_state34;
sc_signal< sc_lv<5> > reg_2294;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_logic > ap_CS_fsm_state41;
sc_signal< sc_lv<32> > reg_2298;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< sc_logic > ap_CS_fsm_state22;
sc_signal< sc_logic > ap_CS_fsm_state36;
sc_signal< sc_logic > ap_CS_fsm_state53;
sc_signal< sc_lv<32> > reg_2316;
sc_signal< sc_lv<32> > reg_2334;
sc_signal< sc_lv<32> > reg_2352;
sc_signal< sc_lv<32> > reg_2370;
sc_signal< sc_lv<33> > reg_2376;
sc_signal< sc_logic > ap_CS_fsm_state31;
sc_signal< sc_logic > ap_CS_fsm_state62;
sc_signal< sc_lv<8> > alloc_cmd_read_reg_5247;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<32> > size_V_reg_5253;
sc_signal< sc_lv<32> > alloc_free_target_re_reg_5258;
sc_signal< sc_lv<20> > free_target_V_fu_2380_p1;
sc_signal< sc_lv<20> > free_target_V_reg_5267;
sc_signal< sc_lv<32> > p_Result_30_fu_2390_p4;
sc_signal< sc_lv<32> > p_Result_30_reg_5273;
sc_signal< sc_lv<1> > tmp_fu_2400_p2;
sc_signal< sc_lv<1> > tmp_reg_5279;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<16> > BB_V_fu_2419_p4;
sc_signal< sc_lv<16> > BB_V_reg_5286;
sc_signal< sc_lv<1> > tmp_3_fu_2435_p2;
sc_signal< sc_lv<1> > tmp_3_reg_5293;
sc_signal< sc_lv<1> > tmp_9_reg_5297;
sc_signal< sc_lv<16> > addr_HTA_V_fu_2479_p1;
sc_signal< sc_lv<16> > addr_HTA_V_reg_5319;
sc_signal< sc_lv<5> > loc2_V_1_reg_5324;
sc_signal< sc_lv<10> > tmp_15_fu_2492_p4;
sc_signal< sc_lv<10> > tmp_15_reg_5329;
sc_signal< sc_lv<11> > phitmp2_fu_2501_p1;
sc_signal< sc_lv<11> > phitmp2_reg_5335;
sc_signal< sc_lv<1> > tmp_s_reg_5342;
sc_signal< sc_lv<64> > p_Val2_65_reg_5346;
sc_signal< sc_lv<64> > p_Val2_57_reg_5351;
sc_signal< sc_lv<64> > p_Val2_59_reg_5356;
sc_signal< sc_lv<64> > p_Val2_61_reg_5361;
sc_signal< sc_lv<64> > p_Val2_63_reg_5366;
sc_signal< sc_lv<64> > TMP_0_V_fu_2557_p3;
sc_signal< sc_lv<64> > TMP_0_V_reg_5371;
sc_signal< sc_lv<64> > p_not_fu_2565_p2;
sc_signal< sc_lv<64> > p_not_reg_5376;
sc_signal< sc_lv<20> > r_V_41_fu_2626_p3;
sc_signal< sc_lv<20> > r_V_41_reg_5381;
sc_signal< sc_lv<5> > extra_mask_V_load_reg_5387;
sc_signal< sc_lv<6> > tmp_48_fu_2634_p2;
sc_signal< sc_lv<6> > tmp_48_reg_5392;
sc_signal< sc_lv<6> > loc_in_group_tree_V_3_fu_2656_p2;
sc_signal< sc_lv<6> > loc_in_group_tree_V_3_reg_5397;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<20> > tmp_50_fu_2665_p2;
sc_signal< sc_lv<20> > tmp_50_reg_5402;
sc_signal< sc_lv<5> > loc2_V_2_fu_2674_p1;
sc_signal< sc_lv<5> > loc2_V_2_reg_5408;
sc_signal< sc_lv<11> > r_V_11_reg_5413;
sc_signal< sc_lv<11> > group_tree_V_addr_reg_5419;
sc_signal< sc_lv<4> > tmp_111_fu_2708_p1;
sc_signal< sc_lv<4> > tmp_111_reg_5429;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<15> > grp_fu_2255_p4;
sc_signal< sc_lv<15> > tmp_18_reg_5434;
sc_signal< sc_lv<62> > tmp_54_fu_2728_p2;
sc_signal< sc_lv<62> > tmp_54_reg_5439;
sc_signal< sc_lv<2> > tmp_58_reg_5444;
sc_signal< sc_lv<16> > addr_HTA_V_1_fu_2744_p1;
sc_signal< sc_lv<16> > addr_HTA_V_1_reg_5449;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<64> > r_V_42_fu_2750_p3;
sc_signal< sc_lv<16> > p_Result_31_fu_2756_p4;
sc_signal< sc_lv<64> > r_V_15_fu_2770_p2;
sc_signal< sc_lv<4> > now1_V_fu_2776_p2;
sc_signal< sc_lv<64> > p_Result_32_fu_2827_p4;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_lv<1> > tmp_68_fu_2797_p2;
sc_signal< sc_lv<16> > p_Result_33_fu_2837_p4;
sc_signal< sc_lv<64> > r_V_19_fu_2851_p2;
sc_signal< sc_lv<4> > now1_V_1_fu_2857_p2;
sc_signal< sc_lv<5> > arrayNo4_reg_5497;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_lv<6> > heap_tree_V_0_addr_2_reg_5502;
sc_signal< sc_lv<6> > heap_tree_V_1_addr_2_reg_5507;
sc_signal< sc_lv<6> > heap_tree_V_2_addr_2_reg_5512;
sc_signal< sc_lv<6> > heap_tree_V_3_addr_2_reg_5517;
sc_signal< sc_lv<6> > heap_tree_V_4_addr_2_reg_5522;
sc_signal< sc_lv<2> > tmp_152_fu_2897_p1;
sc_signal< sc_lv<2> > tmp_152_reg_5527;
sc_signal< sc_lv<32> > i_assign_3_fu_2901_p1;
sc_signal< sc_lv<32> > i_assign_3_reg_5532;
sc_signal< sc_lv<32> > p_Result_s_fu_2929_p4;
sc_signal< sc_lv<32> > p_Result_s_reg_5540;
sc_signal< sc_lv<32> > i_assign_4_fu_2943_p1;
sc_signal< sc_lv<32> > i_assign_4_reg_5549;
sc_signal< sc_logic > ap_CS_fsm_state12;
sc_signal< sc_lv<12> > rhs_V_7_cast_fu_2967_p1;
sc_signal< sc_lv<12> > rhs_V_7_cast_reg_5557;
sc_signal< sc_lv<6> > tmp_116_fu_2992_p4;
sc_signal< sc_lv<6> > tmp_116_reg_5563;
sc_signal< sc_lv<32> > p_Result_4_fu_3050_p4;
sc_signal< sc_lv<32> > p_Result_4_reg_5567;
sc_signal< sc_lv<6> > tmp_130_fu_3100_p4;
sc_signal< sc_lv<6> > tmp_130_reg_5578;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<32> > p_Result_8_fu_3138_p4;
sc_signal< sc_lv<32> > p_Result_8_reg_5582;
sc_signal< sc_lv<1> > cond_fu_3170_p2;
sc_signal< sc_lv<1> > cond_reg_5591;
sc_signal< sc_logic > ap_CS_fsm_state15;
sc_signal< sc_lv<32> > p_Result_16_fu_3219_p4;
sc_signal< sc_lv<32> > p_Result_16_reg_5596;
sc_signal< sc_logic > ap_CS_fsm_state16;
sc_signal< sc_lv<1> > p_Repl2_18_fu_3238_p2;
sc_signal< sc_lv<1> > p_Repl2_18_reg_5603;
sc_signal< sc_logic > ap_CS_fsm_state17;
sc_signal< sc_lv<1> > tmp_73_fu_3244_p2;
sc_signal< sc_logic > ap_CS_fsm_state21;
sc_signal< sc_lv<1> > grp_fu_2284_p2;
sc_signal< sc_lv<4> > arrayNo1_reg_5620;
sc_signal< sc_lv<6> > heap_tree_V_0_addr_1_reg_5625;
sc_signal< sc_lv<6> > heap_tree_V_1_addr_1_reg_5630;
sc_signal< sc_lv<6> > heap_tree_V_2_addr_1_reg_5635;
sc_signal< sc_lv<6> > heap_tree_V_3_addr_1_reg_5640;
sc_signal< sc_lv<6> > heap_tree_V_4_addr_1_reg_5645;
sc_signal< sc_lv<32> > r_V_39_fu_3359_p2;
sc_signal< sc_lv<32> > r_V_39_reg_5655;
sc_signal< sc_lv<32> > tmp_49_fu_3384_p2;
sc_signal< sc_lv<32> > tmp_49_reg_5664;
sc_signal< sc_logic > ap_CS_fsm_state23;
sc_signal< sc_lv<32> > i_assign_1_fu_3393_p1;
sc_signal< sc_lv<32> > i_assign_1_reg_5673;
sc_signal< sc_logic > ap_CS_fsm_state24;
sc_signal< sc_lv<5> > tmp_115_fu_3422_p4;
sc_signal< sc_lv<5> > tmp_115_reg_5681;
sc_signal< sc_lv<32> > tmp_55_fu_3480_p2;
sc_signal< sc_lv<32> > tmp_55_reg_5685;
sc_signal< sc_lv<5> > tmp_129_fu_3510_p4;
sc_signal< sc_lv<5> > tmp_129_reg_5696;
sc_signal< sc_logic > ap_CS_fsm_state26;
sc_signal< sc_lv<32> > tmp_57_fu_3548_p2;
sc_signal< sc_lv<32> > tmp_57_reg_5700;
sc_signal< sc_lv<1> > cond2_fu_3576_p2;
sc_signal< sc_lv<1> > cond2_reg_5709;
sc_signal< sc_logic > ap_CS_fsm_state27;
sc_signal< sc_lv<32> > tmp_59_fu_3609_p2;
sc_signal< sc_lv<32> > tmp_59_reg_5714;
sc_signal< sc_logic > ap_CS_fsm_state28;
sc_signal< sc_lv<64> > p_Result_14_fu_3646_p4;
sc_signal< sc_logic > ap_CS_fsm_state30;
sc_signal< sc_lv<64> > tmp_44_fu_3716_p2;
sc_signal< sc_logic > ap_CS_fsm_state32;
sc_signal< sc_lv<64> > tmp_8_fu_3728_p1;
sc_signal< sc_lv<64> > tmp_8_reg_5731;
sc_signal< sc_lv<64> > tmp0_V_5_fu_3732_p2;
sc_signal< sc_lv<64> > tmp0_V_5_reg_5737;
sc_signal< sc_lv<7> > p_0167_0_i1_cast_fu_3776_p1;
sc_signal< sc_lv<7> > p_0167_0_i1_cast_reg_5757;
sc_signal< sc_lv<7> > p_0252_0_i1_cast_fu_3786_p1;
sc_signal< sc_lv<7> > p_0252_0_i1_cast_reg_5765;
sc_signal< sc_lv<7> > p_0248_0_i1_cast_fu_3796_p1;
sc_signal< sc_lv<7> > p_0248_0_i1_cast_reg_5773;
sc_signal< sc_lv<8> > tmp_76_fu_3839_p2;
sc_signal< sc_lv<8> > tmp_76_reg_5781;
sc_signal< sc_logic > ap_CS_fsm_state35;
sc_signal< sc_lv<6> > heap_tree_V_0_addr_3_reg_5791;
sc_signal< sc_lv<6> > heap_tree_V_1_addr_3_reg_5796;
sc_signal< sc_lv<6> > heap_tree_V_2_addr_3_reg_5801;
sc_signal< sc_lv<6> > heap_tree_V_3_addr_3_reg_5806;
sc_signal< sc_lv<6> > heap_tree_V_4_addr_3_reg_5811;
sc_signal< sc_lv<32> > tmp_80_fu_3907_p7;
sc_signal< sc_lv<32> > tmp_80_reg_5816;
sc_signal< sc_lv<32> > tmp_79_fu_3923_p2;
sc_signal< sc_lv<32> > tmp_79_reg_5823;
sc_signal< sc_lv<32> > tmp_81_fu_3929_p2;
sc_signal< sc_lv<32> > tmp_81_reg_5828;
sc_signal< sc_logic > ap_CS_fsm_state37;
sc_signal< sc_lv<6> > p_061_0_i_cast_fu_3958_p1;
sc_signal< sc_lv<6> > p_061_0_i_cast_reg_5842;
sc_signal< sc_lv<6> > tmp_84_fu_3972_p2;
sc_signal< sc_lv<6> > tmp_84_reg_5850;
sc_signal< bool > ap_block_state38_io;
sc_signal< sc_lv<1> > or_cond_101_reg_5855;
sc_signal< sc_lv<13> > tree_offset_V_fu_4003_p2;
sc_signal< sc_lv<13> > tree_offset_V_reg_5859;
sc_signal< sc_lv<11> > group_tree_V_addr_1_reg_5865;
sc_signal< sc_lv<64> > lhs_V_4_reg_5875;
sc_signal< sc_logic > ap_CS_fsm_state39;
sc_signal< sc_lv<62> > tmp_178_fu_4014_p1;
sc_signal< sc_lv<62> > tmp_178_reg_5884;
sc_signal< sc_lv<16> > AA_V_3_fu_4046_p1;
sc_signal< sc_lv<16> > AA_V_3_reg_5889;
sc_signal< sc_lv<16> > BB_V_3_reg_5894;
sc_signal< sc_lv<16> > CC_V_1_reg_5899;
sc_signal< sc_lv<14> > tmp_90_reg_5904;
sc_signal< sc_lv<16> > tree_offset_V_cast_fu_4080_p1;
sc_signal< sc_lv<16> > tree_offset_V_cast_reg_5909;
sc_signal< sc_logic > ap_CS_fsm_state40;
sc_signal< sc_lv<7> > p_0167_0_i_cast_fu_4088_p1;
sc_signal< sc_lv<7> > p_0167_0_i_cast_reg_5917;
sc_signal< sc_lv<7> > tmp91_fu_4115_p2;
sc_signal< sc_lv<7> > tmp91_reg_5931;
sc_signal< sc_lv<8> > tmp_95_fu_4141_p2;
sc_signal< sc_lv<8> > tmp_95_reg_5941;
sc_signal< sc_lv<6> > lhs_V_8_cast_fu_4147_p1;
sc_signal< sc_lv<6> > lhs_V_8_cast_reg_5946;
sc_signal< sc_lv<17> > r_V_28_fu_4182_p2;
sc_signal< sc_lv<17> > r_V_28_reg_5951;
sc_signal< sc_logic > ap_CS_fsm_state45;
sc_signal< sc_lv<62> > val_assign_7_cast_fu_4344_p2;
sc_signal< sc_lv<62> > val_assign_7_cast_reg_5961;
sc_signal< sc_logic > ap_CS_fsm_state46;
sc_signal< sc_lv<30> > val_assign_7_cast1_fu_4350_p2;
sc_signal< sc_lv<30> > val_assign_7_cast1_reg_5966;
sc_signal< sc_lv<14> > val_assign_7_cast2_fu_4356_p2;
sc_signal< sc_lv<14> > val_assign_7_cast2_reg_5971;
sc_signal< sc_lv<32> > i_assign_5_fu_4368_p1;
sc_signal< sc_lv<32> > i_assign_5_reg_5976;
sc_signal< sc_lv<2> > tmp_135_fu_4377_p4;
sc_signal< sc_lv<2> > tmp_135_reg_5984;
sc_signal< sc_lv<32> > p_Result_20_fu_4414_p4;
sc_signal< sc_lv<32> > i_assign_6_fu_4427_p1;
sc_signal< sc_lv<32> > i_assign_6_reg_5996;
sc_signal< sc_lv<1> > p_Repl2_22_fu_4461_p2;
sc_signal< sc_lv<1> > p_Repl2_22_reg_6004;
sc_signal< sc_lv<9> > rhs_V_13_cast_fu_4467_p1;
sc_signal< sc_lv<9> > rhs_V_13_cast_reg_6009;
sc_signal< sc_logic > ap_CS_fsm_state47;
sc_signal< sc_lv<2> > tmp_136_fu_4475_p4;
sc_signal< sc_lv<2> > tmp_136_reg_6015;
sc_signal< sc_lv<32> > p_Result_22_fu_4513_p4;
sc_signal< sc_lv<32> > p_Result_22_reg_6019;
sc_signal< sc_lv<3> > tmp_137_fu_4561_p4;
sc_signal< sc_lv<3> > tmp_137_reg_6029;
sc_signal< sc_logic > ap_CS_fsm_state48;
sc_signal< sc_lv<32> > p_Result_24_fu_4599_p4;
sc_signal< sc_lv<32> > p_Result_24_reg_6033;
sc_signal< sc_lv<32> > p_Result_26_fu_4680_p4;
sc_signal< sc_logic > ap_CS_fsm_state49;
sc_signal< sc_lv<1> > p_Repl2_28_fu_4719_p2;
sc_signal< sc_lv<1> > p_Repl2_28_reg_6051;
sc_signal< sc_lv<16> > addr_HTA_V_3_reg_6056;
sc_signal< sc_lv<5> > loc2_V_fu_4782_p1;
sc_signal< sc_lv<5> > loc2_V_reg_6065;
sc_signal< sc_lv<1> > tmp_46_reg_6070;
sc_signal< bool > ap_block_state52_io;
sc_signal< sc_lv<11> > r_V_s_reg_6074;
sc_signal< sc_lv<5> > arrayNo_reg_6091;
sc_signal< sc_lv<6> > heap_tree_V_0_addr_reg_6096;
sc_signal< sc_lv<6> > heap_tree_V_1_addr_reg_6101;
sc_signal< sc_lv<6> > heap_tree_V_2_addr_reg_6106;
sc_signal< sc_lv<6> > heap_tree_V_3_addr_reg_6111;
sc_signal< sc_lv<6> > heap_tree_V_4_addr_reg_6116;
sc_signal< sc_lv<32> > tmp_32_fu_4878_p2;
sc_signal< sc_lv<32> > tmp_32_reg_6126;
sc_signal< sc_lv<32> > tmp_33_fu_4903_p2;
sc_signal< sc_lv<32> > tmp_33_reg_6135;
sc_signal< sc_logic > ap_CS_fsm_state54;
sc_signal< sc_lv<32> > i_assign_fu_4912_p1;
sc_signal< sc_lv<32> > i_assign_reg_6144;
sc_signal< sc_logic > ap_CS_fsm_state55;
sc_signal< sc_lv<5> > tmp_108_fu_4941_p4;
sc_signal< sc_lv<5> > tmp_108_reg_6152;
sc_signal< sc_lv<32> > tmp_35_fu_4999_p2;
sc_signal< sc_lv<32> > tmp_35_reg_6156;
sc_signal< sc_lv<5> > tmp_128_fu_5029_p4;
sc_signal< sc_lv<5> > tmp_128_reg_6167;
sc_signal< sc_logic > ap_CS_fsm_state57;
sc_signal< sc_lv<32> > tmp_37_fu_5067_p2;
sc_si
|
gnal< sc_lv<32> > tmp_37_reg_6171;
sc_signal< sc_lv<1> > cond1_fu_5095_p2;
sc_signal< sc_lv<1> > cond1_reg_6180;
sc_signal< sc_logic > ap_CS_fsm_state58;
sc_signal< sc_lv<32> > tmp_39_fu_5128_p2;
sc_signal< sc_lv<32> > tmp_39_reg_6185;
sc_signal< sc_logic > ap_CS_fsm_state59;
sc_signal< sc_lv<64> > p_Result_12_fu_5165_p4;
sc_signal< sc_logic > ap_CS_fsm_state61;
sc_signal< sc_lv<64> > tmp_27_fu_5241_p2;
sc_signal< sc_logic > ap_CS_fsm_state63;
sc_signal< sc_lv<4> > p_061_0_i1_reg_854;
sc_signal< sc_lv<1> > tmp_1_fu_2429_p2;
sc_signal< sc_lv<16> > AA_V_fu_2415_p1;
sc_signal< sc_lv<5> > ap_phi_mux_p_0102_0_i1_phi_fu_929_p34;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<5> > layer_V_fu_2451_p2;
sc_signal< sc_lv<5> > layer0_V_reg_982;
sc_signal< sc_lv<4> > p_3_reg_994;
sc_signal< sc_lv<64> > p_02894_0_in_reg_1003;
sc_signal< sc_lv<16> > p_02759_0_in_in_reg_1012;
sc_signal< sc_lv<64> > p_Val2_66_reg_1021;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_4_phi_fu_1034_p10;
sc_signal< sc_lv<32> > heap_tree_V_3_load_4_reg_1031;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_2_load_4_phi_fu_1050_p10;
sc_signal< sc_lv<32> > heap_tree_V_2_load_4_reg_1047;
sc_signal< sc_lv<32> > heap_tree_V_1_load_2_reg_1063;
sc_signal< sc_lv<32> > heap_tree_V_4_load_4_reg_1078;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_7_phi_fu_1097_p8;
sc_signal< sc_lv<32> > heap_tree_V_3_load_7_reg_1094;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_lv<32> > heap_tree_V_2_load_5_reg_1111;
sc_signal< sc_lv<32> > heap_tree_V_4_load_7_reg_1127;
sc_signal< sc_lv<32> > heap_tree_V_4_load_s_reg_1144;
sc_signal< sc_lv<32> > heap_tree_V_3_load_8_reg_1158;
sc_signal< sc_lv<32> > p_Val2_51_reg_1171;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_1_phi_fu_1184_p10;
sc_signal< sc_lv<32> > heap_tree_V_3_load_1_reg_1181;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_2_load_1_phi_fu_1200_p10;
sc_signal< sc_lv<32> > heap_tree_V_2_load_1_reg_1197;
sc_signal< sc_lv<32> > heap_tree_V_1_load_1_reg_1213;
sc_signal< sc_lv<32> > heap_tree_V_4_load_1_reg_1228;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_3_phi_fu_1247_p8;
sc_signal< sc_lv<32> > heap_tree_V_3_load_3_reg_1244;
sc_signal< sc_logic > ap_CS_fsm_state25;
sc_signal< sc_lv<32> > heap_tree_V_2_load_3_reg_1261;
sc_signal< sc_lv<32> > heap_tree_V_4_load_3_reg_1277;
sc_signal< sc_lv<32> > heap_tree_V_4_load_6_reg_1294;
sc_signal< sc_lv<32> > heap_tree_V_3_load_6_reg_1308;
sc_signal< sc_lv<32> > heap_tree_V_4_load_9_reg_1321;
sc_signal< sc_logic > ap_CS_fsm_state29;
sc_signal< sc_lv<64> > storemerge_reg_1331;
sc_signal< sc_lv<4> > ap_phi_mux_p_0167_0_i1_phi_fu_1343_p34;
sc_signal< sc_lv<4> > p_0167_0_i1_reg_1340;
sc_signal< sc_lv<1> > tmp_10_fu_3770_p2;
sc_signal< sc_lv<16> > AA_V_1_fu_3736_p1;
sc_signal< sc_lv<5> > ap_phi_mux_p_0252_0_i1_phi_fu_1400_p34;
sc_signal< sc_lv<5> > p_0252_0_i1_reg_1397;
sc_signal< sc_lv<1> > tmp_63_fu_3780_p2;
sc_signal< sc_lv<16> > BB_V_1_fu_3740_p4;
sc_signal< sc_lv<6> > ap_phi_mux_p_0248_0_i1_phi_fu_1457_p34;
sc_signal< sc_lv<6> > p_0248_0_i1_reg_1454;
sc_signal< sc_lv<1> > tmp_71_fu_3790_p2;
sc_signal< sc_lv<16> > CC_V_fu_3750_p4;
sc_signal< sc_lv<5> > p_0244_0_i1_reg_1511;
sc_signal< sc_lv<1> > tmp_72_fu_3800_p2;
sc_signal< sc_lv<16> > DD_V_fu_3760_p4;
sc_signal< sc_lv<4> > ap_phi_mux_p_061_0_i_phi_fu_1587_p34;
sc_signal< sc_lv<1> > tmp_82_fu_3952_p2;
sc_signal< sc_lv<16> > AA_V_2_fu_3938_p1;
sc_signal< sc_lv<5> > p_0102_0_i_reg_1640;
sc_signal< sc_lv<1> > tmp_83_fu_3962_p2;
sc_signal< sc_lv<16> > BB_V_2_fu_3942_p4;
sc_signal< sc_lv<4> > ap_phi_mux_p_0167_0_i_phi_fu_1716_p34;
sc_signal< sc_lv<1> > tmp_91_fu_4083_p2;
sc_signal< sc_lv<5> > ap_phi_mux_p_0252_0_i_phi_fu_1772_p34;
sc_signal< sc_lv<1> > tmp_92_fu_4092_p2;
sc_signal< sc_lv<6> > ap_phi_mux_p_0248_0_i_phi_fu_1828_p34;
sc_signal< sc_lv<1> > tmp_93_fu_4101_p2;
sc_signal< sc_lv<5> > p_0244_0_i_reg_1881;
sc_signal< sc_lv<1> > tmp_94_fu_4110_p2;
sc_signal< sc_lv<32> > tmp_123_reg_1946;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_2_load_7_phi_fu_1961_p6;
sc_signal< sc_lv<32> > heap_tree_V_2_load_7_reg_1958;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_1_load_4_phi_fu_1973_p6;
sc_signal< sc_lv<32> > heap_tree_V_1_load_4_reg_1970;
sc_signal< sc_lv<32> > tmp_124_reg_1982;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_s_phi_fu_1999_p6;
sc_signal< sc_lv<32> > heap_tree_V_3_load_s_reg_1996;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_2_load_8_phi_fu_2011_p6;
sc_signal< sc_lv<32> > heap_tree_V_2_load_8_reg_2008;
sc_signal< sc_lv<32> > tmp_125_reg_2022;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_4_load_10_phi_fu_2039_p6;
sc_signal< sc_lv<32> > heap_tree_V_4_load_10_reg_2036;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_10_phi_fu_2051_p6;
sc_signal< sc_lv<32> > heap_tree_V_3_load_10_reg_2048;
sc_signal< sc_lv<32> > tmp_126_reg_2062;
sc_signal< sc_lv<1> > cond3_fu_4666_p2;
sc_signal< sc_lv<32> > tmp_127_reg_2072;
sc_signal< sc_lv<64> > p_Result_29_fu_4767_p4;
sc_signal< sc_lv<64> > ap_phi_mux_storemerge1_phi_fu_2085_p6;
sc_signal< sc_lv<64> > storemerge1_reg_2082;
sc_signal< sc_logic > ap_CS_fsm_state50;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_phi_fu_2096_p10;
sc_signal< sc_lv<32> > heap_tree_V_3_load_reg_2093;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_2_load_phi_fu_2112_p10;
sc_signal< sc_lv<32> > heap_tree_V_2_load_reg_2109;
sc_signal< sc_lv<32> > heap_tree_V_1_load_reg_2125;
sc_signal< sc_lv<32> > heap_tree_V_4_load_reg_2140;
sc_signal< sc_lv<32> > ap_phi_mux_heap_tree_V_3_load_2_phi_fu_2159_p8;
sc_signal< sc_lv<32> > heap_tree_V_3_load_2_reg_2156;
sc_signal< sc_logic > ap_CS_fsm_state56;
sc_signal< sc_lv<32> > heap_tree_V_2_load_2_reg_2173;
sc_signal< sc_lv<32> > heap_tree_V_4_load_2_reg_2189;
sc_signal< sc_lv<32> > heap_tree_V_4_load_5_reg_2206;
sc_signal< sc_lv<32> > heap_tree_V_3_load_5_reg_2220;
sc_signal< sc_lv<32> > heap_tree_V_4_load_8_reg_2233;
sc_signal< sc_logic > ap_CS_fsm_state60;
sc_signal< sc_lv<64> > tmp_31_fu_2468_p1;
sc_signal< sc_lv<64> > tmp_51_fu_2688_p1;
sc_signal< sc_lv<64> > tmp_52_fu_2703_p1;
sc_signal< sc_lv<64> > newIndex3_fu_2888_p1;
sc_signal< sc_lv<64> > tmp_45_fu_3309_p1;
sc_signal< sc_lv<64> > newIndex_fu_3332_p1;
sc_signal< sc_lv<64> > tmp_34_fu_3347_p1;
sc_signal< sc_lv<64> > newIndex9_fu_3863_p1;
sc_signal< sc_lv<64> > tmp_87_fu_4009_p1;
sc_signal< sc_lv<64> > tmp_107_fu_4265_p1;
sc_signal< sc_lv<64> > tmp_28_fu_4822_p1;
sc_signal< sc_lv<64> > newIndex5_fu_4845_p1;
sc_signal< sc_lv<64> > tmp_21_fu_4860_p1;
sc_signal< sc_lv<64> > p_Result_3_fu_2951_p4;
sc_signal< sc_lv<64> > p_Result_2_fu_3401_p4;
sc_signal< sc_lv<64> > tmp_38_fu_3668_p2;
sc_signal< sc_lv<64> > p_Result_21_fu_4436_p4;
sc_signal< sc_lv<64> > p_Result_1_fu_4920_p4;
sc_signal< sc_lv<64> > tmp_23_fu_5193_p2;
sc_signal< sc_lv<64> > p_Result_7_fu_3064_p4;
sc_signal< sc_lv<64> > p_Result_6_fu_3490_p4;
sc_signal< sc_lv<64> > tmp_40_fu_3680_p2;
sc_signal< sc_lv<64> > p_Result_23_fu_4527_p4;
sc_signal< sc_lv<64> > p_Result_5_fu_5009_p4;
sc_signal< sc_lv<64> > tmp_24_fu_5205_p2;
sc_signal< sc_lv<64> > p_Result_15_fu_3181_p4;
sc_signal< sc_lv<64> > p_Result_10_fu_3587_p4;
sc_signal< sc_lv<64> > tmp_42_fu_3692_p2;
sc_signal< sc_lv<64> > p_Result_25_fu_4614_p4;
sc_signal< sc_lv<64> > p_Result_9_fu_5106_p4;
sc_signal< sc_lv<64> > tmp_25_fu_5217_p2;
sc_signal< sc_lv<64> > p_Result_17_fu_3254_p4;
sc_signal< bool > ap_predicate_op368_write_state18;
sc_signal< sc_logic > ap_sig_ioackin_com_port_target_V_ap_ack;
sc_signal< bool > ap_block_state18_io;
sc_signal< sc_lv<64> > p_Result_13_fu_3619_p4;
sc_signal< sc_lv<64> > tmp_43_fu_3704_p2;
sc_signal< sc_lv<64> > p_Result_27_fu_4696_p4;
sc_signal< sc_lv<64> > p_Result_11_fu_5138_p4;
sc_signal< sc_lv<64> > tmp_26_fu_5229_p2;
sc_signal< sc_lv<64> > p_Result_19_fu_3284_p4;
sc_signal< sc_logic > ap_CS_fsm_state33;
sc_signal< sc_lv<32> > tmp_105_fu_4260_p1;
sc_signal< sc_lv<32> > tmp_12_fu_4798_p1;
sc_signal< sc_logic > ap_reg_ioackin_alloc_addr_ap_ack;
sc_signal< bool > ap_block_state42_io;
sc_signal< sc_logic > ap_reg_ioackin_com_port_cmd_ap_ack;
sc_signal< sc_lv<8> > p_2_fu_2474_p1;
sc_signal< sc_lv<8> > p_1_fu_2571_p1;
sc_signal< sc_logic > ap_reg_ioackin_com_port_layer_V_ap_ack;
sc_signal< sc_logic > ap_reg_ioackin_com_port_target_V_ap_ack;
sc_signal< sc_lv<64> > val_assign_2_fu_2863_p2;
sc_signal< sc_lv<64> > r_V_32_fu_4335_p3;
sc_signal< sc_lv<32> > p_Result_18_fu_3269_p4;
sc_signal< sc_lv<32> > tmp_61_fu_3634_p2;
sc_signal< sc_lv<32> > p_Result_28_fu_4752_p4;
sc_signal< sc_lv<32> > tmp_41_fu_5153_p2;
sc_signal< sc_lv<32> > tmp_size_V_fu_2384_p2;
sc_signal< sc_lv<32> > p_s_fu_2405_p2;
sc_signal< sc_lv<32> > p_Val2_1_fu_2410_p2;
sc_signal< sc_lv<5> > p_061_0_i1_cast_fu_2441_p1;
sc_signal< sc_lv<5> > tmp_6_fu_2445_p2;
sc_signal< sc_lv<3> > tmp_56_fu_2505_p1;
sc_signal< sc_lv<1> > sel_tmp_i_fu_2509_p2;
sc_signal< sc_lv<1> > sel_tmp2_i_fu_2523_p2;
sc_signal< sc_lv<64> > sel_tmp1_i_fu_2515_p3;
sc_signal< sc_lv<1> > sel_tmp4_i_fu_2537_p2;
sc_signal< sc_lv<64> > sel_tmp3_i_fu_2529_p3;
sc_signal< sc_lv<1> > sel_tmp6_i_fu_2551_p2;
sc_signal< sc_lv<64> > sel_tmp5_i_fu_2543_p3;
sc_signal< sc_lv<6> > rhs_V_14_cast_fu_2576_p1;
sc_signal< sc_lv<6> > r_V_40_fu_2580_p2;
sc_signal< sc_lv<6> > tmp_20_fu_2601_p2;
sc_signal< sc_lv<32> > tmp_19_fu_2598_p1;
sc_signal< sc_lv<32> > tmp_52_cast_fu_2607_p1;
sc_signal< sc_lv<32> > tmp_29_fu_2611_p2;
sc_signal< sc_lv<20> > tmp_50_cast_fu_2594_p1;
sc_signal< sc_lv<1> > tmp_112_fu_2586_p3;
sc_signal< sc_lv<20> > tmp_113_fu_2617_p1;
sc_signal< sc_lv<20> > tmp_30_fu_2621_p2;
sc_signal< sc_lv<5> > tmp_114_fu_2640_p1;
sc_signal< sc_lv<5> > tmp_47_fu_2643_p2;
sc_signal< sc_lv<6> > shift_constant_V_loa_2_fu_2652_p1;
sc_signal< sc_lv<6> > tmp_67_cast_fu_2648_p1;
sc_signal< sc_lv<20> > tmp_76_cast_fu_2662_p1;
sc_signal< sc_lv<16> > tree_offset_V_2_fu_2670_p1;
sc_signal< sc_lv<7> > rhs_V_cast_fu_2693_p1;
sc_signal< sc_lv<7> > r_V_13_fu_2697_p2;
sc_signal< sc_lv<62> > tmp_134_fu_2712_p1;
sc_signal< sc_lv<62> > tmp_53_fu_2722_p2;
sc_signal< sc_lv<64> > lhs_V_1_fu_2716_p2;
sc_signal< sc_lv<16> > loc_in_group_tree_V_s_fu_2747_p1;
sc_signal< sc_lv<64> > tmp_60_fu_2766_p1;
sc_signal< sc_lv<2> > rec_bits_V_fu_2781_p1;
sc_signal< sc_lv<1> > tmp_67_fu_2785_p2;
sc_signal< sc_lv<1> > not_s_fu_2791_p2;
sc_signal< sc_lv<15> > p_02759_0_in_fu_2803_p4;
sc_signal< sc_lv<16> > tmp_88_fu_2813_p1;
sc_signal< sc_lv<16> > loc_in_group_tree_V_fu_2817_p2;
sc_signal< sc_lv<32> > i_assign_2_fu_2823_p1;
sc_signal< sc_lv<64> > tmp_70_fu_2847_p1;
sc_signal< sc_lv<6> > newIndex_trunc4_fu_2879_p4;
sc_signal< sc_lv<16> > p_Val2_s_fu_2913_p6;
sc_signal< sc_lv<32> > p_Val2_s_fu_2913_p7;
sc_signal< sc_lv<1> > p_Repl2_s_fu_2904_p2;
sc_signal< sc_lv<1> > p_Repl2_3_fu_2946_p2;
sc_signal< sc_lv<4> > tmp_157_fu_2976_p4;
sc_signal< sc_lv<12> > r_V_20_fu_2970_p2;
sc_signal< sc_lv<1> > sel_tmp6_fu_3014_p2;
sc_signal< sc_lv<1> > sel_tmp5_fu_3008_p2;
sc_signal< sc_lv<1> > sel_tmp3_fu_3002_p2;
sc_signal< sc_lv<1> > or_cond2_fu_3028_p2;
sc_signal< sc_lv<32> > newSel6_fu_3020_p3;
sc_signal< sc_lv<32> > newSel7_fu_3034_p3;
sc_signal< sc_lv<32> > p_Val2_34_fu_3042_p3;
sc_signal< sc_lv<1> > p_Repl2_4_fu_2986_p2;
sc_signal< sc_lv<1> > p_Repl2_7_fu_3059_p2;
sc_signal< sc_lv<8> > tmp_162_fu_3084_p4;
sc_signal< sc_lv<12> > r_V_22_fu_3079_p2;
sc_signal< sc_lv<1> > sel_tmp15_fu_3110_p2;
sc_signal< sc_lv<1> > sel_tmp17_fu_3124_p2;
sc_signal< sc_lv<32> > sel_tmp16_fu_3116_p3;
sc_signal< sc_lv<32> > p_Val2_41_fu_3130_p3;
sc_signal< sc_lv<1> > p_Repl2_8_fu_3094_p2;
sc_signal< sc_lv<12> > r_V_24_fu_3147_p2;
sc_signal< sc_lv<6> > tmp_133_fu_3152_p4;
sc_signal< sc_lv<12> > arrayNo12_mask_fu_3162_p3;
sc_signal< sc_lv<1> > p_Repl2_15_fu_3176_p2;
sc_signal< sc_lv<16> > tmp_171_fu_3196_p4;
sc_signal< sc_lv<32> > p_Val2_49_fu_3212_p3;
sc_signal< sc_lv<1> > p_Repl2_16_fu_3206_p2;
sc_signal< sc_lv<32> > tmp_174_fu_3228_p4;
sc_signal< sc_lv<1> > p_Repl2_17_fu_3249_p2;
sc_signal< sc_lv<1> > p_Repl2_19_fu_3278_p2;
sc_signal< sc_lv<4> > tmp_110_fu_3299_p1;
sc_signal< sc_lv<4> > r_V_12_fu_3303_p2;
sc_signal< sc_lv<6> > newIndex_trunc1_fu_3323_p4;
sc_signal< sc_lv<4> > r_V_10_fu_3341_p2;
sc_signal< sc_lv<32> > tmp_148_fu_3352_p1;
sc_signal< sc_lv<32> > tmp_46_cast_fu_3356_p1;
sc_signal< sc_lv<20> > tmp_66_fu_3368_p6;
sc_signal< sc_lv<32> > tmp_66_fu_3368_p7;
sc_signal< sc_lv<1> > p_Repl2_2_fu_3396_p2;
sc_signal< sc_lv<11> > r_V_16_fu_3417_p2;
sc_signal< sc_lv<1> > sel_tmp1_fu_3444_p2;
sc_signal< sc_lv<1> > sel_tmp9_fu_3438_p2;
sc_signal< sc_lv<1> > sel_tmp7_fu_3432_p2;
sc_signal< sc_lv<1> > or_cond1_fu_3458_p2;
sc_signal< sc_lv<32> > newSel3_fu_3450_p3;
sc_signal< sc_lv<32> > newSel4_fu_3464_p3;
sc_signal< sc_lv<32> > newSel5_fu_3472_p3;
sc_signal< sc_lv<1> > p_Repl2_6_fu_3485_p2;
sc_signal< sc_lv<11> > r_V_21_fu_3505_p2;
sc_signal< sc_lv<1> > sel_tmp12_fu_3520_p2;
sc_signal< sc_lv<1> > sel_tmp14_fu_3534_p2;
sc_signal< sc_lv<32> > sel_tmp13_fu_3526_p3;
sc_signal< sc_lv<32> > heap_tree_V_load_7_p_fu_3540_p3;
sc_signal< sc_lv<11> > r_V_23_fu_3553_p2;
sc_signal< sc_lv<5> > tmp_132_fu_3558_p4;
sc_signal< sc_lv<11> > arrayNo10_mask_fu_3568_p3;
sc_signal< sc_lv<1> > p_Repl2_10_fu_3582_p2;
sc_signal< sc_lv<32> > heap_tree_V_load_8_p_fu_3602_p3;
sc_signal< sc_lv<1> > p_Repl2_13_fu_3614_p2;
sc_signal< sc_lv<1> > p_Repl2_14_fu_3640_p2;
sc_signal< sc_lv<64> > maintain_mask_V_load_6_fu_3655_p1;
sc_signal< sc_lv<64> > tmp_36_fu_3659_p1;
sc_signal< sc_lv<64> > r_V_38_fu_3662_p2;
sc_signal< sc_lv<6> > p_0244_0_i1_cast_fu_3806_p1;
sc_signal< sc_lv<7> > tmp76_fu_3822_p2;
sc_signal< sc_lv<7> > p_0244_0_i1_cast1_fu_3810_p1;
sc_signal< sc_lv<7> > tmp77_fu_3830_p2;
sc_signal< sc_lv<8> > tmp93_cast_fu_3835_p1;
sc_signal< sc_lv<8> > tmp92_cast_fu_3826_p1;
sc_signal< sc_lv<6> > tmp_74_fu_3814_p1;
sc_signal< sc_lv<6> > tmp_75_fu_3818_p1;
sc_signal< sc_lv<6> > tmp79_fu_3851_p2;
sc_signal< sc_lv<6> > tmp78_fu_3845_p2;
sc_signal< sc_lv<6> > tmp_78_fu_3857_p2;
sc_signal< sc_lv<11> > tmp_77_fu_3872_p3;
sc_signal< sc_lv<12> > tmp_95_cast_fu_3880_p1;
sc_signal< sc_lv<12> > tmp_96_cast1_fu_3884_p1;
sc_signal< sc_lv<12> > layer_offset_V_fu_3887_p2;
sc_signal< sc_lv<6> > arrayNo9_fu_3893_p4;
sc_signal< sc_lv<16> > tmp_80_fu_3907_p6;
sc_signal< sc_lv<32> > tmp1_V_fu_3933_p2;
sc_signal< sc_lv<6> > p_0102_0_i_cast_fu_3968_p1;
sc_signal< sc_lv<1> > tmp_85_fu_3977_p2;
sc_signal< sc_lv<1> > tmp_86_fu_3982_p2;
sc_signal< sc_lv<13> > tmp_110_cast_fu_3999_p1;
sc_signal< sc_lv<13> > r_V_25_fu_3992_p3;
sc_signal< sc_lv<62> > rhs_V_8_cast_fu_4024_p1;
sc_signal< sc_lv<62> > i_op_assign_cast_fu_4018_p2;
sc_signal< sc_lv<62> > r_V_36_fu_4028_p2;
sc_signal< sc_lv<62> > tmp_89_fu_4034_p2;
sc_signal< sc_lv<62> > group_tree_tmp_maske_fu_4040_p2;
sc_signal< sc_lv<7> > p_0252_0_i_cast_fu_4097_p1;
sc_signal< sc_lv<7> > p_0248_0_i_cast_fu_4106_p1;
sc_signal< sc_lv<6> > p_0244_0_i_cast1_fu_4121_p1;
sc_signal< sc_lv<7> > p_0244_0_i_cast_fu_4125_p1;
sc_signal< sc_lv<7> > tmp92_fu_4132_p2;
sc_signal< sc_lv<8> > tmp98_cast_fu_4137_p1;
sc_signal< sc_lv<8> > tmp97_cast_fu_4129_p1;
sc_signal< sc_lv<6> > tmp_97_fu_4154_p2;
sc_signal< sc_lv<32> > tmp_96_fu_4151_p1;
sc_signal< sc_lv<32> > tmp_125_cast_fu_4160_p1;
sc_signal< sc_lv<32> > tmp_98_fu_4164_p2;
sc_signal< sc_lv<16> > r_V_27_fu_4170_p1;
sc_signal< sc_lv<17> > lhs_V_2_fu_4174_p1;
sc_signal< sc_lv<17> > rhs_V_2_fu_4178_p1;
sc_signal< sc_lv<18> > lhs_V_3_fu_4188_p1;
sc_signal< sc_lv<18> > rhs_V_3_fu_4191_p1;
sc_signal< sc_lv<18> > r_V_29_fu_4195_p2;
sc_signal< sc_lv<6> > r_V_37_fu_4205_p2;
sc_signal< sc_lv<20> > loc_in_layer_V_fu_4201_p1;
sc_signal< sc_lv<6> > tmp_101_fu_4226_p2;
sc_signal< sc_lv<20> > tmp_129_cast_fu_4232_p1;
sc_signal< sc_lv<32> > tmp_100_fu_4222_p1;
sc_signal< sc_lv<32> > tmp_99_fu_4218_p1;
sc_signal< sc_lv<32> > tmp_103_fu_4242_p2;
sc_signal< sc_lv<1> > tmp_181_fu_4210_p3;
sc_signal< sc_lv<20> > tmp_102_fu_4236_p2;
sc_signal< sc_lv<20> > tmp_182_fu_4248_p1;
sc_signal< sc_lv<20> > r_V_31_fu_4252_p3;
sc_signal< sc_lv<30> > tmp_190_fu_4294_p1;
sc_signal< sc_lv<30> > tmp_189_fu_4290_p1;
sc_signal< sc_lv<14> > tmp_188_fu_4287_p1;
sc_signal< sc_lv<14> > tmp_187_fu_4283_p1;
sc_signal< sc_lv<6> > tmp_186_fu_4280_p1;
sc_signal< sc_lv<6> > tmp_185_fu_4276_p1;
sc_signal< sc_lv<2> > tmp_184_fu_4273_p1;
sc_signal< sc_lv<2> > tmp_183_fu_4269_p1;
sc_signal< sc_lv<2> > tmp_118_fu_4302_p4;
sc_signal< sc_lv<62> > tmp_117_fu_4297_p2;
sc_signal< sc_lv<30> > tmp_119_fu_4311_p2;
sc_signal< sc_lv<14> > tmp_120_fu_4317_p2;
sc_signal< sc_lv<6> > tmp_121_fu_4323_p2;
sc_signal< sc_lv<2> > tmp_122_fu_4329_p2;
sc_signal< sc_lv<1> > sel_tmp18_fu_4386_p2;
sc_signal< sc_lv<1> > sel_tmp20_fu_4400_p2;
sc_signal< sc_lv<32> > sel_tmp19_fu_4392_p3;
sc_signal< sc_lv<32> > p_Val2_56_fu_4406_p3;
sc_signal< sc_lv<1> > p_Repl2_20_fu_4371_p2;
sc_signal< sc_lv<1> > p_Repl2_21_fu_4430_p2;
sc_signal< sc_lv<6> > val_assign_7_cast3_fu_4362_p2;
sc_signal< sc_lv<4> > tmp_193_fu_4451_p4;
sc_signal< sc_lv<8> > r_V_33_fu_4470_p2;
sc_signal< sc_lv<1> > sel_tmp21_fu_4485_p2;
sc_signal< sc_lv<1> > sel_tmp23_fu_4499_p2;
sc_signal< sc_lv<32> > sel_tmp22_fu_4491_p3;
sc_signal< sc_lv<32> > p_Val2_58_fu_4505_p3;
sc_signal< sc_lv<1> > p_Repl2_23_fu_4522_p2;
sc_signal< sc_lv<8> > tmp_196_fu_4546_p4;
sc_signal< sc_lv<9> > r_V_34_fu_4541_p2;
sc_signal< sc_lv<1> > sel_tmp24_fu_4571_p2;
sc_signal< sc_lv<1> > sel_tmp26_fu_4585_p2;
sc_signal< sc_lv<32> > sel_tmp25_fu_4577_p3;
sc_signal< sc_lv<32> > p_Val2_60_fu_4591_p3;
sc_signal< sc_lv<1> > p_Repl2_24_fu_4555_p2;
sc_signal< sc_lv<1> > p_Repl2_25_fu_4609_p2;
sc_signal< sc_lv<16> > tmp_199_fu_4633_p4;
sc_signal< sc_lv<9> > r_V_35_fu_4628_p2;
sc_signal< sc_lv<3> > tmp_138_fu_4648_p4;
sc_signal< sc_lv<9> > arrayNo16_mask_fu_4658_p3;
sc_signal< sc_lv<32> > p_Val2_62_fu_4672_p3;
sc_signal< sc_lv<1> > p_Repl2_26_fu_4642_p2;
sc_signal< sc_lv<1> > p_Repl2_27_fu_4690_p2;
sc_signal< sc_lv<32> > tmp_202_fu_4710_p4;
sc_signal< sc_lv<3> > arrayNo2_fu_4725_p3;
sc_signal< sc_lv<33> > p_Val2_64_fu_4736_p6;
sc_signal< sc_lv<32> > p_Val2_64_fu_4736_p7;
sc_signal< sc_lv<1> > p_Repl2_29_fu_4761_p2;
sc_signal< sc_lv<16> > r_V_fu_4793_p2;
sc_signal< sc_lv<4> > tmp_109_fu_4812_p1;
sc_signal< sc_lv<4> > r_V_5_fu_4816_p2;
sc_signal< sc_lv<6> > newIndex_trunc_fu_4836_p4;
sc_signal< sc_lv<4> > r_V_3_fu_4854_p2;
sc_signal< sc_lv<32> > tmp_147_fu_4865_p1;
sc_signal< sc_lv<32> > tmp_29_cast_fu_4869_p1;
sc_signal< sc_lv<32> > r_V_6_fu_4872_p2;
sc_signal< sc_lv<16> > tmp_64_f
|
u_4887_p6;
sc_signal< sc_lv<32> > tmp_64_fu_4887_p7;
sc_signal< sc_lv<1> > p_Repl2_1_fu_4915_p2;
sc_signal< sc_lv<11> > r_V_7_fu_4936_p2;
sc_signal< sc_lv<1> > sel_tmp4_fu_4963_p2;
sc_signal< sc_lv<1> > sel_tmp2_fu_4957_p2;
sc_signal< sc_lv<1> > sel_tmp_fu_4951_p2;
sc_signal< sc_lv<1> > or_cond_fu_4977_p2;
sc_signal< sc_lv<32> > newSel_fu_4969_p3;
sc_signal< sc_lv<32> > newSel1_fu_4983_p3;
sc_signal< sc_lv<32> > newSel2_fu_4991_p3;
sc_signal< sc_lv<1> > p_Repl2_5_fu_5004_p2;
sc_signal< sc_lv<11> > r_V_8_fu_5024_p2;
sc_signal< sc_lv<1> > sel_tmp8_fu_5039_p2;
sc_signal< sc_lv<1> > sel_tmp11_fu_5053_p2;
sc_signal< sc_lv<32> > sel_tmp10_fu_5045_p3;
sc_signal< sc_lv<32> > heap_tree_V_load_2_p_fu_5059_p3;
sc_signal< sc_lv<11> > r_V_9_fu_5072_p2;
sc_signal< sc_lv<5> > tmp_131_fu_5077_p4;
sc_signal< sc_lv<11> > arrayNo8_mask_fu_5087_p3;
sc_signal< sc_lv<1> > p_Repl2_9_fu_5101_p2;
sc_signal< sc_lv<32> > heap_tree_V_load_3_p_fu_5121_p3;
sc_signal< sc_lv<1> > p_Repl2_11_fu_5133_p2;
sc_signal< sc_lv<1> > p_Repl2_12_fu_5159_p2;
sc_signal< sc_lv<64> > maintain_mask_V_load_4_fu_5174_p1;
sc_signal< sc_lv<64> > tmp_22_fu_5178_p1;
sc_signal< sc_lv<64> > r_V_4_fu_5181_p2;
sc_signal< sc_lv<64> > tmp0_V_1_fu_5187_p2;
sc_signal< sc_lv<63> > ap_NS_fsm;
sc_signal< bool > ap_condition_4455;
sc_signal< bool > ap_condition_1591;
sc_signal< bool > ap_condition_2089;
sc_signal< bool > ap_condition_1492;
sc_signal< bool > ap_condition_2007;
sc_signal< bool > ap_condition_1842;
sc_signal< bool > ap_condition_1675;
sc_signal< bool > ap_condition_2174;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<63> ap_ST_fsm_state1;
static const sc_lv<63> ap_ST_fsm_state2;
static const sc_lv<63> ap_ST_fsm_state3;
static const sc_lv<63> ap_ST_fsm_state4;
static const sc_lv<63> ap_ST_fsm_state5;
static const sc_lv<63> ap_ST_fsm_state6;
static const sc_lv<63> ap_ST_fsm_state7;
static const sc_lv<63> ap_ST_fsm_state8;
static const sc_lv<63> ap_ST_fsm_state9;
static const sc_lv<63> ap_ST_fsm_state10;
static const sc_lv<63> ap_ST_fsm_state11;
static const sc_lv<63> ap_ST_fsm_state12;
static const sc_lv<63> ap_ST_fsm_state13;
static const sc_lv<63> ap_ST_fsm_state14;
static const sc_lv<63> ap_ST_fsm_state15;
static const sc_lv<63> ap_ST_fsm_state16;
static const sc_lv<63> ap_ST_fsm_state17;
static const sc_lv<63> ap_ST_fsm_state18;
static const sc_lv<63> ap_ST_fsm_state19;
static const sc_lv<63> ap_ST_fsm_state20;
static const sc_lv<63> ap_ST_fsm_state21;
static const sc_lv<63> ap_ST_fsm_state22;
static const sc_lv<63> ap_ST_fsm_state23;
static const sc_lv<63> ap_ST_fsm_state24;
static const sc_lv<63> ap_ST_fsm_state25;
static const sc_lv<63> ap_ST_fsm_state26;
static const sc_lv<63> ap_ST_fsm_state27;
static const sc_lv<63> ap_ST_fsm_state28;
static const sc_lv<63> ap_ST_fsm_state29;
static const sc_lv<63> ap_ST_fsm_state30;
static const sc_lv<63> ap_ST_fsm_state31;
static const sc_lv<63> ap_ST_fsm_state32;
static const sc_lv<63> ap_ST_fsm_state33;
static const sc_lv<63> ap_ST_fsm_state34;
static const sc_lv<63> ap_ST_fsm_state35;
static const sc_lv<63> ap_ST_fsm_state36;
static const sc_lv<63> ap_ST_fsm_state37;
static const sc_lv<63> ap_ST_fsm_state38;
static const sc_lv<63> ap_ST_fsm_state39;
static const sc_lv<63> ap_ST_fsm_state40;
static const sc_lv<63> ap_ST_fsm_state41;
static const sc_lv<63> ap_ST_fsm_state42;
static const sc_lv<63> ap_ST_fsm_state43;
static const sc_lv<63> ap_ST_fsm_state44;
static const sc_lv<63> ap_ST_fsm_state45;
static const sc_lv<63> ap_ST_fsm_state46;
static const sc_lv<63> ap_ST_fsm_state47;
static const sc_lv<63> ap_ST_fsm_state48;
static const sc_lv<63> ap_ST_fsm_state49;
static const sc_lv<63> ap_ST_fsm_state50;
static const sc_lv<63> ap_ST_fsm_state51;
static const sc_lv<63> ap_ST_fsm_state52;
static const sc_lv<63> ap_ST_fsm_state53;
static const sc_lv<63> ap_ST_fsm_state54;
static const sc_lv<63> ap_ST_fsm_state55;
static const sc_lv<63> ap_ST_fsm_state56;
static const sc_lv<63> ap_ST_fsm_state57;
static const sc_lv<63> ap_ST_fsm_state58;
static const sc_lv<63> ap_ST_fsm_state59;
static const sc_lv<63> ap_ST_fsm_state60;
static const sc_lv<63> ap_ST_fsm_state61;
static const sc_lv<63> ap_ST_fsm_state62;
static const sc_lv<63> ap_ST_fsm_state63;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<64> ap_const_lv64_FFFFFFFFFFFFFFFF;
static const sc_lv<32> ap_const_lv32_33;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_25;
static const sc_lv<32> ap_const_lv32_29;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_2A;
static const sc_lv<32> ap_const_lv32_12;
static const sc_lv<32> ap_const_lv32_32;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_21;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_28;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<32> ap_const_lv32_23;
static const sc_lv<32> ap_const_lv32_34;
static const sc_lv<32> ap_const_lv32_1E;
static const sc_lv<32> ap_const_lv32_3D;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<32> ap_const_lv32_17;
static const sc_lv<32> ap_const_lv32_19;
static const sc_lv<32> ap_const_lv32_1A;
static const sc_lv<32> ap_const_lv32_1B;
static const sc_lv<32> ap_const_lv32_1D;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<32> ap_const_lv32_22;
static const sc_lv<32> ap_const_lv32_24;
static const sc_lv<32> ap_const_lv32_26;
static const sc_lv<32> ap_const_lv32_27;
static const sc_lv<32> ap_const_lv32_2C;
static const sc_lv<32> ap_const_lv32_2D;
static const sc_lv<32> ap_const_lv32_2E;
static const sc_lv<32> ap_const_lv32_2F;
static const sc_lv<32> ap_const_lv32_30;
static const sc_lv<32> ap_const_lv32_35;
static const sc_lv<32> ap_const_lv32_36;
static const sc_lv<32> ap_const_lv32_38;
static const sc_lv<32> ap_const_lv32_39;
static const sc_lv<32> ap_const_lv32_3A;
static const sc_lv<32> ap_const_lv32_3C;
static const sc_lv<32> ap_const_lv32_3E;
static const sc_lv<4> ap_const_lv4_F;
static const sc_lv<16> ap_const_lv16_8000;
static const sc_lv<4> ap_const_lv4_E;
static const sc_lv<16> ap_const_lv16_4000;
static const sc_lv<4> ap_const_lv4_D;
static const sc_lv<16> ap_const_lv16_2000;
static const sc_lv<4> ap_const_lv4_C;
static const sc_lv<16> ap_const_lv16_1000;
static const sc_lv<4> ap_const_lv4_B;
static const sc_lv<16> ap_const_lv16_800;
static const sc_lv<4> ap_const_lv4_A;
static const sc_lv<16> ap_const_lv16_400;
static const sc_lv<4> ap_const_lv4_9;
static const sc_lv<16> ap_const_lv16_200;
static const sc_lv<4> ap_const_lv4_8;
static const sc_lv<16> ap_const_lv16_100;
static const sc_lv<4> ap_const_lv4_7;
static const sc_lv<16> ap_const_lv16_80;
static const sc_lv<4> ap_const_lv4_6;
static const sc_lv<16> ap_const_lv16_40;
static const sc_lv<4> ap_const_lv4_5;
static const sc_lv<16> ap_const_lv16_20;
static const sc_lv<4> ap_const_lv4_4;
static const sc_lv<16> ap_const_lv16_10;
static const sc_lv<4> ap_const_lv4_3;
static const sc_lv<16> ap_const_lv16_8;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<16> ap_const_lv16_4;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<16> ap_const_lv16_2;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<5> ap_const_lv5_1F;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<5> ap_const_lv5_1E;
static const sc_lv<5> ap_const_lv5_1D;
static const sc_lv<5> ap_const_lv5_1C;
static const sc_lv<5> ap_const_lv5_1B;
static const sc_lv<5> ap_const_lv5_1A;
static const sc_lv<5> ap_const_lv5_19;
static const sc_lv<5> ap_const_lv5_18;
static const sc_lv<5> ap_const_lv5_17;
static const sc_lv<5> ap_const_lv5_16;
static const sc_lv<5> ap_const_lv5_15;
static const sc_lv<5> ap_const_lv5_14;
static const sc_lv<5> ap_const_lv5_13;
static const sc_lv<5> ap_const_lv5_12;
static const sc_lv<5> ap_const_lv5_11;
static const sc_lv<5> ap_const_lv5_10;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<5> ap_const_lv5_2;
static const sc_lv<5> ap_const_lv5_3;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<6> ap_const_lv6_1;
static const sc_lv<6> ap_const_lv6_2;
static const sc_lv<6> ap_const_lv6_3;
static const sc_lv<32> ap_const_lv32_18;
static const sc_lv<32> ap_const_lv32_1C;
static const sc_lv<6> ap_const_lv6_2F;
static const sc_lv<6> ap_const_lv6_2E;
static const sc_lv<6> ap_const_lv6_2D;
static const sc_lv<6> ap_const_lv6_2C;
static const sc_lv<6> ap_const_lv6_2B;
static const sc_lv<6> ap_const_lv6_2A;
static const sc_lv<6> ap_const_lv6_29;
static const sc_lv<6> ap_const_lv6_28;
static const sc_lv<6> ap_const_lv6_27;
static const sc_lv<6> ap_const_lv6_26;
static const sc_lv<6> ap_const_lv6_25;
static const sc_lv<6> ap_const_lv6_24;
static const sc_lv<6> ap_const_lv6_23;
static const sc_lv<6> ap_const_lv6_22;
static const sc_lv<6> ap_const_lv6_21;
static const sc_lv<6> ap_const_lv6_20;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<14> ap_const_lv14_2000;
static const sc_lv<14> ap_const_lv14_1000;
static const sc_lv<14> ap_const_lv14_800;
static const sc_lv<14> ap_const_lv14_400;
static const sc_lv<14> ap_const_lv14_200;
static const sc_lv<14> ap_const_lv14_100;
static const sc_lv<14> ap_const_lv14_80;
static const sc_lv<14> ap_const_lv14_40;
static const sc_lv<14> ap_const_lv14_20;
static const sc_lv<14> ap_const_lv14_10;
static const sc_lv<14> ap_const_lv14_8;
static const sc_lv<14> ap_const_lv14_4;
static const sc_lv<14> ap_const_lv14_2;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<3> ap_const_lv3_2;
static const sc_lv<3> ap_const_lv3_3;
static const sc_lv<32> ap_const_lv32_31;
static const sc_lv<32> ap_const_lv32_37;
static const sc_lv<32> ap_const_lv32_3B;
static const sc_lv<32> ap_const_lv32_20;
static const sc_lv<32> ap_const_lv32_FFFFFFFF;
static const sc_lv<8> ap_const_lv8_3;
static const sc_lv<8> ap_const_lv8_2;
static const sc_lv<8> ap_const_lv8_4;
static const sc_lv<8> ap_const_lv8_B;
static const sc_lv<5> ap_const_lv5_C;
static const sc_lv<32> ap_const_lv32_13;
static const sc_lv<5> ap_const_lv5_7;
static const sc_lv<16> ap_const_lv16_0;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<3> ap_const_lv3_5;
static const sc_lv<3> ap_const_lv3_6;
static const sc_lv<3> ap_const_lv3_7;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<6> ap_const_lv6_4;
static const sc_lv<7> ap_const_lv7_3E;
static const sc_lv<62> ap_const_lv62_3FFFFFFFFFFFFFFF;
static const sc_lv<32> ap_const_lv32_3F;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<16> ap_const_lv16_FFFF;
static const sc_lv<12> ap_const_lv12_40;
static const sc_lv<12> ap_const_lv12_80;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<12> ap_const_lv12_C0;
static const sc_lv<11> ap_const_lv11_40;
static const sc_lv<11> ap_const_lv11_80;
static const sc_lv<11> ap_const_lv11_C0;
static const sc_lv<62> ap_const_lv62_0;
static const sc_lv<14> ap_const_lv14_0;
static const sc_lv<62> ap_const_lv62_3FFFFFFFC0000000;
static const sc_lv<30> ap_const_lv30_3FFFC000;
static const sc_lv<14> ap_const_lv14_3FC0;
static const sc_lv<6> ap_const_lv6_3C;
static const sc_lv<8> ap_const_lv8_40;
static const sc_lv<9> ap_const_lv9_80;
static const sc_lv<9> ap_const_lv9_C0;
static const sc_lv<16> ap_const_lv16_5;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_AA_V_1_fu_3736_p1();
void thread_AA_V_2_fu_3938_p1();
void thread_AA_V_3_fu_4046_p1();
void thread_AA_V_fu_2415_p1();
void thread_BB_V_1_fu_3740_p4();
void thread_BB_V_2_fu_3942_p4();
void thread_BB_V_fu_2419_p4();
void thread_CC_V_fu_3750_p4();
void thread_DD_V_fu_3760_p4();
void thread_TMP_0_V_fu_2557_p3();
void thread_addr_HTA_V_1_fu_2744_p1();
void thread_addr_HTA_V_fu_2479_p1();
void thread_alloc_addr();
void thread_alloc_addr_ap_vld();
void thread_alloc_addr_blk_n();
void thread_alloc_cmd_ap_ack();
void thread_alloc_cmd_blk_n();
void thread_alloc_free_target_ap_ack();
void thread_alloc_free_target_blk_n();
void thread_alloc_size_ap_ack();
void thread_alloc_size_blk_n();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state12();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state16();
void thread_ap_CS_fsm_state17();
void thread_ap_CS_fsm_state18();
void thread_ap_CS_fsm_state19();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state21();
void thread_ap_CS_fsm_state22();
void thread_ap_CS_fsm_state23();
void thread_ap_CS_fsm_state24();
void thread_ap_CS_fsm_state25();
void thread_ap_CS_fsm_state26();
void thread_ap_CS_fsm_state27();
void thread_ap_CS_fsm_state28();
void thread_ap_CS_fsm_state29();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state30();
void thread_ap_CS_fsm_state31();
void thread_ap_CS_fsm_state32();
void thread_ap_CS_fsm_state33();
void thread_ap_CS_fsm_state34();
void thread_ap_CS_fsm_state35();
void thread_ap_CS_fsm_state36();
void thread_ap_CS_fsm_state37();
void thread_ap_CS_fsm_state38();
void thread_ap_CS_fsm_state39();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state40();
void thread_ap_CS_fsm_state41();
void thread_ap_CS_fsm_state42();
void thread_ap_CS_fsm_state43();
void thread_ap_CS_fsm_state45();
void thread_ap_CS_fsm_state46();
void thread_ap_CS_fsm_state47();
void thread_ap_CS_fsm_state48();
void thread_ap_CS_fsm_state49();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state50();
void thread_ap_CS_fsm_state51();
void thread_ap_CS_fsm_state52();
void thread_ap_CS_fsm_state53();
void thread_ap_CS_fsm_state54();
void thread_ap_CS_fsm_state55();
void thread_ap_CS_fsm_state56();
void thread_ap_CS_fsm_state57();
void thread_ap_CS_fsm_state58();
void thread_ap_CS_fsm_state59();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state60();
void thread_ap_CS_fsm_state61();
void thread_ap_CS_fsm_state62();
void thread_ap_CS_fsm_state63();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state9();
void thread_ap_block_state1();
void thread_ap_block_state18_io();
void thread_ap_block_state38_io();
void thread_ap_block_state42_io();
void thread_ap_block_state4_io();
void thread_ap_block_state52_io();
void thread_ap_condition_1492();
void thread_ap_condition_1591();
void thread_ap_condition_1675();
void thread_ap_condition_1842();
void thread_ap_condition_2007();
void thread_ap_condition_2089();
void thread_ap_condition_2174();
void thread_ap_condition_4455();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_phi_mux_heap_tree_V_1_load_4_phi_fu_1973_p6();
void thread_ap_phi_mux_heap_tree_V_2_load_1_phi_fu_1200_p10();
void thread_ap_phi_mux_heap_tree_V_2_load_4_phi_fu_1050_p10();
void thread_ap_phi_mux_heap_tree_V_2_load_7_phi_fu_1961_p6();
void thread_ap_phi_mux_heap_tree_V_2_load_8_phi_fu_2011_p6();
void thread_ap_phi_mux_heap_tree_V_2_load_phi_fu_2112_p10();
void thread_ap_phi_mux_heap_tree_V_3_load_10_phi_fu_2051_p6();
void thread_ap_phi_mux_heap_tree_V_3_load_1_phi_fu_1184_p10();
void thread_ap_phi_mux_heap_tree_V_3_load_2_phi_fu_2159_p8();
void thread_ap_phi_mux_heap_tree_V_3_load_3_phi_fu_1247_p8();
void thread_ap_phi_mux_heap_tree_V_3_load_4_phi_fu_1034_p10();
void thread_ap_phi_mux_heap_tree_V_3_load_7_phi_fu_1097_p8();
void thread_ap_phi_mux_heap_tree_V_3_load_phi_fu_2096_p10();
void thread_ap_phi_mux_heap_tree_V_3_load_s_phi_fu_1999_p6();
void thread_ap_phi_mux_heap_tree_V_4_load_10_phi_fu_2039_p6();
void thread_ap_phi_mux_p_0102_0_i1_phi_fu_929_p34();
void thread_ap_phi_mux_p_0167_0_i1_phi_fu_1343_p34();
void thread_ap_phi_mux_p_0167_0_i_phi_fu_1716_p34();
void thread_ap_phi_mux_p_0248_0_i1_phi_fu_1457_p34();
void thread_ap_phi_mux_p_0248_0_i_phi_fu_1828_p34();
void thread_ap_phi_mux_p_0252_0_i1_phi_fu_1400_p34();
void thread_ap_phi_mux_p_0252_0_i_phi_fu_1772_p34();
void thread_ap_phi_mux_p_061_0_i_phi_fu_1587_p34();
void thread_ap_phi_mux_storemerge1_phi_fu_2085_p6();
void thread_ap_predicate_op142_write_state4();
void thread_ap_predicate_op152_write_state4();
void thread_ap_predicate_op177_write_state4();
void thread_ap_predicate_op368_write_state18();
void thread_ap_ready();
void thread_ap_sig_ioackin_alloc_addr_ap_ack();
void thread_ap_sig_ioackin_com_port_cmd_ap_ack();
void thread_ap_sig_ioackin_com_port_layer_V_ap_ack();
void thread_ap_sig_ioackin_com_port_target_V_ap_ack();
void thread_arrayNo10_mask_fu_3568_p3();
void thread_arrayNo12_mask_fu_3162_p3();
void thread_arrayNo16_mask_fu_4658_p3();
void thread_arrayNo2_fu_4725_p3();
void thread_arrayNo8_mask_fu_5087_p3();
void thread_arrayNo9_fu_3893_p4();
void thread_com_port_allocated_addr_V_ap_ack();
void thread_com_port_allocated_addr_V_blk_n();
void thread_com_port_cmd();
void thread_com_port_cmd_ap_vld();
void thread_com_port_cmd_blk_n();
void thread_com_port_layer_V();
void thread_com_port_layer_V_ap_vld();
void thread_com_port_layer_V_blk_n();
void thread_com_port_target_V();
void thread_com_port_target_V_ap_vld();
void thread_com_port_target_V_blk_n();
void thread_cond1_fu_5095_p2();
void thread_cond2_fu_3576_p2();
void thread_cond3_fu_4666_p2();
void thread_cond_fu_3170_p2();
void thread_extra_mask_V_address0();
void thread_extra_mask_V_ce0();
void thread_free_target_V_fu_2380_p1();
void thread_group_tree_V_address0();
void thread_group_tree_V_ce0();
void thread_group_tree_V_d0();
void thread_group_tree_V_we0();
void thread_group_tree_mask_V_address0();
void thread_group_tree_mask_V_ce0();
v
|
oid thread_group_tree_tmp_maske_fu_4040_p2();
void thread_grp_fu_2243_p2();
void thread_grp_fu_2249_p2();
void thread_grp_fu_2255_p4();
void thread_grp_fu_2284_p2();
void thread_heap_tree_V_0_address0();
void thread_heap_tree_V_0_ce0();
void thread_heap_tree_V_0_d0();
void thread_heap_tree_V_0_we0();
void thread_heap_tree_V_1_address0();
void thread_heap_tree_V_1_ce0();
void thread_heap_tree_V_1_d0();
void thread_heap_tree_V_1_we0();
void thread_heap_tree_V_2_address0();
void thread_heap_tree_V_2_ce0();
void thread_heap_tree_V_2_d0();
void thread_heap_tree_V_2_we0();
void thread_heap_tree_V_3_address0();
void thread_heap_tree_V_3_ce0();
void thread_heap_tree_V_3_d0();
void thread_heap_tree_V_3_we0();
void thread_heap_tree_V_4_address0();
void thread_heap_tree_V_4_ce0();
void thread_heap_tree_V_4_d0();
void thread_heap_tree_V_4_we0();
void thread_heap_tree_V_load_2_p_fu_5059_p3();
void thread_heap_tree_V_load_3_p_fu_5121_p3();
void thread_heap_tree_V_load_7_p_fu_3540_p3();
void thread_heap_tree_V_load_8_p_fu_3602_p3();
void thread_i_assign_1_fu_3393_p1();
void thread_i_assign_2_fu_2823_p1();
void thread_i_assign_3_fu_2901_p1();
void thread_i_assign_4_fu_2943_p1();
void thread_i_assign_5_fu_4368_p1();
void thread_i_assign_6_fu_4427_p1();
void thread_i_assign_fu_4912_p1();
void thread_i_op_assign_cast_fu_4018_p2();
void thread_layer_V_fu_2451_p2();
void thread_layer_offset_V_fu_3887_p2();
void thread_lhs_V_1_fu_2716_p2();
void thread_lhs_V_2_fu_4174_p1();
void thread_lhs_V_3_fu_4188_p1();
void thread_lhs_V_8_cast_fu_4147_p1();
void thread_loc2_V_2_fu_2674_p1();
void thread_loc2_V_fu_4782_p1();
void thread_loc_in_group_tree_V_3_fu_2656_p2();
void thread_loc_in_group_tree_V_fu_2817_p2();
void thread_loc_in_group_tree_V_s_fu_2747_p1();
void thread_loc_in_layer_V_fu_4201_p1();
void thread_maintain_mask_V_address0();
void thread_maintain_mask_V_ce0();
void thread_maintain_mask_V_load_4_fu_5174_p1();
void thread_maintain_mask_V_load_6_fu_3655_p1();
void thread_mark_mask_V_address0();
void thread_mark_mask_V_ce0();
void thread_newIndex3_fu_2888_p1();
void thread_newIndex5_fu_4845_p1();
void thread_newIndex9_fu_3863_p1();
void thread_newIndex_fu_3332_p1();
void thread_newIndex_trunc1_fu_3323_p4();
void thread_newIndex_trunc4_fu_2879_p4();
void thread_newIndex_trunc_fu_4836_p4();
void thread_newSel1_fu_4983_p3();
void thread_newSel2_fu_4991_p3();
void thread_newSel3_fu_3450_p3();
void thread_newSel4_fu_3464_p3();
void thread_newSel5_fu_3472_p3();
void thread_newSel6_fu_3020_p3();
void thread_newSel7_fu_3034_p3();
void thread_newSel_fu_4969_p3();
void thread_not_s_fu_2791_p2();
void thread_now1_V_1_fu_2857_p2();
void thread_now1_V_fu_2776_p2();
void thread_or_cond1_fu_3458_p2();
void thread_or_cond2_fu_3028_p2();
void thread_or_cond_101_fu_3986_p2();
void thread_or_cond_fu_4977_p2();
void thread_p_0102_0_i_cast_fu_3968_p1();
void thread_p_0167_0_i1_cast_fu_3776_p1();
void thread_p_0167_0_i_cast_fu_4088_p1();
void thread_p_0244_0_i1_cast1_fu_3810_p1();
void thread_p_0244_0_i1_cast_fu_3806_p1();
void thread_p_0244_0_i_cast1_fu_4121_p1();
void thread_p_0244_0_i_cast_fu_4125_p1();
void thread_p_0248_0_i1_cast_fu_3796_p1();
void thread_p_0248_0_i_cast_fu_4106_p1();
void thread_p_0252_0_i1_cast_fu_3786_p1();
void thread_p_0252_0_i_cast_fu_4097_p1();
void thread_p_02759_0_in_fu_2803_p4();
void thread_p_061_0_i1_cast_fu_2441_p1();
void thread_p_061_0_i_cast_fu_3958_p1();
void thread_p_1_fu_2571_p1();
void thread_p_2_fu_2474_p1();
void thread_p_Repl2_10_fu_3582_p2();
void thread_p_Repl2_11_fu_5133_p2();
void thread_p_Repl2_12_fu_5159_p2();
void thread_p_Repl2_13_fu_3614_p2();
void thread_p_Repl2_14_fu_3640_p2();
void thread_p_Repl2_15_fu_3176_p2();
void thread_p_Repl2_16_fu_3206_p2();
void thread_p_Repl2_17_fu_3249_p2();
void thread_p_Repl2_18_fu_3238_p2();
void thread_p_Repl2_19_fu_3278_p2();
void thread_p_Repl2_1_fu_4915_p2();
void thread_p_Repl2_20_fu_4371_p2();
void thread_p_Repl2_21_fu_4430_p2();
void thread_p_Repl2_22_fu_4461_p2();
void thread_p_Repl2_23_fu_4522_p2();
void thread_p_Repl2_24_fu_4555_p2();
void thread_p_Repl2_25_fu_4609_p2();
void thread_p_Repl2_26_fu_4642_p2();
void thread_p_Repl2_27_fu_4690_p2();
void thread_p_Repl2_28_fu_4719_p2();
void thread_p_Repl2_29_fu_4761_p2();
void thread_p_Repl2_2_fu_3396_p2();
void thread_p_Repl2_3_fu_2946_p2();
void thread_p_Repl2_4_fu_2986_p2();
void thread_p_Repl2_5_fu_5004_p2();
void thread_p_Repl2_6_fu_3485_p2();
void thread_p_Repl2_7_fu_3059_p2();
void thread_p_Repl2_8_fu_3094_p2();
void thread_p_Repl2_9_fu_5101_p2();
void thread_p_Repl2_s_fu_2904_p2();
void thread_p_Result_10_fu_3587_p4();
void thread_p_Result_11_fu_5138_p4();
void thread_p_Result_12_fu_5165_p4();
void thread_p_Result_13_fu_3619_p4();
void thread_p_Result_14_fu_3646_p4();
void thread_p_Result_15_fu_3181_p4();
void thread_p_Result_16_fu_3219_p4();
void thread_p_Result_17_fu_3254_p4();
void thread_p_Result_18_fu_3269_p4();
void thread_p_Result_19_fu_3284_p4();
void thread_p_Result_1_fu_4920_p4();
void thread_p_Result_20_fu_4414_p4();
void thread_p_Result_21_fu_4436_p4();
void thread_p_Result_22_fu_4513_p4();
void thread_p_Result_23_fu_4527_p4();
void thread_p_Result_24_fu_4599_p4();
void thread_p_Result_25_fu_4614_p4();
void thread_p_Result_26_fu_4680_p4();
void thread_p_Result_27_fu_4696_p4();
void thread_p_Result_28_fu_4752_p4();
void thread_p_Result_29_fu_4767_p4();
void thread_p_Result_2_fu_3401_p4();
void thread_p_Result_30_fu_2390_p4();
void thread_p_Result_31_fu_2756_p4();
void thread_p_Result_32_fu_2827_p4();
void thread_p_Result_33_fu_2837_p4();
void thread_p_Result_3_fu_2951_p4();
void thread_p_Result_4_fu_3050_p4();
void thread_p_Result_5_fu_5009_p4();
void thread_p_Result_6_fu_3490_p4();
void thread_p_Result_7_fu_3064_p4();
void thread_p_Result_8_fu_3138_p4();
void thread_p_Result_9_fu_5106_p4();
void thread_p_Result_s_fu_2929_p4();
void thread_p_Val2_1_fu_2410_p2();
void thread_p_Val2_34_fu_3042_p3();
void thread_p_Val2_41_fu_3130_p3();
void thread_p_Val2_49_fu_3212_p3();
void thread_p_Val2_56_fu_4406_p3();
void thread_p_Val2_58_fu_4505_p3();
void thread_p_Val2_60_fu_4591_p3();
void thread_p_Val2_62_fu_4672_p3();
void thread_p_Val2_64_fu_4736_p6();
void thread_p_Val2_s_fu_2913_p6();
void thread_p_not_fu_2565_p2();
void thread_p_s_fu_2405_p2();
void thread_phitmp2_fu_2501_p1();
void thread_r_V_10_fu_3341_p2();
void thread_r_V_12_fu_3303_p2();
void thread_r_V_13_fu_2697_p2();
void thread_r_V_15_fu_2770_p2();
void thread_r_V_16_fu_3417_p2();
void thread_r_V_19_fu_2851_p2();
void thread_r_V_20_fu_2970_p2();
void thread_r_V_21_fu_3505_p2();
void thread_r_V_22_fu_3079_p2();
void thread_r_V_23_fu_3553_p2();
void thread_r_V_24_fu_3147_p2();
void thread_r_V_25_fu_3992_p3();
void thread_r_V_27_fu_4170_p1();
void thread_r_V_28_fu_4182_p2();
void thread_r_V_29_fu_4195_p2();
void thread_r_V_31_fu_4252_p3();
void thread_r_V_32_fu_4335_p3();
void thread_r_V_33_fu_4470_p2();
void thread_r_V_34_fu_4541_p2();
void thread_r_V_35_fu_4628_p2();
void thread_r_V_36_fu_4028_p2();
void thread_r_V_37_fu_4205_p2();
void thread_r_V_38_fu_3662_p2();
void thread_r_V_39_fu_3359_p2();
void thread_r_V_3_fu_4854_p2();
void thread_r_V_40_fu_2580_p2();
void thread_r_V_41_fu_2626_p3();
void thread_r_V_42_fu_2750_p3();
void thread_r_V_4_fu_5181_p2();
void thread_r_V_5_fu_4816_p2();
void thread_r_V_6_fu_4872_p2();
void thread_r_V_7_fu_4936_p2();
void thread_r_V_8_fu_5024_p2();
void thread_r_V_9_fu_5072_p2();
void thread_r_V_fu_4793_p2();
void thread_rec_bits_V_fu_2781_p1();
void thread_rhs_V_13_cast_fu_4467_p1();
void thread_rhs_V_14_cast_fu_2576_p1();
void thread_rhs_V_2_fu_4178_p1();
void thread_rhs_V_3_fu_4191_p1();
void thread_rhs_V_7_cast_fu_2967_p1();
void thread_rhs_V_8_cast_fu_4024_p1();
void thread_rhs_V_cast_fu_2693_p1();
void thread_sel_tmp10_fu_5045_p3();
void thread_sel_tmp11_fu_5053_p2();
void thread_sel_tmp12_fu_3520_p2();
void thread_sel_tmp13_fu_3526_p3();
void thread_sel_tmp14_fu_3534_p2();
void thread_sel_tmp15_fu_3110_p2();
void thread_sel_tmp16_fu_3116_p3();
void thread_sel_tmp17_fu_3124_p2();
void thread_sel_tmp18_fu_4386_p2();
void thread_sel_tmp19_fu_4392_p3();
void thread_sel_tmp1_fu_3444_p2();
void thread_sel_tmp1_i_fu_2515_p3();
void thread_sel_tmp20_fu_4400_p2();
void thread_sel_tmp21_fu_4485_p2();
void thread_sel_tmp22_fu_4491_p3();
void thread_sel_tmp23_fu_4499_p2();
void thread_sel_tmp24_fu_4571_p2();
void thread_sel_tmp25_fu_4577_p3();
void thread_sel_tmp26_fu_4585_p2();
void thread_sel_tmp2_fu_4957_p2();
void thread_sel_tmp2_i_fu_2523_p2();
void thread_sel_tmp3_fu_3002_p2();
void thread_sel_tmp3_i_fu_2529_p3();
void thread_sel_tmp4_fu_4963_p2();
void thread_sel_tmp4_i_fu_2537_p2();
void thread_sel_tmp5_fu_3008_p2();
void thread_sel_tmp5_i_fu_2543_p3();
void thread_sel_tmp6_fu_3014_p2();
void thread_sel_tmp6_i_fu_2551_p2();
void thread_sel_tmp7_fu_3432_p2();
void thread_sel_tmp8_fu_5039_p2();
void thread_sel_tmp9_fu_3438_p2();
void thread_sel_tmp_fu_4951_p2();
void thread_sel_tmp_i_fu_2509_p2();
void thread_shift_constant_V_address0();
void thread_shift_constant_V_ce0();
void thread_shift_constant_V_loa_2_fu_2652_p1();
void thread_tmp0_V_1_fu_5187_p2();
void thread_tmp0_V_5_fu_3732_p2();
void thread_tmp1_V_fu_3933_p2();
void thread_tmp76_fu_3822_p2();
void thread_tmp77_fu_3830_p2();
void thread_tmp78_fu_3845_p2();
void thread_tmp79_fu_3851_p2();
void thread_tmp91_fu_4115_p2();
void thread_tmp92_cast_fu_3826_p1();
void thread_tmp92_fu_4132_p2();
void thread_tmp93_cast_fu_3835_p1();
void thread_tmp97_cast_fu_4129_p1();
void thread_tmp98_cast_fu_4137_p1();
void thread_tmp_100_fu_4222_p1();
void thread_tmp_101_fu_4226_p2();
void thread_tmp_102_fu_4236_p2();
void thread_tmp_103_fu_4242_p2();
void thread_tmp_105_fu_4260_p1();
void thread_tmp_107_fu_4265_p1();
void thread_tmp_108_fu_4941_p4();
void thread_tmp_109_fu_4812_p1();
void thread_tmp_10_fu_3770_p2();
void thread_tmp_110_cast_fu_3999_p1();
void thread_tmp_110_fu_3299_p1();
void thread_tmp_111_fu_2708_p1();
void thread_tmp_112_fu_2586_p3();
void thread_tmp_113_fu_2617_p1();
void thread_tmp_114_fu_2640_p1();
void thread_tmp_115_fu_3422_p4();
void thread_tmp_116_fu_2992_p4();
void thread_tmp_117_fu_4297_p2();
void thread_tmp_118_fu_4302_p4();
void thread_tmp_119_fu_4311_p2();
void thread_tmp_120_fu_4317_p2();
void thread_tmp_121_fu_4323_p2();
void thread_tmp_122_fu_4329_p2();
void thread_tmp_125_cast_fu_4160_p1();
void thread_tmp_128_fu_5029_p4();
void thread_tmp_129_cast_fu_4232_p1();
void thread_tmp_129_fu_3510_p4();
void thread_tmp_12_fu_4798_p1();
void thread_tmp_130_fu_3100_p4();
void thread_tmp_131_fu_5077_p4();
void thread_tmp_132_fu_3558_p4();
void thread_tmp_133_fu_3152_p4();
void thread_tmp_134_fu_2712_p1();
void thread_tmp_135_fu_4377_p4();
void thread_tmp_136_fu_4475_p4();
void thread_tmp_137_fu_4561_p4();
void thread_tmp_138_fu_4648_p4();
void thread_tmp_147_fu_4865_p1();
void thread_tmp_148_fu_3352_p1();
void thread_tmp_152_fu_2897_p1();
void thread_tmp_157_fu_2976_p4();
void thread_tmp_15_fu_2492_p4();
void thread_tmp_162_fu_3084_p4();
void thread_tmp_171_fu_3196_p4();
void thread_tmp_174_fu_3228_p4();
void thread_tmp_178_fu_4014_p1();
void thread_tmp_181_fu_4210_p3();
void thread_tmp_182_fu_4248_p1();
void thread_tmp_183_fu_4269_p1();
void thread_tmp_184_fu_4273_p1();
void thread_tmp_185_fu_4276_p1();
void thread_tmp_186_fu_4280_p1();
void thread_tmp_187_fu_4283_p1();
void thread_tmp_188_fu_4287_p1();
void thread_tmp_189_fu_4290_p1();
void thread_tmp_190_fu_4294_p1();
void thread_tmp_193_fu_4451_p4();
void thread_tmp_196_fu_4546_p4();
void thread_tmp_199_fu_4633_p4();
void thread_tmp_19_fu_2598_p1();
void thread_tmp_1_fu_2429_p2();
void thread_tmp_202_fu_4710_p4();
void thread_tmp_20_fu_2601_p2();
void thread_tmp_21_fu_4860_p1();
void thread_tmp_22_fu_5178_p1();
void thread_tmp_23_fu_5193_p2();
void thread_tmp_24_fu_5205_p2();
void thread_tmp_25_fu_5217_p2();
void thread_tmp_26_fu_5229_p2();
void thread_tmp_27_fu_5241_p2();
void thread_tmp_28_fu_4822_p1();
void thread_tmp_29_cast_fu_4869_p1();
void thread_tmp_29_fu_2611_p2();
void thread_tmp_30_fu_2621_p2();
void thread_tmp_31_fu_2468_p1();
void thread_tmp_32_fu_4878_p2();
void thread_tmp_33_fu_4903_p2();
void thread_tmp_34_fu_3347_p1();
void thread_tmp_35_fu_4999_p2();
void thread_tmp_36_fu_3659_p1();
void thread_tmp_37_fu_5067_p2();
void thread_tmp_38_fu_3668_p2();
void thread_tmp_39_fu_5128_p2();
void thread_tmp_3_fu_2435_p2();
void thread_tmp_40_fu_3680_p2();
void thread_tmp_41_fu_5153_p2();
void thread_tmp_42_fu_3692_p2();
void thread_tmp_43_fu_3704_p2();
void thread_tmp_44_fu_3716_p2();
void thread_tmp_45_fu_3309_p1();
void thread_tmp_46_cast_fu_3356_p1();
void thread_tmp_46_fu_4786_p3();
void thread_tmp_47_fu_2643_p2();
void thread_tmp_48_fu_2634_p2();
void thread_tmp_49_fu_3384_p2();
void thread_tmp_50_cast_fu_2594_p1();
void thread_tmp_50_fu_2665_p2();
void thread_tmp_51_fu_2688_p1();
void thread_tmp_52_cast_fu_2607_p1();
void thread_tmp_52_fu_2703_p1();
void thread_tmp_53_fu_2722_p2();
void thread_tmp_54_fu_2728_p2();
void thread_tmp_55_fu_3480_p2();
void thread_tmp_56_fu_2505_p1();
void thread_tmp_57_fu_3548_p2();
void thread_tmp_59_fu_3609_p2();
void thread_tmp_5_fu_2463_p2();
void thread_tmp_60_fu_2766_p1();
void thread_tmp_61_fu_3634_p2();
void thread_tmp_63_fu_3780_p2();
void thread_tmp_64_fu_4887_p6();
void thread_tmp_66_fu_3368_p6();
void thread_tmp_67_cast_fu_2648_p1();
void thread_tmp_67_fu_2785_p2();
void thread_tmp_68_fu_2797_p2();
void thread_tmp_6_fu_2445_p2();
void thread_tmp_70_fu_2847_p1();
void thread_tmp_71_fu_3790_p2();
void thread_tmp_72_fu_3800_p2();
void thread_tmp_73_fu_3244_p2();
void thread_tmp_74_fu_3814_p1();
void thread_tmp_75_fu_3818_p1();
void thread_tmp_76_cast_fu_2662_p1();
void thread_tmp_76_fu_3839_p2();
void thread_tmp_77_fu_3872_p3();
void thread_tmp_78_fu_3857_p2();
void thread_tmp_79_fu_3923_p2();
void thread_tmp_80_fu_3907_p6();
void thread_tmp_81_fu_3929_p2();
void thread_tmp_82_fu_3952_p2();
void thread_tmp_83_fu_3962_p2();
void thread_tmp_84_fu_3972_p2();
void thread_tmp_85_fu_3977_p2();
void thread_tmp_86_fu_3982_p2();
void thread_tmp_87_fu_4009_p1();
void thread_tmp_88_fu_2813_p1();
void thread_tmp_89_fu_4034_p2();
void thread_tmp_8_fu_3728_p1();
void thread_tmp_91_fu_4083_p2();
void thread_tmp_92_fu_4092_p2();
void thread_tmp_93_fu_4101_p2();
void thread_tmp_94_fu_4110_p2();
void thread_tmp_95_cast_fu_3880_p1();
void thread_tmp_95_fu_4141_p2();
void thread_tmp_96_cast1_fu_3884_p1();
void thread_tmp_96_fu_4151_p1();
void thread_tmp_97_fu_4154_p2();
void thread_tmp_98_fu_4164_p2();
void thread_tmp_99_fu_4218_p1();
void thread_tmp_9_fu_2458_p2();
void thread_tmp_fu_2400_p2();
void thread_tmp_size_V_fu_2384_p2();
void thread_tree_offset_V_2_fu_2670_p1();
void thread_tree_offset_V_cast_fu_4080_p1();
void thread_tree_offset_V_fu_4003_p2();
void thread_val_assign_2_fu_2863_p2();
void thread_val_assign_7_cast1_fu_4350_p2();
void thread_val_assign_7_cast2_fu_4356_p2();
void thread_val_assign_7_cast3_fu_4362_p2();
void thread_val_assign_7_cast_fu_4344_p2();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
/****************************************************************************
*
* This file contains the dut_type_wrapper module
* for use in the verilog verification wrapper dut_vlwrapper.v
* It creats an instance of the dut module and has threads
* for converting the BEH ports to RTL level ports on the wrapper.
*
****************************************************************************/
#ifndef _DUT_TYPE_WRAP_INCLUDED_
#define _DUT_TYPE_WRAP_INCLUDED_
#if !defined(ioConfig_TLM) && !defined(ioConfig_PIN)
#if defined(_p_ioConfig_TLM)
#define ioConfig_TLM 1
#endif
#if defined(_p_ioConfig_PIN)
#define ioConfig_PIN 1
#endif
#endif
#include <systemc.h>
#include "dut.h"
// Declaration of wrapper with RTL level ports
SC_MODULE(dut_type_wrapper)
{
public:
#if defined ( ioConfig_TLM )
sc_in< bool > clk;
sc_in< bool > rst;
#else
sc_in< bool > clk;
sc_in< bool > rst;
#endif
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
#if defined ( ioConfig_TLM )
,clk("clk")
,rst("rst")
#else
,clk("clk")
,rst("rst")
#endif
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
};
#endif /* */
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _foo_HH_
#define _foo_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct foo : public sc_module {
// Port declarations 15
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > d_req_din;
sc_in< sc_logic > d_req_full_n;
sc_out< sc_logic > d_req_write;
sc_in< sc_logic > d_rsp_empty_n;
sc_out< sc_logic > d_rsp_read;
sc_out< sc_lv<32> > d_address;
sc_in< sc_lv<32> > d_datain;
sc_out< sc_lv<32> > d_dataout;
sc_out< sc_lv<32> > d_size;
// Module declarations
foo(sc_module_name name);
SC_HAS_PROCESS(foo);
~foo();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
sc_signal< sc_lv<7> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<32> > acc;
sc_signal< sc_lv<3> > i_fu_76_p2;
sc_signal< sc_lv<3> > i_reg_121;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<32> > d_addr_read_reg_133;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<32> > add_ln9_1_fu_96_p2;
sc_signal< sc_lv<32> > add_ln9_1_reg_138;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<3> > i_0_reg_58;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<64> > zext_ln9_1_fu_82_p1;
sc_signal< sc_lv<64> > zext_ln9_fu_107_p1;
sc_signal< sc_lv<1> > icmp_ln8_fu_70_p2;
sc_signal< sc_lv<7> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<7> ap_ST_fsm_state1;
static const sc_lv<7> ap_ST_fsm_state2;
static const sc_lv<7> ap_ST_fsm_state3;
static const sc_lv<7> ap_ST_fsm_state4;
static const sc_lv<7> ap_ST_fsm_state5;
static const sc_lv<7> ap_ST_fsm_state6;
static const sc_lv<7> ap_ST_fsm_state7;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<1> ap_const_lv1_1;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln9_1_fu_96_p2();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state7();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_d_address();
void thread_d_dataout();
void thread_d_req_din();
void thread_d_req_write();
void thread_d_rsp_read();
void thread_d_size();
void thread_i_fu_76_p2();
void thread_icmp_ln8_fu_70_p2();
void thread_zext_ln9_1_fu_82_p1();
void thread_zext_ln9_fu_107_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
/*
* Copyright (c) 2016 Baptiste Roux.
* email: <baptiste.roux AT inria.fr>.
*/
/*
* File: amba_GP.h
* SystemC TLM2.0 component for simulating amba general purpose memory map bus
* One tlm_socket master for Cpu
* nb_Msk tlm_socket slave for hw accelerators
*/
#ifndef _AMBA_GP
#define _AMBA_GP
#include "systemc.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "models/monSystem/monSystem.h"
#include "models/utility/socConfigStruct.h"
#define FW_DELAY sc_time(10,SC_NS)
/*---
* CLASS DEFINITION
*----------------------------------------------------------------------------*/
class amba_GP: public sc_core::sc_module, public ms::monSysSlave
{
const uint8_t nb_Msk;
uint8_t *amba_mem;
size_t size;
std::map<sc_dt::uint64, uint> addrToSk;
uint updtTransToSubspace(tlm::tlm_generic_payload &trans);
public:
tlm_utils::simple_target_socket<amba_GP> cpu_Ssk;
tlm_utils::simple_initiator_socket<amba_GP> **pl_Msk;
amba_GP(sc_core::sc_module_name name, uint8_t nbMsk, cereal::serialMap<sb::hwCpnCnf> hwCpn);
~amba_GP();
virtual void b_transport(tlm::tlm_generic_payload& trans,
sc_time& delay);
};
#endif /*_AMBA_GP*/
|
#ifndef RISCV_TOP_H
#define RISCV_TOP_H
#include <systemc.h>
#include "axi4.h"
#include "axi4.h"
class Vriscv_top;
class VerilatedVcdC;
//-------------------------------------------------------------
// riscv_top: RTL wrapper class
//-------------------------------------------------------------
class riscv_top: public sc_module
{
public:
sc_in <bool> clk_in;
sc_in <bool> rst_in;
sc_in <bool> intr_in;
sc_in <uint32_t> reset_vector_in;
sc_in <axi4_slave> axi_i_in;
sc_out <axi4_master> axi_i_out;
sc_in <axi4_slave> axi_d_in;
sc_out <axi4_master> axi_d_out;
sc_in<bool> tck_i;
sc_in<bool> tms_i;
sc_in<bool> tdi_i;
sc_out<bool> tdo_o;
//-------------------------------------------------------------
// Constructor
//-------------------------------------------------------------
SC_HAS_PROCESS(riscv_top);
riscv_top(sc_module_name name);
//-------------------------------------------------------------
// Trace
//-------------------------------------------------------------
virtual void add_trace(sc_trace_file *vcd, std::string prefix)
{
#undef TRACE_SIGNAL
#define TRACE_SIGNAL(s) sc_trace(vcd,s,prefix + #s)
TRACE_SIGNAL(clk_in);
TRACE_SIGNAL(rst_in);
TRACE_SIGNAL(intr_in);
TRACE_SIGNAL(reset_vector_in);
TRACE_SIGNAL(axi_i_in);
TRACE_SIGNAL(axi_i_out);
TRACE_SIGNAL(axi_d_in);
TRACE_SIGNAL(axi_d_out);
#undef TRACE_SIGNAL
}
void async_outputs(void);
void trace_rtl(void);
void trace_enable(VerilatedVcdC *p);
void trace_enable(VerilatedVcdC *p, sc_core::sc_time start_time);
//-------------------------------------------------------------
// Signals
//-------------------------------------------------------------
private:
sc_signal <bool> m_clk_in;
sc_signal <bool> m_rst_in;
sc_signal <bool> m_axi_i_awready_in;
sc_signal <bool> m_axi_i_wready_in;
sc_signal <bool> m_axi_i_bvalid_in;
sc_signal <uint32_t> m_axi_i_bresp_in;
sc_signal <uint32_t> m_axi_i_bid_in;
sc_signal <bool> m_axi_i_arready_in;
sc_signal <bool> m_axi_i_rvalid_in;
sc_signal <uint32_t> m_axi_i_rdata_in;
sc_signal <uint32_t> m_axi_i_rresp_in;
sc_signal <uint32_t> m_axi_i_rid_in;
sc_signal <bool> m_axi_i_rlast_in;
sc_signal <bool> m_axi_d_awready_in;
sc_signal <bool> m_axi_d_wready_in;
sc_signal <bool> m_axi_d_bvalid_in;
sc_signal <uint32_t> m_axi_d_bresp_in;
sc_signal <uint32_t> m_axi_d_bid_in;
sc_signal <bool> m_axi_d_arready_in;
sc_signal <bool> m_axi_d_rvalid_in;
sc_signal <uint32_t> m_axi_d_rdata_in;
sc_signal <uint32_t> m_axi_d_rresp_in;
sc_signal <uint32_t> m_axi_d_rid_in;
sc_signal <bool> m_axi_d_rlast_in;
sc_signal <bool> m_intr_in;
sc_signal <uint32_t> m_reset_vector_in;
sc_signal <bool> m_axi_i_awvalid_out;
sc_signal <uint32_t> m_axi_i_awaddr_out;
sc_signal <uint32_t> m_axi_i_awid_out;
sc_signal <uint32_t> m_axi_i_awlen_out;
sc_signal <uint32_t> m_axi_i_awburst_out;
sc_signal <bool> m_axi_i_wvalid_out;
sc_signal <uint32_t> m_axi_i_wdata_out;
sc_signal <uint32_t> m_axi_i_wstrb_out;
sc_signal <bool> m_axi_i_wlast_out;
sc_signal <bool> m_axi_i_bready_out;
sc_signal <bool> m_axi_i_arvalid_out;
sc_signal <uint32_t> m_axi_i_araddr_out;
sc_signal <uint32_t> m_axi_i_arid_out;
sc_signal <uint32_t> m_axi_i_arlen_out;
sc_signal <uint32_t> m_axi_i_arburst_out;
sc_signal <bool> m_axi_i_rready_out;
sc_signal <bool> m_axi_d_awvalid_out;
sc_signal <uint32_t> m_axi_d_awaddr_out;
sc_signal <uint32_t> m_axi_d_awid_out;
sc_signal <uint32_t> m_axi_d_awlen_out;
sc_signal <uint32_t> m_axi_d_awburst_out;
sc_signal <bool> m_axi_d_wvalid_out;
sc_signal <uint32_t> m_axi_d_wdata_out;
sc_signal <uint32_t> m_axi_d_wstrb_out;
sc_signal <bool> m_axi_d_wlast_out;
sc_signal <bool> m_axi_d_bready_out;
sc_signal <bool> m_axi_d_arvalid_out;
sc_signal <uint32_t> m_axi_d_araddr_out;
sc_signal <uint32_t> m_axi_d_arid_out;
sc_signal <uint32_t> m_axi_d_arlen_out;
sc_signal <uint32_t> m_axi_d_arburst_out;
sc_signal <bool> m_axi_d_rready_out;
public:
Vriscv_top *m_rtl;
#if VM_TRACE
VerilatedVcdC * m_vcd;
bool m_delay_waves;
sc_core::sc_time m_waves_start;
#endif
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Duplicate_HH_
#define _Duplicate_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Duplicate : public sc_module {
// Port declarations 19
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_in< sc_logic > start_full_n;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > start_out;
sc_out< sc_logic > start_write;
sc_in< sc_lv<8> > src_data_stream_V_dout;
sc_in< sc_logic > src_data_stream_V_empty_n;
sc_out< sc_logic > src_data_stream_V_read;
sc_out< sc_lv<8> > dst1_data_stream_V_din;
sc_in< sc_logic > dst1_data_stream_V_full_n;
sc_out< sc_logic > dst1_data_stream_V_write;
sc_out< sc_lv<8> > dst2_data_stream_V_din;
sc_in< sc_logic > dst2_data_stream_V_full_n;
sc_out< sc_logic > dst2_data_stream_V_write;
// Module declarations
Duplicate(sc_module_name name);
SC_HAS_PROCESS(Duplicate);
~Duplicate();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > real_start;
sc_signal< sc_logic > start_once_reg;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > internal_ap_ready;
sc_signal< sc_logic > src_data_stream_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<1> > exitcond_reg_169;
sc_signal< sc_logic > dst1_data_stream_V_blk_n;
sc_signal< sc_logic > dst2_data_stream_V_blk_n;
sc_signal< sc_lv<11> > t_V_3_reg_125;
sc_signal< sc_lv<1> > exitcond3_fu_136_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<11> > i_V_fu_142_p2;
sc_signal< sc_lv<11> > i_V_reg_164;
sc_signal< sc_lv<1> > exitcond_fu_148_p2;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<11> > j_V_fu_154_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state3;
sc_signal< sc_lv<11> > t_V_reg_114;
sc_signal< bool > ap_block_state1;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<4> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_pp0_stage0;
static const sc_lv<4> ap_ST_fsm_state5;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_2;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<11> ap_const_lv11_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<11> ap_const_lv11_438;
static const sc_lv<11> ap_const_lv11_1;
static const sc_lv<11> ap_const_lv11_780;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state5();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state3_pp0_stage0_iter0();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_condition_pp0_exit_iter0_state3();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_ready();
void thread_dst1_data_stream_V_blk_n();
void thread_dst1_data_stream_V_din();
void thread_dst1_data_stream_V_write();
void thread_dst2_data_stream_V_blk_n();
void thread_dst2_data_stream_V_din();
void thread_dst2_data_stream_V_write();
void thread_exitcond3_fu_136_p2();
void thread_exitcond_fu_148_p2();
void thread_i_V_fu_142_p2();
void thread_internal_ap_ready();
void thread_j_V_fu_154_p2();
void thread_real_start();
void thread_src_data_stream_V_blk_n();
void thread_src_data_stream_V_read();
void thread_start_out();
void thread_start_write();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#include <systemc.h> // SystemC definitions
#include "system.h" // Top-level System module header file
static System * m_system = NULL; // The pointer that holds the top-level System module instance.
void esc_elaborate() // This function is required by Stratus to support SystemC-Verilog
{ // cosimulation. It instances the top-level module.
m_system = new System( "system" );
}
void esc_cleanup() // This function is called at the end of simulation by the
{ // Stratus co-simulation hub. It should delete the top-level
delete m_system; // module instance.
}
int sc_main( int argc, char ** argv ) // This function is called by the SystemC kernel for pure SystemC simulations
{
esc_initialize( argc, argv ); // esc_initialize() passes in the cmd-line args. This initializes the Stratus simulation
// environment (such as opening report files for later logging and analysis).
esc_elaborate(); // esc_elaborate() (defined above) creates the top-level module instance. In a SystemC-Verilog
// co-simulation, this is called during cosim initialization rather than from sc_main.
sc_start(); // Starts the simulation. Returns when a module calls esc_stop(), which finishes the simulation.
// esc_cleanup() (defined above) is automatically called before sc_start() returns.
return 0; // Returns the status of the simulation. Required by most C compilers.
}
|
#ifndef TOP_H_
#define TOP_H_
#include "systemc.h"
class top : public sc_module {
public:
SC_HAS_PROCESS(top);
top(sc_module_name name_):
sc_module(name_)
, m_phase(0.0)
, clock("CLOCK", 10, 0.5, 0.0)
, sig_sin("sig_sin")
, sig_cos("sig_cos")
, sig_steps("sig_steps", 256) {
SC_METHOD(Action);
sensitive_pos << clock;
}
virtual ~top();
private:
void Action();
private:
double m_phase;
// signal
sc_clock clock;
sc_signal<double> sig_sin;
sc_signal<double> sig_cos;
sc_signal<int> sig_steps;
};
#endif // #ifndef TOP_H_
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pooling2d_cl_1_HH_
#define _pooling2d_cl_1_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "pooling2d_cl_pool_V.h"
namespace ap_rtl {
struct pooling2d_cl_1 : public sc_module {
// Port declarations 14
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<12> > data_V_address0;
sc_out< sc_logic > data_V_ce0;
sc_in< sc_lv<13> > data_V_q0;
sc_out< sc_lv<10> > res_V_address0;
sc_out< sc_logic > res_V_ce0;
sc_out< sc_logic > res_V_we0;
sc_out< sc_lv<14> > res_V_d0;
// Module declarations
pooling2d_cl_1(sc_module_name name);
SC_HAS_PROCESS(pooling2d_cl_1);
~pooling2d_cl_1();
sc_trace_file* mVcdFile;
pooling2d_cl_pool_V* pool_V_U;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<15> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<9> > ff_cast2_cast_fu_215_p1;
sc_signal< sc_lv<9> > ff_cast2_cast_reg_474;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<5> > ff_1_fu_225_p2;
sc_signal< sc_lv<5> > ff_1_reg_482;
sc_signal< sc_lv<11> > tmp_2_fu_277_p3;
sc_signal< sc_lv<11> > tmp_2_reg_490;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > tmp_fu_231_p2;
sc_signal< sc_lv<4> > ii_3_fu_291_p2;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<1> > tmp_3_fu_285_p2;
sc_signal< sc_lv<2> > kk_1_fu_307_p2;
sc_signal< sc_lv<2> > kk_1_reg_506;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<4> > tmp_8_fu_313_p2;
sc_signal< sc_lv<4> > tmp_8_reg_511;
sc_signal< sc_lv<1> > tmp_4_fu_301_p2;
sc_signal< sc_lv<1> > tmp_9_fu_322_p2;
sc_signal< sc_lv<1> > tmp_9_reg_517;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<2> > tmp_31_fu_327_p2;
sc_signal< sc_lv<2> > tmp_31_reg_521;
sc_signal< sc_lv<12> > tmp_10_fu_333_p2;
sc_signal< sc_lv<12> > tmp_10_reg_526;
sc_signal< sc_lv<2> > ll_1_fu_349_p2;
sc_signal< sc_lv<2> > ll_1_reg_534;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<1> > tmp_13_fu_361_p2;
sc_signal< sc_lv<1> > tmp_13_reg_539;
sc_signal< sc_lv<1> > tmp_11_fu_343_p2;
sc_signal< sc_lv<2> > grp_fu_210_p2;
sc_signal< sc_lv<2> > tmp_16_reg_543;
sc_signal< sc_lv<9> > tmp1_fu_379_p2;
sc_signal< sc_lv<9> > tmp1_reg_548;
sc_signal< sc_lv<12> > tmp_19_fu_392_p2;
sc_signal< sc_lv<12> > tmp_19_reg_553;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_lv<13> > data_V_load_reg_563;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_lv<64> > tmp_7_fu_430_p1;
sc_signal< sc_lv<64> > tmp_7_reg_568;
sc_signal< sc_logic > ap_CS_fsm_state12;
sc_signal< sc_lv<14> > pool_V_q0;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_lv<1> > exitcond_i_i_fu_434_p2;
sc_signal< sc_lv<3> > i_fu_445_p2;
sc_signal< sc_lv<3> > i_reg_586;
sc_signal< sc_lv<4> > jj_1_fu_451_p2;
sc_signal< sc_lv<14> > pool_V_load_reg_596;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<14> > y_V_3_fu_462_p3;
sc_signal< sc_logic > ap_CS_fsm_state15;
sc_signal< sc_lv<2> > pool_V_address0;
sc_signal< sc_logic > pool_V_ce0;
sc_signal< sc_logic > pool_V_we0;
sc_signal< sc_lv<14> > pool_V_d0;
sc_signal< sc_lv<5> > ff_reg_129;
sc_signal< sc_lv<4> > ii_reg_141;
sc_signal< sc_lv<1> > exitcond_fu_219_p2;
sc_signal< sc_lv<4> > jj_reg_153;
sc_signal< sc_lv<2> > kk_reg_165;
sc_signal< sc_lv<2> > ll_reg_177;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< sc_lv<14> > agg_result_V_i_i_reg_188;
sc_signal< sc_lv<3> > i_i_i_reg_199;
sc_signal< sc_lv<64> > tmp_15_fu_384_p1;
sc_signal< sc_lv<64> > tmp_20_fu_397_p1;
sc_signal< sc_lv<64> > tmp_17_fu_401_p1;
sc_signal< sc_lv<64> > tmp_i_i_fu_440_p1;
sc_signal< sc_lv<14> > extLd_fu_405_p1;
sc_signal< sc_lv<10> > p_shl_fu_237_p3;
sc_signal< sc_lv<8> > p_shl5_fu_249_p3;
sc_signal< sc_lv<11> > p_shl_cast_fu_245_p1;
sc_signal< sc_lv<11> > p_shl5_cast_fu_257_p1;
sc_signal< sc_lv<11> > tmp_s_fu_261_p2;
sc_signal< sc_lv<6> > tmp_1_fu_267_p4;
sc_signal< sc_lv<4> > kk_cast8_fu_297_p1;
sc_signal< sc_lv<4> > tmp_10_fu_333_p1;
sc_signal< sc_lv<4> > ll_cast7_fu_339_p1;
sc_signal< sc_lv<4> > tmp_12_fu_355_p2;
sc_signal< sc_lv<8> > tmp_18_fu_367_p3;
sc_signal< sc_lv<9> > tmp_66_cast_cast_fu_375_p1;
sc_signal< sc_lv<12> > tmp1_cast_fu_389_p1;
sc_signal< sc_lv<7> > tmp_5_fu_409_p3;
sc_signal< sc_lv<11> > tmp_51_cast_fu_417_p1;
sc_signal< sc_lv<11> > tmp_6_fu_421_p2;
sc_signal< sc_lv<32> > tmp_53_cast_fu_426_p1;
sc_signal< sc_lv<1> > tmp_i_i_37_fu_457_p2;
sc_signal< sc_lv<15> > ap_NS_fsm;
sc_signal< sc_lv<12> > tmp_10_fu_333_p10;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<15> ap_ST_fsm_state1;
static const sc_lv<15> ap_ST_fsm_state2;
static const sc_lv<15> ap_ST_fsm_state3;
static const sc_lv<15> ap_ST_fsm_state4;
static const sc_lv<15> ap_ST_fsm_state5;
static const sc_lv<15> ap_ST_fsm_state6;
static const sc_lv<15> ap_ST_fsm_state7;
static const sc_lv<15> ap_ST_fsm_state8;
static const sc_lv<15> ap_ST_fsm_state9;
static const sc_lv<15> ap_ST_fsm_state10;
static const sc_lv<15> ap_ST_fsm_state11;
static const sc_lv<15> ap_ST_fsm_state12;
static const sc_lv<15> ap_ST_fsm_state13;
static const sc_lv<15> ap_ST_fsm_state14;
static const sc_lv<15> ap_ST_fsm_state15;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<14> ap_const_lv14_2000;
static const sc_lv<5> ap_const_lv5_10;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<4> ap_const_lv4_C;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<4> ap_const_lv4_B;
static const sc_lv<12> ap_const_lv12_D0;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<3> ap_const_lv3_4;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state12();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state9();
void thread_ap_block_state1();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_data_V_address0();
void thread_data_V_ce0();
void thread_exitcond_fu_219_p2();
void thread_exitcond_i_i_fu_434_p2();
void thread_extLd_fu_405_p1();
void thread_ff_1_fu_225_p2();
void thread_ff_cast2_cast_fu_215_p1();
void thread_grp_fu_210_p2();
void thread_i_fu_445_p2();
void thread_ii_3_fu_291_p2();
void thread_jj_1_fu_451_p2();
void thread_kk_1_fu_307_p2();
void thread_kk_cast8_fu_297_p1();
void thread_ll_1_fu_349_p2();
void thread_ll_cast7_fu_339_p1();
void thread_p_shl5_cast_fu_257_p1();
void thread_p_shl5_fu_249_p3();
void thread_p_shl_cast_fu_245_p1();
void thread_p_shl_fu_237_p3();
void thread_pool_V_address0();
void thread_pool_V_ce0();
void thread_pool_V_d0();
void thread_pool_V_we0();
void thread_res_V_address0();
void thread_res_V_ce0();
void thread_res_V_d0();
void thread_res_V_we0();
void thread_tmp1_cast_fu_389_p1();
void thread_tmp1_fu_379_p2();
void thread_tmp_10_fu_333_p1();
void thread_tmp_10_fu_333_p10();
void thread_tmp_10_fu_333_p2();
void thread_tmp_11_fu_343_p2();
void thread_tmp_12_fu_355_p2();
void thread_tmp_13_fu_361_p2();
void thread_tmp_15_fu_384_p1();
void thread_tmp_17_fu_401_p1();
void thread_tmp_18_fu_367_p3();
void thread_tmp_19_fu_392_p2();
void thread_tmp_1_fu_267_p4();
void thread_tmp_20_fu_397_p1();
void thread_tmp_2_fu_277_p3();
void thread_tmp_31_fu_327_p2();
void thread_tmp_3_fu_285_p2();
void thread_tmp_4_fu_301_p2();
void thread_tmp_51_cast_fu_417_p1();
void thread_tmp_53_cast_fu_426_p1();
void thread_tmp_5_fu_409_p3();
void thread_tmp_66_cast_cast_fu_375_p1();
void thread_tmp_6_fu_421_p2();
void thread_tmp_7_fu_430_p1();
void thread_tmp_8_fu_313_p2();
void thread_tmp_9_fu_322_p2();
void thread_tmp_fu_231_p2();
void thread_tmp_i_i_37_fu_457_p2();
void thread_tmp_i_i_fu_440_p1();
void thread_tmp_s_fu_261_p2();
void thread_y_V_3_fu_462_p3();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Block_myproject_axi_exit35_proc_HH_
#define _Block_myproject_axi_exit35_proc_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Block_myproject_axi_exit35_proc : public sc_module {
// Port declarations 57
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<16> > out_local_V_data_0_V_dout;
sc_in< sc_logic > out_local_V_data_0_V_empty_n;
sc_out< sc_logic > out_local_V_data_0_V_read;
sc_in< sc_lv<16> > out_local_V_data_1_V_dout;
sc_in< sc_logic > out_local_V_data_1_V_empty_n;
sc_out< sc_logic > out_local_V_data_1_V_read;
sc_in< sc_lv<16> > out_local_V_data_2_V_dout;
sc_in< sc_logic > out_local_V_data_2_V_empty_n;
sc_out< sc_logic > out_local_V_data_2_V_read;
sc_in< sc_lv<16> > out_local_V_data_3_V_dout;
sc_in< sc_logic > out_local_V_data_3_V_empty_n;
sc_out< sc_logic > out_local_V_data_3_V_read;
sc_in< sc_lv<16> > out_local_V_data_4_V_dout;
sc_in< sc_logic > out_local_V_data_4_V_empty_n;
sc_out< sc_logic > out_local_V_data_4_V_read;
sc_in< sc_lv<16> > out_local_V_data_5_V_dout;
sc_in< sc_logic > out_local_V_data_5_V_empty_n;
sc_out< sc_logic > out_local_V_data_5_V_read;
sc_in< sc_lv<16> > out_local_V_data_6_V_dout;
sc_in< sc_logic > out_local_V_data_6_V_empty_n;
sc_out< sc_logic > out_local_V_data_6_V_read;
sc_in< sc_lv<16> > out_local_V_data_7_V_dout;
sc_in< sc_logic > out_local_V_data_7_V_empty_n;
sc_out< sc_logic > out_local_V_data_7_V_read;
sc_in< sc_lv<16> > out_local_V_data_8_V_dout;
sc_in< sc_logic > out_local_V_data_8_V_empty_n;
sc_out< sc_logic > out_local_V_data_8_V_read;
sc_in< sc_lv<16> > out_local_V_data_9_V_dout;
sc_in< sc_logic > out_local_V_data_9_V_empty_n;
sc_out< sc_logic > out_local_V_data_9_V_read;
sc_out< sc_lv<16> > tmp_data_V_0;
sc_out< sc_logic > tmp_data_V_0_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_1;
sc_out< sc_logic > tmp_data_V_1_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_2;
sc_out< sc_logic > tmp_data_V_2_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_3;
sc_out< sc_logic > tmp_data_V_3_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_4;
sc_out< sc_logic > tmp_data_V_4_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_5;
sc_out< sc_logic > tmp_data_V_5_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_6;
sc_out< sc_logic > tmp_data_V_6_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_7;
sc_out< sc_logic > tmp_data_V_7_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_8;
sc_out< sc_logic > tmp_data_V_8_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_9;
sc_out< sc_logic > tmp_data_V_9_ap_vld;
// Module declarations
Block_myproject_axi_exit35_proc(sc_module_name name);
SC_HAS_PROCESS(Block_myproject_axi_exit35_proc);
~Block_myproject_axi_exit35_proc();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > out_local_V_data_0_V_blk_n;
sc_signal< sc_logic > out_local_V_data_1_V_blk_n;
sc_signal< sc_logic > out_local_V_data_2_V_blk_n;
sc_signal< sc_logic > out_local_V_data_3_V_blk_n;
sc_signal< sc_logic > out_local_V_data_4_V_blk_n;
sc_signal< sc_logic > out_local_V_data_5_V_blk_n;
sc_signal< sc_logic > out_local_V_data_6_V_blk_n;
sc_signal< sc_logic > out_local_V_data_7_V_blk_n;
sc_signal< sc_logic > out_local_V_data_8_V_blk_n;
sc_signal< sc_logic > out_local_V_data_9_V_blk_n;
sc_signal< sc_logic > io_acc_block_signal_op12;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<16> > tmp_data_V_0_preg;
sc_signal< sc_lv<16> > tmp_data_V_1_preg;
sc_signal< sc_lv<16> > tmp_data_V_2_preg;
sc_signal< sc_lv<16> > tmp_data_V_3_preg;
sc_signal< sc_lv<16> > tmp_data_V_4_preg;
sc_signal< sc_lv<16> > tmp_data_V_5_preg;
sc_signal< sc_lv<16> > tmp_data_V_6_preg;
sc_signal< sc_lv<16> > tmp_data_V_7_preg;
sc_signal< sc_lv<16> > tmp_data_V_8_preg;
sc_signal< sc_lv<16> > tmp_data_V_9_preg;
sc_signal< sc_lv<1> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_fsm_state1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<16> ap_const_lv16_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_block_state1();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_io_acc_block_signal_op12();
void thread_out_local_V_data_0_V_blk_n();
void thread_out_local_V_data_0_V_read();
void thread_out_local_V_data_1_V_blk_n();
void thread_out_local_V_data_1_V_read();
void thread_out_local_V_data_2_V_blk_n();
void thread_out_local_V_data_2_V_read();
void thread_out_local_V_data_3_V_blk_n();
void thread_out_local_V_data_3_V_read();
void thread_out_local_V_data_4_V_blk_n();
void thread_out_local_V_data_4_V_read();
void thread_out_local_V_data_5_V_blk_n();
void thread_out_local_V_data_5_V_read();
void thread_out_local_V_data_6_V_blk_n();
void thread_out_local_V_data_6_V_read();
void thread_out_local_V_data_7_V_blk_n();
void thread_out_local_V_data_7_V_read();
void thread_out_local_V_data_8_V_blk_n();
void thread_out_local_V_data_8_V_read();
void thread_out_local_V_data_9_V_blk_n();
void thread_out_local_V_data_9_V_read();
void thread_tmp_data_V_0();
void thread_tmp_data_V_0_ap_vld();
void thread_tmp_data_V_1();
void thread_tmp_data_V_1_ap_vld();
void thread_tmp_data_V_2();
void thread_tmp_data_V_2_ap_vld();
void thread_tmp_data_V_3();
void thread_tmp_data_V_3_ap_vld();
void thread_tmp_data_V_4();
void thread_tmp_data_V_4_ap_vld();
void thread_tmp_data_V_5();
void thread_tmp_data_V_5_ap_vld();
void thread_tmp_data_V_6();
void thread_tmp_data_V_6_ap_vld();
void thread_tmp_data_V_7();
void thread_tmp_data_V_7_ap_vld();
void thread_tmp_data_V_8();
void thread_tmp_data_V_8_ap_vld();
void thread_tmp_data_V_9();
void thread_tmp_data_V_9_ap_vld();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
#ifndef IMG_TRANSMITER_HPP
#define IMG_TRANSMITER_HPP
#include <systemc.h>
#include "address_map.hpp"
SC_MODULE(img_transmiter)
{
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_TRANSMITER_HPP
|
/*
This file is part of wireworld_systemc
Copyright (C) 2015 Julien Thevenon ( julien_thevenon at yahoo.fr )
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>
*/
#ifndef TOP_H
#define TOP_H
#include "systemc.h"
#include "wireworld.h"
namespace wireworld_systemc
{
class top: public sc_module
{
public:
top(sc_module_name p_name,
const std::vector<std::pair<uint32_t,uint32_t> > & p_copper_cells,
const std::vector<std::pair<uint32_t,uint32_t> > & p_tail_cells,
const std::vector<std::pair<uint32_t,uint32_t> > & p_electron_cells,
const wireworld_common::wireworld_configuration & p_conf,
const uint32_t & p_x_max,
const uint32_t & p_y_max,
const wireworld_common::wireworld_types::t_cell_list & p_inactive_cells,
const wireworld_common::wireworld_types::t_neighbours & p_neighbours);
private:
sc_clock m_clk;
wireworld m_wireworld;
};
//----------------------------------------------------------------------------
top::top(sc_module_name p_name,
const std::vector<std::pair<uint32_t,uint32_t> > & p_copper_cells,
const std::vector<std::pair<uint32_t,uint32_t> > & p_tail_cells,
const std::vector<std::pair<uint32_t,uint32_t> > & p_electron_cells,
const wireworld_common::wireworld_configuration & p_conf,
const uint32_t & p_x_max,
const uint32_t & p_y_max,
const wireworld_common::wireworld_types::t_cell_list & p_inactive_cells,
const wireworld_common::wireworld_types::t_neighbours & p_neighbours):
sc_module(p_name),
m_clk("clk",10.0,SC_NS,0.5,5.0,SC_NS,true),
m_wireworld("wireworld",p_copper_cells,p_tail_cells,p_electron_cells,p_conf,p_x_max,p_y_max,p_inactive_cells,p_neighbours)
{
m_wireworld.m_clk(m_clk);
}
}
#endif // TOP_H
//EOF
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _PmodHYGRO_xlconstant_0_0_H_
#define _PmodHYGRO_xlconstant_0_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class PmodHYGRO_xlconstant_0_0 : public sc_module {
public:
xlconstant_v1_1_7<2,0> mod;
sc_out< sc_bv<2> > dout;
PmodHYGRO_xlconstant_0_0 (sc_core::sc_module_name name);
};
#endif
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
#ifndef PACKET_H
#define PACKET_H
#include <vector>
using std::vector;
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
class packet {
public:
short cmd;
int addr;
vector<char> data;
};
//------------------------------------------------------------------------------
// Begin UVMC-specific code
#include "uvmc.h"
using namespace uvmc;
UVMC_UTILS_3 (packet,cmd,addr,data)
#endif // PACKET_H
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_15_0_H_
#define _icyradio_GND_15_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_15_0 : public sc_module {
public:
xlconstant_v1_1_8<5,0> mod;
sc_out< sc_bv<5> > dout;
icyradio_GND_15_0 (sc_core::sc_module_name name);
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _DoMemInit_HH_
#define _DoMemInit_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct DoMemInit : public sc_module {
// Port declarations 1156
sc_in< sc_lv<32> > targetLayer;
sc_in< sc_lv<32> > targetMem;
sc_in< sc_lv<32> > targetInd;
sc_in< sc_lv<64> > val_V;
sc_out< sc_lv<9> > weights0_m_weights_V_address0;
sc_out< sc_logic > weights0_m_weights_V_ce0;
sc_out< sc_logic > weights0_m_weights_V_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_1_address0;
sc_out< sc_logic > weights0_m_weights_V_1_ce0;
sc_out< sc_logic > weights0_m_weights_V_1_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_1_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_2_address0;
sc_out< sc_logic > weights0_m_weights_V_2_ce0;
sc_out< sc_logic > weights0_m_weights_V_2_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_2_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_3_address0;
sc_out< sc_logic > weights0_m_weights_V_3_ce0;
sc_out< sc_logic > weights0_m_weights_V_3_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_3_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_4_address0;
sc_out< sc_logic > weights0_m_weights_V_4_ce0;
sc_out< sc_logic > weights0_m_weights_V_4_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_4_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_5_address0;
sc_out< sc_logic > weights0_m_weights_V_5_ce0;
sc_out< sc_logic > weights0_m_weights_V_5_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_5_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_6_address0;
sc_out< sc_logic > weights0_m_weights_V_6_ce0;
sc_out< sc_logic > weights0_m_weights_V_6_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_6_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_7_address0;
sc_out< sc_logic > weights0_m_weights_V_7_ce0;
sc_out< sc_logic > weights0_m_weights_V_7_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_7_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_8_address0;
sc_out< sc_logic > weights0_m_weights_V_8_ce0;
sc_out< sc_logic > weights0_m_weights_V_8_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_8_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_9_address0;
sc_out< sc_logic > weights0_m_weights_V_9_ce0;
sc_out< sc_logic > weights0_m_weights_V_9_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_9_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_10_address0;
sc_out< sc_logic > weights0_m_weights_V_10_ce0;
sc_out< sc_logic > weights0_m_weights_V_10_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_10_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_11_address0;
sc_out< sc_logic > weights0_m_weights_V_11_ce0;
sc_out< sc_logic > weights0_m_weights_V_11_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_11_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_12_address0;
sc_out< sc_logic > weights0_m_weights_V_12_ce0;
sc_out< sc_logic > weights0_m_weights_V_12_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_12_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_13_address0;
sc_out< sc_logic > weights0_m_weights_V_13_ce0;
sc_out< sc_logic > weights0_m_weights_V_13_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_13_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_14_address0;
sc_out< sc_logic > weights0_m_weights_V_14_ce0;
sc_out< sc_logic > weights0_m_weights_V_14_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_14_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_15_address0;
sc_out< sc_logic > weights0_m_weights_V_15_ce0;
sc_out< sc_logic > weights0_m_weights_V_15_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_15_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_16_address0;
sc_out< sc_logic > weights0_m_weights_V_16_ce0;
sc_out< sc_logic > weights0_m_weights_V_16_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_16_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_17_address0;
sc_out< sc_logic > weights0_m_weights_V_17_ce0;
sc_out< sc_logic > weights0_m_weights_V_17_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_17_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_18_address0;
sc_out< sc_logic > weights0_m_weights_V_18_ce0;
sc_out< sc_logic > weights0_m_weights_V_18_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_18_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_19_address0;
sc_out< sc_logic > weights0_m_weights_V_19_ce0;
sc_out< sc_logic > weights0_m_weights_V_19_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_19_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_20_address0;
sc_out< sc_logic > weights0_m_weights_V_20_ce0;
sc_out< sc_logic > weights0_m_weights_V_20_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_20_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_21_address0;
sc_out< sc_logic > weights0_m_weights_V_21_ce0;
sc_out< sc_logic > weights0_m_weights_V_21_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_21_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_22_address0;
sc_out< sc_logic > weights0_m_weights_V_22_ce0;
sc_out< sc_logic > weights0_m_weights_V_22_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_22_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_23_address0;
sc_out< sc_logic > weights0_m_weights_V_23_ce0;
sc_out< sc_logic > weights0_m_weights_V_23_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_23_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_24_address0;
sc_out< sc_logic > weights0_m_weights_V_24_ce0;
sc_out< sc_logic > weights0_m_weights_V_24_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_24_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_25_address0;
sc_out< sc_logic > weights0_m_weights_V_25_ce0;
sc_out< sc_logic > weights0_m_weights_V_25_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_25_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_26_address0;
sc_out< sc_logic > weights0_m_weights_V_26_ce0;
sc_out< sc_logic > weights0_m_weights_V_26_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_26_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_27_address0;
sc_out< sc_logic > weights0_m_weights_V_27_ce0;
sc_out< sc_logic > weights0_m_weights_V_27_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_27_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_28_address0;
sc_out< sc_logic > weights0_m_weights_V_28_ce0;
sc_out< sc_logic > weights0_m_weights_V_28_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_28_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_29_address0;
sc_out< sc_logic > weights0_m_weights_V_29_ce0;
sc_out< sc_logic > weights0_m_weights_V_29_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_29_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_30_address0;
sc_out< sc_logic > weights0_m_weights_V_30_ce0;
sc_out< sc_logic > weights0_m_weights_V_30_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_30_d0;
sc_out< sc_lv<9> > weights0_m_weights_V_31_address0;
sc_out< sc_logic > weights0_m_weights_V_31_ce0;
sc_out< sc_logic > weights0_m_weights_V_31_we0;
sc_out< sc_lv<64> > weights0_m_weights_V_31_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_31_address0;
sc_out< sc_logic > threshs0_m_threshold_31_ce0;
sc_out< sc_logic > threshs0_m_threshold_31_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_31_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_30_address0;
sc_out< sc_logic > threshs0_m_threshold_30_ce0;
sc_out< sc_logic > threshs0_m_threshold_30_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_30_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_19_address0;
sc_out< sc_logic > threshs0_m_threshold_19_ce0;
sc_out< sc_logic > threshs0_m_threshold_19_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_19_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_8_address0;
sc_out< sc_logic > threshs0_m_threshold_8_ce0;
sc_out< sc_logic > threshs0_m_threshold_8_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_8_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_5_address0;
sc_out< sc_logic > threshs0_m_threshold_5_ce0;
sc_out< sc_logic > threshs0_m_threshold_5_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_5_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_4_address0;
sc_out< sc_logic > threshs0_m_threshold_4_ce0;
sc_out< sc_logic > threshs0_m_threshold_4_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_4_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_3_address0;
sc_out< sc_logic > threshs0_m_threshold_3_ce0;
sc_out< sc_logic > threshs0_m_threshold_3_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_3_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_2_address0;
sc_out< sc_logic > threshs0_m_threshold_2_ce0;
sc_out< sc_logic > threshs0_m_threshold_2_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_2_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_1_address0;
sc_out< sc_logic > threshs0_m_threshold_1_ce0;
sc_out< sc_logic > threshs0_m_threshold_1_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_1_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_address0;
sc_out< sc_logic > threshs0_m_threshold_ce0;
sc_out< sc_logic > threshs0_m_threshold_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_29_address0;
sc_out< sc_logic > threshs0_m_threshold_29_ce0;
sc_out< sc_logic > threshs0_m_threshold_29_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_29_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_28_address0;
sc_out< sc_logic > threshs0_m_threshold_28_ce0;
sc_out< sc_logic > threshs0_m_threshold_28_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_28_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_27_address0;
sc_out< sc_logic > threshs0_m_threshold_27_ce0;
sc_out< sc_logic > threshs0_m_threshold_27_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_27_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_26_address0;
sc_out< sc_logic > threshs0_m_threshold_26_ce0;
sc_out< sc_logic > threshs0_m_threshold_26_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_26_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_25_address0;
sc_out< sc_logic > threshs0_m_threshold_25_ce0;
sc_out< sc_logic > threshs0_m_threshold_25_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_25_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_24_address0;
sc_out< sc_logic > threshs0_m_threshold_24_ce0;
sc_out< sc_logic > threshs0_m_threshold_24_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_24_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_23_address0;
sc_out< sc_logic > threshs0_m_threshold_23_ce0;
sc_out< sc_logic > threshs0_m_threshold_23_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_23_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_22_address0;
sc_out< sc_logic > threshs0_m_threshold_22_ce0;
sc_out< sc_logic > threshs0_m_threshold_22_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_22_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_21_address0;
sc_out< sc_logic > threshs0_m_threshold_21_ce0;
sc_out< sc_logic > threshs0_m_threshold_21_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_21_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_20_address0;
sc_out< sc_logic > threshs0_m_threshold_20_ce0;
sc_out< sc_logic > threshs0_m_threshold_20_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_20_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_18_address0;
sc_out< sc_logic > threshs0_m_threshold_18_ce0;
sc_out< sc_logic > threshs0_m_threshold_18_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_18_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_17_address0;
sc_out< sc_logic > threshs0_m_threshold_17_ce0;
sc_out< sc_logic > threshs0_m_threshold_17_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_17_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_16_address0;
sc_out< sc_logic > threshs0_m_threshold_16_ce0;
sc_out< sc_logic > threshs0_m_threshold_16_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_16_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_15_address0;
sc_out< sc_logic > threshs0_m_threshold_15_ce0;
sc_out< sc_logic > threshs0_m_threshold_15_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_15_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_14_address0;
sc_out< sc_logic > threshs0_m_threshold_14_ce0;
sc_out< sc_logic > threshs0_m_threshold_14_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_14_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_13_address0;
sc_out< sc_logic > threshs0_m_threshold_13_ce0;
sc_out< sc_logic > threshs0_m_threshold_13_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_13_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_12_address0;
sc_out< sc_logic > threshs0_m_threshold_12_ce0;
sc_out< sc_logic > threshs0_m_threshold_12_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_12_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_11_address0;
sc_out< sc_logic > threshs0_m_threshold_11_ce0;
sc_out< sc_logic > threshs0_m_threshold_11_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_11_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_10_address0;
sc_out< sc_logic > threshs0_m_threshold_10_ce0;
sc_out< sc_logic > threshs0_m_threshold_10_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_10_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_9_address0;
sc_out< sc_logic > threshs0_m_threshold_9_ce0;
sc_out< sc_logic > threshs0_m_threshold_9_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_9_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_7_address0;
sc_out< sc_logic > threshs0_m_threshold_7_ce0;
sc_out< sc_logic > threshs0_m_threshold_7_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_7_d0;
sc_out< sc_lv<5> > threshs0_m_threshold_6_address0;
sc_out< sc_logic > threshs0_m_threshold_6_ce0;
sc_out< sc_logic > threshs0_m_threshold_6_we0;
sc_out< sc_lv<16> > threshs0_m_threshold_6_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_address0;
sc_out< sc_logic > weights1_m_weights_V_ce0;
sc_out< sc_logic > weights1_m_weights_V_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_1_address0;
sc_out< sc_logic > weights1_m_weights_V_1_ce0;
sc_out< sc_logic > weights1_m_weights_V_1_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_1_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_2_address0;
sc_out< sc_logic > weights1_m_weights_V_2_ce0;
sc_out< sc_logic > weights1_m_weights_V_2_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_2_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_3_address0;
sc_out< sc_logic > weights1_m_weights_V_3_ce0;
sc_out< sc_logic > weights1_m_weights_V_3_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_3_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_4_address0;
sc_out< sc_logic > weights1_m_weights_V_4_ce0;
sc_out< sc_logic > weights1_m_weights_V_4_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_4_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_5_address0;
sc_out< sc_logic > weights1_m_weights_V_5_ce0;
sc_out< sc_logic > weights1_m_weights_V_5_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_5_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_6_address0;
sc_out< sc_logic > weights1_m_weights_V_6_ce0;
sc_out< sc_logic > weights1_m_weights_V_6_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_6_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_7_address0;
sc_out< sc_logic > weights1_m_weights_V_7_ce0;
sc_out< sc_logic > weights1_m_weights_V_7_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_7_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_8_address0;
sc_out< sc_logic > weights1_m_weights_V_8_ce0;
sc_out< sc_logic > weights1_m_weights_V_8_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_8_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_9_address0;
sc_out< sc_logic > weights1_m_weights_V_9_ce0;
sc_out< sc_logic > weights1_m_weights_V_9_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_9_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_10_address0;
sc_out< sc_logic > weights1_m_weights_V_10_ce0;
sc_out< sc_logic > weights1_m_weights_V_10_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_10_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_11_address0;
sc_out< sc_logic > weights1_m_weights_V_11_ce0;
sc_out< sc_logic > weights1_m_weights_V_11_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_11_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_12_address0;
sc_out< sc_logic > weights1_m_weights_V_12_ce0;
sc_out< sc_logic > weights1_m_weights_V_12_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_12_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_13_address0;
sc_out< sc_logic > weights1_m_weights_V_13_ce0;
sc_out< sc_logic > weights1_m_weights_V_13_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_13_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_14_address0;
sc_out< sc_logic > weights1_m_weights_V_14_ce0;
sc_out< sc_logic > weights1_m_weights_V_14_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_14_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_15_address0;
sc_out< sc_logic > weights1_m_weights_V_15_ce0;
sc_out< sc_logic > weights1_m_weights_V_15_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_15_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_16_address0;
sc_out< sc_logic > weights1_m_weights_V_16_ce0;
sc_out< sc_logic > weights1_m_weights_V_16_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_16_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_17_address0;
sc_out< sc_logic > weights1_m_weights_V_17_ce0;
sc_out< sc_logic > weights1_m_weights_V_17_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_17_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_18_address0;
sc_out< sc_logic > weights1_m_weights_V_18_ce0;
sc_out< sc_logic > weights1_m_weights_V_18_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_18_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_19_address0;
sc_out< sc_logic > weights1_m_weights_V_19_ce0;
sc_out< sc_logic > weights1_m_weights_V_19_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_19_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_20_address0;
sc_out< sc_logic > weights1_m_weights_V_20_ce0;
sc_out< sc_logic > weights1_m_weights_V_20_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_20_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_21_address0;
sc_out< sc_logic > weights1_m_weights_V_21_ce0;
sc_out< sc_logic > weights1_m_weights_V_21_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_21_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_22_address0;
sc_out< sc_logic > weights1_m_weights_V_22_ce0;
sc_out< sc_logic > weights1_m_weights_V_22_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_22_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_23_address0;
sc_out< sc_logic > weights1_m_weights_V_23_ce0;
sc_out< sc_logic > weights1_m_weights_V_23_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_23_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_24_address0;
sc_out< sc_logic > weights1_m_weights_V_24_ce0;
sc_out< sc_logic > weights1_m_weights_V_24_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_24_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_25_address0;
sc_out< sc_logic > weights1_m_weights_V_25_ce0;
sc_out< sc_logic > weights1_m_weights_V_25_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_25_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_26_address0;
sc_out< sc_logic > weights1_m_weights_V_26_ce0;
sc_out< sc_logic > weights1_m_weights_V_26_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_26_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_27_address0;
sc_out< sc_logic > weights1_m_weights_V_27_ce0;
sc_out< sc_logic > weights1_m_weights_
|
V_27_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_27_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_28_address0;
sc_out< sc_logic > weights1_m_weights_V_28_ce0;
sc_out< sc_logic > weights1_m_weights_V_28_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_28_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_29_address0;
sc_out< sc_logic > weights1_m_weights_V_29_ce0;
sc_out< sc_logic > weights1_m_weights_V_29_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_29_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_30_address0;
sc_out< sc_logic > weights1_m_weights_V_30_ce0;
sc_out< sc_logic > weights1_m_weights_V_30_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_30_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_31_address0;
sc_out< sc_logic > weights1_m_weights_V_31_ce0;
sc_out< sc_logic > weights1_m_weights_V_31_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_31_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_32_address0;
sc_out< sc_logic > weights1_m_weights_V_32_ce0;
sc_out< sc_logic > weights1_m_weights_V_32_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_32_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_33_address0;
sc_out< sc_logic > weights1_m_weights_V_33_ce0;
sc_out< sc_logic > weights1_m_weights_V_33_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_33_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_34_address0;
sc_out< sc_logic > weights1_m_weights_V_34_ce0;
sc_out< sc_logic > weights1_m_weights_V_34_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_34_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_35_address0;
sc_out< sc_logic > weights1_m_weights_V_35_ce0;
sc_out< sc_logic > weights1_m_weights_V_35_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_35_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_36_address0;
sc_out< sc_logic > weights1_m_weights_V_36_ce0;
sc_out< sc_logic > weights1_m_weights_V_36_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_36_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_37_address0;
sc_out< sc_logic > weights1_m_weights_V_37_ce0;
sc_out< sc_logic > weights1_m_weights_V_37_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_37_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_38_address0;
sc_out< sc_logic > weights1_m_weights_V_38_ce0;
sc_out< sc_logic > weights1_m_weights_V_38_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_38_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_39_address0;
sc_out< sc_logic > weights1_m_weights_V_39_ce0;
sc_out< sc_logic > weights1_m_weights_V_39_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_39_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_40_address0;
sc_out< sc_logic > weights1_m_weights_V_40_ce0;
sc_out< sc_logic > weights1_m_weights_V_40_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_40_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_41_address0;
sc_out< sc_logic > weights1_m_weights_V_41_ce0;
sc_out< sc_logic > weights1_m_weights_V_41_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_41_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_42_address0;
sc_out< sc_logic > weights1_m_weights_V_42_ce0;
sc_out< sc_logic > weights1_m_weights_V_42_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_42_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_43_address0;
sc_out< sc_logic > weights1_m_weights_V_43_ce0;
sc_out< sc_logic > weights1_m_weights_V_43_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_43_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_44_address0;
sc_out< sc_logic > weights1_m_weights_V_44_ce0;
sc_out< sc_logic > weights1_m_weights_V_44_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_44_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_45_address0;
sc_out< sc_logic > weights1_m_weights_V_45_ce0;
sc_out< sc_logic > weights1_m_weights_V_45_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_45_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_46_address0;
sc_out< sc_logic > weights1_m_weights_V_46_ce0;
sc_out< sc_logic > weights1_m_weights_V_46_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_46_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_47_address0;
sc_out< sc_logic > weights1_m_weights_V_47_ce0;
sc_out< sc_logic > weights1_m_weights_V_47_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_47_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_48_address0;
sc_out< sc_logic > weights1_m_weights_V_48_ce0;
sc_out< sc_logic > weights1_m_weights_V_48_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_48_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_49_address0;
sc_out< sc_logic > weights1_m_weights_V_49_ce0;
sc_out< sc_logic > weights1_m_weights_V_49_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_49_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_50_address0;
sc_out< sc_logic > weights1_m_weights_V_50_ce0;
sc_out< sc_logic > weights1_m_weights_V_50_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_50_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_51_address0;
sc_out< sc_logic > weights1_m_weights_V_51_ce0;
sc_out< sc_logic > weights1_m_weights_V_51_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_51_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_52_address0;
sc_out< sc_logic > weights1_m_weights_V_52_ce0;
sc_out< sc_logic > weights1_m_weights_V_52_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_52_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_53_address0;
sc_out< sc_logic > weights1_m_weights_V_53_ce0;
sc_out< sc_logic > weights1_m_weights_V_53_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_53_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_54_address0;
sc_out< sc_logic > weights1_m_weights_V_54_ce0;
sc_out< sc_logic > weights1_m_weights_V_54_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_54_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_55_address0;
sc_out< sc_logic > weights1_m_weights_V_55_ce0;
sc_out< sc_logic > weights1_m_weights_V_55_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_55_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_56_address0;
sc_out< sc_logic > weights1_m_weights_V_56_ce0;
sc_out< sc_logic > weights1_m_weights_V_56_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_56_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_57_address0;
sc_out< sc_logic > weights1_m_weights_V_57_ce0;
sc_out< sc_logic > weights1_m_weights_V_57_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_57_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_58_address0;
sc_out< sc_logic > weights1_m_weights_V_58_ce0;
sc_out< sc_logic > weights1_m_weights_V_58_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_58_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_59_address0;
sc_out< sc_logic > weights1_m_weights_V_59_ce0;
sc_out< sc_logic > weights1_m_weights_V_59_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_59_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_60_address0;
sc_out< sc_logic > weights1_m_weights_V_60_ce0;
sc_out< sc_logic > weights1_m_weights_V_60_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_60_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_61_address0;
sc_out< sc_logic > weights1_m_weights_V_61_ce0;
sc_out< sc_logic > weights1_m_weights_V_61_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_61_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_62_address0;
sc_out< sc_logic > weights1_m_weights_V_62_ce0;
sc_out< sc_logic > weights1_m_weights_V_62_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_62_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_63_address0;
sc_out< sc_logic > weights1_m_weights_V_63_ce0;
sc_out< sc_logic > weights1_m_weights_V_63_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_63_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_63_address0;
sc_out< sc_logic > threshs1_m_threshold_63_ce0;
sc_out< sc_logic > threshs1_m_threshold_63_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_63_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_62_address0;
sc_out< sc_logic > threshs1_m_threshold_62_ce0;
sc_out< sc_logic > threshs1_m_threshold_62_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_62_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_51_address0;
sc_out< sc_logic > threshs1_m_threshold_51_ce0;
sc_out< sc_logic > threshs1_m_threshold_51_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_51_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_40_address0;
sc_out< sc_logic > threshs1_m_threshold_40_ce0;
sc_out< sc_logic > threshs1_m_threshold_40_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_40_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_29_address0;
sc_out< sc_logic > threshs1_m_threshold_29_ce0;
sc_out< sc_logic > threshs1_m_threshold_29_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_29_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_18_address0;
sc_out< sc_logic > threshs1_m_threshold_18_ce0;
sc_out< sc_logic > threshs1_m_threshold_18_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_18_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_7_address0;
sc_out< sc_logic > threshs1_m_threshold_7_ce0;
sc_out< sc_logic > threshs1_m_threshold_7_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_7_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_2_address0;
sc_out< sc_logic > threshs1_m_threshold_2_ce0;
sc_out< sc_logic > threshs1_m_threshold_2_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_2_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_1_address0;
sc_out< sc_logic > threshs1_m_threshold_1_ce0;
sc_out< sc_logic > threshs1_m_threshold_1_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_1_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_address0;
sc_out< sc_logic > threshs1_m_threshold_ce0;
sc_out< sc_logic > threshs1_m_threshold_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_61_address0;
sc_out< sc_logic > threshs1_m_threshold_61_ce0;
sc_out< sc_logic > threshs1_m_threshold_61_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_61_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_60_address0;
sc_out< sc_logic > threshs1_m_threshold_60_ce0;
sc_out< sc_logic > threshs1_m_threshold_60_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_60_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_59_address0;
sc_out< sc_logic > threshs1_m_threshold_59_ce0;
sc_out< sc_logic > threshs1_m_threshold_59_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_59_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_58_address0;
sc_out< sc_logic > threshs1_m_threshold_58_ce0;
sc_out< sc_logic > threshs1_m_threshold_58_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_58_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_57_address0;
sc_out< sc_logic > threshs1_m_threshold_57_ce0;
sc_out< sc_logic > threshs1_m_threshold_57_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_57_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_56_address0;
sc_out< sc_logic > threshs1_m_threshold_56_ce0;
sc_out< sc_logic > threshs1_m_threshold_56_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_56_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_55_address0;
sc_out< sc_logic > threshs1_m_threshold_55_ce0;
sc_out< sc_logic > threshs1_m_threshold_55_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_55_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_54_address0;
sc_out< sc_logic > threshs1_m_threshold_54_ce0;
sc_out< sc_logic > threshs1_m_threshold_54_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_54_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_53_address0;
sc_out< sc_logic > threshs1_m_threshold_53_ce0;
sc_out< sc_logic > threshs1_m_threshold_53_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_53_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_52_address0;
sc_out< sc_logic > threshs1_m_threshold_52_ce0;
sc_out< sc_logic > threshs1_m_threshold_52_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_52_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_50_address0;
sc_out< sc_logic > threshs1_m_threshold_50_ce0;
sc_out< sc_logic > threshs1_m_threshold_50_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_50_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_49_address0;
sc_out< sc_logic > threshs1_m_threshold_49_ce0;
sc_out< sc_logic > threshs1_m_threshold_49_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_49_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_48_address0;
sc_out< sc_logic > threshs1_m_threshold_48_ce0;
sc_out< sc_logic > threshs1_m_threshold_48_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_48_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_47_address0;
sc_out< sc_logic > threshs1_m_threshold_47_ce0;
sc_out< sc_logic > threshs1_m_threshold_47_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_47_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_46_address0;
sc_out< sc_logic > threshs1_m_threshold_46_ce0;
sc_out< sc_logic > threshs1_m_threshold_46_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_46_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_45_address0;
sc_out< sc_logic > threshs1_m_threshold_45_ce0;
sc_out< sc_logic > threshs1_m_threshold_45_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_45_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_44_address0;
sc_out< sc_logic > threshs1_m_threshold_44_ce0;
sc_out< sc_logic > threshs1_m_threshold_44_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_44_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_43_address0;
sc_out< sc_logic > threshs1_m_threshold_43_ce0;
sc_out< sc_logic > threshs1_m_threshold_43_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_43_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_42_address0;
sc_out< sc_logic > threshs1_m_threshold_42_ce0;
sc_out< sc_logic > threshs1_m_threshold_42_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_42_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_41_address0;
sc_out< sc_logic > threshs1_m_threshold_41_ce0;
sc_out< sc_logic > threshs1_m_threshold_41_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_41_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_39_address0;
sc_out< sc_logic > threshs1_m_threshold_39_ce0;
sc_out< sc_logic > threshs1_m_threshold_39_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_39_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_38_address0;
sc_out< sc_logic > threshs1_m_threshold_38_ce0;
sc_out< sc_logic > threshs1_m_threshold_38_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_38_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_37_address0;
sc_out< sc_logic > threshs1_m_threshold_37_ce0;
sc_out< sc_logic > threshs1_m_threshold_37_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_37_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_36_address0;
sc_out< sc_logic > threshs1_m_threshold_36_ce0;
sc_out< sc_logic > threshs1_m_threshold_36_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_36_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_35_address0;
sc_out< sc_logic > threshs1_m_threshold_35_ce0;
sc_out< sc_logic > threshs1_m_threshold_35_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_35_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_34_address0;
sc_out< sc_logic > threshs1_m_threshold_34_ce0;
sc_out< sc_logic > threshs1_m_threshold_34_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_34_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_33_address0;
sc_out< sc_logic > threshs1_m_threshold_33_ce0;
sc_out< sc_logic > threshs1_m_threshold_33_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_33_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_32_address0;
sc_out< sc_logic > threshs1_m_threshold_32_ce0;
sc_out< sc_logic > threshs1_m_threshold_32_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_32_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_31_address0;
sc_out< sc_logic > threshs1_m_threshold_31_ce0;
sc_out< sc_logic > threshs1_m_threshold_31_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_31_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_30_address0;
sc_out< sc_logic > threshs1_m_threshold_30_ce0;
sc_out< sc_logic > threshs1_m_threshold_30_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_30_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_28_address0;
sc_out< sc_logic > threshs1_m_threshold_28_ce0;
sc_out< sc_logic > threshs1_m_threshold_28_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_28_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_27_address0;
sc_out< sc_logic > threshs1_m_threshold_27_ce0;
sc_out< sc_logic > threshs1_m_threshold_27_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_27_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_26_address0;
sc_out< sc_logic > threshs1_m_threshold_26_ce0;
sc_out< sc_logic > threshs1_m_threshold_26_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_26_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_25_address0;
sc_out< sc_logic > threshs1_m_threshold_25_ce0;
sc_out< sc_logic > threshs1_m_threshold_25_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_25_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_24_address0;
sc_out< sc_logic > threshs1_m_threshold_24_ce0;
sc_out< sc_logic > threshs1_m_threshold_24_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_24_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_23_address0;
sc_out< sc_logic > threshs1_m_threshold_23_ce0;
sc_out< sc_logic > threshs1_m_threshold_23_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_23_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_22_address0;
sc_out< sc_logic > threshs1_m_threshold_22_ce0;
sc_out< sc_logic > threshs1_m_threshold_22_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_22_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_21_address0;
sc_out< sc_logic > threshs1_m_threshold_21_ce0;
sc_out< sc_logic > threshs1_m_threshold_21_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_21_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_20_address0;
sc_out< sc_logic > threshs1_m_threshold_20_ce0;
sc_out< sc_logic > threshs1_m_threshold_20_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_20_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_19_address0;
sc_out< sc_logic > threshs1_m_threshold_19_ce0;
sc_out< sc_logic > threshs1_m_threshold_19_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_19_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_17_address0;
sc_out< sc_logic > threshs1_m_threshold_17_ce0;
sc_out< sc_logic > threshs1_m_threshold_17_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_17_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_16_address0;
sc_out< sc_logic > threshs1_m_threshold_16_ce0;
sc_out< sc_logic > threshs1_m_threshold_16_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_16_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_15_address0;
sc_out< sc_logic > threshs1_m_threshold_15_ce0;
sc_out< sc_logic > threshs1_m_threshold_15_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_15_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_14_address0;
sc_out< sc_logic > threshs1_m_threshold_14_ce0;
sc_out< sc_logic > threshs1_m_threshold_14_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_14_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_13_address0;
sc_out< sc_logic > threshs1_m_threshold_13_ce0;
sc_out< sc_logic > threshs1_m_threshold_13_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_13_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_12_address0;
sc_out< sc_logic > threshs1_m_threshold_12_ce0;
sc_out< sc_logic > threshs1_m_threshold_12_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_12_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_11_address0;
sc_out< sc_logic > threshs1_m_threshold_11_ce0;
sc_out< sc_logic > threshs1_m_threshold_11_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_11_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_10_address0;
sc_out< sc_logic > threshs1_m_threshold_10_ce0;
sc_out< sc_logic > threshs1_m_threshold_
|
10_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_10_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_9_address0;
sc_out< sc_logic > threshs1_m_threshold_9_ce0;
sc_out< sc_logic > threshs1_m_threshold_9_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_9_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_8_address0;
sc_out< sc_logic > threshs1_m_threshold_8_ce0;
sc_out< sc_logic > threshs1_m_threshold_8_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_8_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_6_address0;
sc_out< sc_logic > threshs1_m_threshold_6_ce0;
sc_out< sc_logic > threshs1_m_threshold_6_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_6_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_5_address0;
sc_out< sc_logic > threshs1_m_threshold_5_ce0;
sc_out< sc_logic > threshs1_m_threshold_5_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_5_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_4_address0;
sc_out< sc_logic > threshs1_m_threshold_4_ce0;
sc_out< sc_logic > threshs1_m_threshold_4_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_4_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_3_address0;
sc_out< sc_logic > threshs1_m_threshold_3_ce0;
sc_out< sc_logic > threshs1_m_threshold_3_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_3_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_address0;
sc_out< sc_logic > weights2_m_weights_V_ce0;
sc_out< sc_logic > weights2_m_weights_V_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_1_address0;
sc_out< sc_logic > weights2_m_weights_V_1_ce0;
sc_out< sc_logic > weights2_m_weights_V_1_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_1_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_2_address0;
sc_out< sc_logic > weights2_m_weights_V_2_ce0;
sc_out< sc_logic > weights2_m_weights_V_2_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_2_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_3_address0;
sc_out< sc_logic > weights2_m_weights_V_3_ce0;
sc_out< sc_logic > weights2_m_weights_V_3_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_3_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_4_address0;
sc_out< sc_logic > weights2_m_weights_V_4_ce0;
sc_out< sc_logic > weights2_m_weights_V_4_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_4_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_5_address0;
sc_out< sc_logic > weights2_m_weights_V_5_ce0;
sc_out< sc_logic > weights2_m_weights_V_5_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_5_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_6_address0;
sc_out< sc_logic > weights2_m_weights_V_6_ce0;
sc_out< sc_logic > weights2_m_weights_V_6_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_6_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_7_address0;
sc_out< sc_logic > weights2_m_weights_V_7_ce0;
sc_out< sc_logic > weights2_m_weights_V_7_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_7_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_8_address0;
sc_out< sc_logic > weights2_m_weights_V_8_ce0;
sc_out< sc_logic > weights2_m_weights_V_8_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_8_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_9_address0;
sc_out< sc_logic > weights2_m_weights_V_9_ce0;
sc_out< sc_logic > weights2_m_weights_V_9_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_9_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_10_address0;
sc_out< sc_logic > weights2_m_weights_V_10_ce0;
sc_out< sc_logic > weights2_m_weights_V_10_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_10_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_11_address0;
sc_out< sc_logic > weights2_m_weights_V_11_ce0;
sc_out< sc_logic > weights2_m_weights_V_11_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_11_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_12_address0;
sc_out< sc_logic > weights2_m_weights_V_12_ce0;
sc_out< sc_logic > weights2_m_weights_V_12_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_12_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_13_address0;
sc_out< sc_logic > weights2_m_weights_V_13_ce0;
sc_out< sc_logic > weights2_m_weights_V_13_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_13_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_14_address0;
sc_out< sc_logic > weights2_m_weights_V_14_ce0;
sc_out< sc_logic > weights2_m_weights_V_14_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_14_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_15_address0;
sc_out< sc_logic > weights2_m_weights_V_15_ce0;
sc_out< sc_logic > weights2_m_weights_V_15_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_15_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_16_address0;
sc_out< sc_logic > weights2_m_weights_V_16_ce0;
sc_out< sc_logic > weights2_m_weights_V_16_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_16_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_17_address0;
sc_out< sc_logic > weights2_m_weights_V_17_ce0;
sc_out< sc_logic > weights2_m_weights_V_17_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_17_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_18_address0;
sc_out< sc_logic > weights2_m_weights_V_18_ce0;
sc_out< sc_logic > weights2_m_weights_V_18_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_18_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_19_address0;
sc_out< sc_logic > weights2_m_weights_V_19_ce0;
sc_out< sc_logic > weights2_m_weights_V_19_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_19_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_20_address0;
sc_out< sc_logic > weights2_m_weights_V_20_ce0;
sc_out< sc_logic > weights2_m_weights_V_20_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_20_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_21_address0;
sc_out< sc_logic > weights2_m_weights_V_21_ce0;
sc_out< sc_logic > weights2_m_weights_V_21_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_21_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_22_address0;
sc_out< sc_logic > weights2_m_weights_V_22_ce0;
sc_out< sc_logic > weights2_m_weights_V_22_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_22_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_23_address0;
sc_out< sc_logic > weights2_m_weights_V_23_ce0;
sc_out< sc_logic > weights2_m_weights_V_23_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_23_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_24_address0;
sc_out< sc_logic > weights2_m_weights_V_24_ce0;
sc_out< sc_logic > weights2_m_weights_V_24_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_24_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_25_address0;
sc_out< sc_logic > weights2_m_weights_V_25_ce0;
sc_out< sc_logic > weights2_m_weights_V_25_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_25_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_26_address0;
sc_out< sc_logic > weights2_m_weights_V_26_ce0;
sc_out< sc_logic > weights2_m_weights_V_26_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_26_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_27_address0;
sc_out< sc_logic > weights2_m_weights_V_27_ce0;
sc_out< sc_logic > weights2_m_weights_V_27_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_27_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_28_address0;
sc_out< sc_logic > weights2_m_weights_V_28_ce0;
sc_out< sc_logic > weights2_m_weights_V_28_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_28_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_29_address0;
sc_out< sc_logic > weights2_m_weights_V_29_ce0;
sc_out< sc_logic > weights2_m_weights_V_29_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_29_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_30_address0;
sc_out< sc_logic > weights2_m_weights_V_30_ce0;
sc_out< sc_logic > weights2_m_weights_V_30_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_30_d0;
sc_out< sc_lv<9> > weights2_m_weights_V_31_address0;
sc_out< sc_logic > weights2_m_weights_V_31_ce0;
sc_out< sc_logic > weights2_m_weights_V_31_we0;
sc_out< sc_lv<64> > weights2_m_weights_V_31_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_31_address0;
sc_out< sc_logic > threshs2_m_threshold_31_ce0;
sc_out< sc_logic > threshs2_m_threshold_31_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_31_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_30_address0;
sc_out< sc_logic > threshs2_m_threshold_30_ce0;
sc_out< sc_logic > threshs2_m_threshold_30_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_30_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_19_address0;
sc_out< sc_logic > threshs2_m_threshold_19_ce0;
sc_out< sc_logic > threshs2_m_threshold_19_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_19_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_8_address0;
sc_out< sc_logic > threshs2_m_threshold_8_ce0;
sc_out< sc_logic > threshs2_m_threshold_8_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_8_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_5_address0;
sc_out< sc_logic > threshs2_m_threshold_5_ce0;
sc_out< sc_logic > threshs2_m_threshold_5_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_5_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_4_address0;
sc_out< sc_logic > threshs2_m_threshold_4_ce0;
sc_out< sc_logic > threshs2_m_threshold_4_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_4_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_3_address0;
sc_out< sc_logic > threshs2_m_threshold_3_ce0;
sc_out< sc_logic > threshs2_m_threshold_3_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_3_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_2_address0;
sc_out< sc_logic > threshs2_m_threshold_2_ce0;
sc_out< sc_logic > threshs2_m_threshold_2_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_2_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_1_address0;
sc_out< sc_logic > threshs2_m_threshold_1_ce0;
sc_out< sc_logic > threshs2_m_threshold_1_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_1_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_address0;
sc_out< sc_logic > threshs2_m_threshold_ce0;
sc_out< sc_logic > threshs2_m_threshold_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_29_address0;
sc_out< sc_logic > threshs2_m_threshold_29_ce0;
sc_out< sc_logic > threshs2_m_threshold_29_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_29_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_28_address0;
sc_out< sc_logic > threshs2_m_threshold_28_ce0;
sc_out< sc_logic > threshs2_m_threshold_28_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_28_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_27_address0;
sc_out< sc_logic > threshs2_m_threshold_27_ce0;
sc_out< sc_logic > threshs2_m_threshold_27_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_27_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_26_address0;
sc_out< sc_logic > threshs2_m_threshold_26_ce0;
sc_out< sc_logic > threshs2_m_threshold_26_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_26_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_25_address0;
sc_out< sc_logic > threshs2_m_threshold_25_ce0;
sc_out< sc_logic > threshs2_m_threshold_25_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_25_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_24_address0;
sc_out< sc_logic > threshs2_m_threshold_24_ce0;
sc_out< sc_logic > threshs2_m_threshold_24_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_24_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_23_address0;
sc_out< sc_logic > threshs2_m_threshold_23_ce0;
sc_out< sc_logic > threshs2_m_threshold_23_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_23_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_22_address0;
sc_out< sc_logic > threshs2_m_threshold_22_ce0;
sc_out< sc_logic > threshs2_m_threshold_22_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_22_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_21_address0;
sc_out< sc_logic > threshs2_m_threshold_21_ce0;
sc_out< sc_logic > threshs2_m_threshold_21_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_21_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_20_address0;
sc_out< sc_logic > threshs2_m_threshold_20_ce0;
sc_out< sc_logic > threshs2_m_threshold_20_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_20_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_18_address0;
sc_out< sc_logic > threshs2_m_threshold_18_ce0;
sc_out< sc_logic > threshs2_m_threshold_18_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_18_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_17_address0;
sc_out< sc_logic > threshs2_m_threshold_17_ce0;
sc_out< sc_logic > threshs2_m_threshold_17_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_17_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_16_address0;
sc_out< sc_logic > threshs2_m_threshold_16_ce0;
sc_out< sc_logic > threshs2_m_threshold_16_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_16_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_15_address0;
sc_out< sc_logic > threshs2_m_threshold_15_ce0;
sc_out< sc_logic > threshs2_m_threshold_15_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_15_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_14_address0;
sc_out< sc_logic > threshs2_m_threshold_14_ce0;
sc_out< sc_logic > threshs2_m_threshold_14_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_14_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_13_address0;
sc_out< sc_logic > threshs2_m_threshold_13_ce0;
sc_out< sc_logic > threshs2_m_threshold_13_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_13_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_12_address0;
sc_out< sc_logic > threshs2_m_threshold_12_ce0;
sc_out< sc_logic > threshs2_m_threshold_12_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_12_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_11_address0;
sc_out< sc_logic > threshs2_m_threshold_11_ce0;
sc_out< sc_logic > threshs2_m_threshold_11_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_11_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_10_address0;
sc_out< sc_logic > threshs2_m_threshold_10_ce0;
sc_out< sc_logic > threshs2_m_threshold_10_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_10_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_9_address0;
sc_out< sc_logic > threshs2_m_threshold_9_ce0;
sc_out< sc_logic > threshs2_m_threshold_9_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_9_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_7_address0;
sc_out< sc_logic > threshs2_m_threshold_7_ce0;
sc_out< sc_logic > threshs2_m_threshold_7_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_7_d0;
sc_out< sc_lv<5> > threshs2_m_threshold_6_address0;
sc_out< sc_logic > threshs2_m_threshold_6_ce0;
sc_out< sc_logic > threshs2_m_threshold_6_we0;
sc_out< sc_lv<16> > threshs2_m_threshold_6_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_address0;
sc_out< sc_logic > weights3_m_weights_V_ce0;
sc_out< sc_logic > weights3_m_weights_V_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_1_address0;
sc_out< sc_logic > weights3_m_weights_V_1_ce0;
sc_out< sc_logic > weights3_m_weights_V_1_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_1_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_2_address0;
sc_out< sc_logic > weights3_m_weights_V_2_ce0;
sc_out< sc_logic > weights3_m_weights_V_2_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_2_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_3_address0;
sc_out< sc_logic > weights3_m_weights_V_3_ce0;
sc_out< sc_logic > weights3_m_weights_V_3_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_3_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_4_address0;
sc_out< sc_logic > weights3_m_weights_V_4_ce0;
sc_out< sc_logic > weights3_m_weights_V_4_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_4_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_5_address0;
sc_out< sc_logic > weights3_m_weights_V_5_ce0;
sc_out< sc_logic > weights3_m_weights_V_5_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_5_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_6_address0;
sc_out< sc_logic > weights3_m_weights_V_6_ce0;
sc_out< sc_logic > weights3_m_weights_V_6_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_6_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_7_address0;
sc_out< sc_logic > weights3_m_weights_V_7_ce0;
sc_out< sc_logic > weights3_m_weights_V_7_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_7_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_8_address0;
sc_out< sc_logic > weights3_m_weights_V_8_ce0;
sc_out< sc_logic > weights3_m_weights_V_8_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_8_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_9_address0;
sc_out< sc_logic > weights3_m_weights_V_9_ce0;
sc_out< sc_logic > weights3_m_weights_V_9_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_9_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_10_address0;
sc_out< sc_logic > weights3_m_weights_V_10_ce0;
sc_out< sc_logic > weights3_m_weights_V_10_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_10_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_11_address0;
sc_out< sc_logic > weights3_m_weights_V_11_ce0;
sc_out< sc_logic > weights3_m_weights_V_11_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_11_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_12_address0;
sc_out< sc_logic > weights3_m_weights_V_12_ce0;
sc_out< sc_logic > weights3_m_weights_V_12_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_12_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_13_address0;
sc_out< sc_logic > weights3_m_weights_V_13_ce0;
sc_out< sc_logic > weights3_m_weights_V_13_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_13_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_14_address0;
sc_out< sc_logic > weights3_m_weights_V_14_ce0;
sc_out< sc_logic > weights3_m_weights_V_14_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_14_d0;
sc_out< sc_lv<9> > weights3_m_weights_V_15_address0;
sc_out< sc_logic > weights3_m_weights_V_15_ce0;
sc_out< sc_logic > weights3_m_weights_V_15_we0;
sc_out< sc_lv<8> > weights3_m_weights_V_15_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_15_address0;
sc_out< sc_logic > threshs3_m_threshold_15_ce0;
sc_out< sc_logic > threshs3_m_threshold_15_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_15_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_14_address0;
sc_out< sc_logic > threshs3_m_threshold_14_ce0;
sc_out< sc_logic > threshs3_m_threshold_14_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_14_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_7_address0;
sc_out< sc_logic > threshs3_m_threshold_7_ce0;
sc_out< sc_logic > threshs3_m_threshold_7_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_7_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_6_address0;
sc_out< sc_logic > threshs3_m_threshold_6_ce0;
sc_out< sc_logic > threshs3_m_threshold_6_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_6_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_5_address0;
sc_out< sc_logic > threshs3_m_threshold_5_ce0;
sc_out< sc_logic > threshs3_m_threshold_5_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_5_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_4_address0;
sc_out< sc_logic > threshs3_m_threshold_4_ce0;
sc_out< sc_logic > threshs3_m_threshold_4_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_4_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_3_address0;
sc_out< sc_logic > threshs3_m_threshold_3_ce0;
sc_out< sc_logic > threshs3_m_threshold_3_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_3_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_2_address0;
sc_out< sc_logic > threshs3_m_threshold_2_ce0;
sc_out< sc_logic > threshs3_m_threshold_2_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_2_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_1_address0;
sc_out< sc_logic > threshs3_m_threshold_1_ce0;
sc_out< sc_logi
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c > threshs3_m_threshold_1_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_1_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_address0;
sc_out< sc_logic > threshs3_m_threshold_ce0;
sc_out< sc_logic > threshs3_m_threshold_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_13_address0;
sc_out< sc_logic > threshs3_m_threshold_13_ce0;
sc_out< sc_logic > threshs3_m_threshold_13_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_13_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_12_address0;
sc_out< sc_logic > threshs3_m_threshold_12_ce0;
sc_out< sc_logic > threshs3_m_threshold_12_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_12_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_11_address0;
sc_out< sc_logic > threshs3_m_threshold_11_ce0;
sc_out< sc_logic > threshs3_m_threshold_11_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_11_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_10_address0;
sc_out< sc_logic > threshs3_m_threshold_10_ce0;
sc_out< sc_logic > threshs3_m_threshold_10_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_10_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_9_address0;
sc_out< sc_logic > threshs3_m_threshold_9_ce0;
sc_out< sc_logic > threshs3_m_threshold_9_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_9_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_8_address0;
sc_out< sc_logic > threshs3_m_threshold_8_ce0;
sc_out< sc_logic > threshs3_m_threshold_8_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_8_d0;
// Module declarations
DoMemInit(sc_module_name name);
SC_HAS_PROCESS(DoMemInit);
~DoMemInit();
sc_trace_file* mVcdFile;
sc_signal< sc_lv<64> > tmp_6_fu_4368_p1;
sc_signal< sc_lv<32> > targetLayer_read_read_fu_842_p2;
sc_signal< sc_lv<64> > tmp_5_fu_4412_p1;
sc_signal< sc_lv<64> > tmp_4_fu_4456_p1;
sc_signal< sc_lv<64> > tmp_3_fu_4532_p1;
sc_signal< sc_lv<64> > tmp_2_fu_4572_p1;
sc_signal< sc_lv<64> > tmp_1_fu_4712_p1;
sc_signal< sc_lv<64> > tmp_s_fu_4852_p1;
sc_signal< sc_lv<64> > tmp_fu_4928_p1;
sc_signal< sc_lv<4> > tmp_8415_fu_4408_p1;
sc_signal< sc_lv<16> > tmp_8414_fu_4388_p1;
sc_signal< sc_lv<4> > tmp_8413_fu_4452_p1;
sc_signal< sc_lv<8> > tmp_8412_fu_4432_p1;
sc_signal< sc_lv<5> > tmp_8411_fu_4528_p1;
sc_signal< sc_lv<16> > tmp_8410_fu_4492_p1;
sc_signal< sc_lv<5> > tmp_8409_fu_4568_p1;
sc_signal< sc_lv<6> > tmp_8408_fu_4708_p1;
sc_signal< sc_lv<16> > tmp_8407_fu_4640_p1;
sc_signal< sc_lv<6> > tmp_8406_fu_4848_p1;
sc_signal< sc_lv<32> > tmp_8405_fu_4780_p1;
sc_signal< sc_lv<5> > tmp_8404_fu_4924_p1;
sc_signal< sc_lv<16> > tmp_8403_fu_4888_p1;
sc_signal< sc_lv<5> > tmp_8402_fu_4964_p1;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_logic ap_const_logic_0;
static const sc_logic ap_const_logic_1;
static const sc_lv<4> ap_const_lv4_E;
static const sc_lv<4> ap_const_lv4_D;
static const sc_lv<4> ap_const_lv4_C;
static const sc_lv<4> ap_const_lv4_B;
static const sc_lv<4> ap_const_lv4_A;
static const sc_lv<4> ap_const_lv4_9;
static const sc_lv<4> ap_const_lv4_8;
static const sc_lv<4> ap_const_lv4_7;
static const sc_lv<4> ap_const_lv4_6;
static const sc_lv<4> ap_const_lv4_5;
static const sc_lv<4> ap_const_lv4_4;
static const sc_lv<4> ap_const_lv4_3;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<4> ap_const_lv4_F;
static const sc_lv<5> ap_const_lv5_1E;
static const sc_lv<5> ap_const_lv5_1D;
static const sc_lv<5> ap_const_lv5_1C;
static const sc_lv<5> ap_const_lv5_1B;
static const sc_lv<5> ap_const_lv5_1A;
static const sc_lv<5> ap_const_lv5_19;
static const sc_lv<5> ap_const_lv5_18;
static const sc_lv<5> ap_const_lv5_17;
static const sc_lv<5> ap_const_lv5_16;
static const sc_lv<5> ap_const_lv5_15;
static const sc_lv<5> ap_const_lv5_14;
static const sc_lv<5> ap_const_lv5_13;
static const sc_lv<5> ap_const_lv5_12;
static const sc_lv<5> ap_const_lv5_11;
static const sc_lv<5> ap_const_lv5_10;
static const sc_lv<5> ap_const_lv5_F;
static const sc_lv<5> ap_const_lv5_E;
static const sc_lv<5> ap_const_lv5_D;
static const sc_lv<5> ap_const_lv5_C;
static const sc_lv<5> ap_const_lv5_B;
static const sc_lv<5> ap_const_lv5_A;
static const sc_lv<5> ap_const_lv5_9;
static const sc_lv<5> ap_const_lv5_8;
static const sc_lv<5> ap_const_lv5_7;
static const sc_lv<5> ap_const_lv5_6;
static const sc_lv<5> ap_const_lv5_5;
static const sc_lv<5> ap_const_lv5_4;
static const sc_lv<5> ap_const_lv5_3;
static const sc_lv<5> ap_const_lv5_2;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<5> ap_const_lv5_1F;
static const sc_lv<6> ap_const_lv6_3E;
static const sc_lv<6> ap_const_lv6_3D;
static const sc_lv<6> ap_const_lv6_3C;
static const sc_lv<6> ap_const_lv6_3B;
static const sc_lv<6> ap_const_lv6_3A;
static const sc_lv<6> ap_const_lv6_39;
static const sc_lv<6> ap_const_lv6_38;
static const sc_lv<6> ap_const_lv6_37;
static const sc_lv<6> ap_const_lv6_36;
static const sc_lv<6> ap_const_lv6_35;
static const sc_lv<6> ap_const_lv6_34;
static const sc_lv<6> ap_const_lv6_33;
static const sc_lv<6> ap_const_lv6_32;
static const sc_lv<6> ap_const_lv6_31;
static const sc_lv<6> ap_const_lv6_30;
static const sc_lv<6> ap_const_lv6_2F;
static const sc_lv<6> ap_const_lv6_2E;
static const sc_lv<6> ap_const_lv6_2D;
static const sc_lv<6> ap_const_lv6_2C;
static const sc_lv<6> ap_const_lv6_2B;
static const sc_lv<6> ap_const_lv6_2A;
static const sc_lv<6> ap_const_lv6_29;
static const sc_lv<6> ap_const_lv6_28;
static const sc_lv<6> ap_const_lv6_27;
static const sc_lv<6> ap_const_lv6_26;
static const sc_lv<6> ap_const_lv6_25;
static const sc_lv<6> ap_const_lv6_24;
static const sc_lv<6> ap_const_lv6_23;
static const sc_lv<6> ap_const_lv6_22;
static const sc_lv<6> ap_const_lv6_21;
static const sc_lv<6> ap_const_lv6_20;
static const sc_lv<6> ap_const_lv6_1F;
static const sc_lv<6> ap_const_lv6_1E;
static const sc_lv<6> ap_const_lv6_1D;
static const sc_lv<6> ap_const_lv6_1C;
static const sc_lv<6> ap_const_lv6_1B;
static const sc_lv<6> ap_const_lv6_1A;
static const sc_lv<6> ap_const_lv6_19;
static const sc_lv<6> ap_const_lv6_18;
static const sc_lv<6> ap_const_lv6_17;
static const sc_lv<6> ap_const_lv6_16;
static const sc_lv<6> ap_const_lv6_15;
static const sc_lv<6> ap_const_lv6_14;
static const sc_lv<6> ap_const_lv6_13;
static const sc_lv<6> ap_const_lv6_12;
static const sc_lv<6> ap_const_lv6_11;
static const sc_lv<6> ap_const_lv6_10;
static const sc_lv<6> ap_const_lv6_F;
static const sc_lv<6> ap_const_lv6_E;
static const sc_lv<6> ap_const_lv6_D;
static const sc_lv<6> ap_const_lv6_C;
static const sc_lv<6> ap_const_lv6_B;
static const sc_lv<6> ap_const_lv6_A;
static const sc_lv<6> ap_const_lv6_9;
static const sc_lv<6> ap_const_lv6_8;
static const sc_lv<6> ap_const_lv6_7;
static const sc_lv<6> ap_const_lv6_6;
static const sc_lv<6> ap_const_lv6_5;
static const sc_lv<6> ap_const_lv6_4;
static const sc_lv<6> ap_const_lv6_3;
static const sc_lv<6> ap_const_lv6_2;
static const sc_lv<6> ap_const_lv6_1;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<6> ap_const_lv6_3F;
// Thread declarations
void thread_targetLayer_read_read_fu_842_p2();
void thread_threshs0_m_threshold_10_address0();
void thread_threshs0_m_threshold_10_ce0();
void thread_threshs0_m_threshold_10_d0();
void thread_threshs0_m_threshold_10_we0();
void thread_threshs0_m_threshold_11_address0();
void thread_threshs0_m_threshold_11_ce0();
void thread_threshs0_m_threshold_11_d0();
void thread_threshs0_m_threshold_11_we0();
void thread_threshs0_m_threshold_12_address0();
void thread_threshs0_m_threshold_12_ce0();
void thread_threshs0_m_threshold_12_d0();
void thread_threshs0_m_threshold_12_we0();
void thread_threshs0_m_threshold_13_address0();
void thread_threshs0_m_threshold_13_ce0();
void thread_threshs0_m_threshold_13_d0();
void thread_threshs0_m_threshold_13_we0();
void thread_threshs0_m_threshold_14_address0();
void thread_threshs0_m_threshold_14_ce0();
void thread_threshs0_m_threshold_14_d0();
void thread_threshs0_m_threshold_14_we0();
void thread_threshs0_m_threshold_15_address0();
void thread_threshs0_m_threshold_15_ce0();
void thread_threshs0_m_threshold_15_d0();
void thread_threshs0_m_threshold_15_we0();
void thread_threshs0_m_threshold_16_address0();
void thread_threshs0_m_threshold_16_ce0();
void thread_threshs0_m_threshold_16_d0();
void thread_threshs0_m_threshold_16_we0();
void thread_threshs0_m_threshold_17_address0();
void thread_threshs0_m_threshold_17_ce0();
void thread_threshs0_m_threshold_17_d0();
void thread_threshs0_m_threshold_17_we0();
void thread_threshs0_m_threshold_18_address0();
void thread_threshs0_m_threshold_18_ce0();
void thread_threshs0_m_threshold_18_d0();
void thread_threshs0_m_threshold_18_we0();
void thread_threshs0_m_threshold_19_address0();
void thread_threshs0_m_threshold_19_ce0();
void thread_threshs0_m_threshold_19_d0();
void thread_threshs0_m_threshold_19_we0();
void thread_threshs0_m_threshold_1_address0();
void thread_threshs0_m_threshold_1_ce0();
void thread_threshs0_m_threshold_1_d0();
void thread_threshs0_m_threshold_1_we0();
void thread_threshs0_m_threshold_20_address0();
void thread_threshs0_m_threshold_20_ce0();
void thread_threshs0_m_threshold_20_d0();
void thread_threshs0_m_threshold_20_we0();
void thread_threshs0_m_threshold_21_address0();
void thread_threshs0_m_threshold_21_ce0();
void thread_threshs0_m_threshold_21_d0();
void thread_threshs0_m_threshold_21_we0();
void thread_threshs0_m_threshold_22_address0();
void thread_threshs0_m_threshold_22_ce0();
void thread_threshs0_m_threshold_22_d0();
void thread_threshs0_m_threshold_22_we0();
void thread_threshs0_m_threshold_23_address0();
void thread_threshs0_m_threshold_23_ce0();
void thread_threshs0_m_threshold_23_d0();
void thread_threshs0_m_threshold_23_we0();
void thread_threshs0_m_threshold_24_address0();
void thread_threshs0_m_threshold_24_ce0();
void thread_threshs0_m_threshold_24_d0();
void thread_threshs0_m_threshold_24_we0();
void thread_threshs0_m_threshold_25_address0();
void thread_threshs0_m_threshold_25_ce0();
void thread_threshs0_m_threshold_25_d0();
void thread_threshs0_m_threshold_25_we0();
void thread_threshs0_m_threshold_26_address0();
void thread_threshs0_m_threshold_26_ce0();
void thread_threshs0_m_threshold_26_d0();
void thread_threshs0_m_threshold_26_we0();
void thread_threshs0_m_threshold_27_address0();
void thread_threshs0_m_threshold_27_ce0();
void thread_threshs0_m_threshold_27_d0();
void thread_threshs0_m_threshold_27_we0();
void thread_threshs0_m_threshold_28_address0();
void thread_threshs0_m_threshold_28_ce0();
void thread_threshs0_m_threshold_28_d0();
void thread_threshs0_m_threshold_28_we0();
void thread_threshs0_m_threshold_29_address0();
void thread_threshs0_m_threshold_29_ce0();
void thread_threshs0_m_threshold_29_d0();
void thread_threshs0_m_threshold_29_we0();
void thread_threshs0_m_threshold_2_address0();
void thread_threshs0_m_threshold_2_ce0();
void thread_threshs0_m_threshold_2_d0();
void thread_threshs0_m_threshold_2_we0();
void thread_threshs0_m_threshold_30_address0();
void thread_threshs0_m_threshold_30_ce0();
void thread_threshs0_m_threshold_30_d0();
void thread_threshs0_m_threshold_30_we0();
void thread_threshs0_m_threshold_31_address0();
void thread_threshs0_m_threshold_31_ce0();
void thread_threshs0_m_threshold_31_d0();
void thread_threshs0_m_threshold_31_we0();
void thread_threshs0_m_threshold_3_address0();
void thread_threshs0_m_threshold_3_ce0();
void thread_threshs0_m_threshold_3_d0();
void thread_threshs0_m_threshold_3_we0();
void thread_threshs0_m_threshold_4_address0();
void thread_threshs0_m_threshold_4_ce0();
void thread_threshs0_m_threshold_4_d0();
void thread_threshs0_m_threshold_4_we0();
void thread_threshs0_m_threshold_5_address0();
void thread_threshs0_m_threshold_5_ce0();
void thread_threshs0_m_threshold_5_d0();
void thread_threshs0_m_threshold_5_we0();
void thread_threshs0_m_threshold_6_address0();
void thread_threshs0_m_threshold_6_ce0();
void thread_threshs0_m_threshold_6_d0();
void thread_threshs0_m_threshold_6_we0();
void thread_threshs0_m_threshold_7_address0();
void thread_threshs0_m_threshold_7_ce0();
void thread_threshs0_m_threshold_7_d0();
void thread_threshs0_m_threshold_7_we0();
void thread_threshs0_m_threshold_8_address0();
void thread_threshs0_m_threshold_8_ce0();
void thread_threshs0_m_threshold_8_d0();
void thread_threshs0_m_threshold_8_we0();
void thread_threshs0_m_threshold_9_address0();
void thread_threshs0_m_threshold_9_ce0();
void thread_threshs0_m_threshold_9_d0();
void thread_threshs0_m_threshold_9_we0();
void thread_threshs0_m_threshold_address0();
void thread_threshs0_m_threshold_ce0();
void thread_threshs0_m_threshold_d0();
void thread_threshs0_m_threshold_we0();
void thread_threshs1_m_threshold_10_address0();
void thread_threshs1_m_threshold_10_ce0();
void thread_threshs1_m_threshold_10_d0();
void thread_threshs1_m_threshold_10_we0();
void thread_threshs1_m_threshold_11_address0();
void thread_threshs1_m_threshold_11_ce0();
void thread_threshs1_m_threshold_11_d0();
void thread_threshs1_m_threshold_11_we0();
void thread_threshs1_m_threshold_12_address0();
void thread_threshs1_m_threshold_12_ce0();
void thread_threshs1_m_threshold_12_d0();
void thread_threshs1_m_threshold_12_we0();
void thread_threshs1_m_threshold_13_address0();
void thread_threshs1_m_threshold_13_ce0();
void thread_threshs1_m_threshold_13_d0();
void thread_threshs1_m_threshold_13_we0();
void thread_threshs1_m_threshold_14_address0();
void thread_threshs1_m_threshold_14_ce0();
void thread_threshs1_m_threshold_14_d0();
void thread_threshs1_m_threshold_14_we0();
void thread_threshs1_m_threshold_15_address0();
void thread_threshs1_m_threshold_15_ce0();
void thread_threshs1_m_threshold_15_d0();
void thread_threshs1_m_threshold_15_we0();
void thread_threshs1_m_threshold_16_address0();
void thread_threshs1_m_threshold_16_ce0();
void thread_threshs1_m_threshold_16_d0();
void thread_threshs1_m_threshold_16_we0();
void thread_threshs1_m_threshold_17_address0();
void thread_threshs1_m_threshold_17_ce0();
void thread_threshs1_m_threshold_17_d0();
void thread_threshs1_m_threshold_17_we0();
void thread_threshs1_m_threshold_18_address0();
void thread_threshs1_m_threshold_18_ce0();
void thread_threshs1_m_threshold_18_d0();
void thread_threshs1_m_threshold_18_we0();
void thread_threshs1_m_threshold_19_address0();
void thread_threshs1_m_threshold_19_ce0();
void thread_threshs1_m_threshold_19_d0();
void thread_threshs1_m_threshold_19_we0();
void thread_threshs1_m_threshold_1_address0();
void thread_threshs1_m_threshold_1_ce0();
void thread_threshs1_m_threshold_1_d0();
void thread_threshs1_m_threshold_1_we0();
void thread_threshs1_m_threshold_20_address0();
void thread_threshs1_m_threshold_20_ce0();
void thread_threshs1_m_threshold_20_d0();
void thread_threshs1_m_threshold_20_we0();
void thread_threshs1_m_threshold_21_address0();
void thread_threshs1_m_threshold_21_ce0();
void thread_threshs1_m_threshold_21_d0();
void thread_threshs1_m_threshold_21_we0();
void thread_threshs1_m_threshold_22_address0();
void thread_threshs1_m_threshold_22_ce0();
void thread_threshs1_m_threshold_22_d0();
void thread_threshs1_m_threshold_22_we0();
void thread_threshs1_m_threshold_23_address0();
void thread_threshs1_m_threshold_23_ce0();
void thread_threshs1_m_threshold_23_d0();
void thread_threshs1_m_threshold_23_we0();
void thread_threshs1_m_threshold_24_address0();
void thread_threshs1_m_threshold_24_ce0();
void thread_threshs1_m_threshold_24_d0();
void thread_threshs1_m_threshold_24_we0();
void thread_threshs1_m_threshold_25_address0();
void thread_threshs1_m_threshold_25_ce0();
void thread_threshs1_m_threshold_25_d0();
void thread_threshs1_m_threshold_25_we0();
void thread_threshs1_m_threshold_26_address0();
void thread_threshs1_m_threshold_26_ce0();
void thread_threshs1_m_threshold_26_d0();
void thread_threshs1_m_threshold_26_we0();
void thread_threshs1_m_threshold_27_address0();
void thread_threshs1_m_threshold_27_ce0();
void thread_threshs1_m_threshold_27_d0();
void thread_threshs1_m_threshold_27_we0();
void thread_threshs1_m_threshold_28_address0();
void thread_threshs1_m_threshold_28_ce0();
void thread_threshs1_m_threshold_28_d0();
void thread_threshs1_m_threshold_28_we0();
void thread_threshs1_m_threshold_29_address0();
void thread_threshs1_m_threshold_29_ce0();
void thread_threshs1_m_threshold_29_d0();
void thread_threshs1_m_threshold_29_we0();
void thread_threshs1_m_threshold_2_address0();
void thread_threshs1_m_threshold_2_ce0();
void thread_threshs1_m_threshold_2_d0();
void thread_threshs1_m_threshold_2_we0();
void thread_threshs1_m_threshold_30_address0();
void thread_threshs1_m_threshold_30_ce0();
void thread_threshs1_m_threshold_30_d0();
void thread_threshs1_m_threshold_30_we0();
void thread_threshs1_m_threshold_31_address0();
void thread_threshs1_m_threshold_31_ce0();
void thread_threshs1_m_threshold_31_d0();
void thread_threshs1_m_threshold_31_we0();
void thread_threshs1_m_threshold_32_address0();
void thread_threshs1_m_threshold_32_ce0();
void thread_threshs1_m_threshold_32_d0();
void thread_threshs1_m_threshold_32_we0();
void thread_threshs1_m_threshold_33_address0();
void thread_threshs1_m_threshold_33_ce0();
void thread_threshs1_m_threshold_33_d0();
void thread_threshs1_m_threshold_33_we0();
void thread_threshs1_m_threshold_34_address0();
void thread_threshs1_m_threshold_34_ce0();
void thread_threshs1_m_threshold_34_d0();
void thread_threshs1_m_threshold_34_we0();
void thread_threshs1_m_threshold_35_address0();
void thread_threshs1_m_threshold_35_ce0();
void thread_threshs1_m_threshold_35_d0();
void thread_threshs1_m_threshold_35_we0();
void thread_threshs1_m_threshold_36_address0();
void thread_threshs1_m_threshold_36_ce0();
void thread_threshs1_m_threshold_36_d0();
void thread_threshs1_m_threshold_36_we0();
void thread_threshs1_m_threshold_37_address0();
void thread_threshs1_m_threshold_37_ce0();
void thread_threshs1_m_threshold_37_d0();
void thread_threshs1_m_threshold_37_we0();
void thread_threshs1_m_threshold_38_add
|
ress0();
void thread_threshs1_m_threshold_38_ce0();
void thread_threshs1_m_threshold_38_d0();
void thread_threshs1_m_threshold_38_we0();
void thread_threshs1_m_threshold_39_address0();
void thread_threshs1_m_threshold_39_ce0();
void thread_threshs1_m_threshold_39_d0();
void thread_threshs1_m_threshold_39_we0();
void thread_threshs1_m_threshold_3_address0();
void thread_threshs1_m_threshold_3_ce0();
void thread_threshs1_m_threshold_3_d0();
void thread_threshs1_m_threshold_3_we0();
void thread_threshs1_m_threshold_40_address0();
void thread_threshs1_m_threshold_40_ce0();
void thread_threshs1_m_threshold_40_d0();
void thread_threshs1_m_threshold_40_we0();
void thread_threshs1_m_threshold_41_address0();
void thread_threshs1_m_threshold_41_ce0();
void thread_threshs1_m_threshold_41_d0();
void thread_threshs1_m_threshold_41_we0();
void thread_threshs1_m_threshold_42_address0();
void thread_threshs1_m_threshold_42_ce0();
void thread_threshs1_m_threshold_42_d0();
void thread_threshs1_m_threshold_42_we0();
void thread_threshs1_m_threshold_43_address0();
void thread_threshs1_m_threshold_43_ce0();
void thread_threshs1_m_threshold_43_d0();
void thread_threshs1_m_threshold_43_we0();
void thread_threshs1_m_threshold_44_address0();
void thread_threshs1_m_threshold_44_ce0();
void thread_threshs1_m_threshold_44_d0();
void thread_threshs1_m_threshold_44_we0();
void thread_threshs1_m_threshold_45_address0();
void thread_threshs1_m_threshold_45_ce0();
void thread_threshs1_m_threshold_45_d0();
void thread_threshs1_m_threshold_45_we0();
void thread_threshs1_m_threshold_46_address0();
void thread_threshs1_m_threshold_46_ce0();
void thread_threshs1_m_threshold_46_d0();
void thread_threshs1_m_threshold_46_we0();
void thread_threshs1_m_threshold_47_address0();
void thread_threshs1_m_threshold_47_ce0();
void thread_threshs1_m_threshold_47_d0();
void thread_threshs1_m_threshold_47_we0();
void thread_threshs1_m_threshold_48_address0();
void thread_threshs1_m_threshold_48_ce0();
void thread_threshs1_m_threshold_48_d0();
void thread_threshs1_m_threshold_48_we0();
void thread_threshs1_m_threshold_49_address0();
void thread_threshs1_m_threshold_49_ce0();
void thread_threshs1_m_threshold_49_d0();
void thread_threshs1_m_threshold_49_we0();
void thread_threshs1_m_threshold_4_address0();
void thread_threshs1_m_threshold_4_ce0();
void thread_threshs1_m_threshold_4_d0();
void thread_threshs1_m_threshold_4_we0();
void thread_threshs1_m_threshold_50_address0();
void thread_threshs1_m_threshold_50_ce0();
void thread_threshs1_m_threshold_50_d0();
void thread_threshs1_m_threshold_50_we0();
void thread_threshs1_m_threshold_51_address0();
void thread_threshs1_m_threshold_51_ce0();
void thread_threshs1_m_threshold_51_d0();
void thread_threshs1_m_threshold_51_we0();
void thread_threshs1_m_threshold_52_address0();
void thread_threshs1_m_threshold_52_ce0();
void thread_threshs1_m_threshold_52_d0();
void thread_threshs1_m_threshold_52_we0();
void thread_threshs1_m_threshold_53_address0();
void thread_threshs1_m_threshold_53_ce0();
void thread_threshs1_m_threshold_53_d0();
void thread_threshs1_m_threshold_53_we0();
void thread_threshs1_m_threshold_54_address0();
void thread_threshs1_m_threshold_54_ce0();
void thread_threshs1_m_threshold_54_d0();
void thread_threshs1_m_threshold_54_we0();
void thread_threshs1_m_threshold_55_address0();
void thread_threshs1_m_threshold_55_ce0();
void thread_threshs1_m_threshold_55_d0();
void thread_threshs1_m_threshold_55_we0();
void thread_threshs1_m_threshold_56_address0();
void thread_threshs1_m_threshold_56_ce0();
void thread_threshs1_m_threshold_56_d0();
void thread_threshs1_m_threshold_56_we0();
void thread_threshs1_m_threshold_57_address0();
void thread_threshs1_m_threshold_57_ce0();
void thread_threshs1_m_threshold_57_d0();
void thread_threshs1_m_threshold_57_we0();
void thread_threshs1_m_threshold_58_address0();
void thread_threshs1_m_threshold_58_ce0();
void thread_threshs1_m_threshold_58_d0();
void thread_threshs1_m_threshold_58_we0();
void thread_threshs1_m_threshold_59_address0();
void thread_threshs1_m_threshold_59_ce0();
void thread_threshs1_m_threshold_59_d0();
void thread_threshs1_m_threshold_59_we0();
void thread_threshs1_m_threshold_5_address0();
void thread_threshs1_m_threshold_5_ce0();
void thread_threshs1_m_threshold_5_d0();
void thread_threshs1_m_threshold_5_we0();
void thread_threshs1_m_threshold_60_address0();
void thread_threshs1_m_threshold_60_ce0();
void thread_threshs1_m_threshold_60_d0();
void thread_threshs1_m_threshold_60_we0();
void thread_threshs1_m_threshold_61_address0();
void thread_threshs1_m_threshold_61_ce0();
void thread_threshs1_m_threshold_61_d0();
void thread_threshs1_m_threshold_61_we0();
void thread_threshs1_m_threshold_62_address0();
void thread_threshs1_m_threshold_62_ce0();
void thread_threshs1_m_threshold_62_d0();
void thread_threshs1_m_threshold_62_we0();
void thread_threshs1_m_threshold_63_address0();
void thread_threshs1_m_threshold_63_ce0();
void thread_threshs1_m_threshold_63_d0();
void thread_threshs1_m_threshold_63_we0();
void thread_threshs1_m_threshold_6_address0();
void thread_threshs1_m_threshold_6_ce0();
void thread_threshs1_m_threshold_6_d0();
void thread_threshs1_m_threshold_6_we0();
void thread_threshs1_m_threshold_7_address0();
void thread_threshs1_m_threshold_7_ce0();
void thread_threshs1_m_threshold_7_d0();
void thread_threshs1_m_threshold_7_we0();
void thread_threshs1_m_threshold_8_address0();
void thread_threshs1_m_threshold_8_ce0();
void thread_threshs1_m_threshold_8_d0();
void thread_threshs1_m_threshold_8_we0();
void thread_threshs1_m_threshold_9_address0();
void thread_threshs1_m_threshold_9_ce0();
void thread_threshs1_m_threshold_9_d0();
void thread_threshs1_m_threshold_9_we0();
void thread_threshs1_m_threshold_address0();
void thread_threshs1_m_threshold_ce0();
void thread_threshs1_m_threshold_d0();
void thread_threshs1_m_threshold_we0();
void thread_threshs2_m_threshold_10_address0();
void thread_threshs2_m_threshold_10_ce0();
void thread_threshs2_m_threshold_10_d0();
void thread_threshs2_m_threshold_10_we0();
void thread_threshs2_m_threshold_11_address0();
void thread_threshs2_m_threshold_11_ce0();
void thread_threshs2_m_threshold_11_d0();
void thread_threshs2_m_threshold_11_we0();
void thread_threshs2_m_threshold_12_address0();
void thread_threshs2_m_threshold_12_ce0();
void thread_threshs2_m_threshold_12_d0();
void thread_threshs2_m_threshold_12_we0();
void thread_threshs2_m_threshold_13_address0();
void thread_threshs2_m_threshold_13_ce0();
void thread_threshs2_m_threshold_13_d0();
void thread_threshs2_m_threshold_13_we0();
void thread_threshs2_m_threshold_14_address0();
void thread_threshs2_m_threshold_14_ce0();
void thread_threshs2_m_threshold_14_d0();
void thread_threshs2_m_threshold_14_we0();
void thread_threshs2_m_threshold_15_address0();
void thread_threshs2_m_threshold_15_ce0();
void thread_threshs2_m_threshold_15_d0();
void thread_threshs2_m_threshold_15_we0();
void thread_threshs2_m_threshold_16_address0();
void thread_threshs2_m_threshold_16_ce0();
void thread_threshs2_m_threshold_16_d0();
void thread_threshs2_m_threshold_16_we0();
void thread_threshs2_m_threshold_17_address0();
void thread_threshs2_m_threshold_17_ce0();
void thread_threshs2_m_threshold_17_d0();
void thread_threshs2_m_threshold_17_we0();
void thread_threshs2_m_threshold_18_address0();
void thread_threshs2_m_threshold_18_ce0();
void thread_threshs2_m_threshold_18_d0();
void thread_threshs2_m_threshold_18_we0();
void thread_threshs2_m_threshold_19_address0();
void thread_threshs2_m_threshold_19_ce0();
void thread_threshs2_m_threshold_19_d0();
void thread_threshs2_m_threshold_19_we0();
void thread_threshs2_m_threshold_1_address0();
void thread_threshs2_m_threshold_1_ce0();
void thread_threshs2_m_threshold_1_d0();
void thread_threshs2_m_threshold_1_we0();
void thread_threshs2_m_threshold_20_address0();
void thread_threshs2_m_threshold_20_ce0();
void thread_threshs2_m_threshold_20_d0();
void thread_threshs2_m_threshold_20_we0();
void thread_threshs2_m_threshold_21_address0();
void thread_threshs2_m_threshold_21_ce0();
void thread_threshs2_m_threshold_21_d0();
void thread_threshs2_m_threshold_21_we0();
void thread_threshs2_m_threshold_22_address0();
void thread_threshs2_m_threshold_22_ce0();
void thread_threshs2_m_threshold_22_d0();
void thread_threshs2_m_threshold_22_we0();
void thread_threshs2_m_threshold_23_address0();
void thread_threshs2_m_threshold_23_ce0();
void thread_threshs2_m_threshold_23_d0();
void thread_threshs2_m_threshold_23_we0();
void thread_threshs2_m_threshold_24_address0();
void thread_threshs2_m_threshold_24_ce0();
void thread_threshs2_m_threshold_24_d0();
void thread_threshs2_m_threshold_24_we0();
void thread_threshs2_m_threshold_25_address0();
void thread_threshs2_m_threshold_25_ce0();
void thread_threshs2_m_threshold_25_d0();
void thread_threshs2_m_threshold_25_we0();
void thread_threshs2_m_threshold_26_address0();
void thread_threshs2_m_threshold_26_ce0();
void thread_threshs2_m_threshold_26_d0();
void thread_threshs2_m_threshold_26_we0();
void thread_threshs2_m_threshold_27_address0();
void thread_threshs2_m_threshold_27_ce0();
void thread_threshs2_m_threshold_27_d0();
void thread_threshs2_m_threshold_27_we0();
void thread_threshs2_m_threshold_28_address0();
void thread_threshs2_m_threshold_28_ce0();
void thread_threshs2_m_threshold_28_d0();
void thread_threshs2_m_threshold_28_we0();
void thread_threshs2_m_threshold_29_address0();
void thread_threshs2_m_threshold_29_ce0();
void thread_threshs2_m_threshold_29_d0();
void thread_threshs2_m_threshold_29_we0();
void thread_threshs2_m_threshold_2_address0();
void thread_threshs2_m_threshold_2_ce0();
void thread_threshs2_m_threshold_2_d0();
void thread_threshs2_m_threshold_2_we0();
void thread_threshs2_m_threshold_30_address0();
void thread_threshs2_m_threshold_30_ce0();
void thread_threshs2_m_threshold_30_d0();
void thread_threshs2_m_threshold_30_we0();
void thread_threshs2_m_threshold_31_address0();
void thread_threshs2_m_threshold_31_ce0();
void thread_threshs2_m_threshold_31_d0();
void thread_threshs2_m_threshold_31_we0();
void thread_threshs2_m_threshold_3_address0();
void thread_threshs2_m_threshold_3_ce0();
void thread_threshs2_m_threshold_3_d0();
void thread_threshs2_m_threshold_3_we0();
void thread_threshs2_m_threshold_4_address0();
void thread_threshs2_m_threshold_4_ce0();
void thread_threshs2_m_threshold_4_d0();
void thread_threshs2_m_threshold_4_we0();
void thread_threshs2_m_threshold_5_address0();
void thread_threshs2_m_threshold_5_ce0();
void thread_threshs2_m_threshold_5_d0();
void thread_threshs2_m_threshold_5_we0();
void thread_threshs2_m_threshold_6_address0();
void thread_threshs2_m_threshold_6_ce0();
void thread_threshs2_m_threshold_6_d0();
void thread_threshs2_m_threshold_6_we0();
void thread_threshs2_m_threshold_7_address0();
void thread_threshs2_m_threshold_7_ce0();
void thread_threshs2_m_threshold_7_d0();
void thread_threshs2_m_threshold_7_we0();
void thread_threshs2_m_threshold_8_address0();
void thread_threshs2_m_threshold_8_ce0();
void thread_threshs2_m_threshold_8_d0();
void thread_threshs2_m_threshold_8_we0();
void thread_threshs2_m_threshold_9_address0();
void thread_threshs2_m_threshold_9_ce0();
void thread_threshs2_m_threshold_9_d0();
void thread_threshs2_m_threshold_9_we0();
void thread_threshs2_m_threshold_address0();
void thread_threshs2_m_threshold_ce0();
void thread_threshs2_m_threshold_d0();
void thread_threshs2_m_threshold_we0();
void thread_threshs3_m_threshold_10_address0();
void thread_threshs3_m_threshold_10_ce0();
void thread_threshs3_m_threshold_10_d0();
void thread_threshs3_m_threshold_10_we0();
void thread_threshs3_m_threshold_11_address0();
void thread_threshs3_m_threshold_11_ce0();
void thread_threshs3_m_threshold_11_d0();
void thread_threshs3_m_threshold_11_we0();
void thread_threshs3_m_threshold_12_address0();
void thread_threshs3_m_threshold_12_ce0();
void thread_threshs3_m_threshold_12_d0();
void thread_threshs3_m_threshold_12_we0();
void thread_threshs3_m_threshold_13_address0();
void thread_threshs3_m_threshold_13_ce0();
void thread_threshs3_m_threshold_13_d0();
void thread_threshs3_m_threshold_13_we0();
void thread_threshs3_m_threshold_14_address0();
void thread_threshs3_m_threshold_14_ce0();
void thread_threshs3_m_threshold_14_d0();
void thread_threshs3_m_threshold_14_we0();
void thread_threshs3_m_threshold_15_address0();
void thread_threshs3_m_threshold_15_ce0();
void thread_threshs3_m_threshold_15_d0();
void thread_threshs3_m_threshold_15_we0();
void thread_threshs3_m_threshold_1_address0();
void thread_threshs3_m_threshold_1_ce0();
void thread_threshs3_m_threshold_1_d0();
void thread_threshs3_m_threshold_1_we0();
void thread_threshs3_m_threshold_2_address0();
void thread_threshs3_m_threshold_2_ce0();
void thread_threshs3_m_threshold_2_d0();
void thread_threshs3_m_threshold_2_we0();
void thread_threshs3_m_threshold_3_address0();
void thread_threshs3_m_threshold_3_ce0();
void thread_threshs3_m_threshold_3_d0();
void thread_threshs3_m_threshold_3_we0();
void thread_threshs3_m_threshold_4_address0();
void thread_threshs3_m_threshold_4_ce0();
void thread_threshs3_m_threshold_4_d0();
void thread_threshs3_m_threshold_4_we0();
void thread_threshs3_m_threshold_5_address0();
void thread_threshs3_m_threshold_5_ce0();
void thread_threshs3_m_threshold_5_d0();
void thread_threshs3_m_threshold_5_we0();
void thread_threshs3_m_threshold_6_address0();
void thread_threshs3_m_threshold_6_ce0();
void thread_threshs3_m_threshold_6_d0();
void thread_threshs3_m_threshold_6_we0();
void thread_threshs3_m_threshold_7_address0();
void thread_threshs3_m_threshold_7_ce0();
void thread_threshs3_m_threshold_7_d0();
void thread_threshs3_m_threshold_7_we0();
void thread_threshs3_m_threshold_8_address0();
void thread_threshs3_m_threshold_8_ce0();
void thread_threshs3_m_threshold_8_d0();
void thread_threshs3_m_threshold_8_we0();
void thread_threshs3_m_threshold_9_address0();
void thread_threshs3_m_threshold_9_ce0();
void thread_threshs3_m_threshold_9_d0();
void thread_threshs3_m_threshold_9_we0();
void thread_threshs3_m_threshold_address0();
void thread_threshs3_m_threshold_ce0();
void thread_threshs3_m_threshold_d0();
void thread_threshs3_m_threshold_we0();
void thread_tmp_1_fu_4712_p1();
void thread_tmp_2_fu_4572_p1();
void thread_tmp_3_fu_4532_p1();
void thread_tmp_4_fu_4456_p1();
void thread_tmp_5_fu_4412_p1();
void thread_tmp_6_fu_4368_p1();
void thread_tmp_8402_fu_4964_p1();
void thread_tmp_8403_fu_4888_p1();
void thread_tmp_8404_fu_4924_p1();
void thread_tmp_8405_fu_4780_p1();
void thread_tmp_8406_fu_4848_p1();
void thread_tmp_8407_fu_4640_p1();
void thread_tmp_8408_fu_4708_p1();
void thread_tmp_8409_fu_4568_p1();
void thread_tmp_8410_fu_4492_p1();
void thread_tmp_8411_fu_4528_p1();
void thread_tmp_8412_fu_4432_p1();
void thread_tmp_8413_fu_4452_p1();
void thread_tmp_8414_fu_4388_p1();
void thread_tmp_8415_fu_4408_p1();
void thread_tmp_fu_4928_p1();
void thread_tmp_s_fu_4852_p1();
void thread_weights0_m_weights_V_10_address0();
void thread_weights0_m_weights_V_10_ce0();
void thread_weights0_m_weights_V_10_d0();
void thread_weights0_m_weights_V_10_we0();
void thread_weights0_m_weights_V_11_address0();
void thread_weights0_m_weights_V_11_ce0();
void thread_weights0_m_weights_V_11_d0();
void thread_weights0_m_weights_V_11_we0();
void thread_weights0_m_weights_V_12_address0();
void thread_weights0_m_weights_V_12_ce0();
void thread_weights0_m_weights_V_12_d0();
void thread_weights0_m_weights_V_12_we0();
void thread_weights0_m_weights_V_13_address0();
void thread_weights0_m_weights_V_13_ce0();
void thread_weights0_m_weights_V_13_d0();
void thread_weights0_m_weights_V_13_we0();
void thread_weights0_m_weights_V_14_address0();
void thread_weights0_m_weights_V_14_ce0();
void thread_weights0_m_weights_V_14_d0();
void thread_weights0_m_weights_V_14_we0();
void thread_weights0_m_weights_V_15_address0();
void thread_weights0_m_weights_V_15_ce0();
void thread_weights0_m_weights_V_15_d0();
void thread_weights0_m_weights_V_15_we0();
void thread_weights0_m_weights_V_16_address0();
void thread_weights0_m_weights_V_16_ce0();
void thread_weights0_m_weights_V_16_d0();
void thread_weights0_m_weights_V_16_we0();
void thread_weights0_m_weights_V_17_address0();
void thread_weights0_m_weights_V_17_ce0();
void thread_weights0_m_weights_V_17_d0();
void thread_weights0_m_weights_V_17_we0();
void thread_weights0_m_weights_V_18_address0();
void thread_weights0_m_weights_V_18_ce0();
void thread_weights0_m_weights_V_18_d0();
void thread_weights0_m_weights_V_18_we0();
void thread_weights0_m_weights_V_19_address0();
void thread_weights0_m_weights_V_19_ce0();
void thread_weights0_m_weights_V_19_d0();
void thread_weights0_m_weights_V_19_we0();
void thread_weights0_m_weights_V_1_address0();
void thread_weights0_m_weights_V_1_ce0();
void thread_weights0_m_weights_V_1_d0();
void thread_weights0_m_weights_V_1_we0();
void thread_weights0_m_weights_V_20_address0();
void thread_weights0_m_weights_V_20_ce0();
void thread_weights0_m_weights_V_20_d0();
void thread_weights0_m_weights_V_20_we0();
void thread_weights0_m_weights_V_21_address0();
void thread_weights0_m_weights_V_21_ce0();
void thread_weights0_m_weights_V_21_d0();
void thread_weights0_m_weights_V_21_we0();
void thread_weights0_m_weights_V_22_address0();
void thread_weights0_m_weights_V_22_ce0();
void thread_weights0_m_weights_V_22_d0();
void thread_weights0_m_weights_V_22_we0();
void thread_weights0_m_weights_V_23_address0();
void thread_weights0_m_weights_V_23_ce0();
void thread_weights0_m_weights_V_23_d0();
void thread_weights0_m_weights_V_23_we0();
void thread_weights0_m_weights_V_24_address0();
void thread_weights0_m_weights_V_24_ce0();
void thread_weights0_m_weights_V_24_d0();
void thread_weights0_m_weights_V_24_we0();
void thread_weights0_m_weights_V_25_address0();
void thread_weights0_m_weights_V_25_ce0();
void thread_weights0_m_weights_V_25_d0();
void thread_weights0_m_weights_V_25_we0();
void thread_weights0_m_weights_V_26_address0();
void thread_weights0_m_weights_V_26_ce0();
void thread_weights0_m_weights_V_26_d0();
void thread_weights0_m_weights_V_26_we0();
void thread_weights0_m_weights_V_27_address0();
void thread_weights0_m_weights_V_27_ce0();
void thread_weights0_m_weights_V_27_d0();
vo
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id thread_weights0_m_weights_V_27_we0();
void thread_weights0_m_weights_V_28_address0();
void thread_weights0_m_weights_V_28_ce0();
void thread_weights0_m_weights_V_28_d0();
void thread_weights0_m_weights_V_28_we0();
void thread_weights0_m_weights_V_29_address0();
void thread_weights0_m_weights_V_29_ce0();
void thread_weights0_m_weights_V_29_d0();
void thread_weights0_m_weights_V_29_we0();
void thread_weights0_m_weights_V_2_address0();
void thread_weights0_m_weights_V_2_ce0();
void thread_weights0_m_weights_V_2_d0();
void thread_weights0_m_weights_V_2_we0();
void thread_weights0_m_weights_V_30_address0();
void thread_weights0_m_weights_V_30_ce0();
void thread_weights0_m_weights_V_30_d0();
void thread_weights0_m_weights_V_30_we0();
void thread_weights0_m_weights_V_31_address0();
void thread_weights0_m_weights_V_31_ce0();
void thread_weights0_m_weights_V_31_d0();
void thread_weights0_m_weights_V_31_we0();
void thread_weights0_m_weights_V_3_address0();
void thread_weights0_m_weights_V_3_ce0();
void thread_weights0_m_weights_V_3_d0();
void thread_weights0_m_weights_V_3_we0();
void thread_weights0_m_weights_V_4_address0();
void thread_weights0_m_weights_V_4_ce0();
void thread_weights0_m_weights_V_4_d0();
void thread_weights0_m_weights_V_4_we0();
void thread_weights0_m_weights_V_5_address0();
void thread_weights0_m_weights_V_5_ce0();
void thread_weights0_m_weights_V_5_d0();
void thread_weights0_m_weights_V_5_we0();
void thread_weights0_m_weights_V_6_address0();
void thread_weights0_m_weights_V_6_ce0();
void thread_weights0_m_weights_V_6_d0();
void thread_weights0_m_weights_V_6_we0();
void thread_weights0_m_weights_V_7_address0();
void thread_weights0_m_weights_V_7_ce0();
void thread_weights0_m_weights_V_7_d0();
void thread_weights0_m_weights_V_7_we0();
void thread_weights0_m_weights_V_8_address0();
void thread_weights0_m_weights_V_8_ce0();
void thread_weights0_m_weights_V_8_d0();
void thread_weights0_m_weights_V_8_we0();
void thread_weights0_m_weights_V_9_address0();
void thread_weights0_m_weights_V_9_ce0();
void thread_weights0_m_weights_V_9_d0();
void thread_weights0_m_weights_V_9_we0();
void thread_weights0_m_weights_V_address0();
void thread_weights0_m_weights_V_ce0();
void thread_weights0_m_weights_V_d0();
void thread_weights0_m_weights_V_we0();
void thread_weights1_m_weights_V_10_address0();
void thread_weights1_m_weights_V_10_ce0();
void thread_weights1_m_weights_V_10_d0();
void thread_weights1_m_weights_V_10_we0();
void thread_weights1_m_weights_V_11_address0();
void thread_weights1_m_weights_V_11_ce0();
void thread_weights1_m_weights_V_11_d0();
void thread_weights1_m_weights_V_11_we0();
void thread_weights1_m_weights_V_12_address0();
void thread_weights1_m_weights_V_12_ce0();
void thread_weights1_m_weights_V_12_d0();
void thread_weights1_m_weights_V_12_we0();
void thread_weights1_m_weights_V_13_address0();
void thread_weights1_m_weights_V_13_ce0();
void thread_weights1_m_weights_V_13_d0();
void thread_weights1_m_weights_V_13_we0();
void thread_weights1_m_weights_V_14_address0();
void thread_weights1_m_weights_V_14_ce0();
void thread_weights1_m_weights_V_14_d0();
void thread_weights1_m_weights_V_14_we0();
void thread_weights1_m_weights_V_15_address0();
void thread_weights1_m_weights_V_15_ce0();
void thread_weights1_m_weights_V_15_d0();
void thread_weights1_m_weights_V_15_we0();
void thread_weights1_m_weights_V_16_address0();
void thread_weights1_m_weights_V_16_ce0();
void thread_weights1_m_weights_V_16_d0();
void thread_weights1_m_weights_V_16_we0();
void thread_weights1_m_weights_V_17_address0();
void thread_weights1_m_weights_V_17_ce0();
void thread_weights1_m_weights_V_17_d0();
void thread_weights1_m_weights_V_17_we0();
void thread_weights1_m_weights_V_18_address0();
void thread_weights1_m_weights_V_18_ce0();
void thread_weights1_m_weights_V_18_d0();
void thread_weights1_m_weights_V_18_we0();
void thread_weights1_m_weights_V_19_address0();
void thread_weights1_m_weights_V_19_ce0();
void thread_weights1_m_weights_V_19_d0();
void thread_weights1_m_weights_V_19_we0();
void thread_weights1_m_weights_V_1_address0();
void thread_weights1_m_weights_V_1_ce0();
void thread_weights1_m_weights_V_1_d0();
void thread_weights1_m_weights_V_1_we0();
void thread_weights1_m_weights_V_20_address0();
void thread_weights1_m_weights_V_20_ce0();
void thread_weights1_m_weights_V_20_d0();
void thread_weights1_m_weights_V_20_we0();
void thread_weights1_m_weights_V_21_address0();
void thread_weights1_m_weights_V_21_ce0();
void thread_weights1_m_weights_V_21_d0();
void thread_weights1_m_weights_V_21_we0();
void thread_weights1_m_weights_V_22_address0();
void thread_weights1_m_weights_V_22_ce0();
void thread_weights1_m_weights_V_22_d0();
void thread_weights1_m_weights_V_22_we0();
void thread_weights1_m_weights_V_23_address0();
void thread_weights1_m_weights_V_23_ce0();
void thread_weights1_m_weights_V_23_d0();
void thread_weights1_m_weights_V_23_we0();
void thread_weights1_m_weights_V_24_address0();
void thread_weights1_m_weights_V_24_ce0();
void thread_weights1_m_weights_V_24_d0();
void thread_weights1_m_weights_V_24_we0();
void thread_weights1_m_weights_V_25_address0();
void thread_weights1_m_weights_V_25_ce0();
void thread_weights1_m_weights_V_25_d0();
void thread_weights1_m_weights_V_25_we0();
void thread_weights1_m_weights_V_26_address0();
void thread_weights1_m_weights_V_26_ce0();
void thread_weights1_m_weights_V_26_d0();
void thread_weights1_m_weights_V_26_we0();
void thread_weights1_m_weights_V_27_address0();
void thread_weights1_m_weights_V_27_ce0();
void thread_weights1_m_weights_V_27_d0();
void thread_weights1_m_weights_V_27_we0();
void thread_weights1_m_weights_V_28_address0();
void thread_weights1_m_weights_V_28_ce0();
void thread_weights1_m_weights_V_28_d0();
void thread_weights1_m_weights_V_28_we0();
void thread_weights1_m_weights_V_29_address0();
void thread_weights1_m_weights_V_29_ce0();
void thread_weights1_m_weights_V_29_d0();
void thread_weights1_m_weights_V_29_we0();
void thread_weights1_m_weights_V_2_address0();
void thread_weights1_m_weights_V_2_ce0();
void thread_weights1_m_weights_V_2_d0();
void thread_weights1_m_weights_V_2_we0();
void thread_weights1_m_weights_V_30_address0();
void thread_weights1_m_weights_V_30_ce0();
void thread_weights1_m_weights_V_30_d0();
void thread_weights1_m_weights_V_30_we0();
void thread_weights1_m_weights_V_31_address0();
void thread_weights1_m_weights_V_31_ce0();
void thread_weights1_m_weights_V_31_d0();
void thread_weights1_m_weights_V_31_we0();
void thread_weights1_m_weights_V_32_address0();
void thread_weights1_m_weights_V_32_ce0();
void thread_weights1_m_weights_V_32_d0();
void thread_weights1_m_weights_V_32_we0();
void thread_weights1_m_weights_V_33_address0();
void thread_weights1_m_weights_V_33_ce0();
void thread_weights1_m_weights_V_33_d0();
void thread_weights1_m_weights_V_33_we0();
void thread_weights1_m_weights_V_34_address0();
void thread_weights1_m_weights_V_34_ce0();
void thread_weights1_m_weights_V_34_d0();
void thread_weights1_m_weights_V_34_we0();
void thread_weights1_m_weights_V_35_address0();
void thread_weights1_m_weights_V_35_ce0();
void thread_weights1_m_weights_V_35_d0();
void thread_weights1_m_weights_V_35_we0();
void thread_weights1_m_weights_V_36_address0();
void thread_weights1_m_weights_V_36_ce0();
void thread_weights1_m_weights_V_36_d0();
void thread_weights1_m_weights_V_36_we0();
void thread_weights1_m_weights_V_37_address0();
void thread_weights1_m_weights_V_37_ce0();
void thread_weights1_m_weights_V_37_d0();
void thread_weights1_m_weights_V_37_we0();
void thread_weights1_m_weights_V_38_address0();
void thread_weights1_m_weights_V_38_ce0();
void thread_weights1_m_weights_V_38_d0();
void thread_weights1_m_weights_V_38_we0();
void thread_weights1_m_weights_V_39_address0();
void thread_weights1_m_weights_V_39_ce0();
void thread_weights1_m_weights_V_39_d0();
void thread_weights1_m_weights_V_39_we0();
void thread_weights1_m_weights_V_3_address0();
void thread_weights1_m_weights_V_3_ce0();
void thread_weights1_m_weights_V_3_d0();
void thread_weights1_m_weights_V_3_we0();
void thread_weights1_m_weights_V_40_address0();
void thread_weights1_m_weights_V_40_ce0();
void thread_weights1_m_weights_V_40_d0();
void thread_weights1_m_weights_V_40_we0();
void thread_weights1_m_weights_V_41_address0();
void thread_weights1_m_weights_V_41_ce0();
void thread_weights1_m_weights_V_41_d0();
void thread_weights1_m_weights_V_41_we0();
void thread_weights1_m_weights_V_42_address0();
void thread_weights1_m_weights_V_42_ce0();
void thread_weights1_m_weights_V_42_d0();
void thread_weights1_m_weights_V_42_we0();
void thread_weights1_m_weights_V_43_address0();
void thread_weights1_m_weights_V_43_ce0();
void thread_weights1_m_weights_V_43_d0();
void thread_weights1_m_weights_V_43_we0();
void thread_weights1_m_weights_V_44_address0();
void thread_weights1_m_weights_V_44_ce0();
void thread_weights1_m_weights_V_44_d0();
void thread_weights1_m_weights_V_44_we0();
void thread_weights1_m_weights_V_45_address0();
void thread_weights1_m_weights_V_45_ce0();
void thread_weights1_m_weights_V_45_d0();
void thread_weights1_m_weights_V_45_we0();
void thread_weights1_m_weights_V_46_address0();
void thread_weights1_m_weights_V_46_ce0();
void thread_weights1_m_weights_V_46_d0();
void thread_weights1_m_weights_V_46_we0();
void thread_weights1_m_weights_V_47_address0();
void thread_weights1_m_weights_V_47_ce0();
void thread_weights1_m_weights_V_47_d0();
void thread_weights1_m_weights_V_47_we0();
void thread_weights1_m_weights_V_48_address0();
void thread_weights1_m_weights_V_48_ce0();
void thread_weights1_m_weights_V_48_d0();
void thread_weights1_m_weights_V_48_we0();
void thread_weights1_m_weights_V_49_address0();
void thread_weights1_m_weights_V_49_ce0();
void thread_weights1_m_weights_V_49_d0();
void thread_weights1_m_weights_V_49_we0();
void thread_weights1_m_weights_V_4_address0();
void thread_weights1_m_weights_V_4_ce0();
void thread_weights1_m_weights_V_4_d0();
void thread_weights1_m_weights_V_4_we0();
void thread_weights1_m_weights_V_50_address0();
void thread_weights1_m_weights_V_50_ce0();
void thread_weights1_m_weights_V_50_d0();
void thread_weights1_m_weights_V_50_we0();
void thread_weights1_m_weights_V_51_address0();
void thread_weights1_m_weights_V_51_ce0();
void thread_weights1_m_weights_V_51_d0();
void thread_weights1_m_weights_V_51_we0();
void thread_weights1_m_weights_V_52_address0();
void thread_weights1_m_weights_V_52_ce0();
void thread_weights1_m_weights_V_52_d0();
void thread_weights1_m_weights_V_52_we0();
void thread_weights1_m_weights_V_53_address0();
void thread_weights1_m_weights_V_53_ce0();
void thread_weights1_m_weights_V_53_d0();
void thread_weights1_m_weights_V_53_we0();
void thread_weights1_m_weights_V_54_address0();
void thread_weights1_m_weights_V_54_ce0();
void thread_weights1_m_weights_V_54_d0();
void thread_weights1_m_weights_V_54_we0();
void thread_weights1_m_weights_V_55_address0();
void thread_weights1_m_weights_V_55_ce0();
void thread_weights1_m_weights_V_55_d0();
void thread_weights1_m_weights_V_55_we0();
void thread_weights1_m_weights_V_56_address0();
void thread_weights1_m_weights_V_56_ce0();
void thread_weights1_m_weights_V_56_d0();
void thread_weights1_m_weights_V_56_we0();
void thread_weights1_m_weights_V_57_address0();
void thread_weights1_m_weights_V_57_ce0();
void thread_weights1_m_weights_V_57_d0();
void thread_weights1_m_weights_V_57_we0();
void thread_weights1_m_weights_V_58_address0();
void thread_weights1_m_weights_V_58_ce0();
void thread_weights1_m_weights_V_58_d0();
void thread_weights1_m_weights_V_58_we0();
void thread_weights1_m_weights_V_59_address0();
void thread_weights1_m_weights_V_59_ce0();
void thread_weights1_m_weights_V_59_d0();
void thread_weights1_m_weights_V_59_we0();
void thread_weights1_m_weights_V_5_address0();
void thread_weights1_m_weights_V_5_ce0();
void thread_weights1_m_weights_V_5_d0();
void thread_weights1_m_weights_V_5_we0();
void thread_weights1_m_weights_V_60_address0();
void thread_weights1_m_weights_V_60_ce0();
void thread_weights1_m_weights_V_60_d0();
void thread_weights1_m_weights_V_60_we0();
void thread_weights1_m_weights_V_61_address0();
void thread_weights1_m_weights_V_61_ce0();
void thread_weights1_m_weights_V_61_d0();
void thread_weights1_m_weights_V_61_we0();
void thread_weights1_m_weights_V_62_address0();
void thread_weights1_m_weights_V_62_ce0();
void thread_weights1_m_weights_V_62_d0();
void thread_weights1_m_weights_V_62_we0();
void thread_weights1_m_weights_V_63_address0();
void thread_weights1_m_weights_V_63_ce0();
void thread_weights1_m_weights_V_63_d0();
void thread_weights1_m_weights_V_63_we0();
void thread_weights1_m_weights_V_6_address0();
void thread_weights1_m_weights_V_6_ce0();
void thread_weights1_m_weights_V_6_d0();
void thread_weights1_m_weights_V_6_we0();
void thread_weights1_m_weights_V_7_address0();
void thread_weights1_m_weights_V_7_ce0();
void thread_weights1_m_weights_V_7_d0();
void thread_weights1_m_weights_V_7_we0();
void thread_weights1_m_weights_V_8_address0();
void thread_weights1_m_weights_V_8_ce0();
void thread_weights1_m_weights_V_8_d0();
void thread_weights1_m_weights_V_8_we0();
void thread_weights1_m_weights_V_9_address0();
void thread_weights1_m_weights_V_9_ce0();
void thread_weights1_m_weights_V_9_d0();
void thread_weights1_m_weights_V_9_we0();
void thread_weights1_m_weights_V_address0();
void thread_weights1_m_weights_V_ce0();
void thread_weights1_m_weights_V_d0();
void thread_weights1_m_weights_V_we0();
void thread_weights2_m_weights_V_10_address0();
void thread_weights2_m_weights_V_10_ce0();
void thread_weights2_m_weights_V_10_d0();
void thread_weights2_m_weights_V_10_we0();
void thread_weights2_m_weights_V_11_address0();
void thread_weights2_m_weights_V_11_ce0();
void thread_weights2_m_weights_V_11_d0();
void thread_weights2_m_weights_V_11_we0();
void thread_weights2_m_weights_V_12_address0();
void thread_weights2_m_weights_V_12_ce0();
void thread_weights2_m_weights_V_12_d0();
void thread_weights2_m_weights_V_12_we0();
void thread_weights2_m_weights_V_13_address0();
void thread_weights2_m_weights_V_13_ce0();
void thread_weights2_m_weights_V_13_d0();
void thread_weights2_m_weights_V_13_we0();
void thread_weights2_m_weights_V_14_address0();
void thread_weights2_m_weights_V_14_ce0();
void thread_weights2_m_weights_V_14_d0();
void thread_weights2_m_weights_V_14_we0();
void thread_weights2_m_weights_V_15_address0();
void thread_weights2_m_weights_V_15_ce0();
void thread_weights2_m_weights_V_15_d0();
void thread_weights2_m_weights_V_15_we0();
void thread_weights2_m_weights_V_16_address0();
void thread_weights2_m_weights_V_16_ce0();
void thread_weights2_m_weights_V_16_d0();
void thread_weights2_m_weights_V_16_we0();
void thread_weights2_m_weights_V_17_address0();
void thread_weights2_m_weights_V_17_ce0();
void thread_weights2_m_weights_V_17_d0();
void thread_weights2_m_weights_V_17_we0();
void thread_weights2_m_weights_V_18_address0();
void thread_weights2_m_weights_V_18_ce0();
void thread_weights2_m_weights_V_18_d0();
void thread_weights2_m_weights_V_18_we0();
void thread_weights2_m_weights_V_19_address0();
void thread_weights2_m_weights_V_19_ce0();
void thread_weights2_m_weights_V_19_d0();
void thread_weights2_m_weights_V_19_we0();
void thread_weights2_m_weights_V_1_address0();
void thread_weights2_m_weights_V_1_ce0();
void thread_weights2_m_weights_V_1_d0();
void thread_weights2_m_weights_V_1_we0();
void thread_weights2_m_weights_V_20_address0();
void thread_weights2_m_weights_V_20_ce0();
void thread_weights2_m_weights_V_20_d0();
void thread_weights2_m_weights_V_20_we0();
void thread_weights2_m_weights_V_21_address0();
void thread_weights2_m_weights_V_21_ce0();
void thread_weights2_m_weights_V_21_d0();
void thread_weights2_m_weights_V_21_we0();
void thread_weights2_m_weights_V_22_address0();
void thread_weights2_m_weights_V_22_ce0();
void thread_weights2_m_weights_V_22_d0();
void thread_weights2_m_weights_V_22_we0();
void thread_weights2_m_weights_V_23_address0();
void thread_weights2_m_weights_V_23_ce0();
void thread_weights2_m_weights_V_23_d0();
void thread_weights2_m_weights_V_23_we0();
void thread_weights2_m_weights_V_24_address0();
void thread_weights2_m_weights_V_24_ce0();
void thread_weights2_m_weights_V_24_d0();
void thread_weights2_m_weights_V_24_we0();
void thread_weights2_m_weights_V_25_address0();
void thread_weights2_m_weights_V_25_ce0();
void thread_weights2_m_weights_V_25_d0();
void thread_weights2_m_weights_V_25_we0();
void thread_weights2_m_weights_V_26_address0();
void thread_weights2_m_weights_V_26_ce0();
void thread_weights2_m_weights_V_26_d0();
void thread_weights2_m_weights_V_26_we0();
void thread_weights2_m_weights_V_27_address0();
void thread_weights2_m_weights_V_27_ce0();
void thread_weights2_m_weights_V_27_d0();
void thread_weights2_m_weights_V_27_we0();
void thread_weights2_m_weights_V_28_address0();
void thread_weights2_m_weights_V_28_ce0();
void thread_weights2_m_weights_V_28_d0();
void thread_weights2_m_weights_V_28_we0();
void thread_weights2_m_weights_V_29_address0();
void thread_weights2_m_weights_V_29_ce0();
void thread_weights2_m_weights_V_29_d0();
void thread_weights2_m_weights_V_29_we0();
void thread_weights2_m_weights_V_2_address0();
void thread_weights2_m_weights_V_2_ce0();
void thread_weights2_m_weights_V_2_d0();
void thread_weights2_m_weights_V_2_we0();
void thread_weights2_m_weights_V_30_address0();
void thread_weights2_m_weights_V_30_ce0();
void thread_weights2_m_weights_V_30_d0();
void thread_weights2_m_weights_V_30_we0();
void thread_weights2_m_weights_V_31_address0();
void thread_weights2_m_weights_V_31_ce0();
void thread_weights2_m_weights_V_31_d0();
void thread_weights2_m_weights_V_31_we0();
void thread_weights2_m_weights_V_3_address0();
void thread_weights2_m_weights_V_3_ce0();
void thread_weights2_m_weights_V_3_d0();
void thread_weights2_m_weights_V_3_we0();
void thread_weights2_m_weights_V_4_address0();
void thread_weights2_m_weights_V_4_ce0();
void thread_weights2_m_weights_V_4_d0();
void thread_weights2_m_weights_V_4_we0();
void thread_weights2_m_weights_V_5_address0();
void thread_weights2_m_weights_V_5_ce0();
void thread_weights2_m_weights_V_5_d0();
void thread_weights2_m_weights_V_5_we0();
void thread_weights2_m_weights_V_6_address0();
void thread_weights2_m_weights_V_6_ce0();
vo
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id thread_weights2_m_weights_V_6_d0();
void thread_weights2_m_weights_V_6_we0();
void thread_weights2_m_weights_V_7_address0();
void thread_weights2_m_weights_V_7_ce0();
void thread_weights2_m_weights_V_7_d0();
void thread_weights2_m_weights_V_7_we0();
void thread_weights2_m_weights_V_8_address0();
void thread_weights2_m_weights_V_8_ce0();
void thread_weights2_m_weights_V_8_d0();
void thread_weights2_m_weights_V_8_we0();
void thread_weights2_m_weights_V_9_address0();
void thread_weights2_m_weights_V_9_ce0();
void thread_weights2_m_weights_V_9_d0();
void thread_weights2_m_weights_V_9_we0();
void thread_weights2_m_weights_V_address0();
void thread_weights2_m_weights_V_ce0();
void thread_weights2_m_weights_V_d0();
void thread_weights2_m_weights_V_we0();
void thread_weights3_m_weights_V_10_address0();
void thread_weights3_m_weights_V_10_ce0();
void thread_weights3_m_weights_V_10_d0();
void thread_weights3_m_weights_V_10_we0();
void thread_weights3_m_weights_V_11_address0();
void thread_weights3_m_weights_V_11_ce0();
void thread_weights3_m_weights_V_11_d0();
void thread_weights3_m_weights_V_11_we0();
void thread_weights3_m_weights_V_12_address0();
void thread_weights3_m_weights_V_12_ce0();
void thread_weights3_m_weights_V_12_d0();
void thread_weights3_m_weights_V_12_we0();
void thread_weights3_m_weights_V_13_address0();
void thread_weights3_m_weights_V_13_ce0();
void thread_weights3_m_weights_V_13_d0();
void thread_weights3_m_weights_V_13_we0();
void thread_weights3_m_weights_V_14_address0();
void thread_weights3_m_weights_V_14_ce0();
void thread_weights3_m_weights_V_14_d0();
void thread_weights3_m_weights_V_14_we0();
void thread_weights3_m_weights_V_15_address0();
void thread_weights3_m_weights_V_15_ce0();
void thread_weights3_m_weights_V_15_d0();
void thread_weights3_m_weights_V_15_we0();
void thread_weights3_m_weights_V_1_address0();
void thread_weights3_m_weights_V_1_ce0();
void thread_weights3_m_weights_V_1_d0();
void thread_weights3_m_weights_V_1_we0();
void thread_weights3_m_weights_V_2_address0();
void thread_weights3_m_weights_V_2_ce0();
void thread_weights3_m_weights_V_2_d0();
void thread_weights3_m_weights_V_2_we0();
void thread_weights3_m_weights_V_3_address0();
void thread_weights3_m_weights_V_3_ce0();
void thread_weights3_m_weights_V_3_d0();
void thread_weights3_m_weights_V_3_we0();
void thread_weights3_m_weights_V_4_address0();
void thread_weights3_m_weights_V_4_ce0();
void thread_weights3_m_weights_V_4_d0();
void thread_weights3_m_weights_V_4_we0();
void thread_weights3_m_weights_V_5_address0();
void thread_weights3_m_weights_V_5_ce0();
void thread_weights3_m_weights_V_5_d0();
void thread_weights3_m_weights_V_5_we0();
void thread_weights3_m_weights_V_6_address0();
void thread_weights3_m_weights_V_6_ce0();
void thread_weights3_m_weights_V_6_d0();
void thread_weights3_m_weights_V_6_we0();
void thread_weights3_m_weights_V_7_address0();
void thread_weights3_m_weights_V_7_ce0();
void thread_weights3_m_weights_V_7_d0();
void thread_weights3_m_weights_V_7_we0();
void thread_weights3_m_weights_V_8_address0();
void thread_weights3_m_weights_V_8_ce0();
void thread_weights3_m_weights_V_8_d0();
void thread_weights3_m_weights_V_8_we0();
void thread_weights3_m_weights_V_9_address0();
void thread_weights3_m_weights_V_9_ce0();
void thread_weights3_m_weights_V_9_d0();
void thread_weights3_m_weights_V_9_we0();
void thread_weights3_m_weights_V_address0();
void thread_weights3_m_weights_V_ce0();
void thread_weights3_m_weights_V_d0();
void thread_weights3_m_weights_V_we0();
};
}
using namespace ap_rtl;
#endif
|
#pragma once
/*******************************************************************************
* Apache License, Version 2.0
* Copyright (c) 2023 chciken/Niko
********************************************************************************/
#include <cstdint>
#include <string>
#include "systemc.h"
#include "sysc/kernel/sc_simcontext.h"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using u8 = uint8_t;
using u16 = uint16_t;
using u32 = uint32_t;
using u64 = uint64_t;
using i8 = int8_t;
using i16 = int16_t;
using i32 = int32_t;
using i64 = int64_t;
using string = std::string;
struct GbCommand : public tlm::tlm_extension<GbCommand> {
explicit GbCommand();
enum Cmd {
kGbReadInst,
kGbReadData,
kGbWriteData,
} cmd;
virtual tlm::tlm_extension_base* clone() const override;
virtual void copy_from(tlm::tlm_extension_base const &ext) override;
};
#include "gb_const.h"
|
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux3) {
sc_in <bool> sel;
sc_in <sc_uint<3>> in0;
sc_in <sc_uint<3>> in1;
sc_out <sc_uint<3>> out;
/*
** module global variables
*/
SC_CTOR (Mux3){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
void process () {
if(!sel.read()){
out.write(in0.read());
}
else{
out.write(in1.read());
}
}
};
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_7ded_one_0_H_
#define _bd_7ded_one_0_H_
#include "xlconstant_v1_1.h"
#include "systemc.h"
class bd_7ded_one_0 : public sc_module {
public:
xlconstant_v1_1_5<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_7ded_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
/*******************************************************************************
* i2c.h -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Models a single ESP32 I2C
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _I2C_H
#define _I2C_H
#include <systemc.h>
SC_MODULE(i2c) {
public:
sc_out<bool> scl_en_o {"scl_en_o"};
sc_out<bool> sda_en_o {"sda_en_o"};
sc_in<bool> scl_i {"scl_i"};
sc_in<bool> sda_i {"sda_i"};
sc_fifo<unsigned char> to {"to", 32*8};
sc_fifo<unsigned char> from {"from", 32*8};
sc_signal<unsigned char> snd {"snd"};
enum {IDLE, DEVID, READING, WRITING} state;
void transfer_th();
void trace(sc_trace_file *tf);
// Constructor
SC_CTOR(i2c) {
SC_THREAD(transfer_th);
}
};
extern i2c *i2c0ptr;
extern i2c *i2c1ptr;
#endif
|
//------------------------------------------------------------------------------
//! @file CppEmitter.h
//! @brief C++ Emitter classes
//
// SPDX-FileCopyrightText: Michael Popoloski
// SPDX-License-Identifier: MIT
//------------------------------------------------------------------------------
#pragma once
#include "fmt/format.h"
#include <filesystem>
#include <fstream>
#include <ranges>
#include <sstream>
#include <vector>
#include "slang/util/SmallVector.h"
#include "slang/util/Util.h"
namespace fs = std::filesystem;
class HppFile {
public:
explicit HppFile(std::string_view name, bool noSystemC) : fileName(std::string(name) + ".h") {
includes.emplace_back("ostream");
includes.emplace_back("cstddef");
includes.emplace_back("cstdint");
includes.emplace_back("string");
includes.emplace_back("sstream");
if (!noSystemC)
includes.emplace_back("systemc.h");
}
void add(std::string&& code) { hpp << code; }
void addInclude(std::string&& code) {
if (std::find(includes.begin(), includes.end(), code) == includes.end())
includes.emplace_back(code);
}
void addIncludeHeader(std::string_view code) {
if (std::find(headers.begin(), headers.end(), code) == headers.end())
headers.emplace_back(code);
}
void addWithIndent(std::string&& code) { hpp << indent(currentIndent) << code; }
void increaseIndent() { currentIndent++; }
void decreaseIndent() {
SLANG_ASSERT(currentIndent != 0);
currentIndent--;
}
std::string emit() {
auto includesTransform = std::views::transform(includes, [](const auto& inc) {
return fmt::format("#include <{}>", inc);
});
auto headersTransform = std::views::transform(headers, [](const auto& h) {
return fmt::format("#include \"{}.h\"", h);
});
return fmt::format("// {}\n#pragma once\n\n{}\n{}\n\n{}", fileName,
fmt::join(includesTransform, "\n"), fmt::join(headersTransform, "\n"),
hpp.str());
}
void emitToFile(const fs::path& path) {
auto outFile = std::ofstream(path / fileName);
outFile << emit();
}
private:
std::stringstream hpp;
std::vector<std::string> includes;
std::vector<std::string_view> headers;
std::string fileName;
uint32_t currentIndent{0};
std::string indent(uint64_t blocks) {
std::string ret;
for (auto i = 0; i < blocks * 4; i++)
ret += " ";
return ret;
}
};
class CppEmitter {
public:
explicit CppEmitter(bool noSystemC) : noSystemC(noSystemC) {}
[[nodiscard]] HppFile& newNamespace(std::string_view name) {
hppFiles.push_back(HppFile(name, noSystemC));
return hppFiles.back();
}
std::string emit() {
std::stringstream ret;
for (auto& hpp : hppFiles)
ret << hpp.emit();
return std::move(ret.str());
}
void emitToFile(const fs::path& path) {
for (auto& hpp : hppFiles)
hpp.emitToFile(path);
}
private:
bool noSystemC;
std::vector<HppFile> hppFiles;
};
|
#ifndef _IF_QUANTUMSIM_H_
#define _IF_QUANTUMSIM_H_
#include <systemc.h>
#include <map>
#include <string>
#include <vector>
#include "global_json.h"
#include "interface_lib.h"
#include "telf_module.h"
#ifdef _DEBUG
#undef _DEBUG
#include <Python.h>
#define _DEBUG
#else
#include <Python.h>
#endif
namespace cactus {
using sc_core::sc_in;
using sc_core::sc_out;
using sc_core::sc_signal;
using sc_core::sc_vector;
using sc_dt::sc_uint;
class If_QuantumSim : public Telf_module {
public: // general IO
sc_in<bool> clock_50MHz;
sc_in<bool> init;
// // input
// sc_vector<sc_in<Quantum_operation>> vec_q_operation;
// sc_in<bool> quantum_triggered;
// // output
// sc_vector<sc_out<sc_uint<2>>> vec_msmt_result;
// input
sc_in<Ops_2_qsim> ops_2_qsim; // ADI -> qubit simulator
// output
sc_out<Res_from_qsim> msmt_res; // qubit simulator -> ADI
protected:
PyObject* interface;
void init_python_api();
void apply_quantum_operation();
void apply_idle_gate(unsigned int idle_duration, unsigned int qubit);
void apply_single_qubit_gate(std::string quantum_operation, unsigned int qubit);
void apply_two_qubit_gate(std::string quantum_operation, unsigned int qubit0,
unsigned int qubit1);
unsigned int measure_qubit(unsigned int qubit);
void mock_measure(std::string mock_msmt_res_fn);
void print_ptms_to_do(unsigned int qubit);
void print_full_dm();
unsigned int get_idle_duration(bool is_1st_op, unsigned int cur_gate_duration,
unsigned int current_cycle, unsigned int pre_gate_start_point,
unsigned int pre_gate_duration);
unsigned int starting_cycle = 0;
protected: // logging methods
void add_telf_line();
void add_telf_header();
void log_telf();
protected: // configurations
unsigned int num_qubits = 0;
unsigned int num_msmt_devices = 0;
unsigned int cycle_time = 20; // ns
Instruction_type m_instruction_type;
std::map<std::string, unsigned int> single_qubit_gate_time;
std::map<std::string, unsigned int> two_qubit_gate_time;
std::map<std::string, unsigned int> operation_time;
std::string mock_msmt_res_fn;
// 2D array which store the qubit information for each feedline
std::vector<std::vector<unsigned int>> qubits_in_each_feedline;
void config();
void post_py_process(PyObject* pValue, PyObject* pMethod, const std::string& err_msg);
public:
If_QuantumSim(const sc_core::sc_module_name& n);
SC_HAS_PROCESS(If_QuantumSim);
};
} // namespace cactus
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _base_constant_tkeep_tstrb_0_H_
#define _base_constant_tkeep_tstrb_0_H_
#include "xlconstant_v1_1.h"
#include "systemc.h"
class base_constant_tkeep_tstrb_0 : public sc_module {
public:
xlconstant_v1_1_5<8,255> mod;
sc_out< sc_bv<8> > dout;
base_constant_tkeep_tstrb_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
#pragma once
#include <systemc.h>
#define BUF_SIZE 32
#define MAX_BUF_IDX (BUF_SIZE - 1)
SC_MODULE(FIFO) {
enum ic_addresses {
ICCONF = 0x18,
ICBUF = 0x1C
};
sc_in<bool> clk_i;
sc_in<sc_uint<32>> addr_bi;
sc_in<sc_uint<32>> data_bi;
sc_out<sc_uint<32>> data_bo;
sc_in<bool> wr_i;
sc_in<bool> rd_i;
sc_in<bool> ins_i;
sc_in<sc_uint<32>> icconf_i;
sc_out<sc_uint<32>> icconf_o;
sc_in<sc_uint<2>> ictmr_i;
sc_out<bool> icbne_o;
sc_out<bool> icov_o;
sc_in<sc_uint<32>> tval1_i;
sc_in<sc_uint<32>> tval2_i;
SC_HAS_PROCESS(FIFO);
FIFO(sc_module_name nm);
~FIFO() = default;
private:
sc_uint<32> icbuf[BUF_SIZE] = {0};
int reg_next_idx;
int reg_fst_idx;
bool reg_icov;
bool reg_icbne;
void on_clk();
};
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef AESL_COMP_H
#define AESL_COMP_H
#include <systemc>
//#include "systemc.h"
#define DEBUG(x)
///CFU: combinational FU, no clock, reset and ce
//template<int NUM_STAGE,
// int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
// int DOUT_WIDTH=DIN0_WIDTH>
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH> class AESLFUComp;
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
SC_MODULE( AESLCFUComp )
{
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR( AESLCFUComp );
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> *super;
virtual void sanity_check() {}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ if (super) return super->compute(in0, in1);
else return sc_lv<DOUT_WIDTH>(); }
void thread_compute() {
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] input: %llx %llx\n",
din0.read().to_uint64(),
din1.read().to_uint64());
else
printf("[ACMP_ADD] input: %x %x\n",
din0.read().to_uint(),
din1.read().to_uint());
});
sc_lv<DOUT_WIDTH> result = compute(din0.read(), din1.read());
dout.write(result);
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] comb output: %llx\n", result.to_uint64());
else
printf("[ACMP_ADD] comb output: %x\n", result.to_uint());
});
}
};
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>::
AESLCFUComp(const sc_module_name name): sc_module( name ), super(0) {
//sanity_check();
SC_METHOD( thread_compute );
sensitive << din0;
sensitive << din1;
}
///FU: sequential FU, with clock, reset and ce
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
SC_MODULE(AESLFUComp)
{
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> core;
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
/// Dont use stage_regvec[0].
sc_signal< sc_lv<DOUT_WIDTH> > stage_regvec[NUM_STAGE];
SC_CTOR( AESLFUComp );
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ return sc_lv<DOUT_WIDTH>(); }
void thread_stage() {
if (ce.read() == SC_LOGIC_0) return;
dout.write(stage_regvec[NUM_STAGE-1]);
for (unsigned i = NUM_STAGE-1; i > 1; --i) {
stage_regvec[i].write(stage_regvec[i-1].read());
}
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] reg output %llx\n",
stage_regvec[NUM_STAGE-1].read().to_uint64());
else
printf("[ACMP_ADD] reg output %x\n",
stage_regvec[NUM_STAGE-1].read().to_uint());
});
}
};
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>::
AESLFUComp(const sc_module_name name): sc_module( name ), core("CFU_U") {
//sanity_check();
core.din0(din0);
core.din1(din1);
core.dout(stage_regvec[1]);
core.super = this;
if (NUM_STAGE > 1)
{
SC_METHOD( thread_stage );
sensitive << clk.pos();
}
}
//Need refine here//////////////////////////////////////////////////////////////
///CFU: combinational FU, no clock, reset and ce
//template<int NUM_STAGE,
// int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
// int DOUT_WIDTH=DIN0_WIDTH>
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH> class AESLFUComp_seq;
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
SC_MODULE( AESLCFUComp_seq )
{
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR( AESLCFUComp_seq );
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> *super;
virtual void sanity_check() {}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ if (super) return super->compute(in0, in1);
else return sc_lv<DOUT_WIDTH>(); }
void thread_compute() {
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] input: %llx %llx\n",
din0.read().to_uint64(),
din1.read().to_uint64());
else
printf("[ACMP_ADD] input: %x %x\n",
din0.read().to_uint(),
din1.read().to_uint());
});
sc_lv<DOUT_WIDTH> result = compute(din0.read(), din1.read());
dout.write(result);
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] comb output: %llx\n", result.to_uint64());
else
printf("[ACMP_ADD] comb output: %x\n", result.to_uint());
});
}
};
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
AESLCFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>::
AESLCFUComp_seq(const sc_module_name name): sc_module( name ), super(0) {
//sanity_check();
SC_METHOD( thread_compute );
sensitive << din0;
sensitive << din1;
}
///FU: sequential FU, with clock, reset, ce and start
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
SC_MODULE(AESLFUComp_seq)
{
AESLCFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> core;
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_logic > start;
sc_in< sc_logic > done;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
/// Dont use stage_regvec[0].
sc_signal< sc_lv<DOUT_WIDTH> > stage_regvec[NUM_STAGE];
SC_CTOR( AESLFUComp_seq );
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ return sc_lv<DOUT_WIDTH>(); }
void thread_stage() {
if (ce.read() == SC_LOGIC_0) return;
dout.write(stage_regvec[NUM_STAGE-1]);
for (unsigned i = NUM_STAGE-1; i > 1; --i) {
stage_regvec[i].write(stage_regvec[i-1].read());
}
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] reg output %llx\n",
stage_regvec[NUM_STAGE-1].read().to_uint64());
else
printf("[ACMP_ADD] reg output %x\n",
stage_regvec[NUM_STAGE-1].read().to_uint());
});
}
};
template<int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH,
int DOUT_WIDTH>
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>::
AESLFUComp_seq(const sc_module_name name): sc_module( name ), core("CFU_U") {
//sanity_check();
core.din0(din0);
core.din1(din1);
core.dout(stage_regvec[1]);
core.super = this;
if (NUM_STAGE > 1)
{
SC_METHOD( thread_stage );
sensitive << clk.pos();
}
}
//end///////////////////////////////////////////////////////////////////////////
template<int OPC_WIDTH, int DIN_WIDTH, int DOUT_WIDTH>
struct FUComputeCore
{
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<OPC_WIDTH>& opcode, const sc_lv<DIN_WIDTH>& in)=0;
};
////////////////////////////////////////////////////////////////
// Abstract Multi-op combinational Functional Units.
////////////////////////////////////////////////////////////////
template<int NUM_STAGE, int OPC_WIDTH, int DIN_WIDTH, int DOUT_WIDTH>
SC_MODULE( AESLCFUMOComp )
{
public:
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN_WIDTH> > din;
sc_out< sc_lv<DOUT_WIDTH> > dout;
public:
SC_CTOR( AESLCFUMOComp ) {
assert(OPC_WIDTH > 0 && DIN_WIDTH > 0 && DOUT_WIDTH > 0
&& NUM_STAGE == 1);
SC_METHOD( thread_compute );
sensitive << opcode << din;
}
//virtual sc_lv<DOUT_WIDTH>
//compute(const sc_lv<OPC_WIDTH>& opcode, const sc_lv<DIN_WIDTH>& in) {
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* mCore;
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* core) {
mCore = core;
}
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* getComputeCore() {
return mCore;
}
public:
void thread_compute() {
DEBUG( cerr << "[ACMP] " << name() << " Input: "
<< din.read() << endl; );
assert(mCore);
sc_lv<DOUT_WIDTH> result;
if (din.read().is_01()) {
result = mCore->compute(opcode.read(), din.read());
}
else {
result = sc_lv<DOUT_WIDTH>();
}
dout.write(result);
DEBUG( cerr << "[ACMP] " << name() << " C-out: "
<< result << endl;);
}
};
////////////////////////////////////////////////////////////////
// Abstract Pipelined Functional Units.
////////////////////////////////////////////////////////////////
template<int NUM_STAGE, int OPC_WIDTH, int DIN_WIDTH, int DOUT_WIDTH>
SC_MODULE( AESLFUMultiCycle )
{
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN_WIDTH> > din;
sc_out< sc_lv<DOUT_WIDTH> > dout;
public:
SC_CTOR( AESLFUMultiCycle ) {
assert(OPC_WIDTH > 0 && DIN_WIDTH > 0 && DOUT_WIDTH > 0
&& NUM_STAGE > 0);
SC_METHOD( thread_compute );
sensitive << opcode << din;
sensitive << clk;
if (NUM_STAGE > 1)
{
SC_METHOD( thread_stage );
sensitive << (clk.pos());
}
}
//virtual sc_lv<DOUT_WIDTH>
//compute(const sc_lv<OPC_WIDTH>& opcode, const sc_lv<DIN_WIDTH>& in) {
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* mCore;
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* core) {
mCore = core;
}
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* getComputeCore() {
return mCore;
}
public:
sc_signal< sc_lv<DOUT_WIDTH> > stage_regvec[NUM_STAGE];
void thread_compute() {
DEBUG( cerr << "[ACMP] " << name() << " Input: "
<< din.read() << endl; );
assert(mCore);
sc_lv<DOUT_WIDTH> result;
if (din.read().is_01() && opcode.read().is_01()) {
result = mCore->compute(opcode.read(), din.read());
}
else {
result = sc_lv<DOUT_WIDTH>();
}
if (NUM_STAGE > 1)
stage_regvec[1].write(result);
else
dout.write(result);
DEBUG( cerr << "[ACMP] " << name() << " C-out: "
<< result << endl;);
}
void thread_stage() {
if (ce.read() == SC_LOGIC_0) return;
dout.write(stage_regvec[NUM_STAGE-1]);
for (unsigned i = NUM_STAGE-1; i > 1; --i) {
stage_regvec[i].write(stage_regvec[i-1].read());
}
DEBUG(
cerr << "[ACMP] " << name() << " R-out: "
<< stage_regvec[NUM_STAGE-1].read() << endl;);
}
};
////////////////////////////////////////////////////////////////
/// Unary operator
////////////////////////////////////////////////////////////////
template< int NUM_STAGE,
int DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
SC_MODULE( CFUUnaryOp )
{
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(CFUUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>("u_U");
mMCModule->opcode(sigone);
mMCModule->din(din0);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
}
AESLFUMultiCycle<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>* mMCModule;
void setComputeCore(FUComputeCore<1, DIN0_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
private:
sc_signal< sc_lv<1> > sigone;
sc_signal< bool > clk;
sc_signal< sc_logic > reset;
sc_signal< sc_logic > ce;
void IOConnection() {
sigone.write(sc_lv<1>("1"));
}
};
template< int NUM_STAGE,
int DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
SC_MODULE( FUUnaryOp )
{
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(FUUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>("u_U");
mMCModule->opcode(sigone);
mMCModule->din(din0);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
sensitive << clk;
}
AESLFUMultiCycle<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>* mMCModule;
void setComputeCore(FUComputeCore<1, DIN0_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
private:
sc_signal< sc_lv<1> > sigone;
void IOConnection() {
sigone.write(sc_lv<1>("1"));
}
};
template< int NUM_STAGE,
int OPC_WIDTH,
int DIN0_WIDTH,
int DOUT_WIDTH>
SC_MODULE( FUMOUnaryOp )
{
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(FUMOUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH, DOUT_WIDTH>("mu_U");
mMCModule->opcode(opcode);
mMCModule->din(din0);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
}
AESLFUMultiCycle<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH, DOUT_WIDTH>* mMCModule;
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN0_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
};
template< int NUM_STAGE,
int DIN0_WIDTH,
int DIN1_WIDTH,
int DOUT_WIDTH>
SC_MODULE (CFUBinaryOp)
{
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
AESLFUMultiCycle<NUM_STAGE, 1, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
mMCModule;
SC_CTOR( CFUBinaryOp ) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>("b_u");
//sigone.write(sc_lv<1>("1"));
mMCModule->opcode(sigone);
mMCModule->din(din_sig);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
sensitive << din0 << din1;
}
void setComputeCore(FUComputeCore<1, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
core) {
mMCModule->setComputeCore(core);
}
sc_signal< sc_lv<DIN0_WIDTH+DIN1_WIDTH> > din_sig;
sc_signal< sc_lv<1> > sigone;
sc_signal< bool > clk;
sc_signal< sc_logic > reset;
sc_signal< sc_logic > ce;
void IOConnection() {
sigone.write(sc_lv<1>("1"));
sc_lv<DIN0_WIDTH+DIN1_WIDTH> din_tmp;
din_tmp.range(0, DIN0_WIDTH-1) =
din0.read().range(0, DIN0_WIDTH-1);
din_tmp.range(DIN0_WIDTH, DIN0_WIDTH+DIN1_WIDTH-1) =
din1.read().range(0, DIN1_WIDTH-1);
din_sig.write(din_tmp);
}
};
template< int NUM_STAGE,
int DIN0_WIDTH,
int DIN1_WIDTH,
int DOUT_WIDTH>
SC_MODULE (FUBinaryOp)
{
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
AESLFUMultiCycle<NUM_STAGE, 1, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
mMCModule;
SC_CTOR( FUBinaryOp ) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>("b_u");
//sigone.write(sc_lv<1>("1"));
mMCModule->opcode(sigone);
mMCModule->din(din_sig);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
sensitive << din0 << din1 << clk;
}
void setComputeCore(FUComputeCore<1, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
core) {
mMCModule->setComputeCore(core);
}
sc_signal< sc_lv<DIN0_WIDTH+DIN1_WIDTH> > din_sig;
sc_signal< sc_lv<1> > sigone;
void IOConnection() {
sigone.write(sc_lv<1>("1"));
sc_lv<DIN0_WIDTH+DIN1_WIDTH> din_tmp;
din_tmp.range(0, DIN0_WIDTH-1) =
din0.read().range(0, DIN0_WIDTH-1);
din_tmp.range(DIN0_WIDTH, DIN0_WIDTH+DIN1_WIDTH-1) =
din1.read().range(0, DIN1_WIDTH-1);
din_sig.write(din_tmp);
}
};
template< int NUM_STAGE,
int OPC_WIDTH,
int DIN0_WIDTH,
int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
SC_MODULE (CFUMOBinaryOp)
{
public:
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
AESLCFUMOComp<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
mMCModule;
SC_CTOR( CFUMOBinaryOp ) {
mMCModule =
new AESLCFUMOComp
<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>("mb_U");
mMCModule->opcode(opcode);
mMCModule->din(din_sig);
mMCModule->dout(dout);
SC_METHOD(IOConnection);
sensitive << din0 << din1 << opcode ;
}
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
sc_signal< sc_lv<DIN0_WIDTH+DIN1_WIDTH> > din_sig;
void IOConnection() {
sc_lv<DIN0_WIDTH+DIN1_WIDTH> din_tmp;
din_tmp.range(0, DIN0_WIDTH-1) =
din0.read().range(0, DIN0_WIDTH-1);
din_tmp.range(DIN0_WIDTH, DIN0_WIDTH+DIN1_WIDTH-1) =
din1.read().range(0, DIN1_WIDTH-1);
din_sig.write(din_tmp);
}
};
template< int NUM_STAGE,
int OPC_WIDTH,
int DIN0_WIDTH,
int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
SC_MODULE (FUMOBinaryOp)
{
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< s
|
c_lv<DOUT_WIDTH> > dout;
AESLFUMultiCycle<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
mMCModule;
SC_CTOR( FUMOBinaryOp ) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>("mb_U");
mMCModule->opcode(opcode);
mMCModule->din(din_sig);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
sensitive << din0 << din1 << opcode << clk;
}
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
sc_signal< sc_lv<DIN0_WIDTH+DIN1_WIDTH> > din_sig;
void IOConnection() {
sc_lv<DIN0_WIDTH+DIN1_WIDTH> din_tmp;
din_tmp.range(0, DIN0_WIDTH-1) =
din0.read().range(0, DIN0_WIDTH-1);
din_tmp.range(DIN0_WIDTH, DIN0_WIDTH+DIN1_WIDTH-1) =
din1.read().range(0, DIN1_WIDTH-1);
din_sig.write(din_tmp);
}
};
template< bool SIGNED,
int DIN0_W,
int DIN1_W=DIN0_W,
int DOUT_W=DIN0_W>
struct IntArithCoreDivRem :
public FUComputeCore<2, DIN0_W+DIN1_W, DOUT_W>
{
virtual sc_lv<DOUT_W>
compute(const sc_lv<2>& opcode, const sc_lv<DIN0_W+DIN1_W>& in) {
sc_lv<DIN0_W> in0;
sc_lv<DIN1_W> in1;
(in1, in0) = in;
sc_lv<DOUT_W> undef;
if (!opcode.is_01() || !in.is_01()) return undef;
bool opc = opcode[0].to_bool();
if (!SIGNED) {
unsigned long long val0 = in0.to_uint64();
unsigned long long val1 = in1.to_uint64();
if (val1 == 0) return undef;
sc_biguint<DIN0_W> bval0 = sc_biguint<DIN0_W>(in0);
sc_biguint<DIN1_W> bval1 = sc_biguint<DIN1_W>(in1);
sc_biguint<DOUT_W> boutv = opc ? (bval0 % bval1) : (bval0 / bval1);
return sc_lv<DOUT_W>(boutv);
} else {
long long val0 = in0.to_int64();
long long val1 = in1.to_int64();
if (val1 == 0) return undef;
sc_bigint<DIN0_W> bval0 = sc_bigint<DIN0_W>(in0);
sc_bigint<DIN1_W> bval1 = sc_bigint<DIN1_W>(in1);
sc_bigint<DOUT_W> boutv = opc ? (bval0 % bval1) : (bval0 / bval1);
return sc_lv<DOUT_W>(boutv);
}
}
};
////////////////////////////////////////////////////////////////
// Integer UDIV/UREM component.
////////////////////////////////////////////////////////////////
template<int ID,
int NUM_STAGE,
int DIN0_W,
int DIN1_W,
int DOUT_W>
struct ACMP_udivurem_comb :
public CFUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>
{
ACMP_udivurem_comb(const char* mname ) :
CFUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>(mname) {
setComputeCore(
new
IntArithCoreDivRem<false, DIN0_W, DIN1_W, DOUT_W>());
}
};
template<int ID,
int NUM_STAGE,
int DIN0_W,
int DIN1_W,
int DOUT_W>
struct ACMP_udivurem :
public FUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>
{
ACMP_udivurem(const char* mname ) :
FUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>(mname) {
setComputeCore(
new
IntArithCoreDivRem<false, DIN0_W, DIN1_W, DOUT_W>());
}
};
////////////////////////////////////////////////////////////////
// Integer SDIV/SREM component.
////////////////////////////////////////////////////////////////
template<int ID,
int NUM_STAGE,
int DIN0_W,
int DIN1_W,
int DOUT_W>
struct ACMP_sdivsrem_comb :
public CFUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>
{
ACMP_sdivsrem_comb(const char* mname ) :
CFUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>(mname) {
setComputeCore(
new IntArithCoreDivRem<true, DIN0_W, DIN1_W, DOUT_W>());
}
};
template<int ID,
int NUM_STAGE,
int DIN0_W,
int DIN1_W,
int DOUT_W>
struct ACMP_sdivsrem :
public FUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>
{
ACMP_sdivsrem(const char* mname ) :
FUMOBinaryOp<NUM_STAGE, 2, DIN0_W, DIN1_W, DOUT_W>(mname) {
setComputeCore(
new IntArithCoreDivRem<true, DIN0_W, DIN1_W, DOUT_W>());
}
};
////////////////////////////////////////////////////////////////
// Integer UDIV component.
////////////////////////////////////////////////////////////////
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_udiv_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_udiv_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
unsigned long long ival1 = (in1).to_uint64();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_biguint<DIN0_WIDTH> bval0 = sc_biguint<DIN0_WIDTH>(in0);
sc_biguint<DIN1_WIDTH> bval1 = sc_biguint<DIN1_WIDTH>(in1);
sc_biguint<DOUT_WIDTH> boutv = bval0 / bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_udiv :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_udiv(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
// assert(DIN0_WIDTH == DOUT_WIDTH);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
unsigned long long ival1 = (in1).to_uint64();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_biguint<DIN0_WIDTH> bval0 = sc_biguint<DIN0_WIDTH>(in0);
sc_biguint<DIN1_WIDTH> bval1 = sc_biguint<DIN1_WIDTH>(in1);
sc_biguint<DOUT_WIDTH> boutv = bval0 / bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_udiv_seq :
public AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_udiv_seq(const char* mname) :
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
// assert(DIN0_WIDTH == DOUT_WIDTH);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
unsigned long long ival1 = (in1).to_uint64();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_biguint<DIN0_WIDTH> bval0 = sc_biguint<DIN0_WIDTH>(in0);
sc_biguint<DIN1_WIDTH> bval1 = sc_biguint<DIN1_WIDTH>(in1);
sc_biguint<DOUT_WIDTH> boutv = bval0 / bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_sdiv_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_sdiv_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
int ival1 = (in1).to_int();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_bigint<DIN0_WIDTH> bval0 = sc_bigint<DIN0_WIDTH>(in0);
sc_bigint<DIN1_WIDTH> bval1 = sc_bigint<DIN1_WIDTH>(in1);
sc_bigint<DOUT_WIDTH> boutv = bval0 / bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_sdiv :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_sdiv(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
//assert(DIN0_WIDTH == DOUT_WIDTH);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
int ival1 = (in1).to_int();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_bigint<DIN0_WIDTH> bval0 = sc_bigint<DIN0_WIDTH>(in0);
sc_bigint<DIN1_WIDTH> bval1 = sc_bigint<DIN1_WIDTH>(in1);
sc_bigint<DOUT_WIDTH> boutv = bval0 / bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_sdiv_seq :
public AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_sdiv_seq(const char* mname) :
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
//assert(DIN0_WIDTH == DOUT_WIDTH);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
int ival1 = (in1).to_int();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_bigint<DIN0_WIDTH> bval0 = sc_bigint<DIN0_WIDTH>(in0);
sc_bigint<DIN1_WIDTH> bval1 = sc_bigint<DIN1_WIDTH>(in1);
sc_bigint<DOUT_WIDTH> boutv = bval0 / bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int DIN0_WIDTH, int DIN1_WIDTH, int DOUT_WIDTH>
sc_lv<DOUT_WIDTH> compute_mul_ss(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
sc_bigint<DOUT_WIDTH> outi = sc_bigint<DIN0_WIDTH>(in0) * sc_bigint<DIN1_WIDTH>(in1);
return sc_lv<DOUT_WIDTH>(outi);
}
template<int DIN0_WIDTH, int DIN1_WIDTH, int DOUT_WIDTH>
sc_lv<DOUT_WIDTH> compute_mul_su(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
sc_bigint<DOUT_WIDTH> outi = sc_bigint<DIN0_WIDTH>(in0) * sc_biguint<DIN1_WIDTH>(in1);
return sc_lv<DOUT_WIDTH>(outi);
}
template<int DIN0_WIDTH, int DIN1_WIDTH, int DOUT_WIDTH>
sc_lv<DOUT_WIDTH> compute_mul_us(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
sc_bigint<DOUT_WIDTH> outi = sc_biguint<DIN0_WIDTH>(in0) * sc_bigint<DIN1_WIDTH>(in1);
return sc_lv<DOUT_WIDTH>(outi);
}
template<int DIN0_WIDTH, int DIN1_WIDTH, int DOUT_WIDTH>
sc_lv<DOUT_WIDTH> compute_mul_uu(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
sc_biguint<DOUT_WIDTH> outi = sc_biguint<DIN0_WIDTH>(in0) * sc_biguint<DIN1_WIDTH>(in1);
return sc_lv<DOUT_WIDTH>(outi);
}
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_mul_ss :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_mul_ss(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_ss<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_mul_su :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_mul_su(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_su<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_mul_us :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_mul_us(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_us<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_mul_uu :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_mul_uu(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_uu<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_smul_ss :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_smul_ss(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_ss<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_smul_su :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_smul_su(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_su<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_smul_us :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_smul_us(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_us<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_smul_uu :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_smul_uu(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
return compute_mul_uu<DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(in0, in1);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_add_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_bigint<DIN0_WIDTH> OpDataTypeT;
ACMP_add_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT ival0 = OpDataTypeT(in0);
OpDataTypeT ival1 = OpDataTypeT(in1);
OpDataTypeT outi = ival0 + ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_add :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_bigint<DIN0_WIDTH> OpDataTypeT;
ACMP_add(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT ival0 = OpDataTypeT(in0);
OpDataTypeT ival1 = OpDataTypeT(in1);
OpDataTypeT outi = ival0 + ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_sub_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_bigint<DIN0_WIDTH> OpDataTypeT;
ACMP_sub_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT ival0 = OpDataTypeT(in0);
OpDataTypeT ival1 = OpDataTypeT(in1);
OpDataTypeT outi = ival0 - ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_sub :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_bigint<DIN0_WIDTH> OpDataTypeT;
ACMP_sub(const
|
char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT ival0 = OpDataTypeT(in0);
OpDataTypeT ival1 = OpDataTypeT(in1);
OpDataTypeT outi = ival0 - ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_urem_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_urem_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 32);
// assert(DIN1_WIDTH == DOUT_WIDTH);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
unsigned int ival0 = (in0).to_uint();
unsigned int ival1 = (in1).to_uint();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_biguint<DIN0_WIDTH> bval0 = sc_biguint<DIN0_WIDTH>(in0);
sc_biguint<DIN1_WIDTH> bval1 = sc_biguint<DIN1_WIDTH>(in1);
sc_biguint<DOUT_WIDTH> boutv = bval0 % bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_urem :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_urem(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
unsigned int ival0 = (in0).to_uint();
unsigned int ival1 = (in1).to_uint();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_biguint<DIN0_WIDTH> bval0 = sc_biguint<DIN0_WIDTH>(in0);
sc_biguint<DIN1_WIDTH> bval1 = sc_biguint<DIN1_WIDTH>(in1);
sc_biguint<DOUT_WIDTH> boutv = bval0 % bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_urem_seq :
public AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_urem_seq(const char* mname) :
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
unsigned int ival0 = (in0).to_uint();
unsigned int ival1 = (in1).to_uint();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_biguint<DIN0_WIDTH> bval0 = sc_biguint<DIN0_WIDTH>(in0);
sc_biguint<DIN1_WIDTH> bval1 = sc_biguint<DIN1_WIDTH>(in1);
sc_biguint<DOUT_WIDTH> boutv = bval0 % bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_srem_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_srem_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
int ival1 = (in1).to_int();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_bigint<DIN0_WIDTH> bval0 = sc_bigint<DIN0_WIDTH>(in0);
sc_bigint<DIN1_WIDTH> bval1 = sc_bigint<DIN1_WIDTH>(in1);
sc_bigint<DOUT_WIDTH> boutv = bval0 % bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_srem :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_srem(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
int ival1 = (in1).to_int();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_bigint<DIN0_WIDTH> bval0 = sc_bigint<DIN0_WIDTH>(in0);
sc_bigint<DIN1_WIDTH> bval1 = sc_bigint<DIN1_WIDTH>(in1);
sc_bigint<DOUT_WIDTH> boutv = bval0 % bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_srem_seq :
public AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>
{
public:
ACMP_srem_seq(const char* mname) :
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
//assert(DIN0_WIDTH <= 64);
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if (!in0.is_01() || !in1.is_01()) return sc_lv<DOUT_WIDTH>();
int ival1 = (in1).to_int();
if (ival1 == 0)
return sc_lv<DOUT_WIDTH>();
sc_bigint<DIN0_WIDTH> bval0 = sc_bigint<DIN0_WIDTH>(in0);
sc_bigint<DIN1_WIDTH> bval1 = sc_bigint<DIN1_WIDTH>(in1);
sc_bigint<DOUT_WIDTH> boutv = bval0 % bval1;
return sc_lv<DOUT_WIDTH>(boutv);
}
};
// shl
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_shl_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_biguint<DIN0_WIDTH> OpDataTypeT1;
typedef sc_biguint<DIN1_WIDTH> OpDataTypeT2;
ACMP_shl_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN0_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT1 ival0 = OpDataTypeT1(in0);
OpDataTypeT2 ival1 = sc_bv<DIN1_WIDTH>(in1.range(DIN1_WIDTH-1, 0));
if(ival1>DIN0_WIDTH) return sc_lv<DOUT_WIDTH>(0);
OpDataTypeT1 outi = ival0 << ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_shl :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_biguint<DIN0_WIDTH> OpDataTypeT1;
typedef sc_biguint<DIN1_WIDTH> OpDataTypeT2;
ACMP_shl(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN0_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT1 ival0 = OpDataTypeT1(in0);
OpDataTypeT2 ival1 = sc_bv<DIN1_WIDTH>(in1.range(DIN1_WIDTH-1, 0));
if(ival1>DIN0_WIDTH) return sc_lv<DOUT_WIDTH>(0);
OpDataTypeT1 outi = ival0 << ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
// lshr
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_lshr_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_biguint<DIN0_WIDTH> OpDataTypeT1;
typedef sc_biguint<DIN1_WIDTH> OpDataTypeT2;
ACMP_lshr_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN0_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT1 ival0 = OpDataTypeT1(in0);
OpDataTypeT2 ival1 = sc_bv<DIN1_WIDTH>(in1.range(DIN1_WIDTH-1, 0));
OpDataTypeT1 outi = ival0 >> ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_lshr :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_biguint<DIN0_WIDTH> OpDataTypeT1;
typedef sc_biguint<DIN1_WIDTH> OpDataTypeT2;
ACMP_lshr(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN0_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT1 ival0 = OpDataTypeT1(in0);
OpDataTypeT2 ival1 = sc_bv<DIN1_WIDTH>(in1.range(DIN1_WIDTH-1, 0));
OpDataTypeT1 outi = ival0 >> ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
// ashr
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_ashr_comb :
public AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_bigint<DIN0_WIDTH> OpDataTypeT1;
typedef sc_biguint<DIN1_WIDTH> OpDataTypeT2;
ACMP_ashr_comb(const char* mname) :
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN0_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT1 ival0 = OpDataTypeT1(in0);
OpDataTypeT2 ival1 = sc_bv<DIN1_WIDTH>(in1.range(DIN1_WIDTH-1, 0));
OpDataTypeT1 outi = ival0 >> ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
template<int ID, int NUM_STAGE,
int DIN0_WIDTH, int DIN1_WIDTH=DIN0_WIDTH,
int DOUT_WIDTH=DIN0_WIDTH>
struct ACMP_ashr :
public AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>
{
public:
typedef sc_bigint<DIN0_WIDTH> OpDataTypeT1;
typedef sc_biguint<DIN1_WIDTH> OpDataTypeT2;
ACMP_ashr(const char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN0_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN0_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
OpDataTypeT1 ival0 = OpDataTypeT1(in0);
OpDataTypeT2 ival1 = sc_bv<DIN1_WIDTH>(in1.range(DIN1_WIDTH-1, 0));
OpDataTypeT1 outi = ival0 >> ival1;
return sc_lv<DOUT_WIDTH>(outi);
}
else
return sc_lv<DOUT_WIDTH>(SC_LOGIC_X);
}
};
#endif
// XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
#ifndef PE_H
#define PE_H
#include <iostream>
#include <fstream>
#include <cstdlib>
#include <iomanip>
#include <algorithm>
#include <vector>
#include "systemc.h"
using namespace std;
#define DEBUG_MODE true // You can change this value to get more information
#define TOTAL_PACKET_NUM 1 // Please don't change this value
struct Packet {
int source_id;
int dest_id;
vector<float> datas;
};
class PE {
public:
PE();
Packet* get_packet();
void check_packet(Packet* p);
void init(int pe_id);
private:
int id;
int send_count;
int recv_count;
vector<Packet> send_packets;
vector<Packet> recv_packets;
};
#endif
|
#include "systemc.h"
#include "define.h"
#include <iostream>
using namespace std;
SC_MODULE( Monitor ) {
sc_in_clk clk;
sc_in < bool > rst;
sc_in < DATA_TYPE > data_in;
sc_in < bool > data_valid;
void monitor();
int x, cycle;
SC_CTOR( Monitor )
{
x = 0;
cycle = 0;
SC_METHOD( monitor );
sensitive << clk.pos();
}
};
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> I2C0_SDA_I;
sc_core::sc_out<bool> I2C0_SDA_O;
sc_core::sc_out<bool> I2C0_SDA_T;
sc_core::sc_in<bool> I2C0_SCL_I;
sc_core::sc_out<bool> I2C0_SCL_O;
sc_core::sc_out<bool> I2C0_SCL_T;
sc_core::sc_in<bool> SDIO0_WP;
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
sc_core::sc_out<sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
sc_core::sc_out<sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
sc_core::sc_out<sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
sc_core::sc_out<sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
sc_core::sc_in<bool> S_AXI_HP0_ACLK;
sc_core::sc_in<bool> S_AXI_HP0_RDISSUECAP1_EN;
sc_core::sc_in<bool> S_AXI_HP0_WRISSUECAP1_EN;
sc_core::sc_in<sc_dt::sc_bv<2> > IRQ_F2P;
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
xtlm::xaximm_xtlm2tlm_t<64,32> S_AXI_HP0_xtlm_brdg;
xtlm::xtlm_aximm_fifo *S_AXI_HP0_buff;
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
void IRQ_F2P_method();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif
|
#include <systemc.h>
//
// Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
//
// .. hwt-autodoc::
//
SC_MODULE(Showcase0) {
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
};
void assig_process_c() {
c.write(static_cast<sc_uint<32>>(a.read() + static_cast<sc_uint<32>>(b.read())));
}
void assig_process_cmp_0() {
cmp_0.write(a.read() < sc_uint<32>("0x00000004"));
}
void assig_process_cmp_1() {
cmp_1.write(a.read() > sc_uint<32>("0x00000004"));
}
void assig_process_cmp_2() {
cmp_2.write(b.read() <= sc_int<32>("0x00000004"));
}
void assig_process_cmp_3() {
cmp_3.write(b.read() >= sc_int<32>("0x00000004"));
}
void assig_process_cmp_4() {
cmp_4.write(b.read() != sc_int<32>("0x00000004"));
}
void assig_process_cmp_5() {
cmp_5.write(b.read() == sc_int<32>("0x00000004"));
}
void assig_process_contOut() {
contOut.write(static_cast<sc_uint<32>>(const_private_signal));
}
void assig_process_f() {
f.write(r);
}
void assig_process_fallingEdgeRam() {
sc_signal<sc_uint<32>> tmpConcat_0;
tmpConcat_0.write((sc_uint<24>("0x000000"), static_cast<sc_uint<8>>(static_cast<sc_uint<8>>(fallingEdgeRam[r_1])), ));
{
(fallingEdgeRam[r_1]).write(static_cast<sc_int<8>>(a.read().range(sc_int<32>("0x00000008"), sc_int<32>("0x00000000"))));
k = tmpConcat_0.read();
}
}
void assig_process_fitted() {
fitted.write(static_cast<sc_uint<16>>(a.read().range(sc_int<32>("0x00000010"), sc_int<32>("0x00000000"))));
}
void assig_process_g() {
sc_signal<sc_uint<2>> tmpConcat_1;
sc_signal<sc_uint<8>> tmpConcat_0;
tmpConcat_1.write((a.read()[sc_int<32>("0x00000001")] & b.read()[sc_int<32>("0x00000001")], a.read()[sc_int<32>("0x00000000")] ^ b.read()[sc_int<32>("0x00000000")] | a.read()[sc_int<32>("0x00000001")], ));
tmpConcat_0.write((tmpConcat_1.read(), static_cast<sc_uint<6>>(a.read().range(sc_int<32>("0x00000006"), sc_int<32>("0x00000000"))), ));
g.write(tmpConcat_0.read());
}
void assig_process_h() {
if (a.read()[sc_int<32>("0x00000002")] == sc_uint<1>("0b1"))
if (r == sc_uint<1>("0b1"))
h.write(sc_uint<8>("0x00"));
else if (a.read()[sc_int<32>("0x00000001")] == sc_uint<1>("0b1"))
h.write(sc_uint<8>("0x01"));
else
h.write(sc_uint<8>("0x02"));
}
void assig_process_j() {
j = static_cast<sc_uint<8>>(rom[r_1]);
}
void assig_process_out() {
out.write(sc_uint<1>("0b0"));
}
void assig_process_output() {
output.write(sc_uint<1>("0bX"));
}
void assig_process_r() {
if (rst_n.read() == sc_uint<1>("0b0")) {
r_1 = sc_uint<2>("0b00");
r_0 = sc_uint<2>("0b00");
r = sc_uint<1>("0b0");
} else {
r_1 = r_next_1.read();
r_0 = r_next_0.read();
r = r_next.read();
}
}
void assig_process_r_next() {
r_next_0.write(i.read());
}
void assig_process_r_next_0() {
r_next_1.write(r_0);
}
void assig_process_r_next_1() {
if (r == sc_uint<1>("0b0"))
r_next.write(e.read());
else
r_next.write(r);
}
void assig_process_sc_signal_0() {
switch(a.read()) {
case sc_uint<32>("0x00000001"): {
sc_signal_0.write(sc_uint<8>("0x00"));
break;
}
case sc_uint<32>("0x00000002"): {
sc_signal_0.write(sc_uint<8>("0x01"));
break;
}
case sc_uint<32>("0x00000003"): {
sc_signal_0.write(sc_uint<8>("0x03"));
break;
}
default:
sc_signal_0.write(sc_uint<8>("0x04"));
}
}
SC_CTOR(Showcase0) {
SC_METHOD(assig_process_c);
sensitive << a << b;
SC_METHOD(assig_process_cmp_0);
sensitive << a;
SC_METHOD(assig_process_cmp_1);
sensitive << a;
SC_METHOD(assig_process_cmp_2);
sensitive << b;
SC_METHOD(assig_process_cmp_3);
sensitive << b;
SC_METHOD(assig_process_cmp_4);
sensitive << b;
SC_METHOD(assig_process_cmp_5);
sensitive << b;
assig_process_contOut();
SC_METHOD(assig_process_f);
sensitive << r;
SC_METHOD(assig_process_fallingEdgeRam);
sensitive << clk.neg();
SC_METHOD(assig_process_fitted);
sensitive << a;
SC_METHOD(assig_process_g);
sensitive << a << b;
SC_METHOD(assig_process_h);
sensitive << a << r;
SC_METHOD(assig_process_j);
sensitive << clk.pos();
assig_process_out();
assig_process_output();
SC_METHOD(assig_process_r);
sensitive << clk.pos();
SC_METHOD(assig_process_r_next);
sensitive << i;
SC_METHOD(assig_process_r_next_0);
sensitive << r_0;
SC_METHOD(assig_process_r_next_1);
sensitive << e << r;
SC_METHOD(assig_process_sc_signal_0);
sensitive << a;
// connect ports
}
};
|
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (DCT) of the 8x8 image.
* 3. Each transformed 8x8 block is divided by a quantization value for each block entry.
* 4. Each quantized 8x8 block is reordered by a Zig-Zag sequence into a array of size 64.
* *5. Entropy compression by variable length encoding (huffman). Used to maximize compression. Not implemented here.
*/
#define PI 3.1415926535897932384626433832795
#define BLOCK_ROWS 8
#define BLOCK_COLS 8
SC_MODULE (jpg_output) {
//-----------Internal variables-------------------
//const int Block_rows = 8;
//const int Block_cols = 8;
double* image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
//input variables
int pixel_value = 0;
int row = 0;
int col = 0;
//output variables
signed char *element;
int index = 0;
//compression variables
int *output_size = 0;
int quantificator[8][8] = { // quantization table
{16,11,10,16,24,40,51,61},
{12,12,14,19,26,58,60,55},
{14,13,16,24,40,57,69,56},
{14,17,22,29,51,87,80,62},
{18,22,37,56,68,109,103,77},
{24,35,55,64,81,104,113,92},
{49,64,78,87,103,121,120,101},
{72,92,95,98,112,100,103,99}};
int zigzag_index[64]={ // zigzag table
0,1,5,6,14,15,27,28,
2,4,7,13,16,26,29,42,
3,8,12,17,25,30,41,43,
9,11,18,24,31,40,44,53,
10,19,23,32,39,45,52,54,
20,22,33,38,46,51,55,60,
21,34,37,47,50,56,59,61,
35,36,48,49,57,58,62,63};
sc_event input_event, output_event, compression_event;
// Constructor for compressor
SC_HAS_PROCESS(jpg_output);
jpg_output(sc_module_name jpg_compressor, int im_rows = 480, int im_cols = 640): sc_module(jpg_compressor){
if(im_rows%BLOCK_ROWS==0) {image_rows=im_rows;}
else {image_rows=(im_rows/BLOCK_ROWS+1)*BLOCK_ROWS;}
if(im_cols%BLOCK_COLS==0) {image_cols=im_cols;}
else {image_cols=(im_cols/BLOCK_COLS+1)*BLOCK_COLS;}
image = new double[image_rows*image_cols];
//initialize the image matrix to avoid nan
for(int i=0; i<(image_rows*image_cols);i++){
image[i]=0;
}
SC_THREAD(input_operation);
SC_THREAD(output_operation);
SC_THREAD(compression_operation);
} // End of Constructor
//------------Code Starts Here-------------------------
void input_pixel(int pixel_value_local, int row_local, int col_local) {
pixel_value = pixel_value_local;
row = row_local;
col = col_local;
input_event.notify(8, SC_NS);
}
void input_operation(){
while(true) {
wait(output_event);
double* i_row = &image[row * image_cols];
i_row[col] = double(pixel_value);
}
}
//void OutputPixel(int *Pixel, int row, int col) {
// double* i_row = &image[row * image_cols];
// *Pixel = int(i_row[col]);
//}
void output_byte(signed char *element_local, int index_local) {
element = element_local;
index = index_local;
output_event.notify(8, SC_NS);
}
void output_operation(){
while(true) {
wait(output_event);
element[index] = image[index];
}
}
void jpeg_compression(int *output_size_local) {
output_size = output_size_local;
compression_event.notify(9000, SC_NS);
}
void compression_operation() {
while(true) {
wait(compression_event);
//Level shift
for(int i=0; i<(image_rows*image_cols);i++){
image[i]=image[i]-128;
}
int number_of_blocks = image_rows*image_cols/(BLOCK_ROWS*BLOCK_COLS);
int block_output[number_of_blocks][BLOCK_ROWS*BLOCK_COLS] = {0};
int block_output_size[number_of_blocks] = {0};
int block_counter = 0;
*output_size = 0;
for(int row=0; row<image_rows; row+=BLOCK_ROWS) {
double* i_row = &image[row * image_cols];
for(int col=0; col<image_cols; col+=BLOCK_COLS) { //Divided the image in 8×8 blocks
dct(row,col);
quantization(row,col);
zigzag(row,col,&block_output_size[block_counter],block_output[block_counter]);
*output_size += block_output_size[block_counter]+1;
block_counter++;
}
}
int output_counter = 0;
for(int block_index=0;block_index<number_of_blocks;block_index++){
for(int out_index=0; out_index<block_output_size[block_index];out_index++){
image[output_counter]=block_output[block_index][out_index];
output_counter++;
}
image[output_counter]=eob;
output_counter++;
}
}
}
void dct(int row_offset, int col_offset) {
double cos_table[BLOCK_ROWS][BLOCK_COLS];
for (int row = 0; row < BLOCK_ROWS; row++) //make the cosine table
{
for (int col = 0; col < BLOCK_COLS; col++) {
cos_table[row][col] = cos((((2*row)+1)*col*PI)/16);
}
}
double temp = 0.0;
for(int row=row_offset; row<row_offset+BLOCK_ROWS; row++)
{
double* i_row = &image[row * image_cols];
for(int col=col_offset; col<col_offset+BLOCK_COLS; col++) {
//i_row[col] = cos_table[row-row_offset][col-col_offset];
temp = 0.0;
for (int x = 0; x < 8; x++){
double* x_row = &image[(x+row_offset) * image_cols];
for (int y = 0; y < 8; y++) {
temp += x_row[y+col_offset] * cos_table[x][row-row_offset] * cos_table[y][col-col_offset];
}
}
if ((row-row_offset == 0) && (col-col_offset == 0)) {
temp /= 8.0;
}
else if (((row-row_offset == 0) && (col-col_offset != 0)) || ((row-row_offset != 0) && (col-col_offset == 0))){
temp /= (4.0*sqrt(2.0));
}
else {
temp /= 4.0;
}
i_row[col] = temp;
}
}
}
void quantization(int row_offset, int col_offset) {
for(int row=row_offset; row<row_offset+BLOCK_ROWS; row++)
{
double* i_row = &image[row * image_cols];
for(int col=col_offset; col<col_offset+BLOCK_COLS; col++) {
i_row[col] = round(i_row[col]/quantificator[row-row_offset][col-col_offset]);
}
}
}
void zigzag(int row_offset, int col_offset, int *block_output_size, int *block_output) {
int index_last_non_zero_value = 0; // index to last non-zero in a block zigzag array
for(int row=row_offset; row<row_offset+BLOCK_ROWS; row++)
{
double* i_row = &image[row * image_cols];
for(int col=col_offset; col<col_offset+BLOCK_COLS; col++) {
int temp_index = zigzag_index[(row-row_offset)*8+(col-col_offset)];
block_output[temp_index]=i_row[col];
if(i_row[col] !=0 && temp_index>index_last_non_zero_value) {index_last_non_zero_value = temp_index+1;}
}
}
*block_output_size = index_last_non_zero_value;
}
};
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_23_H_
#define _design_1_xlconstant_0_23_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_23 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_23 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Seuil_calc_do_gen_HH_
#define _Seuil_calc_do_gen_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Seuil_calc_fadd_3dEe.h"
#include "Seuil_calc_fmul_3eOg.h"
#include "Seuil_calc_fdiv_3fYi.h"
#include "Seuil_calc_uitofpg8j.h"
#include "Seuil_calc_fcmp_3hbi.h"
namespace ap_rtl {
struct Seuil_calc_do_gen : public sc_module {
// Port declarations 8
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_lv<8> > e_dout;
sc_in< sc_logic > e_empty_n;
sc_out< sc_logic > e_read;
sc_out< sc_logic > detect_din;
sc_in< sc_logic > detect_full_n;
sc_out< sc_logic > detect_write;
sc_signal< sc_lv<32> > ap_var_for_const0;
sc_signal< sc_lv<32> > ap_var_for_const1;
sc_signal< sc_lv<32> > ap_var_for_const2;
sc_signal< sc_lv<5> > ap_var_for_const3;
// Module declarations
Seuil_calc_do_gen(sc_module_name name);
SC_HAS_PROCESS(Seuil_calc_do_gen);
~Seuil_calc_do_gen();
sc_trace_file* mVcdFile;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U22;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U23;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U24;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U25;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U26;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U27;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U28;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U29;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U30;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U31;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U32;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U33;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U34;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U35;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U36;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U37;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U38;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U39;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U40;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U41;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U42;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U43;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U44;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U45;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U46;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U47;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U48;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U49;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U50;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U51;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U52;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U53;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U54;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U55;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U56;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U57;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U58;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U59;
Seuil_calc_fadd_3dEe<1,5,32,32,32>* Seuil_calc_fadd_3dEe_U60;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U61;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U62;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U63;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U64;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U65;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U66;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U67;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U68;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U69;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U70;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U71;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U72;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U73;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U74;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U75;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U76;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U77;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U78;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U79;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U80;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U81;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U82;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U83;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U84;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U85;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U86;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U87;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U88;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U89;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U90;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U91;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U92;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U93;
Seuil_calc_fmul_3eOg<1,4,32,32,32>* Seuil_calc_fmul_3eOg_U94;
Seuil_calc_fdiv_3fYi<1,16,32,32,32>* Seuil_calc_fdiv_3fYi_U95;
Seuil_calc_uitofpg8j<1,6,32,32>* Seuil_calc_uitofpg8j_U96;
Seuil_calc_fcmp_3hbi<1,2,32,32,1>* Seuil_calc_fcmp_3hbi_U97;
sc_signal< sc_logic > e_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter25;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_logic > detect_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter186;
sc_signal< sc_lv<32> > buffer_load_reg_998;
sc_signal< sc_lv<2> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< bool > ap_block_state2_pp0_stage0_iter0;
sc_signal< bool > ap_block_state3_pp0_stage0_iter1;
sc_signal< bool > ap_block_state4_pp0_stage0_iter2;
sc_signal< bool > ap_block_state5_pp0_stage0_iter3;
sc_signal< bool > ap_block_state6_pp0_stage0_iter4;
sc_signal< bool > ap_block_state7_pp0_stage0_iter5;
sc_signal< bool > ap_block_state8_pp0_stage0_iter6;
sc_signal< bool > ap_block_state9_pp0_stage0_iter7;
sc_signal< bool > ap_block_state10_pp0_stage0_iter8;
sc_signal< bool > ap_block_state11_pp0_stage0_iter9;
sc_signal< bool > ap_block_state12_pp0_stage0_iter10;
sc_signal< bool > ap_block_state13_pp0_stage0_iter11;
sc_signal< bool > ap_block_state14_pp0_stage0_iter12;
sc_signal< bool > ap_block_state15_pp0_stage0_iter13;
sc_signal< bool > ap_block_state16_pp0_stage0_iter14;
sc_signal< bool > ap_block_state17_pp0_stage0_iter15;
sc_signal< bool > ap_block_state18_pp0_stage0_iter16;
sc_signal< bool > ap_block_state19_pp0_stage0_iter17;
sc_signal< bool > ap_block_state20_pp0_stage0_iter18;
sc_signal< bool > ap_block_state21_pp0_stage0_iter19;
sc_signal< bool > ap_block_state22_pp0_stage0_iter20;
sc_signal< bool > ap_block_state23_pp0_stage0_iter21;
sc_signal< bool > ap_block_state24_pp0_stage0_iter22;
sc_signal< bool > ap_block_state25_pp0_stage0_iter23;
sc_signal< bool > ap_block_state26_pp0_stage0_iter24;
sc_signal< bool > ap_block_state27_pp0_stage0_iter25;
sc_signal< bool > ap_block_state28_pp0_stage0_iter26;
sc_signal< bool > ap_block_state29_pp0_stage0_iter27;
sc_signal< bool > ap_block_state30_pp0_stage0_iter28;
sc_signal< bool > ap_block_state31_pp0_stage0_iter29;
sc_signal< bool > ap_block_state32_pp0_stage0_iter30;
sc_signal< bool > ap_block_state33_pp0_stage0_iter31;
sc_signal< bool > ap_block_state34_pp0_stage0_iter32;
sc_signal< bool > ap_block_state35_pp0_stage0_iter33;
sc_signal< bool > ap_block_state36_pp0_stage0_iter34;
sc_signal< bool > ap_block_state37_pp0_stage0_iter35;
sc_signal< bool > ap_block_state38_pp0_stage0_iter36;
sc_signal< bool > ap_block_state39_pp0_stage0_iter37;
sc_signal< bool > ap_block_state40_pp0_stage0_iter38;
sc_signal< bool > ap_block_state41_pp0_stage0_iter39;
sc_signal< bool > ap_block_state42_pp0_stage0_iter40;
sc_signal< bool > ap_block_state43_pp0_stage0_iter41;
sc_signal< bool > ap_block_state44_pp0_stage0_iter42;
sc_signal< bool > ap_block_state45_pp0_stage0_iter43;
sc_signal< bool > ap_block_state46_pp0_stage0_iter44;
sc_signal< bool > ap_block_state47_pp0_stage0_iter45;
sc_signal< bool > ap_block_state48_pp0_stage0_iter46;
sc_signal< bool > ap_block_state49_pp0_stage0_iter47;
sc_signal< bool > ap_block_state50_pp0_stage0_iter48;
sc_signal< bool > ap_block_state51_pp0_stage0_iter49;
sc_signal< bool > ap_block_state52_pp0_stage0_iter50;
sc_signal< bool > ap_block_state53_pp0_stage0_iter51;
sc_signal< bool > ap_block_state54_pp0_stage0_iter52;
sc_signal< bool > ap_block_state55_pp0_stage0_iter53;
sc_signal< bool > ap_block_state56_pp0_stage0_iter54;
sc_signal< bool > ap_block_state57_pp0_stage0_iter55;
sc_signal< bool > ap_block_state58_pp0_stage0_iter56;
sc_signal< bool > ap_block_state59_pp0_stage0_iter57;
sc_signal< bool > ap_block_state60_pp0_stage0_iter58;
sc_signal< bool > ap_block_state61_pp0_stage0_iter59;
sc_signal< bool > ap_block_state62_pp0_stage0_iter60;
sc_signal< bool > ap_block_state63_pp0_stage0_iter61;
sc_signal< bool > ap_block_state64_pp0_stage0_iter62;
sc_signal< bool > ap_block_state65_pp0_stage0_iter63;
sc_signal< bool > ap_block_state66_pp0_stage0_iter64;
sc_signal< bool > ap_block_state67_pp0_stage0_iter65;
sc_signal< bool > ap_block_state68_pp0_stage0_iter66;
sc_signal< bool > ap_block_state69_pp0_stage0_iter67;
sc_signal< bool > ap_block_state70_pp0_stage0_iter68;
sc_signal< bool > ap_block_state71_pp0_stage0_iter69;
sc_signal< bool > ap_block_state72_pp0_stage0_iter70;
sc_signal< bool > ap_block_state73_pp0_stage0_iter71;
sc_signal< bool > ap_block_state74_pp0_stage0_iter72;
sc_signal< bool > ap_block_state75_pp0_stage0_iter73;
sc_signal< bool > ap_block_state76_pp0_stage0_iter74;
sc_signal< bool > ap_block_state77_pp0_stage0_iter75;
sc_signal< bool > ap_block_state78_pp0_stage0_iter76;
sc_signal< bool > ap_block_state79_pp0_stage0_iter77;
sc_signal< bool > ap_block_state80_pp0_stage0_iter78;
sc_signal< bool > ap_block_state81_pp0_stage0_iter79;
sc_signal< bool > ap_block_state82_pp0_stage0_iter80;
sc_signal< bool > ap_block_state83_pp0_stage0_iter81;
sc_signal< bool > ap_block_state84_pp0_stage0_iter82;
sc_signal< bool > ap_block_state85_pp0_stage0_iter83;
sc_signal< bool > ap_block_state86_pp0_stage0_iter84;
sc_signal< bool > ap_block_state87_pp0_stage0_iter85;
sc_signal< bool > ap_block_state88_pp0_stage0_iter86;
sc_signal< bool > ap_block_state89_pp0_stage0_iter87;
sc_signal< bool > ap_block_state90_pp0_stage0_iter88;
sc_signal< bool > ap_block_state91_pp0_stage0_iter89;
sc_signal< bool > ap_block_state92_pp0_stage0_iter90;
sc_signal< bool > ap_block_state93_pp0_stage0_iter91;
sc_signal< bool > ap_block_state94_pp0_stage0_iter92;
sc_signal< bool > ap_block_state95_pp0_stage0_iter93;
sc_signal< bool > ap_block_state96_pp0_stage0_iter94;
sc_signal< bool > ap_block_state97_pp0_stage0_iter95;
sc_signal< bool > ap_block_state98_pp0_stage0_iter96;
sc_signal< bool > ap_block_state99_pp0_stage0_iter97;
sc_signal< bool > ap_block_state100_pp0_stage0_iter98;
sc_signal< bool > ap_block_state101_pp0_stage0_iter99;
sc_signal< bool > ap_block_state102_pp0_stage0_iter100;
sc_signal< bool > ap_block_state103_pp0_stage0_iter101;
sc_signal< bool > ap_block_state104_pp0_stage0_iter102;
sc_signal< bool > ap_block_state105_pp0_stage0_iter103;
sc_signal< bool > ap_block_state106_pp0_stage0_iter104;
sc_signal< bool > ap_block_state107_pp0_stage0_iter105;
sc_signal< bool > ap_block_state108_pp0_stage0_iter106;
sc_signal< bool > ap_block_state109_pp0_stage0_iter107;
sc_signal< bool > ap_block_state110_pp0_stage0_iter108;
sc_signal< bool > ap_block_state111_pp0_stage0_iter109;
sc_signal< bool > ap_block_state112_pp0_stage0_iter110;
sc_signal< bool > ap_block_state113_pp0_stage0_iter111;
sc_signal< bool > ap_block_state114_pp0_stage0_iter112;
sc_signal< bool > ap_block_state115_pp0_stage0_iter113;
sc_signal< bool > ap_block_state116_pp0_stage0_iter114;
sc_signal< bool > ap_block_state117_pp0_stage0_iter115;
sc_signal< bool > ap_block_state118_pp0_stage0_iter116;
sc_signal< bool > ap_block_state119_pp0_stage0_iter117;
sc_signal< bool > ap_block_state120_pp0_stage0_iter118;
sc_signal< bool > ap_block_state121_pp0_stage0_iter119;
sc_signal< bool > ap_block_state122_pp0_stage0_iter120;
sc_signal< bool > ap_block_state123_pp0_stage0_iter121;
sc_signal< bool > ap_block_state124_pp0_stage0_iter122;
sc_signal< bool > ap_block_state125_pp0_stage0_iter123;
sc_signal< bool > ap_block_state126_pp0_stage0_iter124;
sc_signal< bool > ap_block_state127_pp0_stage0_iter125;
sc_signal< bool > ap_block_state128_pp0_stage0_iter126;
sc_signal< bool > ap_block_state129_pp0_stage0_iter127;
sc_signal< bool > ap_block_state130_pp0_stage0_iter128;
sc_signal< bool > ap_block_state131_pp0_stage0_iter129;
sc_signal< bool > ap_block_state132_pp0_stage0_iter130;
sc_signal< bool > ap_block_state133_pp0_stage0_iter131;
sc_signal< bool > ap_block_state134_pp0_stage0_iter132;
sc_signal< bool > ap_block_state135_pp0_stage0_iter133;
sc_signal< bool > ap_block_state136_pp0_stage0_iter134;
sc_signal< bool > ap_block_state137_pp0_stage0_iter135;
sc_signal< bool > ap_block_state138_pp0_stage0_iter136;
sc_signal< bool > ap_block_state139_pp0_stage0_iter137;
sc_signal< bool > ap_block_state140_pp0_stage0_iter138;
sc_signal< bool > ap_block_state141_pp0_stage0_iter139;
sc_signal< bool > ap_block_state142_pp0_stage0_iter140;
sc_signal< bool > ap_block_state143_pp0_stage0_iter141;
sc_signal< bool > ap_block_state144_pp0_stage0_iter142;
sc_signal< bool > ap_block_state145_pp0_stage0_iter143;
sc_signal< bool > ap_block_state146_pp0_stage0_iter144;
sc_signal< bool > ap_block_state147_pp0_stage0_iter145;
sc_signal< bool > ap_block_state148_pp0_stage0_iter146;
sc_signal< bool > ap_block_state149_pp0_stage0_iter147;
sc_signal< bool > ap_block_state150_pp0_stage0_iter148;
sc_signal< bool > ap_block_state151_pp0_stage0_iter149;
sc_signal< bool > ap_block_state152_pp0_stage0_iter150;
sc_signal< bool > ap_block_state153_pp0_stage0_iter151;
sc_signal< bool > ap_block_state154_pp0_stage0_iter152;
sc_signal< bool > ap_block_state155_pp0_stage0_iter153;
sc_signal< bool > ap_block_state156_pp0_stage0_iter154;
sc_signal< bool > ap_block_state157_pp0_stage0_iter155;
sc_signal< bool > ap_block_state158_pp0_stage0_iter156;
sc_signal< bool > ap_block_state159_pp0_stage0_iter157;
sc_signal< bool > ap_block_state160_pp0_stage0_iter158;
sc_signal< bool > ap_block_state161_pp0_stage0_iter159;
sc_signal< bool > ap_block_state162_pp0_stage0_iter160;
sc_signal< bool > ap_block_state163_pp0_stage0_iter161;
sc_signal< bool > ap_block_state164_pp0_stage0_iter162;
sc_signal< bool > ap_block_state165_pp0_stage0_iter163;
sc_signal< bool > ap_block_state166_pp0_stage0_iter164;
sc_signal< bool > ap_block_state167_pp0_stage0_iter165;
sc_signal< bool > ap_block_state168_pp0_stage0_iter166;
sc_signal< bool > ap_block_state169_pp0_stage0_iter167;
sc_signal< bool > ap_block_state170_pp0_stage0_iter168;
sc_signal< bool > ap_block_state171_pp0_stage0_iter169;
sc_signal< bool > ap_block_state172_pp0_stage0_iter170;
sc_signal< bool > ap_block_state173_pp0_stage0_iter171;
sc_signal< bool > ap_block_state174_pp0_stage0_iter172;
sc_signal< bool > ap_block_state175_pp0_stage0_iter173;
sc_signal< bool > ap_block_state176_pp0_stage0_iter174;
sc_signal< bool > ap_block_state177_pp0_stage0_iter175;
sc_signal< bool > ap_block_state178_pp0_stage0_iter176;
sc_signal< bool > ap_block_state179_pp0_stage0_iter177;
sc_signal< bool > ap_block_state180_pp0_stage0_iter178;
sc_signal< bool > ap_block_state181_pp0_stage0_iter179;
sc_signal< bool > ap_block_state182_pp0_stage0_iter180;
sc_signal< bool > ap_block_state183_pp0_stage0_iter181;
sc_signal< bool > ap_block_state184_pp0_stage0_iter182;
sc_signal< bool > ap_block_state185_pp0_stage0_iter183;
sc_signal< bool > ap_block_state186_pp0_stage0_iter184;
sc_signal< bool > ap_block_state187_pp0_stage0_iter185;
sc_signal< bool > ap_block_state188_pp0_stage0_iter186;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<32> > buffer_load_reg_998_pp0_iter1_reg;
sc_signal< sc_lv<32> > buffer_load_reg_998_pp0_iter2_reg;
sc_signal< sc_lv<32> > buffer_load_reg_998_pp0_iter3_reg;
sc_signal< sc_lv<32> > buffer_load_reg_998_pp0_iter4_reg;
sc_signal< sc_lv<32> > buffer_load_1_reg_1005;
sc_signal< sc_lv<32> > buffer_load_1_reg_1005_pp0_iter2_reg;
sc_signal< sc_lv<32> > buffer_load_1_reg_1005_pp0_iter3_reg;
sc_signal< sc_lv<32> > buffer_load_1_reg_1005_pp0_iter4_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter3_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter4_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter5_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter6_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter7_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter8_reg;
sc_signal< sc_lv<32> > buffer_load_2_reg_1012_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter4_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter5_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter6_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter7_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter8_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter10_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_3_reg_1018_pp0_iter14_reg;
sc_signal< sc_lv<32> > grp_fu_370_p2;
sc_signal< sc_lv<32> > sqrv_reg_1024;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter5_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter6_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter7_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter8_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter10_reg;
sc_
|
signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter6_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter7_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter8_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter10_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_5_reg_1036_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter7_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter8_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter10_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_6_reg_1043_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter8_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter10_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_7_reg_1049_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter9_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter10_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_8_reg_1055_pp0_iter39_reg;
sc_signal< sc_lv<32> > grp_fu_213_p2;
sc_signal< sc_lv<32> > sum_1_reg_1061;
sc_signal< sc_lv<32> > grp_fu_374_p2;
sc_signal< sc_lv<32> > sqrv_1_reg_1066;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter10_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_9_reg_1071_pp0_iter44_reg;
sc_signal< sc_lv<32> > grp_fu_218_p2;
sc_signal< sc_lv<32> > tmp_1_reg_1077;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter10_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter11_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter12_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter13_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter14_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter15_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter16_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter17_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter18_reg;
sc_signal< sc_lv<32> > tmp_1_reg_1077_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_10_reg_1082_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_11_reg_1088_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_12_reg_1094_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_l
|
oad_13_reg_1100_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter64_reg;
sc_signal< sc_lv<32> > grp_fu_222_p2;
sc_signal< sc_lv<32> > sum_1_1_reg_1106;
sc_signal< sc_lv<32> > grp_fu_378_p2;
sc_signal< sc_lv<32> > sqrv_2_reg_1111;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter15_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_14_reg_1116_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter16_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_15_reg_1123_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter17_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_16_reg_1130_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter18_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_17_reg_1136_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter19_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load
|
_18_reg_1142_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter89_reg;
sc_signal< sc_lv<32> > grp_fu_226_p2;
sc_signal< sc_lv<32> > sum_1_2_reg_1149;
sc_signal< sc_lv<32> > grp_fu_382_p2;
sc_signal< sc_lv<32> > sqrv_3_reg_1154;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter20_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_19_reg_1159_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter21_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_20_reg_1166_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter95_reg;
sc_sign
|
al< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_22_reg_1178_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_23_reg_1184_pp0_iter114_reg;
sc_signal< sc_lv<32> > grp_fu_230_p2;
sc_signal< sc_lv<32> > sum_1_3_reg_1190;
sc_signal< sc_lv<32> > grp_fu_386_p2;
sc_signal< sc_lv<32> > sqrv_4_reg_1195;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_24_reg_1200_pp0_iter119_reg;
sc_signal< sc_lv<32> > grp_fu_234_p2;
sc_signal< sc_lv<32> > tmp_2_reg_1206;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter34_reg
|
;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter119_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter120_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter121_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter122_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter123_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter124_reg;
sc_signal< sc_lv<8> > val_V_reg_1217;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter119_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter120_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter121_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter122_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter123_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter124_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter125_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter126_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter127_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter128_reg;
sc_signal< sc_lv<32> > buffer_load_26_reg_1222_pp0_iter129_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter28_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter119_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter120_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter121_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter122_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter123_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter124_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter125_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter126_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter127_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter128_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter129_reg;
|
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter130_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter131_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter132_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter133_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter134_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter29_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter119_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter120_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter121_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter122_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter123_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter124_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter125_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter126_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter127_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter128_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter129_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter130_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter131_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter132_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter133_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter134_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter135_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter136_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter137_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter138_reg;
sc_signal< sc_lv<32> > buffer_load_28_reg_1239_pp0_iter139_reg;
sc_signal< sc_lv<32> > grp_fu_238_p2;
sc_signal< sc_lv<32> > sum_1_4_reg_1245;
sc_signal< sc_lv<32> > grp_fu_390_p2;
sc_signal< sc_lv<32> > sqrv_5_reg_1250;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter30_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter55_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter119_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter120_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter121_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter122_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter123_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter124_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter125_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter126_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter127_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter128_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter129_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter130_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter131_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter132_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter133_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter134_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter135_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter136_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter137_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter138_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter139_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter140_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter141_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter142_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter143_reg;
sc_signal< sc_lv<32> > buffer_load_29_reg_1255_pp0_iter144_reg;
sc_signal< sc_lv<32> > grp_fu_242_p2;
sc_signal< sc_lv<32> > tmp_3_reg_1261;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter30_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter31_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter32_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter33_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter34_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter35_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter36_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter37_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter38_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter39_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter40_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter41_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter42_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter43_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter44_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter45_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter46_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter47_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter48_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter49_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter50_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter51_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter52_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter53_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter54_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter55_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter56_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter57_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter58_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter59_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter60_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter61_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter62_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter63_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter64_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter65_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter66_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter67_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter68_reg;
sc_signal< sc_lv<32> > tmp_3_reg_1261_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter31_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter32_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter33_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter34_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter39_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter40_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter41_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter42_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter43_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter44_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter45_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter46_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter47_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter48_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter49_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter50_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter51_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter52_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter53_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter54_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter55_reg;
sc_signal< sc_lv<32> >
|
buffer_load_30_reg_1266_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter60_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter61_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter62_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter63_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter64_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter65_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter66_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter67_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter68_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter69_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter70_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter71_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter72_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter73_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter74_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter75_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter76_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter77_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter78_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter79_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter80_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter81_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter82_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter83_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter84_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter85_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter86_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter87_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter88_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter89_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter90_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter91_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter92_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter93_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter94_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter95_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter100_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter101_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter102_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter103_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter104_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter105_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter106_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter107_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter108_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter109_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter110_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter111_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter112_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter113_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter114_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter115_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter116_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter117_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter118_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter119_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter120_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter121_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter122_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter123_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter124_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter125_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter126_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter127_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter128_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter129_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter130_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter131_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter132_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter133_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter134_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter135_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter136_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter137_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter138_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter139_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter140_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter141_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter142_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter143_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter144_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter145_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter146_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter147_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter148_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter149_reg;
sc_signal< sc_lv<32> > grp_fu_511_p1;
sc_signal< sc_lv<32> > tmp_reg_1272;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter32_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter33_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter34_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter35_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter36_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter37_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter38_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter39_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter40_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter41_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter42_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter43_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter44_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter45_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter46_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter47_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter48_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter49_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter50_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter51_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter52_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter53_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter54_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter55_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter56_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter57_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter58_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter59_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter60_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter61_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter62_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter63_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter64_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter65_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter66_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter67_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter68_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter69_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter70_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter71_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter72_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter73_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter74_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter75_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter76_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter77_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter78_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter79_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter80_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter81_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter82_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter83_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter84_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter85_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter86_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter87_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter88_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter89_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter90_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter91_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter92_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter93_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter94_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter95_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter96_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter97_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter98_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter99_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter100_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter101_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter102_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter103_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter104_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter105_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter106_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter107_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter108_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter109_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter110_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter111_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter112_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter113_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter114_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter115_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter116_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter117_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter118_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter119_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter120_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter121_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter122_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter123_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter124_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter125_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter126_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter127_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter128_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter129_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter130_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter131_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter132_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter133_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter134_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter135_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter136_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter137_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter138_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter139_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter140_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter141_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter142_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter143_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter144_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter145_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter146_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter147_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter148_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter149_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter150_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter151_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter152_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter153_reg;
sc_signal< sc_lv<32> > tmp_reg_1272_pp0_iter154_reg;
sc_signal< sc_lv<32> > grp_fu_246_p2;
sc_signal< sc_lv<32> > sum_1_5_reg_1278;
sc_signal< sc_lv<32> > grp_fu_394_p2;
sc_signal< sc_lv<32> > sqrv_6_reg_1283;
sc_signal< sc_lv<32> > grp_fu_250_p2;
sc_signal< sc_lv<32> > sum_1_6_reg_1288;
sc_signal< sc_lv<32> > grp_fu_398_p2;
sc_signal< sc_lv<32> > sqrv_7_reg_1293;
sc_signal< sc_lv<32> > grp_fu_254_p2;
sc_signal< sc_lv<32> > sum_1_7_reg_1298;
sc_signal< sc_lv<32> > grp_fu_402_p2;
sc_signal< sc_lv<32> > sqrv_8_reg_1303;
sc_signal< sc_lv<32> > grp_fu_258_p2;
sc_signal< sc_lv<32> > sum_1_8_reg_1308;
sc_signal< sc_lv<32> > grp_fu_406_p2;
sc_signal< sc_lv<32> > sqrv_9_reg_1313;
sc_signal< sc_lv<32> > grp_fu_262_p2;
sc_signal< sc_lv<32> > sum_1_9_reg_1318;
sc_signal< sc_lv<32> > grp_fu_410_p2;
sc_signal< sc_lv<32> > sqrv_s_reg_1323;
sc_signal< sc_lv<32> > grp_fu_266_p2;
sc_signal< sc_lv<32> > sum_1_s_reg_1328;
sc_signal< sc_lv<32> > grp_fu_414_p2;
sc_signal< sc_lv<32> > sqrv_10_reg_1333;
sc_signal< sc_lv<32> > grp_fu_270_p2;
sc_signal< sc_lv<32> > sum_1_10_reg_1338;
sc_signal< sc_lv<32> > grp_fu_418_p2;
sc_signal< sc_lv<32> > sqrv_11_reg_1343;
sc_signal< sc_lv<32> > grp_fu_274_p2;
sc_signal< sc_lv<32> > sum_1_11_reg_1348;
sc_signal< sc_lv<32> > grp_fu_422_p2;
sc_signal< sc_lv<32> > sqrv_12_reg_1353;
sc_signal< sc_lv<32> > grp_fu_278_p2;
sc_signal< sc_lv<32> > sum_1_12_reg_1358;
sc_signal< sc_lv<32> > grp_fu_426_p2;
sc_signal< sc_lv<32> > sqrv_13_reg_1363;
sc_signal< sc_lv<32> > grp_fu_282_p2;
sc_signal< sc_lv<32> > tmp_4_reg_1368;
sc_signal< sc_lv<32> > grp_fu_286_p2;
sc_signal< sc_lv<32> > sum_1_13_reg_1373;
sc_signal< sc_lv<32> > grp_fu_430_p2;
sc_signal< sc_lv<32> > sqrv_14_reg_1378;
sc_signal< sc_lv<32> > grp_fu_290_p2;
sc_signal< sc_lv<32> > tmp_5_reg_1383;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter80_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter81_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter82_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter83_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter84_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter85_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter86_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter87_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter88_reg;
sc_signal< sc_lv<32> > tmp_5_reg_1383_pp0_iter89_reg;
sc_signal< sc_lv<32> > grp_fu_294_p2;
sc_signal< sc_lv<32> > sum_1_14_reg_1388;
sc_signal< sc_lv<32> > grp_fu_434_p2;
sc_signal< sc_lv<32> > sqrv_15_reg_1393;
sc_signal< sc_lv<32> > grp_fu_298_p2;
sc_signal< sc_lv<32> > sum_1_15_reg_1398;
sc_signal< sc_lv<32> > grp_fu_438_p2;
sc_signal< sc_lv<32> > sqrv_16_reg_1403;
sc_signal< sc_lv<32> > grp_fu_302_p2;
sc_signal< sc_lv<32> > sum_1_16_reg_1408;
sc_signal< sc_lv<32> > grp_fu_442_p2;
sc_signal< sc_lv<32> > sqrv_17_reg_1413;
sc_signal< sc_lv<32> > grp_fu_306_p2;
sc_signal< sc_lv<32> > tmp_6_reg_1418;
sc_signal< sc_lv<32> > grp_fu_310_p2;
sc_signal< sc_lv<32> > sum_1_17_reg_1423;
sc_signal< sc_lv<32> > grp_fu_446_p2;
sc_signal< sc_lv<32> > sqrv_18_reg_1428;
sc_signal< sc_lv<32> > grp_fu_314_p2;
sc_signal< sc_lv<32> > ps_reg_1433;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter100_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter101_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter102_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter103_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter104_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter105_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter106_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter107_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter108_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter109_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter110_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter111_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter112_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter113_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter114_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter115_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter116_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter117_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter118_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter119_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter120_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter121_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter122_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter123_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter124_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter125_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter126_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter127_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter128_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter129_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter130_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter131_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter132_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter133_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter134_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter135_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter136_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter137_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter138_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter139_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter140_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter141_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter142_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter143_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter144_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter145_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter146_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter147_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter148_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter149_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter150_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter151_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter152_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter153_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter154_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter155_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter156_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter157_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter1
|
58_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter159_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter160_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter161_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter162_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter163_reg;
sc_signal< sc_lv<32> > grp_fu_318_p2;
sc_signal< sc_lv<32> > sum_1_18_reg_1439;
sc_signal< sc_lv<32> > grp_fu_450_p2;
sc_signal< sc_lv<32> > sqrv_19_reg_1444;
sc_signal< sc_lv<32> > grp_fu_322_p2;
sc_signal< sc_lv<32> > sum_1_19_reg_1449;
sc_signal< sc_lv<32> > grp_fu_454_p2;
sc_signal< sc_lv<32> > sqrv_20_reg_1454;
sc_signal< sc_lv<32> > grp_fu_326_p2;
sc_signal< sc_lv<32> > sum_1_20_reg_1459;
sc_signal< sc_lv<32> > grp_fu_458_p2;
sc_signal< sc_lv<32> > sqrv_21_reg_1464;
sc_signal< sc_lv<32> > grp_fu_330_p2;
sc_signal< sc_lv<32> > sum_1_21_reg_1469;
sc_signal< sc_lv<32> > grp_fu_462_p2;
sc_signal< sc_lv<32> > sqrv_22_reg_1474;
sc_signal< sc_lv<32> > grp_fu_334_p2;
sc_signal< sc_lv<32> > sum_1_22_reg_1479;
sc_signal< sc_lv<32> > grp_fu_466_p2;
sc_signal< sc_lv<32> > sqrv_23_reg_1484;
sc_signal< sc_lv<32> > grp_fu_338_p2;
sc_signal< sc_lv<32> > sum_1_23_reg_1489;
sc_signal< sc_lv<32> > grp_fu_470_p2;
sc_signal< sc_lv<32> > sqrv_24_reg_1494;
sc_signal< sc_lv<32> > grp_fu_342_p2;
sc_signal< sc_lv<32> > sum_1_24_reg_1499;
sc_signal< sc_lv<32> > grp_fu_474_p2;
sc_signal< sc_lv<32> > sqrv_25_reg_1504;
sc_signal< sc_lv<32> > grp_fu_346_p2;
sc_signal< sc_lv<32> > sum_1_25_reg_1509;
sc_signal< sc_lv<32> > grp_fu_478_p2;
sc_signal< sc_lv<32> > sqrv_26_reg_1514;
sc_signal< sc_lv<32> > grp_fu_350_p2;
sc_signal< sc_lv<32> > sum_1_26_reg_1519;
sc_signal< sc_lv<32> > grp_fu_482_p2;
sc_signal< sc_lv<32> > sqrv_27_reg_1524;
sc_signal< sc_lv<32> > grp_fu_354_p2;
sc_signal< sc_lv<32> > sum_1_27_reg_1529;
sc_signal< sc_lv<32> > grp_fu_486_p2;
sc_signal< sc_lv<32> > sqrv_28_reg_1534;
sc_signal< sc_lv<32> > grp_fu_358_p2;
sc_signal< sc_lv<32> > sum_1_28_reg_1539;
sc_signal< sc_lv<32> > grp_fu_490_p2;
sc_signal< sc_lv<32> > sqrv_29_reg_1544;
sc_signal< sc_lv<32> > grp_fu_362_p2;
sc_signal< sc_lv<32> > sum_1_29_reg_1549;
sc_signal< sc_lv<32> > grp_fu_494_p2;
sc_signal< sc_lv<32> > sqrv_30_reg_1554;
sc_signal< sc_lv<32> > grp_fu_366_p2;
sc_signal< sc_lv<32> > sum_1_30_reg_1559;
sc_signal< sc_lv<32> > grp_fu_498_p2;
sc_signal< sc_lv<32> > sum_reg_1564;
sc_signal< sc_lv<32> > grp_fu_503_p2;
sc_signal< sc_lv<32> > tmp_8_reg_1569;
sc_signal< sc_lv<32> > grp_fu_507_p2;
sc_signal< sc_lv<32> > res_reg_1574;
sc_signal< sc_lv<1> > icmp_ln68_fu_790_p2;
sc_signal< sc_lv<1> > icmp_ln68_reg_1580;
sc_signal< sc_lv<1> > icmp_ln68_1_fu_796_p2;
sc_signal< sc_lv<1> > icmp_ln68_1_reg_1585;
sc_signal< sc_lv<1> > and_ln68_fu_806_p2;
sc_signal< sc_lv<1> > and_ln68_reg_1590;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_logic > ap_enable_reg_pp0_iter5;
sc_signal< sc_logic > ap_enable_reg_pp0_iter6;
sc_signal< sc_logic > ap_enable_reg_pp0_iter7;
sc_signal< sc_logic > ap_enable_reg_pp0_iter8;
sc_signal< sc_logic > ap_enable_reg_pp0_iter9;
sc_signal< sc_logic > ap_enable_reg_pp0_iter10;
sc_signal< sc_logic > ap_enable_reg_pp0_iter11;
sc_signal< sc_logic > ap_enable_reg_pp0_iter12;
sc_signal< sc_logic > ap_enable_reg_pp0_iter13;
sc_signal< sc_logic > ap_enable_reg_pp0_iter14;
sc_signal< sc_logic > ap_enable_reg_pp0_iter15;
sc_signal< sc_logic > ap_enable_reg_pp0_iter16;
sc_signal< sc_logic > ap_enable_reg_pp0_iter17;
sc_signal< sc_logic > ap_enable_reg_pp0_iter18;
sc_signal< sc_logic > ap_enable_reg_pp0_iter19;
sc_signal< sc_logic > ap_enable_reg_pp0_iter20;
sc_signal< sc_logic > ap_enable_reg_pp0_iter21;
sc_signal< sc_logic > ap_enable_reg_pp0_iter22;
sc_signal< sc_logic > ap_enable_reg_pp0_iter23;
sc_signal< sc_logic > ap_enable_reg_pp0_iter24;
sc_signal< sc_logic > ap_enable_reg_pp0_iter26;
sc_signal< sc_logic > ap_enable_reg_pp0_iter27;
sc_signal< sc_logic > ap_enable_reg_pp0_iter28;
sc_signal< sc_logic > ap_enable_reg_pp0_iter29;
sc_signal< sc_logic > ap_enable_reg_pp0_iter30;
sc_signal< sc_logic > ap_enable_reg_pp0_iter31;
sc_signal< sc_logic > ap_enable_reg_pp0_iter32;
sc_signal< sc_logic > ap_enable_reg_pp0_iter33;
sc_signal< sc_logic > ap_enable_reg_pp0_iter34;
sc_signal< sc_logic > ap_enable_reg_pp0_iter35;
sc_signal< sc_logic > ap_enable_reg_pp0_iter36;
sc_signal< sc_logic > ap_enable_reg_pp0_iter37;
sc_signal< sc_logic > ap_enable_reg_pp0_iter38;
sc_signal< sc_logic > ap_enable_reg_pp0_iter39;
sc_signal< sc_logic > ap_enable_reg_pp0_iter40;
sc_signal< sc_logic > ap_enable_reg_pp0_iter41;
sc_signal< sc_logic > ap_enable_reg_pp0_iter42;
sc_signal< sc_logic > ap_enable_reg_pp0_iter43;
sc_signal< sc_logic > ap_enable_reg_pp0_iter44;
sc_signal< sc_logic > ap_enable_reg_pp0_iter45;
sc_signal< sc_logic > ap_enable_reg_pp0_iter46;
sc_signal< sc_logic > ap_enable_reg_pp0_iter47;
sc_signal< sc_logic > ap_enable_reg_pp0_iter48;
sc_signal< sc_logic > ap_enable_reg_pp0_iter49;
sc_signal< sc_logic > ap_enable_reg_pp0_iter50;
sc_signal< sc_logic > ap_enable_reg_pp0_iter51;
sc_signal< sc_logic > ap_enable_reg_pp0_iter52;
sc_signal< sc_logic > ap_enable_reg_pp0_iter53;
sc_signal< sc_logic > ap_enable_reg_pp0_iter54;
sc_signal< sc_logic > ap_enable_reg_pp0_iter55;
sc_signal< sc_logic > ap_enable_reg_pp0_iter56;
sc_signal< sc_logic > ap_enable_reg_pp0_iter57;
sc_signal< sc_logic > ap_enable_reg_pp0_iter58;
sc_signal< sc_logic > ap_enable_reg_pp0_iter59;
sc_signal< sc_logic > ap_enable_reg_pp0_iter60;
sc_signal< sc_logic > ap_enable_reg_pp0_iter61;
sc_signal< sc_logic > ap_enable_reg_pp0_iter62;
sc_signal< sc_logic > ap_enable_reg_pp0_iter63;
sc_signal< sc_logic > ap_enable_reg_pp0_iter64;
sc_signal< sc_logic > ap_enable_reg_pp0_iter65;
sc_signal< sc_logic > ap_enable_reg_pp0_iter66;
sc_signal< sc_logic > ap_enable_reg_pp0_iter67;
sc_signal< sc_logic > ap_enable_reg_pp0_iter68;
sc_signal< sc_logic > ap_enable_reg_pp0_iter69;
sc_signal< sc_logic > ap_enable_reg_pp0_iter70;
sc_signal< sc_logic > ap_enable_reg_pp0_iter71;
sc_signal< sc_logic > ap_enable_reg_pp0_iter72;
sc_signal< sc_logic > ap_enable_reg_pp0_iter73;
sc_signal< sc_logic > ap_enable_reg_pp0_iter74;
sc_signal< sc_logic > ap_enable_reg_pp0_iter75;
sc_signal< sc_logic > ap_enable_reg_pp0_iter76;
sc_signal< sc_logic > ap_enable_reg_pp0_iter77;
sc_signal< sc_logic > ap_enable_reg_pp0_iter78;
sc_signal< sc_logic > ap_enable_reg_pp0_iter79;
sc_signal< sc_logic > ap_enable_reg_pp0_iter80;
sc_signal< sc_logic > ap_enable_reg_pp0_iter81;
sc_signal< sc_logic > ap_enable_reg_pp0_iter82;
sc_signal< sc_logic > ap_enable_reg_pp0_iter83;
sc_signal< sc_logic > ap_enable_reg_pp0_iter84;
sc_signal< sc_logic > ap_enable_reg_pp0_iter85;
sc_signal< sc_logic > ap_enable_reg_pp0_iter86;
sc_signal< sc_logic > ap_enable_reg_pp0_iter87;
sc_signal< sc_logic > ap_enable_reg_pp0_iter88;
sc_signal< sc_logic > ap_enable_reg_pp0_iter89;
sc_signal< sc_logic > ap_enable_reg_pp0_iter90;
sc_signal< sc_logic > ap_enable_reg_pp0_iter91;
sc_signal< sc_logic > ap_enable_reg_pp0_iter92;
sc_signal< sc_logic > ap_enable_reg_pp0_iter93;
sc_signal< sc_logic > ap_enable_reg_pp0_iter94;
sc_signal< sc_logic > ap_enable_reg_pp0_iter95;
sc_signal< sc_logic > ap_enable_reg_pp0_iter96;
sc_signal< sc_logic > ap_enable_reg_pp0_iter97;
sc_signal< sc_logic > ap_enable_reg_pp0_iter98;
sc_signal< sc_logic > ap_enable_reg_pp0_iter99;
sc_signal< sc_logic > ap_enable_reg_pp0_iter100;
sc_signal< sc_logic > ap_enable_reg_pp0_iter101;
sc_signal< sc_logic > ap_enable_reg_pp0_iter102;
sc_signal< sc_logic > ap_enable_reg_pp0_iter103;
sc_signal< sc_logic > ap_enable_reg_pp0_iter104;
sc_signal< sc_logic > ap_enable_reg_pp0_iter105;
sc_signal< sc_logic > ap_enable_reg_pp0_iter106;
sc_signal< sc_logic > ap_enable_reg_pp0_iter107;
sc_signal< sc_logic > ap_enable_reg_pp0_iter108;
sc_signal< sc_logic > ap_enable_reg_pp0_iter109;
sc_signal< sc_logic > ap_enable_reg_pp0_iter110;
sc_signal< sc_logic > ap_enable_reg_pp0_iter111;
sc_signal< sc_logic > ap_enable_reg_pp0_iter112;
sc_signal< sc_logic > ap_enable_reg_pp0_iter113;
sc_signal< sc_logic > ap_enable_reg_pp0_iter114;
sc_signal< sc_logic > ap_enable_reg_pp0_iter115;
sc_signal< sc_logic > ap_enable_reg_pp0_iter116;
sc_signal< sc_logic > ap_enable_reg_pp0_iter117;
sc_signal< sc_logic > ap_enable_reg_pp0_iter118;
sc_signal< sc_logic > ap_enable_reg_pp0_iter119;
sc_signal< sc_logic > ap_enable_reg_pp0_iter120;
sc_signal< sc_logic > ap_enable_reg_pp0_iter121;
sc_signal< sc_logic > ap_enable_reg_pp0_iter122;
sc_signal< sc_logic > ap_enable_reg_pp0_iter123;
sc_signal< sc_logic > ap_enable_reg_pp0_iter124;
sc_signal< sc_logic > ap_enable_reg_pp0_iter125;
sc_signal< sc_logic > ap_enable_reg_pp0_iter126;
sc_signal< sc_logic > ap_enable_reg_pp0_iter127;
sc_signal< sc_logic > ap_enable_reg_pp0_iter128;
sc_signal< sc_logic > ap_enable_reg_pp0_iter129;
sc_signal< sc_logic > ap_enable_reg_pp0_iter130;
sc_signal< sc_logic > ap_enable_reg_pp0_iter131;
sc_signal< sc_logic > ap_enable_reg_pp0_iter132;
sc_signal< sc_logic > ap_enable_reg_pp0_iter133;
sc_signal< sc_logic > ap_enable_reg_pp0_iter134;
sc_signal< sc_logic > ap_enable_reg_pp0_iter135;
sc_signal< sc_logic > ap_enable_reg_pp0_iter136;
sc_signal< sc_logic > ap_enable_reg_pp0_iter137;
sc_signal< sc_logic > ap_enable_reg_pp0_iter138;
sc_signal< sc_logic > ap_enable_reg_pp0_iter139;
sc_signal< sc_logic > ap_enable_reg_pp0_iter140;
sc_signal< sc_logic > ap_enable_reg_pp0_iter141;
sc_signal< sc_logic > ap_enable_reg_pp0_iter142;
sc_signal< sc_logic > ap_enable_reg_pp0_iter143;
sc_signal< sc_logic > ap_enable_reg_pp0_iter144;
sc_signal< sc_logic > ap_enable_reg_pp0_iter145;
sc_signal< sc_logic > ap_enable_reg_pp0_iter146;
sc_signal< sc_logic > ap_enable_reg_pp0_iter147;
sc_signal< sc_logic > ap_enable_reg_pp0_iter148;
sc_signal< sc_logic > ap_enable_reg_pp0_iter149;
sc_signal< sc_logic > ap_enable_reg_pp0_iter150;
sc_signal< sc_logic > ap_enable_reg_pp0_iter151;
sc_signal< sc_logic > ap_enable_reg_pp0_iter152;
sc_signal< sc_logic > ap_enable_reg_pp0_iter153;
sc_signal< sc_logic > ap_enable_reg_pp0_iter154;
sc_signal< sc_logic > ap_enable_reg_pp0_iter155;
sc_signal< sc_logic > ap_enable_reg_pp0_iter156;
sc_signal< sc_logic > ap_enable_reg_pp0_iter157;
sc_signal< sc_logic > ap_enable_reg_pp0_iter158;
sc_signal< sc_logic > ap_enable_reg_pp0_iter159;
sc_signal< sc_logic > ap_enable_reg_pp0_iter160;
sc_signal< sc_logic > ap_enable_reg_pp0_iter161;
sc_signal< sc_logic > ap_enable_reg_pp0_iter162;
sc_signal< sc_logic > ap_enable_reg_pp0_iter163;
sc_signal< sc_logic > ap_enable_reg_pp0_iter164;
sc_signal< sc_logic > ap_enable_reg_pp0_iter165;
sc_signal< sc_logic > ap_enable_reg_pp0_iter166;
sc_signal< sc_logic > ap_enable_reg_pp0_iter167;
sc_signal< sc_logic > ap_enable_reg_pp0_iter168;
sc_signal< sc_logic > ap_enable_reg_pp0_iter169;
sc_signal< sc_logic > ap_enable_reg_pp0_iter170;
sc_signal< sc_logic > ap_enable_reg_pp0_iter171;
sc_signal< sc_logic > ap_enable_reg_pp0_iter172;
sc_signal< sc_logic > ap_enable_reg_pp0_iter173;
sc_signal< sc_logic > ap_enable_reg_pp0_iter174;
sc_signal< sc_logic > ap_enable_reg_pp0_iter175;
sc_signal< sc_logic > ap_enable_reg_pp0_iter176;
sc_signal< sc_logic > ap_enable_reg_pp0_iter177;
sc_signal< sc_logic > ap_enable_reg_pp0_iter178;
sc_signal< sc_logic > ap_enable_reg_pp0_iter179;
sc_signal< sc_logic > ap_enable_reg_pp0_iter180;
sc_signal< sc_logic > ap_enable_reg_pp0_iter181;
sc_signal< sc_logic > ap_enable_reg_pp0_iter182;
sc_signal< sc_logic > ap_enable_reg_pp0_iter183;
sc_signal< sc_logic > ap_enable_reg_pp0_iter184;
sc_signal< sc_logic > ap_enable_reg_pp0_iter185;
sc_signal< sc_lv<32> > buffer_load_8_0_fu_76;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load;
sc_signal< sc_lv<32> > buffer_load_8_1_fu_80;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_1;
sc_signal< sc_lv<32> > buffer_load_8_2_fu_84;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_2;
sc_signal< sc_lv<32> > buffer_load_8_3_fu_88;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_3;
sc_signal< sc_lv<32> > buffer_load_8_4_fu_92;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_4;
sc_signal< sc_lv<32> > buffer_load_8_5_fu_96;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_5;
sc_signal< sc_lv<32> > buffer_load_8_6_fu_100;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_6;
sc_signal< sc_lv<32> > buffer_load_8_7_fu_104;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_7;
sc_signal< sc_lv<32> > buffer_load_8_8_fu_108;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_8;
sc_signal< sc_lv<32> > buffer_load_8_9_fu_112;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_9;
sc_signal< sc_lv<32> > buffer_load_8_10_fu_116;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_10;
sc_signal< sc_lv<32> > buffer_load_8_11_fu_120;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_11;
sc_signal< sc_lv<32> > buffer_load_8_12_fu_124;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_12;
sc_signal< sc_lv<32> > buffer_load_8_13_fu_128;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_13;
sc_signal< sc_lv<32> > buffer_load_8_14_fu_132;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_14;
sc_signal< sc_lv<32> > buffer_load_8_15_fu_136;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_15;
sc_signal< sc_lv<32> > buffer_load_8_16_fu_140;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_16;
sc_signal< sc_lv<32> > buffer_load_8_17_fu_144;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_17;
sc_signal< sc_lv<32> > buffer_load_8_18_fu_148;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_18;
sc_signal< sc_lv<32> > buffer_load_8_19_fu_152;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_19;
sc_signal< sc_lv<32> > buffer_load_8_20_fu_156;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_20;
sc_signal< sc_lv<32> > buffer_load_8_21_fu_160;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_21;
sc_signal< sc_lv<32> > buffer_load_8_22_fu_164;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_22;
sc_signal< sc_lv<32> > buffer_load_8_23_fu_168;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_23;
sc_signal< sc_lv<32> > buffer_load_8_24_fu_172;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_24;
sc_signal< sc_lv<32> > buffer_load_8_25_fu_176;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_25;
sc_signal< sc_lv<32> > buffer_load_8_26_fu_180;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_26;
sc_signal< sc_lv<32> > buffer_load_8_27_fu_184;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_27;
sc_signal< sc_lv<32> > buffer_load_8_28_fu_188;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_28;
sc_signal< sc_lv<32> > buffer_load_8_29_fu_192;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_29;
sc_signal< sc_lv<32> > buffer_load_8_30_fu_196;
sc_signal< sc_lv<32> > ap_sig_allocacmp_buffer_load_30;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<32> > grp_fu_511_p0;
sc_signal< sc_lv<32> > bitcast_ln68_fu_773_p1;
sc_signal< sc_lv<8> > tmp_s_fu_776_p4;
sc_signal< sc_lv<23> > trunc_ln68_fu_786_p1;
sc_signal< sc_lv<1> > or_ln68_fu_802_p2;
sc_signal< sc_lv<1> > grp_fu_514_p2;
sc_signal< sc_logic > grp_fu_213_ce;
sc_signal< sc_logic > grp_fu_218_ce;
sc_signal< sc_logic > grp_fu_222_ce;
sc_signal< sc_logic > grp_fu_226_ce;
sc_signal< sc_logic > grp_fu_230_ce;
sc_signal< sc_logic > grp_fu_234_ce;
sc_signal< sc_logic > grp_fu_238_ce;
sc_signal< sc_logic > grp_fu_242_ce;
sc_signal< sc_logic > grp_fu_246_ce;
sc_signal< sc_logic > grp_fu_250_ce;
sc_signal< sc_logic > grp_fu_254_ce;
sc_signal< sc_logic > grp_fu_258_ce;
sc_signal< sc_logic > grp_fu_262_ce;
sc_signal< sc_logic > grp_fu_266_ce;
sc_signal< sc_logic > grp_fu_270_ce;
sc_signal< sc_logic > grp_fu_274_ce;
sc_signal< sc_logic > grp_fu_278_ce;
sc_signal< sc_logic > grp_fu_282_ce;
sc_signal< sc_logic > grp_fu_286_ce;
sc_signal< sc_logic > grp_fu_290_ce;
sc_signal< sc_logic > grp_fu_294_ce;
sc_signal< sc_logic > grp_fu_298_ce;
sc_signal< sc_logic > grp_fu_302_ce;
sc_signal< sc_logic > grp_fu_306_ce;
sc_signal< sc_logic > grp_fu_310_ce;
sc_signal< sc_logic > grp_fu_314_ce;
sc_signal< sc_logic > grp_fu_318_ce;
sc_signal< sc_logic > grp_fu_322_ce;
sc_signal< sc_logic > grp_fu_326_ce;
sc_signal< sc_logic > grp_fu_330_ce;
sc_signal< sc_logic > grp_fu_334_ce;
sc_signal< sc_logic > grp_fu_338_ce;
sc_signal< sc_logic > grp_fu_342_ce;
sc_signal< sc_logic > grp_fu_346_ce;
sc_signal< sc_logic > grp_fu_350_ce;
sc_signal< sc_logic > grp_fu_354_ce;
sc_signal< sc_logic > grp_fu_358_ce;
sc_signal< sc_logic > grp_fu_362_ce;
sc_signal< sc_logic > grp_fu_366_ce;
sc_signal< sc_logic > grp_fu_370_ce;
sc_signal< sc_logic > grp_fu_374_ce;
sc_signal< sc_logic > grp_fu_378_ce;
sc_signal< sc_logic > grp_fu_382_ce;
sc_signal< sc_logic > grp_fu_386_ce;
sc_signal< sc_logic > grp_fu_390_ce;
sc_signal< sc_logic > grp_fu_394_ce;
sc_signal< sc_logic > grp_fu_398_ce;
sc_signal< sc_logic > grp_fu_402_ce;
sc_signal< sc_logic > grp_fu_406_ce;
sc_signal< sc_logic > grp_fu_410_ce;
sc_signal< sc_logic > grp_fu_414_ce;
sc_signal< sc_logic > grp_fu_418_ce;
sc_signal< sc_logic > grp_fu_422_ce;
sc_signal< sc_logic > grp_fu_426_ce;
sc_signal< sc_logic > grp_fu_430_ce;
sc_signal< sc_logic > grp_fu_434_ce;
sc_signal< sc_logic > grp_fu_438_ce;
sc_signal< sc_logic > grp_fu_442_ce;
sc_signal< sc_logic > grp_fu_446_ce;
sc_signal< sc_logic > grp_fu_450_ce;
sc_signal< sc_logic > grp_fu_454_ce;
sc_signal< sc_logic > grp_fu_458_ce;
sc_signal< sc_logic > grp_fu_462_ce;
sc_signal< sc_logic > grp_fu_466_ce;
sc_signal< sc_logic > grp_fu_470_ce;
sc_signal< sc_logic > grp_fu_474_ce;
sc_signal< sc_logic > grp_fu_478_ce;
sc_signal< sc_logic > grp_fu_482_ce;
sc_signal< sc_logic > grp_fu_486_ce;
sc_signal< sc_logic > grp_fu_490_ce;
sc_signal< sc_logic > grp_fu_494_ce;
sc_signal< sc_logic > grp_fu_498_ce;
sc_signal< sc_logic > grp_fu_503_ce;
sc_signal< sc_logic > grp_fu_507_ce;
sc_signal< sc_logic > grp_fu_511_ce;
sc_signal< sc_logic > grp_fu_514_ce;
sc_signal< bool > ap_block_pp0_stage0_00001;
sc_signal< sc_lv<2> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<2> ap_ST_fsm_state1;
static const sc_lv<
|
2> ap_ST_fsm_pp0_stage0;
static const bool ap_const_boolean_1;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_41000000;
static const sc_lv<32> ap_const_lv32_3F4CCCCD;
static const sc_lv<32> ap_const_lv32_17;
static const sc_lv<32> ap_const_lv32_1E;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<23> ap_const_lv23_0;
static const sc_lv<5> ap_const_lv5_2;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_var_for_const2();
void thread_ap_var_for_const3();
void thread_ap_clk_no_reset_();
void thread_and_ln68_fu_806_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_00001();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state100_pp0_stage0_iter98();
void thread_ap_block_state101_pp0_stage0_iter99();
void thread_ap_block_state102_pp0_stage0_iter100();
void thread_ap_block_state103_pp0_stage0_iter101();
void thread_ap_block_state104_pp0_stage0_iter102();
void thread_ap_block_state105_pp0_stage0_iter103();
void thread_ap_block_state106_pp0_stage0_iter104();
void thread_ap_block_state107_pp0_stage0_iter105();
void thread_ap_block_state108_pp0_stage0_iter106();
void thread_ap_block_state109_pp0_stage0_iter107();
void thread_ap_block_state10_pp0_stage0_iter8();
void thread_ap_block_state110_pp0_stage0_iter108();
void thread_ap_block_state111_pp0_stage0_iter109();
void thread_ap_block_state112_pp0_stage0_iter110();
void thread_ap_block_state113_pp0_stage0_iter111();
void thread_ap_block_state114_pp0_stage0_iter112();
void thread_ap_block_state115_pp0_stage0_iter113();
void thread_ap_block_state116_pp0_stage0_iter114();
void thread_ap_block_state117_pp0_stage0_iter115();
void thread_ap_block_state118_pp0_stage0_iter116();
void thread_ap_block_state119_pp0_stage0_iter117();
void thread_ap_block_state11_pp0_stage0_iter9();
void thread_ap_block_state120_pp0_stage0_iter118();
void thread_ap_block_state121_pp0_stage0_iter119();
void thread_ap_block_state122_pp0_stage0_iter120();
void thread_ap_block_state123_pp0_stage0_iter121();
void thread_ap_block_state124_pp0_stage0_iter122();
void thread_ap_block_state125_pp0_stage0_iter123();
void thread_ap_block_state126_pp0_stage0_iter124();
void thread_ap_block_state127_pp0_stage0_iter125();
void thread_ap_block_state128_pp0_stage0_iter126();
void thread_ap_block_state129_pp0_stage0_iter127();
void thread_ap_block_state12_pp0_stage0_iter10();
void thread_ap_block_state130_pp0_stage0_iter128();
void thread_ap_block_state131_pp0_stage0_iter129();
void thread_ap_block_state132_pp0_stage0_iter130();
void thread_ap_block_state133_pp0_stage0_iter131();
void thread_ap_block_state134_pp0_stage0_iter132();
void thread_ap_block_state135_pp0_stage0_iter133();
void thread_ap_block_state136_pp0_stage0_iter134();
void thread_ap_block_state137_pp0_stage0_iter135();
void thread_ap_block_state138_pp0_stage0_iter136();
void thread_ap_block_state139_pp0_stage0_iter137();
void thread_ap_block_state13_pp0_stage0_iter11();
void thread_ap_block_state140_pp0_stage0_iter138();
void thread_ap_block_state141_pp0_stage0_iter139();
void thread_ap_block_state142_pp0_stage0_iter140();
void thread_ap_block_state143_pp0_stage0_iter141();
void thread_ap_block_state144_pp0_stage0_iter142();
void thread_ap_block_state145_pp0_stage0_iter143();
void thread_ap_block_state146_pp0_stage0_iter144();
void thread_ap_block_state147_pp0_stage0_iter145();
void thread_ap_block_state148_pp0_stage0_iter146();
void thread_ap_block_state149_pp0_stage0_iter147();
void thread_ap_block_state14_pp0_stage0_iter12();
void thread_ap_block_state150_pp0_stage0_iter148();
void thread_ap_block_state151_pp0_stage0_iter149();
void thread_ap_block_state152_pp0_stage0_iter150();
void thread_ap_block_state153_pp0_stage0_iter151();
void thread_ap_block_state154_pp0_stage0_iter152();
void thread_ap_block_state155_pp0_stage0_iter153();
void thread_ap_block_state156_pp0_stage0_iter154();
void thread_ap_block_state157_pp0_stage0_iter155();
void thread_ap_block_state158_pp0_stage0_iter156();
void thread_ap_block_state159_pp0_stage0_iter157();
void thread_ap_block_state15_pp0_stage0_iter13();
void thread_ap_block_state160_pp0_stage0_iter158();
void thread_ap_block_state161_pp0_stage0_iter159();
void thread_ap_block_state162_pp0_stage0_iter160();
void thread_ap_block_state163_pp0_stage0_iter161();
void thread_ap_block_state164_pp0_stage0_iter162();
void thread_ap_block_state165_pp0_stage0_iter163();
void thread_ap_block_state166_pp0_stage0_iter164();
void thread_ap_block_state167_pp0_stage0_iter165();
void thread_ap_block_state168_pp0_stage0_iter166();
void thread_ap_block_state169_pp0_stage0_iter167();
void thread_ap_block_state16_pp0_stage0_iter14();
void thread_ap_block_state170_pp0_stage0_iter168();
void thread_ap_block_state171_pp0_stage0_iter169();
void thread_ap_block_state172_pp0_stage0_iter170();
void thread_ap_block_state173_pp0_stage0_iter171();
void thread_ap_block_state174_pp0_stage0_iter172();
void thread_ap_block_state175_pp0_stage0_iter173();
void thread_ap_block_state176_pp0_stage0_iter174();
void thread_ap_block_state177_pp0_stage0_iter175();
void thread_ap_block_state178_pp0_stage0_iter176();
void thread_ap_block_state179_pp0_stage0_iter177();
void thread_ap_block_state17_pp0_stage0_iter15();
void thread_ap_block_state180_pp0_stage0_iter178();
void thread_ap_block_state181_pp0_stage0_iter179();
void thread_ap_block_state182_pp0_stage0_iter180();
void thread_ap_block_state183_pp0_stage0_iter181();
void thread_ap_block_state184_pp0_stage0_iter182();
void thread_ap_block_state185_pp0_stage0_iter183();
void thread_ap_block_state186_pp0_stage0_iter184();
void thread_ap_block_state187_pp0_stage0_iter185();
void thread_ap_block_state188_pp0_stage0_iter186();
void thread_ap_block_state18_pp0_stage0_iter16();
void thread_ap_block_state19_pp0_stage0_iter17();
void thread_ap_block_state20_pp0_stage0_iter18();
void thread_ap_block_state21_pp0_stage0_iter19();
void thread_ap_block_state22_pp0_stage0_iter20();
void thread_ap_block_state23_pp0_stage0_iter21();
void thread_ap_block_state24_pp0_stage0_iter22();
void thread_ap_block_state25_pp0_stage0_iter23();
void thread_ap_block_state26_pp0_stage0_iter24();
void thread_ap_block_state27_pp0_stage0_iter25();
void thread_ap_block_state28_pp0_stage0_iter26();
void thread_ap_block_state29_pp0_stage0_iter27();
void thread_ap_block_state2_pp0_stage0_iter0();
void thread_ap_block_state30_pp0_stage0_iter28();
void thread_ap_block_state31_pp0_stage0_iter29();
void thread_ap_block_state32_pp0_stage0_iter30();
void thread_ap_block_state33_pp0_stage0_iter31();
void thread_ap_block_state34_pp0_stage0_iter32();
void thread_ap_block_state35_pp0_stage0_iter33();
void thread_ap_block_state36_pp0_stage0_iter34();
void thread_ap_block_state37_pp0_stage0_iter35();
void thread_ap_block_state38_pp0_stage0_iter36();
void thread_ap_block_state39_pp0_stage0_iter37();
void thread_ap_block_state3_pp0_stage0_iter1();
void thread_ap_block_state40_pp0_stage0_iter38();
void thread_ap_block_state41_pp0_stage0_iter39();
void thread_ap_block_state42_pp0_stage0_iter40();
void thread_ap_block_state43_pp0_stage0_iter41();
void thread_ap_block_state44_pp0_stage0_iter42();
void thread_ap_block_state45_pp0_stage0_iter43();
void thread_ap_block_state46_pp0_stage0_iter44();
void thread_ap_block_state47_pp0_stage0_iter45();
void thread_ap_block_state48_pp0_stage0_iter46();
void thread_ap_block_state49_pp0_stage0_iter47();
void thread_ap_block_state4_pp0_stage0_iter2();
void thread_ap_block_state50_pp0_stage0_iter48();
void thread_ap_block_state51_pp0_stage0_iter49();
void thread_ap_block_state52_pp0_stage0_iter50();
void thread_ap_block_state53_pp0_stage0_iter51();
void thread_ap_block_state54_pp0_stage0_iter52();
void thread_ap_block_state55_pp0_stage0_iter53();
void thread_ap_block_state56_pp0_stage0_iter54();
void thread_ap_block_state57_pp0_stage0_iter55();
void thread_ap_block_state58_pp0_stage0_iter56();
void thread_ap_block_state59_pp0_stage0_iter57();
void thread_ap_block_state5_pp0_stage0_iter3();
void thread_ap_block_state60_pp0_stage0_iter58();
void thread_ap_block_state61_pp0_stage0_iter59();
void thread_ap_block_state62_pp0_stage0_iter60();
void thread_ap_block_state63_pp0_stage0_iter61();
void thread_ap_block_state64_pp0_stage0_iter62();
void thread_ap_block_state65_pp0_stage0_iter63();
void thread_ap_block_state66_pp0_stage0_iter64();
void thread_ap_block_state67_pp0_stage0_iter65();
void thread_ap_block_state68_pp0_stage0_iter66();
void thread_ap_block_state69_pp0_stage0_iter67();
void thread_ap_block_state6_pp0_stage0_iter4();
void thread_ap_block_state70_pp0_stage0_iter68();
void thread_ap_block_state71_pp0_stage0_iter69();
void thread_ap_block_state72_pp0_stage0_iter70();
void thread_ap_block_state73_pp0_stage0_iter71();
void thread_ap_block_state74_pp0_stage0_iter72();
void thread_ap_block_state75_pp0_stage0_iter73();
void thread_ap_block_state76_pp0_stage0_iter74();
void thread_ap_block_state77_pp0_stage0_iter75();
void thread_ap_block_state78_pp0_stage0_iter76();
void thread_ap_block_state79_pp0_stage0_iter77();
void thread_ap_block_state7_pp0_stage0_iter5();
void thread_ap_block_state80_pp0_stage0_iter78();
void thread_ap_block_state81_pp0_stage0_iter79();
void thread_ap_block_state82_pp0_stage0_iter80();
void thread_ap_block_state83_pp0_stage0_iter81();
void thread_ap_block_state84_pp0_stage0_iter82();
void thread_ap_block_state85_pp0_stage0_iter83();
void thread_ap_block_state86_pp0_stage0_iter84();
void thread_ap_block_state87_pp0_stage0_iter85();
void thread_ap_block_state88_pp0_stage0_iter86();
void thread_ap_block_state89_pp0_stage0_iter87();
void thread_ap_block_state8_pp0_stage0_iter6();
void thread_ap_block_state90_pp0_stage0_iter88();
void thread_ap_block_state91_pp0_stage0_iter89();
void thread_ap_block_state92_pp0_stage0_iter90();
void thread_ap_block_state93_pp0_stage0_iter91();
void thread_ap_block_state94_pp0_stage0_iter92();
void thread_ap_block_state95_pp0_stage0_iter93();
void thread_ap_block_state96_pp0_stage0_iter94();
void thread_ap_block_state97_pp0_stage0_iter95();
void thread_ap_block_state98_pp0_stage0_iter96();
void thread_ap_block_state99_pp0_stage0_iter97();
void thread_ap_block_state9_pp0_stage0_iter7();
void thread_ap_enable_pp0();
void thread_ap_idle_pp0();
void thread_ap_sig_allocacmp_buffer_load();
void thread_ap_sig_allocacmp_buffer_load_1();
void thread_ap_sig_allocacmp_buffer_load_10();
void thread_ap_sig_allocacmp_buffer_load_11();
void thread_ap_sig_allocacmp_buffer_load_12();
void thread_ap_sig_allocacmp_buffer_load_13();
void thread_ap_sig_allocacmp_buffer_load_14();
void thread_ap_sig_allocacmp_buffer_load_15();
void thread_ap_sig_allocacmp_buffer_load_16();
void thread_ap_sig_allocacmp_buffer_load_17();
void thread_ap_sig_allocacmp_buffer_load_18();
void thread_ap_sig_allocacmp_buffer_load_19();
void thread_ap_sig_allocacmp_buffer_load_2();
void thread_ap_sig_allocacmp_buffer_load_20();
void thread_ap_sig_allocacmp_buffer_load_21();
void thread_ap_sig_allocacmp_buffer_load_22();
void thread_ap_sig_allocacmp_buffer_load_23();
void thread_ap_sig_allocacmp_buffer_load_24();
void thread_ap_sig_allocacmp_buffer_load_25();
void thread_ap_sig_allocacmp_buffer_load_26();
void thread_ap_sig_allocacmp_buffer_load_27();
void thread_ap_sig_allocacmp_buffer_load_28();
void thread_ap_sig_allocacmp_buffer_load_29();
void thread_ap_sig_allocacmp_buffer_load_3();
void thread_ap_sig_allocacmp_buffer_load_30();
void thread_ap_sig_allocacmp_buffer_load_4();
void thread_ap_sig_allocacmp_buffer_load_5();
void thread_ap_sig_allocacmp_buffer_load_6();
void thread_ap_sig_allocacmp_buffer_load_7();
void thread_ap_sig_allocacmp_buffer_load_8();
void thread_ap_sig_allocacmp_buffer_load_9();
void thread_bitcast_ln68_fu_773_p1();
void thread_detect_blk_n();
void thread_detect_din();
void thread_detect_write();
void thread_e_blk_n();
void thread_e_read();
void thread_grp_fu_213_ce();
void thread_grp_fu_218_ce();
void thread_grp_fu_222_ce();
void thread_grp_fu_226_ce();
void thread_grp_fu_230_ce();
void thread_grp_fu_234_ce();
void thread_grp_fu_238_ce();
void thread_grp_fu_242_ce();
void thread_grp_fu_246_ce();
void thread_grp_fu_250_ce();
void thread_grp_fu_254_ce();
void thread_grp_fu_258_ce();
void thread_grp_fu_262_ce();
void thread_grp_fu_266_ce();
void thread_grp_fu_270_ce();
void thread_grp_fu_274_ce();
void thread_grp_fu_278_ce();
void thread_grp_fu_282_ce();
void thread_grp_fu_286_ce();
void thread_grp_fu_290_ce();
void thread_grp_fu_294_ce();
void thread_grp_fu_298_ce();
void thread_grp_fu_302_ce();
void thread_grp_fu_306_ce();
void thread_grp_fu_310_ce();
void thread_grp_fu_314_ce();
void thread_grp_fu_318_ce();
void thread_grp_fu_322_ce();
void thread_grp_fu_326_ce();
void thread_grp_fu_330_ce();
void thread_grp_fu_334_ce();
void thread_grp_fu_338_ce();
void thread_grp_fu_342_ce();
void thread_grp_fu_346_ce();
void thread_grp_fu_350_ce();
void thread_grp_fu_354_ce();
void thread_grp_fu_358_ce();
void thread_grp_fu_362_ce();
void thread_grp_fu_366_ce();
void thread_grp_fu_370_ce();
void thread_grp_fu_374_ce();
void thread_grp_fu_378_ce();
void thread_grp_fu_382_ce();
void thread_grp_fu_386_ce();
void thread_grp_fu_390_ce();
void thread_grp_fu_394_ce();
void thread_grp_fu_398_ce();
void thread_grp_fu_402_ce();
void thread_grp_fu_406_ce();
void thread_grp_fu_410_ce();
void thread_grp_fu_414_ce();
void thread_grp_fu_418_ce();
void thread_grp_fu_422_ce();
void thread_grp_fu_426_ce();
void thread_grp_fu_430_ce();
void thread_grp_fu_434_ce();
void thread_grp_fu_438_ce();
void thread_grp_fu_442_ce();
void thread_grp_fu_446_ce();
void thread_grp_fu_450_ce();
void thread_grp_fu_454_ce();
void thread_grp_fu_458_ce();
void thread_grp_fu_462_ce();
void thread_grp_fu_466_ce();
void thread_grp_fu_470_ce();
void thread_grp_fu_474_ce();
void thread_grp_fu_478_ce();
void thread_grp_fu_482_ce();
void thread_grp_fu_486_ce();
void thread_grp_fu_490_ce();
void thread_grp_fu_494_ce();
void thread_grp_fu_498_ce();
void thread_grp_fu_503_ce();
void thread_grp_fu_507_ce();
void thread_grp_fu_511_ce();
void thread_grp_fu_511_p0();
void thread_grp_fu_514_ce();
void thread_icmp_ln68_1_fu_796_p2();
void thread_icmp_ln68_fu_790_p2();
void thread_or_ln68_fu_802_p2();
void thread_tmp_s_fu_776_p4();
void thread_trunc_ln68_fu_786_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
/*******************************************************************************
* gpio_mf.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC model of a generic multi-function GPIO.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _GPIO_MF_H
#define _GPIO_MF_H
#include <systemc.h>
#include "gpio_simple.h"
class gpio_mf : public gpio {
public:
/* We inherit the main i/o pin and add the function pins. */
sc_port< sc_signal_in_if<bool>,0 > fin {"fin"};
sc_port< sc_signal_in_if<bool>,0 > fen {"fen"};
sc_port< sc_signal_out_if<bool>,0 > fout {"fout"};
/* Multifunction specific tasks */
virtual void set_function(gpio_function_t newfunction);
virtual gpio_function_t get_function();
virtual void set_val(bool newval);
/* Threads */
sc_event updatefunc; /* Triggers a function change. */
sc_event updatereturn; /* Triggers a feedback drive event. */
void drive_func(); /* Updates the function drive. */
void drive_return(); /* Updates feedback pins to functions */
/* Sets initial drive condition. */
gpio_mf(sc_module_name name, int optargs, int initial,
gpio_function_t initialfunc = GPIOMF_GPIO):
gpio(name, optargs, initial) {
function = initialfunc;
SC_THREAD(drive_return);
sensitive << pin << updatereturn;
/* This one has no sensitivity list as it varies according to the
* selected function.
*/
SC_THREAD(drive_func);
}
SC_HAS_PROCESS(gpio_mf);
virtual gpio_type_t get_type() const {return GPIO_TYPE_MF; }
protected:
gpio_function_t function; /* Indicates internal selected function */
bool pinval; /* Indicates intended drive value for pin */
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.1
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _AXIvideo2Mat_HH_
#define _AXIvideo2Mat_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct AXIvideo2Mat : public sc_module {
// Port declarations 40
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_in< sc_logic > start_full_n;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > start_out;
sc_out< sc_logic > start_write;
sc_in< sc_lv<24> > stream_in_TDATA;
sc_in< sc_logic > stream_in_TVALID;
sc_out< sc_logic > stream_in_TREADY;
sc_in< sc_lv<3> > stream_in_TKEEP;
sc_in< sc_lv<3> > stream_in_TSTRB;
sc_in< sc_lv<1> > stream_in_TUSER;
sc_in< sc_lv<1> > stream_in_TLAST;
sc_in< sc_lv<1> > stream_in_TID;
sc_in< sc_lv<1> > stream_in_TDEST;
sc_in< sc_lv<11> > img_rows_V_dout;
sc_in< sc_logic > img_rows_V_empty_n;
sc_out< sc_logic > img_rows_V_read;
sc_in< sc_lv<12> > img_cols_V_dout;
sc_in< sc_logic > img_cols_V_empty_n;
sc_out< sc_logic > img_cols_V_read;
sc_out< sc_lv<8> > img_data_stream_0_V_din;
sc_in< sc_logic > img_data_stream_0_V_full_n;
sc_out< sc_logic > img_data_stream_0_V_write;
sc_out< sc_lv<8> > img_data_stream_1_V_din;
sc_in< sc_logic > img_data_stream_1_V_full_n;
sc_out< sc_logic > img_data_stream_1_V_write;
sc_out< sc_lv<8> > img_data_stream_2_V_din;
sc_in< sc_logic > img_data_stream_2_V_full_n;
sc_out< sc_logic > img_data_stream_2_V_write;
sc_out< sc_lv<11> > img_rows_V_out_din;
sc_in< sc_logic > img_rows_V_out_full_n;
sc_out< sc_logic > img_rows_V_out_write;
sc_out< sc_lv<12> > img_cols_V_out_din;
sc_in< sc_logic > img_cols_V_out_full_n;
sc_out< sc_logic > img_cols_V_out_write;
// Module declarations
AXIvideo2Mat(sc_module_name name);
SC_HAS_PROCESS(AXIvideo2Mat);
~AXIvideo2Mat();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > real_start;
sc_signal< sc_logic > start_once_reg;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<8> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > internal_ap_ready;
sc_signal< sc_lv<24> > AXI_video_strm_V_data_V_0_data_out;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_vld_in;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_vld_out;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_ack_in;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_ack_out;
sc_signal< sc_lv<24> > AXI_video_strm_V_data_V_0_payload_A;
sc_signal< sc_lv<24> > AXI_video_strm_V_data_V_0_payload_B;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_sel_rd;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_sel_wr;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_sel;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_load_A;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_load_B;
sc_signal< sc_lv<2> > AXI_video_strm_V_data_V_0_state;
sc_signal< sc_logic > AXI_video_strm_V_data_V_0_state_cmp_full;
sc_signal< sc_lv<1> > AXI_video_strm_V_user_V_0_data_out;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_vld_in;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_vld_out;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_ack_in;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_ack_out;
sc_signal< sc_lv<1> > AXI_video_strm_V_user_V_0_payload_A;
sc_signal< sc_lv<1> > AXI_video_strm_V_user_V_0_payload_B;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_sel_rd;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_sel_wr;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_sel;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_load_A;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_load_B;
sc_signal< sc_lv<2> > AXI_video_strm_V_user_V_0_state;
sc_signal< sc_logic > AXI_video_strm_V_user_V_0_state_cmp_full;
sc_signal< sc_lv<1> > AXI_video_strm_V_last_V_0_data_out;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_vld_in;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_vld_out;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_ack_in;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_ack_out;
sc_signal< sc_lv<1> > AXI_video_strm_V_last_V_0_payload_A;
sc_signal< sc_lv<1> > AXI_video_strm_V_last_V_0_payload_B;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_sel_rd;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_sel_wr;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_sel;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_load_A;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_load_B;
sc_signal< sc_lv<2> > AXI_video_strm_V_last_V_0_state;
sc_signal< sc_logic > AXI_video_strm_V_last_V_0_state_cmp_full;
sc_signal< sc_logic > AXI_video_strm_V_dest_V_0_vld_in;
sc_signal< sc_logic > AXI_video_strm_V_dest_V_0_ack_out;
sc_signal< sc_lv<2> > AXI_video_strm_V_dest_V_0_state;
sc_signal< sc_logic > stream_in_TDATA_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > ap_CS_fsm_pp1_stage0;
sc_signal< sc_logic > ap_enable_reg_pp1_iter1;
sc_signal< bool > ap_block_pp1_stage0;
sc_signal< sc_lv<1> > exitcond_i_reg_434;
sc_signal< sc_lv<1> > brmerge_i_reg_443;
sc_signal< sc_logic > ap_CS_fsm_pp2_stage0;
sc_signal< sc_logic > ap_enable_reg_pp2_iter1;
sc_signal< bool > ap_block_pp2_stage0;
sc_signal< sc_lv<1> > eol_2_i_reg_270;
sc_signal< sc_logic > img_rows_V_blk_n;
sc_signal< sc_logic > img_cols_V_blk_n;
sc_signal< sc_logic > img_data_stream_0_V_blk_n;
sc_signal< sc_logic > img_data_stream_1_V_blk_n;
sc_signal< sc_logic > img_data_stream_2_V_blk_n;
sc_signal< sc_logic > img_rows_V_out_blk_n;
sc_signal< sc_logic > img_cols_V_out_blk_n;
sc_signal< sc_lv<32> > t_V_3_reg_200;
sc_signal< sc_lv<1> > eol_i_reg_211;
sc_signal< sc_lv<1> > eol_reg_223;
sc_signal< sc_lv<24> > axi_data_V_1_i_reg_234;
sc_signal< sc_lv<1> > axi_last_V_3_i_reg_281;
sc_signal< sc_lv<24> > axi_data_V_3_i_reg_293;
sc_signal< sc_lv<32> > rows_V_fu_315_p1;
sc_signal< sc_lv<32> > rows_V_reg_395;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<32> > cols_V_fu_319_p1;
sc_signal< sc_lv<32> > cols_V_reg_400;
sc_signal< sc_lv<24> > tmp_data_V_reg_405;
sc_signal< sc_lv<1> > tmp_last_V_reg_413;
sc_signal< sc_lv<1> > exitcond5_i_fu_332_p2;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<32> > i_V_fu_337_p2;
sc_signal< sc_lv<32> > i_V_reg_429;
sc_signal< sc_lv<1> > exitcond_i_fu_343_p2;
sc_signal< bool > ap_block_state5_pp1_stage0_iter0;
sc_signal< bool > ap_predicate_op73_read_state6;
sc_signal< bool > ap_block_state6_pp1_stage0_iter1;
sc_signal< bool > ap_block_pp1_stage0_11001;
sc_signal< sc_lv<32> > j_V_fu_348_p2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter0;
sc_signal< sc_lv<1> > brmerge_i_fu_357_p2;
sc_signal< bool > ap_block_state8_pp2_stage0_iter0;
sc_signal< bool > ap_block_state9_pp2_stage0_iter1;
sc_signal< bool > ap_block_pp2_stage0_11001;
sc_signal< bool > ap_block_pp1_stage0_subdone;
sc_signal< sc_logic > ap_enable_reg_pp2_iter0;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< bool > ap_block_pp2_stage0_subdone;
sc_signal< sc_lv<1> > ap_phi_mux_eol_2_i_phi_fu_273_p4;
sc_signal< sc_lv<1> > axi_last_V1_i_reg_169;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<24> > axi_data_V1_i_reg_179;
sc_signal< sc_lv<32> > t_V_reg_189;
sc_signal< sc_lv<1> > ap_phi_mux_eol_i_phi_fu_215_p4;
sc_signal< sc_lv<1> > ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
sc_signal< sc_lv<24> > ap_phi_mux_p_Val2_s_phi_fu_262_p4;
sc_signal< sc_lv<1> > ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
sc_signal< sc_lv<24> > ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
sc_signal< bool > ap_block_pp1_stage0_01001;
sc_signal< sc_lv<1> > sof_1_i_fu_98;
sc_signal< sc_lv<11> > rows_V_fu_315_p0;
sc_signal< sc_lv<12> > cols_V_fu_319_p0;
sc_signal< sc_lv<1> > tmp_user_V_fu_323_p1;
sc_signal< sc_lv<8> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp1;
sc_signal< sc_logic > ap_enable_pp1;
sc_signal< sc_logic > ap_idle_pp2;
sc_signal< sc_logic > ap_enable_pp2;
sc_signal< bool > ap_condition_529;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<8> ap_ST_fsm_state1;
static const sc_lv<8> ap_ST_fsm_state2;
static const sc_lv<8> ap_ST_fsm_state3;
static const sc_lv<8> ap_ST_fsm_state4;
static const sc_lv<8> ap_ST_fsm_pp1_stage0;
static const sc_lv<8> ap_ST_fsm_state7;
static const sc_lv<8> ap_ST_fsm_pp2_stage0;
static const sc_lv<8> ap_ST_fsm_state10;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_4;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_17;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_AXI_video_strm_V_data_V_0_ack_in();
void thread_AXI_video_strm_V_data_V_0_ack_out();
void thread_AXI_video_strm_V_data_V_0_data_out();
void thread_AXI_video_strm_V_data_V_0_load_A();
void thread_AXI_video_strm_V_data_V_0_load_B();
void thread_AXI_video_strm_V_data_V_0_sel();
void thread_AXI_video_strm_V_data_V_0_state_cmp_full();
void thread_AXI_video_strm_V_data_V_0_vld_in();
void thread_AXI_video_strm_V_data_V_0_vld_out();
void thread_AXI_video_strm_V_dest_V_0_ack_out();
void thread_AXI_video_strm_V_dest_V_0_vld_in();
void thread_AXI_video_strm_V_last_V_0_ack_in();
void thread_AXI_video_strm_V_last_V_0_ack_out();
void thread_AXI_video_strm_V_last_V_0_data_out();
void thread_AXI_video_strm_V_last_V_0_load_A();
void thread_AXI_video_strm_V_last_V_0_load_B();
void thread_AXI_video_strm_V_last_V_0_sel();
void thread_AXI_video_strm_V_last_V_0_state_cmp_full();
void thread_AXI_video_strm_V_last_V_0_vld_in();
void thread_AXI_video_strm_V_last_V_0_vld_out();
void thread_AXI_video_strm_V_user_V_0_ack_in();
void thread_AXI_video_strm_V_user_V_0_ack_out();
void thread_AXI_video_strm_V_user_V_0_data_out();
void thread_AXI_video_strm_V_user_V_0_load_A();
void thread_AXI_video_strm_V_user_V_0_load_B();
void thread_AXI_video_strm_V_user_V_0_sel();
void thread_AXI_video_strm_V_user_V_0_state_cmp_full();
void thread_AXI_video_strm_V_user_V_0_vld_in();
void thread_AXI_video_strm_V_user_V_0_vld_out();
void thread_ap_CS_fsm_pp1_stage0();
void thread_ap_CS_fsm_pp2_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state7();
void thread_ap_block_pp1_stage0();
void thread_ap_block_pp1_stage0_01001();
void thread_ap_block_pp1_stage0_11001();
void thread_ap_block_pp1_stage0_subdone();
void thread_ap_block_pp2_stage0();
void thread_ap_block_pp2_stage0_11001();
void thread_ap_block_pp2_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state5_pp1_stage0_iter0();
void thread_ap_block_state6_pp1_stage0_iter1();
void thread_ap_block_state8_pp2_stage0_iter0();
void thread_ap_block_state9_pp2_stage0_iter1();
void thread_ap_condition_529();
void thread_ap_done();
void thread_ap_enable_pp1();
void thread_ap_enable_pp2();
void thread_ap_idle();
void thread_ap_idle_pp1();
void thread_ap_idle_pp2();
void thread_ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4();
void thread_ap_phi_mux_eol_2_i_phi_fu_273_p4();
void thread_ap_phi_mux_eol_i_phi_fu_215_p4();
void thread_ap_phi_mux_p_Val2_s_phi_fu_262_p4();
void thread_ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245();
void thread_ap_phi_reg_pp1_iter1_p_Val2_s_reg_258();
void thread_ap_predicate_op73_read_state6();
void thread_ap_ready();
void thread_brmerge_i_fu_357_p2();
void thread_cols_V_fu_319_p0();
void thread_cols_V_fu_319_p1();
void thread_exitcond5_i_fu_332_p2();
void thread_exitcond_i_fu_343_p2();
void thread_i_V_fu_337_p2();
void thread_img_cols_V_blk_n();
void thread_img_cols_V_out_blk_n();
void thread_img_cols_V_out_din();
void thread_img_cols_V_out_write();
void thread_img_cols_V_read();
void thread_img_data_stream_0_V_blk_n();
void thread_img_data_stream_0_V_din();
void thread_img_data_stream_0_V_write();
void thread_img_data_stream_1_V_blk_n();
void thread_img_data_stream_1_V_din();
void thread_img_data_stream_1_V_write();
void thread_img_data_stream_2_V_blk_n();
void thread_img_data_stream_2_V_din();
void thread_img_data_stream_2_V_write();
void thread_img_rows_V_blk_n();
void thread_img_rows_V_out_blk_n();
void thread_img_rows_V_out_din();
void thread_img_rows_V_out_write();
void thread_img_rows_V_read();
void thread_internal_ap_ready();
void thread_j_V_fu_348_p2();
void thread_real_start();
void thread_rows_V_fu_315_p0();
void thread_rows_V_fu_315_p1();
void thread_start_out();
void thread_start_write();
void thread_stream_in_TDATA_blk_n();
void thread_stream_in_TREADY();
void thread_tmp_user_V_fu_323_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
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/*
* Copyright (c) 2016 Baptiste Roux.
* email: <baptiste.roux AT inria.fr>.
*/
/*
* File: nocIpc.h
* Noc for inter systemC kernel communication
*/
#ifndef _NOC_BASE
#define _NOC_BASE
//nocCtrl primitives
#include "noc_helper.h"
//configuration struct
#include "models/utility/socConfigStruct.h"
// list of task and MS calculation
#include <math.h>
#include <vector>
//systemC header
#include "systemc.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "tlm_utils/tlm_quantumkeeper.h"
#ifndef NDEBUG
# define ASSERT(condition, message) \
do { \
if (! (condition)) { \
std::cerr << "Assertion `" #condition "` failed in " << __FILE__ \
<< " line " << __LINE__ << ": " << message << std::endl; \
std::terminate(); \
} \
} while (false)
#ifdef NOC_DEBUG
#define NOC_DEBUG_BIND
#define NOC_DEBUG_LOG
#endif
#else
# define ASSERT(condition, message) do { } while (false)
#endif
//register getter/setter
#define _RNOC(NAME) (((uintptr_t)noc_register+ (RNOC_##NAME)))
namespace noc{
class nocItf_base: public sc_core::sc_module
{
protected:
virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& delay)=0;
//NoC job management
std::map<task_t, uint> pendingOrder;
std::map<task_t, uint> pendingWait;
std::vector<waitPoint> wakeupTask;
std::vector<orderHeader> rcvOrder;
//NoC discover
std::map<uint,noc::clPos> nocDiscover;
//NoC ctrl buffer
uint8_t *noc_register;
virtual void cpuCmdEvent()=0;
//PowerLog buffer
float enj_noc;
uint tns_noc;
public:
/* irq lines */
sc_out<bool> irq_wakeUp;
sc_out<bool> irq_orderRcv;
/* tlm sockets */
tlm_utils::simple_target_socket<nocItf_base> cmd_Ssk;
tlm_utils::simple_initiator_socket<nocItf_base> DMA_Msk;
nocItf_base(sc_core::sc_module_name name, std::map<uint, noc::clPos>nocDiscover);
~nocItf_base();
//nocSk getter
virtual tlm_utils::simple_target_socket<nocItf_base>* get_noc_Ssk(){return NULL;};
virtual tlm_utils::simple_initiator_socket<nocItf_base>* get_noc_Msk(){return NULL;};
//FIXME: change encapsulation if possible: this function only relevant for IPC impl
virtual void openUnixIpc(std::string socketPath){}
virtual void closeUnixIpc(){}
virtual void syncUnixMsg(){}
};
class nocRouter_base
{
protected:
std::map<uint64_t,uint> clMapOnSk;
std::map<uint,clPos> skToClpos;
uint nb_sk;
uint toClusterAddr(uint64_t &addr);
//Monitor Systems vars
sb::nocCnf nocConfig;
void comLog(uint fromSk, uint toSk, size_t size);
uint nHop(clPos from, clPos to);
float enj_log;
uint tns_log;
public:
nocRouter_base(int nbSk, sb::nocCnf config);
~nocRouter_base(){}
virtual uint bindToCluster(tlm_utils::simple_target_socket<nocItf_base>* nocItf_Ssk,
tlm_utils::simple_initiator_socket<nocItf_base>* nocItf_Msk,
uint64_t clBaseAddr, uint8_t cl_x, uint8_t cl_y)=0;
//FIXME: change encapsulation if possible: this function only relevant for IPC impl
virtual void startRouter(){}
};
}// end namespace noc
#endif /*_NOC_BASE*/
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _axis_timestamper_HH_
#define _axis_timestamper_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct axis_timestamper : public sc_module {
// Port declarations 13
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_in< sc_lv<64> > data_in_TDATA;
sc_in< sc_logic > data_in_TVALID;
sc_out< sc_logic > data_in_TREADY;
sc_in< sc_lv<8> > data_in_TKEEP;
sc_in< sc_lv<1> > data_in_TLAST;
sc_out< sc_lv<64> > data_out_TDATA;
sc_out< sc_logic > data_out_TVALID;
sc_in< sc_logic > data_out_TREADY;
sc_out< sc_lv<8> > data_out_TKEEP;
sc_out< sc_lv<1> > data_out_TLAST;
sc_in< sc_lv<1> > start_V;
// Module declarations
axis_timestamper(sc_module_name name);
SC_HAS_PROCESS(axis_timestamper);
~axis_timestamper();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_lv<64> > timestamp_V;
sc_signal< sc_lv<1> > timestamp_flag_V;
sc_signal< sc_logic > data_in_TDATA_blk_n;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<1> > tmp_1_nbreadreq_fu_70_p5;
sc_signal< sc_lv<1> > tmp_2_nbwritereq_fu_82_p5;
sc_signal< sc_logic > data_out_TDATA_blk_n;
sc_signal< sc_lv<64> > out_word_data_V_fu_129_p3;
sc_signal< bool > ap_predicate_op26_read_state1;
sc_signal< bool > ap_block_state1;
sc_signal< bool > ap_predicate_op30_write_state1;
sc_signal< bool > ap_predicate_op35_write_state1;
sc_signal< bool > ap_block_state1_io;
sc_signal< sc_lv<1> > tmp_last_V_fu_158_p1;
sc_signal< sc_lv<64> > tmp_fu_123_p2;
sc_signal< sc_lv<1> > ap_NS_fsm;
sc_signal< bool > ap_condition_87;
sc_signal< bool > ap_condition_125;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_fsm_state1;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<1> ap_const_lv1_1;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<64> ap_const_lv64_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_block_state1();
void thread_ap_block_state1_io();
void thread_ap_condition_125();
void thread_ap_condition_87();
void thread_ap_predicate_op26_read_state1();
void thread_ap_predicate_op30_write_state1();
void thread_ap_predicate_op35_write_state1();
void thread_ap_rst_n_inv();
void thread_data_in_TDATA_blk_n();
void thread_data_in_TREADY();
void thread_data_out_TDATA();
void thread_data_out_TDATA_blk_n();
void thread_data_out_TKEEP();
void thread_data_out_TLAST();
void thread_data_out_TVALID();
void thread_out_word_data_V_fu_129_p3();
void thread_tmp_1_nbreadreq_fu_70_p5();
void thread_tmp_2_nbwritereq_fu_82_p5();
void thread_tmp_fu_123_p2();
void thread_tmp_last_V_fu_158_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _acc4kmau_HH_
#define _acc4kmau_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "HLS_malloc_1_s.h"
#include "HLS_free_1_s.h"
#include "acc4kmau_req_cmd.h"
#include "acc4kmau_req_list.h"
#include "acc4kmau_req_size.h"
namespace ap_rtl {
struct acc4kmau : public sc_module {
// Port declarations 19
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<32> > alloc_1_size;
sc_out< sc_logic > alloc_1_size_ap_vld;
sc_in< sc_logic > alloc_1_size_ap_ack;
sc_in< sc_lv<32> > alloc_1_addr;
sc_in< sc_logic > alloc_1_addr_ap_vld;
sc_out< sc_logic > alloc_1_addr_ap_ack;
sc_out< sc_lv<32> > alloc_1_free_target;
sc_out< sc_logic > alloc_1_free_target_ap_vld;
sc_in< sc_logic > alloc_1_free_target_ap_ack;
sc_out< sc_lv<8> > alloc_1_cmd;
sc_out< sc_logic > alloc_1_cmd_ap_vld;
sc_in< sc_logic > alloc_1_cmd_ap_ack;
sc_out< sc_lv<32> > ap_return;
// Module declarations
acc4kmau(sc_module_name name);
SC_HAS_PROCESS(acc4kmau);
~acc4kmau();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
acc4kmau_req_cmd* req_cmd_U;
acc4kmau_req_list* req_list_U;
acc4kmau_req_size* req_size_U;
HLS_malloc_1_s* grp_HLS_malloc_1_s_fu_99;
HLS_free_1_s* grp_HLS_free_1_s_fu_113;
sc_signal< sc_lv<6> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<10> > req_cmd_address0;
sc_signal< sc_logic > req_cmd_ce0;
sc_signal< sc_lv<2> > req_cmd_q0;
sc_signal< sc_lv<10> > req_list_address0;
sc_signal< sc_logic > req_list_ce0;
sc_signal< sc_lv<12> > req_list_q0;
sc_signal< sc_lv<10> > req_size_address0;
sc_signal< sc_logic > req_size_ce0;
sc_signal< sc_lv<11> > req_size_q0;
sc_signal< sc_lv<64> > tmp_fu_126_p1;
sc_signal< sc_lv<64> > tmp_reg_186;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<12> > size_reg_201;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > tmp_1_fu_136_p2;
sc_signal< sc_lv<1> > tmp_1_reg_207;
sc_signal< sc_lv<32> > i_1_fu_142_p2;
sc_signal< sc_lv<32> > i_1_reg_211;
sc_signal< sc_lv<1> > tmp_3_fu_148_p2;
sc_signal< sc_lv<1> > tmp_3_reg_216;
sc_signal< sc_lv<1> > tmp_5_fu_160_p2;
sc_signal< sc_lv<1> > tmp_5_reg_220;
sc_signal< sc_lv<11> > req_size_load_reg_229;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_ap_start;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_ap_done;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_ap_idle;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_ap_ready;
sc_signal< sc_lv<32> > grp_HLS_malloc_1_s_fu_99_allocator_size;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_allocator_size_ap_vld;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_allocator_addr_ap_ack;
sc_signal< sc_lv<32> > grp_HLS_malloc_1_s_fu_99_allocator_free_targe;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_allocator_free_targe_ap_vld;
sc_signal< sc_lv<8> > grp_HLS_malloc_1_s_fu_99_allocator_cmd;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_allocator_cmd_ap_vld;
sc_signal< sc_lv<32> > grp_HLS_malloc_1_s_fu_99_ap_return;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_ap_start;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_ap_done;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_ap_idle;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_ap_ready;
sc_signal< sc_lv<32> > grp_HLS_free_1_s_fu_113_allocator_size;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_allocator_size_ap_vld;
sc_signal< sc_lv<32> > grp_HLS_free_1_s_fu_113_allocator_free_targe;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_allocator_free_targe_ap_vld;
sc_signal< sc_lv<8> > grp_HLS_free_1_s_fu_113_allocator_cmd;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_allocator_cmd_ap_vld;
sc_signal< sc_lv<32> > i_reg_87;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< bool > ap_predicate_op41_call_state5;
sc_signal< bool > ap_block_state5_on_subcall_done;
sc_signal< sc_logic > grp_HLS_malloc_1_s_fu_99_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_logic > grp_HLS_free_1_s_fu_113_ap_start_reg;
sc_signal< sc_lv<32> > r_fu_44;
sc_signal< sc_lv<33> > tmp_cast_fu_132_p1;
sc_signal< sc_lv<33> > tmp_4_fu_154_p2;
sc_signal< sc_lv<6> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<6> ap_ST_fsm_state1;
static const sc_lv<6> ap_ST_fsm_state2;
static const sc_lv<6> ap_ST_fsm_state3;
static const sc_lv<6> ap_ST_fsm_state4;
static const sc_lv<6> ap_ST_fsm_state5;
static const sc_lv<6> ap_ST_fsm_state6;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_4;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<33> ap_const_lv33_1FFFFFE70;
static const sc_lv<33> ap_const_lv33_270;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_alloc_1_addr_ap_ack();
void thread_alloc_1_cmd();
void thread_alloc_1_cmd_ap_vld();
void thread_alloc_1_free_target();
void thread_alloc_1_free_target_ap_vld();
void thread_alloc_1_size();
void thread_alloc_1_size_ap_vld();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_block_state5_on_subcall_done();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_predicate_op41_call_state5();
void thread_ap_ready();
void thread_ap_return();
void thread_grp_HLS_free_1_s_fu_113_ap_start();
void thread_grp_HLS_malloc_1_s_fu_99_ap_start();
void thread_i_1_fu_142_p2();
void thread_req_cmd_address0();
void thread_req_cmd_ce0();
void thread_req_list_address0();
void thread_req_list_ce0();
void thread_req_size_address0();
void thread_req_size_ce0();
void thread_tmp_1_fu_136_p2();
void thread_tmp_3_fu_148_p2();
void thread_tmp_4_fu_154_p2();
void thread_tmp_5_fu_160_p2();
void thread_tmp_cast_fu_132_p1();
void thread_tmp_fu_126_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
#define SC_INCLUDE_FX
#include <systemc.h>
#include<fstream>
#include <iostream>
#include <vector>
using namespace std;
//--------------------------------------------------------
// CONV_RELU_1
// - in_feature_map: 150528 (3, 224, 224)
// - out_feature_map: 193600 (64, 55, 55)
//--------------------------------------------------------
SC_MODULE(CONV_RELU_1)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 150528};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 193600};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> weight1{"weight1", 23232};
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> bias1{"bias1", 64};
vector<double> weight1;
vector<double> bias1;
int IN_CHANNELS;
int IN_HEIGHT = 224;
int IN_WIDTH = 224;
int KERNAL_SIZE = 11;
int OUT_CHANNELS = 64;
int OUT_HEIGHT = 55;
int OUT_WIDTH = 55;
int STRIDE = 4;
int PADDING = 2;
void run(){
// const int IN_CHANNELS = 3;
// const int IN_HEIGHT = 224;
// const int IN_WIDTH = 224;
// const int KERNAL_SIZE = 11;
// const int OUT_CHANNELS = 64;
// const int OUT_HEIGHT = 55;
// const int OUT_WIDTH = 55;
// const int STRIDE = 4;
// const int PADDING = 2;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/conv1_bias.txt");
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
//bias1[bcnt].write((sc_fixed_fast<45,17>)(b_value));
bias1.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/conv1_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
//weight1[wcnt].write((sc_fixed_fast<45,17>)(w_value));
weight1.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
//cout<<"bias.size: "<<bias1.size()<<" bcnt: "<<bcnt<<endl;
// for(int i=0; i<bias1.size(); i++){
// cout<<"bias1["<<i<<"]: "<<bias1[i]<<endl;
// }
//cout<<"weight1.size: "<<weight1[weight1.size()-1]<<" wcnt: "<<wcnt<<endl;
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//conv1
if(in_valid.read()) {
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
//sc_fixed_fast<45,17> partial_sum;
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow -2, stride*ocol + kcol -2]
i_ptr_x = STRIDE*ocol + kcol - PADDING;
i_ptr_y = STRIDE*orow + krow - PADDING;
i_ptr = ic*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
w_ptr = oc*IN_CHANNELS*KERNAL_SIZE*KERNAL_SIZE + ic*KERNAL_SIZE*KERNAL_SIZE + krow*KERNAL_SIZE + kcol; //[oc, ic, krow, kcol]]
if(!(i_ptr_x<0 || i_ptr_x>=IN_WIDTH || i_ptr_y<0 || i_ptr_y>=IN_HEIGHT)){
partial_sum += (in_feature_map[i_ptr] * weight1[w_ptr]);
}
}
}
}
if((partial_sum + bias1[oc])>0){
//out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = partial_sum + bias1[oc]; //(sc_fixed_fast<45,17>)(partial_sum);
partial_sum += bias1[oc];
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = (sc_fixed_fast<45,17>)partial_sum;
}
else{
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = 0;
}
}
}
}
out_valid.write(1);
}
//std::cout<<"conv1_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
SC_CTOR(CONV_RELU_1)
{
SC_METHOD(run);
sensitive << clk.pos();
}
};
//--------------------------------------------------------
// MAX_POOLING_1
// - in_feature_map: 193600 (64, 55, 55)
// - out_feature_map: 46656 (64, 27, 27)
//--------------------------------------------------------
SC_MODULE(MAX_POOLING_1)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 193600};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 46656};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
void run(){
const int IN_CHANNELS = 64;
const int IN_HEIGHT = 55;
const int IN_WIDTH = 55;
const int KERNAL_SIZE = 3;
const int OUT_CHANNELS = 64;
const int OUT_HEIGHT = 27;
const int OUT_WIDTH = 27;
const int STRIDE = 2;
//const int PADDING = 2;
out_valid.write(0);
if ( rst.read() == 1 ) {
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//maxpool1
if(in_valid.read()) {
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
sc_fixed_fast<45,17> largest;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
largest = 0;
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow, stride*ocol + kcol]
i_ptr_x = STRIDE*ocol + kcol;
i_ptr_y = STRIDE*orow + krow;
i_ptr = oc*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
if(in_feature_map[i_ptr] > largest){
largest = in_feature_map[i_ptr];
}
}
}
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = largest;
}
}
}
out_valid.write(1);
//std::cout<<"mp1_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(MAX_POOLING_1)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// CONV_RELU_2
// - in_feature_map: 46656 (64, 27, 27)
// - out_feature_map: 139968 (192, 27, 27)
//--------------------------------------------------------
SC_MODULE(CONV_RELU_2)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 46656};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 139968};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> weight2{"weight2", 307200};
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> bias2{"bias2", 192};
vector<double> weight2;
vector<double> bias2;
void run(){
const int IN_CHANNELS = 64;
const int IN_HEIGHT = 27;
const int IN_WIDTH = 27;
const int KERNAL_SIZE = 5;
const int OUT_CHANNELS = 192;
const int OUT_HEIGHT = 27;
const int OUT_WIDTH = 27;
const int STRIDE = 1;
const int PADDING = 2;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/conv2_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias2 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias2.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/conv2_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight2.push_back(w_value);
wcnt++;
}
//for(int i=0; i<64; i++){
// std::cout<<"weight_"<<i<<": "<<weight1[i]<<std::endl;
//}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//conv2
if(in_valid.read()) {
//for(int i=0; i<64; i++){
// std::cout<<"weight2_"<<i<<": "<<weight2[i]<<std::endl;
//}
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow -2, stride*ocol + kcol -2]
i_ptr_x = STRIDE*ocol + kcol - PADDING;
i_ptr_y = STRIDE*orow + krow - PADDING;
i_ptr = ic*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
w_ptr = oc*IN_CHANNELS*KERNAL_SIZE*KERNAL_SIZE + ic*KERNAL_SIZE*KERNAL_SIZE + krow*KERNAL_SIZE + kcol; //[oc, ic, krow, kcol]]
if(!(i_ptr_x<0 || i_ptr_x>=IN_WIDTH || i_ptr_y<0 || i_ptr_y>=IN_HEIGHT)){
partial_sum +=( in_feature_map[i_ptr] * weight2[w_ptr]);
}
}
}
}
if((partial_sum + bias2[oc])>0){
partial_sum += bias2[oc];
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = 0;
}
}
}
}
out_valid.write(1);
//std::cout<<"conv2_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(CONV_RELU_2)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// MAX_POOLING_2
// - in_feature_map: 139968 (192, 27, 27)
// - out_feature_map: 32448 (192, 13, 13)
//--------------------------------------------------------
SC_MODULE(MAX_POOLING_2)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 139968};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 32448};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
void run(){
const int IN_CHANNELS = 192;
const int IN_HEIGHT = 27;
const int IN_WIDTH = 27;
const int KERNAL_SIZE = 3;
const int OUT_CHANNELS = 192;
const int OUT_HEIGHT = 13;
const int OUT_WIDTH = 13;
const int STRIDE = 2;
//const int PADDING = 2;
out_valid.write(0);
if ( rst.read() == 1 ) {
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//maxpool2
if(in_valid.read()) {
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
sc_fixed_fast<45,17> largest;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
largest = 0;
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow, stride*ocol + kcol]
i_ptr_x = STRIDE*ocol + kcol;
i_ptr_y = STRIDE*orow + krow;
i_ptr = oc*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
if(in_feature_map[i_ptr] > largest){
largest = in_feature_map[i_ptr];
}
}
}
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = largest;
}
}
}
out_valid.write(1);
//std::cout<<"mp2_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(MAX_POOLING_2)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// CONV_RELU_3
// - in_feature_map: 32448 (192, 13, 13)
// - out_feature_map: 64896 (384, 13, 13)
//--------------------------------------------------------
SC_MODULE(CONV_RELU_3)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 32448};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 64896};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> weight3{"weight3", 663552};
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> bias3{"bias3", 384};
vector<double> weight3;
vector<double> bias3;
void run(){
const int IN_CHANNELS = 192;
const int IN_HEIGHT = 13;
const int IN_WIDTH = 13;
const int KERNAL_SIZE = 3;
const int OUT_CHANNELS = 384;
const int OUT_HEIGHT = 13;
const int OUT_WIDTH = 13;
const int STRIDE = 1;
const int PADDING = 1;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/conv3_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias3 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias3.push_back(b_value);
//std::cout << "bias1[" << bcnt << "]: " << b_value << std::endl;
bcnt++;
}
std::ifstream wfile("data/conv3_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight3.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//conv3
if(in_valid.read()) {
//for(int i=0; i<64; i++){
// std::cout<<"weight3_"<<i<<": "<<weight3[i]<<std::endl;
//}
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow -2, stride*ocol + kcol -2]
i_ptr_x = STRIDE*ocol + kcol - PADDING;
i_ptr_y = STRIDE*orow + krow - PADDING;
i_ptr = ic*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
w_ptr = oc*IN_CHANNELS*KERNAL_SIZE*KERNAL_SIZE + ic*KERNAL_SIZE*KERNAL_SIZE + krow*KERNAL_SIZE + kcol; //[oc, ic, krow, kcol]]
if(!(i_ptr_x<0 || i_ptr_x>=IN_WIDTH || i_ptr_y<0 || i_ptr_y>=IN_HEIGHT)){
partial_sum += (in_feature_map[i_ptr] * weight3[w_ptr]);
}
}
}
}
if((partial_sum + bias3[oc])>0){
partial_sum += bias3[oc];
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = 0;
}
}
}
}
out_valid.write(1);
//std::cout<<"conv3_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(CONV_RELU_3)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// CONV_RELU_4
// - in_feature_map: 64896 (384, 13, 13)
// - out_feature_map: 43264 (256, 13, 13)
//--------------------------------------------------------
SC_MODULE(CONV_RELU_4)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 64896};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 43264};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> weight4{"weight4", 884736};
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> bias4{"bias4", 256};
vector<double> weight4;
vector<double> bias4;
void run(){
const int IN_CHANNELS = 384;
const int IN_HEIGHT = 13;
const int IN_WIDTH = 13;
const int KERNAL_SIZE = 3;
const int OUT_CHANNELS = 256;
const int OUT_HEIGHT = 13;
const int OUT_WIDTH = 13;
const int STRIDE = 1;
const int PADDING = 1;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/conv4_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias4 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias4.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/conv4_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight4.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//conv4
if(in_valid.read()) {
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow -2, stride*ocol + kcol -2]
i_ptr_x = STRIDE*ocol + kcol - PADDING;
i_ptr_y = STRIDE*orow + krow - PADDING;
i_ptr = ic*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
w_ptr = oc*IN_CHANNELS*KERNAL_SIZE*KERNAL_SIZE + ic*KERNAL_SIZE*KERNAL_SIZE + krow*KERNAL_SIZE + kcol; //[oc, ic, krow, kcol]]
if(!(i_ptr_x<0 || i_ptr_x>=IN_WIDTH || i_ptr_y<0 || i_ptr_y>=IN_HEIGHT)){
partial_sum += (in_feature_map[i_ptr] * weight4[w_ptr]);
}
}
}
}
if((partial_sum + bias4[oc])>0){
partial_sum += bias4[oc];
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = 0;
}
}
}
}
out_valid.write(1);
//std::cout<<"conv4_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(CONV_RELU_4)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// CONV_RELU_5
// - in_feature_map: 43264 (256, 13, 13)
// - out_feature_map: 43264 (256, 13, 13)
//--------------------------------------------------------
SC_MODULE(CONV_RELU_5)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 43264};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 43264};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> weight5{"weight5", 589824};
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> bias5{"bias5", 256};
vector<double> weight5;
vector<double> bias5;
void run(){
const int IN_CHANNELS = 256;
const int IN_HEIGHT = 13;
const int IN_WIDTH = 13;
const int KERNAL_SIZE = 3;
const int OUT_CHANNELS = 256;
const int OUT_HEIGHT = 13;
const int OUT_WIDTH = 13;
const int STRIDE = 1;
const int PADDING = 1;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/conv5_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias5 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias5.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/conv5_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight5.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//conv5
if(in_valid.read()) {
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow -2, stride*ocol + kcol -2]
i_ptr_x = STRIDE*ocol + kcol - PADDING;
i_ptr_y = STRIDE*orow + krow - PADDING;
i_ptr = ic*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
w_ptr = oc*IN_CHANNELS*KERNAL_SIZE*KERNAL_SIZE + ic*KERNAL_SIZE*KERNAL_SIZE + krow*KERNAL_SIZE + kcol; //[oc, ic, krow, kcol]]
if(!(i_ptr_x<0 || i_ptr_x>=IN_WIDTH || i_ptr_y<0 || i_ptr_y>=IN_HEIGHT)){
partial_sum += (in_feature_map[i_ptr] * weight5[w_ptr]);
}
}
}
}
if((partial_sum + bias5[oc])>0){
partial_sum += bias5[oc];
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WID
|
TH + ocol] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = 0;
}
}
}
}
out_valid.write(1);
//std::cout<<"conv5_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(CONV_RELU_5)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// MAX_POOLING_3
// - in_feature_map: 43264 (256, 13, 13)
// - out_feature_map: 9216 (256, 6, 6)
//--------------------------------------------------------
SC_MODULE(MAX_POOLING_3)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 43264};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 9216};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
void run(){
const int IN_CHANNELS = 256;
const int IN_HEIGHT = 13;
const int IN_WIDTH = 13;
const int KERNAL_SIZE = 3;
const int OUT_CHANNELS = 256;
const int OUT_HEIGHT = 6;
const int OUT_WIDTH = 6;
const int STRIDE = 2;
//const int PADDING = 2;
out_valid.write(0);
if ( rst.read() == 1 ) {
for(int i=0; i<OUT_CHANNELS*OUT_HEIGHT*OUT_WIDTH; i++){
out_feature_map[i].write(0.0);
}
}
//maxpool3
if(in_valid.read()) {
int i_ptr, w_ptr;
int i_ptr_x, i_ptr_y;
sc_fixed_fast<45,17> largest;
for(int oc=0; oc<OUT_CHANNELS; oc++){
for(int orow=0; orow<OUT_HEIGHT; orow++){
for(int ocol=0; ocol<OUT_WIDTH; ocol++){
largest = 0;
for(int krow=0; krow<KERNAL_SIZE; krow++){
for(int kcol=0; kcol<KERNAL_SIZE; kcol++){
//[ic, wrow, wcol] -> [ic, stride*orow + krow, stride*ocol + kcol]
i_ptr_x = STRIDE*ocol + kcol;
i_ptr_y = STRIDE*orow + krow;
i_ptr = oc*IN_HEIGHT*IN_WIDTH + i_ptr_y*IN_WIDTH + i_ptr_x;
if(in_feature_map[i_ptr] > largest){
largest = in_feature_map[i_ptr];
}
}
}
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = largest;
}
}
}
out_valid.write(1);
//std::cout<<"mp3_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(MAX_POOLING_3)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// LINEAR_RELU_1
// - in_feature_map: 9216
// - out_feature_map: 4096
//--------------------------------------------------------
SC_MODULE(LINEAR_RELU_1)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 9216};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 4096};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> weight6{"weight6", 37748736};
//sc_vector<sc_signal<sc_fixed_fast<45,17>>> bias6{"bias6", 4096};
vector<double> weight6;
vector<double> bias6;
void run(){
const int IN_CHANNELS = 9216;
const int OUT_CHANNELS = 4096;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/fc6_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias6 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias6.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/fc6_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight6.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS; i++){
out_feature_map[i].write(0.0);
}
}
//fc6 + RELU
if(in_valid.read()) {
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
partial_sum += in_feature_map[ic] * weight6[oc*IN_CHANNELS + ic];
}
//RELU
if((partial_sum + bias6[oc])>0){
partial_sum += bias6[oc];
out_feature_map[oc] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc] = 0;
}
}
out_valid.write(1);
//std::cout<<"fc6_result[0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(LINEAR_RELU_1)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// LINEAR_RELU_2
// - in_feature_map: 4096
// - out_feature_map: 4096
//--------------------------------------------------------
SC_MODULE(LINEAR_RELU_2)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 4096};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 4096};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
vector<double> weight7;
vector<double> bias7;
void run(){
const int IN_CHANNELS = 4096;
const int OUT_CHANNELS = 4096;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/fc7_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias7 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias7.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/fc7_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight7.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS; i++){
out_feature_map[i].write(0.0);
}
}
//fc7 + RELU
if(in_valid.read()) {
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
partial_sum += in_feature_map[ic] * weight7[oc*IN_CHANNELS + ic];
}
//RELU
if((partial_sum + bias7[oc])>0){
partial_sum += bias7[oc];
out_feature_map[oc] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc] = 0;
}
}
out_valid.write(1);
//std::cout<<"fc7_result[0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(LINEAR_RELU_2)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
//--------------------------------------------------------
// LINEAR_3
// - in_feature_map: 4096
// - out_feature_map: 1000
//--------------------------------------------------------
SC_MODULE(LINEAR_3)
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 4096};
sc_vector<sc_out<sc_fixed_fast<45,17>>> out_feature_map{"out_feature_map", 1000};
sc_in<bool> in_valid;
sc_out<bool> out_valid;
vector<double> weight8;
vector<double> bias8;
void run(){
const int IN_CHANNELS = 4096;
const int OUT_CHANNELS = 1000;
out_valid.write(0);
//read weight and bias
if ( rst.read() == 1 ) {
std::ifstream bfile("data/fc8_bias.txt");
if (!bfile.is_open()) {
std::cerr << "Unable to open bias8 file!" << std::endl;
return;
}
double b_value;
int bcnt = 0;
while(bfile >> b_value) {
bias8.push_back(b_value);
bcnt++;
}
std::ifstream wfile("data/fc8_weight.txt");
double w_value;
int wcnt = 0;
while(wfile >> w_value) {
weight8.push_back(w_value);
wcnt++;
}
wfile.close();
bfile.close();
for(int i=0; i<OUT_CHANNELS; i++){
out_feature_map[i].write(0.0);
}
}
//fc8
if(in_valid.read()) {
double partial_sum;
for(int oc=0; oc<OUT_CHANNELS; oc++){
partial_sum = 0;
for(int ic=0; ic<IN_CHANNELS; ic++){
partial_sum += in_feature_map[ic] * weight8[oc*IN_CHANNELS + ic];
}
partial_sum += bias8[oc];
out_feature_map[oc] = (sc_fixed_fast<45,17>)(partial_sum);
}
out_valid.write(1);
//std::cout<<"fc7_result[0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(LINEAR_3)
{
SC_METHOD(run);
sensitive << clk.pos() ;
}
};
|
#pragma once
#include "systemc.hpp"
#include "tlm.hpp"
#include "common.hpp"
struct Observer_module : sc_core::sc_module
{
sc_core::sc_export<sc_core::sc_signal_out_if<Data_t>> actual_export { "actual_export" };
sc_core::sc_port<sc_core::sc_signal_in_if<Data_t>> expect_port { "expect_port" };
sc_core::sc_port<sc_core::sc_signal_in_if<bool>> running_port { "running_port" };
Observer_module( sc_core::sc_module_name instance );
void start_of_simulation();
void prepare_thread();
void checker_thread();
private:
uint16_t observed_count{ 0 };
uint16_t failures_count{ 0 };
sc_core::sc_signal<Data_t> actual_data;
tlm::tlm_fifo<Data_t> expected_fifo{ -1 }; // unbounded
// Following are here only for tracing purposes
Data_t received_value{};
Data_t expected_value{};
Data_t actual_value{};
};
|
#include <systemc.h>
#include "memory.cpp"
int sc_main (int argc, char* argv[]) {
int data;
ram mem("MEM", 1024);
// Open VCD file
sc_trace_file *wf = sc_create_vcd_trace_file("memory");
wf->set_time_unit(1, SC_NS);
// Dump the desired signals
sc_trace(wf, data, "data");
sc_start();
cout << "@" << sc_time_stamp()<< endl;
printf("Writing in zero time\n");
printf("WR: addr = 0x10, data = 0xaced\n");
printf("WR: addr = 0x12, data = 0xbeef\n");
printf("WR: addr = 0x13, data = 0xdead\n");
printf("WR: addr = 0x14, data = 0x1234\n");
mem.wr(0x10, 0xaced);
mem.wr(0x11, 0xbeef);
mem.wr(0x12, 0xdead);
mem.wr(0x13, 0x1234);
cout << "@" << sc_time_stamp()<< endl;
cout << "Reading in zero time" <<endl;
data = mem.rd(0x10);
printf("Rd: addr = 0x10, data = %x\n",data);
data = mem.rd(0x11);
printf("Rd: addr = 0x11, data = %x\n",data);
data = mem.rd(0x12);
printf("Rd: addr = 0x12, data = %x\n",data);
data = mem.rd(0x13);
printf("Rd: addr = 0x13, data = %x\n",data);
cout << "@" << sc_time_stamp()<< endl;
cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl;
sc_close_vcd_trace_file(wf);
return 0;// Terminate simulation
}
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "sdctrl_cfg.h"
#include "../riverlib/cache/tagmem.h"
namespace debugger {
SC_MODULE(sdctrl_cache) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Data path:
sc_in<bool> i_req_valid;
sc_in<bool> i_req_write;
sc_in<sc_uint<CFG_SDCACHE_ADDR_BITS>> i_req_addr;
sc_in<sc_uint<64>> i_req_wdata;
sc_in<sc_uint<8>> i_req_wstrb;
sc_out<bool> o_req_ready;
sc_out<bool> o_resp_valid;
sc_out<sc_uint<64>> o_resp_data;
sc_out<bool> o_resp_err;
sc_in<bool> i_resp_ready;
// Memory interface:
sc_in<bool> i_req_mem_ready;
sc_out<bool> o_req_mem_valid;
sc_out<bool> o_req_mem_write;
sc_out<sc_uint<CFG_SDCACHE_ADDR_BITS>> o_req_mem_addr;
sc_out<sc_biguint<SDCACHE_LINE_BITS>> o_req_mem_data;
sc_in<bool> i_mem_data_valid;
sc_in<sc_biguint<SDCACHE_LINE_BITS>> i_mem_data;
sc_in<bool> i_mem_fault;
// Debug interface
sc_in<bool> i_flush_valid;
sc_out<bool> o_flush_end;
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_cache);
sdctrl_cache(sc_module_name name,
bool async_reset);
virtual ~sdctrl_cache();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int abus = CFG_SDCACHE_ADDR_BITS;
static const int ibits = CFG_LOG2_SDCACHE_LINEBITS;
static const int lnbits = CFG_LOG2_SDCACHE_BYTES_PER_LINE;
static const int flbits = SDCACHE_FL_TOTAL;
// State machine states:
static const uint8_t State_Idle = 0;
static const uint8_t State_CheckHit = 2;
static const uint8_t State_TranslateAddress = 3;
static const uint8_t State_WaitGrant = 4;
static const uint8_t State_WaitResp = 5;
static const uint8_t State_CheckResp = 6;
static const uint8_t State_SetupReadAdr = 1;
static const uint8_t State_WriteBus = 7;
static const uint8_t State_FlushAddr = 8;
static const uint8_t State_FlushCheck = 9;
static const uint8_t State_Reset = 10;
static const uint8_t State_ResetWrite = 11;
static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_SDCACHE_BYTES_PER_LINE) - 1);
static const uint32_t FLUSH_ALL_VALUE = ((1 << ibits) - 1);
struct sdctrl_cache_registers {
sc_signal<bool> req_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> req_addr;
sc_signal<sc_uint<64>> req_wdata;
sc_signal<sc_uint<8>> req_wstrb;
sc_signal<sc_uint<4>> state;
sc_signal<bool> req_mem_valid;
sc_signal<bool> req_mem_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> mem_addr;
sc_signal<bool> mem_fault;
sc_signal<bool> write_first;
sc_signal<bool> write_flush;
sc_signal<bool> req_flush;
sc_signal<sc_uint<32>> flush_cnt;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_addr_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_o;
} v, r;
void sdctrl_cache_r_reset(sdctrl_cache_registers &iv) {
iv.req_write = 0;
iv.req_addr = 0;
iv.req_wdata = 0;
iv.req_wstrb = 0;
iv.state = State_Reset;
iv.req_mem_valid = 0;
iv.req_mem_write = 0;
iv.mem_addr = 0;
iv.mem_fault = 0;
iv.write_first = 0;
iv.write_flush = 0;
iv.req_flush = 0;
iv.flush_cnt = 0;
iv.line_addr_i = 0;
iv.cache_line_i = 0;
iv.cache_line_o = 0;
}
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_wdata_i;
sc_signal<sc_uint<SDCACHE_BYTES_PER_LINE>> line_wstrb_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_wflags_i;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_raddr_o;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_rdata_o;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_rflags_o;
sc_signal<bool> line_hit_o;
// Snoop signals:
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_snoop_addr_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_snoop_flags_o;
TagMem<abus, ibits, lnbits, flbits, 0> *mem0;
};
} // namespace debugger
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_higher_wordlength_1_xlconstant_1_0_H_
#define _design_higher_wordlength_1_xlconstant_1_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class design_higher_wordlength_1_xlconstant_1_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
design_higher_wordlength_1_xlconstant_1_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_VCC_1_1_H_
#define _icyradio_VCC_1_1_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_VCC_1_1 : public sc_module {
public:
xlconstant_v1_1_8<1,1> mod;
sc_out< sc_bv<1> > dout;
icyradio_VCC_1_1 (sc_core::sc_module_name name);
};
#endif
|
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