KlaraHDL/hardware_code_and_sec_median · Datasets at Hugging Face

content stringlengths 0 376M
prefix=@prefix@ exec_prefix=@prefix@ libdir=${prefix}/@libdir@ includedir=${prefix}/@includedir@ Name: riscv-spike_main Description: RISC-V ISA simulator library Version: git Depends: riscv-riscv riscv-softfloat Libs: -Wl,-rpath,${libdir} -L${libdir} -lspike_main Cflags: -I${includedir} URL: http://riscv.org/download.html#tab_spike
/debug_rom /debug_rom32 /debug_rom64 /debug_rom32.h /debug_rom64.h
static const unsigned char debug_rom_raw[] = { 0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x40, 0x05, 0x6f, 0x00, 0x40, 0x03, 0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00, 0x63, 0x10, 0x04, 0x02, 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x24, 0x00, 0xe3, 0x18, 0x04, 0xfc, 0x6f, 0xf0, 0xdf, 0xfd, 0x23, 0x26, 0x00, 0x10, 0x73, 0x00, 0x10, 0x00, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x22, 0x00, 0x10, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00, 0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b }; static const unsigned int debug_rom_raw_len = 104;
// See LICENSE.SiFive for license details. #include "riscv/encoding.h" #include "riscv/debug_rom_defines.h" .option norvc .global entry .global exception // Entry location on ebreak, Halt, or Breakpoint // It is the same for all harts. They branch when // their GO or RESUME bit is set. entry: jal zero, _entry resume: jal zero, _resume exception: jal zero, _exception _entry: // This fence is required because the execution may have written something // into the Abstract Data or Program Buffer registers. fence csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID // We continue to let the hart know that we are halted in order that // a DM which was reset is still made aware that a hart is halted. // We keep checking both whether there is something the debugger wants // us to do, or whether we should resume. entry_loop: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_HALTED(zero) lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) bnez s0, going csrr s0, CSR_MHARTID lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME) bnez s0, resume jal zero, entry_loop _exception: sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. ebreak going: csrr s0, CSR_DSCRATCH // Restore s0 here sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. fence fence.i jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM, // so we use fence and fence.i for safety. (rocket-chip doesn't have this // because jalr is special there) _resume: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. csrr s0, CSR_DSCRATCH // Restore s0 dret // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT. .section .whereto whereto: nop // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer, // or jal x0 resume, as desired. // Debug Module state machine tracks what is 'desired'. // We don't need/want to use jalr here because all of the // Variable ROM contents are set by // Debug Module before setting the OK_GO byte.
OUTPUT_ARCH( "riscv" ) ENTRY( entry ) SECTIONS { .whereto 0x300 : { (.whereto) } . = 0x800; .text : { (.text) } _end = .; }
# Recursive make is bad, but in this case we're cross compiling which is a # pretty unusual use case. CC = $(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy COMPILE = $(CC) -nostdlib -nostartfiles -I.. -Tlink.ld ELFS = debug_rom DEPS = debug_rom.S link.ld ../riscv/debug_rom_defines.h ../riscv/encoding.h all: $(patsubst %,%.h,$(ELFS)) %.h: %.raw xxd -i $^ \| sed "s/^unsigned/static const unsigned/" > $@ %.raw: % $(OBJCOPY) -O binary --only-section .text $^ $@ debug_rom: $(DEPS) $(COMPILE) -o $@ $^ clean: rm -f $(ELFS) debug_rom*.raw debug_rom.h

#include "rocc.h" #include "mmu.h" #include <cstring> class dummy_rocc_t : public rocc_t { public: const char* name() { return "dummy_rocc"; } reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2) { reg_t prev_acc = acc[insn.rs2]; if (insn.rs2 >= num_acc) illegal_instruction(); switch (insn.funct) { case 0: // acc <- xs1 acc[insn.rs2] = xs1; break; case 1: // xd <- acc (the only real work is the return statement below) break; case 2: // acc[rs2] <- Mem[xs1] acc[insn.rs2] = p->get_mmu()->load_uint64(xs1); break; case 3: // acc[rs2] <- accX + xs1 acc[insn.rs2] += xs1; break; default: illegal_instruction(); } return prev_acc; // in all cases, xd <- previous value of acc[rs2] } dummy_rocc_t() { memset(acc, 0, sizeof(acc)); } private: static const int num_acc = 4; reg_t acc[num_acc]; }; REGISTER_EXTENSION(dummy_rocc, []() { return new dummy_rocc_t; })
dummy_rocc_subproject_deps = \ spike_main \ riscv \ softfloat \ dummy_rocc_srcs = \ dummy_rocc.cc \
// The following is a RISC-V program to test the functionality of the // dummy RoCC accelerator. // Compile with riscv64-unknown-elf-gcc dummy_rocc_test.c // Run with spike --extension=dummy_rocc pk a.out #include <assert.h> #include <stdio.h> #include <stdint.h> int main() { uint64_t x = 123, y = 456, z = 0; // load x into accumulator 2 (funct=0) asm volatile ("custom0 x0, %0, 2, 0" : : "r"(x)); // read it back into z (funct=1) to verify it asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); assert(z == x); // accumulate 456 into it (funct=3) asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y)); // verify it asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); assert(z == x+y); // do it all again, but initialize acc2 via memory this time (funct=2) asm volatile ("custom0 x0, %0, 2, 2" : : "r"(&x)); asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y)); asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); assert(z == x+y); printf("success!\n"); }
// Auto-generated code const int reset_vec_size = 372; uint32_t reset_vec[reset_vec_size] = { 0x00100413, 0x01f41413, 0xf1402573, 0x00000597, 0x07458593, 0x00040067, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf1402573, 0x00000597, 0x03c58593, 0x10500073, 0xffdff06f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xedfe0dd0, 0x4a050000, 0x38000000, 0x44040000, 0x28000000, 0x11000000, 0x10000000, 0x00000000, 0x06010000, 0x0c040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, 0x03000000, 0x04000000, 0x00000000, 0x02000000, 0x03000000, 0x04000000, 0x0f000000, 0x02000000, 0x03000000, 0x14000000, 0x1b000000, 0x2c687465, 0x61697261, 0x622d656e, 0x2d657261, 0x00766564, 0x03000000, 0x10000000, 0x26000000, 0x2c687465, 0x61697261, 0x622d656e, 0x00657261, 0x01000000, 0x73757063, 0x00000000, 0x03000000, 0x04000000, 0x00000000, 0x01000000, 0x03000000, 0x04000000, 0x0f000000, 0x00000000, 0x03000000, 0x04000000, 0x2c000000, 0x00800000, 0x01000000, 0x40757063, 0x00000030, 0x03000000, 0x04000000, 0x3f000000, 0x80f0fa02, 0x03000000, 0x04000000, 0x4f000000, 0x00757063, 0x03000000, 0x04000000, 0x5b000000, 0x00000000, 0x03000000, 0x05000000, 0x5f000000, 0x79616b6f, 0x00000000, 0x03000000, 0x12000000, 0x1b000000, 0x2c687465, 0x69726120, 0x00656e61, 0x63736972, 0x00000076, 0x03000000, 0x0b000000, 0x66000000, 0x34367672, 0x66616d69, 0x00006364, 0x03000000, 0x0b000000, 0x70000000, 0x63736972, 0x76732c76, 0x00003933, 0x03000000, 0x00000000, 0x79000000, 0x01000000, 0x65746e69, 0x70757272, 0x6f632d74, 0x6f72746e, 0x72656c6c, 0x00000000, 0x03000000, 0x04000000, 0x83000000, 0x01000000, 0x03000000, 0x00000000, 0x94000000, 0x03000000, 0x0f000000, 0x1b000000, 0x63736972, 0x70632c76, 0x6e692d75, 0x00006374, 0x03000000, 0x04000000, 0xa9000000, 0x01000000, 0x02000000, 0x02000000, 0x02000000, 0x01000000, 0x6f6d656d, 0x38407972, 0x30303030, 0x00303030, 0x03000000, 0x07000000, 0x4f000000, 0x6f6d656d, 0x00007972, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000080, 0x00000000, 0x00000010, 0x02000000, 0x01000000, 0x00636f73, 0x03000000, 0x04000000, 0x00000000, 0x02000000, 0x03000000, 0x04000000, 0x0f000000, 0x02000000, 0x03000000, 0x1f000000, 0x1b000000, 0x2c687465, 0x61697261, 0x622d656e, 0x2d657261, 0x00636f73, 0x706d6973, 0x622d656c, 0x00007375, 0x03000000, 0x00000000, 0xb1000000, 0x01000000, 0x6e696c63, 0x30324074, 0x30303030, 0x00000030, 0x03000000, 0x0d000000, 0x1b000000, 0x63736972, 0x6c632c76, 0x30746e69, 0x00000000, 0x03000000, 0x10000000, 0xb8000000, 0x01000000, 0x03000000, 0x01000000, 0x07000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000002, 0x00000000, 0x00000c00, 0x03000000, 0x08000000, 0xcc000000, 0x746e6f63, 0x006c6f72, 0x02000000, 0x01000000, 0x74726175, 0x30303140, 0x30303030, 0x00000030, 0x03000000, 0x09000000, 0x1b000000, 0x3631736e, 0x61303535, 0x00000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000010, 0x00000000, 0x00100000, 0x03000000, 0x04000000, 0x3f000000, 0x80f0fa02, 0x03000000, 0x04000000, 0xd6000000, 0x00c20100, 0x03000000, 0x04000000, 0xe4000000, 0x01000000, 0x03000000, 0x04000000, 0xef000000, 0x02000000, 0x03000000, 0x04000000, 0xf9000000, 0x04000000, 0x02000000, 0x01000000, 0x656d6974, 0x38314072, 0x30303030, 0x00003030, 0x03000000, 0x0f000000, 0x1b000000, 0x706c7570, 0x6270612c, 0x6d69745f, 0x00007265, 0x03000000, 0x10000000, 0xe4000000, 0x04000000, 0x05000000, 0x06000000, 0x07000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000018, 0x00000000, 0x00100000, 0x03000000, 0x08000000, 0xcc000000, 0x746e6f63, 0x006c6f72, 0x02000000, 0x02000000, 0x02000000, 0x09000000, 0x64646123, 0x73736572, 0x6c65632d, 0x2300736c, 0x657a6973, 0x6c65632d, 0x6300736c, 0x61706d6f, 0x6c626974, 0x6f6d0065, 0x006c6564, 0x656d6974, 0x65736162, 0x6572662d, 0x6e657571, 0x63007963, 0x6b636f6c, 0x6572662d, 0x6e657571, 0x64007963, 0x63697665, 0x79745f65, 0x72006570, 0x73006765, 0x75746174, 0x69720073, 0x2c766373, 0x00617369, 0x2d756d6d, 0x65707974, 0x626c7400, 0x6c70732d, 0x23007469, 0x65746e69, 0x70757272, 0x65632d74, 0x00736c6c, 0x65746e69, 0x70757272, 0x6f632d74, 0x6f72746e, 0x72656c6c, 0x61687000, 0x656c646e, 0x6e617200, 0x00736567, 0x65746e69, 0x70757272, 0x652d7374, 0x6e657478, 0x00646564, 0x2d676572, 0x656d616e, 0x75630073, 0x6e657272, 0x70732d74, 0x00646565, 0x65746e69, 0x70757272, 0x72007374, 0x732d6765, 0x74666968, 0x67657200, 0x2d6f692d, 0x74646977, 0x00000068, 0x00000000 };
// See LICENSE for license details. #include "cachesim.h" #include "common.h" #include <cstdlib> #include <iostream> #include <iomanip> cache_sim_t::cache_sim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name) : sets(_sets), ways(_ways), linesz(_linesz), name(_name), log(false) { init(); } static void help() { std::cerr << "Cache configurations must be of the form" << std::endl; std::cerr << " sets:ways:blocksize" << std::endl; std::cerr << "where sets, ways, and blocksize are positive integers, with" << std::endl; std::cerr << "sets and blocksize both powers of two and blocksize at least 8." << std::endl; exit(1); } cache_sim_t* cache_sim_t::construct(const char* config, const char* name) { const char* wp = strchr(config, ':'); if (!wp++) help(); const char* bp = strchr(wp, ':'); if (!bp++) help(); size_t sets = atoi(std::string(config, wp).c_str()); size_t ways = atoi(std::string(wp, bp).c_str()); size_t linesz = atoi(bp); if (ways > 4 /* empirical / && sets == 1) return new fa_cache_sim_t(ways, linesz, name); return new cache_sim_t(sets, ways, linesz, name); } void cache_sim_t::init() { if(sets == 0 \|\| (sets & (sets-1))) help(); if(linesz < 8 \|\| (linesz & (linesz-1))) help(); idx_shift = 0; for (size_t x = linesz; x>1; x >>= 1) idx_shift++; tags = new uint64_t[setsways](); read_accesses = 0; read_misses = 0; bytes_read = 0; write_accesses = 0; write_misses = 0; bytes_written = 0; writebacks = 0; miss_handler = NULL; } cache_sim_t::cache_sim_t(const cache_sim_t& rhs) : sets(rhs.sets), ways(rhs.ways), linesz(rhs.linesz), idx_shift(rhs.idx_shift), name(rhs.name), log(false) { tags = new uint64_t[setsways]; memcpy(tags, rhs.tags, setswayssizeof(uint64_t)); } cache_sim_t::~cache_sim_t() { print_stats(); delete [] tags; } void cache_sim_t::print_stats() { if(read_accesses + write_accesses == 0) return; float mr = 100.0f(read_misses+write_misses)/(read_accesses+write_accesses); std::cout << std::setprecision(3) << std::fixed; std::cout << name << " "; std::cout << "Bytes Read: " << bytes_read << std::endl; std::cout << name << " "; std::cout << "Bytes Written: " << bytes_written << std::endl; std::cout << name << " "; std::cout << "Read Accesses: " << read_accesses << std::endl; std::cout << name << " "; std::cout << "Write Accesses: " << write_accesses << std::endl; std::cout << name << " "; std::cout << "Read Misses: " << read_misses << std::endl; std::cout << name << " "; std::cout << "Write Misses: " << write_misses << std::endl; std::cout << name << " "; std::cout << "Writebacks: " << writebacks << std::endl; std::cout << name << " "; std::cout << "Miss Rate: " << mr << '%' << std::endl; } uint64_t* cache_sim_t::check_tag(uint64_t addr) { size_t idx = (addr >> idx_shift) & (sets-1); size_t tag = (addr >> idx_shift) \| VALID; for (size_t i = 0; i < ways; i++) if (tag == (tags[idxways + i] & ~DIRTY)) return &tags[idxways + i]; return NULL; } uint64_t cache_sim_t::victimize(uint64_t addr) { size_t idx = (addr >> idx_shift) & (sets-1); size_t way = lfsr.next() % ways; uint64_t victim = tags[idxways + way]; tags[idxways + way] = (addr >> idx_shift) \| VALID; return victim; } void cache_sim_t::access(uint64_t addr, size_t bytes, bool store) { store ? write_accesses++ : read_accesses++; (store ? bytes_written : bytes_read) += bytes; uint64_t* hit_way = check_tag(addr); if (likely(hit_way != NULL)) { if (store) hit_way \|= DIRTY; return; } store ? write_misses++ : read_misses++; if (log) { std::cerr << name << " " << (store ? "write" : "read") << " miss 0x" << std::hex << addr << std::endl; } uint64_t victim = victimize(addr); if ((victim & (VALID \| DIRTY)) == (VALID \| DIRTY)) { uint64_t dirty_addr = (victim & ~(VALID \| DIRTY)) << idx_shift; if (miss_handler) miss_handler->access(dirty_addr, linesz, true); writebacks++; } if (miss_handler) miss_handler->access(addr & ~(linesz-1), linesz, false); if (store) check_tag(addr) \|= DIRTY; } fa_cache_sim_t::fa_cache_sim_t(size_t ways, size_t linesz, const char* name) : cache_sim_t(1, ways, linesz, name) { } uint64_t* fa_cache_sim_t::check_tag(uint64_t addr) { auto it = tags.find(addr >> idx_shift); return it == tags.end() ? NULL : &it->second; } uint64_t fa_cache_sim_t::victimize(uint64_t addr) { uint64_t old_tag = 0; if (tags.size() == ways) { auto it = tags.begin(); std::advance(it, lfsr.next() % ways); old_tag = it->second; tags.erase(it); } tags[addr >> idx_shift] = (addr >> idx_shift) \| VALID; return old_tag; }
// See LICENSE for license details. #ifndef _RISCV_CACHE_SIM_H #define _RISCV_CACHE_SIM_H #include "memtracer.h" #include <cstring> #include <string> #include <map> #include <cstdint> class lfsr_t { public: lfsr_t() : reg(1) {} lfsr_t(const lfsr_t& lfsr) : reg(lfsr.reg) {} uint32_t next() { return reg = (reg>>1)^(-(reg&1) & 0xd0000001); } private: uint32_t reg; }; class cache_sim_t { public: cache_sim_t(size_t sets, size_t ways, size_t linesz, const char* name); cache_sim_t(const cache_sim_t& rhs); virtual ~cache_sim_t(); void access(uint64_t addr, size_t bytes, bool store); void print_stats(); void set_miss_handler(cache_sim_t* mh) { miss_handler = mh; } void set_log(bool _log) { log = _log; } static cache_sim_t* construct(const char* config, const char* name); protected: static const uint64_t VALID = 1ULL << 63; static const uint64_t DIRTY = 1ULL << 62; virtual uint64_t* check_tag(uint64_t addr); virtual uint64_t victimize(uint64_t addr); lfsr_t lfsr; cache_sim_t* miss_handler; size_t sets; size_t ways; size_t linesz; size_t idx_shift; uint64_t* tags; uint64_t read_accesses; uint64_t read_misses; uint64_t bytes_read; uint64_t write_accesses; uint64_t write_misses; uint64_t bytes_written; uint64_t writebacks; std::string name; bool log; void init(); }; class fa_cache_sim_t : public cache_sim_t { public: fa_cache_sim_t(size_t ways, size_t linesz, const char* name); uint64_t* check_tag(uint64_t addr); uint64_t victimize(uint64_t addr); private: static bool cmp(uint64_t a, uint64_t b); std::map<uint64_t, uint64_t> tags; }; class cache_memtracer_t : public memtracer_t { public: cache_memtracer_t(const char* config, const char* name) { cache = cache_sim_t::construct(config, name); } ~cache_memtracer_t() { delete cache; } void set_miss_handler(cache_sim_t* mh) { cache->set_miss_handler(mh); } void set_log(bool log) { cache->set_log(log); } protected: cache_sim_t* cache; }; class icache_sim_t : public cache_memtracer_t { public: icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {} bool interested_in_range(uint64_t begin, uint64_t end, access_type type) { return type == FETCH; } void trace(uint64_t addr, size_t bytes, access_type type) { if (type == FETCH) cache->access(addr, bytes, false); } }; class dcache_sim_t : public cache_memtracer_t { public: dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {} bool interested_in_range(uint64_t begin, uint64_t end, access_type type) { return type == LOAD \|\| type == STORE; } void trace(uint64_t addr, size_t bytes, access_type type) { if (type == LOAD \|\| type == STORE) cache->access(addr, bytes, type == STORE); } }; #endif
#include "devices.h" #include "processor.h" clint_t::clint_t(std::vector<processor_t>& procs) : procs(procs), mtimecmp(procs.size()) { } / 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi / #define MSIP_BASE 0x0 #define MTIMECMP_BASE 0x4000 #define MTIME_BASE 0xbff8 void clint_t::reset() { mtime = 0; } bool clint_t::load(reg_t addr, size_t len, uint8_t bytes) { if (addr >= MSIP_BASE && addr + len <= MSIP_BASE + procs.size()sizeof(msip_t)) { std::vector<msip_t> msip(procs.size()); for (size_t i = 0; i < procs.size(); ++i) msip[i] = !!(procs[i]->state.mip & MIP_MSIP); memcpy(bytes, (uint8_t)&msip[0] + addr - MSIP_BASE, len); } else if (addr >= MTIMECMP_BASE && addr + len <= MTIMECMP_BASE + procs.size()sizeof(mtimecmp_t)) { memcpy(bytes, (uint8_t)&mtimecmp[0] + addr - MTIMECMP_BASE, len); } else if (addr >= MTIME_BASE && addr + len <= MTIME_BASE + sizeof(mtime_t)) { memcpy(bytes, (uint8_t)&mtime + addr - MTIME_BASE, len); } else { return false; } return true; } bool clint_t::store(reg_t addr, size_t len, const uint8_t bytes) { if (addr >= MSIP_BASE && addr + len <= MSIP_BASE + procs.size()sizeof(msip_t)) { std::vector<msip_t> msip(procs.size()); std::vector<msip_t> mask(procs.size(), 0); memcpy((uint8_t)&msip[0] + addr - MSIP_BASE, bytes, len); memset((uint8_t)&mask[0] + addr - MSIP_BASE, 0xff, len); for (size_t i = 0; i < procs.size(); ++i) { if (!(mask[i] & 0xFF)) continue; procs[i]->state.mip &= ~MIP_MSIP; if (!!(msip[i] & 1)) procs[i]->state.mip \|= MIP_MSIP; } } else if (addr >= MTIMECMP_BASE && addr + len <= MTIMECMP_BASE + procs.size()sizeof(mtimecmp_t)) { memcpy((uint8_t)&mtimecmp[0] + addr - MTIMECMP_BASE, bytes, len); } else if (addr >= MTIME_BASE && addr + len <= MTIME_BASE + sizeof(mtime_t)) { memcpy((uint8_t)&mtime + addr - MTIME_BASE, bytes, len); } else { return false; } increment(0); return true; } void clint_t::increment(reg_t inc) { mtime += inc; for (size_t i = 0; i < procs.size(); i++) { procs[i]->state.mip &= ~MIP_MTIP; if (mtime >= mtimecmp[i]) procs[i]->state.mip \|= MIP_MTIP; } }
// See LICENSE for license details. #ifndef _RISCV_COMMON_H #define _RISCV_COMMON_H #define likely(x) __builtin_expect(x, 1) #define unlikely(x) __builtin_expect(x, 0) #endif
#define DTM_IDCODE 0x01 /* * Identifies the release version of this part. / #define DTM_IDCODE_VERSION_OFFSET 28 #define DTM_IDCODE_VERSION_LENGTH 4 #define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET) / * Identifies the designer's part number of this part. / #define DTM_IDCODE_PARTNUMBER_OFFSET 12 #define DTM_IDCODE_PARTNUMBER_LENGTH 16 #define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET) / * Identifies the designer/manufacturer of this part. Bits 6:0 must be * bits 6:0 of the designer/manufacturer's Identification Code as * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 * count of the number of continuation characters (0x7f) in that same * Identification Code. / #define DTM_IDCODE_MANUFID_OFFSET 1 #define DTM_IDCODE_MANUFID_LENGTH 11 #define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET) #define DTM_IDCODE_1_OFFSET 0 #define DTM_IDCODE_1_LENGTH 1 #define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET) #define DTM_DTMCS 0x10 / * Writing 1 to this bit does a hard reset of the DTM, * causing the DTM to forget about any outstanding DMI transactions. * In general this should only be used when the Debugger has * reason to expect that the outstanding DMI transaction will never * complete (e.g. a reset condition caused an inflight DMI transaction to * be cancelled). / #define DTM_DTMCS_DMIHARDRESET_OFFSET 17 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1 #define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET) / * Writing 1 to this bit clears the sticky error state * and allows the DTM to retry or complete the previous * transaction. / #define DTM_DTMCS_DMIRESET_OFFSET 16 #define DTM_DTMCS_DMIRESET_LENGTH 1 #define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET) / * This is a hint to the debugger of the minimum number of * cycles a debugger should spend in * Run-Test/Idle after every DMI scan to avoid a `busy' * return code (\Fdmistat of 3). A debugger must still * check \Fdmistat when necessary. * * 0: It is not necessary to enter Run-Test/Idle at all. * * 1: Enter Run-Test/Idle and leave it immediately. * * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. * * And so on. / #define DTM_DTMCS_IDLE_OFFSET 12 #define DTM_DTMCS_IDLE_LENGTH 3 #define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET) / * 0: No error. * * 1: Reserved. Interpret the same as 2. * * 2: An operation failed (resulted in \Fop of 2). * * 3: An operation was attempted while a DMI access was still in * progress (resulted in \Fop of 3). / #define DTM_DTMCS_DMISTAT_OFFSET 10 #define DTM_DTMCS_DMISTAT_LENGTH 2 #define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET) / * The size of \Faddress in \Rdmi. / #define DTM_DTMCS_ABITS_OFFSET 4 #define DTM_DTMCS_ABITS_LENGTH 6 #define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET) / * 0: Version described in spec version 0.11. * * 1: Version described in spec version 0.13 (and later?), which * reduces the DMI data width to 32 bits. * * 15: Version not described in any available version of this spec. / #define DTM_DTMCS_VERSION_OFFSET 0 #define DTM_DTMCS_VERSION_LENGTH 4 #define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET) #define DTM_DMI 0x11 / * Address used for DMI access. In Update-DR this value is used * to access the DM over the DMI. / #define DTM_DMI_ADDRESS_OFFSET 34 #define DTM_DMI_ADDRESS_LENGTH abits #define DTM_DMI_ADDRESS (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET) / * The data to send to the DM over the DMI during Update-DR, and * the data returned from the DM as a result of the previous operation. / #define DTM_DMI_DATA_OFFSET 2 #define DTM_DMI_DATA_LENGTH 32 #define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET) / * When the debugger writes this field, it has the following meaning: * * 0: Ignore \Fdata and \Faddress. (nop) * * Don't send anything over the DMI during Update-DR. * This operation should never result in a busy or error response. * The address and data reported in the following Capture-DR * are undefined. * * 1: Read from \Faddress. (read) * * 2: Write \Fdata to \Faddress. (write) * * 3: Reserved. * * When the debugger reads this field, it means the following: * * 0: The previous operation completed successfully. * * 1: Reserved. * * 2: A previous operation failed. The data scanned into \Rdmi in * this access will be ignored. This status is sticky and can be * cleared by writing \Fdmireset in \Rdtmcs. * * This indicates that the DM itself responded with an error. * Note: there are no specified cases in which the DM would * respond with an error, and DMI is not required to support * returning errors. * * 3: An operation was attempted while a DMI request is still in * progress. The data scanned into \Rdmi in this access will be * ignored. This status is sticky and can be cleared by writing * \Fdmireset in \Rdtmcs. If a debugger sees this status, it * needs to give the target more TCK edges between Update-DR and * Capture-DR. The simplest way to do that is to add extra transitions * in Run-Test/Idle. * * (The DTM, DM, and/or component may be in different clock domains, * so synchronization may be required. Some relatively fixed number of * TCK ticks may be needed for the request to reach the DM, complete, * and for the response to be synchronized back into the TCK domain.) / #define DTM_DMI_OP_OFFSET 0 #define DTM_DMI_OP_LENGTH 2 #define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET) #define CSR_DCSR 0x7b0 / * 0: There is no external debug support. * * 4: External debug support exists as it is described in this document. * * 15: There is external debug support, but it does not conform to any * available version of this spec. / #define CSR_DCSR_XDEBUGVER_OFFSET 28 #define CSR_DCSR_XDEBUGVER_LENGTH 4 #define CSR_DCSR_XDEBUGVER (0xfU << CSR_DCSR_XDEBUGVER_OFFSET) / * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode. / #define CSR_DCSR_EBREAKM_OFFSET 15 #define CSR_DCSR_EBREAKM_LENGTH 1 #define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET) / * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode. / #define CSR_DCSR_EBREAKS_OFFSET 13 #define CSR_DCSR_EBREAKS_LENGTH 1 #define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET) / * When 1, {\tt ebreak} instructions in User/Application Mode enter * Debug Mode. / #define CSR_DCSR_EBREAKU_OFFSET 12 #define CSR_DCSR_EBREAKU_LENGTH 1 #define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET) / * 0: Interrupts are disabled during single stepping. * * 1: Interrupts are enabled during single stepping. * * Implementations may hard wire this bit to 0. * The debugger must read back the value it * writes to check whether the feature is supported. If not * supported, interrupt behavior can be emulated by the debugger. / #define CSR_DCSR_STEPIE_OFFSET 11 #define CSR_DCSR_STEPIE_LENGTH 1 #define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET) / * 0: Increment counters as usual. * * 1: Don't increment any counters while in Debug Mode or on {\tt * ebreak} instructions that cause entry into Debug Mode. These * counters include the {\tt cycle} and {\tt instret} CSRs. This is * preferred for most debugging scenarios. * * An implementation may choose not to support writing to this bit. * The debugger must read back the value it writes to check whether * the feature is supported. / #define CSR_DCSR_STOPCOUNT_OFFSET 10 #define CSR_DCSR_STOPCOUNT_LENGTH 1 #define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET) / * 0: Increment timers as usual. * * 1: Don't increment any hart-local timers while in Debug Mode. * * An implementation may choose not to support writing to this bit. * The debugger must read back the value it writes to check whether * the feature is supported. / #define CSR_DCSR_STOPTIME_OFFSET 9 #define CSR_DCSR_STOPTIME_LENGTH 1 #define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET) / * Explains why Debug Mode was entered. * * When there are multiple reasons to enter Debug Mode in a single * cycle, hardware should set \Fcause to the cause with the highest * priority. * * 1: An {\tt ebreak} instruction was executed. (priority 3) * * 2: The Trigger Module caused a breakpoint exception. (priority 4) * * 3: The debugger requested entry to Debug Mode. (priority 2) * * 4: The hart single stepped because \Fstep was set. (priority 1) * * Other values are reserved for future use. / #define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_LENGTH 3 #define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET) / * When 1, \Fmprv in \Rmstatus takes effect during debug mode. * When 0, it is ignored during debug mode. * Implementing this bit is optional. * If not implemented it should be tied to 0. / #define CSR_DCSR_MPRVEN_OFFSET 4 #define CSR_DCSR_MPRVEN_LENGTH 1 #define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET) / * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. * * Since an NMI can indicate a hardware error condition, * reliable debugging may no longer be possible once this bit becomes set. * This is implementation-dependent. / #define CSR_DCSR_NMIP_OFFSET 3 #define CSR_DCSR_NMIP_LENGTH 1 #define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET) / * When set and not in Debug Mode, the hart will only execute a single * instruction and then enter Debug Mode. * If the instruction does not complete due to an exception, * the hart will immediately enter Debug Mode before executing * the trap handler, with appropriate exception registers set. / #define CSR_DCSR_STEP_OFFSET 2 #define CSR_DCSR_STEP_LENGTH 1 #define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET) / * Contains the privilege level the hart was operating in when Debug * Mode was entered. The encoding is described in Table * \ref{tab:privlevel}. A debugger can change this value to change * the hart's privilege level when exiting Debug Mode. * * Not all privilege levels are supported on all harts. If the * encoding written is not supported or the debugger is not allowed to * change to it, the hart may change to any supported privilege level. / #define CSR_DCSR_PRV_OFFSET 0 #define CSR_DCSR_PRV_LENGTH 2 #define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET) #define CSR_DPC 0x7b1 #define CSR_DPC_DPC_OFFSET 0 #define CSR_DPC_DPC_LENGTH MXLEN #define CSR_DPC_DPC (((1L<<MXLEN)-1) << CSR_DPC_DPC_OFFSET) #define CSR_DSCRATCH0 0x7b2 #define CSR_DSCRATCH1 0x7b3 #define CSR_TSELECT 0x7a0 #define CSR_TSELECT_INDEX_OFFSET 0 #define CSR_TSELECT_INDEX_LENGTH MXLEN #define CSR_TSELECT_INDEX (((1L<<MXLEN)-1) << CSR_TSELECT_INDEX_OFFSET) #define CSR_TDATA1 0x7a1 / * 0: There is no trigger at this \Rtselect. * * 1: The trigger is a legacy SiFive address match trigger. These * should not be implemented and aren't further documented here. * * 2: The trigger is an address/data match trigger. The remaining bits * in this register act as described in \Rmcontrol. * * 3: The trigger is an instruction count trigger. The remaining bits * in this register act as described in \Ricount. * * 4: The trigger is an interrupt trigger. The remaining bits * in this register act as described in \Ritrigger. * * 5: The trigger is an exception trigger. The remaining bits * in this register act as described in \Retrigger. * * 15: This trigger exists (so enumeration shouldn't terminate), but * is not currently available. * * Other values are reserved for future use. * * When this field is written to an unsupported value, it takes on its * reset value instead. The reset value is any one of the types * supported by the trigger selected by \Rtselect. / #define CSR_TDATA1_TYPE_OFFSET (MXLEN-4) #define CSR_TDATA1_TYPE_LENGTH 4 #define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET) / * 0: Both Debug and M Mode can write the {\tt tdata} registers at the * selected \Rtselect. * * 1: Only Debug Mode can write the {\tt tdata} registers at the * selected \Rtselect. Writes from other modes are ignored. * * This bit is only writable from Debug Mode. / #define CSR_TDATA1_DMODE_OFFSET (MXLEN-5) #define CSR_TDATA1_DMODE_LENGTH 1 #define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET) / * Trigger-specific data. / #define CSR_TDATA1_DATA_OFFSET 0 #define CSR_TDATA1_DATA_LENGTH (MXLEN - 5) #define CSR_TDATA1_DATA (((1L<<MXLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET) #define CSR_TDATA2 0x7a2 #define CSR_TDATA2_DATA_OFFSET 0 #define CSR_TDATA2_DATA_LENGTH MXLEN #define CSR_TDATA2_DATA (((1L<<MXLEN)-1) << CSR_TDATA2_DATA_OFFSET) #define CSR_TDATA3 0x7a3 #define CSR_TDATA3_DATA_OFFSET 0 #define CSR_TDATA3_DATA_LENGTH MXLEN #define CSR_TDATA3_DATA (((1L<<MXLEN)-1) << CSR_TDATA3_DATA_OFFSET) #define CSR_TINFO 0x7a4 / * One bit for each possible \Ftype enumerated in \Rtdataone. Bit N * corresponds to type N. If the bit is set, then that type is * supported by the currently selected trigger. * * If the currently selected trigger doesn't exist, this field * contains 1. * * If \Ftype is not writable, this register may be unimplemented, in * which case reading it causes an illegal instruction exception. In * this case the debugger can read the only supported type from * \Rtdataone. / #define CSR_TINFO_INFO_OFFSET 0 #define CSR_TINFO_INFO_LENGTH 16 #define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET) #define CSR_MCONTROL 0x7a1 #define CSR_MCONTROL_TYPE_OFFSET (MXLEN-4) #define CSR_MCONTROL_TYPE_LENGTH 4 #define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET) #define CSR_MCONTROL_DMODE_OFFSET (MXLEN-5) #define CSR_MCONTROL_DMODE_LENGTH 1 #define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET) / * Specifies the largest naturally aligned powers-of-two (NAPOT) range * supported by the hardware when \Fmatch is 1. The value is the * logarithm base 2 of the * number of bytes in that range. A value of 0 indicates that only * exact value matches are supported (one byte range). A value of 63 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in * size. / #define CSR_MCONTROL_MASKMAX_OFFSET (MXLEN-11) #define CSR_MCONTROL_MASKMAX_LENGTH 6 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET) / * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. / #define CSR_MCONTROL_HIT_OFFSET 20 #define CSR_MCONTROL_HIT_LENGTH 1 #define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET) / * 0: Perform a match on the virtual address. * * 1: Perform a match on the data value loaded/stored, or the * instruction executed. / #define CSR_MCONTROL_SELECT_OFFSET 19 #define CSR_MCONTROL_SELECT_LENGTH 1 #define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET) / * 0: The action for this trigger will be taken just before the * instruction that triggered it is executed, but after all preceding * instructions are are committed. * * 1: The action for this trigger will be taken after the instruction * that triggered it is executed. It should be taken before the next * instruction is executed, but it is better to implement triggers and * not implement that suggestion than to not implement them at all. * * Most hardware will only implement one timing or the other, possibly * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit * primarily exists for the hardware to communicate to the debugger * what will happen. Hardware may implement the bit fully writable, in * which case the debugger has a little more control. * * Data load triggers with \Ftiming of 0 will result in the same load * happening again when the debugger lets the hart run. For data load * triggers, debuggers must first attempt to set the breakpoint with * \Ftiming of 1. * * A chain of triggers that don't all have the same \Ftiming value * will never fire (unless consecutive instructions match the * appropriate triggers). / #define CSR_MCONTROL_TIMING_OFFSET 18 #define CSR_MCONTROL_TIMING_LENGTH 1 #define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET) / * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. / #define CSR_MCONTROL_ACTION_OFFSET 12 #define CSR_MCONTROL_ACTION_LENGTH 6 #define CSR_MCONTROL_ACTION (0x3fULL << CSR_MCONTROL_ACTION_OFFSET) / * 0: When this trigger matches, the configured action is taken. * * 1: While this trigger does not match, it prevents the trigger with * the next index from matching. * * Because \Fchain affects the next trigger, hardware must zero it in * writes to \Rmcontrol that set \Fdmode to 0 if the next trigger has * \Fdmode of 1. * In addition hardware should ignore writes to \Rmcontrol that set * \Fdmode to 1 if the previous trigger has both \Fdmode of 0 and * \Fchain of 1. Debuggers must avoid the latter case by checking * \Fchain on the previous trigger if they're writing \Rmcontrol. * * Implementations that wish to limit the maximum length of a trigger * chain (eg. to meet timing requirements) may do so by zeroing * \Fchain in writes to \Rmcontrol that would make the chain too long. / #define CSR_MCONTROL_CHAIN_OFFSET 11 #define CSR_MCONTROL_CHAIN_LENGTH 1 #define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET) / * 0: Matches when the value equals \Rtdatatwo. * * 1: Matches when the top M bits of the value match the top M bits of * \Rtdatatwo. M is MXLEN-1 minus the index of the least-significant * bit containing 0 in \Rtdatatwo. * * 2: Matches when the value is greater than (unsigned) or equal to * \Rtdatatwo. * * 3: Matches when the value is less than (unsigned) \Rtdatatwo. * * 4: Matches when the lower half of the value equals the lower half * of \Rtdatatwo after the lower half of the value is ANDed with the * upper half of \Rtdatatwo. * * 5: Matches when the upper half of the value equals the lower half * of \Rtdatatwo after the upper half of the value is ANDed with the * upper half of \Rtdatatwo. * * Other values are reserved for future use. / #define CSR_MCONTROL_MATCH_OFFSET 7 #define CSR_MCONTROL_MATCH_LENGTH 4 #define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET) / * When set, enable this trigger in M mode. / #define CSR_MCONTROL_M_OFFSET 6 #define CSR_MCONTROL_M_LENGTH 1 #define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET) / * When set, enable this trigger in S mode. / #define CSR_MCONTROL_S_OFFSET 4 #define CSR_MCONTROL_S_LENGTH 1 #define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET) / * When set, enable this trigger in U mode. / #define CSR_MCONTROL_U_OFFSET 3 #define CSR_MCONTROL_U_LENGTH 1 #define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET) / * When set, the trigger fires on the virtual address or opcode of an * instruction that is executed. / #define CSR_MCONTROL_EXECUTE_OFFSET 2 #define CSR_MCONTROL_EXECUTE_LENGTH 1 #define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET) / * When set, the trigger fires on the virtual address or data of a store. / #define CSR_MCONTROL_STORE_OFFSET 1 #define CSR_MCONTROL_STORE_LENGTH 1 #define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET) / * When set, the trigger fires on the virtual address or data of a load. / #define CSR_MCONTROL_LOAD_OFFSET 0 #define CSR_MCONTROL_LOAD_LENGTH 1 #define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET) #define CSR_ICOUNT 0x7a1 #define CSR_ICOUNT_TYPE_OFFSET (MXLEN-4) #define CSR_ICOUNT_TYPE_LENGTH 4 #define CSR_ICOUNT_TYPE (0xfULL << CSR_ICOUNT_TYPE_OFFSET) #define CSR_ICOUNT_DMODE_OFFSET (MXLEN-5) #define CSR_ICOUNT_DMODE_LENGTH 1 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET) / * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. / #define CSR_ICOUNT_HIT_OFFSET 24 #define CSR_ICOUNT_HIT_LENGTH 1 #define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET) / * When count is decremented to 0, the trigger fires. Instead of * changing \Fcount from 1 to 0, it is also acceptable for hardware to * clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired * to 1 if this register just exists for single step. / #define CSR_ICOUNT_COUNT_OFFSET 10 #define CSR_ICOUNT_COUNT_LENGTH 14 #define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET) / * When set, every instruction completed or exception taken in M mode decrements \Fcount * by 1. / #define CSR_ICOUNT_M_OFFSET 9 #define CSR_ICOUNT_M_LENGTH 1 #define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET) / * When set, every instruction completed or exception taken in S mode decrements \Fcount * by 1. / #define CSR_ICOUNT_S_OFFSET 7 #define CSR_ICOUNT_S_LENGTH 1 #define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET) / * When set, every instruction completed or exception taken in U mode decrements \Fcount * by 1. / #define CSR_ICOUNT_U_OFFSET 6 #define CSR_ICOUNT_U_LENGTH 1 #define CSR_ICOUNT_U (0x1ULL << CSR_ICOUNT_U_OFFSET) / * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. / #define CSR_ICOUNT_ACTION_OFFSET 0 #define CSR_ICOUNT_ACTION_LENGTH 6 #define CSR_ICOUNT_ACTION (0x3fULL << CSR_ICOUNT_ACTION_OFFSET) #define CSR_ITRIGGER 0x7a1 #define CSR_ITRIGGER_TYPE_OFFSET (MXLEN-4) #define CSR_ITRIGGER_TYPE_LENGTH 4 #define CSR_ITRIGGER_TYPE (0xfULL << CSR_ITRIGGER_TYPE_OFFSET) #define CSR_ITRIGGER_DMODE_OFFSET (MXLEN-5) #define CSR_ITRIGGER_DMODE_LENGTH 1 #define CSR_ITRIGGER_DMODE (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET) / * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. / #define CSR_ITRIGGER_HIT_OFFSET (MXLEN-6) #define CSR_ITRIGGER_HIT_LENGTH 1 #define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET) / * When set, enable this trigger for interrupts that are taken from M * mode. / #define CSR_ITRIGGER_M_OFFSET 9 #define CSR_ITRIGGER_M_LENGTH 1 #define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET) / * When set, enable this trigger for interrupts that are taken from S * mode. / #define CSR_ITRIGGER_S_OFFSET 7 #define CSR_ITRIGGER_S_LENGTH 1 #define CSR_ITRIGGER_S (0x1ULL << CSR_ITRIGGER_S_OFFSET) / * When set, enable this trigger for interrupts that are taken from U * mode. / #define CSR_ITRIGGER_U_OFFSET 6 #define CSR_ITRIGGER_U_LENGTH 1 #define CSR_ITRIGGER_U (0x1ULL << CSR_ITRIGGER_U_OFFSET) / * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. / #define CSR_ITRIGGER_ACTION_OFFSET 0 #define CSR_ITRIGGER_ACTION_LENGTH 6 #define CSR_ITRIGGER_ACTION (0x3fULL << CSR_ITRIGGER_ACTION_OFFSET) #define CSR_ETRIGGER 0x7a1 #define CSR_ETRIGGER_TYPE_OFFSET (MXLEN-4) #define CSR_ETRIGGER_TYPE_LENGTH 4 #define CSR_ETRIGGER_TYPE (0xfULL << CSR_ETRIGGER_TYPE_OFFSET) #define CSR_ETRIGGER_DMODE_OFFSET (MXLEN-5) #define CSR_ETRIGGER_DMODE_LENGTH 1 #define CSR_ETRIGGER_DMODE (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET) / * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. / #define CSR_ETRIGGER_HIT_OFFSET (MXLEN-6) #define CSR_ETRIGGER_HIT_LENGTH 1 #define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET) / * When set, enable this trigger for exceptions that are taken from M * mode. / #define CSR_ETRIGGER_M_OFFSET 9 #define CSR_ETRIGGER_M_LENGTH 1 #define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET) / * When set, enable this trigger for exceptions that are taken from S * mode. / #define CSR_ETRIGGER_S_OFFSET 7 #define CSR_ETRIGGER_S_LENGTH 1 #define CSR_ETRIGGER_S (0x1ULL << CSR_ETRIGGER_S_OFFSET) / * When set, enable this trigger for exceptions that are taken from U * mode. / #define CSR_ETRIGGER_U_OFFSET 6 #define CSR_ETRIGGER_U_LENGTH 1 #define CSR_ETRIGGER_U (0x1ULL << CSR_ETRIGGER_U_OFFSET) / * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. / #define CSR_ETRIGGER_ACTION_OFFSET 0 #define CSR_ETRIGGER_ACTION_LENGTH 6 #define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET) #define DMI_DMSTATUS 0x11 / * If 1, then there is an implicit {\tt ebreak} instruction at the * non-existent word immediately after the Program Buffer. This saves * the debugger from having to write the {\tt ebreak} itself, and * allows the Program Buffer to be one word smaller. * * This must be 1 when \Fprogbufsize is 1. / #define DMI_DMSTATUS_IMPEBREAK_OFFSET 22 #define DMI_DMSTATUS_IMPEBREAK_LENGTH 1 #define DMI_DMSTATUS_IMPEBREAK (0x1U << DMI_DMSTATUS_IMPEBREAK_OFFSET) / * This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged. / #define DMI_DMSTATUS_ALLHAVERESET_OFFSET 19 #define DMI_DMSTATUS_ALLHAVERESET_LENGTH 1 #define DMI_DMSTATUS_ALLHAVERESET (0x1U << DMI_DMSTATUS_ALLHAVERESET_OFFSET) / * This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged. / #define DMI_DMSTATUS_ANYHAVERESET_OFFSET 18 #define DMI_DMSTATUS_ANYHAVERESET_LENGTH 1 #define DMI_DMSTATUS_ANYHAVERESET (0x1U << DMI_DMSTATUS_ANYHAVERESET_OFFSET) / * This field is 1 when all currently selected harts have acknowledged * the previous resume request. / #define DMI_DMSTATUS_ALLRESUMEACK_OFFSET 17 #define DMI_DMSTATUS_ALLRESUMEACK_LENGTH 1 #define DMI_DMSTATUS_ALLRESUMEACK (0x1U << DMI_DMSTATUS_ALLRESUMEACK_OFFSET) / * This field is 1 when any currently selected hart has acknowledged * the previous resume request. / #define DMI_DMSTATUS_ANYRESUMEACK_OFFSET 16 #define DMI_DMSTATUS_ANYRESUMEACK_LENGTH 1 #define DMI_DMSTATUS_ANYRESUMEACK (0x1U << DMI_DMSTATUS_ANYRESUMEACK_OFFSET) / * This field is 1 when all currently selected harts do not exist in this system. / #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET 15 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH 1 #define DMI_DMSTATUS_ALLNONEXISTENT (0x1U << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET) / * This field is 1 when any currently selected hart does not exist in this system. / #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET 14 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH 1 #define DMI_DMSTATUS_ANYNONEXISTENT (0x1U << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET) / * This field is 1 when all currently selected harts are unavailable. / #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET 13 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH 1 #define DMI_DMSTATUS_ALLUNAVAIL (0x1U << DMI_DMSTATUS_ALLUNAVAIL_OFFSET) / * This field is 1 when any currently selected hart is unavailable. / #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET 12 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH 1 #define DMI_DMSTATUS_ANYUNAVAIL (0x1U << DMI_DMSTATUS_ANYUNAVAIL_OFFSET) / * This field is 1 when all currently selected harts are running. / #define DMI_DMSTATUS_ALLRUNNING_OFFSET 11 #define DMI_DMSTATUS_ALLRUNNING_LENGTH 1 #define DMI_DMSTATUS_ALLRUNNING (0x1U << DMI_DMSTATUS_ALLRUNNING_OFFSET) / * This field is 1 when any currently selected hart is running. / #define DMI_DMSTATUS_ANYRUNNING_OFFSET 10 #define DMI_DMSTATUS_ANYRUNNING_LENGTH 1 #define DMI_DMSTATUS_ANYRUNNING (0x1U << DMI_DMSTATUS_ANYRUNNING_OFFSET) / * This field is 1 when all currently selected harts are halted. / #define DMI_DMSTATUS_ALLHALTED_OFFSET 9 #define DMI_DMSTATUS_ALLHALTED_LENGTH 1 #define DMI_DMSTATUS_ALLHALTED (0x1U << DMI_DMSTATUS_ALLHALTED_OFFSET) / * This field is 1 when any currently selected hart is halted. / #define DMI_DMSTATUS_ANYHALTED_OFFSET 8 #define DMI_DMSTATUS_ANYHALTED_LENGTH 1 #define DMI_DMSTATUS_ANYHALTED (0x1U << DMI_DMSTATUS_ANYHALTED_OFFSET) / * 0 when authentication is required before using the DM. 1 when the * authentication check has passed. On components that don't implement * authentication, this bit must be preset as 1. / #define DMI_DMSTATUS_AUTHENTICATED_OFFSET 7 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH 1 #define DMI_DMSTATUS_AUTHENTICATED (0x1U << DMI_DMSTATUS_AUTHENTICATED_OFFSET) / * 0: The authentication module is ready to process the next * read/write to \Rauthdata. * * 1: The authentication module is busy. Accessing \Rauthdata results * in unspecified behavior. * * \Fauthbusy only becomes set in immediate response to an access to * \Rauthdata. / #define DMI_DMSTATUS_AUTHBUSY_OFFSET 6 #define DMI_DMSTATUS_AUTHBUSY_LENGTH 1 #define DMI_DMSTATUS_AUTHBUSY (0x1U << DMI_DMSTATUS_AUTHBUSY_OFFSET) / * 1 if this Debug Module supports halt-on-reset functionality * controllable by the \Fsetresethaltreq and \Fclrresethaltreq bits. * 0 otherwise. / #define DMI_DMSTATUS_HASRESETHALTREQ_OFFSET 5 #define DMI_DMSTATUS_HASRESETHALTREQ_LENGTH 1 #define DMI_DMSTATUS_HASRESETHALTREQ (0x1U << DMI_DMSTATUS_HASRESETHALTREQ_OFFSET) / * 0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which * is not relevant to the Device Tree. * * 1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the * Device Tree. / #define DMI_DMSTATUS_DEVTREEVALID_OFFSET 4 #define DMI_DMSTATUS_DEVTREEVALID_LENGTH 1 #define DMI_DMSTATUS_DEVTREEVALID (0x1U << DMI_DMSTATUS_DEVTREEVALID_OFFSET) / * 0: There is no Debug Module present. * * 1: There is a Debug Module and it conforms to version 0.11 of this * specification. * * 2: There is a Debug Module and it conforms to version 0.13 of this * specification. * * 15: There is a Debug Module but it does not conform to any * available version of this spec. / #define DMI_DMSTATUS_VERSION_OFFSET 0 #define DMI_DMSTATUS_VERSION_LENGTH 4 #define DMI_DMSTATUS_VERSION (0xfU << DMI_DMSTATUS_VERSION_OFFSET) #define DMI_DMCONTROL 0x10 / * Writes the halt request bit for all currently selected harts. * When set to 1, each selected hart will halt if it is not currently * halted. * * Writing 1 or 0 has no effect on a hart which is already halted, but * the bit must be cleared to 0 before the hart is resumed. * * Writes apply to the new value of \Fhartsel and \Fhasel. / #define DMI_DMCONTROL_HALTREQ_OFFSET 31 #define DMI_DMCONTROL_HALTREQ_LENGTH 1 #define DMI_DMCONTROL_HALTREQ (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET) / * Writes the resume request bit for all currently selected harts. * When set to 1, each selected hart will resume if it is currently * halted. * * The resume request bit is ignored while the halt request bit is * set. * * Writes apply to the new value of \Fhartsel and \Fhasel. / #define DMI_DMCONTROL_RESUMEREQ_OFFSET 30 #define DMI_DMCONTROL_RESUMEREQ_LENGTH 1 #define DMI_DMCONTROL_RESUMEREQ (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET) / * This optional field writes the reset bit for all the currently * selected harts. To perform a reset the debugger writes 1, and then * writes 0 to deassert the reset signal. * * If this feature is not implemented, the bit always stays 0, so * after writing 1 the debugger can read the register back to see if * the feature is supported. * * Writes apply to the new value of \Fhartsel and \Fhasel. / #define DMI_DMCONTROL_HARTRESET_OFFSET 29 #define DMI_DMCONTROL_HARTRESET_LENGTH 1 #define DMI_DMCONTROL_HARTRESET (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET) / * Writing 1 to this bit clears the {\tt havereset} bits for * any selected harts. * * Writes apply to the new value of \Fhartsel and \Fhasel. / #define DMI_DMCONTROL_ACKHAVERESET_OFFSET 28 #define DMI_DMCONTROL_ACKHAVERESET_LENGTH 1 #define DMI_DMCONTROL_ACKHAVERESET (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET) / * Selects the definition of currently selected harts. * * 0: There is a single currently selected hart, that selected by \Fhartsel. * * 1: There may be multiple currently selected harts -- that selected by \Fhartsel, * plus those selected by the hart array mask register. * * An implementation which does not implement the hart array mask register * must tie this field to 0. A debugger which wishes to use the hart array * mask register feature should set this bit and read back to see if the functionality * is supported. / #define DMI_DMCONTROL_HASEL_OFFSET 26 #define DMI_DMCONTROL_HASEL_LENGTH 1 #define DMI_DMCONTROL_HASEL (0x1U << DMI_DMCONTROL_HASEL_OFFSET) / * The low 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. / #define DMI_DMCONTROL_HARTSELLO_OFFSET 16 #define DMI_DMCONTROL_HARTSELLO_LENGTH 10 #define DMI_DMCONTROL_HARTSELLO (0x3ffU << DMI_DMCONTROL_HARTSELLO_OFFSET) / * The high 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. / #define DMI_DMCONTROL_HARTSELHI_OFFSET 6 #define DMI_DMCONTROL_HARTSELHI_LENGTH 10 #define DMI_DMCONTROL_HARTSELHI (0x3ffU << DMI_DMCONTROL_HARTSELHI_OFFSET) / * This optional field writes the halt-on-reset request bit for all * currently selected harts. * When set to 1, each selected hart will halt upon the next deassertion * of its reset. The halt-on-reset request bit is not automatically * cleared. The debugger must write to \Fclrresethaltreq to clear it. * * Writes apply to the new value of \Fhartsel and \Fhasel. * * If \Fhasresethaltreq is 0, this field is not implemented. / #define DMI_DMCONTROL_SETRESETHALTREQ_OFFSET 3 #define DMI_DMCONTROL_SETRESETHALTREQ_LENGTH 1 #define DMI_DMCONTROL_SETRESETHALTREQ (0x1U << DMI_DMCONTROL_SETRESETHALTREQ_OFFSET) / * This optional field clears the halt-on-reset request bit for all * currently selected harts. * * Writes apply to the new value of \Fhartsel and \Fhasel. / #define DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 #define DMI_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 #define DMI_DMCONTROL_CLRRESETHALTREQ (0x1U << DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET) / * This bit controls the reset signal from the DM to the rest of the * system. The signal should reset every part of the system, including * every hart, except for the DM and any logic required to access the * DM. * To perform a system reset the debugger writes 1, * and then writes 0 * to deassert the reset. / #define DMI_DMCONTROL_NDMRESET_OFFSET 1 #define DMI_DMCONTROL_NDMRESET_LENGTH 1 #define DMI_DMCONTROL_NDMRESET (0x1U << DMI_DMCONTROL_NDMRESET_OFFSET) / * This bit serves as a reset signal for the Debug Module itself. * * 0: The module's state, including authentication mechanism, * takes its reset values (the \Fdmactive bit is the only bit which can * be written to something other than its reset value). * * 1: The module functions normally. * * No other mechanism should exist that may result in resetting the * Debug Module after power up, including the platform's system reset * or Debug Transport reset signals. * * A debugger may pulse this bit low to get the Debug Module into a * known state. * * Implementations may use this bit to aid debugging, for example by * preventing the Debug Module from being power gated while debugging * is active. / #define DMI_DMCONTROL_DMACTIVE_OFFSET 0 #define DMI_DMCONTROL_DMACTIVE_LENGTH 1 #define DMI_DMCONTROL_DMACTIVE (0x1U << DMI_DMCONTROL_DMACTIVE_OFFSET) #define DMI_HARTINFO 0x12 / * Number of {\tt dscratch} registers available for the debugger * to use during program buffer execution, starting from \Rdscratchzero. * The debugger can make no assumptions about the contents of these * registers between commands. / #define DMI_HARTINFO_NSCRATCH_OFFSET 20 #define DMI_HARTINFO_NSCRATCH_LENGTH 4 #define DMI_HARTINFO_NSCRATCH (0xfU << DMI_HARTINFO_NSCRATCH_OFFSET) / * 0: The {\tt data} registers are shadowed in the hart by CSR * registers. Each CSR register is MXLEN bits in size, and corresponds * to a single argument, per Table~\ref{tab:datareg}. * * 1: The {\tt data} registers are shadowed in the hart's memory map. * Each register takes up 4 bytes in the memory map. / #define DMI_HARTINFO_DATAACCESS_OFFSET 16 #define DMI_HARTINFO_DATAACCESS_LENGTH 1 #define DMI_HARTINFO_DATAACCESS (0x1U << DMI_HARTINFO_DATAACCESS_OFFSET) / * If \Fdataaccess is 0: Number of CSR registers dedicated to * shadowing the {\tt data} registers. * * If \Fdataaccess is 1: Number of 32-bit words in the memory map * dedicated to shadowing the {\tt data} registers. * * Since there are at most 12 {\tt data} registers, the value in this * register must be 12 or smaller. / #define DMI_HARTINFO_DATASIZE_OFFSET 12 #define DMI_HARTINFO_DATASIZE_LENGTH 4 #define DMI_HARTINFO_DATASIZE (0xfU << DMI_HARTINFO_DATASIZE_OFFSET) / * If \Fdataaccess is 0: The number of the first CSR dedicated to * shadowing the {\tt data} registers. * * If \Fdataaccess is 1: Signed address of RAM where the {\tt data} * registers are shadowed, to be used to access relative to \Rzero. / #define DMI_HARTINFO_DATAADDR_OFFSET 0 #define DMI_HARTINFO_DATAADDR_LENGTH 12 #define DMI_HARTINFO_DATAADDR (0xfffU << DMI_HARTINFO_DATAADDR_OFFSET) #define DMI_HAWINDOWSEL 0x14 / * The high bits of this field may be tied to 0, depending on how large * the array mask register is. Eg. on a system with 48 harts only bit 0 * of this field may actually be writable. / #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15 #define DMI_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET) #define DMI_HAWINDOW 0x15 #define DMI_HAWINDOW_MASKDATA_OFFSET 0 #define DMI_HAWINDOW_MASKDATA_LENGTH 32 #define DMI_HAWINDOW_MASKDATA (0xffffffffU << DMI_HAWINDOW_MASKDATA_OFFSET) #define DMI_ABSTRACTCS 0x16 / * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. / #define DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET 24 #define DMI_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 #define DMI_ABSTRACTCS_PROGBUFSIZE (0x1fU << DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET) / * 1: An abstract command is currently being executed. * * This bit is set as soon as \Rcommand is written, and is * not cleared until that command has completed. / #define DMI_ABSTRACTCS_BUSY_OFFSET 12 #define DMI_ABSTRACTCS_BUSY_LENGTH 1 #define DMI_ABSTRACTCS_BUSY (0x1U << DMI_ABSTRACTCS_BUSY_OFFSET) / * Gets set if an abstract command fails. The bits in this field remain set until * they are cleared by writing 1 to them. No abstract command is * started until the value is reset to 0. * * 0 (none): No error. * * 1 (busy): An abstract command was executing while \Rcommand, * \Rabstractcs, \Rabstractauto was written, or when one * of the {\tt data} or {\tt progbuf} registers was read or written. * * 2 (not supported): The requested command is not supported, * regardless of whether the hart is running or not. * * 3 (exception): An exception occurred while executing the command * (eg. while executing the Program Buffer). * * 4 (halt/resume): The abstract command couldn't execute because the * hart wasn't in the required state (running/halted). * * 7 (other): The command failed for another reason. / #define DMI_ABSTRACTCS_CMDERR_OFFSET 8 #define DMI_ABSTRACTCS_CMDERR_LENGTH 3 #define DMI_ABSTRACTCS_CMDERR (0x7U << DMI_ABSTRACTCS_CMDERR_OFFSET) / * Number of {\tt data} registers that are implemented as part of the * abstract command interface. Valid sizes are 0 - 12. / #define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4 #define DMI_ABSTRACTCS_DATACOUNT (0xfU << DMI_ABSTRACTCS_DATACOUNT_OFFSET) #define DMI_COMMAND 0x17 / * The type determines the overall functionality of this * abstract command. / #define DMI_COMMAND_CMDTYPE_OFFSET 24 #define DMI_COMMAND_CMDTYPE_LENGTH 8 #define DMI_COMMAND_CMDTYPE (0xffU << DMI_COMMAND_CMDTYPE_OFFSET) / * This field is interpreted in a command-specific manner, * described for each abstract command. / #define DMI_COMMAND_CONTROL_OFFSET 0 #define DMI_COMMAND_CONTROL_LENGTH 24 #define DMI_COMMAND_CONTROL (0xffffffU << DMI_COMMAND_CONTROL_OFFSET) #define DMI_ABSTRACTAUTO 0x18 / * When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word * cause the command in \Rcommand to be executed again. / #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) / * When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word * cause the command in \Rcommand to be executed again. / #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12 #define DMI_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) #define DMI_DEVTREEADDR0 0x19 #define DMI_DEVTREEADDR0_ADDR_OFFSET 0 #define DMI_DEVTREEADDR0_ADDR_LENGTH 32 #define DMI_DEVTREEADDR0_ADDR (0xffffffffU << DMI_DEVTREEADDR0_ADDR_OFFSET) #define DMI_DEVTREEADDR1 0x1a #define DMI_DEVTREEADDR2 0x1b #define DMI_DEVTREEADDR3 0x1c #define DMI_NEXTDM 0x1d #define DMI_NEXTDM_ADDR_OFFSET 0 #define DMI_NEXTDM_ADDR_LENGTH 32 #define DMI_NEXTDM_ADDR (0xffffffffU << DMI_NEXTDM_ADDR_OFFSET) #define DMI_DATA0 0x04 #define DMI_DATA0_DATA_OFFSET 0 #define DMI_DATA0_DATA_LENGTH 32 #define DMI_DATA0_DATA (0xffffffffU << DMI_DATA0_DATA_OFFSET) #define DMI_DATA11 0x0f #define DMI_PROGBUF0 0x20 #define DMI_PROGBUF0_DATA_OFFSET 0 #define DMI_PROGBUF0_DATA_LENGTH 32 #define DMI_PROGBUF0_DATA (0xffffffffU << DMI_PROGBUF0_DATA_OFFSET) #define DMI_PROGBUF15 0x2f #define DMI_AUTHDATA 0x30 #define DMI_AUTHDATA_DATA_OFFSET 0 #define DMI_AUTHDATA_DATA_LENGTH 32 #define DMI_AUTHDATA_DATA (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET) #define DMI_HALTSUM0 0x40 #define DMI_HALTSUM0_HALTSUM0_OFFSET 0 #define DMI_HALTSUM0_HALTSUM0_LENGTH 32 #define DMI_HALTSUM0_HALTSUM0 (0xffffffffU << DMI_HALTSUM0_HALTSUM0_OFFSET) #define DMI_HALTSUM1 0x13 #define DMI_HALTSUM1_HALTSUM1_OFFSET 0 #define DMI_HALTSUM1_HALTSUM1_LENGTH 32 #define DMI_HALTSUM1_HALTSUM1 (0xffffffffU << DMI_HALTSUM1_HALTSUM1_OFFSET) #define DMI_HALTSUM2 0x34 #define DMI_HALTSUM2_HALTSUM2_OFFSET 0 #define DMI_HALTSUM2_HALTSUM2_LENGTH 32 #define DMI_HALTSUM2_HALTSUM2 (0xffffffffU << DMI_HALTSUM2_HALTSUM2_OFFSET) #define DMI_HALTSUM3 0x35 #define DMI_HALTSUM3_HALTSUM3_OFFSET 0 #define DMI_HALTSUM3_HALTSUM3_LENGTH 32 #define DMI_HALTSUM3_HALTSUM3 (0xffffffffU << DMI_HALTSUM3_HALTSUM3_OFFSET) #define DMI_SBADDRESS3 0x37 / * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). / #define DMI_SBADDRESS3_ADDRESS_OFFSET 0 #define DMI_SBADDRESS3_ADDRESS_LENGTH 32 #define DMI_SBADDRESS3_ADDRESS (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET) #define DMI_SBCS 0x38 / * 0: The System Bus interface conforms to mainline drafts of this * spec older than 1 January, 2018. * * 1: The System Bus interface conforms to this version of the spec. * * Other values are reserved for future versions. / #define DMI_SBCS_SBVERSION_OFFSET 29 #define DMI_SBCS_SBVERSION_LENGTH 3 #define DMI_SBCS_SBVERSION (0x7U << DMI_SBCS_SBVERSION_OFFSET) / * Set when the debugger attempts to read data while a read is in * progress, or when the debugger initiates a new access while one is * already in progress (while \Fsbbusy is set). It remains set until * it's explicitly cleared by the debugger. * * While this field is non-zero, no more system bus accesses can be * initiated by the Debug Module. / #define DMI_SBCS_SBBUSYERROR_OFFSET 22 #define DMI_SBCS_SBBUSYERROR_LENGTH 1 #define DMI_SBCS_SBBUSYERROR (0x1U << DMI_SBCS_SBBUSYERROR_OFFSET) / * When 1, indicates the system bus master is busy. (Whether the * system bus itself is busy is related, but not the same thing.) This * bit goes high immediately when a read or write is requested for any * reason, and does not go low until the access is fully completed. * * Writes to \Rsbcs while \Fsbbusy is high result in undefined * behavior. A debugger must not write to \Rsbcs until it reads * \Fsbbusy as 0. / #define DMI_SBCS_SBBUSY_OFFSET 21 #define DMI_SBCS_SBBUSY_LENGTH 1 #define DMI_SBCS_SBBUSY (0x1U << DMI_SBCS_SBBUSY_OFFSET) / * When 1, every write to \Rsbaddresszero automatically triggers a * system bus read at the new address. / #define DMI_SBCS_SBREADONADDR_OFFSET 20 #define DMI_SBCS_SBREADONADDR_LENGTH 1 #define DMI_SBCS_SBREADONADDR (0x1U << DMI_SBCS_SBREADONADDR_OFFSET) / * Select the access size to use for system bus accesses. * * 0: 8-bit * * 1: 16-bit * * 2: 32-bit * * 3: 64-bit * * 4: 128-bit * * If \Fsbaccess has an unsupported value when the DM starts a bus * access, the access is not performed and \Fsberror is set to 3. / #define DMI_SBCS_SBACCESS_OFFSET 17 #define DMI_SBCS_SBACCESS_LENGTH 3 #define DMI_SBCS_SBACCESS (0x7U << DMI_SBCS_SBACCESS_OFFSET) / * When 1, {\tt sbaddress} is incremented by the access size (in * bytes) selected in \Fsbaccess after every system bus access. / #define DMI_SBCS_SBAUTOINCREMENT_OFFSET 16 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH 1 #define DMI_SBCS_SBAUTOINCREMENT (0x1U << DMI_SBCS_SBAUTOINCREMENT_OFFSET) / * When 1, every read from \Rsbdatazero automatically triggers a * system bus read at the (possibly auto-incremented) address. / #define DMI_SBCS_SBREADONDATA_OFFSET 15 #define DMI_SBCS_SBREADONDATA_LENGTH 1 #define DMI_SBCS_SBREADONDATA (0x1U << DMI_SBCS_SBREADONDATA_OFFSET) / * When the Debug Module's system bus * master causes a bus error, this field gets set. The bits in this * field remain set until they are cleared by writing 1 to them. * While this field is non-zero, no more system bus accesses can be * initiated by the Debug Module. * * An implementation may report "Other" (7) for any error condition. * * 0: There was no bus error. * * 1: There was a timeout. * * 2: A bad address was accessed. * * 3: There was an alignment error. * * 4: An access of unsupported size was requested. * * 7: Other. / #define DMI_SBCS_SBERROR_OFFSET 12 #define DMI_SBCS_SBERROR_LENGTH 3 #define DMI_SBCS_SBERROR (0x7U << DMI_SBCS_SBERROR_OFFSET) / * Width of system bus addresses in bits. (0 indicates there is no bus * access support.) / #define DMI_SBCS_SBASIZE_OFFSET 5 #define DMI_SBCS_SBASIZE_LENGTH 7 #define DMI_SBCS_SBASIZE (0x7fU << DMI_SBCS_SBASIZE_OFFSET) / * 1 when 128-bit system bus accesses are supported. / #define DMI_SBCS_SBACCESS128_OFFSET 4 #define DMI_SBCS_SBACCESS128_LENGTH 1 #define DMI_SBCS_SBACCESS128 (0x1U << DMI_SBCS_SBACCESS128_OFFSET) / * 1 when 64-bit system bus accesses are supported. / #define DMI_SBCS_SBACCESS64_OFFSET 3 #define DMI_SBCS_SBACCESS64_LENGTH 1 #define DMI_SBCS_SBACCESS64 (0x1U << DMI_SBCS_SBACCESS64_OFFSET) / * 1 when 32-bit system bus accesses are supported. / #define DMI_SBCS_SBACCESS32_OFFSET 2 #define DMI_SBCS_SBACCESS32_LENGTH 1 #define DMI_SBCS_SBACCESS32 (0x1U << DMI_SBCS_SBACCESS32_OFFSET) / * 1 when 16-bit system bus accesses are supported. / #define DMI_SBCS_SBACCESS16_OFFSET 1 #define DMI_SBCS_SBACCESS16_LENGTH 1 #define DMI_SBCS_SBACCESS16 (0x1U << DMI_SBCS_SBACCESS16_OFFSET) / * 1 when 8-bit system bus accesses are supported. / #define DMI_SBCS_SBACCESS8_OFFSET 0 #define DMI_SBCS_SBACCESS8_LENGTH 1 #define DMI_SBCS_SBACCESS8 (0x1U << DMI_SBCS_SBACCESS8_OFFSET) #define DMI_SBADDRESS0 0x39 / * Accesses bits 31:0 of the physical address in {\tt sbaddress}. / #define DMI_SBADDRESS0_ADDRESS_OFFSET 0 #define DMI_SBADDRESS0_ADDRESS_LENGTH 32 #define DMI_SBADDRESS0_ADDRESS (0xffffffffU << DMI_SBADDRESS0_ADDRESS_OFFSET) #define DMI_SBADDRESS1 0x3a / * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). / #define DMI_SBADDRESS1_ADDRESS_OFFSET 0 #define DMI_SBADDRESS1_ADDRESS_LENGTH 32 #define DMI_SBADDRESS1_ADDRESS (0xffffffffU << DMI_SBADDRESS1_ADDRESS_OFFSET) #define DMI_SBADDRESS2 0x3b / * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). / #define DMI_SBADDRESS2_ADDRESS_OFFSET 0 #define DMI_SBADDRESS2_ADDRESS_LENGTH 32 #define DMI_SBADDRESS2_ADDRESS (0xffffffffU << DMI_SBADDRESS2_ADDRESS_OFFSET) #define DMI_SBDATA0 0x3c / * Accesses bits 31:0 of {\tt sbdata}. / #define DMI_SBDATA0_DATA_OFFSET 0 #define DMI_SBDATA0_DATA_LENGTH 32 #define DMI_SBDATA0_DATA (0xffffffffU << DMI_SBDATA0_DATA_OFFSET) #define DMI_SBDATA1 0x3d / * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that * wide). / #define DMI_SBDATA1_DATA_OFFSET 0 #define DMI_SBDATA1_DATA_LENGTH 32 #define DMI_SBDATA1_DATA (0xffffffffU << DMI_SBDATA1_DATA_OFFSET) #define DMI_SBDATA2 0x3e / * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that * wide). / #define DMI_SBDATA2_DATA_OFFSET 0 #define DMI_SBDATA2_DATA_LENGTH 32 #define DMI_SBDATA2_DATA (0xffffffffU << DMI_SBDATA2_DATA_OFFSET) #define DMI_SBDATA3 0x3f / * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that * wide). / #define DMI_SBDATA3_DATA_OFFSET 0 #define DMI_SBDATA3_DATA_LENGTH 32 #define DMI_SBDATA3_DATA (0xffffffffU << DMI_SBDATA3_DATA_OFFSET) #define SHORTNAME 0x123 / * Description of what this field is used for. / #define SHORTNAME_FIELD_OFFSET 0 #define SHORTNAME_FIELD_LENGTH 8 #define SHORTNAME_FIELD (0xffU << SHORTNAME_FIELD_OFFSET) #define AC_ACCESS_REGISTER None / * This is 0 to indicate Access Register Command. / #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 #define AC_ACCESS_REGISTER_CMDTYPE (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET) / * 2: Access the lowest 32 bits of the register. * * 3: Access the lowest 64 bits of the register. * * 4: Access the lowest 128 bits of the register. * * If \Fsize specifies a size larger than the register's actual size, * then the access must fail. If a register is accessible, then reads of \Fsize * less than or equal to the register's actual size must be supported. * * This field controls the Argument Width as referenced in * Table~\ref{tab:datareg}. / #define AC_ACCESS_REGISTER_SIZE_OFFSET 20 #define AC_ACCESS_REGISTER_SIZE_LENGTH 3 #define AC_ACCESS_REGISTER_SIZE (0x7U << AC_ACCESS_REGISTER_SIZE_OFFSET) / * When 1, execute the program in the Program Buffer exactly once * after performing the transfer, if any. / #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 #define AC_ACCESS_REGISTER_POSTEXEC (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET) / * 0: Don't do the operation specified by \Fwrite. * * 1: Do the operation specified by \Fwrite. * * This bit can be used to just execute the Program Buffer without * having to worry about placing valid values into \Fsize or \Fregno. / #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 #define AC_ACCESS_REGISTER_TRANSFER (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET) / * When \Ftransfer is set: * 0: Copy data from the specified register into {\tt arg0} portion * of {\tt data}. * * 1: Copy data from {\tt arg0} portion of {\tt data} into the * specified register. / #define AC_ACCESS_REGISTER_WRITE_OFFSET 16 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1 #define AC_ACCESS_REGISTER_WRITE (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET) / * Number of the register to access, as described in * Table~\ref{tab:regno}. * \Rdpc may be used as an alias for PC if this command is * supported on a non-halted hart. / #define AC_ACCESS_REGISTER_REGNO_OFFSET 0 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16 #define AC_ACCESS_REGISTER_REGNO (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET) #define AC_QUICK_ACCESS None / * This is 1 to indicate Quick Access command. / #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 #define AC_QUICK_ACCESS_CMDTYPE (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET) #define VIRT_PRIV virtual / * Contains the privilege level the hart was operating in when Debug * Mode was entered. The encoding is described in Table * \ref{tab:privlevel}, and matches the privilege level encoding from * the RISC-V Privileged ISA Specification. A user can write this * value to change the hart's privilege level when exiting Debug Mode. */ #define VIRT_PRIV_PRV_OFFSET 0 #define VIRT_PRIV_PRV_LENGTH 2 #define VIRT_PRIV_PRV (0x3U << VIRT_PRIV_PRV_OFFSET)
#include <cassert> #include "debug_module.h" #include "debug_defines.h" #include "opcodes.h" #include "mmu.h" #include "sim.h" #include "debug_rom/debug_rom.h" #include "debug_rom_defines.h" #if 0 # define D(x) x #else # define D(x) #endif ///////////////////////// debug_module_t debug_module_t::debug_module_t(sim_t sim, unsigned progbufsize, unsigned max_bus_master_bits, bool require_authentication) : progbufsize(progbufsize), program_buffer_bytes(4 + 4progbufsize), max_bus_master_bits(max_bus_master_bits), require_authentication(require_authentication), debug_progbuf_start(debug_data_start - program_buffer_bytes), debug_abstract_start(debug_progbuf_start - debug_abstract_size4), custom_base(0), sim(sim) { D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start)); D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start)); D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start)); program_buffer = new uint8_t[program_buffer_bytes]; memset(halted, 0, sizeof(halted)); memset(debug_rom_flags, 0, sizeof(debug_rom_flags)); memset(resumeack, 0, sizeof(resumeack)); memset(havereset, 0, sizeof(havereset)); memset(program_buffer, 0, program_buffer_bytes); program_buffer[4progbufsize] = ebreak(); program_buffer[4progbufsize+1] = ebreak() >> 8; program_buffer[4progbufsize+2] = ebreak() >> 16; program_buffer[4progbufsize+3] = ebreak() >> 24; memset(dmdata, 0, sizeof(dmdata)); write32(debug_rom_whereto, 0, jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO)); memset(debug_abstract, 0, sizeof(debug_abstract)); reset(); } debug_module_t::~debug_module_t() { delete[] program_buffer; } void debug_module_t::reset() { for (unsigned i = 0; i < sim->nprocs(); i++) { processor_t proc = sim->get_core(i); if (proc) proc->halt_request = false; } dmcontrol = {0}; dmstatus = {0}; dmstatus.impebreak = true; dmstatus.authenticated = !require_authentication; dmstatus.version = 2; abstractcs = {0}; abstractcs.datacount = sizeof(dmdata) / 4; abstractcs.progbufsize = progbufsize; abstractauto = {0}; sbcs = {0}; if (max_bus_master_bits > 0) { sbcs.version = 1; sbcs.asize = sizeof(reg_t) * 8; } if (max_bus_master_bits >= 64) sbcs.access64 = true; if (max_bus_master_bits >= 32) sbcs.access32 = true; if (max_bus_master_bits >= 16) sbcs.access16 = true; if (max_bus_master_bits >= 8) sbcs.access8 = true; challenge = random(); } void debug_module_t::add_device(bus_t bus) { bus->add_device(DEBUG_START, this); } bool debug_module_t::load(reg_t addr, size_t len, uint8_t bytes) { addr = DEBUG_START + addr; if (addr >= DEBUG_ROM_ENTRY && (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) { memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len); return true; } if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) { memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len); return true; } if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) { memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len); return true; } if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) { memcpy(bytes, debug_abstract + addr - debug_abstract_start, len); return true; } if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { memcpy(bytes, dmdata + addr - debug_data_start, len); return true; } if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) { memcpy(bytes, program_buffer + addr - debug_progbuf_start, len); return true; } fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) { D( switch (len) { case 4: fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " "hartsel=0x%x\n", addr, (unsigned) len, (uint32_t ) bytes, dmcontrol.hartsel); break; default: fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); break; } ); uint8_t id_bytes[4]; uint32_t id = 0; if (len == 4) { memcpy(id_bytes, bytes, 4); id = read32(id_bytes, 0); } addr = DEBUG_START + addr; if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { memcpy(dmdata + addr - debug_data_start, bytes, len); return true; } if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) { memcpy(program_buffer + addr - debug_progbuf_start, bytes, len); return true; } if (addr == DEBUG_ROM_HALTED) { assert (len == 4); halted[id] = true; if (dmcontrol.hartsel == id) { if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){ if (dmcontrol.hartsel == id) { abstractcs.busy = false; } } } return true; } if (addr == DEBUG_ROM_GOING) { debug_rom_flags[dmcontrol.hartsel] &= ~(1 << DEBUG_ROM_FLAG_GO); return true; } if (addr == DEBUG_ROM_RESUMING) { assert (len == 4); halted[id] = false; resumeack[id] = true; debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME); return true; } if (addr == DEBUG_ROM_EXCEPTION) { if (abstractcs.cmderr == CMDERR_NONE) { abstractcs.cmderr = CMDERR_EXCEPTION; } return true; } fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } void debug_module_t::write32(uint8_t memory, unsigned int index, uint32_t value) { uint8_t base = memory + index * 4; base[0] = value & 0xff; base[1] = (value >> 8) & 0xff; base[2] = (value >> 16) & 0xff; base[3] = (value >> 24) & 0xff; } uint32_t debug_module_t::read32(uint8_t memory, unsigned int index) { uint8_t base = memory + index * 4; uint32_t value = ((uint32_t) base[0]) \| (((uint32_t) base[1]) << 8) \| (((uint32_t) base[2]) << 16) \| (((uint32_t) base[3]) << 24); return value; } processor_t debug_module_t::current_proc() const { processor_t proc = NULL; try { proc = sim->get_core(dmcontrol.hartsel); } catch (const std::out_of_range&) { } return proc; } unsigned debug_module_t::sb_access_bits() { return 8 << sbcs.sbaccess; } void debug_module_t::sb_autoincrement() { if (!sbcs.autoincrement \|\| !max_bus_master_bits) return; uint64_t value = sbaddress[0] + sb_access_bits() / 8; sbaddress[0] = value; uint32_t carry = value >> 32; value = sbaddress[1] + carry; sbaddress[1] = value; carry = value >> 32; value = sbaddress[2] + carry; sbaddress[2] = value; carry = value >> 32; sbaddress[3] += carry; } void debug_module_t::sb_read() { reg_t address = ((uint64_t) sbaddress[1] << 32) \| sbaddress[0]; try { if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { sbdata[0] = sim->debug_mmu->load_uint8(address); } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { sbdata[0] = sim->debug_mmu->load_uint16(address); } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { sbdata[0] = sim->debug_mmu->load_uint32(address); } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { uint64_t value = sim->debug_mmu->load_uint64(address); sbdata[0] = value; sbdata[1] = value >> 32; } else { sbcs.error = 3; } } catch (trap_load_access_fault& t) { sbcs.error = 2; } } void debug_module_t::sb_write() { reg_t address = ((uint64_t) sbaddress[1] << 32) \| sbaddress[0]; D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { sim->debug_mmu->store_uint8(address, sbdata[0]); } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { sim->debug_mmu->store_uint16(address, sbdata[0]); } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { sim->debug_mmu->store_uint32(address, sbdata[0]); } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { sim->debug_mmu->store_uint64(address, (((uint64_t) sbdata[1]) << 32) \| sbdata[0]); } else { sbcs.error = 3; } } bool debug_module_t::dmi_read(unsigned address, uint32_t value) { uint32_t result = 0; D(fprintf(stderr, "dmi_read(0x%x) -> ", address)); if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { unsigned i = address - DMI_DATA0; result = read32(dmdata, i); if (abstractcs.busy) { result = -1; fprintf(stderr, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address, i); } if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) { abstractcs.cmderr = CMDERR_BUSY; } if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) { perform_abstract_command(); } } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) { unsigned i = address - DMI_PROGBUF0; result = read32(program_buffer, i); if (abstractcs.busy) { result = -1; fprintf(stderr, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address, i); } if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) { perform_abstract_command(); } } else { switch (address) { case DMI_DMCONTROL: { processor_t proc = current_proc(); if (proc) dmcontrol.haltreq = proc->halt_request; result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq); result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq); result = set_field(result, DMI_DMCONTROL_HARTSELHI, dmcontrol.hartsel >> DMI_DMCONTROL_HARTSELLO_LENGTH); result = set_field(result, DMI_DMCONTROL_HARTSELLO, dmcontrol.hartsel); result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset); result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset); result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive); } break; case DMI_DMSTATUS: { processor_t proc = current_proc(); dmstatus.allnonexistant = false; dmstatus.allunavail = false; dmstatus.allrunning = false; dmstatus.allhalted = false; dmstatus.allresumeack = false; if (proc) { if (halted[dmcontrol.hartsel]) { dmstatus.allhalted = true; } else { dmstatus.allrunning = true; } } else { dmstatus.allnonexistant = true; } dmstatus.anynonexistant = dmstatus.allnonexistant; dmstatus.anyunavail = dmstatus.allunavail; dmstatus.anyrunning = dmstatus.allrunning; dmstatus.anyhalted = dmstatus.allhalted; if (proc) { if (resumeack[dmcontrol.hartsel]) { dmstatus.allresumeack = true; } else { dmstatus.allresumeack = false; } } else { dmstatus.allresumeack = false; } result = set_field(result, DMI_DMSTATUS_IMPEBREAK, dmstatus.impebreak); result = set_field(result, DMI_DMSTATUS_ALLHAVERESET, havereset[dmcontrol.hartsel]); result = set_field(result, DMI_DMSTATUS_ANYHAVERESET, havereset[dmcontrol.hartsel]); result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning); result = set_field(result, DMI_DMSTATUS_ALLHALTED, dmstatus.allhalted); result = set_field(result, DMI_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack); result = set_field(result, DMI_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); result = set_field(result, DMI_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); result = set_field(result, DMI_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); result = set_field(result, DMI_DMSTATUS_ANYHALTED, dmstatus.anyhalted); result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack); result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated); result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy); result = set_field(result, DMI_DMSTATUS_VERSION, dmstatus.version); } break; case DMI_ABSTRACTCS: result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr); result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy); result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount); result = set_field(result, DMI_ABSTRACTCS_PROGBUFSIZE, abstractcs.progbufsize); break; case DMI_ABSTRACTAUTO: result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf); result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata); break; case DMI_COMMAND: result = 0; break; case DMI_HARTINFO: result = set_field(result, DMI_HARTINFO_NSCRATCH, 1); result = set_field(result, DMI_HARTINFO_DATAACCESS, 1); result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount); result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start); break; case DMI_SBCS: result = set_field(result, DMI_SBCS_SBVERSION, sbcs.version); result = set_field(result, DMI_SBCS_SBREADONADDR, sbcs.readonaddr); result = set_field(result, DMI_SBCS_SBACCESS, sbcs.sbaccess); result = set_field(result, DMI_SBCS_SBAUTOINCREMENT, sbcs.autoincrement); result = set_field(result, DMI_SBCS_SBREADONDATA, sbcs.readondata); result = set_field(result, DMI_SBCS_SBERROR, sbcs.error); result = set_field(result, DMI_SBCS_SBASIZE, sbcs.asize); result = set_field(result, DMI_SBCS_SBACCESS128, sbcs.access128); result = set_field(result, DMI_SBCS_SBACCESS64, sbcs.access64); result = set_field(result, DMI_SBCS_SBACCESS32, sbcs.access32); result = set_field(result, DMI_SBCS_SBACCESS16, sbcs.access16); result = set_field(result, DMI_SBCS_SBACCESS8, sbcs.access8); break; case DMI_SBADDRESS0: result = sbaddress[0]; break; case DMI_SBADDRESS1: result = sbaddress[1]; break; case DMI_SBADDRESS2: result = sbaddress[2]; break; case DMI_SBADDRESS3: result = sbaddress[3]; break; case DMI_SBDATA0: result = sbdata[0]; if (sbcs.error == 0) { sb_autoincrement(); if (sbcs.readondata) { sb_read(); } } break; case DMI_SBDATA1: result = sbdata[1]; break; case DMI_SBDATA2: result = sbdata[2]; break; case DMI_SBDATA3: result = sbdata[3]; break; case DMI_AUTHDATA: result = challenge; break; default: result = 0; D(fprintf(stderr, "Unexpected. Returning Error.")); return false; } } D(fprintf(stderr, "0x%x\n", result)); value = result; return true; } bool debug_module_t::perform_abstract_command() { if (abstractcs.cmderr != CMDERR_NONE) return true; if (abstractcs.busy) { abstractcs.cmderr = CMDERR_BUSY; return true; } if ((command >> 24) == 0) { // register access unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE); bool write = get_field(command, AC_ACCESS_REGISTER_WRITE); unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO); if (!halted[dmcontrol.hartsel]) { abstractcs.cmderr = CMDERR_HALTRESUME; return true; } unsigned i = 0; if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) { if (regno < 0x1000 && progbufsize < 2) { // Make the debugger use the program buffer if it's available, so it // can test both use cases. write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH)); if (write) { switch (size) { case 2: write32(debug_abstract, i++, lw(S0, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, ld(S0, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } write32(debug_abstract, i++, csrw(S0, regno)); } else { write32(debug_abstract, i++, csrr(S0, regno)); switch (size) { case 2: write32(debug_abstract, i++, sw(S0, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, sd(S0, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH)); } else if (regno >= 0x1000 && regno < 0x1020) { unsigned regnum = regno - 0x1000; switch (size) { case 2: if (write) write32(debug_abstract, i++, lw(regnum, ZERO, debug_data_start)); else write32(debug_abstract, i++, sw(regnum, ZERO, debug_data_start)); break; case 3: if (write) write32(debug_abstract, i++, ld(regnum, ZERO, debug_data_start)); else write32(debug_abstract, i++, sd(regnum, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } else if (regno >= 0x1020 && regno < 0x1040) { // Don't force the debugger to use progbuf if it exists, so the // debugger has to make the decision not to use abstract commands to // access 64-bit FPRs on 32-bit targets. unsigned fprnum = regno - 0x1020; if (write) { switch (size) { case 2: write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, fld(fprnum, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } else { switch (size) { case 2: write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, fsd(fprnum, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } } else if (regno >= 0xc000 && (regno & 1) == 1) { // Support odd-numbered custom registers, to allow for debugger testing. unsigned custom_number = regno - 0xc000; abstractcs.cmderr = CMDERR_NONE; if (write) { // Writing V to custom register N will cause future reads of N to // return V, reads of N-1 will return V-1, etc. custom_base = read32(dmdata, 0) - custom_number; } else { write32(dmdata, 0, custom_number + custom_base); write32(dmdata, 1, 0); } return true; } else { abstractcs.cmderr = CMDERR_NOTSUP; return true; } } if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) { write32(debug_abstract, i, jal(ZERO, debug_progbuf_start - debug_abstract_start - 4 * i)); i++; } else { write32(debug_abstract, i++, ebreak()); } debug_rom_flags[dmcontrol.hartsel] \|= 1 << DEBUG_ROM_FLAG_GO; abstractcs.busy = true; } else { abstractcs.cmderr = CMDERR_NOTSUP; } return true; } bool debug_module_t::dmi_write(unsigned address, uint32_t value) { D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value)); if (!dmstatus.authenticated && address != DMI_AUTHDATA && address != DMI_DMCONTROL) return false; if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { unsigned i = address - DMI_DATA0; if (!abstractcs.busy) write32(dmdata, address - DMI_DATA0, value); if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) { abstractcs.cmderr = CMDERR_BUSY; } if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) { perform_abstract_command(); } return true; } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) { unsigned i = address - DMI_PROGBUF0; if (!abstractcs.busy) write32(program_buffer, i, value); if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) { perform_abstract_command(); } return true; } else { switch (address) { case DMI_DMCONTROL: { if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE)) reset(); dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE); if (!dmstatus.authenticated) return true; if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ); dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET); dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSELHI) << DMI_DMCONTROL_HARTSELLO_LENGTH; dmcontrol.hartsel \|= get_field(value, DMI_DMCONTROL_HARTSELLO); dmcontrol.hartsel &= (1L<<hartsellen) - 1; if (get_field(value, DMI_DMCONTROL_ACKHAVERESET)) { havereset[dmcontrol.hartsel] = false; } } processor_t *proc = current_proc(); if (proc) { proc->halt_request = dmcontrol.haltreq; if (dmcontrol.resumereq) { debug_rom_flags[dmcontrol.hartsel] \|= (1 << DEBUG_ROM_FLAG_RESUME); resumeack[dmcontrol.hartsel] = false; } if (dmcontrol.hartreset) { proc->reset(); } } if (dmcontrol.ndmreset) { for (size_t i = 0; i < sim->nprocs(); i++) { proc = sim->get_core(i); proc->reset(); } } } return true; case DMI_COMMAND: command = value; return perform_abstract_command(); case DMI_ABSTRACTCS: abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DMI_ABSTRACTCS_CMDERR)))); return true; case DMI_ABSTRACTAUTO: abstractauto.autoexecprogbuf = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF); abstractauto.autoexecdata = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECDATA); return true; case DMI_SBCS: sbcs.readonaddr = get_field(value, DMI_SBCS_SBREADONADDR); sbcs.sbaccess = get_field(value, DMI_SBCS_SBACCESS); sbcs.autoincrement = get_field(value, DMI_SBCS_SBAUTOINCREMENT); sbcs.readondata = get_field(value, DMI_SBCS_SBREADONDATA); sbcs.error &= ~get_field(value, DMI_SBCS_SBERROR); return true; case DMI_SBADDRESS0: sbaddress[0] = value; if (sbcs.error == 0 && sbcs.readonaddr) { sb_read(); } return true; case DMI_SBADDRESS1: sbaddress[1] = value; return true; case DMI_SBADDRESS2: sbaddress[2] = value; return true; case DMI_SBADDRESS3: sbaddress[3] = value; return true; case DMI_SBDATA0: sbdata[0] = value; if (sbcs.error == 0) { sb_write(); if (sbcs.autoincrement && sbcs.error == 0) { sb_autoincrement(); } } return true; case DMI_SBDATA1: sbdata[1] = value; return true; case DMI_SBDATA2: sbdata[2] = value; return true; case DMI_SBDATA3: sbdata[3] = value; return true; case DMI_AUTHDATA: D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value, challenge + secret)); if (require_authentication) { if (value == challenge + secret) { dmstatus.authenticated = true; } else { dmstatus.authenticated = false; challenge = random(); } } return true; } } return false; } void debug_module_t::proc_reset(unsigned id) { havereset[id] = true; halted[id] = false; }
// See LICENSE for license details. #ifndef _RISCV_DEBUG_MODULE_H #define _RISCV_DEBUG_MODULE_H #include <set> #include "devices.h" class sim_t; typedef struct { bool haltreq; bool resumereq; unsigned hartsel; bool hartreset; bool dmactive; bool ndmreset; } dmcontrol_t; typedef struct { bool impebreak; bool allhavereset; bool anyhavereset; bool allnonexistant; bool anynonexistant; bool allunavail; bool anyunavail; bool allrunning; bool anyrunning; bool allhalted; bool anyhalted; bool allresumeack; bool anyresumeack; bool authenticated; bool authbusy; bool cfgstrvalid; unsigned version; } dmstatus_t; typedef enum cmderr { CMDERR_NONE = 0, CMDERR_BUSY = 1, CMDERR_NOTSUP = 2, CMDERR_EXCEPTION = 3, CMDERR_HALTRESUME = 4, CMDERR_OTHER = 7 } cmderr_t; typedef struct { bool busy; unsigned datacount; unsigned progbufsize; cmderr_t cmderr; } abstractcs_t; typedef struct { unsigned autoexecprogbuf; unsigned autoexecdata; } abstractauto_t; typedef struct { unsigned version; bool readonaddr; unsigned sbaccess; bool autoincrement; bool readondata; unsigned error; unsigned asize; bool access128; bool access64; bool access32; bool access16; bool access8; } sbcs_t; class debug_module_t : public abstract_device_t { public: /* * If require_authentication is true, then a debugger must authenticate as * follows: * 1. Read a 32-bit value from authdata: * 2. Write the value that was read back, plus one, to authdata. / debug_module_t(sim_t sim, unsigned progbufsize, unsigned max_bus_master_bits, bool require_authentication); ~debug_module_t(); void add_device(bus_t bus); bool load(reg_t addr, size_t len, uint8_t bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); // Debug Module Interface that the debugger (in our case through JTAG DTM) // uses to access the DM. // Return true for success, false for failure. bool dmi_read(unsigned address, uint32_t value); bool dmi_write(unsigned address, uint32_t value); // Called when one of the attached harts was reset. void proc_reset(unsigned id); private: static const unsigned datasize = 2; // Size of program_buffer in 32-bit words, as exposed to the rest of the // world. unsigned progbufsize; // Actual size of the program buffer, which is 1 word bigger than we let on // to implement the implicit ebreak at the end. unsigned program_buffer_bytes; unsigned max_bus_master_bits; bool require_authentication; static const unsigned debug_data_start = 0x380; unsigned debug_progbuf_start; static const unsigned debug_abstract_size = 5; unsigned debug_abstract_start; // R/W this through custom registers, to allow debuggers to test that // functionality. unsigned custom_base; // We only support 1024 harts currently. More requires at least resizing // the arrays below, and their corresponding special memory regions. static const unsigned hartsellen = 10; sim_t sim; uint8_t debug_rom_whereto[4]; uint8_t debug_abstract[debug_abstract_size * 4]; uint8_t program_buffer; uint8_t dmdata[datasize 4]; bool halted[1024]; bool resumeack[1024]; bool havereset[1024]; uint8_t debug_rom_flags[1024]; void write32(uint8_t rom, unsigned int index, uint32_t value); uint32_t read32(uint8_t rom, unsigned int index); void sb_autoincrement(); void sb_read(); void sb_write(); unsigned sb_access_bits(); dmcontrol_t dmcontrol; dmstatus_t dmstatus; abstractcs_t abstractcs; abstractauto_t abstractauto; uint32_t command; sbcs_t sbcs; uint32_t sbaddress[4]; uint32_t sbdata[4]; uint32_t challenge; const uint32_t secret = 1; processor_t *current_proc() const; void reset(); bool perform_abstract_command(); }; #endif
// See LICENSE file for license details. #ifndef DEBUG_ROM_DEFINES_H #define DEBUG_ROM_DEFINES_H // These are implementation-specific addresses in the Debug Module #define DEBUG_ROM_HALTED 0x100 #define DEBUG_ROM_GOING 0x104 #define DEBUG_ROM_RESUMING 0x108 #define DEBUG_ROM_EXCEPTION 0x10C // Region of memory where each hart has 1 // byte to read. #define DEBUG_ROM_FLAGS 0x400 #define DEBUG_ROM_FLAG_GO 0 #define DEBUG_ROM_FLAG_RESUME 1 // These needs to match the link.ld #define DEBUG_ROM_WHERETO 0x300 #define DEBUG_ROM_ENTRY 0x800 #define DEBUG_ROM_TVEC 0x808 #endif
// See LICENSE for license details. #ifndef _RISCV_DECODE_H #define _RISCV_DECODE_H #if (-1 != ~0) \|\| ((-1 >> 1) != -1) # error spike requires a two''s-complement c++ implementation #endif #ifdef WORDS_BIGENDIAN # error spike requires a little-endian host #endif #include <cstdint> #include <string.h> #include <strings.h> #include "encoding.h" #include "config.h" #include "common.h" #include "softfloat_types.h" #include "specialize.h" #include <cinttypes> typedef int64_t sreg_t; typedef uint64_t reg_t; const int NXPR = 32; const int NFPR = 32; const int NCSR = 4096; #define X_RA 1 #define X_SP 2 #define FP_RD_NE 0 #define FP_RD_0 1 #define FP_RD_DN 2 #define FP_RD_UP 3 #define FP_RD_NMM 4 #define FSR_RD_SHIFT 5 #define FSR_RD (0x7 << FSR_RD_SHIFT) #define FPEXC_NX 0x01 #define FPEXC_UF 0x02 #define FPEXC_OF 0x04 #define FPEXC_DZ 0x08 #define FPEXC_NV 0x10 #define FSR_AEXC_SHIFT 0 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA) #define insn_length(x) \ (((x) & 0x03) < 0x03 ? 2 : \ ((x) & 0x1f) < 0x1f ? 4 : \ ((x) & 0x3f) < 0x3f ? 6 : \ 8) #define MAX_INSN_LENGTH 8 #define PC_ALIGN 2 typedef uint64_t insn_bits_t; class insn_t { public: insn_t() = default; insn_t(insn_bits_t bits) : b(bits) {} insn_bits_t bits() { return b; } int length() { return insn_length(b); } int64_t i_imm() { return int64_t(b) >> 20; } int64_t shamt() { return x(20, 6); } int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); } int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); } int64_t u_imm() { return int64_t(b) >> 12 << 12; } int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); } uint64_t rd() { return x(7, 5); } uint64_t rs1() { return x(15, 5); } uint64_t rs2() { return x(20, 5); } uint64_t rs3() { return x(27, 5); } uint64_t rm() { return x(12, 3); } uint64_t csr() { return x(20, 12); } int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } int64_t rvc_simm3() { return x(10, 3); } uint64_t rvc_rd() { return rd(); } uint64_t rvc_rs1() { return rd(); } uint64_t rvc_rs2() { return x(2, 5); } uint64_t rvc_rs1s() { return 8 + x(7, 3); } uint64_t rvc_rs2s() { return 8 + x(2, 3); } private: insn_bits_t b; uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); } uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); } uint64_t imm_sign() { return xs(63, 1); } }; template <class T, size_t N, bool zero_reg> class regfile_t { public: void write(size_t i, T value) { if (!zero_reg \|\| i != 0) data[i] = value; } const T& operator [] (size_t i) const { return data[i]; } private: T data[N]; }; // helpful macros, etc #define MMU (p->get_mmu()) #define STATE (p->get_state()) #define READ_REG(reg) STATE.XPR[reg] #define READ_FREG(reg) STATE.FPR[reg] #define RS1 READ_REG(insn.rs1()) #define RS2 READ_REG(insn.rs2()) #define WRITE_RD(value) WRITE_REG(insn.rd(), value) #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) #else # define WRITE_REG(reg, value) ({ \ reg_t wdata = (value); /* value may have side effects / \ STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \ STATE.XPR.write(reg, wdata); \ }) # define WRITE_FREG(reg, value) ({ \ freg_t wdata = freg(value); / value may have side effects / \ STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) \| 1, wdata}; \ DO_WRITE_FREG(reg, wdata); \ }) #endif // RVC macros #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) #define RVC_RS1 READ_REG(insn.rvc_rs1()) #define RVC_RS2 READ_REG(insn.rvc_rs2()) #define RVC_RS1S READ_REG(insn.rvc_rs1s()) #define RVC_RS2S READ_REG(insn.rvc_rs2s()) #define RVC_FRS2 READ_FREG(insn.rvc_rs2()) #define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) #define RVC_SP READ_REG(X_SP) // FPU macros #define FRS1 READ_FREG(insn.rs1()) #define FRS2 READ_FREG(insn.rs2()) #define FRS3 READ_FREG(insn.rs3()) // #define dirty_fp_state (STATE.mstatus \|= MSTATUS_FS \| (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define dirty_fp_state (STATE.mstatus &= MSTATUS_FS \| (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define dirty_ext_state (STATE.mstatus \|= MSTATUS_XS \| (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) #define SHAMT (insn.i_imm() & 0x3F) #define BRANCH_TARGET (pc + insn.sb_imm()) #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ if(rm == 7) rm = STATE.frm; \ if(rm > 4) throw trap_illegal_instruction(0); \ rm; }) #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) \| (((decltype(reg))(val) ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0) #define require_privilege(p) require(STATE.prv >= (p)) #define require_rv64 require(xlen == 64) #define require_rv32 require(xlen == 32) #define require_extension(s) require(p->supports_extension(s)) #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0) #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0) #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ dirty_fp_state; \ STATE.fflags \|= softfloat_exceptionFlags; \ } \ softfloat_exceptionFlags = 0; }) #define sext32(x) ((sreg_t)(int32_t)(x)) #define zext32(x) ((reg_t)(uint32_t)(x)) #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen)) #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) #define set_pc(x) \ do { p->check_pc_alignment(x); \ npc = sext_xlen(x); \ } while(0) #define set_pc_and_serialize(x) \ do { reg_t __npc = (x) & p->pc_alignment_mask(); \ npc = PC_SERIALIZE_AFTER; \ STATE.pc = __npc; \ } while(0) #define wfi() \ do { set_pc_and_serialize(npc); \ npc = PC_SERIALIZE_WFI; \ } while(0) #define serialize() set_pc_and_serialize(npc) /* Sentinel PC values to serialize simulator pipeline / #define PC_SERIALIZE_BEFORE 3 #define PC_SERIALIZE_AFTER 5 #define PC_SERIALIZE_WFI 7 #define invalid_pc(pc) ((pc) & 1) / Convenience wrappers to simplify softfloat code sequences */ #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) #define isBoxedF64(r) ((r.v[1] + 1) == 0) #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI) typedef float128_t freg_t; inline float32_t f32(uint32_t v) { return { v }; } inline float64_t f64(uint64_t v) { return { v }; } inline float32_t f32(freg_t r) { return f32(unboxF32(r)); } inline float64_t f64(freg_t r) { return f64(unboxF64(r)); } inline float128_t f128(freg_t r) { return r; } inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) \| f.v, (uint64_t)-1 }; } inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; } inline freg_t freg(float128_t f) { return f; } #define F32_SIGN ((uint32_t)1 << 31) #define F64_SIGN ((uint64_t)1 << 63) #define fsgnj32(a, b, n, x) \ f32((f32(a).v & ~F32_SIGN) \| ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) #define fsgnj64(a, b, n, x) \ f64((f64(a).v & ~F64_SIGN) \| ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) #define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0]) inline float128_t defaultNaNF128() { float128_t nan; nan.v[1] = defaultNaNF128UI64; nan.v[0] = defaultNaNF128UI0; return nan; } inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x) { a.v[1] = (a.v[1] & ~F64_SIGN) \| (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN); return a; } inline freg_t f128_negate(freg_t a) { a.v[1] ^= F64_SIGN; return a; } #define validate_csr(which, write) ({ \ if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ STATE.serialized = false; \ unsigned csr_priv = get_field((which), 0x300); \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ if (((write) && csr_read_only) \|\| STATE.prv < csr_priv) \ throw trap_illegal_instruction(0); \ (which); }) // Seems that 0x0 doesn't work. #define DEBUG_START 0x100 #define DEBUG_END (0x1000 - 1) #endif
#include "devices.h" void bus_t::add_device(reg_t addr, abstract_device_t* dev) { // Searching devices via lower_bound/upper_bound // implicitly relies on the underlying std::map // container to sort the keys and provide ordered // iteration over this sort, which it does. (python's // SortedDict is a good analogy) devices[addr] = dev; } bool bus_t::load(reg_t addr, size_t len, uint8_t* bytes) { // Find the device with the base address closest to but // less than addr (price-is-right search) auto it = devices.upper_bound(addr); if (devices.empty() \|\| it == devices.begin()) { // Either the bus is empty, or there weren't // any items with a base address <= addr return false; } // Found at least one item with base address <= addr // The iterator points to the device after this, so // go back by one item. it--; return it->second->load(addr - it->first, len, bytes); } bool bus_t::store(reg_t addr, size_t len, const uint8_t* bytes) { // See comments in bus_t::load auto it = devices.upper_bound(addr); if (devices.empty() \|\| it == devices.begin()) { return false; } it--; return it->second->store(addr - it->first, len, bytes); } std::pair<reg_t, abstract_device_t> bus_t::find_device(reg_t addr) { // See comments in bus_t::load auto it = devices.upper_bound(addr); if (devices.empty() \|\| it == devices.begin()) { return std::make_pair((reg_t)0, (abstract_device_t)NULL); } it--; return std::make_pair(it->first, it->second); }
#ifndef _RISCV_DEVICES_H #define _RISCV_DEVICES_H #include "decode.h" #include <cstdlib> #include <string> #include <map> #include <vector> #include <fstream> class processor_t; class abstract_device_t { public: virtual bool load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) = 0; virtual ~abstract_device_t() {} }; class bus_t : public abstract_device_t { public: bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); void add_device(reg_t addr, abstract_device_t* dev); std::pair<reg_t, abstract_device_t> find_device(reg_t addr); private: std::map<reg_t, abstract_device_t> devices; }; class rom_device_t : public abstract_device_t { public: rom_device_t(std::vector<char> data); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); const std::vector<char>& contents() { return data; } private: std::vector<char> data; }; class mem_t : public abstract_device_t { public: mem_t(size_t size) : len(size) { if (!size) throw std::runtime_error("zero bytes of target memory requested"); data = (char)calloc(1, size); if (!data) throw std::runtime_error("couldn't allocate " + std::to_string(size) + " bytes of target memory"); } mem_t(const mem_t& that) = delete; ~mem_t() { free(data); } bool load(reg_t addr, size_t len, uint8_t bytes) { return false; } bool store(reg_t addr, size_t len, const uint8_t* bytes) { return false; } char* contents() { return data; } size_t size() { return len; } private: char* data; size_t len; }; class clint_t : public abstract_device_t { public: clint_t(std::vector<processor_t>&); bool load(reg_t addr, size_t len, uint8_t bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); void reset(); size_t size() { return CLINT_SIZE; } void increment(reg_t inc); private: typedef uint64_t mtime_t; typedef uint64_t mtimecmp_t; typedef uint32_t msip_t; std::vector<processor_t>& procs; mtime_t mtime; std::vector<mtimecmp_t> mtimecmp; }; class uart_t : public abstract_device_t { public: uart_t(); bool load(reg_t addr, size_t len, uint8_t bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); private: uint8_t ier; uint8_t dll; uint8_t dlm; uint8_t lcr; uint8_t lsr; uint8_t scr; uint8_t msr; uint8_t mcr; bool fifo_enabled; }; class dump_t : public abstract_device_t { public: dump_t(); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); private: std::ofstream ofs; }; #endif
// See LICENSE for license details. #ifndef _RISCV_DISASM_H #define _RISCV_DISASM_H #include "decode.h" #include <string> #include <sstream> #include <vector> extern const char* xpr_name[NXPR]; extern const char* fpr_name[NFPR]; extern const char* csr_name(int which); class arg_t { public: virtual std::string to_string(insn_t val) const = 0; virtual ~arg_t() {} }; class disasm_insn_t { public: disasm_insn_t(const char* name, uint32_t match, uint32_t mask, const std::vector<const arg_t>& args) : match(match), mask(mask), args(args), name(name) {} bool operator == (insn_t insn) const { return (insn.bits() & mask) == match; } std::string to_string(insn_t insn) const { std::stringstream s; int len; for (len = 0; name[len]; len++) s << (name[len] == '_' ? '.' : name[len]); if (args.size()) { s << std::string(std::max(1, 8 - len), ' '); for (size_t i = 0; i < args.size()-1; i++) s << args[i]->to_string(insn) << ", "; s << args[args.size()-1]->to_string(insn); } return s.str(); } uint32_t get_match() const { return match; } uint32_t get_mask() const { return mask; } private: uint32_t match; uint32_t mask; std::vector<const arg_t> args; const char* name; }; class disassembler_t { public: disassembler_t(int xlen); ~disassembler_t(); std::string disassemble(insn_t insn) const; void add_insn(disasm_insn_t* insn); private: static const int HASH_SIZE = 256; std::vector<const disasm_insn_t> chain[HASH_SIZE+1]; const disasm_insn_t lookup(insn_t insn) const; }; #endif
// See LICENSE for license details. #include "dts.h" #include <iostream> #include <sstream> #include <signal.h> #include <unistd.h> #include <sys/wait.h> #include <sys/types.h> std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, std::vector<processor_t> procs, std::vector<std::pair<reg_t, mem_t>> mems) { std::stringstream s; s << std::dec << "/dts-v1/;\n" "\n" "/ {\n" " #address-cells = <2>;\n" " #size-cells = <2>;\n" " compatible = \"ucbbar,spike-bare-dev\";\n" " model = \"ucbbar,spike-bare\";\n" " cpus {\n" " #address-cells = <1>;\n" " #size-cells = <0>;\n" " timebase-frequency = <" << (cpu_hz/insns_per_rtc_tick) << ">;\n"; for (size_t i = 0; i < procs.size(); i++) { s << " CPU" << i << ": cpu@" << i << " {\n" " device_type = \"cpu\";\n" " reg = <" << i << ">;\n" " status = \"okay\";\n" " compatible = \"riscv\";\n" " riscv,isa = \"" << procs[i]->get_isa_string() << "\";\n" " mmu-type = \"riscv," << (procs[i]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << cpu_hz << ">;\n" " CPU" << i << "_intc: interrupt-controller {\n" " #interrupt-cells = <1>;\n" " interrupt-controller;\n" " compatible = \"riscv,cpu-intc\";\n" " };\n" " };\n"; } s << " };\n"; for (auto& m : mems) { s << std::hex << " memory@" << m.first << " {\n" " device_type = \"memory\";\n" " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" " };\n"; } s << " soc {\n" " #address-cells = <2>;\n" " #size-cells = <2>;\n" " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" " ranges;\n" " clint@" << CLINT_BASE << " {\n" " compatible = \"riscv,clint0\";\n" " interrupts-extended = <" << std::dec; for (size_t i = 0; i < procs.size(); i++) s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; reg_t clintbs = CLINT_BASE; reg_t clintsz = CLINT_SIZE; s << std::hex << ">;\n" " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) << " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" " };\n" " };\n" // " htif {\n" // " compatible = \"ucb,htif0\";\n" // " };\n" " uart@" << UART_BASE << " {\n" " compatible = \"ns16750\";\n" " reg = <0x0 0x10000000 0x0 0x1000>;\n" " clock-frequency = <50000000>;\n" " current-speed = <115200>;\n" // " interrupt-parent = <&PLIC0>;\n" // " interrupts = <1>;\n" " reg-shift = <2>;\n" " reg-io-width = <4>;\n" " };\n" "};\n"; return s.str(); } std::string dts_compile(const std::string& dts) { // Convert the DTS to DTB int dts_pipe[2]; pid_t dts_pid; if (pipe(dts_pipe) != 0 \|\| (dts_pid = fork()) < 0) { std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; exit(1); } // Child process to output dts if (dts_pid == 0) { close(dts_pipe[0]); int step, len = dts.length(); const char *buf = dts.c_str(); for (int done = 0; done < len; done += step) { step = write(dts_pipe[1], buf+done, len-done); if (step == -1) { std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; exit(1); } } close(dts_pipe[1]); exit(0); } pid_t dtb_pid; int dtb_pipe[2]; if (pipe(dtb_pipe) != 0 \|\| (dtb_pid = fork()) < 0) { std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; exit(1); } // Child process to output dtb if (dtb_pid == 0) { dup2(dts_pipe[0], 0); dup2(dtb_pipe[1], 1); close(dts_pipe[0]); close(dts_pipe[1]); close(dtb_pipe[0]); close(dtb_pipe[1]); execl(DTC, DTC, "-O", "dtb", 0); std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; exit(1); } close(dts_pipe[1]); close(dts_pipe[0]); close(dtb_pipe[1]); // Read-out dtb std::stringstream dtb; int got; char buf[4096]; while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { dtb.write(buf, got); } if (got == -1) { std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; exit(1); } close(dtb_pipe[0]); // Reap children int status; waitpid(dts_pid, &status, 0); if (!WIFEXITED(status) \|\| WEXITSTATUS(status) != 0) { std::cerr << "Child dts process failed" << std::endl; exit(1); } waitpid(dtb_pid, &status, 0); if (!WIFEXITED(status) \|\| WEXITSTATUS(status) != 0) { std::cerr << "Child dtb process failed" << std::endl; exit(1); } return dtb.str(); }
// See LICENSE for license details. #ifndef _RISCV_DTS_H #define _RISCV_DTS_H #include "processor.h" #include "mmu.h" #include <string> std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, std::vector<processor_t> procs, std::vector<std::pair<reg_t, mem_t>> mems); std::string dts_compile(const std::string& dts); #endif
#include "devices.h" #include "processor.h" #include <fstream> dump_t::dump_t() : ofs("dump.bin") { // printf("Calling Dump\n"); } bool dump_t::load(reg_t addr, size_t len, uint8_t* bytes) { return true; } bool dump_t::store(reg_t addr, size_t len, const uint8_t* bytes) { // printf("DUmpping\n"); ofs.write(reinterpret_cast<const char *>(bytes), len); return true; }
// See LICENSE for license details. #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 #define MSTATUS_MIE 0x00000008 #define MSTATUS_UPIE 0x00000010 #define MSTATUS_SPIE 0x00000020 #define MSTATUS_HPIE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 #define MSTATUS_HPP 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 #define MSTATUS_SUM 0x00040000 #define MSTATUS_MXR 0x00080000 #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 #define MSTATUS64_SD 0x8000000000000000 #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) #define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) #define DCSR_EBREAKU (1<<12) #define DCSR_STOPCYCLE (1<<10) #define DCSR_STOPTIME (1<<9) #define DCSR_CAUSE (7<<6) #define DCSR_DEBUGINT (1<<5) #define DCSR_HALT (1<<3) #define DCSR_STEP (1<<2) #define DCSR_PRV (3<<0) #define DCSR_CAUSE_NONE 0 #define DCSR_CAUSE_SWBP 1 #define DCSR_CAUSE_HWBP 2 #define DCSR_CAUSE_DEBUGINT 3 #define DCSR_CAUSE_STEP 4 #define DCSR_CAUSE_HALT 5 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) #define MCONTROL_SELECT (1<<19) #define MCONTROL_TIMING (1<<18) #define MCONTROL_ACTION (0x3f<<12) #define MCONTROL_CHAIN (1<<11) #define MCONTROL_MATCH (0xf<<7) #define MCONTROL_M (1<<6) #define MCONTROL_H (1<<5) #define MCONTROL_S (1<<4) #define MCONTROL_U (1<<3) #define MCONTROL_EXECUTE (1<<2) #define MCONTROL_STORE (1<<1) #define MCONTROL_LOAD (1<<0) #define MCONTROL_TYPE_NONE 0 #define MCONTROL_TYPE_MATCH 2 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 #define MCONTROL_ACTION_DEBUG_MODE 1 #define MCONTROL_ACTION_TRACE_START 2 #define MCONTROL_ACTION_TRACE_STOP 3 #define MCONTROL_ACTION_TRACE_EMIT 4 #define MCONTROL_MATCH_EQUAL 0 #define MCONTROL_MATCH_NAPOT 1 #define MCONTROL_MATCH_GE 2 #define MCONTROL_MATCH_LT 3 #define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_STIP (1 << IRQ_S_TIMER) #define MIP_HTIP (1 << IRQ_H_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_HEIP (1 << IRQ_H_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 #define PRV_M 3 #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7FC00000 #define SATP32_PPN 0x003FFFFF #define SATP64_MODE 0xF000000000000000 #define SATP64_ASID 0x0FFFF00000000000 #define SATP64_PPN 0x00000FFFFFFFFFFF #define SATP_MODE_OFF 0 #define SATP_MODE_SV32 1 #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 #define SATP_MODE_SV57 10 #define SATP_MODE_SV64 11 #define PMP_R 0x01 #define PMP_W 0x02 #define PMP_X 0x04 #define PMP_A 0x18 #define PMP_L 0x80 #define PMP_SHIFT 2 #define PMP_TOR 0x08 #define PMP_NA4 0x10 #define PMP_NAPOT 0x18 #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_S_TIMER 5 #define IRQ_H_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_S_EXT 9 #define IRQ_H_EXT 10 #define IRQ_M_EXT 11 #define IRQ_COP 12 #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00010000 #define CLINT_BASE 0x02000000 #define CLINT_SIZE 0x000c0000 #define UART_BASE 0x10000000 #define UART_SIZE 0x00010000 #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 #define DUMP_BASE 0x82000000 #define DUMP_SIZE 0x20000000 // page table entry (PTE) fields #define PTE_V 0x001 // Valid #define PTE_R 0x002 // Read #define PTE_W 0x004 // Write #define PTE_X 0x008 // Execute #define PTE_U 0x010 // User #define PTE_G 0x020 // Global #define PTE_A 0x040 // Accessed #define PTE_D 0x080 // Dirty #define PTE_SOFT 0x300 // Reserved for Software #define PTE_PPN_SHIFT 10 #define PTE_TABLE(PTE) (((PTE) & (PTE_V \| PTE_R \| PTE_W \| PTE_X)) == PTE_V) #ifdef __riscv #if __riscv_xlen == 64 # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVEL_BITS 9 # define SATP_MODE SATP64_MODE #else # define MSTATUS_SD MSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVEL_BITS 10 # define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) #ifndef __ASSEMBLER__ #ifdef __GNUC__ #define read_csr(reg) ({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) #define write_csr(reg, val) ({ \ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ __tmp; }) #define set_csr(reg, bit) ({ unsigned long __tmp; \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define clear_csr(reg, bit) ({ unsigned long __tmp; \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) #define rdinstret() read_csr(instret) #endif #endif #endif #endif /* Automatically generated by parse-opcodes. */ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H #define MATCH_BEQ 0x63 #define MASK_BEQ 0x707f #define MATCH_BNE 0x1063 #define MASK_BNE 0x707f #define MATCH_BLT 0x4063 #define MASK_BLT 0x707f #define MATCH_BGE 0x5063 #define MASK_BGE 0x707f #define MATCH_BLTU 0x6063 #define MASK_BLTU 0x707f #define MATCH_BGEU 0x7063 #define MASK_BGEU 0x707f #define MATCH_JALR 0x67 #define MASK_JALR 0x707f #define MATCH_JAL 0x6f #define MASK_JAL 0x7f #define MATCH_LUI 0x37 #define MASK_LUI 0x7f #define MATCH_AUIPC 0x17 #define MASK_AUIPC 0x7f #define MATCH_ADDI 0x13 #define MASK_ADDI 0x707f #define MATCH_SLLI 0x1013 #define MASK_SLLI 0xfc00707f #define MATCH_SLTI 0x2013 #define MASK_SLTI 0x707f #define MATCH_SLTIU 0x3013 #define MASK_SLTIU 0x707f #define MATCH_XORI 0x4013 #define MASK_XORI 0x707f #define MATCH_SRLI 0x5013 #define MASK_SRLI 0xfc00707f #define MATCH_SRAI 0x40005013 #define MASK_SRAI 0xfc00707f #define MATCH_ORI 0x6013 #define MASK_ORI 0x707f #define MATCH_ANDI 0x7013 #define MASK_ANDI 0x707f #define MATCH_ADD 0x33 #define MASK_ADD 0xfe00707f #define MATCH_SUB 0x40000033 #define MASK_SUB 0xfe00707f #define MATCH_SLL 0x1033 #define MASK_SLL 0xfe00707f #define MATCH_SLT 0x2033 #define MASK_SLT 0xfe00707f #define MATCH_SLTU 0x3033 #define MASK_SLTU 0xfe00707f #define MATCH_XOR 0x4033 #define MASK_XOR 0xfe00707f #define MATCH_SRL 0x5033 #define MASK_SRL 0xfe00707f #define MATCH_SRA 0x40005033 #define MASK_SRA 0xfe00707f #define MATCH_OR 0x6033 #define MASK_OR 0xfe00707f #define MATCH_AND 0x7033 #define MASK_AND 0xfe00707f #define MATCH_ADDIW 0x1b #define MASK_ADDIW 0x707f #define MATCH_SLLIW 0x101b #define MASK_SLLIW 0xfe00707f #define MATCH_SRLIW 0x501b #define MASK_SRLIW 0xfe00707f #define MATCH_SRAIW 0x4000501b #define MASK_SRAIW 0xfe00707f #define MATCH_ADDW 0x3b #define MASK_ADDW 0xfe00707f #define MATCH_SUBW 0x4000003b #define MASK_SUBW 0xfe00707f #define MATCH_SLLW 0x103b #define MASK_SLLW 0xfe00707f #define MATCH_SRLW 0x503b #define MASK_SRLW 0xfe00707f #define MATCH_SRAW 0x4000503b #define MASK_SRAW 0xfe00707f #define MATCH_LB 0x3 #define MASK_LB 0x707f #define MATCH_LH 0x1003 #define MASK_LH 0x707f #define MATCH_LW 0x2003 #define MASK_LW 0x707f #define MATCH_LD 0x3003 #define MASK_LD 0x707f #define MATCH_LBU 0x4003 #define MASK_LBU 0x707f #define MATCH_LHU 0x5003 #define MASK_LHU 0x707f #define MATCH_LWU 0x6003 #define MASK_LWU 0x707f #define MATCH_SB 0x23 #define MASK_SB 0x707f #define MATCH_SH 0x1023 #define MASK_SH 0x707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f #define MATCH_SD 0x3023 #define MASK_SD 0x707f #define MATCH_FENCE 0xf #define MASK_FENCE 0x707f #define MATCH_FENCE_I 0x100f #define MASK_FENCE_I 0x707f #define MATCH_MUL 0x2000033 #define MASK_MUL 0xfe00707f #define MATCH_MULH 0x2001033 #define MASK_MULH 0xfe00707f #define MATCH_MULHSU 0x2002033 #define MASK_MULHSU 0xfe00707f #define MATCH_MULHU 0x2003033 #define MASK_MULHU 0xfe00707f #define MATCH_DIV 0x2004033 #define MASK_DIV 0xfe00707f #define MATCH_DIVU 0x2005033 #define MASK_DIVU 0xfe00707f #define MATCH_REM 0x2006033 #define MASK_REM 0xfe00707f #define MATCH_REMU 0x2007033 #define MASK_REMU 0xfe00707f #define MATCH_MULW 0x200003b #define MASK_MULW 0xfe00707f #define MATCH_DIVW 0x200403b #define MASK_DIVW 0xfe00707f #define MATCH_DIVUW 0x200503b #define MASK_DIVUW 0xfe00707f #define MATCH_REMW 0x200603b #define MASK_REMW 0xfe00707f #define MATCH_REMUW 0x200703b #define MASK_REMUW 0xfe00707f #define MATCH_AMOADD_W 0x202f #define MASK_AMOADD_W 0xf800707f #define MATCH_AMOXOR_W 0x2000202f #define MASK_AMOXOR_W 0xf800707f #define MATCH_AMOOR_W 0x4000202f #define MASK_AMOOR_W 0xf800707f #define MATCH_AMOAND_W 0x6000202f #define MASK_AMOAND_W 0xf800707f #define MATCH_AMOMIN_W 0x8000202f #define MASK_AMOMIN_W 0xf800707f #define MATCH_AMOMAX_W 0xa000202f #define MASK_AMOMAX_W 0xf800707f #define MATCH_AMOMINU_W 0xc000202f #define MASK_AMOMINU_W 0xf800707f #define MATCH_AMOMAXU_W 0xe000202f #define MASK_AMOMAXU_W 0xf800707f #define MATCH_AMOSWAP_W 0x800202f #define MASK_AMOSWAP_W 0xf800707f #define MATCH_LR_W 0x1000202f #define MASK_LR_W 0xf9f0707f #define MATCH_SC_W 0x1800202f #define MASK_SC_W 0xf800707f #define MATCH_AMOADD_D 0x302f #define MASK_AMOADD_D 0xf800707f #define MATCH_AMOXOR_D 0x2000302f #define MASK_AMOXOR_D 0xf800707f #define MATCH_AMOOR_D 0x4000302f #define MASK_AMOOR_D 0xf800707f #define MATCH_AMOAND_D 0x6000302f #define MASK_AMOAND_D 0xf800707f #define MATCH_AMOMIN_D 0x8000302f #define MASK_AMOMIN_D 0xf800707f #define MATCH_AMOMAX_D 0xa000302f #define MASK_AMOMAX_D 0xf800707f #define MATCH_AMOMINU_D 0xc000302f #define MASK_AMOMINU_D 0xf800707f #define MATCH_AMOMAXU_D 0xe000302f #define MASK_AMOMAXU_D 0xf800707f #define MATCH_AMOSWAP_D 0x800302f #define MASK_AMOSWAP_D 0xf800707f #define MATCH_LR_D 0x1000302f #define MASK_LR_D 0xf9f0707f #define MATCH_SC_D 0x1800302f #define MASK_SC_D 0xf800707f #define MATCH_ECALL 0x73 #define MASK_ECALL 0xffffffff #define MATCH_EBREAK 0x100073 #define MASK_EBREAK 0xffffffff #define MATCH_URET 0x200073 #define MASK_URET 0xffffffff #define MATCH_SRET 0x10200073 #define MASK_SRET 0xffffffff #define MATCH_MRET 0x30200073 #define MASK_MRET 0xffffffff #define MATCH_DRET 0x7b200073 #define MASK_DRET 0xffffffff #define MATCH_SFENCE_VMA 0x12000073 #define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 #define MASK_CSRRW 0x707f #define MATCH_CSRRS 0x2073 #define MASK_CSRRS 0x707f #define MATCH_CSRRC 0x3073 #define MASK_CSRRC 0x707f #define MATCH_CSRRWI 0x5073 #define MASK_CSRRWI 0x707f #define MATCH_CSRRSI 0x6073 #define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 #define MASK_CSRRCI 0x707f #define MATCH_FADD_S 0x53 #define MASK_FADD_S 0xfe00007f #define MATCH_FSUB_S 0x8000053 #define MASK_FSUB_S 0xfe00007f #define MATCH_FMUL_S 0x10000053 #define MASK_FMUL_S 0xfe00007f #define MATCH_FDIV_S 0x18000053 #define MASK_FDIV_S 0xfe00007f #define MATCH_FSGNJ_S 0x20000053 #define MASK_FSGNJ_S 0xfe00707f #define MATCH_FSGNJN_S 0x20001053 #define MASK_FSGNJN_S 0xfe00707f #define MATCH_FSGNJX_S 0x20002053 #define MASK_FSGNJX_S 0xfe00707f #define MATCH_FMIN_S 0x28000053 #define MASK_FMIN_S 0xfe00707f #define MATCH_FMAX_S 0x28001053 #define MASK_FMAX_S 0xfe00707f #define MATCH_FSQRT_S 0x58000053 #define MASK_FSQRT_S 0xfff0007f #define MATCH_FADD_D 0x2000053 #define MASK_FADD_D 0xfe00007f #define MATCH_FSUB_D 0xa000053 #define MASK_FSUB_D 0xfe00007f #define MATCH_FMUL_D 0x12000053 #define MASK_FMUL_D 0xfe00007f #define MATCH_FDIV_D 0x1a000053 #define MASK_FDIV_D 0xfe00007f #define MATCH_FSGNJ_D 0x22000053 #define MASK_FSGNJ_D 0xfe00707f #define MATCH_FSGNJN_D 0x22001053 #define MASK_FSGNJN_D 0xfe00707f #define MATCH_FSGNJX_D 0x22002053 #define MASK_FSGNJX_D 0xfe00707f #define MATCH_FMIN_D 0x2a000053 #define MASK_FMIN_D 0xfe00707f #define MATCH_FMAX_D 0x2a001053 #define MASK_FMAX_D 0xfe00707f #define MATCH_FCVT_S_D 0x40100053 #define MASK_FCVT_S_D 0xfff0007f #define MATCH_FCVT_D_S 0x42000053 #define MASK_FCVT_D_S 0xfff0007f #define MATCH_FSQRT_D 0x5a000053 #define MASK_FSQRT_D 0xfff0007f #define MATCH_FADD_Q 0x6000053 #define MASK_FADD_Q 0xfe00007f #define MATCH_FSUB_Q 0xe000053 #define MASK_FSUB_Q 0xfe00007f #define MATCH_FMUL_Q 0x16000053 #define MASK_FMUL_Q 0xfe00007f #define MATCH_FDIV_Q 0x1e000053 #define MASK_FDIV_Q 0xfe00007f #define MATCH_FSGNJ_Q 0x26000053 #define MASK_FSGNJ_Q 0xfe00707f #define MATCH_FSGNJN_Q 0x26001053 #define MASK_FSGNJN_Q 0xfe00707f #define MATCH_FSGNJX_Q 0x26002053 #define MASK_FSGNJX_Q 0xfe00707f #define MATCH_FMIN_Q 0x2e000053 #define MASK_FMIN_Q 0xfe00707f #define MATCH_FMAX_Q 0x2e001053 #define MASK_FMAX_Q 0xfe00707f #define MATCH_FCVT_S_Q 0x40300053 #define MASK_FCVT_S_Q 0xfff0007f #define MATCH_FCVT_Q_S 0x46000053 #define MASK_FCVT_Q_S 0xfff0007f #define MATCH_FCVT_D_Q 0x42300053 #define MASK_FCVT_D_Q 0xfff0007f #define MATCH_FCVT_Q_D 0x46100053 #define MASK_FCVT_Q_D 0xfff0007f #define MATCH_FSQRT_Q 0x5e000053 #define MASK_FSQRT_Q 0xfff0007f #define MATCH_FLE_S 0xa0000053 #define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 #define MASK_FLT_S 0xfe00707f #define MATCH_FEQ_S 0xa0002053 #define MASK_FEQ_S 0xfe00707f #define MATCH_FLE_D 0xa2000053 #define MASK_FLE_D 0xfe00707f #define MATCH_FLT_D 0xa2001053 #define MASK_FLT_D 0xfe00707f #define MATCH_FEQ_D 0xa2002053 #define MASK_FEQ_D 0xfe00707f #define MATCH_FLE_Q 0xa6000053 #define MASK_FLE_Q 0xfe00707f #define MATCH_FLT_Q 0xa6001053 #define MASK_FLT_Q 0xfe00707f #define MATCH_FEQ_Q 0xa6002053 #define MASK_FEQ_Q 0xfe00707f #define MATCH_FCVT_W_S 0xc0000053 #define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 #define MASK_FCVT_WU_S 0xfff0007f #define MATCH_FCVT_L_S 0xc0200053 #define MASK_FCVT_L_S 0xfff0007f #define MATCH_FCVT_LU_S 0xc0300053 #define MASK_FCVT_LU_S 0xfff0007f #define MATCH_FMV_X_W 0xe0000053 #define MASK_FMV_X_W 0xfff0707f #define MATCH_FCLASS_S 0xe0001053 #define MASK_FCLASS_S 0xfff0707f #define MATCH_FCVT_W_D 0xc2000053 #define MASK_FCVT_W_D 0xfff0007f #define MATCH_FCVT_WU_D 0xc2100053 #define MASK_FCVT_WU_D 0xfff0007f #define MATCH_FCVT_L_D 0xc2200053 #define MASK_FCVT_L_D 0xfff0007f #define MATCH_FCVT_LU_D 0xc2300053 #define MASK_FCVT_LU_D 0xfff0007f #define MATCH_FMV_X_D 0xe2000053 #define MASK_FMV_X_D 0xfff0707f #define MATCH_FCLASS_D 0xe2001053 #define MASK_FCLASS_D 0xfff0707f #define MATCH_FCVT_W_Q 0xc6000053 #define MASK_FCVT_W_Q 0xfff0007f #define MATCH_FCVT_WU_Q 0xc6100053 #define MASK_FCVT_WU_Q 0xfff0007f #define MATCH_FCVT_L_Q 0xc6200053 #define MASK_FCVT_L_Q 0xfff0007f #define MATCH_FCVT_LU_Q 0xc6300053 #define MASK_FCVT_LU_Q 0xfff0007f #define MATCH_FMV_X_Q 0xe6000053 #define MASK_FMV_X_Q 0xfff0707f #define MATCH_FCLASS_Q 0xe6001053 #define MASK_FCLASS_Q 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 #define MASK_FCVT_S_WU 0xfff0007f #define MATCH_FCVT_S_L 0xd0200053 #define MASK_FCVT_S_L 0xfff0007f #define MATCH_FCVT_S_LU 0xd0300053 #define MASK_FCVT_S_LU 0xfff0007f #define MATCH_FMV_W_X 0xf0000053 #define MASK_FMV_W_X 0xfff0707f #define MATCH_FCVT_D_W 0xd2000053 #define MASK_FCVT_D_W 0xfff0007f #define MATCH_FCVT_D_WU 0xd2100053 #define MASK_FCVT_D_WU 0xfff0007f #define MATCH_FCVT_D_L 0xd2200053 #define MASK_FCVT_D_L 0xfff0007f #define MATCH_FCVT_D_LU 0xd2300053 #define MASK_FCVT_D_LU 0xfff0007f #define MATCH_FMV_D_X 0xf2000053 #define MASK_FMV_D_X 0xfff0707f #define MATCH_FCVT_Q_W 0xd6000053 #define MASK_FCVT_Q_W 0xfff0007f #define MATCH_FCVT_Q_WU 0xd6100053 #define MASK_FCVT_Q_WU 0xfff0007f #define MATCH_FCVT_Q_L 0xd6200053 #define MASK_FCVT_Q_L 0xfff0007f #define MATCH_FCVT_Q_LU 0xd6300053 #define MASK_FCVT_Q_LU 0xfff0007f #define MATCH_FMV_Q_X 0xf6000053 #define MASK_FMV_Q_X 0xfff0707f #define MATCH_FLW 0x2007 #define MASK_FLW 0x707f #define MATCH_FLD 0x3007 #define MASK_FLD 0x707f #define MATCH_FLQ 0x4007 #define MASK_FLQ 0x707f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f #define MATCH_FSD 0x3027 #define MASK_FSD 0x707f #define MATCH_FSQ 0x4027 #define MASK_FSQ 0x707f #define MATCH_FMADD_S 0x43 #define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 #define MASK_FMSUB_S 0x600007f #define MATCH_FNMSUB_S 0x4b #define MASK_FNMSUB_S 0x600007f #define MATCH_FNMADD_S 0x4f #define MASK_FNMADD_S 0x600007f #define MATCH_FMADD_D 0x2000043 #define MASK_FMADD_D 0x600007f #define MATCH_FMSUB_D 0x2000047 #define MASK_FMSUB_D 0x600007f #define MATCH_FNMSUB_D 0x200004b #define MASK_FNMSUB_D 0x600007f #define MATCH_FNMADD_D 0x200004f #define MASK_FNMADD_D 0x600007f #define MATCH_FMADD_Q 0x6000043 #define MASK_FMADD_Q 0x600007f #define MATCH_FMSUB_Q 0x6000047 #define MASK_FMSUB_Q 0x600007f #define MATCH_FNMSUB_Q 0x600004b #define MASK_FNMSUB_Q 0x600007f #define MATCH_FNMADD_Q 0x600004f #define MASK_FNMADD_Q 0x600007f #define MATCH_C_NOP 0x1 #define MASK_C_NOP 0xffff #define MATCH_C_ADDI16SP 0x6101 #define MASK_C_ADDI16SP 0xef83 #define MATCH_C_JR 0x8002 #define MASK_C_JR 0xf07f #define MATCH_C_JALR 0x9002 #define MASK_C_JALR 0xf07f #define MATCH_C_EBREAK 0x9002 #define MASK_C_EBREAK 0xffff #define MATCH_C_LD 0x6000 #define MASK_C_LD 0xe003 #define MATCH_C_SD 0xe000 #define MASK_C_SD 0xe003 #define MATCH_C_ADDIW 0x2001 #define MASK_C_ADDIW 0xe003 #define MATCH_C_LDSP 0x6002 #define MASK_C_LDSP 0xe003 #define MATCH_C_SDSP 0xe002 #define MASK_C_SDSP 0xe003 #define MATCH_C_ADDI4SPN 0x0 #define MASK_C_ADDI4SPN 0xe003 #define MATCH_C_FLD 0x2000 #define MASK_C_FLD 0xe003 #define MATCH_C_LW 0x4000 #define MASK_C_LW 0xe003 #define MATCH_C_FLW 0x6000 #define MASK_C_FLW 0xe003 #define MATCH_C_FSD 0xa000 #define MASK_C_FSD 0xe003 #define MATCH_C_SW 0xc000 #define MASK_C_SW 0xe003 #define MATCH_C_FSW 0xe000 #define MASK_C_FSW 0xe003 #define MATCH_C_ADDI 0x1 #define MASK_C_ADDI 0xe003 #define MATCH_C_JAL 0x2001 #define MASK_C_JAL 0xe003 #define MATCH_C_LI 0x4001 #define MASK_C_LI 0xe003 #define MATCH_C_LUI 0x6001 #define MASK_C_LUI 0xe003 #define MATCH_C_SRLI 0x8001 #define MASK_C_SRLI 0xec03 #define MATCH_C_SRAI 0x8401 #define MASK_C_SRAI 0xec03 #define MATCH_C_ANDI 0x8801 #define MASK_C_ANDI 0xec03 #define MATCH_C_SUB 0x8c01 #define MASK_C_SUB 0xfc63 #define MATCH_C_XOR 0x8c21 #define MASK_C_XOR 0xfc63 #define MATCH_C_OR 0x8c41 #define MASK_C_OR 0xfc63 #define MATCH_C_AND 0x8c61 #define MASK_C_AND 0xfc63 #define MATCH_C_SUBW 0x9c01 #define MASK_C_SUBW 0xfc63 #define MATCH_C_ADDW 0x9c21 #define MASK_C_ADDW 0xfc63 #define MATCH_C_J 0xa001 #define MASK_C_J 0xe003 #define MATCH_C_BEQZ 0xc001 #define MASK_C_BEQZ 0xe003 #define MATCH_C_BNEZ 0xe001 #define MASK_C_BNEZ 0xe003 #define MATCH_C_SLLI 0x2 #define MASK_C_SLLI 0xe003 #define MATCH_C_FLDSP 0x2002 #define MASK_C_FLDSP 0xe003 #define MATCH_C_LWSP 0x4002 #define MASK_C_LWSP 0xe003 #define MATCH_C_FLWSP 0x6002 #define MASK_C_FLWSP 0xe003 #define MATCH_C_MV 0x8002 #define MASK_C_MV 0xf003 #define MATCH_C_ADD 0x9002 #define MASK_C_ADD 0xf003 #define MATCH_C_FSDSP 0xa002 #define MASK_C_FSDSP 0xe003 #define MATCH_C_SWSP 0xc002 #define MASK_C_SWSP 0xe003 #define MATCH_C_FSWSP 0xe002 #define MASK_C_FSWSP 0xe003 #define MATCH_CUSTOM0 0xb #define MASK_CUSTOM0 0x707f #define MATCH_CUSTOM0_RS1 0x200b #define MASK_CUSTOM0_RS1 0x707f #define MATCH_CUSTOM0_RS1_RS2 0x300b #define MASK_CUSTOM0_RS1_RS2 0x707f #define MATCH_CUSTOM0_RD 0x400b #define MASK_CUSTOM0_RD 0x707f #define MATCH_CUSTOM0_RD_RS1 0x600b #define MASK_CUSTOM0_RD_RS1 0x707f #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b #define MASK_CUSTOM0_RD_RS1_RS2 0x707f #define MATCH_CUSTOM1 0x2b #define MASK_CUSTOM1 0x707f #define MATCH_CUSTOM1_RS1 0x202b #define MASK_CUSTOM1_RS1 0x707f #define MATCH_CUSTOM1_RS1_RS2 0x302b #define MASK_CUSTOM1_RS1_RS2 0x707f #define MATCH_CUSTOM1_RD 0x402b #define MASK_CUSTOM1_RD 0x707f #define MATCH_CUSTOM1_RD_RS1 0x602b #define MASK_CUSTOM1_RD_RS1 0x707f #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b #define MASK_CUSTOM1_RD_RS1_RS2 0x707f #define MATCH_CUSTOM2 0x5b #define MASK_CUSTOM2 0x707f #define MATCH_CUSTOM2_RS1 0x205b #define MASK_CUSTOM2_RS1 0x707f #define MATCH_CUSTOM2_RS1_RS2 0x305b #define MASK_CUSTOM2_RS1_RS2 0x707f #define MATCH_CUSTOM2_RD 0x405b #define MASK_CUSTOM2_RD 0x707f #define MATCH_CUSTOM2_RD_RS1 0x605b #define MASK_CUSTOM2_RD_RS1 0x707f #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b #define MASK_CUSTOM2_RD_RS1_RS2 0x707f #define MATCH_CUSTOM3 0x7b #define MASK_CUSTOM3 0x707f #define MATCH_CUSTOM3_RS1 0x207b #define MASK_CUSTOM3_RS1 0x707f #define MATCH_CUSTOM3_RS1_RS2 0x307b #define MASK_CUSTOM3_RS1_RS2 0x707f #define MATCH_CUSTOM3_RD 0x407b #define MASK_CUSTOM3_RD 0x707f #define MATCH_CUSTOM3_RD_RS1 0x607b #define MASK_CUSTOM3_RD_RS1 0x707f #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b #define MASK_CUSTOM3_RD_RS1_RS2 0x707f #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 #define CSR_HPMCOUNTER3 0xc03 #define CSR_HPMCOUNTER4 0xc04 #define CSR_HPMCOUNTER5 0xc05 #define CSR_HPMCOUNTER6 0xc06 #define CSR_HPMCOUNTER7 0xc07 #define CSR_HPMCOUNTER8 0xc08 #define CSR_HPMCOUNTER9 0xc09 #define CSR_HPMCOUNTER10 0xc0a #define CSR_HPMCOUNTER11 0xc0b #define CSR_HPMCOUNTER12 0xc0c #define CSR_HPMCOUNTER13 0xc0d #define CSR_HPMCOUNTER14 0xc0e #define CSR_HPMCOUNTER15 0xc0f #define CSR_HPMCOUNTER16 0xc10 #define CSR_HPMCOUNTER17 0xc11 #define CSR_HPMCOUNTER18 0xc12 #define CSR_HPMCOUNTER19 0xc13 #define CSR_HPMCOUNTER20 0xc14 #define CSR_HPMCOUNTER21 0xc15 #define CSR_HPMCOUNTER22 0xc16 #define CSR_HPMCOUNTER23 0xc17 #define CSR_HPMCOUNTER24 0xc18 #define CSR_HPMCOUNTER25 0xc19 #define CSR_HPMCOUNTER26 0xc1a #define CSR_HPMCOUNTER27 0xc1b #define CSR_HPMCOUNTER28 0xc1c #define CSR_HPMCOUNTER29 0xc1d #define CSR_HPMCOUNTER30 0xc1e #define CSR_HPMCOUNTER31 0xc1f #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MEDELEG 0x302 #define CSR_MIDELEG 0x303 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG2 0x3a2 #define CSR_PMPCFG3 0x3a3 #define CSR_PMPADDR0 0x3b0 #define CSR_PMPADDR1 0x3b1 #define CSR_PMPADDR2 0x3b2 #define CSR_PMPADDR3 0x3b3 #define CSR_PMPADDR4 0x3b4 #define CSR_PMPADDR5 0x3b5 #define CSR_PMPADDR6 0x3b6 #define CSR_PMPADDR7 0x3b7 #define CSR_PMPADDR8 0x3b8 #define CSR_PMPADDR9 0x3b9 #define CSR_PMPADDR10 0x3ba #define CSR_PMPADDR11 0x3bb #define CSR_PMPADDR12 0x3bc #define CSR_PMPADDR13 0x3bd #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 #define CSR_MCYCLE 0xb00 #define CSR_MINSTRET 0xb02 #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 #define CSR_MHPMCOUNTER5 0xb05 #define CSR_MHPMCOUNTER6 0xb06 #define CSR_MHPMCOUNTER7 0xb07 #define CSR_MHPMCOUNTER8 0xb08 #define CSR_MHPMCOUNTER9 0xb09 #define CSR_MHPMCOUNTER10 0xb0a #define CSR_MHPMCOUNTER11 0xb0b #define CSR_MHPMCOUNTER12 0xb0c #define CSR_MHPMCOUNTER13 0xb0d #define CSR_MHPMCOUNTER14 0xb0e #define CSR_MHPMCOUNTER15 0xb0f #define CSR_MHPMCOUNTER16 0xb10 #define CSR_MHPMCOUNTER17 0xb11 #define CSR_MHPMCOUNTER18 0xb12 #define CSR_MHPMCOUNTER19 0xb13 #define CSR_MHPMCOUNTER20 0xb14 #define CSR_MHPMCOUNTER21 0xb15 #define CSR_MHPMCOUNTER22 0xb16 #define CSR_MHPMCOUNTER23 0xb17 #define CSR_MHPMCOUNTER24 0xb18 #define CSR_MHPMCOUNTER25 0xb19 #define CSR_MHPMCOUNTER26 0xb1a #define CSR_MHPMCOUNTER27 0xb1b #define CSR_MHPMCOUNTER28 0xb1c #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 #define CSR_MHPMEVENT6 0x326 #define CSR_MHPMEVENT7 0x327 #define CSR_MHPMEVENT8 0x328 #define CSR_MHPMEVENT9 0x329 #define CSR_MHPMEVENT10 0x32a #define CSR_MHPMEVENT11 0x32b #define CSR_MHPMEVENT12 0x32c #define CSR_MHPMEVENT13 0x32d #define CSR_MHPMEVENT14 0x32e #define CSR_MHPMEVENT15 0x32f #define CSR_MHPMEVENT16 0x330 #define CSR_MHPMEVENT17 0x331 #define CSR_MHPMEVENT18 0x332 #define CSR_MHPMEVENT19 0x333 #define CSR_MHPMEVENT20 0x334 #define CSR_MHPMEVENT21 0x335 #define CSR_MHPMEVENT22 0x336 #define CSR_MHPMEVENT23 0x337 #define CSR_MHPMEVENT24 0x338 #define CSR_MHPMEVENT25 0x339 #define CSR_MHPMEVENT26 0x33a #define CSR_MHPMEVENT27 0x33b #define CSR_MHPMEVENT28 0x33c #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 #define CSR_HPMCOUNTER3H 0xc83 #define CSR_HPMCOUNTER4H 0xc84 #define CSR_HPMCOUNTER5H 0xc85 #define CSR_HPMCOUNTER6H 0xc86 #define CSR_HPMCOUNTER7H 0xc87 #define CSR_HPMCOUNTER8H 0xc88 #define CSR_HPMCOUNTER9H 0xc89 #define CSR_HPMCOUNTER10H 0xc8a #define CSR_HPMCOUNTER11H 0xc8b #define CSR_HPMCOUNTER12H 0xc8c #define CSR_HPMCOUNTER13H 0xc8d #define CSR_HPMCOUNTER14H 0xc8e #define CSR_HPMCOUNTER15H 0xc8f #define CSR_HPMCOUNTER16H 0xc90 #define CSR_HPMCOUNTER17H 0xc91 #define CSR_HPMCOUNTER18H 0xc92 #define CSR_HPMCOUNTER19H 0xc93 #define CSR_HPMCOUNTER20H 0xc94 #define CSR_HPMCOUNTER21H 0xc95 #define CSR_HPMCOUNTER22H 0xc96 #define CSR_HPMCOUNTER23H 0xc97 #define CSR_HPMCOUNTER24H 0xc98 #define CSR_HPMCOUNTER25H 0xc99 #define CSR_HPMCOUNTER26H 0xc9a #define CSR_HPMCOUNTER27H 0xc9b #define CSR_HPMCOUNTER28H 0xc9c #define CSR_HPMCOUNTER29H 0xc9d #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f #define CSR_MCYCLEH 0xb80 #define CSR_MINSTRETH 0xb82 #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 #define CSR_MHPMCOUNTER6H 0xb86 #define CSR_MHPMCOUNTER7H 0xb87 #define CSR_MHPMCOUNTER8H 0xb88 #define CSR_MHPMCOUNTER9H 0xb89 #define CSR_MHPMCOUNTER10H 0xb8a #define CSR_MHPMCOUNTER11H 0xb8b #define CSR_MHPMCOUNTER12H 0xb8c #define CSR_MHPMCOUNTER13H 0xb8d #define CSR_MHPMCOUNTER14H 0xb8e #define CSR_MHPMCOUNTER15H 0xb8f #define CSR_MHPMCOUNTER16H 0xb90 #define CSR_MHPMCOUNTER17H 0xb91 #define CSR_MHPMCOUNTER18H 0xb92 #define CSR_MHPMCOUNTER19H 0xb93 #define CSR_MHPMCOUNTER20H 0xb94 #define CSR_MHPMCOUNTER21H 0xb95 #define CSR_MHPMCOUNTER22H 0xb96 #define CSR_MHPMCOUNTER23H 0xb97 #define CSR_MHPMCOUNTER24H 0xb98 #define CSR_MHPMCOUNTER25H 0xb99 #define CSR_MHPMCOUNTER26H 0xb9a #define CSR_MHPMCOUNTER27H 0xb9b #define CSR_MHPMCOUNTER28H 0xb9c #define CSR_MHPMCOUNTER29H 0xb9d #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FETCH_ACCESS 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_LOAD_ACCESS 0x5 #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_STORE_ACCESS 0x7 #define CAUSE_USER_ECALL 0x8 #define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd #define CAUSE_STORE_PAGE_FAULT 0xf #endif #ifdef DECLARE_INSN DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) DECLARE_INSN(add, MATCH_ADD, MASK_ADD) DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) DECLARE_INSN(or, MATCH_OR, MASK_OR) DECLARE_INSN(and, MATCH_AND, MASK_AND) DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) DECLARE_INSN(lb, MATCH_LB, MASK_LB) DECLARE_INSN(lh, MATCH_LH, MASK_LH) DECLARE_INSN(lw, MATCH_LW, MASK_LW) DECLARE_INSN(ld, MATCH_LD, MASK_LD) DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) DECLARE_INSN(sb, MATCH_SB, MASK_SB) DECLARE_INSN(sh, MATCH_SH, MASK_SH) DECLARE_INSN(sw, MATCH_SW, MASK_SW) DECLARE_INSN(sd, MATCH_SD, MASK_SD) DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) DECLARE_INSN(div, MATCH_DIV, MASK_DIV) DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) DECLARE_INSN(rem, MATCH_REM, MASK_REM) DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) DECLARE_INSN(uret, MATCH_URET, MASK_URET) DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) #endif #ifdef DECLARE_CSR DECLARE_CSR(fflags, CSR_FFLAGS) DECLARE_CSR(frm, CSR_FRM) DECLARE_CSR(fcsr, CSR_FCSR) DECLARE_CSR(cycle, CSR_CYCLE) DECLARE_CSR(time, CSR_TIME) DECLARE_CSR(instret, CSR_INSTRET) DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) DECLARE_CSR(scounteren, CSR_SCOUNTEREN) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(stval, CSR_STVAL) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mtval, CSR_MTVAL) DECLARE_CSR(mip, CSR_MIP) // DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) // DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) // DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) // DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) // DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) // DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) // DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) // DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) // DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) // DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) // DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) // DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) // DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) // DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) // DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) // DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) // DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) // DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) // DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) // DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) DECLARE_CSR(tselect, CSR_TSELECT) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) DECLARE_CSR(tdata3, CSR_TDATA3) DECLARE_CSR(dcsr, CSR_DCSR) DECLARE_CSR(dpc, CSR_DPC) DECLARE_CSR(dscratch, CSR_DSCRATCH) DECLARE_CSR(mcycle, CSR_MCYCLE) DECLARE_CSR(minstret, CSR_MINSTRET) DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) DECLARE_CSR(mimpid, CSR_MIMPID) DECLARE_CSR(mhartid, CSR_MHARTID) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) DECLARE_CSR(mcycleh, CSR_MCYCLEH) DECLARE_CSR(minstreth, CSR_MINSTRETH) DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) #endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) #endif
// See LICENSE for license details. #include "processor.h" #include "mmu.h" #include <cassert> static void commit_log_stash_privilege(processor_t* p) { #ifdef RISCV_ENABLE_COMMITLOG state_t* state = p->get_state(); state->last_inst_priv = state->prv; state->last_inst_xlen = p->get_xlen(); state->last_inst_flen = p->get_flen(); #endif } static void commit_log_print_value(int width, uint64_t hi, uint64_t lo) { switch (width) { case 16: fprintf(stderr, "0x%04" PRIx16, (uint16_t)lo); break; case 32: fprintf(stderr, "0x%08" PRIx32, (uint32_t)lo); break; case 64: fprintf(stderr, "0x%016" PRIx64, lo); break; case 128: fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64, hi, lo); break; default: abort(); } } static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn) { #ifdef RISCV_ENABLE_COMMITLOG auto& reg = state->log_reg_write; int priv = state->last_inst_priv; int xlen = state->last_inst_xlen; int flen = state->last_inst_flen; state->last_insn = insn.bits(); if (reg.addr) { bool fp = reg.addr & 1; int rd = reg.addr >> 1; int size = fp ? flen : xlen; } #endif } inline void processor_t::update_histogram(reg_t pc) { #ifdef RISCV_ENABLE_HISTOGRAM pc_histogram[pc]++; #endif } // This is expected to be inlined by the compiler so each use of execute_insn // includes a duplicated body of the function to get separate fetch.func // function calls. static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { commit_log_stash_privilege(p); reg_t npc = fetch.func(p, fetch.insn, pc); if (npc != PC_SERIALIZE_BEFORE) { commit_log_print_insn(p->get_state(), pc, fetch.insn); p->update_histogram(pc); } return npc; } bool processor_t::slow_path() { return debug \|\| state.single_step != state.STEP_NONE \|\| state.dcsr.cause; } // fetch/decode/execute loop void processor_t::step(size_t n) { #ifdef RISCV_ENABLE_COMMITLOG state.was_exception = false; #endif if (state.dcsr.cause == DCSR_CAUSE_NONE) { if (halt_request) { enter_debug_mode(DCSR_CAUSE_DEBUGINT); } // !!!The halt bit in DCSR is deprecated. else if (state.dcsr.halt) { enter_debug_mode(DCSR_CAUSE_HALT); } } while (n > 0) { size_t instret = 0; reg_t pc = state.pc; mmu_t* _mmu = mmu; #define advance_pc() \ if (unlikely(invalid_pc(pc))) { \ switch (pc) { \ case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ case PC_SERIALIZE_AFTER: ++instret; break; \ case PC_SERIALIZE_WFI: n = ++instret; break; \ default: abort(); \ } \ pc = state.pc; \ break; \ } else { \ state.pc = pc; \ instret++; \ } try { insn_fetch_t fetch = mmu->load_insn(pc); // check whether the instruction is an AMO, we dpn't take interrupts on AMOs if (likely((fetch.insn.bits() & 0x2f) != 0x2f)) { take_pending_interrupt(); } if (unlikely(slow_path())) { while (instret < n) { if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) { state.single_step = state.STEP_NONE; if (state.dcsr.cause == DCSR_CAUSE_NONE) { enter_debug_mode(DCSR_CAUSE_STEP); // enter_debug_mode changed state.pc, so we can't just continue. break; } } if (unlikely(state.single_step == state.STEP_STEPPING)) { state.single_step = state.STEP_STEPPED; } if (debug && !state.serialized) disasm(fetch.insn); pc = execute_insn(this, pc, fetch); advance_pc(); if (unlikely(state.pc >= DEBUG_ROM_ENTRY && state.pc < DEBUG_END)) { // We're waiting for the debugger to tell us something. return; } } } else while (instret < n) { // This code uses a modified Duff's Device to improve the performance // of executing instructions. While typical Duff's Devices are used // for software pipelining, the switch statement below primarily // benefits from separate call points for the fetch.func function call // found in each execute_insn. This function call is an indirect jump // that depends on the current instruction. By having an indirect jump // dedicated for each icache entry, you improve the performance of the // host's next address predictor. Each case in the switch statement // allows for the program flow to contine to the next case if it // corresponds to the next instruction in the program and instret is // still less than n. // // According to Andrew Waterman's recollection, this optimization // resulted in approximately a 2x performance increase. // This figures out where to jump to in the switch statement size_t idx = _mmu->icache_index(pc); // This gets the cached decoded instruction from the MMU. If the MMU // does not have the current pc cached, it will refill the MMU and // return the correct entry. ic_entry->data.func is the C++ function // corresponding to the instruction. auto ic_entry = _mmu->access_icache(pc); // This macro is included in "icache.h" included within the switch // statement below. The indirect jump corresponding to the instruction // is located within the execute_insn() function call. #define ICACHE_ACCESS(i) { \ insn_fetch_t fetch = ic_entry->data; \ pc = execute_insn(this, pc, fetch); \ ic_entry = ic_entry->next; \ if (i == mmu_t::ICACHE_ENTRIES-1) break; \ if (unlikely(ic_entry->tag != pc)) break; \ if (unlikely(instret+1 == n)) break; \ instret++; \ state.pc = pc; \ } // This switch statement implements the modified Duff's device as // explained above. switch (idx) { // "icache.h" is generated by the gen_icache script #include "icache.h" } advance_pc(); } } catch(trap_t& t) { #ifdef RISCV_ENABLE_COMMITLOG state.was_exception = true; #endif take_trap(t, pc); n = instret; if (unlikely(state.single_step == state.STEP_STEPPED)) { state.single_step = state.STEP_NONE; enter_debug_mode(DCSR_CAUSE_STEP); } } catch (trigger_matched_t& t) { if (mmu->matched_trigger) { // This exception came from the MMU. That means the instruction hasn't // fully executed yet. We start it again, but this time it won't throw // an exception because matched_trigger is already set. (All memory // instructions are idempotent so restarting is safe.) insn_fetch_t fetch = mmu->load_insn(pc); pc = execute_insn(this, pc, fetch); advance_pc(); delete mmu->matched_trigger; mmu->matched_trigger = NULL; } switch (state.mcontrol[t.index].action) { case ACTION_DEBUG_MODE: enter_debug_mode(DCSR_CAUSE_HWBP); break; case ACTION_DEBUG_EXCEPTION: { mem_trap_t trap(CAUSE_BREAKPOINT, t.address); take_trap(trap, pc); break; } default: abort(); } } state.minstret += instret; n -= instret; } }
// See LICENSE for license details. #include "extension.h" #include "trap.h" extension_t::~extension_t() { } void extension_t::illegal_instruction() { throw trap_illegal_instruction(0); } void extension_t::raise_interrupt() { p->take_interrupt((reg_t)1 << IRQ_COP); // must not return throw std::logic_error("a COP exception was posted, but interrupts are disabled!"); } void extension_t::clear_interrupt() { }
// See LICENSE for license details. #ifndef _RISCV_COPROCESSOR_H #define _RISCV_COPROCESSOR_H #include "processor.h" #include "disasm.h" #include <vector> #include <functional> class extension_t { public: virtual std::vector<insn_desc_t> get_instructions() = 0; virtual std::vector<disasm_insn_t> get_disasms() = 0; virtual const char name() = 0; virtual void reset() {}; virtual void set_debug(bool value) {}; virtual ~extension_t(); void set_processor(processor_t* _p) { p = _p; } protected: processor_t* p; void illegal_instruction(); void raise_interrupt(); void clear_interrupt(); }; std::function<extension_t()> find_extension(const char name); void register_extension(const char* name, std::function<extension_t*()> f); #define REGISTER_EXTENSION(name, constructor) \ class register_##name { \ public: register_##name() { register_extension(#name, constructor); } \ }; static register_##name dummy_##name; #endif
// See LICENSE for license details. #include "extension.h" #include <string> #include <map> #include <dlfcn.h> static std::map<std::string, std::function<extension_t()>>& extensions() { static std::map<std::string, std::function<extension_t()>> v; return v; } void register_extension(const char* name, std::function<extension_t()> f) { extensions()[name] = f; } std::function<extension_t()> find_extension(const char* name) { if (!extensions().count(name)) { // try to find extension xyz by loading libxyz.so std::string libname = std::string("lib") + name + ".so"; if (!dlopen(libname.c_str(), RTLD_LAZY)) { fprintf(stderr, "couldn't find extension '%s' (or library '%s')\n", name, libname.c_str()); exit(-1); } if (!extensions().count(name)) { fprintf(stderr, "couldn't find extension '%s' in shared library '%s'\n", name, libname.c_str()); exit(-1); } } return extensions()[name]; }
#!/bin/sh n=$(($1-1)) for i in `seq 0 $n` do echo case $i: ICACHE_ACCESS\($i\)\; done echo
// See LICENSE for license details. #include "insn_template.h" reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) { int xlen = 32; reg_t npc = sext_xlen(pc + insn_length(OPCODE)); #include "insns/NAME.h" trace_opcode(p, OPCODE, insn); return npc; } reg_t rv64_NAME(processor_t* p, insn_t insn, reg_t pc) { int xlen = 64; reg_t npc = sext_xlen(pc + insn_length(OPCODE)); #include "insns/NAME.h" trace_opcode(p, OPCODE, insn); return npc; }
// See LICENSE for license details. #include "mmu.h" #include "mulhi.h" #include "softfloat.h" #include "internals.h" #include "specialize.h" #include "tracer.h" #include <assert.h>
// See LICENSE for license details. #include "decode.h" #include "disasm.h" #include "sim.h" #include "mmu.h" #include <sys/mman.h> #include <termios.h> #include <map> #include <iostream> #include <climits> #include <cinttypes> #include <assert.h> #include <stdlib.h> #include <unistd.h> #include <sstream> #include <string> #include <vector> #include <algorithm> #include <math.h> DECLARE_TRAP(-1, interactive) processor_t sim_t::get_core(const std::string& i) { char ptr; unsigned long p = strtoul(i.c_str(), &ptr, 10); if (ptr \|\| p >= procs.size()) throw trap_interactive(); return get_core(p); } static std::string readline(int fd) { struct termios tios; bool noncanonical = tcgetattr(fd, &tios) == 0 && (tios.c_lflag & ICANON) == 0; std::string s; for (char ch; read(fd, &ch, 1) == 1; ) { if (ch == '\x7f') { if (s.empty()) continue; s.erase(s.end()-1); if (noncanonical && write(fd, "\b \b", 3) != 3) ; // shut up gcc } else if (noncanonical && write(fd, &ch, 1) != 1) ; // shut up gcc if (ch == '\n') break; if (ch != '\x7f') s += ch; } return s; } void sim_t::interactive() { typedef void (sim_t::interactive_func)(const std::string&, const std::vector<std::string>&); std::map<std::string,interactive_func> funcs; funcs["run"] = &sim_t::interactive_run_noisy; funcs["r"] = funcs["run"]; funcs["rs"] = &sim_t::interactive_run_silent; funcs["reg"] = &sim_t::interactive_reg; funcs["freg"] = &sim_t::interactive_freg; funcs["fregs"] = &sim_t::interactive_fregs; funcs["fregd"] = &sim_t::interactive_fregd; funcs["pc"] = &sim_t::interactive_pc; funcs["mem"] = &sim_t::interactive_mem; funcs["str"] = &sim_t::interactive_str; funcs["until"] = &sim_t::interactive_until_silent; funcs["untiln"] = &sim_t::interactive_until_noisy; funcs["while"] = &sim_t::interactive_until_silent; funcs["quit"] = &sim_t::interactive_quit; funcs["q"] = funcs["quit"]; funcs["help"] = &sim_t::interactive_help; funcs["h"] = funcs["help"]; while (!done()) { std::cerr << ": " << std::flush; std::string s = readline(2); std::stringstream ss(s); std::string cmd, tmp; std::vector<std::string> args; if (!(ss >> cmd)) { set_procs_debug(true); step(1); continue; } while (ss >> tmp) args.push_back(tmp); try { if(funcs.count(cmd)) (this->funcs[cmd])(cmd, args); else fprintf(stderr, "Unknown command %s\n", cmd.c_str()); } catch(trap_t t) {} } ctrlc_pressed = false; } void sim_t::interactive_help(const std::string& cmd, const std::vector<std::string>& args) { std::cerr << "Interactive commands:\n" "reg <core> [reg] # Display [reg] (all if omitted) in <core>\n" "fregs <core> <reg> # Display single precision <reg> in <core>\n" "fregd <core> <reg> # Display double precision <reg> in <core>\n" "pc <core> # Show current PC in <core>\n" "mem <hex addr> # Show contents of physical memory\n" "str <hex addr> # Show NUL-terminated C string\n" "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n" "until pc <core> <val> # Stop when PC in <core> hits <val>\n" "untiln pc <core> <val> # Run noisy and stop when PC in <core> hits <val>\n" "until mem <addr> <val> # Stop when memory <addr> becomes <val>\n" "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n" "while pc <core> <val> # Run while PC in <core> is <val>\n" "while mem <addr> <val> # Run while memory <addr> is <val>\n" "run [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n" "r [count] Alias for run\n" "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n" "quit # End the simulation\n" "q Alias for quit\n" "help # This screen!\n" "h Alias for help\n" "Note: Hitting enter is the same as: run 1\n" << std::flush; } void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args) { interactive_run(cmd,args,true); } void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args) { interactive_run(cmd,args,false); } void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy) { size_t steps = args.size() ? atoll(args[0].c_str()) : -1; ctrlc_pressed = false; set_procs_debug(noisy); for (size_t i = 0; i < steps && !ctrlc_pressed && !done(); i++) step(1); } void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args) { exit(0); } reg_t sim_t::get_pc(const std::vector<std::string>& args) { if(args.size() != 1) throw trap_interactive(); processor_t p = get_core(args[0]); return p->get_state()->pc; } void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args) { fprintf(stderr, "0x%016" PRIx64 "\n", get_pc(args)); } reg_t sim_t::get_reg(const std::vector<std::string>& args) { if(args.size() != 2) throw trap_interactive(); processor_t p = get_core(args[0]); unsigned long r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name; if (r == NXPR) { char ptr; r = strtoul(args[1].c_str(), &ptr, 10); if (ptr) { #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number); #include "encoding.h" // generates if's for all csrs r = NXPR; // else case (csr name not found) #undef DECLARE_CSR } } if (r >= NXPR) throw trap_interactive(); return p->get_state()->XPR[r]; } freg_t sim_t::get_freg(const std::vector<std::string>& args) { if(args.size() != 2) throw trap_interactive(); processor_t p = get_core(args[0]); int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name; if (r == NFPR) r = atoi(args[1].c_str()); if (r >= NFPR) throw trap_interactive(); return p->get_state()->FPR[r]; } void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { if (args.size() == 1) { // Show all the regs! processor_t p = get_core(args[0]); for (int r = 0; r < NXPR; ++r) { fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->get_state()->XPR[r]); if ((r + 1) % 4 == 0) fprintf(stderr, "\n"); } } else fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args)); } union fpr { freg_t r; float s; double d; }; void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args) { freg_t r = get_freg(args); fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]); } void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args) { fpr f; f.r = get_freg(args); fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN); } void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args) { fpr f; f.r = get_freg(args); fprintf(stderr, "%g\n", isBoxedF64(f.r) ? f.d : NAN); } reg_t sim_t::get_mem(const std::vector<std::string>& args) { if(args.size() != 1 && args.size() != 2) throw trap_interactive(); std::string addr_str = args[0]; mmu_t mmu = debug_mmu; if(args.size() == 2) { processor_t p = get_core(args[0]); mmu = p->get_mmu(); addr_str = args[1]; } reg_t addr = strtol(addr_str.c_str(),NULL,16), val; if(addr == LONG_MAX) addr = strtoul(addr_str.c_str(),NULL,16); switch(addr % 8) { case 0: val = mmu->load_uint64(addr); break; case 4: val = mmu->load_uint32(addr); break; case 2: case 6: val = mmu->load_uint16(addr); break; default: val = mmu->load_uint8(addr); break; } return val; } void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args) { fprintf(stderr, "0x%016" PRIx64 "\n", get_mem(args)); } void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) { if(args.size() != 1) throw trap_interactive(); reg_t addr = strtol(args[0].c_str(),NULL,16); char ch; while((ch = debug_mmu->load_uint8(addr++))) putchar(ch); putchar('\n'); } void sim_t::interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args) { interactive_until(cmd, args, false); } void sim_t::interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args) { interactive_until(cmd, args, true); } void sim_t::interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy) { bool cmd_until = cmd == "until" \|\| cmd == "untiln"; if(args.size() < 3) return; reg_t val = strtol(args[args.size()-1].c_str(),NULL,16); if(val == LONG_MAX) val = strtoul(args[args.size()-1].c_str(),NULL,16); std::vector<std::string> args2; args2 = std::vector<std::string>(args.begin()+1,args.end()-1); auto func = args[0] == "reg" ? &sim_t::get_reg : args[0] == "pc" ? &sim_t::get_pc : args[0] == "mem" ? &sim_t::get_mem : NULL; if (func == NULL) return; ctrlc_pressed = false; while (1) { try { reg_t current = (this->func)(args2); if (cmd_until == (current == val)) break; if (ctrlc_pressed) break; } catch (trap_t t) {} set_procs_debug(noisy); step(1); } }
#include <stdio.h> #include "decode.h" #include "jtag_dtm.h" #include "debug_module.h" #include "debug_defines.h" #if 0 # define D(x) x #else # define D(x) #endif enum { IR_IDCODE=1, IR_DTMCONTROL=0x10, IR_DBUS=0x11, IR_RESET=0x1c }; #define DTMCONTROL_VERSION 0xf #define DTMCONTROL_ABITS (0x3f << 4) #define DTMCONTROL_DBUSSTAT (3<<10) #define DTMCONTROL_IDLE (7<<12) #define DTMCONTROL_DBUSRESET (1<<16) #define DMI_OP 3 #define DMI_DATA (0xffffffffL<<2) #define DMI_ADDRESS ((1L<<(abits+34)) - (1L<<34)) #define DMI_OP_STATUS_SUCCESS 0 #define DMI_OP_STATUS_RESERVED 1 #define DMI_OP_STATUS_FAILED 2 #define DMI_OP_STATUS_BUSY 3 #define DMI_OP_NOP 0 #define DMI_OP_READ 1 #define DMI_OP_WRITE 2 #define DMI_OP_RESERVED 3 jtag_dtm_t::jtag_dtm_t(debug_module_t dm) : dm(dm), _tck(false), _tms(false), _tdi(false), _tdo(false), dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) \| 1), dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET), _state(TEST_LOGIC_RESET) { } void jtag_dtm_t::reset() { _state = TEST_LOGIC_RESET; } void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) { const jtag_state_t next[16][2] = { / TEST_LOGIC_RESET / { RUN_TEST_IDLE, TEST_LOGIC_RESET }, / RUN_TEST_IDLE / { RUN_TEST_IDLE, SELECT_DR_SCAN }, / SELECT_DR_SCAN / { CAPTURE_DR, SELECT_IR_SCAN }, / CAPTURE_DR / { SHIFT_DR, EXIT1_DR }, / SHIFT_DR / { SHIFT_DR, EXIT1_DR }, / EXIT1_DR / { PAUSE_DR, UPDATE_DR }, / PAUSE_DR / { PAUSE_DR, EXIT2_DR }, / EXIT2_DR / { SHIFT_DR, UPDATE_DR }, / UPDATE_DR / { RUN_TEST_IDLE, SELECT_DR_SCAN }, / SELECT_IR_SCAN / { CAPTURE_IR, TEST_LOGIC_RESET }, / CAPTURE_IR / { SHIFT_IR, EXIT1_IR }, / SHIFT_IR / { SHIFT_IR, EXIT1_IR }, / EXIT1_IR / { PAUSE_IR, UPDATE_IR }, / PAUSE_IR / { PAUSE_IR, EXIT2_IR }, / EXIT2_IR / { SHIFT_IR, UPDATE_IR }, / UPDATE_IR */ { RUN_TEST_IDLE, SELECT_DR_SCAN } }; if (!_tck && tck) { // Positive clock edge. switch (_state) { case SHIFT_DR: dr >>= 1; dr \|= (uint64_t) _tdi << (dr_length-1); break; case SHIFT_IR: ir >>= 1; ir \|= _tdi << (ir_length-1); break; default: break; } _state = next[_state][_tms]; switch (_state) { case TEST_LOGIC_RESET: ir = IR_IDCODE; break; case CAPTURE_DR: capture_dr(); break; case SHIFT_DR: _tdo = dr & 1; break; case UPDATE_DR: update_dr(); break; case CAPTURE_IR: break; case SHIFT_IR: _tdo = ir & 1; break; //case UPDATE_IR: //if (ir == IR_RESET) { // Make a reset happen //} //break; default: break; } } D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, " "dr=0x%lx\n", _state, _tdi, _tdo, _tms, _tck, ir, dr)); _tck = tck; _tms = tms; _tdi = tdi; } void jtag_dtm_t::capture_dr() { switch (ir) { case IR_IDCODE: dr = idcode; dr_length = 32; break; case IR_DTMCONTROL: dr = dtmcontrol; dr_length = 32; break; case IR_DBUS: dr = dmi; dr_length = abits + 34; break; default: D(fprintf(stderr, "Unsupported IR: 0x%x\n", ir)); break; } D(fprintf(stderr, "Capture DR; IR=0x%x, DR=0x%lx (%d bits)\n", ir, dr, dr_length)); } void jtag_dtm_t::update_dr() { D(fprintf(stderr, "Update DR; IR=0x%x, DR=0x%lx (%d bits)\n", ir, dr, dr_length)); switch (ir) { case IR_DBUS: { unsigned op = get_field(dr, DMI_OP); uint32_t data = get_field(dr, DMI_DATA); unsigned address = get_field(dr, DMI_ADDRESS); dmi = dr; bool success = true; if (op == DMI_OP_READ) { uint32_t value; if (dm->dmi_read(address, &value)) { dmi = set_field(dmi, DMI_DATA, value); } else { success = false; } } else if (op == DMI_OP_WRITE) { success = dm->dmi_write(address, data); } if (success) { dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_SUCCESS); } else { dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_FAILED); } D(fprintf(stderr, "dmi=0x%lx\n", dmi)); } break; } }
#ifndef JTAG_DTM_H #define JTAG_DTM_H #include <stdint.h> class debug_module_t; typedef enum { TEST_LOGIC_RESET, RUN_TEST_IDLE, SELECT_DR_SCAN, CAPTURE_DR, SHIFT_DR, EXIT1_DR, PAUSE_DR, EXIT2_DR, UPDATE_DR, SELECT_IR_SCAN, CAPTURE_IR, SHIFT_IR, EXIT1_IR, PAUSE_IR, EXIT2_IR, UPDATE_IR } jtag_state_t; class jtag_dtm_t { static const unsigned idcode = 0xdeadbeef; public: jtag_dtm_t(debug_module_t dm); void reset(); void set_pins(bool tck, bool tms, bool tdi); bool tdo() const { return _tdo; } jtag_state_t state() const { return _state; } private: debug_module_t dm; bool _tck, _tms, _tdi, _tdo; uint32_t ir; const unsigned ir_length = 5; uint64_t dr; unsigned dr_length; // abits must come before dtmcontrol so it can easily be used in the // constructor. const unsigned abits = 6; uint32_t dtmcontrol; uint64_t dmi; jtag_state_t _state; void capture_dr(); void update_dr(); }; #endif
// See LICENSE for license details. #ifndef _MEMTRACER_H #define _MEMTRACER_H #include <cstdint> #include <string.h> #include <vector> enum access_type { LOAD, STORE, FETCH, }; class memtracer_t { public: memtracer_t() {} virtual ~memtracer_t() {} virtual bool interested_in_range(uint64_t begin, uint64_t end, access_type type) = 0; virtual void trace(uint64_t addr, size_t bytes, access_type type) = 0; }; class memtracer_list_t : public memtracer_t { public: bool empty() { return list.empty(); } bool interested_in_range(uint64_t begin, uint64_t end, access_type type) { for (std::vector<memtracer_t>::iterator it = list.begin(); it != list.end(); ++it) if ((it)->interested_in_range(begin, end, type)) return true; return false; } void trace(uint64_t addr, size_t bytes, access_type type) { for (std::vector<memtracer_t>::iterator it = list.begin(); it != list.end(); ++it) (it)->trace(addr, bytes, type); } void hook(memtracer_t* h) { list.push_back(h); } private: std::vector<memtracer_t*> list; }; #endif
// See LICENSE for license details. #include "mmu.h" #include "simif.h" #include "processor.h" mmu_t::mmu_t(simif_t* sim, processor_t* proc) : sim(sim), proc(proc), check_triggers_fetch(false), check_triggers_load(false), check_triggers_store(false), matched_trigger(NULL) { flush_tlb(); yield_load_reservation(); } mmu_t::~mmu_t() { } void mmu_t::flush_icache() { for (size_t i = 0; i < ICACHE_ENTRIES; i++) icache[i].tag = -1; } void mmu_t::flush_tlb() { memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag)); memset(tlb_load_tag, -1, sizeof(tlb_load_tag)); memset(tlb_store_tag, -1, sizeof(tlb_store_tag)); flush_icache(); } static void throw_access_exception(reg_t addr, access_type type) { switch (type) { case FETCH: throw trap_instruction_access_fault(addr); case LOAD: throw trap_load_access_fault(addr); case STORE: throw trap_store_access_fault(addr); default: abort(); } } reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type) { if (!proc) return addr; reg_t mode = proc->state.prv; if (type != FETCH) { if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV)) mode = get_field(proc->state.mstatus, MSTATUS_MPP); } reg_t paddr = walk(addr, type, mode) \| (addr & (PGSIZE-1)); if (!pmp_ok(paddr, type, mode) \|\| !pmp_homogeneous(paddr, len)) throw_access_exception(addr, type); return paddr; } tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr) { reg_t paddr = translate(vaddr, sizeof(fetch_temp), FETCH); if (auto host_addr = sim->addr_to_mem(paddr)) { return refill_tlb(vaddr, paddr, host_addr, FETCH); } else { if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t)&fetch_temp)) throw trap_instruction_access_fault(vaddr); tlb_entry_t entry = {(char)&fetch_temp - vaddr, paddr - vaddr}; return entry; } } reg_t reg_from_bytes(size_t len, const uint8_t* bytes) { switch (len) { case 1: return bytes[0]; case 2: return bytes[0] \| (((reg_t) bytes[1]) << 8); case 4: return bytes[0] \| (((reg_t) bytes[1]) << 8) \| (((reg_t) bytes[2]) << 16) \| (((reg_t) bytes[3]) << 24); case 8: return bytes[0] \| (((reg_t) bytes[1]) << 8) \| (((reg_t) bytes[2]) << 16) \| (((reg_t) bytes[3]) << 24) \| (((reg_t) bytes[4]) << 32) \| (((reg_t) bytes[5]) << 40) \| (((reg_t) bytes[6]) << 48) \| (((reg_t) bytes[7]) << 56); } abort(); } void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes) { reg_t paddr = translate(addr, len, LOAD); if (auto host_addr = sim->addr_to_mem(paddr)) { memcpy(bytes, host_addr, len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.trace(paddr, len, LOAD); else refill_tlb(addr, paddr, host_addr, LOAD); } else if (!sim->mmio_load(paddr, len, bytes)) { throw trap_load_access_fault(addr); } if (!matched_trigger) { reg_t data = reg_from_bytes(len, bytes); matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); if (matched_trigger) throw matched_trigger; } } void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t bytes) { reg_t paddr = translate(addr, len, STORE); if (!matched_trigger) { reg_t data = reg_from_bytes(len, bytes); matched_trigger = trigger_exception(OPERATION_STORE, addr, data); if (matched_trigger) throw matched_trigger; } if (auto host_addr = sim->addr_to_mem(paddr)) { memcpy(host_addr, bytes, len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE)) tracer.trace(paddr, len, STORE); else refill_tlb(addr, paddr, host_addr, STORE); } else if (!sim->mmio_store(paddr, len, bytes)) { throw trap_store_access_fault(addr); } } tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char host_addr, access_type type) { reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES; reg_t expected_tag = vaddr >> PGSHIFT; if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_load_tag[idx] = -1; if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_store_tag[idx] = -1; if ((tlb_insn_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_insn_tag[idx] = -1; if ((check_triggers_fetch && type == FETCH) \|\| (check_triggers_load && type == LOAD) \|\| (check_triggers_store && type == STORE)) expected_tag \|= TLB_CHECK_TRIGGERS; if (pmp_homogeneous(paddr & ~reg_t(PGSIZE - 1), PGSIZE)) { if (type == FETCH) tlb_insn_tag[idx] = expected_tag; else if (type == STORE) tlb_store_tag[idx] = expected_tag; else tlb_load_tag[idx] = expected_tag; } tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; tlb_data[idx] = entry; return entry; } reg_t mmu_t::pmp_ok(reg_t addr, access_type type, reg_t mode) { if (!proc) return true; reg_t base = 0; for (size_t i = 0; i < proc->state.n_pmp; i++) { reg_t tor = proc->state.pmpaddr[i] << PMP_SHIFT; uint8_t cfg = proc->state.pmpcfg[i]; if (cfg & PMP_A) { bool is_tor = (cfg & PMP_A) == PMP_TOR; bool is_na4 = (cfg & PMP_A) == PMP_NA4; reg_t mask = (proc->state.pmpaddr[i] << 1) \| (!is_na4); mask = ~(mask & ~(mask + 1)) << PMP_SHIFT; bool napot_match = ((addr ^ tor) & mask) == 0; bool tor_match = base <= addr && addr < tor; if (is_tor ? tor_match : napot_match) { return (mode == PRV_M && !(cfg & PMP_L)) \|\| (type == LOAD && (cfg & PMP_R)) \|\| (type == STORE && (cfg & PMP_W)) \|\| (type == FETCH && (cfg & PMP_X)); } } base = tor; } return mode == PRV_M; } reg_t mmu_t::pmp_homogeneous(reg_t addr, reg_t len) { if ((addr \| len) & (len - 1)) abort(); if (!proc) return true; reg_t base = 0; for (size_t i = 0; i < proc->state.n_pmp; i++) { reg_t tor = proc->state.pmpaddr[i] << PMP_SHIFT; uint8_t cfg = proc->state.pmpcfg[i]; if (cfg & PMP_A) { bool is_tor = (cfg & PMP_A) == PMP_TOR; bool is_na4 = (cfg & PMP_A) == PMP_NA4; bool begins_after_lower = addr >= base; bool begins_after_upper = addr >= tor; bool ends_before_lower = (addr & -len) < (base & -len); bool ends_before_upper = (addr & -len) < (tor & -len); bool tor_homogeneous = ends_before_lower \|\| begins_after_upper \|\| (begins_after_lower && ends_before_upper); reg_t mask = (proc->state.pmpaddr[i] << 1) \| (!is_na4); mask = ~(mask & ~(mask + 1)) << PMP_SHIFT; bool mask_homogeneous = ~(mask << 1) & len; bool napot_homogeneous = mask_homogeneous \|\| ((addr ^ tor) / len) != 0; if (!(is_tor ? tor_homogeneous : napot_homogeneous)) return false; } base = tor; } return true; } reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) { vm_info vm = decode_vm_info(proc->max_xlen, mode, proc->get_state()->satp); if (vm.levels == 0) return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen bool s_mode = mode == PRV_S; bool sum = get_field(proc->state.mstatus, MSTATUS_SUM); bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR); // verify bits xlen-1:va_bits-1 are all equal int va_bits = PGSHIFT + vm.levels * vm.idxbits; reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1; reg_t masked_msbs = (addr >> (va_bits-1)) & mask; if (masked_msbs != 0 && masked_msbs != mask) vm.levels = 0; reg_t base = vm.ptbase; for (int i = vm.levels - 1; i >= 0; i--) { int ptshift = i * vm.idxbits; reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << vm.idxbits) - 1); // check that physical address of PTE is legal auto pte_paddr = base + idx * vm.ptesize; auto ppte = sim->addr_to_mem(pte_paddr); if (!ppte \|\| !pmp_ok(pte_paddr, LOAD, PRV_S)) throw_access_exception(addr, type); reg_t pte = vm.ptesize == 4 ? (uint32_t)ppte : (uint64_t)ppte; reg_t ppn = pte >> PTE_PPN_SHIFT; if (PTE_TABLE(pte)) { // next level of page table base = ppn << PGSHIFT; } else if ((pte & PTE_U) ? s_mode && (type == FETCH \|\| !sum) : !s_mode) { break; } else if (!(pte & PTE_V) \|\| (!(pte & PTE_R) && (pte & PTE_W))) { break; } else if (type == FETCH ? !(pte & PTE_X) : type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_W))) { break; } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { break; } else { reg_t ad = PTE_A \| ((type == STORE) * PTE_D); #ifdef RISCV_ENABLE_DIRTY // set accessed and possibly dirty bits. if ((pte & ad) != ad) { if (!pmp_ok(pte_paddr, STORE, PRV_S)) throw_access_exception(addr, type); (uint32_t)ppte \|= ad; } #else // take exception if access or possibly dirty bit is not set. if ((pte & ad) != ad) break; #endif // for superpage mappings, make a fake leaf PTE for the TLB's benefit. reg_t vpn = addr >> PGSHIFT; reg_t value = (ppn \| (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT; return value; } } switch (type) { case FETCH: throw trap_instruction_page_fault(addr); case LOAD: throw trap_load_page_fault(addr); case STORE: throw trap_store_page_fault(addr); default: abort(); } } void mmu_t::register_memtracer(memtracer_t* t) { flush_tlb(); tracer.hook(t); }
// See LICENSE for license details. #ifndef _RISCV_MMU_H #define _RISCV_MMU_H #include "decode.h" #include "trap.h" #include "common.h" #include "config.h" #include "simif.h" #include "processor.h" #include "memtracer.h" #include <stdlib.h> #include <vector> // virtual memory configuration #define PGSHIFT 12 const reg_t PGSIZE = 1 << PGSHIFT; const reg_t PGMASK = ~(PGSIZE-1); struct insn_fetch_t { insn_func_t func; insn_t insn; }; struct icache_entry_t { reg_t tag; struct icache_entry_t* next; insn_fetch_t data; }; struct tlb_entry_t { char* host_offset; reg_t target_offset; }; class trigger_matched_t { public: trigger_matched_t(int index, trigger_operation_t operation, reg_t address, reg_t data) : index(index), operation(operation), address(address), data(data) {} int index; trigger_operation_t operation; reg_t address; reg_t data; }; // this class implements a processor's port into the virtual memory system. // an MMU and instruction cache are maintained for simulator performance. class mmu_t { public: mmu_t(simif_t* sim, processor_t* proc); ~mmu_t(); inline reg_t misaligned_load(reg_t addr, size_t size) { #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; for (size_t i = 0; i < size; i++) res += (reg_t)load_uint8(addr + i) << (i * 8); return res; #else throw trap_load_address_misaligned(addr); #endif } inline void misaligned_store(reg_t addr, reg_t data, size_t size) { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) store_uint8(addr + i, data >> (i * 8)); #else throw trap_store_address_misaligned(addr); #endif } // template for functions that load an aligned value from memory #define load_func(type) \ inline type##_t load_##type(reg_t addr) { \ if (unlikely(addr & (sizeof(type##_t)-1))) \ return misaligned_load(addr, sizeof(type##_t)); \ reg_t vpn = addr >> PGSHIFT; \ if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) \ return (type##_t)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); \ if (unlikely(tlb_load_tag[vpn % TLB_ENTRIES] == (vpn \| TLB_CHECK_TRIGGERS))) { \ type##_t data = (type##_t)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); \ if (!matched_trigger) { \ matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); \ if (matched_trigger) \ throw matched_trigger; \ } \ return data; \ } \ type##_t res; \ load_slow_path(addr, sizeof(type##_t), (uint8_t)&res); \ return res; \ } // load value from memory at aligned address; zero extend to register width load_func(uint8) load_func(uint16) load_func(uint32) load_func(uint64) // load value from memory at aligned address; sign extend to register width load_func(int8) load_func(int16) load_func(int32) load_func(int64) // template for functions that store an aligned value to memory #define store_func(type) \ void store_##type(reg_t addr, type##_t val) { \ if (unlikely(addr & (sizeof(type##_t)-1))) \ return misaligned_store(addr, val, sizeof(type##_t)); \ reg_t vpn = addr >> PGSHIFT; \ if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \ (type##_t)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr) = val; \ else if (unlikely(tlb_store_tag[vpn % TLB_ENTRIES] == (vpn \| TLB_CHECK_TRIGGERS))) { \ if (!matched_trigger) { \ matched_trigger = trigger_exception(OPERATION_STORE, addr, val); \ if (matched_trigger) \ throw matched_trigger; \ } \ (type##_t)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr) = val; \ } \ else \ store_slow_path(addr, sizeof(type##_t), (const uint8_t)&val); \ } // template for functions that perform an atomic memory operation #define amo_func(type) \ template<typename op> \ type##_t amo_##type(reg_t addr, op f) { \ if (addr & (sizeof(type##_t)-1)) \ throw trap_store_address_misaligned(addr); \ try { \ auto lhs = load_##type(addr); \ store_##type(addr, f(lhs)); \ return lhs; \ } catch (trap_load_page_fault& t) { \ /* AMO faults should be reported as store faults / \ throw trap_store_page_fault(t.get_tval()); \ } catch (trap_load_access_fault& t) { \ / AMO faults should be reported as store faults / \ throw trap_store_access_fault(t.get_tval()); \ } \ } void store_float128(reg_t addr, float128_t val) { #ifndef RISCV_ENABLE_MISALIGNED if (unlikely(addr & (sizeof(float128_t)-1))) throw trap_store_address_misaligned(addr); #endif store_uint64(addr, val.v[0]); store_uint64(addr + 8, val.v[1]); } float128_t load_float128(reg_t addr) { #ifndef RISCV_ENABLE_MISALIGNED if (unlikely(addr & (sizeof(float128_t)-1))) throw trap_load_address_misaligned(addr); #endif return (float128_t){load_uint64(addr), load_uint64(addr + 8)}; } // store value to memory at aligned address store_func(uint8) store_func(uint16) store_func(uint32) store_func(uint64) // perform an atomic memory operation at an aligned address amo_func(uint32) amo_func(uint64) inline void yield_load_reservation() { load_reservation_address = (reg_t)-1; } inline void acquire_load_reservation(reg_t vaddr) { reg_t paddr = translate(vaddr, 1, LOAD); if (auto host_addr = sim->addr_to_mem(paddr)) load_reservation_address = refill_tlb(vaddr, paddr, host_addr, LOAD).target_offset + vaddr; else throw trap_load_access_fault(vaddr); // disallow LR to I/O space } inline bool check_load_reservation(reg_t vaddr) { reg_t paddr = translate(vaddr, 1, STORE); if (auto host_addr = sim->addr_to_mem(paddr)) return load_reservation_address == refill_tlb(vaddr, paddr, host_addr, STORE).target_offset + vaddr; else throw trap_store_access_fault(vaddr); // disallow SC to I/O space } static const reg_t ICACHE_ENTRIES = 1024; inline size_t icache_index(reg_t addr) { return (addr / PC_ALIGN) % ICACHE_ENTRIES; } inline icache_entry_t refill_icache(reg_t addr, icache_entry_t* entry) { auto tlb_entry = translate_insn_addr(addr); insn_bits_t insn = (uint16_t)(tlb_entry.host_offset + addr); int length = insn_length(insn); if (likely(length == 4)) { insn \|= (insn_bits_t)(const int16_t)translate_insn_addr_to_host(addr + 2) << 16; } else if (length == 2) { insn = (int16_t)insn; } else if (length == 6) { insn \|= (insn_bits_t)(const int16_t)translate_insn_addr_to_host(addr + 4) << 32; insn \|= (insn_bits_t)(const uint16_t)translate_insn_addr_to_host(addr + 2) << 16; } else { static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t"); insn \|= (insn_bits_t)(const int16_t)translate_insn_addr_to_host(addr + 6) << 48; insn \|= (insn_bits_t)(const uint16_t)translate_insn_addr_to_host(addr + 4) << 32; insn \|= (insn_bits_t)(const uint16_t)translate_insn_addr_to_host(addr + 2) << 16; } insn_fetch_t fetch = {proc->decode_insn(insn), insn}; entry->tag = addr; entry->next = &icache[icache_index(addr + length)]; entry->data = fetch; reg_t paddr = tlb_entry.target_offset + addr;; if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) { entry->tag = -1; tracer.trace(paddr, length, FETCH); } return entry; } inline icache_entry_t* access_icache(reg_t addr) { icache_entry_t* entry = &icache[icache_index(addr)]; if (likely(entry->tag == addr)) return entry; return refill_icache(addr, entry); } inline insn_fetch_t load_insn(reg_t addr) { icache_entry_t entry; return refill_icache(addr, &entry)->data; } void flush_tlb(); void flush_icache(); void register_memtracer(memtracer_t); int is_dirty_enabled() { #ifdef RISCV_ENABLE_DIRTY return 1; #else return 0; #endif } int is_misaligned_enabled() { #ifdef RISCV_ENABLE_MISALIGNED return 1; #else return 0; #endif } private: simif_t sim; processor_t* proc; memtracer_list_t tracer; reg_t load_reservation_address; uint16_t fetch_temp; // implement an instruction cache for simulator performance icache_entry_t icache[ICACHE_ENTRIES]; // implement a TLB for simulator performance static const reg_t TLB_ENTRIES = 256; // If a TLB tag has TLB_CHECK_TRIGGERS set, then the MMU must check for a // trigger match before completing an access. static const reg_t TLB_CHECK_TRIGGERS = reg_t(1) << 63; tlb_entry_t tlb_data[TLB_ENTRIES]; reg_t tlb_insn_tag[TLB_ENTRIES]; reg_t tlb_load_tag[TLB_ENTRIES]; reg_t tlb_store_tag[TLB_ENTRIES]; // finish translation on a TLB miss and update the TLB tlb_entry_t refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_type type); const char* fill_from_mmio(reg_t vaddr, reg_t paddr); // perform a page table walk for a given VA; set referenced/dirty bits reg_t walk(reg_t addr, access_type type, reg_t prv); // handle uncommon cases: TLB misses, page faults, MMIO tlb_entry_t fetch_slow_path(reg_t addr); void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes); void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes); reg_t translate(reg_t addr, reg_t len, access_type type); // ITLB lookup inline tlb_entry_t translate_insn_addr(reg_t addr) { reg_t vpn = addr >> PGSHIFT; if (likely(tlb_insn_tag[vpn % TLB_ENTRIES] == vpn)) return tlb_data[vpn % TLB_ENTRIES]; tlb_entry_t result; if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] != (vpn \| TLB_CHECK_TRIGGERS))) { result = fetch_slow_path(addr); } else { result = tlb_data[vpn % TLB_ENTRIES]; } if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] == (vpn \| TLB_CHECK_TRIGGERS))) { uint16_t* ptr = (uint16_t)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); int match = proc->trigger_match(OPERATION_EXECUTE, addr, ptr); if (match >= 0) { throw trigger_matched_t(match, OPERATION_EXECUTE, addr, ptr); } } return result; } inline const uint16_t translate_insn_addr_to_host(reg_t addr) { return (uint16_t)(translate_insn_addr(addr).host_offset + addr); } inline trigger_matched_t trigger_exception(trigger_operation_t operation, reg_t address, reg_t data) { if (!proc) { return NULL; } int match = proc->trigger_match(operation, address, data); if (match == -1) return NULL; if (proc->state.mcontrol[match].timing == 0) { throw trigger_matched_t(match, operation, address, data); } return new trigger_matched_t(match, operation, address, data); } reg_t pmp_homogeneous(reg_t addr, reg_t len); reg_t pmp_ok(reg_t addr, access_type type, reg_t mode); bool check_triggers_fetch; bool check_triggers_load; bool check_triggers_store; // The exception describing a matched trigger, or NULL. trigger_matched_t *matched_trigger; friend class processor_t; }; struct vm_info { int levels; int idxbits; int ptesize; reg_t ptbase; }; inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t satp) { if (prv == PRV_M) { return {0, 0, 0, 0}; } else if (prv <= PRV_S && xlen == 32) { switch (get_field(satp, SATP32_MODE)) { case SATP_MODE_OFF: return {0, 0, 0, 0}; case SATP_MODE_SV32: return {2, 10, 4, (satp & SATP32_PPN) << PGSHIFT}; default: abort(); } } else if (prv <= PRV_S && xlen == 64) { switch (get_field(satp, SATP64_MODE)) { case SATP_MODE_OFF: return {0, 0, 0, 0}; case SATP_MODE_SV39: return {3, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; case SATP_MODE_SV48: return {4, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; case SATP_MODE_SV57: return {5, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; case SATP_MODE_SV64: return {6, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; default: abort(); } } else { abort(); } } #endif
// See LICENSE for license details. #ifndef _RISCV_MULHI_H #define _RISCV_MULHI_H #include <cstdint> inline uint64_t mulhu(uint64_t a, uint64_t b) { uint64_t t; uint32_t y1, y2, y3; uint64_t a0 = (uint32_t)a, a1 = a >> 32; uint64_t b0 = (uint32_t)b, b1 = b >> 32; t = a1b0 + ((a0b0) >> 32); y1 = t; y2 = t >> 32; t = a0b1 + y1; y1 = t; t = a1b1 + y2 + (t >> 32); y2 = t; y3 = t >> 32; return ((uint64_t)y3 << 32) \| y2; } inline int64_t mulh(int64_t a, int64_t b) { int negate = (a < 0) != (b < 0); uint64_t res = mulhu(a < 0 ? -a : a, b < 0 ? -b : b); return negate ? ~res + (a * b == 0) : res; } inline int64_t mulhsu(int64_t a, uint64_t b) { int negate = a < 0; uint64_t res = mulhu(a < 0 ? -a : a, b); return negate ? ~res + (a * b == 0) : res; } #endif
#include "encoding.h" #define ZERO 0 #define T0 5 #define S0 8 #define S1 9 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) { return (value >> lo) & ((1 << (hi+1-lo)) - 1); } static uint32_t bit(uint32_t value, unsigned int b) { return (value >> b) & 1; } static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__ ((unused)); static uint32_t jal(unsigned int rd, uint32_t imm) { return (bit(imm, 20) << 31) \| (bits(imm, 10, 1) << 21) \| (bit(imm, 11) << 20) \| (bits(imm, 19, 12) << 12) \| (rd << 7) \| MATCH_JAL; } static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__ ((unused)); static uint32_t csrsi(unsigned int csr, uint16_t imm) { return (csr << 20) \| (bits(imm, 4, 0) << 15) \| MATCH_CSRRSI; } static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (src << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_SW; } static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (src << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_SD; } static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (src << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_SH; } static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (src << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_SB; } static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) \| (base << 15) \| (bits(rd, 4, 0) << 7) \| MATCH_LD; } static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) \| (base << 15) \| (bits(rd, 4, 0) << 7) \| MATCH_LW; } static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) \| (base << 15) \| (bits(rd, 4, 0) << 7) \| MATCH_LH; } static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) \| (base << 15) \| (bits(rd, 4, 0) << 7) \| MATCH_LB; } static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__ ((unused)); static uint32_t csrw(unsigned int source, unsigned int csr) { return (csr << 20) \| (source << 15) \| MATCH_CSRRW; } static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) { return (bits(imm, 11, 0) << 20) \| (src << 15) \| (dest << 7) \| MATCH_ADDI; } static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__ ((unused)); static uint32_t csrr(unsigned int rd, unsigned int csr) { return (csr << 20) \| (rd << 7) \| MATCH_CSRRS; } static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (bits(src, 4, 0) << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_FSW; } static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (bits(src, 4, 0) << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_FSD; } static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) \| (base << 15) \| (bits(dest, 4, 0) << 7) \| MATCH_FLW; } static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) \| (base << 15) \| (bits(dest, 4, 0) << 7) \| MATCH_FLD; } static uint32_t ebreak(void) __attribute__ ((unused)); static uint32_t ebreak(void) { return MATCH_EBREAK; } static uint32_t ebreak_c(void) __attribute__ ((unused)); static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; } static uint32_t dret(void) __attribute__ ((unused)); static uint32_t dret(void) { return MATCH_DRET; } static uint32_t fence_i(void) __attribute__ ((unused)); static uint32_t fence_i(void) { return MATCH_FENCE_I; } /* static uint32_t lui(unsigned int dest, uint32_t imm) __attribute__ ((unused)); static uint32_t lui(unsigned int dest, uint32_t imm) { return (bits(imm, 19, 0) << 12) \| (dest << 7) \| MATCH_LUI; } static uint32_t csrci(unsigned int csr, uint16_t imm) __attribute__ ((unused)); static uint32_t csrci(unsigned int csr, uint16_t imm) { return (csr << 20) \| (bits(imm, 4, 0) << 15) \| MATCH_CSRRCI; } static uint32_t li(unsigned int dest, uint16_t imm) __attribute__ ((unused)); static uint32_t li(unsigned int dest, uint16_t imm) { return addi(dest, 0, imm); } static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) \| (bits(src, 4, 0) << 20) \| (base << 15) \| (bits(offset, 4, 0) << 7) \| MATCH_FSD; } static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm) { return (bits(imm, 11, 0) << 20) \| (src << 15) \| (dest << 7) \| MATCH_ORI; } static uint32_t nop(void) __attribute__ ((unused)); static uint32_t nop(void) { return addi(0, 0, 0); } */ static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) { return (bits(imm, 11, 0) << 20) \| (src << 15) \| (dest << 7) \| MATCH_XORI; } static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__ ((unused)); static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) { return (bits(shamt, 4, 0) << 20) \| (src << 15) \| (dest << 7) \| MATCH_SRLI; }
// See LICENSE for license details. #include "processor.h" #include "extension.h" #include "common.h" #include "config.h" #include "simif.h" #include "mmu.h" #include "disasm.h" #include <cinttypes> #include <cmath> #include <cstdlib> #include <iostream> #include <assert.h> #include <limits.h> #include <stdexcept> #include <algorithm> #undef STATE #define STATE state processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset) : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset), last_pc(1), executions(1) { parse_isa_string(isa); register_base_instructions(); mmu = new mmu_t(sim, this); disassembler = new disassembler_t(max_xlen); if (ext) for (auto disasm_insn : ext->get_disasms()) disassembler->add_insn(disasm_insn); reset(); } processor_t::~processor_t() { #ifdef RISCV_ENABLE_HISTOGRAM if (histogram_enabled) { fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size()); for (auto it : pc_histogram) fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second); } #endif delete mmu; delete disassembler; } static void bad_isa_string(const char* isa) { fprintf(stderr, "error: bad --isa option %s\n", isa); abort(); } void processor_t::parse_isa_string(const char* str) { std::string lowercase, tmp; for (const char r = str; r; r++) lowercase += std::tolower(r); const char p = lowercase.c_str(); const char* all_subsets = "imafdqc"; max_xlen = 64; state.misa = reg_t(2) << 62; if (strncmp(p, "rv32", 4) == 0) max_xlen = 32, state.misa = reg_t(1) << 30, p += 4; else if (strncmp(p, "rv64", 4) == 0) p += 4; else if (strncmp(p, "rv", 2) == 0) p += 2; if (!p) { p = "imafdc"; } else if (p == 'g') { // treat "G" as "IMAFD" tmp = std::string("imafd") + (p+1); p = &tmp[0]; } else if (p != 'i') { bad_isa_string(str); } isa_string = "rv" + std::to_string(max_xlen) + p; state.misa \|= 1L << ('s' - 'a'); // advertise support for supervisor mode state.misa \|= 1L << ('u' - 'a'); // advertise support for user mode while (p) { state.misa \|= 1L << (p - 'a'); if (auto next = strchr(all_subsets, p)) { all_subsets = next + 1; p++; } else if (p == 'x') { const char ext = p+1, end = ext; while (islower(end)) end++; register_extension(find_extension(std::string(ext, end - ext).c_str())()); p = end; } else { bad_isa_string(str); } } if (supports_extension('D') && !supports_extension('F')) bad_isa_string(str); if (supports_extension('Q') && !supports_extension('D')) bad_isa_string(str); if (supports_extension('Q') && max_xlen < 64) bad_isa_string(str); max_isa = state.misa; } void state_t::reset(reg_t max_isa) { memset(this, 0, sizeof(this)); misa = max_isa; prv = PRV_M; mstatus = 0; pc = DEFAULT_RSTVEC; tselect = 0; for (unsigned int i = 0; i < num_triggers; i++) mcontrol[i].type = 2; pmpcfg[0] = PMP_R \| PMP_W \| PMP_X \| PMP_NAPOT; pmpaddr[0] = ~reg_t(0); } void processor_t::set_debug(bool value) { debug = value; if (ext) ext->set_debug(value); } void processor_t::set_histogram(bool value) { histogram_enabled = value; #ifndef RISCV_ENABLE_HISTOGRAM if (value) { fprintf(stderr, "PC Histogram support has not been properly enabled;"); fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n"); } #endif } void processor_t::reset() { state.reset(max_isa); state.dcsr.halt = halt_on_reset; halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); if (ext) ext->reset(); // reset the extension if (sim) sim->proc_reset(id); } // Count number of contiguous 0 bits starting from the LSB. static int ctz(reg_t val) { int res = 0; if (val) while ((val & 1) == 0) val >>= 1, res++; return res; } void processor_t::take_interrupt(reg_t pending_interrupts) { reg_t mie = get_field(state.mstatus, MSTATUS_MIE); reg_t m_enabled = state.prv < PRV_M \|\| (state.prv == PRV_M && mie); reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled; reg_t sie = get_field(state.mstatus, MSTATUS_SIE); reg_t s_enabled = state.prv < PRV_S \|\| (state.prv == PRV_S && sie); // M-ints have highest priority; consider S-ints only if no M-ints pending if (enabled_interrupts == 0) enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; if (state.dcsr.cause == 0 && enabled_interrupts) { // nonstandard interrupts have highest priority if (enabled_interrupts >> IRQ_M_EXT) enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT; // external interrupts have next-highest priority else if (enabled_interrupts & (MIP_MEIP \| MIP_SEIP)) enabled_interrupts = enabled_interrupts & (MIP_MEIP \| MIP_SEIP); // software interrupts have next-highest priority else if (enabled_interrupts & (MIP_MSIP \| MIP_SSIP)) enabled_interrupts = enabled_interrupts & (MIP_MSIP \| MIP_SSIP); // timer interrupts have next-highest priority else if (enabled_interrupts & (MIP_MTIP \| MIP_STIP)) enabled_interrupts = enabled_interrupts & (MIP_MTIP \| MIP_STIP); else abort(); throw trap_t(((reg_t)1 << (max_xlen-1)) \| ctz(enabled_interrupts)); } } static int xlen_to_uxl(int xlen) { if (xlen == 32) return 1; if (xlen == 64) return 2; abort(); } reg_t processor_t::legalize_privilege(reg_t prv) { assert(prv <= PRV_M); if (!supports_extension('U')) return PRV_M; if (prv == PRV_H \|\| !supports_extension('S')) return PRV_U; return prv; } void processor_t::set_privilege(reg_t prv) { // mmu->flush_tlb(); state.prv = legalize_privilege(prv); } void processor_t::enter_debug_mode(uint8_t cause) { state.dcsr.cause = cause; state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; state.pc = DEBUG_ROM_ENTRY; } void processor_t::take_trap(trap_t& t, reg_t epc) { if (debug) { fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); if (t.has_tval()) fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id, t.get_tval()); } if (state.dcsr.cause) { if (t.cause() == CAUSE_BREAKPOINT) { state.pc = DEBUG_ROM_ENTRY; } else { state.pc = DEBUG_ROM_TVEC; } return; } if (t.cause() == CAUSE_BREAKPOINT && ( (state.prv == PRV_M && state.dcsr.ebreakm) \|\| (state.prv == PRV_S && state.dcsr.ebreaks) \|\| (state.prv == PRV_U && state.dcsr.ebreaku))) { enter_debug_mode(DCSR_CAUSE_SWBP); return; } // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0; if (interrupt) deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1)); if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) { // handle the trap in S-mode state.pc = state.stvec; state.scause = t.cause(); state.sepc = epc; state.stval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, state.prv); s = set_field(s, MSTATUS_SIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_S); } else { reg_t vector = (state.mtvec & 1) && interrupt ? 4bit : 0; state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; state.mcause = t.cause(); state.mtval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, state.prv); s = set_field(s, MSTATUS_MIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_M); } } void processor_t::disasm(insn_t insn) { uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); if (last_pc != state.pc \|\| last_bits != bits) { if (executions != 1) { fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions); } fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", id, state.pc, bits, disassembler->disassemble(insn).c_str()); last_pc = state.pc; last_bits = bits; executions = 1; } else { executions++; } } int processor_t::paddr_bits() { assert(xlen == max_xlen); return max_xlen == 64 ? 50 : 34; } void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); reg_t delegable_ints = MIP_SSIP \| MIP_STIP \| MIP_SEIP \| ((ext != NULL) << IRQ_COP); reg_t all_ints = delegable_ints \| MIP_MSIP \| MIP_MTIP; // if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.n_pmp) { // size_t i = which - CSR_PMPADDR0; // bool locked = state.pmpcfg[i] & PMP_L; // bool next_locked = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_L); // bool next_tor = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_A) == PMP_TOR; // if (!locked && !(next_locked && next_tor)) // state.pmpaddr[i] = val; // // mmu->flush_tlb(); // } // if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.n_pmp / 4) { // for (size_t i0 = (which - CSR_PMPCFG0) * 4, i = i0; i < i0 + xlen / 8; i++) { // if (!(state.pmpcfg[i] & PMP_L)) // state.pmpcfg[i] = (val >> (8 * (i - i0))) & (PMP_R \| PMP_W \| PMP_X \| PMP_A \| PMP_L); // } // // mmu->flush_tlb(); // } switch (which) { case CSR_FFLAGS: dirty_fp_state; state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT); break; case CSR_FRM: dirty_fp_state; state.frm = val & (FSR_RD >> FSR_RD_SHIFT); break; case CSR_FCSR: dirty_fp_state; state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT; state.frm = (val & FSR_RD) >> FSR_RD_SHIFT; break; case CSR_MSTATUS: { // if ((val ^ state.mstatus) & // (MSTATUS_MPP \| MSTATUS_MPRV \| MSTATUS_SUM \| MSTATUS_MXR)) // mmu->flush_tlb(); reg_t mask = MSTATUS_SIE \| MSTATUS_SPIE \| MSTATUS_MIE \| MSTATUS_MPIE \| MSTATUS_MPRV \| MSTATUS_SUM \| MSTATUS_MXR \| MSTATUS_TW \| MSTATUS_TVM \| MSTATUS_TSR \| MSTATUS_UXL \| MSTATUS_SXL \| (ext ? MSTATUS_XS : 0); reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP)); state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp); if (supports_extension('S')) mask \|= MSTATUS_SPP; state.mstatus = (state.mstatus & ~mask) \| (val & mask); bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS; dirty \|= (state.mstatus & MSTATUS_XS) == MSTATUS_XS; dirty = 0; if (max_xlen == 32) state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty); else state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty); state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen)); // U-XLEN == S-XLEN == M-XLEN xlen = max_xlen; break; } case CSR_MIP: { reg_t mask = MIP_SSIP \| MIP_STIP; state.mip = (state.mip & ~mask) \| (val & mask); break; } case CSR_MIE: state.mie = (state.mie & ~all_ints) \| (val & all_ints); break; case CSR_MIDELEG: state.mideleg = (state.mideleg & ~delegable_ints) \| (val & delegable_ints); break; case CSR_MEDELEG: { reg_t mask = (1 << CAUSE_MISALIGNED_FETCH) \| (1 << CAUSE_BREAKPOINT) \| (1 << CAUSE_USER_ECALL) \| (1 << CAUSE_FETCH_PAGE_FAULT) \| (1 << CAUSE_LOAD_PAGE_FAULT) \| (1 << CAUSE_STORE_PAGE_FAULT); state.medeleg = (state.medeleg & ~mask) \| (val & mask); break; } case CSR_MINSTRET: case CSR_MCYCLE: if (xlen == 32) state.minstret = (state.minstret >> 32 << 32) \| (val & 0xffffffffU); else state.minstret = val; // The ISA mandates that if an instruction writes instret, the write // takes precedence over the increment to instret. However, Spike // unconditionally increments instret after executing an instruction. // Correct for this artifact by decrementing instret here. state.minstret--; break; case CSR_MINSTRETH: case CSR_MCYCLEH: state.minstret = (val << 32) \| (state.minstret << 32 >> 32); state.minstret--; // See comment above. break; case CSR_SCOUNTEREN: state.scounteren = val; break; case CSR_MCOUNTEREN: state.mcounteren = val; break; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE \| SSTATUS_SPIE \| SSTATUS_SPP \| SSTATUS_FS \| SSTATUS_XS \| SSTATUS_SUM \| SSTATUS_MXR; return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) \| (val & mask)); } case CSR_SIP: { reg_t mask = MIP_SSIP & state.mideleg; return set_csr(CSR_MIP, (state.mip & ~mask) \| (val & mask)); } case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) \| (val & state.mideleg)); case CSR_SATP: { mmu->flush_tlb(); if (max_xlen == 32) state.satp = val & (SATP32_PPN \| SATP32_MODE); if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF \|\| get_field(val, SATP64_MODE) == SATP_MODE_SV39 \|\| get_field(val, SATP64_MODE) == SATP_MODE_SV48)) state.satp = val & (SATP64_PPN \| SATP64_MODE); break; } case CSR_SEPC: state.sepc = val & ~(reg_t)1; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; case CSR_STVAL: state.stval = val; break; case CSR_MEPC: state.mepc = val & ~(reg_t)1; break; case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MTVAL: state.mtval = val; break; case CSR_MISA: { // the write is ignored if increasing IALIGN would misalign the PC if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2)) break; if (!(val & (1L << ('F' - 'A')))) val &= ~(1L << ('D' - 'A')); // allow MAFDC bits in MISA to be modified reg_t mask = 0; mask \|= 1L << ('M' - 'A'); mask \|= 1L << ('A' - 'A'); mask \|= 1L << ('F' - 'A'); mask \|= 1L << ('D' - 'A'); mask \|= 1L << ('C' - 'A'); mask &= max_isa; state.misa = (val & mask) \| (state.misa & ~mask); break; } case CSR_TSELECT: if (val < state.num_triggers) { state.tselect = val; } break; case CSR_TDATA1: { mcontrol_t mc = &state.mcontrol[state.tselect]; if (mc->dmode && !state.dcsr.cause) { break; } mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); mc->select = get_field(val, MCONTROL_SELECT); mc->timing = get_field(val, MCONTROL_TIMING); mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); mc->chain = get_field(val, MCONTROL_CHAIN); mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH); mc->m = get_field(val, MCONTROL_M); mc->h = get_field(val, MCONTROL_H); mc->s = get_field(val, MCONTROL_S); mc->u = get_field(val, MCONTROL_U); mc->execute = get_field(val, MCONTROL_EXECUTE); mc->store = get_field(val, MCONTROL_STORE); mc->load = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. if (mc->execute) mc->timing = 0; trigger_updated(); } break; case CSR_TDATA2: if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) { break; } if (state.tselect < state.num_triggers) { state.tdata2[state.tselect] = val; } break; case CSR_DCSR: state.dcsr.prv = get_field(val, DCSR_PRV); state.dcsr.step = get_field(val, DCSR_STEP); // TODO: ndreset and fullreset state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM); state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH); state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS); state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU); state.dcsr.halt = get_field(val, DCSR_HALT); break; case CSR_DPC: state.dpc = val & ~(reg_t)1; break; case CSR_DSCRATCH: state.dscratch = val; break; } } // Note that get_csr is sometimes called when read side-effects should not // be actioned. In other words, Spike cannot currently support CSRs with // side effects on reads. reg_t processor_t::get_csr(int which) { uint32_t ctr_en = -1; if (state.prv < PRV_M) ctr_en &= state.mcounteren; if (state.prv < PRV_S) ctr_en &= state.scounteren; bool ctr_ok = (ctr_en >> (which & 31)) & 1; if (ctr_ok) { if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31) return 0; if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H) return 0; } if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31) return 0; if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H) return 0; if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31) return 0; // if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.n_pmp) // return state.pmpaddr[which - CSR_PMPADDR0]; // if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.n_pmp / 4) { // require((which & ((xlen / 32) - 1)) == 0); // reg_t res = 0; // for (size_t i0 = (which - CSR_PMPCFG0) 4, i = i0; i < i0 + xlen / 8 && i < state.n_pmp; i++) // res \|= reg_t(state.pmpcfg[i]) << (8 * (i - i0)); // return res; // } switch (which) { case CSR_FFLAGS: require_fp; if (!supports_extension('F')) break; return state.fflags; case CSR_FRM: require_fp; if (!supports_extension('F')) break; return state.frm; case CSR_FCSR: require_fp; if (!supports_extension('F')) break; return (state.fflags << FSR_AEXC_SHIFT) \| (state.frm << FSR_RD_SHIFT); case CSR_INSTRET: case CSR_CYCLE: if (ctr_ok) return state.minstret; break; case CSR_MINSTRET: case CSR_MCYCLE: return state.minstret; case CSR_INSTRETH: case CSR_CYCLEH: if (ctr_ok && xlen == 32) return state.minstret >> 32; break; case CSR_MINSTRETH: case CSR_MCYCLEH: if (xlen == 32) return state.minstret >> 32; break; case CSR_SCOUNTEREN: return state.scounteren; case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE \| SSTATUS_SPIE \| SSTATUS_SPP \| SSTATUS_FS \| SSTATUS_XS \| SSTATUS_SUM \| SSTATUS_MXR \| SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS \|\| (sstatus & SSTATUS_XS) == SSTATUS_XS) sstatus \|= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD); return sstatus; } case CSR_SIP: return state.mip & state.mideleg; case CSR_SIE: return state.mie & state.mideleg; case CSR_SEPC: return state.sepc & pc_alignment_mask(); case CSR_STVAL: return state.stval; case CSR_STVEC: return state.stvec; case CSR_SCAUSE: if (max_xlen > xlen) return state.scause \| ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; case CSR_SATP: if (get_field(state.mstatus, MSTATUS_TVM)) require_privilege(PRV_M); return state.satp; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; case CSR_MIE: return state.mie; case CSR_MEPC: return state.mepc & pc_alignment_mask(); case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; case CSR_MTVAL: return state.mtval; case CSR_MISA: return state.misa; case CSR_MARCHID: return 5; case CSR_MIMPID: return 0; case CSR_MVENDORID: return 0; case CSR_MHARTID: return id; case CSR_MTVEC: return state.mtvec; case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TSELECT: return state.tselect; case CSR_TDATA1: if (state.tselect < state.num_triggers) { reg_t v = 0; mcontrol_t mc = &state.mcontrol[state.tselect]; v = set_field(v, MCONTROL_TYPE(xlen), mc->type); v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode); v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax); v = set_field(v, MCONTROL_SELECT, mc->select); v = set_field(v, MCONTROL_TIMING, mc->timing); v = set_field(v, MCONTROL_ACTION, mc->action); v = set_field(v, MCONTROL_CHAIN, mc->chain); v = set_field(v, MCONTROL_MATCH, mc->match); v = set_field(v, MCONTROL_M, mc->m); v = set_field(v, MCONTROL_H, mc->h); v = set_field(v, MCONTROL_S, mc->s); v = set_field(v, MCONTROL_U, mc->u); v = set_field(v, MCONTROL_EXECUTE, mc->execute); v = set_field(v, MCONTROL_STORE, mc->store); v = set_field(v, MCONTROL_LOAD, mc->load); return v; } else { return 0; } break; case CSR_TDATA2: if (state.tselect < state.num_triggers) { return state.tdata2[state.tselect]; } else { return 0; } break; case CSR_TDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; v = set_field(v, DCSR_XDEBUGVER, 1); v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); v = set_field(v, DCSR_STOPCYCLE, 0); v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_CAUSE, state.dcsr.cause); v = set_field(v, DCSR_STEP, state.dcsr.step); v = set_field(v, DCSR_PRV, state.dcsr.prv); return v; } case CSR_DPC: return state.dpc & pc_alignment_mask(); case CSR_DSCRATCH: return state.dscratch; } throw trap_illegal_instruction(0); } reg_t illegal_instruction(processor_t p, insn_t insn, reg_t pc) { throw trap_illegal_instruction(0); } insn_func_t processor_t::decode_insn(insn_t insn) { // look up opcode in hash table size_t idx = insn.bits() % OPCODE_CACHE_SIZE; insn_desc_t desc = opcode_cache[idx]; if (unlikely(insn.bits() != desc.match)) { // fall back to linear search insn_desc_t* p = &instructions[0]; while ((insn.bits() & p->mask) != p->match) p++; desc = p; if (p->mask != 0 && p > &instructions[0]) { if (p->match != (p-1)->match && p->match != (p+1)->match) { // move to front of opcode list to reduce miss penalty while (--p >= &instructions[0]) (p+1) = p; instructions[0] = desc; } } opcode_cache[idx] = desc; opcode_cache[idx].match = insn.bits(); } return xlen == 64 ? desc.rv64 : desc.rv32; } void processor_t::register_insn(insn_desc_t desc) { instructions.push_back(desc); } void processor_t::build_opcode_map() { struct cmp { bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) { if (lhs.match == rhs.match) return lhs.mask > rhs.mask; return lhs.match > rhs.match; } }; std::sort(instructions.begin(), instructions.end(), cmp()); for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction}; } void processor_t::register_extension(extension_t x) { for (auto insn : x->get_instructions()) register_insn(insn); build_opcode_map(); for (auto disasm_insn : x->get_disasms()) disassembler->add_insn(disasm_insn); if (ext != NULL) throw std::logic_error("only one extension may be registered"); ext = x; x->set_processor(this); } void processor_t::register_base_instructions() { #define DECLARE_INSN(name, match, mask) \ insn_bits_t name##_match = (match), name##_mask = (mask); #include "encoding.h" #undef DECLARE_INSN #define DEFINE_INSN(name) \ REGISTER_INSN(this, name, name##_match, name##_mask) #include "insn_list.h" #undef DEFINE_INSN register_insn({0, 0, &illegal_instruction, &illegal_instruction}); build_opcode_map(); } bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes) { switch (addr) { case 0: if (len <= 4) { memset(bytes, 0, len); bytes[0] = get_field(state.mip, MIP_MSIP); return true; } break; } return false; } bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) { switch (addr) { case 0: if (len <= 4) { state.mip = set_field(state.mip, MIP_MSIP, bytes[0]); return true; } break; } return false; } void processor_t::trigger_updated() { // mmu->flush_tlb(); mmu->check_triggers_fetch = false; mmu->check_triggers_load = false; mmu->check_triggers_store = false; for (unsigned i = 0; i < state.num_triggers; i++) { if (state.mcontrol[i].execute) { mmu->check_triggers_fetch = true; } if (state.mcontrol[i].load) { mmu->check_triggers_load = true; } if (state.mcontrol[i].store) { mmu->check_triggers_store = true; } } }
// See LICENSE for license details. #ifndef _RISCV_PROCESSOR_H #define _RISCV_PROCESSOR_H #include "decode.h" #include "config.h" #include "devices.h" #include "trap.h" #include <string> #include <vector> #include <map> #include "debug_rom_defines.h" class processor_t; class mmu_t; typedef reg_t (insn_func_t)(processor_t, insn_t, reg_t); class simif_t; class trap_t; class extension_t; class disassembler_t; struct insn_desc_t { insn_bits_t match; insn_bits_t mask; insn_func_t rv32; insn_func_t rv64; }; struct commit_log_reg_t { reg_t addr; freg_t data; }; typedef struct { uint8_t prv; bool step; bool ebreakm; bool ebreakh; bool ebreaks; bool ebreaku; bool halt; uint8_t cause; } dcsr_t; typedef enum { ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE, ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START, ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP, ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT } mcontrol_action_t; typedef enum { MATCH_EQUAL = MCONTROL_MATCH_EQUAL, MATCH_NAPOT = MCONTROL_MATCH_NAPOT, MATCH_GE = MCONTROL_MATCH_GE, MATCH_LT = MCONTROL_MATCH_LT, MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW, MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH } mcontrol_match_t; typedef struct { uint8_t type; bool dmode; uint8_t maskmax; bool select; bool timing; mcontrol_action_t action; bool chain; mcontrol_match_t match; bool m; bool h; bool s; bool u; bool execute; bool store; bool load; } mcontrol_t; // architectural state of a RISC-V hart struct state_t { void reset(reg_t max_isa); static const int num_triggers = 4; reg_t pc; regfile_t<reg_t, NXPR, true> XPR; regfile_t<freg_t, NFPR, false> FPR; // control and status registers reg_t prv; // TODO: Can this be an enum instead? reg_t misa; reg_t mstatus; reg_t mepc; reg_t mtval; reg_t mscratch; reg_t mtvec; reg_t mcause; reg_t minstret; reg_t mie; reg_t mip; reg_t medeleg; reg_t mideleg; uint32_t mcounteren; uint32_t scounteren; reg_t sepc; reg_t stval; reg_t sscratch; reg_t stvec; reg_t satp; reg_t scause; reg_t dpc; reg_t dscratch; dcsr_t dcsr; reg_t tselect; mcontrol_t mcontrol[num_triggers]; reg_t tdata2[num_triggers]; static const int n_pmp = 16; uint8_t pmpcfg[n_pmp]; reg_t pmpaddr[n_pmp]; uint32_t fflags; uint32_t frm; bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This // can only be set by executing dret. enum { STEP_NONE, STEP_STEPPING, STEP_STEPPED } single_step; #ifdef RISCV_ENABLE_COMMITLOG commit_log_reg_t log_reg_write; reg_t last_inst_priv; int last_inst_xlen; int last_inst_flen; uint32_t last_insn; bool was_exception; #endif }; typedef enum { OPERATION_EXECUTE, OPERATION_STORE, OPERATION_LOAD, } trigger_operation_t; // Count number of contiguous 1 bits starting from the LSB. static int cto(reg_t val) { int res = 0; while ((val & 1) == 1) val >>= 1, res++; return res; } // this class represents one processor in a RISC-V machine. class processor_t : public abstract_device_t { public: processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset=false); ~processor_t(); void set_debug(bool value); void set_histogram(bool value); void reset(); void step(size_t n); // run for n cycles void set_csr(int which, reg_t val); reg_t get_csr(int which); mmu_t* get_mmu() { return mmu; } state_t* get_state() { return &state; } unsigned get_xlen() { return xlen; } unsigned get_max_xlen() { return max_xlen; } std::string get_isa_string() { return isa_string; } unsigned get_flen() { return supports_extension('Q') ? 128 : supports_extension('D') ? 64 : supports_extension('F') ? 32 : 0; } extension_t* get_extension() { return ext; } bool supports_extension(unsigned char ext) { if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a'; return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1); } reg_t pc_alignment_mask() { return ~(reg_t)(supports_extension('C') ? 0 : 2); } void check_pc_alignment(reg_t pc) { if (unlikely(pc & ~pc_alignment_mask())) throw trap_instruction_address_misaligned(pc); } reg_t legalize_privilege(reg_t); void set_privilege(reg_t); void update_histogram(reg_t pc); const disassembler_t* get_disassembler() { return disassembler; } void register_insn(insn_desc_t); void register_extension(extension_t); // MMIO slave interface bool load(reg_t addr, size_t len, uint8_t bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); // When true, display disassembly of each instruction that's executed. bool debug; // When true, take the slow simulation path. bool slow_path(); bool halted() { return state.dcsr.cause ? true : false; } bool halt_request; // Return the index of a trigger that matched, or -1. inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data) { if (state.dcsr.cause) return -1; bool chain_ok = true; for (unsigned int i = 0; i < state.num_triggers; i++) { if (!chain_ok) { chain_ok \|= !state.mcontrol[i].chain; continue; } if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) \|\| (operation == OPERATION_STORE && !state.mcontrol[i].store) \|\| (operation == OPERATION_LOAD && !state.mcontrol[i].load) \|\| (state.prv == PRV_M && !state.mcontrol[i].m) \|\| (state.prv == PRV_S && !state.mcontrol[i].s) \|\| (state.prv == PRV_U && !state.mcontrol[i].u)) { continue; } reg_t value; if (state.mcontrol[i].select) { value = data; } else { value = address; } // We need this because in 32-bit mode sometimes the PC bits get sign // extended. if (xlen == 32) { value &= 0xffffffff; } switch (state.mcontrol[i].match) { case MATCH_EQUAL: if (value != state.tdata2[i]) continue; break; case MATCH_NAPOT: { reg_t mask = ~((1 << cto(state.tdata2[i])) - 1); if ((value & mask) != (state.tdata2[i] & mask)) continue; } break; case MATCH_GE: if (value < state.tdata2[i]) continue; break; case MATCH_LT: if (value >= state.tdata2[i]) continue; break; case MATCH_MASK_LOW: { reg_t mask = state.tdata2[i] >> (xlen/2); if ((value & mask) != (state.tdata2[i] & mask)) continue; } break; case MATCH_MASK_HIGH: { reg_t mask = state.tdata2[i] >> (xlen/2); if (((value >> (xlen/2)) & mask) != (state.tdata2[i] & mask)) continue; } break; } if (!state.mcontrol[i].chain) { return i; } chain_ok = true; } return -1; } void trigger_updated(); private: simif_t* sim; mmu_t* mmu; // main memory is always accessed via the mmu extension_t* ext; disassembler_t* disassembler; state_t state; uint32_t id; unsigned max_xlen; unsigned xlen; reg_t max_isa; std::string isa_string; bool histogram_enabled; bool halt_on_reset; std::vector<insn_desc_t> instructions; std::map<reg_t,uint64_t> pc_histogram; static const size_t OPCODE_CACHE_SIZE = 8191; insn_desc_t opcode_cache[OPCODE_CACHE_SIZE]; void take_pending_interrupt() { take_interrupt(state.mip & state.mie); } void take_interrupt(reg_t mask); // take first enabled interrupt in mask void take_trap(trap_t& t, reg_t epc); // take an exception void disasm(insn_t insn); // disassemble and print an instruction int paddr_bits(); void enter_debug_mode(uint8_t cause); friend class mmu_t; friend class clint_t; friend class extension_t; void parse_isa_string(const char* isa); void build_opcode_map(); void register_base_instructions(); insn_func_t decode_insn(insn_t insn); // Track repeated executions for processor_t::disasm() uint64_t last_pc, last_bits, executions; }; reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); #define REGISTER_INSN(proc, name, match, mask) \ extern reg_t rv32_##name(processor_t, insn_t, reg_t); \ extern reg_t rv64_##name(processor_t, insn_t, reg_t); \ proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name}); #endif
// See LICENSE for license details. #include "disasm.h" const char* xpr_name[] = { "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" }; const char* fpr_name[] = { "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" }; const char* csr_name(int which) { switch (which) { #define DECLARE_CSR(name, number) case number: return #name; #include "encoding.h" #undef DECLARE_CSR } return "unknown-csr"; }
#include <arpa/inet.h> #include <errno.h> #include <fcntl.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <algorithm> #include <cassert> #include <cstdio> #include "remote_bitbang.h" #if 1 # define D(x) x #else # define D(x) #endif /////////// remote_bitbang_t remote_bitbang_t::remote_bitbang_t(uint16_t port, jtag_dtm_t tap) : tap(tap), socket_fd(0), client_fd(0), recv_start(0), recv_end(0) { socket_fd = socket(AF_INET, SOCK_STREAM, 0); if (socket_fd == -1) { fprintf(stderr, "remote_bitbang failed to make socket: %s (%d)\n", strerror(errno), errno); abort(); } fcntl(socket_fd, F_SETFL, O_NONBLOCK); int reuseaddr = 1; if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr, sizeof(int)) == -1) { fprintf(stderr, "remote_bitbang failed setsockopt: %s (%d)\n", strerror(errno), errno); abort(); } struct sockaddr_in addr; memset(&addr, 0, sizeof(addr)); addr.sin_family = AF_INET; addr.sin_addr.s_addr = INADDR_ANY; addr.sin_port = htons(port); if (bind(socket_fd, (struct sockaddr ) &addr, sizeof(addr)) == -1) { fprintf(stderr, "remote_bitbang failed to bind socket: %s (%d)\n", strerror(errno), errno); abort(); } if (listen(socket_fd, 1) == -1) { fprintf(stderr, "remote_bitbang failed to listen on socket: %s (%d)\n", strerror(errno), errno); abort(); } socklen_t addrlen = sizeof(addr); if (getsockname(socket_fd, (struct sockaddr ) &addr, &addrlen) == -1) { fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n", strerror(errno), errno); abort(); } printf("Listening for remote bitbang connection on port %d.\n", ntohs(addr.sin_port)); fflush(stdout); } void remote_bitbang_t::accept() { client_fd = ::accept(socket_fd, NULL, NULL); if (client_fd == -1) { if (errno == EAGAIN) { // No client waiting to connect right now. } else { fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno), errno); abort(); } } else { fcntl(client_fd, F_SETFL, O_NONBLOCK); } } void remote_bitbang_t::tick() { if (client_fd > 0) { execute_commands(); } else { this->accept(); } } void remote_bitbang_t::execute_commands() { static char send_buf[buf_size]; unsigned total_processed = 0; bool quit = false; bool in_rti = tap->state() == RUN_TEST_IDLE; bool entered_rti = false; while (1) { if (recv_start < recv_end) { unsigned send_offset = 0; while (recv_start < recv_end) { uint8_t command = recv_buf[recv_start]; switch (command) { case 'B': / fprintf(stderr, "BLINK\n"); / break; case 'b': / fprintf(stderr, "_______\n"); */ break; case 'r': tap->reset(); break; case '0': tap->set_pins(0, 0, 0); break; case '1': tap->set_pins(0, 0, 1); break; case '2': tap->set_pins(0, 1, 0); break; case '3': tap->set_pins(0, 1, 1); break; case '4': tap->set_pins(1, 0, 0); break; case '5': tap->set_pins(1, 0, 1); break; case '6': tap->set_pins(1, 1, 0); break; case '7': tap->set_pins(1, 1, 1); break; case 'R': send_buf[send_offset++] = tap->tdo() ? '1' : '0'; break; case 'Q': quit = true; break; default: fprintf(stderr, "remote_bitbang got unsupported command '%c'\n", command); } recv_start++; total_processed++; if (!in_rti && tap->state() == RUN_TEST_IDLE) { entered_rti = true; break; } in_rti = false; } unsigned sent = 0; while (sent < send_offset) { ssize_t bytes = write(client_fd, send_buf + sent, send_offset); if (bytes == -1) { fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno); abort(); } sent += bytes; } } if (total_processed > buf_size \|\| quit \|\| entered_rti) { // Don't go forever, because that could starve the main simulation. break; } recv_start = 0; recv_end = read(client_fd, recv_buf, buf_size); if (recv_end == -1) { if (errno == EAGAIN) { break; } else { fprintf(stderr, "remote_bitbang failed to read on socket: %s (%d)\n", strerror(errno), errno); abort(); } } if (quit) { fprintf(stderr, "Remote Bitbang received 'Q'\n"); } if (recv_end == 0 \|\| quit) { // The remote disconnected. fprintf(stderr, "Received nothing. Quitting.\n"); close(client_fd); client_fd = 0; break; } } }
#ifndef REMOTE_BITBANG_H #define REMOTE_BITBANG_H #include <stdint.h> #include "jtag_dtm.h" class remote_bitbang_t { public: // Create a new server, listening for connections from localhost on the given // port. remote_bitbang_t(uint16_t port, jtag_dtm_t tap); // Do a bit of work. void tick(); private: jtag_dtm_t tap; int socket_fd; int client_fd; static const ssize_t buf_size = 64 * 1024; char recv_buf[buf_size]; ssize_t recv_start, recv_end; // Check for a client connecting, and accept if there is one. void accept(); // Execute any commands the client has for us. void execute_commands(); }; #endif
AC_LANG_CPLUSPLUS AC_ARG_WITH(isa, [AS_HELP_STRING([--with-isa=RV64IMAFDC], [Sets the default RISC-V ISA])], AC_DEFINE_UNQUOTED([DEFAULT_ISA], "$withval", [Default value for --isa switch]), AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC", [Default value for --isa switch])) AC_SEARCH_LIBS([dlopen], [dl dld], [], [ AC_MSG_ERROR([unable to find the dlopen() function]) ]) AC_ARG_WITH([fesvr], [AS_HELP_STRING([--with-fesvr], [path to your fesvr installation if not in a standard location])], [ LDFLAGS="-L$withval/lib $LDFLAGS" CPPFLAGS="-I$withval/include $CPPFLAGS" ] ) AC_CHECK_LIB(fesvr, libfesvr_is_present, [], [AC_MSG_ERROR([libfesvr is required])], [-pthread]) AC_CHECK_LIB(pthread, pthread_create, [], [AC_MSG_ERROR([libpthread is required])]) AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit log generation])) AS_IF([test "x$enable_commitlog" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation]) ]) AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histogram generation])) AS_IF([test "x$enable_histogram" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation]) ]) AC_ARG_ENABLE([dirty], AS_HELP_STRING([--enable-dirty], [Enable hardware management of PTE accessed and dirty bits])) AS_IF([test "x$enable_dirty" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits]) ]) AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores])) AS_IF([test "x$enable_misaligned" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores]) ])
get_insn_list = $(shell grep ^DECLARE_INSN $(1) \| sed 's/DECLARE_INSN(\(.\),.,.)/\1/') get_opcode = $(shell grep ^DECLARE_INSN.\\\<$(2)\\\> $(1) \| sed 's/DECLARE_INSN(.,\(.\),.)/\1/') riscv_subproject_deps = \ softfloat \ riscv_install_prog_srcs = \ riscv_hdrs = \ common.h \ decode.h \ devices.h \ disasm.h \ dts.h \ mmu.h \ processor.h \ sim.h \ simif.h \ trap.h \ encoding.h \ cachesim.h \ memtracer.h \ tracer.h \ extension.h \ rocc.h \ insn_template.h \ mulhi.h \ debug_module.h \ debug_rom_defines.h \ remote_bitbang.h \ jtag_dtm.h \ riscv_precompiled_hdrs = \ insn_template.h \ riscv_srcs = \ processor.cc \ execute.cc \ dts.cc \ sim.cc \ interactive.cc \ trap.cc \ cachesim.cc \ mmu.cc \ disasm.cc \ extension.cc \ extensions.cc \ rocc.cc \ regnames.cc \ devices.cc \ rom.cc \ clint.cc \ uart.cc \ dump.cc \ debug_module.cc \ remote_bitbang.cc \ jtag_dtm.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = riscv_gen_hdrs = \ icache.h \ insn_list.h \ riscv_insn_list = \ add \ addi \ addiw \ addw \ amoadd_d \ amoadd_w \ amoand_d \ amoand_w \ amomax_d \ amomaxu_d \ amomaxu_w \ amomax_w \ amomin_d \ amominu_d \ amominu_w \ amomin_w \ amoor_d \ amoor_w \ amoswap_d \ amoswap_w \ amoxor_d \ amoxor_w \ and \ andi \ auipc \ beq \ bge \ bgeu \ blt \ bltu \ bne \ c_add \ c_addi4spn \ c_addi \ c_addw \ c_and \ c_andi \ c_beqz \ c_bnez \ c_ebreak \ c_fld \ c_fldsp \ c_flw \ c_flwsp \ c_fsd \ c_fsdsp \ c_fsw \ c_fswsp \ c_jal \ c_jalr \ c_j \ c_jr \ c_li \ c_lui \ c_lw \ c_lwsp \ c_mv \ c_or \ c_slli \ c_srai \ c_srli \ c_sub \ c_subw \ c_xor \ csrrc \ csrrci \ csrrs \ csrrsi \ csrrw \ csrrwi \ c_sw \ c_swsp \ div \ divu \ divuw \ divw \ dret \ ebreak \ ecall \ fadd_d \ fadd_q \ fadd_s \ fclass_d \ fclass_q \ fclass_s \ fcvt_d_l \ fcvt_d_lu \ fcvt_d_q \ fcvt_d_s \ fcvt_d_w \ fcvt_d_wu \ fcvt_l_d \ fcvt_l_q \ fcvt_l_s \ fcvt_lu_d \ fcvt_lu_q \ fcvt_lu_s \ fcvt_q_d \ fcvt_q_l \ fcvt_q_lu \ fcvt_q_s \ fcvt_q_w \ fcvt_q_wu \ fcvt_s_d \ fcvt_s_l \ fcvt_s_lu \ fcvt_s_q \ fcvt_s_w \ fcvt_s_wu \ fcvt_w_d \ fcvt_w_q \ fcvt_w_s \ fcvt_wu_d \ fcvt_wu_q \ fcvt_wu_s \ fdiv_d \ fdiv_q \ fdiv_s \ fence \ fence_i \ feq_d \ feq_q \ feq_s \ fld \ fle_d \ fle_q \ fle_s \ flq \ flt_d \ flt_q \ flt_s \ flw \ fmadd_d \ fmadd_q \ fmadd_s \ fmax_d \ fmax_q \ fmax_s \ fmin_d \ fmin_q \ fmin_s \ fmsub_d \ fmsub_q \ fmsub_s \ fmul_d \ fmul_q \ fmul_s \ fmv_d_x \ fmv_w_x \ fmv_x_d \ fmv_x_w \ fnmadd_d \ fnmadd_q \ fnmadd_s \ fnmsub_d \ fnmsub_q \ fnmsub_s \ fsd \ fsgnj_d \ fsgnj_q \ fsgnjn_d \ fsgnjn_q \ fsgnjn_s \ fsgnj_s \ fsgnjx_d \ fsgnjx_q \ fsgnjx_s \ fsq \ fsqrt_d \ fsqrt_q \ fsqrt_s \ fsub_d \ fsub_q \ fsub_s \ fsw \ jal \ jalr \ lb \ lbu \ ld \ lh \ lhu \ lr_d \ lr_w \ lui \ lw \ lwu \ mret \ mul \ mulh \ mulhsu \ mulhu \ mulw \ or \ ori \ rem \ remu \ remuw \ remw \ sb \ sc_d \ sc_w \ sd \ sfence_vma \ sh \ sll \ slli \ slliw \ sllw \ slt \ slti \ sltiu \ sltu \ sra \ srai \ sraiw \ sraw \ sret \ srl \ srli \ srliw \ srlw \ sub \ subw \ sw \ wfi \ xor \ xori \ riscv_gen_srcs = \ $(addsuffix .cc,$(riscv_insn_list)) icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h \| sed 's/. = \(.*\);/\1/'` icache.h: mmu.h $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp mv $@.tmp $@ insn_list.h: $(src_dir)/riscv/riscv.mk.in for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \ printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \ done > $@.tmp mv $@.tmp $@ $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc \| sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@ riscv_junk = \ $(riscv_gen_srcs) \
// See LICENSE for license details. #include "rocc.h" #include "trap.h" #include <cstdlib> #define customX(n) \ static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ { \ rocc_t* rocc = static_cast<rocc_t>(p->get_extension()); \ rocc_insn_union_t u; \ u.i = insn; \ reg_t xs1 = u.r.xs1 ? RS1 : -1; \ reg_t xs2 = u.r.xs2 ? RS2 : -1; \ reg_t xd = rocc->custom##n(u.r, xs1, xs2); \ if (u.r.xd) \ WRITE_RD(xd); \ return pc+4; \ } \ \ reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \ { \ illegal_instruction(); \ return 0; \ } customX(0) customX(1) customX(2) customX(3) std::vector<insn_desc_t> rocc_t::get_instructions() { std::vector<insn_desc_t> insns; insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0}); insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1}); insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2}); insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3}); return insns; } std::vector<disasm_insn_t> rocc_t::get_disasms() { std::vector<disasm_insn_t*> insns; return insns; }
#ifndef _RISCV_ROCC_H #define _RISCV_ROCC_H #include "extension.h" struct rocc_insn_t { unsigned opcode : 7; unsigned rd : 5; unsigned xs2 : 1; unsigned xs1 : 1; unsigned xd : 1; unsigned rs1 : 5; unsigned rs2 : 5; unsigned funct : 7; }; union rocc_insn_union_t { rocc_insn_t r; insn_t i; }; class rocc_t : public extension_t { public: virtual reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2); virtual reg_t custom1(rocc_insn_t insn, reg_t xs1, reg_t xs2); virtual reg_t custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2); virtual reg_t custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2); std::vector<insn_desc_t> get_instructions(); std::vector<disasm_insn_t*> get_disasms(); }; #endif
#include "devices.h" rom_device_t::rom_device_t(std::vector<char> data) : data(data) { } bool rom_device_t::load(reg_t addr, size_t len, uint8_t* bytes) { if (addr + len > data.size()) return false; memcpy(bytes, &data[addr], len); return true; } bool rom_device_t::store(reg_t addr, size_t len, const uint8_t* bytes) { return false; }
// See LICENSE for license details. #include "sim.h" #include "mmu.h" #include "dts.h" #include "remote_bitbang.h" #include <map> #include <iostream> #include <sstream> #include <climits> #include <cstdlib> #include <cassert> #include <signal.h> #include <unistd.h> #include <sys/wait.h> #include <sys/types.h> volatile bool ctrlc_pressed = false; static void handle_signal(int sig) { if (ctrlc_pressed) exit(-1); ctrlc_pressed = true; signal(sig, &handle_signal); } sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t>> mems, const std::vector<std::string>& args, std::vector<int> const hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication) : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))), start_pc(start_pc), current_step(0), current_proc(0), debug(false), histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits, require_authentication) { signal(SIGINT, &handle_signal); for (auto& x : mems) bus.add_device(x.first, x.second); debug_module.add_device(&bus); debug_mmu = new mmu_t(this, NULL); if (hartids.size() == 0) { for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, i, halted); } } else { if (hartids.size() != procs.size()) { std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl; exit(1); } for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, hartids[i], halted); } } clint.reset(new clint_t(procs)); bus.add_device(CLINT_BASE, clint.get()); uart.reset(new uart_t()); bus.add_device(UART_BASE, uart.get()); dump.reset(new dump_t()); bus.add_device(DUMP_BASE, dump.get()); } sim_t::~sim_t() { for (size_t i = 0; i < procs.size(); i++) delete procs[i]; delete debug_mmu; } void sim_thread_main(void arg) { ((sim_t)arg)->main(); } void sim_t::main() { if (!debug && log) set_procs_debug(true); while (!done()) { if (debug \|\| ctrlc_pressed) interactive(); else step(INTERLEAVE); if (remote_bitbang) { remote_bitbang->tick(); } } } int sim_t::run() { host = context_t::current(); target.init(sim_thread_main, this); return htif_t::run(); } void sim_t::step(size_t n) { for (size_t i = 0, steps = 0; i < n; i += steps) { steps = std::min(n - i, INTERLEAVE - current_step); procs[current_proc]->step(steps); current_step += steps; if (current_step == INTERLEAVE) { current_step = 0; procs[current_proc]->get_mmu()->yield_load_reservation(); if (++current_proc == procs.size()) { current_proc = 0; clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); } host->switch_to(); } } } void sim_t::set_debug(bool value) { debug = value; } void sim_t::set_log(bool value) { log = value; } void sim_t::set_histogram(bool value) { histogram_enabled = value; for (size_t i = 0; i < procs.size(); i++) { procs[i]->set_histogram(histogram_enabled); } } void sim_t::set_procs_debug(bool value) { for (size_t i=0; i< procs.size(); i++) procs[i]->set_debug(value); } bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t bytes) { if (addr + len < addr) return false; return bus.load(addr, len, bytes); } bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { if (addr + len < addr) return false; return bus.store(addr, len, bytes); } void sim_t::make_dtb() { start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; #include "bootrom.h" std::vector<char> rom((char)reset_vec, (char)reset_vec + sizeof(reset_vec)); // dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, procs, mems); // std::string dtb = dts_compile(dts); // rom.insert(rom.end(), dtb.begin(), dtb.end()); const int align = 0x1000; rom.resize((rom.size() + align - 1) / align * align); boot_rom.reset(new rom_device_t(rom)); bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } char* sim_t::addr_to_mem(reg_t addr) { auto desc = bus.find_device(addr); if (auto mem = dynamic_cast<mem_t>(desc.second)) if (addr - desc.first < mem->size()) return mem->contents() + (addr - desc.first); return NULL; } // htif void sim_t::reset() { if (dtb_enabled) make_dtb(); } void sim_t::idle() { target.switch_to(); } void sim_t::read_chunk(addr_t taddr, size_t len, void dst) { assert(len == 8); auto data = debug_mmu->load_uint64(taddr); memcpy(dst, &data, sizeof data); } void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) { assert(len == 8); uint64_t data; memcpy(&data, src, sizeof data); debug_mmu->store_uint64(taddr, data); } void sim_t::proc_reset(unsigned id) { debug_module.proc_reset(id); }
// See LICENSE for license details. #ifndef _RISCV_SIM_H #define _RISCV_SIM_H #include "processor.h" #include "devices.h" #include "debug_module.h" #include "simif.h" #include <fesvr/htif.h> #include <fesvr/context.h> #include <vector> #include <string> #include <memory> class mmu_t; class remote_bitbang_t; // this class encapsulates the processors and memory in a RISC-V machine. class sim_t : public htif_t, public simif_t { public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication); ~sim_t(); // run the simulation to completion int run(); void set_debug(bool value); void set_log(bool value); void set_histogram(bool value); void set_procs_debug(bool value); void set_dtb_enabled(bool value) { this->dtb_enabled = value; } void set_remote_bitbang(remote_bitbang_t remote_bitbang) { this->remote_bitbang = remote_bitbang; } const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } // Callback for processors to let the simulation know they were reset. void proc_reset(unsigned id); private: std::vector<std::pair<reg_t, mem_t>> mems; mmu_t debug_mmu; // debug port into main memory std::vector<processor_t> procs; reg_t start_pc; std::string dts; std::unique_ptr<rom_device_t> boot_rom; std::unique_ptr<clint_t> clint; std::unique_ptr<dump_t> dump; std::unique_ptr<uart_t> uart; bus_t bus; processor_t get_core(const std::string& i); void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; bool log; bool histogram_enabled; // provide a histogram of PCs bool dtb_enabled; remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines char* addr_to_mem(reg_t addr); bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); void make_dtb(); // presents a prompt for introspection into the simulation void interactive(); // functions that help implement interactive() void interactive_help(const std::string& cmd, const std::vector<std::string>& args); void interactive_quit(const std::string& cmd, const std::vector<std::string>& args); void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy); void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args); void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args); void interactive_reg(const std::string& cmd, const std::vector<std::string>& args); void interactive_freg(const std::string& cmd, const std::vector<std::string>& args); void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args); void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args); void interactive_pc(const std::string& cmd, const std::vector<std::string>& args); void interactive_mem(const std::string& cmd, const std::vector<std::string>& args); void interactive_str(const std::string& cmd, const std::vector<std::string>& args); void interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy); void interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args); void interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args); reg_t get_reg(const std::vector<std::string>& args); freg_t get_freg(const std::vector<std::string>& args); reg_t get_mem(const std::vector<std::string>& args); reg_t get_pc(const std::vector<std::string>& args); friend class processor_t; friend class mmu_t; friend class debug_module_t; // htif friend void sim_thread_main(void); void main(); context_t host; context_t target; void reset(); void idle(); void read_chunk(addr_t taddr, size_t len, void* dst); void write_chunk(addr_t taddr, size_t len, const void* src); size_t chunk_align() { return 8; } size_t chunk_max_size() { return 8; } public: // Initialize this after procs, because in debug_module_t::reset() we // enumerate processors, which segfaults if procs hasn't been initialized // yet. debug_module_t debug_module; }; extern volatile bool ctrlc_pressed; #endif
// See LICENSE for license details. #ifndef _RISCV_SIMIF_H #define _RISCV_SIMIF_H #include "decode.h" // this is the interface to the simulator used by the processors and memory class simif_t { public: // should return NULL for MMIO addresses virtual char* addr_to_mem(reg_t addr) = 0; // used for MMIO addresses virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) = 0; }; #endif
// See LICENSE for license details. #ifndef _RISCV_TRACER_H #define _RISCV_TRACER_H #include "processor.h" static inline void trace_opcode(processor_t* p, insn_bits_t opc, insn_t insn) { } #endif
// See LICENSE for license details. #include "trap.h" #include "processor.h" #include <cstdio> const char* trap_t::name() { const char* fmt = uint8_t(which) == which ? "trap #%u" : "interrupt #%u"; sprintf(_name, fmt, uint8_t(which)); return _name; }
// See LICENSE for license details. #ifndef _RISCV_TRAP_H #define _RISCV_TRAP_H #include "decode.h" #include <stdlib.h> struct state_t; class trap_t { public: trap_t(reg_t which) : which(which) {} virtual const char* name(); virtual bool has_tval() { return false; } virtual reg_t get_tval() { return 0; } reg_t cause() { return which; } private: char _name[16]; reg_t which; }; class mem_trap_t : public trap_t { public: mem_trap_t(reg_t which, reg_t tval) : trap_t(which), tval(tval) {} bool has_tval() override { return true; } reg_t get_tval() override { return tval; } private: reg_t tval; }; #define DECLARE_TRAP(n, x) class trap_##x : public trap_t { \ public: \ trap_##x() : trap_t(n) {} \ const char* name() { return "trap_"#x; } \ }; #define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \ public: \ trap_##x(reg_t tval) : mem_trap_t(n, tval) {} \ const char* name() { return "trap_"#x; } \ }; DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault) DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) DECLARE_MEM_TRAP(CAUSE_STORE_PAGE_FAULT, store_page_fault) #endif
#include "devices.h" #include "processor.h" #define RBR 0 #define THR 0 #define IER 1 #define IIR 2 #define FCR 2 #define LCR 3 #define MCR 4 #define LSR 5 #define MSR 6 #define SCR 7 #define DLL 0 #define DLM 1 #define THRE 5 // transmit holding register empty #define TEMT 6 // transmit holding register empty uart_t::uart_t() { dll = 0; dlm = 0; ier = 0; lcr = 0; mcr = 0; lsr = 0; msr = 0; scr = 0; } // set {char} 0x10000004 = 0x00 // set {char} 0x1000000C = 0x80 // set {char} 0x10000000 = 0x1B // set {char} 0x10000004 = 0x00 // set {char} 0x1000000C = 0x03 // set {char} 0x10000008 = 0xC7 bool uart_t::load(reg_t addr, size_t len, uint8_t* bytes) { // we do not support unaligned stores if ((addr & 0x3) != 0) { return false; } switch ((addr >> 0x2) & 0x7) { case THR: // access DLL if (lcr & 0x80) { bytes[0] = dll; } else { // TODO(zarubaf) // printf("%c", bytes[0]); bytes[0] = 0; } break; case IER: // access DLM if (lcr & 0x80) { bytes[0] = dlm; } else { bytes[0] = ier; } break; case IIR: if (fifo_enabled) { bytes[0] = 0xC0; } else { bytes[0] = 0x00; } break; case LCR: bytes[0] = lcr; break; case MCR: bytes[0] = mcr; break; case LSR: bytes[0] = lsr \| (1 << THRE) \| (1 << TEMT); break; case MSR: bytes[0] = msr; break; case SCR: bytes[0] = scr; break; } return true; } bool uart_t::store(reg_t addr, size_t len, const uint8_t* bytes) { // we do not support unaligned stores if ((addr & 0x3) != 0) { return false; } switch ((addr >> 0x2) & 0x7) { case THR: // access DLL if (lcr & 0x80) { dll = bytes[0]; } else { printf("%c", bytes[0]); } break; case IER: // access DLM if (lcr & 0x80) { dlm = bytes[0]; } else { ier = bytes[0] & 0xF; } break; case FCR: if (bytes[0] & 0x1) { fifo_enabled = true; } else { fifo_enabled = false; } break; case LCR: lcr = bytes[0]; break; case MCR: mcr = bytes[0] & 0x1F; break; case LSR: lsr = bytes[0]; break; case MSR: msr = bytes[0]; break; case SCR: scr = bytes[0]; break; } return true; }
WRITE_RD(sext_xlen(RS1 + RS2));
WRITE_RD(sext_xlen(RS1 + insn.i_imm()));
require_rv64; WRITE_RD(sext32(insn.i_imm() + RS1));
require_rv64; WRITE_RD(sext32(RS1 + RS2));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs + RS2; }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs + RS2; })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs & RS2; }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs \| RS2; }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs \| RS2; })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; })));
require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs ^ RS2; }));
require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs ^ RS2; })));
WRITE_RD(RS1 & RS2);
WRITE_RD(insn.i_imm() & RS1);
WRITE_RD(sext_xlen(insn.u_imm() + pc));
if(RS1 == RS2) set_pc(BRANCH_TARGET);
if(sreg_t(RS1) >= sreg_t(RS2)) set_pc(BRANCH_TARGET);
if(RS1 >= RS2) set_pc(BRANCH_TARGET);
if(sreg_t(RS1) < sreg_t(RS2)) set_pc(BRANCH_TARGET);
if(RS1 < RS2) set_pc(BRANCH_TARGET);
if(RS1 != RS2) set_pc(BRANCH_TARGET);
bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old & ~RS1); } WRITE_RD(sext_xlen(old)); serialize();
bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old & ~(reg_t)insn.rs1()); } WRITE_RD(sext_xlen(old)); serialize();
bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old \| RS1); } WRITE_RD(sext_xlen(old)); serialize();
bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old \| insn.rs1()); } WRITE_RD(sext_xlen(old)); serialize();
int csr = validate_csr(insn.csr(), true); reg_t old = p->get_csr(csr); p->set_csr(csr, RS1); WRITE_RD(sext_xlen(old)); serialize();
int csr = validate_csr(insn.csr(), true); reg_t old = p->get_csr(csr); p->set_csr(csr, insn.rs1()); WRITE_RD(sext_xlen(old)); serialize();
require_extension('C'); require(insn.rvc_rs2() != 0); WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
require_extension('C'); WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm()));
require_extension('C'); require(insn.rvc_addi4spn_imm() != 0); WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm()));
require_extension('C'); require_rv64; WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S));

prefix=@prefix@ exec_prefix=@prefix@ libdir=${prefix}/@libdir@ includedir=${prefix}/@includedir@ Name: riscv-spike_main Description: RISC-V ISA simulator library Version: git Depends: riscv-riscv riscv-softfloat Libs: -Wl,-rpath,${libdir} -L${libdir} -lspike_main Cflags: -I${includedir} URL: http://riscv.org/download.html#tab_spike

/debug_rom /debug_rom32 /debug_rom64 /debug_rom32.h /debug_rom64.h

static const unsigned char debug_rom_raw[] = { 0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x40, 0x05, 0x6f, 0x00, 0x40, 0x03, 0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00, 0x63, 0x10, 0x04, 0x02, 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x24, 0x00, 0xe3, 0x18, 0x04, 0xfc, 0x6f, 0xf0, 0xdf, 0xfd, 0x23, 0x26, 0x00, 0x10, 0x73, 0x00, 0x10, 0x00, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x22, 0x00, 0x10, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00, 0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b }; static const unsigned int debug_rom_raw_len = 104;

// See LICENSE.SiFive for license details. #include "riscv/encoding.h" #include "riscv/debug_rom_defines.h" .option norvc .global entry .global exception // Entry location on ebreak, Halt, or Breakpoint // It is the same for all harts. They branch when // their GO or RESUME bit is set. entry: jal zero, _entry resume: jal zero, _resume exception: jal zero, _exception _entry: // This fence is required because the execution may have written something // into the Abstract Data or Program Buffer registers. fence csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID // We continue to let the hart know that we are halted in order that // a DM which was reset is still made aware that a hart is halted. // We keep checking both whether there is something the debugger wants // us to do, or whether we should resume. entry_loop: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_HALTED(zero) lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) bnez s0, going csrr s0, CSR_MHARTID lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME) bnez s0, resume jal zero, entry_loop _exception: sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. ebreak going: csrr s0, CSR_DSCRATCH // Restore s0 here sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. fence fence.i jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM, // so we use fence and fence.i for safety. (rocket-chip doesn't have this // because jalr is special there) _resume: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. csrr s0, CSR_DSCRATCH // Restore s0 dret // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT. .section .whereto whereto: nop // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer, // or jal x0 resume, as desired. // Debug Module state machine tracks what is 'desired'. // We don't need/want to use jalr here because all of the // Variable ROM contents are set by // Debug Module before setting the OK_GO byte.

OUTPUT_ARCH( "riscv" ) ENTRY( entry ) SECTIONS { .whereto 0x300 : { *(.whereto) } . = 0x800; .text : { *(.text) } _end = .; }

# Recursive make is bad, but in this case we're cross compiling which is a # pretty unusual use case. CC = $(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy COMPILE = $(CC) -nostdlib -nostartfiles -I.. -Tlink.ld ELFS = debug_rom DEPS = debug_rom.S link.ld ../riscv/debug_rom_defines.h ../riscv/encoding.h all: $(patsubst %,%.h,$(ELFS)) %.h: %.raw xxd -i $^ | sed "s/^unsigned/static const unsigned/" > $@ %.raw: % $(OBJCOPY) -O binary --only-section .text $^ $@ debug_rom: $(DEPS) $(COMPILE) -o $@ $^ clean: rm -f $(ELFS) debug_rom*.raw debug_rom.h

#include "rocc.h" #include "mmu.h" #include <cstring> class dummy_rocc_t : public rocc_t { public: const char* name() { return "dummy_rocc"; } reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2) { reg_t prev_acc = acc[insn.rs2]; if (insn.rs2 >= num_acc) illegal_instruction(); switch (insn.funct) { case 0: // acc <- xs1 acc[insn.rs2] = xs1; break; case 1: // xd <- acc (the only real work is the return statement below) break; case 2: // acc[rs2] <- Mem[xs1] acc[insn.rs2] = p->get_mmu()->load_uint64(xs1); break; case 3: // acc[rs2] <- accX + xs1 acc[insn.rs2] += xs1; break; default: illegal_instruction(); } return prev_acc; // in all cases, xd <- previous value of acc[rs2] } dummy_rocc_t() { memset(acc, 0, sizeof(acc)); } private: static const int num_acc = 4; reg_t acc[num_acc]; }; REGISTER_EXTENSION(dummy_rocc, []() { return new dummy_rocc_t; })

dummy_rocc_subproject_deps = \ spike_main \ riscv \ softfloat \ dummy_rocc_srcs = \ dummy_rocc.cc \

// The following is a RISC-V program to test the functionality of the // dummy RoCC accelerator. // Compile with riscv64-unknown-elf-gcc dummy_rocc_test.c // Run with spike --extension=dummy_rocc pk a.out #include <assert.h> #include <stdio.h> #include <stdint.h> int main() { uint64_t x = 123, y = 456, z = 0; // load x into accumulator 2 (funct=0) asm volatile ("custom0 x0, %0, 2, 0" : : "r"(x)); // read it back into z (funct=1) to verify it asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); assert(z == x); // accumulate 456 into it (funct=3) asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y)); // verify it asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); assert(z == x+y); // do it all again, but initialize acc2 via memory this time (funct=2) asm volatile ("custom0 x0, %0, 2, 2" : : "r"(&x)); asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y)); asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); assert(z == x+y); printf("success!\n"); }

// Auto-generated code const int reset_vec_size = 372; uint32_t reset_vec[reset_vec_size] = { 0x00100413, 0x01f41413, 0xf1402573, 0x00000597, 0x07458593, 0x00040067, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf1402573, 0x00000597, 0x03c58593, 0x10500073, 0xffdff06f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xedfe0dd0, 0x4a050000, 0x38000000, 0x44040000, 0x28000000, 0x11000000, 0x10000000, 0x00000000, 0x06010000, 0x0c040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, 0x03000000, 0x04000000, 0x00000000, 0x02000000, 0x03000000, 0x04000000, 0x0f000000, 0x02000000, 0x03000000, 0x14000000, 0x1b000000, 0x2c687465, 0x61697261, 0x622d656e, 0x2d657261, 0x00766564, 0x03000000, 0x10000000, 0x26000000, 0x2c687465, 0x61697261, 0x622d656e, 0x00657261, 0x01000000, 0x73757063, 0x00000000, 0x03000000, 0x04000000, 0x00000000, 0x01000000, 0x03000000, 0x04000000, 0x0f000000, 0x00000000, 0x03000000, 0x04000000, 0x2c000000, 0x00800000, 0x01000000, 0x40757063, 0x00000030, 0x03000000, 0x04000000, 0x3f000000, 0x80f0fa02, 0x03000000, 0x04000000, 0x4f000000, 0x00757063, 0x03000000, 0x04000000, 0x5b000000, 0x00000000, 0x03000000, 0x05000000, 0x5f000000, 0x79616b6f, 0x00000000, 0x03000000, 0x12000000, 0x1b000000, 0x2c687465, 0x69726120, 0x00656e61, 0x63736972, 0x00000076, 0x03000000, 0x0b000000, 0x66000000, 0x34367672, 0x66616d69, 0x00006364, 0x03000000, 0x0b000000, 0x70000000, 0x63736972, 0x76732c76, 0x00003933, 0x03000000, 0x00000000, 0x79000000, 0x01000000, 0x65746e69, 0x70757272, 0x6f632d74, 0x6f72746e, 0x72656c6c, 0x00000000, 0x03000000, 0x04000000, 0x83000000, 0x01000000, 0x03000000, 0x00000000, 0x94000000, 0x03000000, 0x0f000000, 0x1b000000, 0x63736972, 0x70632c76, 0x6e692d75, 0x00006374, 0x03000000, 0x04000000, 0xa9000000, 0x01000000, 0x02000000, 0x02000000, 0x02000000, 0x01000000, 0x6f6d656d, 0x38407972, 0x30303030, 0x00303030, 0x03000000, 0x07000000, 0x4f000000, 0x6f6d656d, 0x00007972, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000080, 0x00000000, 0x00000010, 0x02000000, 0x01000000, 0x00636f73, 0x03000000, 0x04000000, 0x00000000, 0x02000000, 0x03000000, 0x04000000, 0x0f000000, 0x02000000, 0x03000000, 0x1f000000, 0x1b000000, 0x2c687465, 0x61697261, 0x622d656e, 0x2d657261, 0x00636f73, 0x706d6973, 0x622d656c, 0x00007375, 0x03000000, 0x00000000, 0xb1000000, 0x01000000, 0x6e696c63, 0x30324074, 0x30303030, 0x00000030, 0x03000000, 0x0d000000, 0x1b000000, 0x63736972, 0x6c632c76, 0x30746e69, 0x00000000, 0x03000000, 0x10000000, 0xb8000000, 0x01000000, 0x03000000, 0x01000000, 0x07000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000002, 0x00000000, 0x00000c00, 0x03000000, 0x08000000, 0xcc000000, 0x746e6f63, 0x006c6f72, 0x02000000, 0x01000000, 0x74726175, 0x30303140, 0x30303030, 0x00000030, 0x03000000, 0x09000000, 0x1b000000, 0x3631736e, 0x61303535, 0x00000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000010, 0x00000000, 0x00100000, 0x03000000, 0x04000000, 0x3f000000, 0x80f0fa02, 0x03000000, 0x04000000, 0xd6000000, 0x00c20100, 0x03000000, 0x04000000, 0xe4000000, 0x01000000, 0x03000000, 0x04000000, 0xef000000, 0x02000000, 0x03000000, 0x04000000, 0xf9000000, 0x04000000, 0x02000000, 0x01000000, 0x656d6974, 0x38314072, 0x30303030, 0x00003030, 0x03000000, 0x0f000000, 0x1b000000, 0x706c7570, 0x6270612c, 0x6d69745f, 0x00007265, 0x03000000, 0x10000000, 0xe4000000, 0x04000000, 0x05000000, 0x06000000, 0x07000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000018, 0x00000000, 0x00100000, 0x03000000, 0x08000000, 0xcc000000, 0x746e6f63, 0x006c6f72, 0x02000000, 0x02000000, 0x02000000, 0x09000000, 0x64646123, 0x73736572, 0x6c65632d, 0x2300736c, 0x657a6973, 0x6c65632d, 0x6300736c, 0x61706d6f, 0x6c626974, 0x6f6d0065, 0x006c6564, 0x656d6974, 0x65736162, 0x6572662d, 0x6e657571, 0x63007963, 0x6b636f6c, 0x6572662d, 0x6e657571, 0x64007963, 0x63697665, 0x79745f65, 0x72006570, 0x73006765, 0x75746174, 0x69720073, 0x2c766373, 0x00617369, 0x2d756d6d, 0x65707974, 0x626c7400, 0x6c70732d, 0x23007469, 0x65746e69, 0x70757272, 0x65632d74, 0x00736c6c, 0x65746e69, 0x70757272, 0x6f632d74, 0x6f72746e, 0x72656c6c, 0x61687000, 0x656c646e, 0x6e617200, 0x00736567, 0x65746e69, 0x70757272, 0x652d7374, 0x6e657478, 0x00646564, 0x2d676572, 0x656d616e, 0x75630073, 0x6e657272, 0x70732d74, 0x00646565, 0x65746e69, 0x70757272, 0x72007374, 0x732d6765, 0x74666968, 0x67657200, 0x2d6f692d, 0x74646977, 0x00000068, 0x00000000 };

// See LICENSE for license details. #include "cachesim.h" #include "common.h" #include <cstdlib> #include <iostream> #include <iomanip> cache_sim_t::cache_sim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name) : sets(_sets), ways(_ways), linesz(_linesz), name(_name), log(false) { init(); } static void help() { std::cerr << "Cache configurations must be of the form" << std::endl; std::cerr << " sets:ways:blocksize" << std::endl; std::cerr << "where sets, ways, and blocksize are positive integers, with" << std::endl; std::cerr << "sets and blocksize both powers of two and blocksize at least 8." << std::endl; exit(1); } cache_sim_t* cache_sim_t::construct(const char* config, const char* name) { const char* wp = strchr(config, ':'); if (!wp++) help(); const char* bp = strchr(wp, ':'); if (!bp++) help(); size_t sets = atoi(std::string(config, wp).c_str()); size_t ways = atoi(std::string(wp, bp).c_str()); size_t linesz = atoi(bp); if (ways > 4 /* empirical */ && sets == 1) return new fa_cache_sim_t(ways, linesz, name); return new cache_sim_t(sets, ways, linesz, name); } void cache_sim_t::init() { if(sets == 0 || (sets & (sets-1))) help(); if(linesz < 8 || (linesz & (linesz-1))) help(); idx_shift = 0; for (size_t x = linesz; x>1; x >>= 1) idx_shift++; tags = new uint64_t[sets*ways](); read_accesses = 0; read_misses = 0; bytes_read = 0; write_accesses = 0; write_misses = 0; bytes_written = 0; writebacks = 0; miss_handler = NULL; } cache_sim_t::cache_sim_t(const cache_sim_t& rhs) : sets(rhs.sets), ways(rhs.ways), linesz(rhs.linesz), idx_shift(rhs.idx_shift), name(rhs.name), log(false) { tags = new uint64_t[sets*ways]; memcpy(tags, rhs.tags, sets*ways*sizeof(uint64_t)); } cache_sim_t::~cache_sim_t() { print_stats(); delete [] tags; } void cache_sim_t::print_stats() { if(read_accesses + write_accesses == 0) return; float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses); std::cout << std::setprecision(3) << std::fixed; std::cout << name << " "; std::cout << "Bytes Read: " << bytes_read << std::endl; std::cout << name << " "; std::cout << "Bytes Written: " << bytes_written << std::endl; std::cout << name << " "; std::cout << "Read Accesses: " << read_accesses << std::endl; std::cout << name << " "; std::cout << "Write Accesses: " << write_accesses << std::endl; std::cout << name << " "; std::cout << "Read Misses: " << read_misses << std::endl; std::cout << name << " "; std::cout << "Write Misses: " << write_misses << std::endl; std::cout << name << " "; std::cout << "Writebacks: " << writebacks << std::endl; std::cout << name << " "; std::cout << "Miss Rate: " << mr << '%' << std::endl; } uint64_t* cache_sim_t::check_tag(uint64_t addr) { size_t idx = (addr >> idx_shift) & (sets-1); size_t tag = (addr >> idx_shift) | VALID; for (size_t i = 0; i < ways; i++) if (tag == (tags[idx*ways + i] & ~DIRTY)) return &tags[idx*ways + i]; return NULL; } uint64_t cache_sim_t::victimize(uint64_t addr) { size_t idx = (addr >> idx_shift) & (sets-1); size_t way = lfsr.next() % ways; uint64_t victim = tags[idx*ways + way]; tags[idx*ways + way] = (addr >> idx_shift) | VALID; return victim; } void cache_sim_t::access(uint64_t addr, size_t bytes, bool store) { store ? write_accesses++ : read_accesses++; (store ? bytes_written : bytes_read) += bytes; uint64_t* hit_way = check_tag(addr); if (likely(hit_way != NULL)) { if (store) *hit_way |= DIRTY; return; } store ? write_misses++ : read_misses++; if (log) { std::cerr << name << " " << (store ? "write" : "read") << " miss 0x" << std::hex << addr << std::endl; } uint64_t victim = victimize(addr); if ((victim & (VALID | DIRTY)) == (VALID | DIRTY)) { uint64_t dirty_addr = (victim & ~(VALID | DIRTY)) << idx_shift; if (miss_handler) miss_handler->access(dirty_addr, linesz, true); writebacks++; } if (miss_handler) miss_handler->access(addr & ~(linesz-1), linesz, false); if (store) *check_tag(addr) |= DIRTY; } fa_cache_sim_t::fa_cache_sim_t(size_t ways, size_t linesz, const char* name) : cache_sim_t(1, ways, linesz, name) { } uint64_t* fa_cache_sim_t::check_tag(uint64_t addr) { auto it = tags.find(addr >> idx_shift); return it == tags.end() ? NULL : &it->second; } uint64_t fa_cache_sim_t::victimize(uint64_t addr) { uint64_t old_tag = 0; if (tags.size() == ways) { auto it = tags.begin(); std::advance(it, lfsr.next() % ways); old_tag = it->second; tags.erase(it); } tags[addr >> idx_shift] = (addr >> idx_shift) | VALID; return old_tag; }

// See LICENSE for license details. #ifndef _RISCV_CACHE_SIM_H #define _RISCV_CACHE_SIM_H #include "memtracer.h" #include <cstring> #include <string> #include <map> #include <cstdint> class lfsr_t { public: lfsr_t() : reg(1) {} lfsr_t(const lfsr_t& lfsr) : reg(lfsr.reg) {} uint32_t next() { return reg = (reg>>1)^(-(reg&1) & 0xd0000001); } private: uint32_t reg; }; class cache_sim_t { public: cache_sim_t(size_t sets, size_t ways, size_t linesz, const char* name); cache_sim_t(const cache_sim_t& rhs); virtual ~cache_sim_t(); void access(uint64_t addr, size_t bytes, bool store); void print_stats(); void set_miss_handler(cache_sim_t* mh) { miss_handler = mh; } void set_log(bool _log) { log = _log; } static cache_sim_t* construct(const char* config, const char* name); protected: static const uint64_t VALID = 1ULL << 63; static const uint64_t DIRTY = 1ULL << 62; virtual uint64_t* check_tag(uint64_t addr); virtual uint64_t victimize(uint64_t addr); lfsr_t lfsr; cache_sim_t* miss_handler; size_t sets; size_t ways; size_t linesz; size_t idx_shift; uint64_t* tags; uint64_t read_accesses; uint64_t read_misses; uint64_t bytes_read; uint64_t write_accesses; uint64_t write_misses; uint64_t bytes_written; uint64_t writebacks; std::string name; bool log; void init(); }; class fa_cache_sim_t : public cache_sim_t { public: fa_cache_sim_t(size_t ways, size_t linesz, const char* name); uint64_t* check_tag(uint64_t addr); uint64_t victimize(uint64_t addr); private: static bool cmp(uint64_t a, uint64_t b); std::map<uint64_t, uint64_t> tags; }; class cache_memtracer_t : public memtracer_t { public: cache_memtracer_t(const char* config, const char* name) { cache = cache_sim_t::construct(config, name); } ~cache_memtracer_t() { delete cache; } void set_miss_handler(cache_sim_t* mh) { cache->set_miss_handler(mh); } void set_log(bool log) { cache->set_log(log); } protected: cache_sim_t* cache; }; class icache_sim_t : public cache_memtracer_t { public: icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {} bool interested_in_range(uint64_t begin, uint64_t end, access_type type) { return type == FETCH; } void trace(uint64_t addr, size_t bytes, access_type type) { if (type == FETCH) cache->access(addr, bytes, false); } }; class dcache_sim_t : public cache_memtracer_t { public: dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {} bool interested_in_range(uint64_t begin, uint64_t end, access_type type) { return type == LOAD || type == STORE; } void trace(uint64_t addr, size_t bytes, access_type type) { if (type == LOAD || type == STORE) cache->access(addr, bytes, type == STORE); } }; #endif

#include "devices.h" #include "processor.h" clint_t::clint_t(std::vector<processor_t*>& procs) : procs(procs), mtimecmp(procs.size()) { } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi */ #define MSIP_BASE 0x0 #define MTIMECMP_BASE 0x4000 #define MTIME_BASE 0xbff8 void clint_t::reset() { mtime = 0; } bool clint_t::load(reg_t addr, size_t len, uint8_t* bytes) { if (addr >= MSIP_BASE && addr + len <= MSIP_BASE + procs.size()*sizeof(msip_t)) { std::vector<msip_t> msip(procs.size()); for (size_t i = 0; i < procs.size(); ++i) msip[i] = !!(procs[i]->state.mip & MIP_MSIP); memcpy(bytes, (uint8_t*)&msip[0] + addr - MSIP_BASE, len); } else if (addr >= MTIMECMP_BASE && addr + len <= MTIMECMP_BASE + procs.size()*sizeof(mtimecmp_t)) { memcpy(bytes, (uint8_t*)&mtimecmp[0] + addr - MTIMECMP_BASE, len); } else if (addr >= MTIME_BASE && addr + len <= MTIME_BASE + sizeof(mtime_t)) { memcpy(bytes, (uint8_t*)&mtime + addr - MTIME_BASE, len); } else { return false; } return true; } bool clint_t::store(reg_t addr, size_t len, const uint8_t* bytes) { if (addr >= MSIP_BASE && addr + len <= MSIP_BASE + procs.size()*sizeof(msip_t)) { std::vector<msip_t> msip(procs.size()); std::vector<msip_t> mask(procs.size(), 0); memcpy((uint8_t*)&msip[0] + addr - MSIP_BASE, bytes, len); memset((uint8_t*)&mask[0] + addr - MSIP_BASE, 0xff, len); for (size_t i = 0; i < procs.size(); ++i) { if (!(mask[i] & 0xFF)) continue; procs[i]->state.mip &= ~MIP_MSIP; if (!!(msip[i] & 1)) procs[i]->state.mip |= MIP_MSIP; } } else if (addr >= MTIMECMP_BASE && addr + len <= MTIMECMP_BASE + procs.size()*sizeof(mtimecmp_t)) { memcpy((uint8_t*)&mtimecmp[0] + addr - MTIMECMP_BASE, bytes, len); } else if (addr >= MTIME_BASE && addr + len <= MTIME_BASE + sizeof(mtime_t)) { memcpy((uint8_t*)&mtime + addr - MTIME_BASE, bytes, len); } else { return false; } increment(0); return true; } void clint_t::increment(reg_t inc) { mtime += inc; for (size_t i = 0; i < procs.size(); i++) { procs[i]->state.mip &= ~MIP_MTIP; if (mtime >= mtimecmp[i]) procs[i]->state.mip |= MIP_MTIP; } }

// See LICENSE for license details. #ifndef _RISCV_COMMON_H #define _RISCV_COMMON_H #define likely(x) __builtin_expect(x, 1) #define unlikely(x) __builtin_expect(x, 0) #endif

#define DTM_IDCODE 0x01 /* * Identifies the release version of this part. */ #define DTM_IDCODE_VERSION_OFFSET 28 #define DTM_IDCODE_VERSION_LENGTH 4 #define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET) /* * Identifies the designer's part number of this part. */ #define DTM_IDCODE_PARTNUMBER_OFFSET 12 #define DTM_IDCODE_PARTNUMBER_LENGTH 16 #define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET) /* * Identifies the designer/manufacturer of this part. Bits 6:0 must be * bits 6:0 of the designer/manufacturer's Identification Code as * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 * count of the number of continuation characters (0x7f) in that same * Identification Code. */ #define DTM_IDCODE_MANUFID_OFFSET 1 #define DTM_IDCODE_MANUFID_LENGTH 11 #define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET) #define DTM_IDCODE_1_OFFSET 0 #define DTM_IDCODE_1_LENGTH 1 #define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET) #define DTM_DTMCS 0x10 /* * Writing 1 to this bit does a hard reset of the DTM, * causing the DTM to forget about any outstanding DMI transactions. * In general this should only be used when the Debugger has * reason to expect that the outstanding DMI transaction will never * complete (e.g. a reset condition caused an inflight DMI transaction to * be cancelled). */ #define DTM_DTMCS_DMIHARDRESET_OFFSET 17 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1 #define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET) /* * Writing 1 to this bit clears the sticky error state * and allows the DTM to retry or complete the previous * transaction. */ #define DTM_DTMCS_DMIRESET_OFFSET 16 #define DTM_DTMCS_DMIRESET_LENGTH 1 #define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET) /* * This is a hint to the debugger of the minimum number of * cycles a debugger should spend in * Run-Test/Idle after every DMI scan to avoid a `busy' * return code (\Fdmistat of 3). A debugger must still * check \Fdmistat when necessary. * * 0: It is not necessary to enter Run-Test/Idle at all. * * 1: Enter Run-Test/Idle and leave it immediately. * * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. * * And so on. */ #define DTM_DTMCS_IDLE_OFFSET 12 #define DTM_DTMCS_IDLE_LENGTH 3 #define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET) /* * 0: No error. * * 1: Reserved. Interpret the same as 2. * * 2: An operation failed (resulted in \Fop of 2). * * 3: An operation was attempted while a DMI access was still in * progress (resulted in \Fop of 3). */ #define DTM_DTMCS_DMISTAT_OFFSET 10 #define DTM_DTMCS_DMISTAT_LENGTH 2 #define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET) /* * The size of \Faddress in \Rdmi. */ #define DTM_DTMCS_ABITS_OFFSET 4 #define DTM_DTMCS_ABITS_LENGTH 6 #define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET) /* * 0: Version described in spec version 0.11. * * 1: Version described in spec version 0.13 (and later?), which * reduces the DMI data width to 32 bits. * * 15: Version not described in any available version of this spec. */ #define DTM_DTMCS_VERSION_OFFSET 0 #define DTM_DTMCS_VERSION_LENGTH 4 #define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET) #define DTM_DMI 0x11 /* * Address used for DMI access. In Update-DR this value is used * to access the DM over the DMI. */ #define DTM_DMI_ADDRESS_OFFSET 34 #define DTM_DMI_ADDRESS_LENGTH abits #define DTM_DMI_ADDRESS (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET) /* * The data to send to the DM over the DMI during Update-DR, and * the data returned from the DM as a result of the previous operation. */ #define DTM_DMI_DATA_OFFSET 2 #define DTM_DMI_DATA_LENGTH 32 #define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET) /* * When the debugger writes this field, it has the following meaning: * * 0: Ignore \Fdata and \Faddress. (nop) * * Don't send anything over the DMI during Update-DR. * This operation should never result in a busy or error response. * The address and data reported in the following Capture-DR * are undefined. * * 1: Read from \Faddress. (read) * * 2: Write \Fdata to \Faddress. (write) * * 3: Reserved. * * When the debugger reads this field, it means the following: * * 0: The previous operation completed successfully. * * 1: Reserved. * * 2: A previous operation failed. The data scanned into \Rdmi in * this access will be ignored. This status is sticky and can be * cleared by writing \Fdmireset in \Rdtmcs. * * This indicates that the DM itself responded with an error. * Note: there are no specified cases in which the DM would * respond with an error, and DMI is not required to support * returning errors. * * 3: An operation was attempted while a DMI request is still in * progress. The data scanned into \Rdmi in this access will be * ignored. This status is sticky and can be cleared by writing * \Fdmireset in \Rdtmcs. If a debugger sees this status, it * needs to give the target more TCK edges between Update-DR and * Capture-DR. The simplest way to do that is to add extra transitions * in Run-Test/Idle. * * (The DTM, DM, and/or component may be in different clock domains, * so synchronization may be required. Some relatively fixed number of * TCK ticks may be needed for the request to reach the DM, complete, * and for the response to be synchronized back into the TCK domain.) */ #define DTM_DMI_OP_OFFSET 0 #define DTM_DMI_OP_LENGTH 2 #define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET) #define CSR_DCSR 0x7b0 /* * 0: There is no external debug support. * * 4: External debug support exists as it is described in this document. * * 15: There is external debug support, but it does not conform to any * available version of this spec. */ #define CSR_DCSR_XDEBUGVER_OFFSET 28 #define CSR_DCSR_XDEBUGVER_LENGTH 4 #define CSR_DCSR_XDEBUGVER (0xfU << CSR_DCSR_XDEBUGVER_OFFSET) /* * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode. */ #define CSR_DCSR_EBREAKM_OFFSET 15 #define CSR_DCSR_EBREAKM_LENGTH 1 #define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET) /* * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode. */ #define CSR_DCSR_EBREAKS_OFFSET 13 #define CSR_DCSR_EBREAKS_LENGTH 1 #define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET) /* * When 1, {\tt ebreak} instructions in User/Application Mode enter * Debug Mode. */ #define CSR_DCSR_EBREAKU_OFFSET 12 #define CSR_DCSR_EBREAKU_LENGTH 1 #define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET) /* * 0: Interrupts are disabled during single stepping. * * 1: Interrupts are enabled during single stepping. * * Implementations may hard wire this bit to 0. * The debugger must read back the value it * writes to check whether the feature is supported. If not * supported, interrupt behavior can be emulated by the debugger. */ #define CSR_DCSR_STEPIE_OFFSET 11 #define CSR_DCSR_STEPIE_LENGTH 1 #define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET) /* * 0: Increment counters as usual. * * 1: Don't increment any counters while in Debug Mode or on {\tt * ebreak} instructions that cause entry into Debug Mode. These * counters include the {\tt cycle} and {\tt instret} CSRs. This is * preferred for most debugging scenarios. * * An implementation may choose not to support writing to this bit. * The debugger must read back the value it writes to check whether * the feature is supported. */ #define CSR_DCSR_STOPCOUNT_OFFSET 10 #define CSR_DCSR_STOPCOUNT_LENGTH 1 #define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET) /* * 0: Increment timers as usual. * * 1: Don't increment any hart-local timers while in Debug Mode. * * An implementation may choose not to support writing to this bit. * The debugger must read back the value it writes to check whether * the feature is supported. */ #define CSR_DCSR_STOPTIME_OFFSET 9 #define CSR_DCSR_STOPTIME_LENGTH 1 #define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET) /* * Explains why Debug Mode was entered. * * When there are multiple reasons to enter Debug Mode in a single * cycle, hardware should set \Fcause to the cause with the highest * priority. * * 1: An {\tt ebreak} instruction was executed. (priority 3) * * 2: The Trigger Module caused a breakpoint exception. (priority 4) * * 3: The debugger requested entry to Debug Mode. (priority 2) * * 4: The hart single stepped because \Fstep was set. (priority 1) * * Other values are reserved for future use. */ #define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_LENGTH 3 #define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET) /* * When 1, \Fmprv in \Rmstatus takes effect during debug mode. * When 0, it is ignored during debug mode. * Implementing this bit is optional. * If not implemented it should be tied to 0. */ #define CSR_DCSR_MPRVEN_OFFSET 4 #define CSR_DCSR_MPRVEN_LENGTH 1 #define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET) /* * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. * * Since an NMI can indicate a hardware error condition, * reliable debugging may no longer be possible once this bit becomes set. * This is implementation-dependent. */ #define CSR_DCSR_NMIP_OFFSET 3 #define CSR_DCSR_NMIP_LENGTH 1 #define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET) /* * When set and not in Debug Mode, the hart will only execute a single * instruction and then enter Debug Mode. * If the instruction does not complete due to an exception, * the hart will immediately enter Debug Mode before executing * the trap handler, with appropriate exception registers set. */ #define CSR_DCSR_STEP_OFFSET 2 #define CSR_DCSR_STEP_LENGTH 1 #define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET) /* * Contains the privilege level the hart was operating in when Debug * Mode was entered. The encoding is described in Table * \ref{tab:privlevel}. A debugger can change this value to change * the hart's privilege level when exiting Debug Mode. * * Not all privilege levels are supported on all harts. If the * encoding written is not supported or the debugger is not allowed to * change to it, the hart may change to any supported privilege level. */ #define CSR_DCSR_PRV_OFFSET 0 #define CSR_DCSR_PRV_LENGTH 2 #define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET) #define CSR_DPC 0x7b1 #define CSR_DPC_DPC_OFFSET 0 #define CSR_DPC_DPC_LENGTH MXLEN #define CSR_DPC_DPC (((1L<<MXLEN)-1) << CSR_DPC_DPC_OFFSET) #define CSR_DSCRATCH0 0x7b2 #define CSR_DSCRATCH1 0x7b3 #define CSR_TSELECT 0x7a0 #define CSR_TSELECT_INDEX_OFFSET 0 #define CSR_TSELECT_INDEX_LENGTH MXLEN #define CSR_TSELECT_INDEX (((1L<<MXLEN)-1) << CSR_TSELECT_INDEX_OFFSET) #define CSR_TDATA1 0x7a1 /* * 0: There is no trigger at this \Rtselect. * * 1: The trigger is a legacy SiFive address match trigger. These * should not be implemented and aren't further documented here. * * 2: The trigger is an address/data match trigger. The remaining bits * in this register act as described in \Rmcontrol. * * 3: The trigger is an instruction count trigger. The remaining bits * in this register act as described in \Ricount. * * 4: The trigger is an interrupt trigger. The remaining bits * in this register act as described in \Ritrigger. * * 5: The trigger is an exception trigger. The remaining bits * in this register act as described in \Retrigger. * * 15: This trigger exists (so enumeration shouldn't terminate), but * is not currently available. * * Other values are reserved for future use. * * When this field is written to an unsupported value, it takes on its * reset value instead. The reset value is any one of the types * supported by the trigger selected by \Rtselect. */ #define CSR_TDATA1_TYPE_OFFSET (MXLEN-4) #define CSR_TDATA1_TYPE_LENGTH 4 #define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET) /* * 0: Both Debug and M Mode can write the {\tt tdata} registers at the * selected \Rtselect. * * 1: Only Debug Mode can write the {\tt tdata} registers at the * selected \Rtselect. Writes from other modes are ignored. * * This bit is only writable from Debug Mode. */ #define CSR_TDATA1_DMODE_OFFSET (MXLEN-5) #define CSR_TDATA1_DMODE_LENGTH 1 #define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET) /* * Trigger-specific data. */ #define CSR_TDATA1_DATA_OFFSET 0 #define CSR_TDATA1_DATA_LENGTH (MXLEN - 5) #define CSR_TDATA1_DATA (((1L<<MXLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET) #define CSR_TDATA2 0x7a2 #define CSR_TDATA2_DATA_OFFSET 0 #define CSR_TDATA2_DATA_LENGTH MXLEN #define CSR_TDATA2_DATA (((1L<<MXLEN)-1) << CSR_TDATA2_DATA_OFFSET) #define CSR_TDATA3 0x7a3 #define CSR_TDATA3_DATA_OFFSET 0 #define CSR_TDATA3_DATA_LENGTH MXLEN #define CSR_TDATA3_DATA (((1L<<MXLEN)-1) << CSR_TDATA3_DATA_OFFSET) #define CSR_TINFO 0x7a4 /* * One bit for each possible \Ftype enumerated in \Rtdataone. Bit N * corresponds to type N. If the bit is set, then that type is * supported by the currently selected trigger. * * If the currently selected trigger doesn't exist, this field * contains 1. * * If \Ftype is not writable, this register may be unimplemented, in * which case reading it causes an illegal instruction exception. In * this case the debugger can read the only supported type from * \Rtdataone. */ #define CSR_TINFO_INFO_OFFSET 0 #define CSR_TINFO_INFO_LENGTH 16 #define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET) #define CSR_MCONTROL 0x7a1 #define CSR_MCONTROL_TYPE_OFFSET (MXLEN-4) #define CSR_MCONTROL_TYPE_LENGTH 4 #define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET) #define CSR_MCONTROL_DMODE_OFFSET (MXLEN-5) #define CSR_MCONTROL_DMODE_LENGTH 1 #define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET) /* * Specifies the largest naturally aligned powers-of-two (NAPOT) range * supported by the hardware when \Fmatch is 1. The value is the * logarithm base 2 of the * number of bytes in that range. A value of 0 indicates that only * exact value matches are supported (one byte range). A value of 63 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in * size. */ #define CSR_MCONTROL_MASKMAX_OFFSET (MXLEN-11) #define CSR_MCONTROL_MASKMAX_LENGTH 6 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET) /* * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ #define CSR_MCONTROL_HIT_OFFSET 20 #define CSR_MCONTROL_HIT_LENGTH 1 #define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET) /* * 0: Perform a match on the virtual address. * * 1: Perform a match on the data value loaded/stored, or the * instruction executed. */ #define CSR_MCONTROL_SELECT_OFFSET 19 #define CSR_MCONTROL_SELECT_LENGTH 1 #define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET) /* * 0: The action for this trigger will be taken just before the * instruction that triggered it is executed, but after all preceding * instructions are are committed. * * 1: The action for this trigger will be taken after the instruction * that triggered it is executed. It should be taken before the next * instruction is executed, but it is better to implement triggers and * not implement that suggestion than to not implement them at all. * * Most hardware will only implement one timing or the other, possibly * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit * primarily exists for the hardware to communicate to the debugger * what will happen. Hardware may implement the bit fully writable, in * which case the debugger has a little more control. * * Data load triggers with \Ftiming of 0 will result in the same load * happening again when the debugger lets the hart run. For data load * triggers, debuggers must first attempt to set the breakpoint with * \Ftiming of 1. * * A chain of triggers that don't all have the same \Ftiming value * will never fire (unless consecutive instructions match the * appropriate triggers). */ #define CSR_MCONTROL_TIMING_OFFSET 18 #define CSR_MCONTROL_TIMING_LENGTH 1 #define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET) /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_MCONTROL_ACTION_OFFSET 12 #define CSR_MCONTROL_ACTION_LENGTH 6 #define CSR_MCONTROL_ACTION (0x3fULL << CSR_MCONTROL_ACTION_OFFSET) /* * 0: When this trigger matches, the configured action is taken. * * 1: While this trigger does not match, it prevents the trigger with * the next index from matching. * * Because \Fchain affects the next trigger, hardware must zero it in * writes to \Rmcontrol that set \Fdmode to 0 if the next trigger has * \Fdmode of 1. * In addition hardware should ignore writes to \Rmcontrol that set * \Fdmode to 1 if the previous trigger has both \Fdmode of 0 and * \Fchain of 1. Debuggers must avoid the latter case by checking * \Fchain on the previous trigger if they're writing \Rmcontrol. * * Implementations that wish to limit the maximum length of a trigger * chain (eg. to meet timing requirements) may do so by zeroing * \Fchain in writes to \Rmcontrol that would make the chain too long. */ #define CSR_MCONTROL_CHAIN_OFFSET 11 #define CSR_MCONTROL_CHAIN_LENGTH 1 #define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET) /* * 0: Matches when the value equals \Rtdatatwo. * * 1: Matches when the top M bits of the value match the top M bits of * \Rtdatatwo. M is MXLEN-1 minus the index of the least-significant * bit containing 0 in \Rtdatatwo. * * 2: Matches when the value is greater than (unsigned) or equal to * \Rtdatatwo. * * 3: Matches when the value is less than (unsigned) \Rtdatatwo. * * 4: Matches when the lower half of the value equals the lower half * of \Rtdatatwo after the lower half of the value is ANDed with the * upper half of \Rtdatatwo. * * 5: Matches when the upper half of the value equals the lower half * of \Rtdatatwo after the upper half of the value is ANDed with the * upper half of \Rtdatatwo. * * Other values are reserved for future use. */ #define CSR_MCONTROL_MATCH_OFFSET 7 #define CSR_MCONTROL_MATCH_LENGTH 4 #define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET) /* * When set, enable this trigger in M mode. */ #define CSR_MCONTROL_M_OFFSET 6 #define CSR_MCONTROL_M_LENGTH 1 #define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET) /* * When set, enable this trigger in S mode. */ #define CSR_MCONTROL_S_OFFSET 4 #define CSR_MCONTROL_S_LENGTH 1 #define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET) /* * When set, enable this trigger in U mode. */ #define CSR_MCONTROL_U_OFFSET 3 #define CSR_MCONTROL_U_LENGTH 1 #define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET) /* * When set, the trigger fires on the virtual address or opcode of an * instruction that is executed. */ #define CSR_MCONTROL_EXECUTE_OFFSET 2 #define CSR_MCONTROL_EXECUTE_LENGTH 1 #define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET) /* * When set, the trigger fires on the virtual address or data of a store. */ #define CSR_MCONTROL_STORE_OFFSET 1 #define CSR_MCONTROL_STORE_LENGTH 1 #define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET) /* * When set, the trigger fires on the virtual address or data of a load. */ #define CSR_MCONTROL_LOAD_OFFSET 0 #define CSR_MCONTROL_LOAD_LENGTH 1 #define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET) #define CSR_ICOUNT 0x7a1 #define CSR_ICOUNT_TYPE_OFFSET (MXLEN-4) #define CSR_ICOUNT_TYPE_LENGTH 4 #define CSR_ICOUNT_TYPE (0xfULL << CSR_ICOUNT_TYPE_OFFSET) #define CSR_ICOUNT_DMODE_OFFSET (MXLEN-5) #define CSR_ICOUNT_DMODE_LENGTH 1 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET) /* * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ #define CSR_ICOUNT_HIT_OFFSET 24 #define CSR_ICOUNT_HIT_LENGTH 1 #define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET) /* * When count is decremented to 0, the trigger fires. Instead of * changing \Fcount from 1 to 0, it is also acceptable for hardware to * clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired * to 1 if this register just exists for single step. */ #define CSR_ICOUNT_COUNT_OFFSET 10 #define CSR_ICOUNT_COUNT_LENGTH 14 #define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET) /* * When set, every instruction completed or exception taken in M mode decrements \Fcount * by 1. */ #define CSR_ICOUNT_M_OFFSET 9 #define CSR_ICOUNT_M_LENGTH 1 #define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET) /* * When set, every instruction completed or exception taken in S mode decrements \Fcount * by 1. */ #define CSR_ICOUNT_S_OFFSET 7 #define CSR_ICOUNT_S_LENGTH 1 #define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET) /* * When set, every instruction completed or exception taken in U mode decrements \Fcount * by 1. */ #define CSR_ICOUNT_U_OFFSET 6 #define CSR_ICOUNT_U_LENGTH 1 #define CSR_ICOUNT_U (0x1ULL << CSR_ICOUNT_U_OFFSET) /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_ICOUNT_ACTION_OFFSET 0 #define CSR_ICOUNT_ACTION_LENGTH 6 #define CSR_ICOUNT_ACTION (0x3fULL << CSR_ICOUNT_ACTION_OFFSET) #define CSR_ITRIGGER 0x7a1 #define CSR_ITRIGGER_TYPE_OFFSET (MXLEN-4) #define CSR_ITRIGGER_TYPE_LENGTH 4 #define CSR_ITRIGGER_TYPE (0xfULL << CSR_ITRIGGER_TYPE_OFFSET) #define CSR_ITRIGGER_DMODE_OFFSET (MXLEN-5) #define CSR_ITRIGGER_DMODE_LENGTH 1 #define CSR_ITRIGGER_DMODE (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET) /* * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ #define CSR_ITRIGGER_HIT_OFFSET (MXLEN-6) #define CSR_ITRIGGER_HIT_LENGTH 1 #define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET) /* * When set, enable this trigger for interrupts that are taken from M * mode. */ #define CSR_ITRIGGER_M_OFFSET 9 #define CSR_ITRIGGER_M_LENGTH 1 #define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET) /* * When set, enable this trigger for interrupts that are taken from S * mode. */ #define CSR_ITRIGGER_S_OFFSET 7 #define CSR_ITRIGGER_S_LENGTH 1 #define CSR_ITRIGGER_S (0x1ULL << CSR_ITRIGGER_S_OFFSET) /* * When set, enable this trigger for interrupts that are taken from U * mode. */ #define CSR_ITRIGGER_U_OFFSET 6 #define CSR_ITRIGGER_U_LENGTH 1 #define CSR_ITRIGGER_U (0x1ULL << CSR_ITRIGGER_U_OFFSET) /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_ITRIGGER_ACTION_OFFSET 0 #define CSR_ITRIGGER_ACTION_LENGTH 6 #define CSR_ITRIGGER_ACTION (0x3fULL << CSR_ITRIGGER_ACTION_OFFSET) #define CSR_ETRIGGER 0x7a1 #define CSR_ETRIGGER_TYPE_OFFSET (MXLEN-4) #define CSR_ETRIGGER_TYPE_LENGTH 4 #define CSR_ETRIGGER_TYPE (0xfULL << CSR_ETRIGGER_TYPE_OFFSET) #define CSR_ETRIGGER_DMODE_OFFSET (MXLEN-5) #define CSR_ETRIGGER_DMODE_LENGTH 1 #define CSR_ETRIGGER_DMODE (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET) /* * If this optional bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any * time. The trigger's user can use this bit to determine which * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ #define CSR_ETRIGGER_HIT_OFFSET (MXLEN-6) #define CSR_ETRIGGER_HIT_LENGTH 1 #define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET) /* * When set, enable this trigger for exceptions that are taken from M * mode. */ #define CSR_ETRIGGER_M_OFFSET 9 #define CSR_ETRIGGER_M_LENGTH 1 #define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET) /* * When set, enable this trigger for exceptions that are taken from S * mode. */ #define CSR_ETRIGGER_S_OFFSET 7 #define CSR_ETRIGGER_S_LENGTH 1 #define CSR_ETRIGGER_S (0x1ULL << CSR_ETRIGGER_S_OFFSET) /* * When set, enable this trigger for exceptions that are taken from U * mode. */ #define CSR_ETRIGGER_U_OFFSET 6 #define CSR_ETRIGGER_U_LENGTH 1 #define CSR_ETRIGGER_U (0x1ULL << CSR_ETRIGGER_U_OFFSET) /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ #define CSR_ETRIGGER_ACTION_OFFSET 0 #define CSR_ETRIGGER_ACTION_LENGTH 6 #define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET) #define DMI_DMSTATUS 0x11 /* * If 1, then there is an implicit {\tt ebreak} instruction at the * non-existent word immediately after the Program Buffer. This saves * the debugger from having to write the {\tt ebreak} itself, and * allows the Program Buffer to be one word smaller. * * This must be 1 when \Fprogbufsize is 1. */ #define DMI_DMSTATUS_IMPEBREAK_OFFSET 22 #define DMI_DMSTATUS_IMPEBREAK_LENGTH 1 #define DMI_DMSTATUS_IMPEBREAK (0x1U << DMI_DMSTATUS_IMPEBREAK_OFFSET) /* * This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged. */ #define DMI_DMSTATUS_ALLHAVERESET_OFFSET 19 #define DMI_DMSTATUS_ALLHAVERESET_LENGTH 1 #define DMI_DMSTATUS_ALLHAVERESET (0x1U << DMI_DMSTATUS_ALLHAVERESET_OFFSET) /* * This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged. */ #define DMI_DMSTATUS_ANYHAVERESET_OFFSET 18 #define DMI_DMSTATUS_ANYHAVERESET_LENGTH 1 #define DMI_DMSTATUS_ANYHAVERESET (0x1U << DMI_DMSTATUS_ANYHAVERESET_OFFSET) /* * This field is 1 when all currently selected harts have acknowledged * the previous resume request. */ #define DMI_DMSTATUS_ALLRESUMEACK_OFFSET 17 #define DMI_DMSTATUS_ALLRESUMEACK_LENGTH 1 #define DMI_DMSTATUS_ALLRESUMEACK (0x1U << DMI_DMSTATUS_ALLRESUMEACK_OFFSET) /* * This field is 1 when any currently selected hart has acknowledged * the previous resume request. */ #define DMI_DMSTATUS_ANYRESUMEACK_OFFSET 16 #define DMI_DMSTATUS_ANYRESUMEACK_LENGTH 1 #define DMI_DMSTATUS_ANYRESUMEACK (0x1U << DMI_DMSTATUS_ANYRESUMEACK_OFFSET) /* * This field is 1 when all currently selected harts do not exist in this system. */ #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET 15 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH 1 #define DMI_DMSTATUS_ALLNONEXISTENT (0x1U << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET) /* * This field is 1 when any currently selected hart does not exist in this system. */ #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET 14 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH 1 #define DMI_DMSTATUS_ANYNONEXISTENT (0x1U << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET) /* * This field is 1 when all currently selected harts are unavailable. */ #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET 13 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH 1 #define DMI_DMSTATUS_ALLUNAVAIL (0x1U << DMI_DMSTATUS_ALLUNAVAIL_OFFSET) /* * This field is 1 when any currently selected hart is unavailable. */ #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET 12 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH 1 #define DMI_DMSTATUS_ANYUNAVAIL (0x1U << DMI_DMSTATUS_ANYUNAVAIL_OFFSET) /* * This field is 1 when all currently selected harts are running. */ #define DMI_DMSTATUS_ALLRUNNING_OFFSET 11 #define DMI_DMSTATUS_ALLRUNNING_LENGTH 1 #define DMI_DMSTATUS_ALLRUNNING (0x1U << DMI_DMSTATUS_ALLRUNNING_OFFSET) /* * This field is 1 when any currently selected hart is running. */ #define DMI_DMSTATUS_ANYRUNNING_OFFSET 10 #define DMI_DMSTATUS_ANYRUNNING_LENGTH 1 #define DMI_DMSTATUS_ANYRUNNING (0x1U << DMI_DMSTATUS_ANYRUNNING_OFFSET) /* * This field is 1 when all currently selected harts are halted. */ #define DMI_DMSTATUS_ALLHALTED_OFFSET 9 #define DMI_DMSTATUS_ALLHALTED_LENGTH 1 #define DMI_DMSTATUS_ALLHALTED (0x1U << DMI_DMSTATUS_ALLHALTED_OFFSET) /* * This field is 1 when any currently selected hart is halted. */ #define DMI_DMSTATUS_ANYHALTED_OFFSET 8 #define DMI_DMSTATUS_ANYHALTED_LENGTH 1 #define DMI_DMSTATUS_ANYHALTED (0x1U << DMI_DMSTATUS_ANYHALTED_OFFSET) /* * 0 when authentication is required before using the DM. 1 when the * authentication check has passed. On components that don't implement * authentication, this bit must be preset as 1. */ #define DMI_DMSTATUS_AUTHENTICATED_OFFSET 7 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH 1 #define DMI_DMSTATUS_AUTHENTICATED (0x1U << DMI_DMSTATUS_AUTHENTICATED_OFFSET) /* * 0: The authentication module is ready to process the next * read/write to \Rauthdata. * * 1: The authentication module is busy. Accessing \Rauthdata results * in unspecified behavior. * * \Fauthbusy only becomes set in immediate response to an access to * \Rauthdata. */ #define DMI_DMSTATUS_AUTHBUSY_OFFSET 6 #define DMI_DMSTATUS_AUTHBUSY_LENGTH 1 #define DMI_DMSTATUS_AUTHBUSY (0x1U << DMI_DMSTATUS_AUTHBUSY_OFFSET) /* * 1 if this Debug Module supports halt-on-reset functionality * controllable by the \Fsetresethaltreq and \Fclrresethaltreq bits. * 0 otherwise. */ #define DMI_DMSTATUS_HASRESETHALTREQ_OFFSET 5 #define DMI_DMSTATUS_HASRESETHALTREQ_LENGTH 1 #define DMI_DMSTATUS_HASRESETHALTREQ (0x1U << DMI_DMSTATUS_HASRESETHALTREQ_OFFSET) /* * 0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which * is not relevant to the Device Tree. * * 1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the * Device Tree. */ #define DMI_DMSTATUS_DEVTREEVALID_OFFSET 4 #define DMI_DMSTATUS_DEVTREEVALID_LENGTH 1 #define DMI_DMSTATUS_DEVTREEVALID (0x1U << DMI_DMSTATUS_DEVTREEVALID_OFFSET) /* * 0: There is no Debug Module present. * * 1: There is a Debug Module and it conforms to version 0.11 of this * specification. * * 2: There is a Debug Module and it conforms to version 0.13 of this * specification. * * 15: There is a Debug Module but it does not conform to any * available version of this spec. */ #define DMI_DMSTATUS_VERSION_OFFSET 0 #define DMI_DMSTATUS_VERSION_LENGTH 4 #define DMI_DMSTATUS_VERSION (0xfU << DMI_DMSTATUS_VERSION_OFFSET) #define DMI_DMCONTROL 0x10 /* * Writes the halt request bit for all currently selected harts. * When set to 1, each selected hart will halt if it is not currently * halted. * * Writing 1 or 0 has no effect on a hart which is already halted, but * the bit must be cleared to 0 before the hart is resumed. * * Writes apply to the new value of \Fhartsel and \Fhasel. */ #define DMI_DMCONTROL_HALTREQ_OFFSET 31 #define DMI_DMCONTROL_HALTREQ_LENGTH 1 #define DMI_DMCONTROL_HALTREQ (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET) /* * Writes the resume request bit for all currently selected harts. * When set to 1, each selected hart will resume if it is currently * halted. * * The resume request bit is ignored while the halt request bit is * set. * * Writes apply to the new value of \Fhartsel and \Fhasel. */ #define DMI_DMCONTROL_RESUMEREQ_OFFSET 30 #define DMI_DMCONTROL_RESUMEREQ_LENGTH 1 #define DMI_DMCONTROL_RESUMEREQ (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET) /* * This optional field writes the reset bit for all the currently * selected harts. To perform a reset the debugger writes 1, and then * writes 0 to deassert the reset signal. * * If this feature is not implemented, the bit always stays 0, so * after writing 1 the debugger can read the register back to see if * the feature is supported. * * Writes apply to the new value of \Fhartsel and \Fhasel. */ #define DMI_DMCONTROL_HARTRESET_OFFSET 29 #define DMI_DMCONTROL_HARTRESET_LENGTH 1 #define DMI_DMCONTROL_HARTRESET (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET) /* * Writing 1 to this bit clears the {\tt havereset} bits for * any selected harts. * * Writes apply to the new value of \Fhartsel and \Fhasel. */ #define DMI_DMCONTROL_ACKHAVERESET_OFFSET 28 #define DMI_DMCONTROL_ACKHAVERESET_LENGTH 1 #define DMI_DMCONTROL_ACKHAVERESET (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET) /* * Selects the definition of currently selected harts. * * 0: There is a single currently selected hart, that selected by \Fhartsel. * * 1: There may be multiple currently selected harts -- that selected by \Fhartsel, * plus those selected by the hart array mask register. * * An implementation which does not implement the hart array mask register * must tie this field to 0. A debugger which wishes to use the hart array * mask register feature should set this bit and read back to see if the functionality * is supported. */ #define DMI_DMCONTROL_HASEL_OFFSET 26 #define DMI_DMCONTROL_HASEL_LENGTH 1 #define DMI_DMCONTROL_HASEL (0x1U << DMI_DMCONTROL_HASEL_OFFSET) /* * The low 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. */ #define DMI_DMCONTROL_HARTSELLO_OFFSET 16 #define DMI_DMCONTROL_HARTSELLO_LENGTH 10 #define DMI_DMCONTROL_HARTSELLO (0x3ffU << DMI_DMCONTROL_HARTSELLO_OFFSET) /* * The high 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. */ #define DMI_DMCONTROL_HARTSELHI_OFFSET 6 #define DMI_DMCONTROL_HARTSELHI_LENGTH 10 #define DMI_DMCONTROL_HARTSELHI (0x3ffU << DMI_DMCONTROL_HARTSELHI_OFFSET) /* * This optional field writes the halt-on-reset request bit for all * currently selected harts. * When set to 1, each selected hart will halt upon the next deassertion * of its reset. The halt-on-reset request bit is not automatically * cleared. The debugger must write to \Fclrresethaltreq to clear it. * * Writes apply to the new value of \Fhartsel and \Fhasel. * * If \Fhasresethaltreq is 0, this field is not implemented. */ #define DMI_DMCONTROL_SETRESETHALTREQ_OFFSET 3 #define DMI_DMCONTROL_SETRESETHALTREQ_LENGTH 1 #define DMI_DMCONTROL_SETRESETHALTREQ (0x1U << DMI_DMCONTROL_SETRESETHALTREQ_OFFSET) /* * This optional field clears the halt-on-reset request bit for all * currently selected harts. * * Writes apply to the new value of \Fhartsel and \Fhasel. */ #define DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 #define DMI_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 #define DMI_DMCONTROL_CLRRESETHALTREQ (0x1U << DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET) /* * This bit controls the reset signal from the DM to the rest of the * system. The signal should reset every part of the system, including * every hart, except for the DM and any logic required to access the * DM. * To perform a system reset the debugger writes 1, * and then writes 0 * to deassert the reset. */ #define DMI_DMCONTROL_NDMRESET_OFFSET 1 #define DMI_DMCONTROL_NDMRESET_LENGTH 1 #define DMI_DMCONTROL_NDMRESET (0x1U << DMI_DMCONTROL_NDMRESET_OFFSET) /* * This bit serves as a reset signal for the Debug Module itself. * * 0: The module's state, including authentication mechanism, * takes its reset values (the \Fdmactive bit is the only bit which can * be written to something other than its reset value). * * 1: The module functions normally. * * No other mechanism should exist that may result in resetting the * Debug Module after power up, including the platform's system reset * or Debug Transport reset signals. * * A debugger may pulse this bit low to get the Debug Module into a * known state. * * Implementations may use this bit to aid debugging, for example by * preventing the Debug Module from being power gated while debugging * is active. */ #define DMI_DMCONTROL_DMACTIVE_OFFSET 0 #define DMI_DMCONTROL_DMACTIVE_LENGTH 1 #define DMI_DMCONTROL_DMACTIVE (0x1U << DMI_DMCONTROL_DMACTIVE_OFFSET) #define DMI_HARTINFO 0x12 /* * Number of {\tt dscratch} registers available for the debugger * to use during program buffer execution, starting from \Rdscratchzero. * The debugger can make no assumptions about the contents of these * registers between commands. */ #define DMI_HARTINFO_NSCRATCH_OFFSET 20 #define DMI_HARTINFO_NSCRATCH_LENGTH 4 #define DMI_HARTINFO_NSCRATCH (0xfU << DMI_HARTINFO_NSCRATCH_OFFSET) /* * 0: The {\tt data} registers are shadowed in the hart by CSR * registers. Each CSR register is MXLEN bits in size, and corresponds * to a single argument, per Table~\ref{tab:datareg}. * * 1: The {\tt data} registers are shadowed in the hart's memory map. * Each register takes up 4 bytes in the memory map. */ #define DMI_HARTINFO_DATAACCESS_OFFSET 16 #define DMI_HARTINFO_DATAACCESS_LENGTH 1 #define DMI_HARTINFO_DATAACCESS (0x1U << DMI_HARTINFO_DATAACCESS_OFFSET) /* * If \Fdataaccess is 0: Number of CSR registers dedicated to * shadowing the {\tt data} registers. * * If \Fdataaccess is 1: Number of 32-bit words in the memory map * dedicated to shadowing the {\tt data} registers. * * Since there are at most 12 {\tt data} registers, the value in this * register must be 12 or smaller. */ #define DMI_HARTINFO_DATASIZE_OFFSET 12 #define DMI_HARTINFO_DATASIZE_LENGTH 4 #define DMI_HARTINFO_DATASIZE (0xfU << DMI_HARTINFO_DATASIZE_OFFSET) /* * If \Fdataaccess is 0: The number of the first CSR dedicated to * shadowing the {\tt data} registers. * * If \Fdataaccess is 1: Signed address of RAM where the {\tt data} * registers are shadowed, to be used to access relative to \Rzero. */ #define DMI_HARTINFO_DATAADDR_OFFSET 0 #define DMI_HARTINFO_DATAADDR_LENGTH 12 #define DMI_HARTINFO_DATAADDR (0xfffU << DMI_HARTINFO_DATAADDR_OFFSET) #define DMI_HAWINDOWSEL 0x14 /* * The high bits of this field may be tied to 0, depending on how large * the array mask register is. Eg. on a system with 48 harts only bit 0 * of this field may actually be writable. */ #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15 #define DMI_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET) #define DMI_HAWINDOW 0x15 #define DMI_HAWINDOW_MASKDATA_OFFSET 0 #define DMI_HAWINDOW_MASKDATA_LENGTH 32 #define DMI_HAWINDOW_MASKDATA (0xffffffffU << DMI_HAWINDOW_MASKDATA_OFFSET) #define DMI_ABSTRACTCS 0x16 /* * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. */ #define DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET 24 #define DMI_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 #define DMI_ABSTRACTCS_PROGBUFSIZE (0x1fU << DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET) /* * 1: An abstract command is currently being executed. * * This bit is set as soon as \Rcommand is written, and is * not cleared until that command has completed. */ #define DMI_ABSTRACTCS_BUSY_OFFSET 12 #define DMI_ABSTRACTCS_BUSY_LENGTH 1 #define DMI_ABSTRACTCS_BUSY (0x1U << DMI_ABSTRACTCS_BUSY_OFFSET) /* * Gets set if an abstract command fails. The bits in this field remain set until * they are cleared by writing 1 to them. No abstract command is * started until the value is reset to 0. * * 0 (none): No error. * * 1 (busy): An abstract command was executing while \Rcommand, * \Rabstractcs, \Rabstractauto was written, or when one * of the {\tt data} or {\tt progbuf} registers was read or written. * * 2 (not supported): The requested command is not supported, * regardless of whether the hart is running or not. * * 3 (exception): An exception occurred while executing the command * (eg. while executing the Program Buffer). * * 4 (halt/resume): The abstract command couldn't execute because the * hart wasn't in the required state (running/halted). * * 7 (other): The command failed for another reason. */ #define DMI_ABSTRACTCS_CMDERR_OFFSET 8 #define DMI_ABSTRACTCS_CMDERR_LENGTH 3 #define DMI_ABSTRACTCS_CMDERR (0x7U << DMI_ABSTRACTCS_CMDERR_OFFSET) /* * Number of {\tt data} registers that are implemented as part of the * abstract command interface. Valid sizes are 0 - 12. */ #define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4 #define DMI_ABSTRACTCS_DATACOUNT (0xfU << DMI_ABSTRACTCS_DATACOUNT_OFFSET) #define DMI_COMMAND 0x17 /* * The type determines the overall functionality of this * abstract command. */ #define DMI_COMMAND_CMDTYPE_OFFSET 24 #define DMI_COMMAND_CMDTYPE_LENGTH 8 #define DMI_COMMAND_CMDTYPE (0xffU << DMI_COMMAND_CMDTYPE_OFFSET) /* * This field is interpreted in a command-specific manner, * described for each abstract command. */ #define DMI_COMMAND_CONTROL_OFFSET 0 #define DMI_COMMAND_CONTROL_LENGTH 24 #define DMI_COMMAND_CONTROL (0xffffffU << DMI_COMMAND_CONTROL_OFFSET) #define DMI_ABSTRACTAUTO 0x18 /* * When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word * cause the command in \Rcommand to be executed again. */ #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) /* * When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word * cause the command in \Rcommand to be executed again. */ #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12 #define DMI_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) #define DMI_DEVTREEADDR0 0x19 #define DMI_DEVTREEADDR0_ADDR_OFFSET 0 #define DMI_DEVTREEADDR0_ADDR_LENGTH 32 #define DMI_DEVTREEADDR0_ADDR (0xffffffffU << DMI_DEVTREEADDR0_ADDR_OFFSET) #define DMI_DEVTREEADDR1 0x1a #define DMI_DEVTREEADDR2 0x1b #define DMI_DEVTREEADDR3 0x1c #define DMI_NEXTDM 0x1d #define DMI_NEXTDM_ADDR_OFFSET 0 #define DMI_NEXTDM_ADDR_LENGTH 32 #define DMI_NEXTDM_ADDR (0xffffffffU << DMI_NEXTDM_ADDR_OFFSET) #define DMI_DATA0 0x04 #define DMI_DATA0_DATA_OFFSET 0 #define DMI_DATA0_DATA_LENGTH 32 #define DMI_DATA0_DATA (0xffffffffU << DMI_DATA0_DATA_OFFSET) #define DMI_DATA11 0x0f #define DMI_PROGBUF0 0x20 #define DMI_PROGBUF0_DATA_OFFSET 0 #define DMI_PROGBUF0_DATA_LENGTH 32 #define DMI_PROGBUF0_DATA (0xffffffffU << DMI_PROGBUF0_DATA_OFFSET) #define DMI_PROGBUF15 0x2f #define DMI_AUTHDATA 0x30 #define DMI_AUTHDATA_DATA_OFFSET 0 #define DMI_AUTHDATA_DATA_LENGTH 32 #define DMI_AUTHDATA_DATA (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET) #define DMI_HALTSUM0 0x40 #define DMI_HALTSUM0_HALTSUM0_OFFSET 0 #define DMI_HALTSUM0_HALTSUM0_LENGTH 32 #define DMI_HALTSUM0_HALTSUM0 (0xffffffffU << DMI_HALTSUM0_HALTSUM0_OFFSET) #define DMI_HALTSUM1 0x13 #define DMI_HALTSUM1_HALTSUM1_OFFSET 0 #define DMI_HALTSUM1_HALTSUM1_LENGTH 32 #define DMI_HALTSUM1_HALTSUM1 (0xffffffffU << DMI_HALTSUM1_HALTSUM1_OFFSET) #define DMI_HALTSUM2 0x34 #define DMI_HALTSUM2_HALTSUM2_OFFSET 0 #define DMI_HALTSUM2_HALTSUM2_LENGTH 32 #define DMI_HALTSUM2_HALTSUM2 (0xffffffffU << DMI_HALTSUM2_HALTSUM2_OFFSET) #define DMI_HALTSUM3 0x35 #define DMI_HALTSUM3_HALTSUM3_OFFSET 0 #define DMI_HALTSUM3_HALTSUM3_LENGTH 32 #define DMI_HALTSUM3_HALTSUM3 (0xffffffffU << DMI_HALTSUM3_HALTSUM3_OFFSET) #define DMI_SBADDRESS3 0x37 /* * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ #define DMI_SBADDRESS3_ADDRESS_OFFSET 0 #define DMI_SBADDRESS3_ADDRESS_LENGTH 32 #define DMI_SBADDRESS3_ADDRESS (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET) #define DMI_SBCS 0x38 /* * 0: The System Bus interface conforms to mainline drafts of this * spec older than 1 January, 2018. * * 1: The System Bus interface conforms to this version of the spec. * * Other values are reserved for future versions. */ #define DMI_SBCS_SBVERSION_OFFSET 29 #define DMI_SBCS_SBVERSION_LENGTH 3 #define DMI_SBCS_SBVERSION (0x7U << DMI_SBCS_SBVERSION_OFFSET) /* * Set when the debugger attempts to read data while a read is in * progress, or when the debugger initiates a new access while one is * already in progress (while \Fsbbusy is set). It remains set until * it's explicitly cleared by the debugger. * * While this field is non-zero, no more system bus accesses can be * initiated by the Debug Module. */ #define DMI_SBCS_SBBUSYERROR_OFFSET 22 #define DMI_SBCS_SBBUSYERROR_LENGTH 1 #define DMI_SBCS_SBBUSYERROR (0x1U << DMI_SBCS_SBBUSYERROR_OFFSET) /* * When 1, indicates the system bus master is busy. (Whether the * system bus itself is busy is related, but not the same thing.) This * bit goes high immediately when a read or write is requested for any * reason, and does not go low until the access is fully completed. * * Writes to \Rsbcs while \Fsbbusy is high result in undefined * behavior. A debugger must not write to \Rsbcs until it reads * \Fsbbusy as 0. */ #define DMI_SBCS_SBBUSY_OFFSET 21 #define DMI_SBCS_SBBUSY_LENGTH 1 #define DMI_SBCS_SBBUSY (0x1U << DMI_SBCS_SBBUSY_OFFSET) /* * When 1, every write to \Rsbaddresszero automatically triggers a * system bus read at the new address. */ #define DMI_SBCS_SBREADONADDR_OFFSET 20 #define DMI_SBCS_SBREADONADDR_LENGTH 1 #define DMI_SBCS_SBREADONADDR (0x1U << DMI_SBCS_SBREADONADDR_OFFSET) /* * Select the access size to use for system bus accesses. * * 0: 8-bit * * 1: 16-bit * * 2: 32-bit * * 3: 64-bit * * 4: 128-bit * * If \Fsbaccess has an unsupported value when the DM starts a bus * access, the access is not performed and \Fsberror is set to 3. */ #define DMI_SBCS_SBACCESS_OFFSET 17 #define DMI_SBCS_SBACCESS_LENGTH 3 #define DMI_SBCS_SBACCESS (0x7U << DMI_SBCS_SBACCESS_OFFSET) /* * When 1, {\tt sbaddress} is incremented by the access size (in * bytes) selected in \Fsbaccess after every system bus access. */ #define DMI_SBCS_SBAUTOINCREMENT_OFFSET 16 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH 1 #define DMI_SBCS_SBAUTOINCREMENT (0x1U << DMI_SBCS_SBAUTOINCREMENT_OFFSET) /* * When 1, every read from \Rsbdatazero automatically triggers a * system bus read at the (possibly auto-incremented) address. */ #define DMI_SBCS_SBREADONDATA_OFFSET 15 #define DMI_SBCS_SBREADONDATA_LENGTH 1 #define DMI_SBCS_SBREADONDATA (0x1U << DMI_SBCS_SBREADONDATA_OFFSET) /* * When the Debug Module's system bus * master causes a bus error, this field gets set. The bits in this * field remain set until they are cleared by writing 1 to them. * While this field is non-zero, no more system bus accesses can be * initiated by the Debug Module. * * An implementation may report "Other" (7) for any error condition. * * 0: There was no bus error. * * 1: There was a timeout. * * 2: A bad address was accessed. * * 3: There was an alignment error. * * 4: An access of unsupported size was requested. * * 7: Other. */ #define DMI_SBCS_SBERROR_OFFSET 12 #define DMI_SBCS_SBERROR_LENGTH 3 #define DMI_SBCS_SBERROR (0x7U << DMI_SBCS_SBERROR_OFFSET) /* * Width of system bus addresses in bits. (0 indicates there is no bus * access support.) */ #define DMI_SBCS_SBASIZE_OFFSET 5 #define DMI_SBCS_SBASIZE_LENGTH 7 #define DMI_SBCS_SBASIZE (0x7fU << DMI_SBCS_SBASIZE_OFFSET) /* * 1 when 128-bit system bus accesses are supported. */ #define DMI_SBCS_SBACCESS128_OFFSET 4 #define DMI_SBCS_SBACCESS128_LENGTH 1 #define DMI_SBCS_SBACCESS128 (0x1U << DMI_SBCS_SBACCESS128_OFFSET) /* * 1 when 64-bit system bus accesses are supported. */ #define DMI_SBCS_SBACCESS64_OFFSET 3 #define DMI_SBCS_SBACCESS64_LENGTH 1 #define DMI_SBCS_SBACCESS64 (0x1U << DMI_SBCS_SBACCESS64_OFFSET) /* * 1 when 32-bit system bus accesses are supported. */ #define DMI_SBCS_SBACCESS32_OFFSET 2 #define DMI_SBCS_SBACCESS32_LENGTH 1 #define DMI_SBCS_SBACCESS32 (0x1U << DMI_SBCS_SBACCESS32_OFFSET) /* * 1 when 16-bit system bus accesses are supported. */ #define DMI_SBCS_SBACCESS16_OFFSET 1 #define DMI_SBCS_SBACCESS16_LENGTH 1 #define DMI_SBCS_SBACCESS16 (0x1U << DMI_SBCS_SBACCESS16_OFFSET) /* * 1 when 8-bit system bus accesses are supported. */ #define DMI_SBCS_SBACCESS8_OFFSET 0 #define DMI_SBCS_SBACCESS8_LENGTH 1 #define DMI_SBCS_SBACCESS8 (0x1U << DMI_SBCS_SBACCESS8_OFFSET) #define DMI_SBADDRESS0 0x39 /* * Accesses bits 31:0 of the physical address in {\tt sbaddress}. */ #define DMI_SBADDRESS0_ADDRESS_OFFSET 0 #define DMI_SBADDRESS0_ADDRESS_LENGTH 32 #define DMI_SBADDRESS0_ADDRESS (0xffffffffU << DMI_SBADDRESS0_ADDRESS_OFFSET) #define DMI_SBADDRESS1 0x3a /* * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ #define DMI_SBADDRESS1_ADDRESS_OFFSET 0 #define DMI_SBADDRESS1_ADDRESS_LENGTH 32 #define DMI_SBADDRESS1_ADDRESS (0xffffffffU << DMI_SBADDRESS1_ADDRESS_OFFSET) #define DMI_SBADDRESS2 0x3b /* * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ #define DMI_SBADDRESS2_ADDRESS_OFFSET 0 #define DMI_SBADDRESS2_ADDRESS_LENGTH 32 #define DMI_SBADDRESS2_ADDRESS (0xffffffffU << DMI_SBADDRESS2_ADDRESS_OFFSET) #define DMI_SBDATA0 0x3c /* * Accesses bits 31:0 of {\tt sbdata}. */ #define DMI_SBDATA0_DATA_OFFSET 0 #define DMI_SBDATA0_DATA_LENGTH 32 #define DMI_SBDATA0_DATA (0xffffffffU << DMI_SBDATA0_DATA_OFFSET) #define DMI_SBDATA1 0x3d /* * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that * wide). */ #define DMI_SBDATA1_DATA_OFFSET 0 #define DMI_SBDATA1_DATA_LENGTH 32 #define DMI_SBDATA1_DATA (0xffffffffU << DMI_SBDATA1_DATA_OFFSET) #define DMI_SBDATA2 0x3e /* * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that * wide). */ #define DMI_SBDATA2_DATA_OFFSET 0 #define DMI_SBDATA2_DATA_LENGTH 32 #define DMI_SBDATA2_DATA (0xffffffffU << DMI_SBDATA2_DATA_OFFSET) #define DMI_SBDATA3 0x3f /* * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that * wide). */ #define DMI_SBDATA3_DATA_OFFSET 0 #define DMI_SBDATA3_DATA_LENGTH 32 #define DMI_SBDATA3_DATA (0xffffffffU << DMI_SBDATA3_DATA_OFFSET) #define SHORTNAME 0x123 /* * Description of what this field is used for. */ #define SHORTNAME_FIELD_OFFSET 0 #define SHORTNAME_FIELD_LENGTH 8 #define SHORTNAME_FIELD (0xffU << SHORTNAME_FIELD_OFFSET) #define AC_ACCESS_REGISTER None /* * This is 0 to indicate Access Register Command. */ #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 #define AC_ACCESS_REGISTER_CMDTYPE (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET) /* * 2: Access the lowest 32 bits of the register. * * 3: Access the lowest 64 bits of the register. * * 4: Access the lowest 128 bits of the register. * * If \Fsize specifies a size larger than the register's actual size, * then the access must fail. If a register is accessible, then reads of \Fsize * less than or equal to the register's actual size must be supported. * * This field controls the Argument Width as referenced in * Table~\ref{tab:datareg}. */ #define AC_ACCESS_REGISTER_SIZE_OFFSET 20 #define AC_ACCESS_REGISTER_SIZE_LENGTH 3 #define AC_ACCESS_REGISTER_SIZE (0x7U << AC_ACCESS_REGISTER_SIZE_OFFSET) /* * When 1, execute the program in the Program Buffer exactly once * after performing the transfer, if any. */ #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 #define AC_ACCESS_REGISTER_POSTEXEC (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET) /* * 0: Don't do the operation specified by \Fwrite. * * 1: Do the operation specified by \Fwrite. * * This bit can be used to just execute the Program Buffer without * having to worry about placing valid values into \Fsize or \Fregno. */ #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 #define AC_ACCESS_REGISTER_TRANSFER (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET) /* * When \Ftransfer is set: * 0: Copy data from the specified register into {\tt arg0} portion * of {\tt data}. * * 1: Copy data from {\tt arg0} portion of {\tt data} into the * specified register. */ #define AC_ACCESS_REGISTER_WRITE_OFFSET 16 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1 #define AC_ACCESS_REGISTER_WRITE (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET) /* * Number of the register to access, as described in * Table~\ref{tab:regno}. * \Rdpc may be used as an alias for PC if this command is * supported on a non-halted hart. */ #define AC_ACCESS_REGISTER_REGNO_OFFSET 0 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16 #define AC_ACCESS_REGISTER_REGNO (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET) #define AC_QUICK_ACCESS None /* * This is 1 to indicate Quick Access command. */ #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 #define AC_QUICK_ACCESS_CMDTYPE (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET) #define VIRT_PRIV virtual /* * Contains the privilege level the hart was operating in when Debug * Mode was entered. The encoding is described in Table * \ref{tab:privlevel}, and matches the privilege level encoding from * the RISC-V Privileged ISA Specification. A user can write this * value to change the hart's privilege level when exiting Debug Mode. */ #define VIRT_PRIV_PRV_OFFSET 0 #define VIRT_PRIV_PRV_LENGTH 2 #define VIRT_PRIV_PRV (0x3U << VIRT_PRIV_PRV_OFFSET)

#include <cassert> #include "debug_module.h" #include "debug_defines.h" #include "opcodes.h" #include "mmu.h" #include "sim.h" #include "debug_rom/debug_rom.h" #include "debug_rom_defines.h" #if 0 # define D(x) x #else # define D(x) #endif ///////////////////////// debug_module_t debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits, bool require_authentication) : progbufsize(progbufsize), program_buffer_bytes(4 + 4*progbufsize), max_bus_master_bits(max_bus_master_bits), require_authentication(require_authentication), debug_progbuf_start(debug_data_start - program_buffer_bytes), debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), custom_base(0), sim(sim) { D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start)); D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start)); D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start)); program_buffer = new uint8_t[program_buffer_bytes]; memset(halted, 0, sizeof(halted)); memset(debug_rom_flags, 0, sizeof(debug_rom_flags)); memset(resumeack, 0, sizeof(resumeack)); memset(havereset, 0, sizeof(havereset)); memset(program_buffer, 0, program_buffer_bytes); program_buffer[4*progbufsize] = ebreak(); program_buffer[4*progbufsize+1] = ebreak() >> 8; program_buffer[4*progbufsize+2] = ebreak() >> 16; program_buffer[4*progbufsize+3] = ebreak() >> 24; memset(dmdata, 0, sizeof(dmdata)); write32(debug_rom_whereto, 0, jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO)); memset(debug_abstract, 0, sizeof(debug_abstract)); reset(); } debug_module_t::~debug_module_t() { delete[] program_buffer; } void debug_module_t::reset() { for (unsigned i = 0; i < sim->nprocs(); i++) { processor_t *proc = sim->get_core(i); if (proc) proc->halt_request = false; } dmcontrol = {0}; dmstatus = {0}; dmstatus.impebreak = true; dmstatus.authenticated = !require_authentication; dmstatus.version = 2; abstractcs = {0}; abstractcs.datacount = sizeof(dmdata) / 4; abstractcs.progbufsize = progbufsize; abstractauto = {0}; sbcs = {0}; if (max_bus_master_bits > 0) { sbcs.version = 1; sbcs.asize = sizeof(reg_t) * 8; } if (max_bus_master_bits >= 64) sbcs.access64 = true; if (max_bus_master_bits >= 32) sbcs.access32 = true; if (max_bus_master_bits >= 16) sbcs.access16 = true; if (max_bus_master_bits >= 8) sbcs.access8 = true; challenge = random(); } void debug_module_t::add_device(bus_t *bus) { bus->add_device(DEBUG_START, this); } bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) { addr = DEBUG_START + addr; if (addr >= DEBUG_ROM_ENTRY && (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) { memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len); return true; } if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) { memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len); return true; } if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) { memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len); return true; } if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) { memcpy(bytes, debug_abstract + addr - debug_abstract_start, len); return true; } if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { memcpy(bytes, dmdata + addr - debug_data_start, len); return true; } if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) { memcpy(bytes, program_buffer + addr - debug_progbuf_start, len); return true; } fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) { D( switch (len) { case 4: fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes, dmcontrol.hartsel); break; default: fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); break; } ); uint8_t id_bytes[4]; uint32_t id = 0; if (len == 4) { memcpy(id_bytes, bytes, 4); id = read32(id_bytes, 0); } addr = DEBUG_START + addr; if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { memcpy(dmdata + addr - debug_data_start, bytes, len); return true; } if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) { memcpy(program_buffer + addr - debug_progbuf_start, bytes, len); return true; } if (addr == DEBUG_ROM_HALTED) { assert (len == 4); halted[id] = true; if (dmcontrol.hartsel == id) { if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){ if (dmcontrol.hartsel == id) { abstractcs.busy = false; } } } return true; } if (addr == DEBUG_ROM_GOING) { debug_rom_flags[dmcontrol.hartsel] &= ~(1 << DEBUG_ROM_FLAG_GO); return true; } if (addr == DEBUG_ROM_RESUMING) { assert (len == 4); halted[id] = false; resumeack[id] = true; debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME); return true; } if (addr == DEBUG_ROM_EXCEPTION) { if (abstractcs.cmderr == CMDERR_NONE) { abstractcs.cmderr = CMDERR_EXCEPTION; } return true; } fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value) { uint8_t* base = memory + index * 4; base[0] = value & 0xff; base[1] = (value >> 8) & 0xff; base[2] = (value >> 16) & 0xff; base[3] = (value >> 24) & 0xff; } uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index) { uint8_t* base = memory + index * 4; uint32_t value = ((uint32_t) base[0]) | (((uint32_t) base[1]) << 8) | (((uint32_t) base[2]) << 16) | (((uint32_t) base[3]) << 24); return value; } processor_t *debug_module_t::current_proc() const { processor_t *proc = NULL; try { proc = sim->get_core(dmcontrol.hartsel); } catch (const std::out_of_range&) { } return proc; } unsigned debug_module_t::sb_access_bits() { return 8 << sbcs.sbaccess; } void debug_module_t::sb_autoincrement() { if (!sbcs.autoincrement || !max_bus_master_bits) return; uint64_t value = sbaddress[0] + sb_access_bits() / 8; sbaddress[0] = value; uint32_t carry = value >> 32; value = sbaddress[1] + carry; sbaddress[1] = value; carry = value >> 32; value = sbaddress[2] + carry; sbaddress[2] = value; carry = value >> 32; sbaddress[3] += carry; } void debug_module_t::sb_read() { reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; try { if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { sbdata[0] = sim->debug_mmu->load_uint8(address); } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { sbdata[0] = sim->debug_mmu->load_uint16(address); } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { sbdata[0] = sim->debug_mmu->load_uint32(address); } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { uint64_t value = sim->debug_mmu->load_uint64(address); sbdata[0] = value; sbdata[1] = value >> 32; } else { sbcs.error = 3; } } catch (trap_load_access_fault& t) { sbcs.error = 2; } } void debug_module_t::sb_write() { reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { sim->debug_mmu->store_uint8(address, sbdata[0]); } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { sim->debug_mmu->store_uint16(address, sbdata[0]); } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { sim->debug_mmu->store_uint32(address, sbdata[0]); } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { sim->debug_mmu->store_uint64(address, (((uint64_t) sbdata[1]) << 32) | sbdata[0]); } else { sbcs.error = 3; } } bool debug_module_t::dmi_read(unsigned address, uint32_t *value) { uint32_t result = 0; D(fprintf(stderr, "dmi_read(0x%x) -> ", address)); if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { unsigned i = address - DMI_DATA0; result = read32(dmdata, i); if (abstractcs.busy) { result = -1; fprintf(stderr, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address, i); } if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) { abstractcs.cmderr = CMDERR_BUSY; } if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) { perform_abstract_command(); } } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) { unsigned i = address - DMI_PROGBUF0; result = read32(program_buffer, i); if (abstractcs.busy) { result = -1; fprintf(stderr, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address, i); } if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) { perform_abstract_command(); } } else { switch (address) { case DMI_DMCONTROL: { processor_t *proc = current_proc(); if (proc) dmcontrol.haltreq = proc->halt_request; result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq); result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq); result = set_field(result, DMI_DMCONTROL_HARTSELHI, dmcontrol.hartsel >> DMI_DMCONTROL_HARTSELLO_LENGTH); result = set_field(result, DMI_DMCONTROL_HARTSELLO, dmcontrol.hartsel); result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset); result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset); result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive); } break; case DMI_DMSTATUS: { processor_t *proc = current_proc(); dmstatus.allnonexistant = false; dmstatus.allunavail = false; dmstatus.allrunning = false; dmstatus.allhalted = false; dmstatus.allresumeack = false; if (proc) { if (halted[dmcontrol.hartsel]) { dmstatus.allhalted = true; } else { dmstatus.allrunning = true; } } else { dmstatus.allnonexistant = true; } dmstatus.anynonexistant = dmstatus.allnonexistant; dmstatus.anyunavail = dmstatus.allunavail; dmstatus.anyrunning = dmstatus.allrunning; dmstatus.anyhalted = dmstatus.allhalted; if (proc) { if (resumeack[dmcontrol.hartsel]) { dmstatus.allresumeack = true; } else { dmstatus.allresumeack = false; } } else { dmstatus.allresumeack = false; } result = set_field(result, DMI_DMSTATUS_IMPEBREAK, dmstatus.impebreak); result = set_field(result, DMI_DMSTATUS_ALLHAVERESET, havereset[dmcontrol.hartsel]); result = set_field(result, DMI_DMSTATUS_ANYHAVERESET, havereset[dmcontrol.hartsel]); result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning); result = set_field(result, DMI_DMSTATUS_ALLHALTED, dmstatus.allhalted); result = set_field(result, DMI_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack); result = set_field(result, DMI_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); result = set_field(result, DMI_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); result = set_field(result, DMI_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); result = set_field(result, DMI_DMSTATUS_ANYHALTED, dmstatus.anyhalted); result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack); result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated); result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy); result = set_field(result, DMI_DMSTATUS_VERSION, dmstatus.version); } break; case DMI_ABSTRACTCS: result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr); result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy); result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount); result = set_field(result, DMI_ABSTRACTCS_PROGBUFSIZE, abstractcs.progbufsize); break; case DMI_ABSTRACTAUTO: result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf); result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata); break; case DMI_COMMAND: result = 0; break; case DMI_HARTINFO: result = set_field(result, DMI_HARTINFO_NSCRATCH, 1); result = set_field(result, DMI_HARTINFO_DATAACCESS, 1); result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount); result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start); break; case DMI_SBCS: result = set_field(result, DMI_SBCS_SBVERSION, sbcs.version); result = set_field(result, DMI_SBCS_SBREADONADDR, sbcs.readonaddr); result = set_field(result, DMI_SBCS_SBACCESS, sbcs.sbaccess); result = set_field(result, DMI_SBCS_SBAUTOINCREMENT, sbcs.autoincrement); result = set_field(result, DMI_SBCS_SBREADONDATA, sbcs.readondata); result = set_field(result, DMI_SBCS_SBERROR, sbcs.error); result = set_field(result, DMI_SBCS_SBASIZE, sbcs.asize); result = set_field(result, DMI_SBCS_SBACCESS128, sbcs.access128); result = set_field(result, DMI_SBCS_SBACCESS64, sbcs.access64); result = set_field(result, DMI_SBCS_SBACCESS32, sbcs.access32); result = set_field(result, DMI_SBCS_SBACCESS16, sbcs.access16); result = set_field(result, DMI_SBCS_SBACCESS8, sbcs.access8); break; case DMI_SBADDRESS0: result = sbaddress[0]; break; case DMI_SBADDRESS1: result = sbaddress[1]; break; case DMI_SBADDRESS2: result = sbaddress[2]; break; case DMI_SBADDRESS3: result = sbaddress[3]; break; case DMI_SBDATA0: result = sbdata[0]; if (sbcs.error == 0) { sb_autoincrement(); if (sbcs.readondata) { sb_read(); } } break; case DMI_SBDATA1: result = sbdata[1]; break; case DMI_SBDATA2: result = sbdata[2]; break; case DMI_SBDATA3: result = sbdata[3]; break; case DMI_AUTHDATA: result = challenge; break; default: result = 0; D(fprintf(stderr, "Unexpected. Returning Error.")); return false; } } D(fprintf(stderr, "0x%x\n", result)); *value = result; return true; } bool debug_module_t::perform_abstract_command() { if (abstractcs.cmderr != CMDERR_NONE) return true; if (abstractcs.busy) { abstractcs.cmderr = CMDERR_BUSY; return true; } if ((command >> 24) == 0) { // register access unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE); bool write = get_field(command, AC_ACCESS_REGISTER_WRITE); unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO); if (!halted[dmcontrol.hartsel]) { abstractcs.cmderr = CMDERR_HALTRESUME; return true; } unsigned i = 0; if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) { if (regno < 0x1000 && progbufsize < 2) { // Make the debugger use the program buffer if it's available, so it // can test both use cases. write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH)); if (write) { switch (size) { case 2: write32(debug_abstract, i++, lw(S0, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, ld(S0, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } write32(debug_abstract, i++, csrw(S0, regno)); } else { write32(debug_abstract, i++, csrr(S0, regno)); switch (size) { case 2: write32(debug_abstract, i++, sw(S0, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, sd(S0, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH)); } else if (regno >= 0x1000 && regno < 0x1020) { unsigned regnum = regno - 0x1000; switch (size) { case 2: if (write) write32(debug_abstract, i++, lw(regnum, ZERO, debug_data_start)); else write32(debug_abstract, i++, sw(regnum, ZERO, debug_data_start)); break; case 3: if (write) write32(debug_abstract, i++, ld(regnum, ZERO, debug_data_start)); else write32(debug_abstract, i++, sd(regnum, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } else if (regno >= 0x1020 && regno < 0x1040) { // Don't force the debugger to use progbuf if it exists, so the // debugger has to make the decision not to use abstract commands to // access 64-bit FPRs on 32-bit targets. unsigned fprnum = regno - 0x1020; if (write) { switch (size) { case 2: write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, fld(fprnum, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } else { switch (size) { case 2: write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start)); break; case 3: write32(debug_abstract, i++, fsd(fprnum, ZERO, debug_data_start)); break; default: abstractcs.cmderr = CMDERR_NOTSUP; return true; } } } else if (regno >= 0xc000 && (regno & 1) == 1) { // Support odd-numbered custom registers, to allow for debugger testing. unsigned custom_number = regno - 0xc000; abstractcs.cmderr = CMDERR_NONE; if (write) { // Writing V to custom register N will cause future reads of N to // return V, reads of N-1 will return V-1, etc. custom_base = read32(dmdata, 0) - custom_number; } else { write32(dmdata, 0, custom_number + custom_base); write32(dmdata, 1, 0); } return true; } else { abstractcs.cmderr = CMDERR_NOTSUP; return true; } } if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) { write32(debug_abstract, i, jal(ZERO, debug_progbuf_start - debug_abstract_start - 4 * i)); i++; } else { write32(debug_abstract, i++, ebreak()); } debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO; abstractcs.busy = true; } else { abstractcs.cmderr = CMDERR_NOTSUP; } return true; } bool debug_module_t::dmi_write(unsigned address, uint32_t value) { D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value)); if (!dmstatus.authenticated && address != DMI_AUTHDATA && address != DMI_DMCONTROL) return false; if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { unsigned i = address - DMI_DATA0; if (!abstractcs.busy) write32(dmdata, address - DMI_DATA0, value); if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) { abstractcs.cmderr = CMDERR_BUSY; } if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) { perform_abstract_command(); } return true; } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) { unsigned i = address - DMI_PROGBUF0; if (!abstractcs.busy) write32(program_buffer, i, value); if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) { perform_abstract_command(); } return true; } else { switch (address) { case DMI_DMCONTROL: { if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE)) reset(); dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE); if (!dmstatus.authenticated) return true; if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ); dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET); dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSELHI) << DMI_DMCONTROL_HARTSELLO_LENGTH; dmcontrol.hartsel |= get_field(value, DMI_DMCONTROL_HARTSELLO); dmcontrol.hartsel &= (1L<<hartsellen) - 1; if (get_field(value, DMI_DMCONTROL_ACKHAVERESET)) { havereset[dmcontrol.hartsel] = false; } } processor_t *proc = current_proc(); if (proc) { proc->halt_request = dmcontrol.haltreq; if (dmcontrol.resumereq) { debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME); resumeack[dmcontrol.hartsel] = false; } if (dmcontrol.hartreset) { proc->reset(); } } if (dmcontrol.ndmreset) { for (size_t i = 0; i < sim->nprocs(); i++) { proc = sim->get_core(i); proc->reset(); } } } return true; case DMI_COMMAND: command = value; return perform_abstract_command(); case DMI_ABSTRACTCS: abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DMI_ABSTRACTCS_CMDERR)))); return true; case DMI_ABSTRACTAUTO: abstractauto.autoexecprogbuf = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF); abstractauto.autoexecdata = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECDATA); return true; case DMI_SBCS: sbcs.readonaddr = get_field(value, DMI_SBCS_SBREADONADDR); sbcs.sbaccess = get_field(value, DMI_SBCS_SBACCESS); sbcs.autoincrement = get_field(value, DMI_SBCS_SBAUTOINCREMENT); sbcs.readondata = get_field(value, DMI_SBCS_SBREADONDATA); sbcs.error &= ~get_field(value, DMI_SBCS_SBERROR); return true; case DMI_SBADDRESS0: sbaddress[0] = value; if (sbcs.error == 0 && sbcs.readonaddr) { sb_read(); } return true; case DMI_SBADDRESS1: sbaddress[1] = value; return true; case DMI_SBADDRESS2: sbaddress[2] = value; return true; case DMI_SBADDRESS3: sbaddress[3] = value; return true; case DMI_SBDATA0: sbdata[0] = value; if (sbcs.error == 0) { sb_write(); if (sbcs.autoincrement && sbcs.error == 0) { sb_autoincrement(); } } return true; case DMI_SBDATA1: sbdata[1] = value; return true; case DMI_SBDATA2: sbdata[2] = value; return true; case DMI_SBDATA3: sbdata[3] = value; return true; case DMI_AUTHDATA: D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value, challenge + secret)); if (require_authentication) { if (value == challenge + secret) { dmstatus.authenticated = true; } else { dmstatus.authenticated = false; challenge = random(); } } return true; } } return false; } void debug_module_t::proc_reset(unsigned id) { havereset[id] = true; halted[id] = false; }

// See LICENSE for license details. #ifndef _RISCV_DEBUG_MODULE_H #define _RISCV_DEBUG_MODULE_H #include <set> #include "devices.h" class sim_t; typedef struct { bool haltreq; bool resumereq; unsigned hartsel; bool hartreset; bool dmactive; bool ndmreset; } dmcontrol_t; typedef struct { bool impebreak; bool allhavereset; bool anyhavereset; bool allnonexistant; bool anynonexistant; bool allunavail; bool anyunavail; bool allrunning; bool anyrunning; bool allhalted; bool anyhalted; bool allresumeack; bool anyresumeack; bool authenticated; bool authbusy; bool cfgstrvalid; unsigned version; } dmstatus_t; typedef enum cmderr { CMDERR_NONE = 0, CMDERR_BUSY = 1, CMDERR_NOTSUP = 2, CMDERR_EXCEPTION = 3, CMDERR_HALTRESUME = 4, CMDERR_OTHER = 7 } cmderr_t; typedef struct { bool busy; unsigned datacount; unsigned progbufsize; cmderr_t cmderr; } abstractcs_t; typedef struct { unsigned autoexecprogbuf; unsigned autoexecdata; } abstractauto_t; typedef struct { unsigned version; bool readonaddr; unsigned sbaccess; bool autoincrement; bool readondata; unsigned error; unsigned asize; bool access128; bool access64; bool access32; bool access16; bool access8; } sbcs_t; class debug_module_t : public abstract_device_t { public: /* * If require_authentication is true, then a debugger must authenticate as * follows: * 1. Read a 32-bit value from authdata: * 2. Write the value that was read back, plus one, to authdata. */ debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits, bool require_authentication); ~debug_module_t(); void add_device(bus_t *bus); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); // Debug Module Interface that the debugger (in our case through JTAG DTM) // uses to access the DM. // Return true for success, false for failure. bool dmi_read(unsigned address, uint32_t *value); bool dmi_write(unsigned address, uint32_t value); // Called when one of the attached harts was reset. void proc_reset(unsigned id); private: static const unsigned datasize = 2; // Size of program_buffer in 32-bit words, as exposed to the rest of the // world. unsigned progbufsize; // Actual size of the program buffer, which is 1 word bigger than we let on // to implement the implicit ebreak at the end. unsigned program_buffer_bytes; unsigned max_bus_master_bits; bool require_authentication; static const unsigned debug_data_start = 0x380; unsigned debug_progbuf_start; static const unsigned debug_abstract_size = 5; unsigned debug_abstract_start; // R/W this through custom registers, to allow debuggers to test that // functionality. unsigned custom_base; // We only support 1024 harts currently. More requires at least resizing // the arrays below, and their corresponding special memory regions. static const unsigned hartsellen = 10; sim_t *sim; uint8_t debug_rom_whereto[4]; uint8_t debug_abstract[debug_abstract_size * 4]; uint8_t *program_buffer; uint8_t dmdata[datasize * 4]; bool halted[1024]; bool resumeack[1024]; bool havereset[1024]; uint8_t debug_rom_flags[1024]; void write32(uint8_t *rom, unsigned int index, uint32_t value); uint32_t read32(uint8_t *rom, unsigned int index); void sb_autoincrement(); void sb_read(); void sb_write(); unsigned sb_access_bits(); dmcontrol_t dmcontrol; dmstatus_t dmstatus; abstractcs_t abstractcs; abstractauto_t abstractauto; uint32_t command; sbcs_t sbcs; uint32_t sbaddress[4]; uint32_t sbdata[4]; uint32_t challenge; const uint32_t secret = 1; processor_t *current_proc() const; void reset(); bool perform_abstract_command(); }; #endif

// See LICENSE file for license details. #ifndef DEBUG_ROM_DEFINES_H #define DEBUG_ROM_DEFINES_H // These are implementation-specific addresses in the Debug Module #define DEBUG_ROM_HALTED 0x100 #define DEBUG_ROM_GOING 0x104 #define DEBUG_ROM_RESUMING 0x108 #define DEBUG_ROM_EXCEPTION 0x10C // Region of memory where each hart has 1 // byte to read. #define DEBUG_ROM_FLAGS 0x400 #define DEBUG_ROM_FLAG_GO 0 #define DEBUG_ROM_FLAG_RESUME 1 // These needs to match the link.ld #define DEBUG_ROM_WHERETO 0x300 #define DEBUG_ROM_ENTRY 0x800 #define DEBUG_ROM_TVEC 0x808 #endif

// See LICENSE for license details. #ifndef _RISCV_DECODE_H #define _RISCV_DECODE_H #if (-1 != ~0) || ((-1 >> 1) != -1) # error spike requires a two''s-complement c++ implementation #endif #ifdef WORDS_BIGENDIAN # error spike requires a little-endian host #endif #include <cstdint> #include <string.h> #include <strings.h> #include "encoding.h" #include "config.h" #include "common.h" #include "softfloat_types.h" #include "specialize.h" #include <cinttypes> typedef int64_t sreg_t; typedef uint64_t reg_t; const int NXPR = 32; const int NFPR = 32; const int NCSR = 4096; #define X_RA 1 #define X_SP 2 #define FP_RD_NE 0 #define FP_RD_0 1 #define FP_RD_DN 2 #define FP_RD_UP 3 #define FP_RD_NMM 4 #define FSR_RD_SHIFT 5 #define FSR_RD (0x7 << FSR_RD_SHIFT) #define FPEXC_NX 0x01 #define FPEXC_UF 0x02 #define FPEXC_OF 0x04 #define FPEXC_DZ 0x08 #define FPEXC_NV 0x10 #define FSR_AEXC_SHIFT 0 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) #define insn_length(x) \ (((x) & 0x03) < 0x03 ? 2 : \ ((x) & 0x1f) < 0x1f ? 4 : \ ((x) & 0x3f) < 0x3f ? 6 : \ 8) #define MAX_INSN_LENGTH 8 #define PC_ALIGN 2 typedef uint64_t insn_bits_t; class insn_t { public: insn_t() = default; insn_t(insn_bits_t bits) : b(bits) {} insn_bits_t bits() { return b; } int length() { return insn_length(b); } int64_t i_imm() { return int64_t(b) >> 20; } int64_t shamt() { return x(20, 6); } int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); } int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); } int64_t u_imm() { return int64_t(b) >> 12 << 12; } int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); } uint64_t rd() { return x(7, 5); } uint64_t rs1() { return x(15, 5); } uint64_t rs2() { return x(20, 5); } uint64_t rs3() { return x(27, 5); } uint64_t rm() { return x(12, 3); } uint64_t csr() { return x(20, 12); } int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } int64_t rvc_simm3() { return x(10, 3); } uint64_t rvc_rd() { return rd(); } uint64_t rvc_rs1() { return rd(); } uint64_t rvc_rs2() { return x(2, 5); } uint64_t rvc_rs1s() { return 8 + x(7, 3); } uint64_t rvc_rs2s() { return 8 + x(2, 3); } private: insn_bits_t b; uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); } uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); } uint64_t imm_sign() { return xs(63, 1); } }; template <class T, size_t N, bool zero_reg> class regfile_t { public: void write(size_t i, T value) { if (!zero_reg || i != 0) data[i] = value; } const T& operator [] (size_t i) const { return data[i]; } private: T data[N]; }; // helpful macros, etc #define MMU (*p->get_mmu()) #define STATE (*p->get_state()) #define READ_REG(reg) STATE.XPR[reg] #define READ_FREG(reg) STATE.FPR[reg] #define RS1 READ_REG(insn.rs1()) #define RS2 READ_REG(insn.rs2()) #define WRITE_RD(value) WRITE_REG(insn.rd(), value) #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) #else # define WRITE_REG(reg, value) ({ \ reg_t wdata = (value); /* value may have side effects */ \ STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \ STATE.XPR.write(reg, wdata); \ }) # define WRITE_FREG(reg, value) ({ \ freg_t wdata = freg(value); /* value may have side effects */ \ STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \ DO_WRITE_FREG(reg, wdata); \ }) #endif // RVC macros #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) #define RVC_RS1 READ_REG(insn.rvc_rs1()) #define RVC_RS2 READ_REG(insn.rvc_rs2()) #define RVC_RS1S READ_REG(insn.rvc_rs1s()) #define RVC_RS2S READ_REG(insn.rvc_rs2s()) #define RVC_FRS2 READ_FREG(insn.rvc_rs2()) #define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) #define RVC_SP READ_REG(X_SP) // FPU macros #define FRS1 READ_FREG(insn.rs1()) #define FRS2 READ_FREG(insn.rs2()) #define FRS3 READ_FREG(insn.rs3()) // #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define dirty_fp_state (STATE.mstatus &= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) #define SHAMT (insn.i_imm() & 0x3F) #define BRANCH_TARGET (pc + insn.sb_imm()) #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ if(rm == 7) rm = STATE.frm; \ if(rm > 4) throw trap_illegal_instruction(0); \ rm; }) #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0) #define require_privilege(p) require(STATE.prv >= (p)) #define require_rv64 require(xlen == 64) #define require_rv32 require(xlen == 32) #define require_extension(s) require(p->supports_extension(s)) #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0) #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0) #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ dirty_fp_state; \ STATE.fflags |= softfloat_exceptionFlags; \ } \ softfloat_exceptionFlags = 0; }) #define sext32(x) ((sreg_t)(int32_t)(x)) #define zext32(x) ((reg_t)(uint32_t)(x)) #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen)) #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) #define set_pc(x) \ do { p->check_pc_alignment(x); \ npc = sext_xlen(x); \ } while(0) #define set_pc_and_serialize(x) \ do { reg_t __npc = (x) & p->pc_alignment_mask(); \ npc = PC_SERIALIZE_AFTER; \ STATE.pc = __npc; \ } while(0) #define wfi() \ do { set_pc_and_serialize(npc); \ npc = PC_SERIALIZE_WFI; \ } while(0) #define serialize() set_pc_and_serialize(npc) /* Sentinel PC values to serialize simulator pipeline */ #define PC_SERIALIZE_BEFORE 3 #define PC_SERIALIZE_AFTER 5 #define PC_SERIALIZE_WFI 7 #define invalid_pc(pc) ((pc) & 1) /* Convenience wrappers to simplify softfloat code sequences */ #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) #define isBoxedF64(r) ((r.v[1] + 1) == 0) #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI) typedef float128_t freg_t; inline float32_t f32(uint32_t v) { return { v }; } inline float64_t f64(uint64_t v) { return { v }; } inline float32_t f32(freg_t r) { return f32(unboxF32(r)); } inline float64_t f64(freg_t r) { return f64(unboxF64(r)); } inline float128_t f128(freg_t r) { return r; } inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; } inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; } inline freg_t freg(float128_t f) { return f; } #define F32_SIGN ((uint32_t)1 << 31) #define F64_SIGN ((uint64_t)1 << 63) #define fsgnj32(a, b, n, x) \ f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) #define fsgnj64(a, b, n, x) \ f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) #define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0]) inline float128_t defaultNaNF128() { float128_t nan; nan.v[1] = defaultNaNF128UI64; nan.v[0] = defaultNaNF128UI0; return nan; } inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x) { a.v[1] = (a.v[1] & ~F64_SIGN) | (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN); return a; } inline freg_t f128_negate(freg_t a) { a.v[1] ^= F64_SIGN; return a; } #define validate_csr(which, write) ({ \ if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ STATE.serialized = false; \ unsigned csr_priv = get_field((which), 0x300); \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ if (((write) && csr_read_only) || STATE.prv < csr_priv) \ throw trap_illegal_instruction(0); \ (which); }) // Seems that 0x0 doesn't work. #define DEBUG_START 0x100 #define DEBUG_END (0x1000 - 1) #endif

#include "devices.h" void bus_t::add_device(reg_t addr, abstract_device_t* dev) { // Searching devices via lower_bound/upper_bound // implicitly relies on the underlying std::map // container to sort the keys and provide ordered // iteration over this sort, which it does. (python's // SortedDict is a good analogy) devices[addr] = dev; } bool bus_t::load(reg_t addr, size_t len, uint8_t* bytes) { // Find the device with the base address closest to but // less than addr (price-is-right search) auto it = devices.upper_bound(addr); if (devices.empty() || it == devices.begin()) { // Either the bus is empty, or there weren't // any items with a base address <= addr return false; } // Found at least one item with base address <= addr // The iterator points to the device after this, so // go back by one item. it--; return it->second->load(addr - it->first, len, bytes); } bool bus_t::store(reg_t addr, size_t len, const uint8_t* bytes) { // See comments in bus_t::load auto it = devices.upper_bound(addr); if (devices.empty() || it == devices.begin()) { return false; } it--; return it->second->store(addr - it->first, len, bytes); } std::pair<reg_t, abstract_device_t*> bus_t::find_device(reg_t addr) { // See comments in bus_t::load auto it = devices.upper_bound(addr); if (devices.empty() || it == devices.begin()) { return std::make_pair((reg_t)0, (abstract_device_t*)NULL); } it--; return std::make_pair(it->first, it->second); }

#ifndef _RISCV_DEVICES_H #define _RISCV_DEVICES_H #include "decode.h" #include <cstdlib> #include <string> #include <map> #include <vector> #include <fstream> class processor_t; class abstract_device_t { public: virtual bool load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) = 0; virtual ~abstract_device_t() {} }; class bus_t : public abstract_device_t { public: bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); void add_device(reg_t addr, abstract_device_t* dev); std::pair<reg_t, abstract_device_t*> find_device(reg_t addr); private: std::map<reg_t, abstract_device_t*> devices; }; class rom_device_t : public abstract_device_t { public: rom_device_t(std::vector<char> data); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); const std::vector<char>& contents() { return data; } private: std::vector<char> data; }; class mem_t : public abstract_device_t { public: mem_t(size_t size) : len(size) { if (!size) throw std::runtime_error("zero bytes of target memory requested"); data = (char*)calloc(1, size); if (!data) throw std::runtime_error("couldn't allocate " + std::to_string(size) + " bytes of target memory"); } mem_t(const mem_t& that) = delete; ~mem_t() { free(data); } bool load(reg_t addr, size_t len, uint8_t* bytes) { return false; } bool store(reg_t addr, size_t len, const uint8_t* bytes) { return false; } char* contents() { return data; } size_t size() { return len; } private: char* data; size_t len; }; class clint_t : public abstract_device_t { public: clint_t(std::vector<processor_t*>&); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); void reset(); size_t size() { return CLINT_SIZE; } void increment(reg_t inc); private: typedef uint64_t mtime_t; typedef uint64_t mtimecmp_t; typedef uint32_t msip_t; std::vector<processor_t*>& procs; mtime_t mtime; std::vector<mtimecmp_t> mtimecmp; }; class uart_t : public abstract_device_t { public: uart_t(); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); private: uint8_t ier; uint8_t dll; uint8_t dlm; uint8_t lcr; uint8_t lsr; uint8_t scr; uint8_t msr; uint8_t mcr; bool fifo_enabled; }; class dump_t : public abstract_device_t { public: dump_t(); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); private: std::ofstream ofs; }; #endif

// See LICENSE for license details. #ifndef _RISCV_DISASM_H #define _RISCV_DISASM_H #include "decode.h" #include <string> #include <sstream> #include <vector> extern const char* xpr_name[NXPR]; extern const char* fpr_name[NFPR]; extern const char* csr_name(int which); class arg_t { public: virtual std::string to_string(insn_t val) const = 0; virtual ~arg_t() {} }; class disasm_insn_t { public: disasm_insn_t(const char* name, uint32_t match, uint32_t mask, const std::vector<const arg_t*>& args) : match(match), mask(mask), args(args), name(name) {} bool operator == (insn_t insn) const { return (insn.bits() & mask) == match; } std::string to_string(insn_t insn) const { std::stringstream s; int len; for (len = 0; name[len]; len++) s << (name[len] == '_' ? '.' : name[len]); if (args.size()) { s << std::string(std::max(1, 8 - len), ' '); for (size_t i = 0; i < args.size()-1; i++) s << args[i]->to_string(insn) << ", "; s << args[args.size()-1]->to_string(insn); } return s.str(); } uint32_t get_match() const { return match; } uint32_t get_mask() const { return mask; } private: uint32_t match; uint32_t mask; std::vector<const arg_t*> args; const char* name; }; class disassembler_t { public: disassembler_t(int xlen); ~disassembler_t(); std::string disassemble(insn_t insn) const; void add_insn(disasm_insn_t* insn); private: static const int HASH_SIZE = 256; std::vector<const disasm_insn_t*> chain[HASH_SIZE+1]; const disasm_insn_t* lookup(insn_t insn) const; }; #endif

// See LICENSE for license details. #include "dts.h" #include <iostream> #include <sstream> #include <signal.h> #include <unistd.h> #include <sys/wait.h> #include <sys/types.h> std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, std::vector<processor_t*> procs, std::vector<std::pair<reg_t, mem_t*>> mems) { std::stringstream s; s << std::dec << "/dts-v1/;\n" "\n" "/ {\n" " #address-cells = <2>;\n" " #size-cells = <2>;\n" " compatible = \"ucbbar,spike-bare-dev\";\n" " model = \"ucbbar,spike-bare\";\n" " cpus {\n" " #address-cells = <1>;\n" " #size-cells = <0>;\n" " timebase-frequency = <" << (cpu_hz/insns_per_rtc_tick) << ">;\n"; for (size_t i = 0; i < procs.size(); i++) { s << " CPU" << i << ": cpu@" << i << " {\n" " device_type = \"cpu\";\n" " reg = <" << i << ">;\n" " status = \"okay\";\n" " compatible = \"riscv\";\n" " riscv,isa = \"" << procs[i]->get_isa_string() << "\";\n" " mmu-type = \"riscv," << (procs[i]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << cpu_hz << ">;\n" " CPU" << i << "_intc: interrupt-controller {\n" " #interrupt-cells = <1>;\n" " interrupt-controller;\n" " compatible = \"riscv,cpu-intc\";\n" " };\n" " };\n"; } s << " };\n"; for (auto& m : mems) { s << std::hex << " memory@" << m.first << " {\n" " device_type = \"memory\";\n" " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" " };\n"; } s << " soc {\n" " #address-cells = <2>;\n" " #size-cells = <2>;\n" " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" " ranges;\n" " clint@" << CLINT_BASE << " {\n" " compatible = \"riscv,clint0\";\n" " interrupts-extended = <" << std::dec; for (size_t i = 0; i < procs.size(); i++) s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; reg_t clintbs = CLINT_BASE; reg_t clintsz = CLINT_SIZE; s << std::hex << ">;\n" " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) << " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" " };\n" " };\n" // " htif {\n" // " compatible = \"ucb,htif0\";\n" // " };\n" " uart@" << UART_BASE << " {\n" " compatible = \"ns16750\";\n" " reg = <0x0 0x10000000 0x0 0x1000>;\n" " clock-frequency = <50000000>;\n" " current-speed = <115200>;\n" // " interrupt-parent = <&PLIC0>;\n" // " interrupts = <1>;\n" " reg-shift = <2>;\n" " reg-io-width = <4>;\n" " };\n" "};\n"; return s.str(); } std::string dts_compile(const std::string& dts) { // Convert the DTS to DTB int dts_pipe[2]; pid_t dts_pid; if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) { std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; exit(1); } // Child process to output dts if (dts_pid == 0) { close(dts_pipe[0]); int step, len = dts.length(); const char *buf = dts.c_str(); for (int done = 0; done < len; done += step) { step = write(dts_pipe[1], buf+done, len-done); if (step == -1) { std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; exit(1); } } close(dts_pipe[1]); exit(0); } pid_t dtb_pid; int dtb_pipe[2]; if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) { std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; exit(1); } // Child process to output dtb if (dtb_pid == 0) { dup2(dts_pipe[0], 0); dup2(dtb_pipe[1], 1); close(dts_pipe[0]); close(dts_pipe[1]); close(dtb_pipe[0]); close(dtb_pipe[1]); execl(DTC, DTC, "-O", "dtb", 0); std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; exit(1); } close(dts_pipe[1]); close(dts_pipe[0]); close(dtb_pipe[1]); // Read-out dtb std::stringstream dtb; int got; char buf[4096]; while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { dtb.write(buf, got); } if (got == -1) { std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; exit(1); } close(dtb_pipe[0]); // Reap children int status; waitpid(dts_pid, &status, 0); if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { std::cerr << "Child dts process failed" << std::endl; exit(1); } waitpid(dtb_pid, &status, 0); if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { std::cerr << "Child dtb process failed" << std::endl; exit(1); } return dtb.str(); }

// See LICENSE for license details. #ifndef _RISCV_DTS_H #define _RISCV_DTS_H #include "processor.h" #include "mmu.h" #include <string> std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, std::vector<processor_t*> procs, std::vector<std::pair<reg_t, mem_t*>> mems); std::string dts_compile(const std::string& dts); #endif

#include "devices.h" #include "processor.h" #include <fstream> dump_t::dump_t() : ofs("dump.bin") { // printf("Calling Dump\n"); } bool dump_t::load(reg_t addr, size_t len, uint8_t* bytes) { return true; } bool dump_t::store(reg_t addr, size_t len, const uint8_t* bytes) { // printf("DUmpping\n"); ofs.write(reinterpret_cast<const char *>(bytes), len); return true; }

// See LICENSE for license details. #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 #define MSTATUS_MIE 0x00000008 #define MSTATUS_UPIE 0x00000010 #define MSTATUS_SPIE 0x00000020 #define MSTATUS_HPIE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 #define MSTATUS_HPP 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 #define MSTATUS_SUM 0x00040000 #define MSTATUS_MXR 0x00080000 #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 #define MSTATUS64_SD 0x8000000000000000 #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) #define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) #define DCSR_EBREAKU (1<<12) #define DCSR_STOPCYCLE (1<<10) #define DCSR_STOPTIME (1<<9) #define DCSR_CAUSE (7<<6) #define DCSR_DEBUGINT (1<<5) #define DCSR_HALT (1<<3) #define DCSR_STEP (1<<2) #define DCSR_PRV (3<<0) #define DCSR_CAUSE_NONE 0 #define DCSR_CAUSE_SWBP 1 #define DCSR_CAUSE_HWBP 2 #define DCSR_CAUSE_DEBUGINT 3 #define DCSR_CAUSE_STEP 4 #define DCSR_CAUSE_HALT 5 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) #define MCONTROL_SELECT (1<<19) #define MCONTROL_TIMING (1<<18) #define MCONTROL_ACTION (0x3f<<12) #define MCONTROL_CHAIN (1<<11) #define MCONTROL_MATCH (0xf<<7) #define MCONTROL_M (1<<6) #define MCONTROL_H (1<<5) #define MCONTROL_S (1<<4) #define MCONTROL_U (1<<3) #define MCONTROL_EXECUTE (1<<2) #define MCONTROL_STORE (1<<1) #define MCONTROL_LOAD (1<<0) #define MCONTROL_TYPE_NONE 0 #define MCONTROL_TYPE_MATCH 2 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 #define MCONTROL_ACTION_DEBUG_MODE 1 #define MCONTROL_ACTION_TRACE_START 2 #define MCONTROL_ACTION_TRACE_STOP 3 #define MCONTROL_ACTION_TRACE_EMIT 4 #define MCONTROL_MATCH_EQUAL 0 #define MCONTROL_MATCH_NAPOT 1 #define MCONTROL_MATCH_GE 2 #define MCONTROL_MATCH_LT 3 #define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_STIP (1 << IRQ_S_TIMER) #define MIP_HTIP (1 << IRQ_H_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_HEIP (1 << IRQ_H_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 #define PRV_M 3 #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7FC00000 #define SATP32_PPN 0x003FFFFF #define SATP64_MODE 0xF000000000000000 #define SATP64_ASID 0x0FFFF00000000000 #define SATP64_PPN 0x00000FFFFFFFFFFF #define SATP_MODE_OFF 0 #define SATP_MODE_SV32 1 #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 #define SATP_MODE_SV57 10 #define SATP_MODE_SV64 11 #define PMP_R 0x01 #define PMP_W 0x02 #define PMP_X 0x04 #define PMP_A 0x18 #define PMP_L 0x80 #define PMP_SHIFT 2 #define PMP_TOR 0x08 #define PMP_NA4 0x10 #define PMP_NAPOT 0x18 #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_S_TIMER 5 #define IRQ_H_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_S_EXT 9 #define IRQ_H_EXT 10 #define IRQ_M_EXT 11 #define IRQ_COP 12 #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00010000 #define CLINT_BASE 0x02000000 #define CLINT_SIZE 0x000c0000 #define UART_BASE 0x10000000 #define UART_SIZE 0x00010000 #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 #define DUMP_BASE 0x82000000 #define DUMP_SIZE 0x20000000 // page table entry (PTE) fields #define PTE_V 0x001 // Valid #define PTE_R 0x002 // Read #define PTE_W 0x004 // Write #define PTE_X 0x008 // Execute #define PTE_U 0x010 // User #define PTE_G 0x020 // Global #define PTE_A 0x040 // Accessed #define PTE_D 0x080 // Dirty #define PTE_SOFT 0x300 // Reserved for Software #define PTE_PPN_SHIFT 10 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) #ifdef __riscv #if __riscv_xlen == 64 # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVEL_BITS 9 # define SATP_MODE SATP64_MODE #else # define MSTATUS_SD MSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVEL_BITS 10 # define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) #ifndef __ASSEMBLER__ #ifdef __GNUC__ #define read_csr(reg) ({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) #define write_csr(reg, val) ({ \ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ __tmp; }) #define set_csr(reg, bit) ({ unsigned long __tmp; \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define clear_csr(reg, bit) ({ unsigned long __tmp; \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) #define rdinstret() read_csr(instret) #endif #endif #endif #endif /* Automatically generated by parse-opcodes. */ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H #define MATCH_BEQ 0x63 #define MASK_BEQ 0x707f #define MATCH_BNE 0x1063 #define MASK_BNE 0x707f #define MATCH_BLT 0x4063 #define MASK_BLT 0x707f #define MATCH_BGE 0x5063 #define MASK_BGE 0x707f #define MATCH_BLTU 0x6063 #define MASK_BLTU 0x707f #define MATCH_BGEU 0x7063 #define MASK_BGEU 0x707f #define MATCH_JALR 0x67 #define MASK_JALR 0x707f #define MATCH_JAL 0x6f #define MASK_JAL 0x7f #define MATCH_LUI 0x37 #define MASK_LUI 0x7f #define MATCH_AUIPC 0x17 #define MASK_AUIPC 0x7f #define MATCH_ADDI 0x13 #define MASK_ADDI 0x707f #define MATCH_SLLI 0x1013 #define MASK_SLLI 0xfc00707f #define MATCH_SLTI 0x2013 #define MASK_SLTI 0x707f #define MATCH_SLTIU 0x3013 #define MASK_SLTIU 0x707f #define MATCH_XORI 0x4013 #define MASK_XORI 0x707f #define MATCH_SRLI 0x5013 #define MASK_SRLI 0xfc00707f #define MATCH_SRAI 0x40005013 #define MASK_SRAI 0xfc00707f #define MATCH_ORI 0x6013 #define MASK_ORI 0x707f #define MATCH_ANDI 0x7013 #define MASK_ANDI 0x707f #define MATCH_ADD 0x33 #define MASK_ADD 0xfe00707f #define MATCH_SUB 0x40000033 #define MASK_SUB 0xfe00707f #define MATCH_SLL 0x1033 #define MASK_SLL 0xfe00707f #define MATCH_SLT 0x2033 #define MASK_SLT 0xfe00707f #define MATCH_SLTU 0x3033 #define MASK_SLTU 0xfe00707f #define MATCH_XOR 0x4033 #define MASK_XOR 0xfe00707f #define MATCH_SRL 0x5033 #define MASK_SRL 0xfe00707f #define MATCH_SRA 0x40005033 #define MASK_SRA 0xfe00707f #define MATCH_OR 0x6033 #define MASK_OR 0xfe00707f #define MATCH_AND 0x7033 #define MASK_AND 0xfe00707f #define MATCH_ADDIW 0x1b #define MASK_ADDIW 0x707f #define MATCH_SLLIW 0x101b #define MASK_SLLIW 0xfe00707f #define MATCH_SRLIW 0x501b #define MASK_SRLIW 0xfe00707f #define MATCH_SRAIW 0x4000501b #define MASK_SRAIW 0xfe00707f #define MATCH_ADDW 0x3b #define MASK_ADDW 0xfe00707f #define MATCH_SUBW 0x4000003b #define MASK_SUBW 0xfe00707f #define MATCH_SLLW 0x103b #define MASK_SLLW 0xfe00707f #define MATCH_SRLW 0x503b #define MASK_SRLW 0xfe00707f #define MATCH_SRAW 0x4000503b #define MASK_SRAW 0xfe00707f #define MATCH_LB 0x3 #define MASK_LB 0x707f #define MATCH_LH 0x1003 #define MASK_LH 0x707f #define MATCH_LW 0x2003 #define MASK_LW 0x707f #define MATCH_LD 0x3003 #define MASK_LD 0x707f #define MATCH_LBU 0x4003 #define MASK_LBU 0x707f #define MATCH_LHU 0x5003 #define MASK_LHU 0x707f #define MATCH_LWU 0x6003 #define MASK_LWU 0x707f #define MATCH_SB 0x23 #define MASK_SB 0x707f #define MATCH_SH 0x1023 #define MASK_SH 0x707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f #define MATCH_SD 0x3023 #define MASK_SD 0x707f #define MATCH_FENCE 0xf #define MASK_FENCE 0x707f #define MATCH_FENCE_I 0x100f #define MASK_FENCE_I 0x707f #define MATCH_MUL 0x2000033 #define MASK_MUL 0xfe00707f #define MATCH_MULH 0x2001033 #define MASK_MULH 0xfe00707f #define MATCH_MULHSU 0x2002033 #define MASK_MULHSU 0xfe00707f #define MATCH_MULHU 0x2003033 #define MASK_MULHU 0xfe00707f #define MATCH_DIV 0x2004033 #define MASK_DIV 0xfe00707f #define MATCH_DIVU 0x2005033 #define MASK_DIVU 0xfe00707f #define MATCH_REM 0x2006033 #define MASK_REM 0xfe00707f #define MATCH_REMU 0x2007033 #define MASK_REMU 0xfe00707f #define MATCH_MULW 0x200003b #define MASK_MULW 0xfe00707f #define MATCH_DIVW 0x200403b #define MASK_DIVW 0xfe00707f #define MATCH_DIVUW 0x200503b #define MASK_DIVUW 0xfe00707f #define MATCH_REMW 0x200603b #define MASK_REMW 0xfe00707f #define MATCH_REMUW 0x200703b #define MASK_REMUW 0xfe00707f #define MATCH_AMOADD_W 0x202f #define MASK_AMOADD_W 0xf800707f #define MATCH_AMOXOR_W 0x2000202f #define MASK_AMOXOR_W 0xf800707f #define MATCH_AMOOR_W 0x4000202f #define MASK_AMOOR_W 0xf800707f #define MATCH_AMOAND_W 0x6000202f #define MASK_AMOAND_W 0xf800707f #define MATCH_AMOMIN_W 0x8000202f #define MASK_AMOMIN_W 0xf800707f #define MATCH_AMOMAX_W 0xa000202f #define MASK_AMOMAX_W 0xf800707f #define MATCH_AMOMINU_W 0xc000202f #define MASK_AMOMINU_W 0xf800707f #define MATCH_AMOMAXU_W 0xe000202f #define MASK_AMOMAXU_W 0xf800707f #define MATCH_AMOSWAP_W 0x800202f #define MASK_AMOSWAP_W 0xf800707f #define MATCH_LR_W 0x1000202f #define MASK_LR_W 0xf9f0707f #define MATCH_SC_W 0x1800202f #define MASK_SC_W 0xf800707f #define MATCH_AMOADD_D 0x302f #define MASK_AMOADD_D 0xf800707f #define MATCH_AMOXOR_D 0x2000302f #define MASK_AMOXOR_D 0xf800707f #define MATCH_AMOOR_D 0x4000302f #define MASK_AMOOR_D 0xf800707f #define MATCH_AMOAND_D 0x6000302f #define MASK_AMOAND_D 0xf800707f #define MATCH_AMOMIN_D 0x8000302f #define MASK_AMOMIN_D 0xf800707f #define MATCH_AMOMAX_D 0xa000302f #define MASK_AMOMAX_D 0xf800707f #define MATCH_AMOMINU_D 0xc000302f #define MASK_AMOMINU_D 0xf800707f #define MATCH_AMOMAXU_D 0xe000302f #define MASK_AMOMAXU_D 0xf800707f #define MATCH_AMOSWAP_D 0x800302f #define MASK_AMOSWAP_D 0xf800707f #define MATCH_LR_D 0x1000302f #define MASK_LR_D 0xf9f0707f #define MATCH_SC_D 0x1800302f #define MASK_SC_D 0xf800707f #define MATCH_ECALL 0x73 #define MASK_ECALL 0xffffffff #define MATCH_EBREAK 0x100073 #define MASK_EBREAK 0xffffffff #define MATCH_URET 0x200073 #define MASK_URET 0xffffffff #define MATCH_SRET 0x10200073 #define MASK_SRET 0xffffffff #define MATCH_MRET 0x30200073 #define MASK_MRET 0xffffffff #define MATCH_DRET 0x7b200073 #define MASK_DRET 0xffffffff #define MATCH_SFENCE_VMA 0x12000073 #define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 #define MASK_CSRRW 0x707f #define MATCH_CSRRS 0x2073 #define MASK_CSRRS 0x707f #define MATCH_CSRRC 0x3073 #define MASK_CSRRC 0x707f #define MATCH_CSRRWI 0x5073 #define MASK_CSRRWI 0x707f #define MATCH_CSRRSI 0x6073 #define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 #define MASK_CSRRCI 0x707f #define MATCH_FADD_S 0x53 #define MASK_FADD_S 0xfe00007f #define MATCH_FSUB_S 0x8000053 #define MASK_FSUB_S 0xfe00007f #define MATCH_FMUL_S 0x10000053 #define MASK_FMUL_S 0xfe00007f #define MATCH_FDIV_S 0x18000053 #define MASK_FDIV_S 0xfe00007f #define MATCH_FSGNJ_S 0x20000053 #define MASK_FSGNJ_S 0xfe00707f #define MATCH_FSGNJN_S 0x20001053 #define MASK_FSGNJN_S 0xfe00707f #define MATCH_FSGNJX_S 0x20002053 #define MASK_FSGNJX_S 0xfe00707f #define MATCH_FMIN_S 0x28000053 #define MASK_FMIN_S 0xfe00707f #define MATCH_FMAX_S 0x28001053 #define MASK_FMAX_S 0xfe00707f #define MATCH_FSQRT_S 0x58000053 #define MASK_FSQRT_S 0xfff0007f #define MATCH_FADD_D 0x2000053 #define MASK_FADD_D 0xfe00007f #define MATCH_FSUB_D 0xa000053 #define MASK_FSUB_D 0xfe00007f #define MATCH_FMUL_D 0x12000053 #define MASK_FMUL_D 0xfe00007f #define MATCH_FDIV_D 0x1a000053 #define MASK_FDIV_D 0xfe00007f #define MATCH_FSGNJ_D 0x22000053 #define MASK_FSGNJ_D 0xfe00707f #define MATCH_FSGNJN_D 0x22001053 #define MASK_FSGNJN_D 0xfe00707f #define MATCH_FSGNJX_D 0x22002053 #define MASK_FSGNJX_D 0xfe00707f #define MATCH_FMIN_D 0x2a000053 #define MASK_FMIN_D 0xfe00707f #define MATCH_FMAX_D 0x2a001053 #define MASK_FMAX_D 0xfe00707f #define MATCH_FCVT_S_D 0x40100053 #define MASK_FCVT_S_D 0xfff0007f #define MATCH_FCVT_D_S 0x42000053 #define MASK_FCVT_D_S 0xfff0007f #define MATCH_FSQRT_D 0x5a000053 #define MASK_FSQRT_D 0xfff0007f #define MATCH_FADD_Q 0x6000053 #define MASK_FADD_Q 0xfe00007f #define MATCH_FSUB_Q 0xe000053 #define MASK_FSUB_Q 0xfe00007f #define MATCH_FMUL_Q 0x16000053 #define MASK_FMUL_Q 0xfe00007f #define MATCH_FDIV_Q 0x1e000053 #define MASK_FDIV_Q 0xfe00007f #define MATCH_FSGNJ_Q 0x26000053 #define MASK_FSGNJ_Q 0xfe00707f #define MATCH_FSGNJN_Q 0x26001053 #define MASK_FSGNJN_Q 0xfe00707f #define MATCH_FSGNJX_Q 0x26002053 #define MASK_FSGNJX_Q 0xfe00707f #define MATCH_FMIN_Q 0x2e000053 #define MASK_FMIN_Q 0xfe00707f #define MATCH_FMAX_Q 0x2e001053 #define MASK_FMAX_Q 0xfe00707f #define MATCH_FCVT_S_Q 0x40300053 #define MASK_FCVT_S_Q 0xfff0007f #define MATCH_FCVT_Q_S 0x46000053 #define MASK_FCVT_Q_S 0xfff0007f #define MATCH_FCVT_D_Q 0x42300053 #define MASK_FCVT_D_Q 0xfff0007f #define MATCH_FCVT_Q_D 0x46100053 #define MASK_FCVT_Q_D 0xfff0007f #define MATCH_FSQRT_Q 0x5e000053 #define MASK_FSQRT_Q 0xfff0007f #define MATCH_FLE_S 0xa0000053 #define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 #define MASK_FLT_S 0xfe00707f #define MATCH_FEQ_S 0xa0002053 #define MASK_FEQ_S 0xfe00707f #define MATCH_FLE_D 0xa2000053 #define MASK_FLE_D 0xfe00707f #define MATCH_FLT_D 0xa2001053 #define MASK_FLT_D 0xfe00707f #define MATCH_FEQ_D 0xa2002053 #define MASK_FEQ_D 0xfe00707f #define MATCH_FLE_Q 0xa6000053 #define MASK_FLE_Q 0xfe00707f #define MATCH_FLT_Q 0xa6001053 #define MASK_FLT_Q 0xfe00707f #define MATCH_FEQ_Q 0xa6002053 #define MASK_FEQ_Q 0xfe00707f #define MATCH_FCVT_W_S 0xc0000053 #define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 #define MASK_FCVT_WU_S 0xfff0007f #define MATCH_FCVT_L_S 0xc0200053 #define MASK_FCVT_L_S 0xfff0007f #define MATCH_FCVT_LU_S 0xc0300053 #define MASK_FCVT_LU_S 0xfff0007f #define MATCH_FMV_X_W 0xe0000053 #define MASK_FMV_X_W 0xfff0707f #define MATCH_FCLASS_S 0xe0001053 #define MASK_FCLASS_S 0xfff0707f #define MATCH_FCVT_W_D 0xc2000053 #define MASK_FCVT_W_D 0xfff0007f #define MATCH_FCVT_WU_D 0xc2100053 #define MASK_FCVT_WU_D 0xfff0007f #define MATCH_FCVT_L_D 0xc2200053 #define MASK_FCVT_L_D 0xfff0007f #define MATCH_FCVT_LU_D 0xc2300053 #define MASK_FCVT_LU_D 0xfff0007f #define MATCH_FMV_X_D 0xe2000053 #define MASK_FMV_X_D 0xfff0707f #define MATCH_FCLASS_D 0xe2001053 #define MASK_FCLASS_D 0xfff0707f #define MATCH_FCVT_W_Q 0xc6000053 #define MASK_FCVT_W_Q 0xfff0007f #define MATCH_FCVT_WU_Q 0xc6100053 #define MASK_FCVT_WU_Q 0xfff0007f #define MATCH_FCVT_L_Q 0xc6200053 #define MASK_FCVT_L_Q 0xfff0007f #define MATCH_FCVT_LU_Q 0xc6300053 #define MASK_FCVT_LU_Q 0xfff0007f #define MATCH_FMV_X_Q 0xe6000053 #define MASK_FMV_X_Q 0xfff0707f #define MATCH_FCLASS_Q 0xe6001053 #define MASK_FCLASS_Q 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 #define MASK_FCVT_S_WU 0xfff0007f #define MATCH_FCVT_S_L 0xd0200053 #define MASK_FCVT_S_L 0xfff0007f #define MATCH_FCVT_S_LU 0xd0300053 #define MASK_FCVT_S_LU 0xfff0007f #define MATCH_FMV_W_X 0xf0000053 #define MASK_FMV_W_X 0xfff0707f #define MATCH_FCVT_D_W 0xd2000053 #define MASK_FCVT_D_W 0xfff0007f #define MATCH_FCVT_D_WU 0xd2100053 #define MASK_FCVT_D_WU 0xfff0007f #define MATCH_FCVT_D_L 0xd2200053 #define MASK_FCVT_D_L 0xfff0007f #define MATCH_FCVT_D_LU 0xd2300053 #define MASK_FCVT_D_LU 0xfff0007f #define MATCH_FMV_D_X 0xf2000053 #define MASK_FMV_D_X 0xfff0707f #define MATCH_FCVT_Q_W 0xd6000053 #define MASK_FCVT_Q_W 0xfff0007f #define MATCH_FCVT_Q_WU 0xd6100053 #define MASK_FCVT_Q_WU 0xfff0007f #define MATCH_FCVT_Q_L 0xd6200053 #define MASK_FCVT_Q_L 0xfff0007f #define MATCH_FCVT_Q_LU 0xd6300053 #define MASK_FCVT_Q_LU 0xfff0007f #define MATCH_FMV_Q_X 0xf6000053 #define MASK_FMV_Q_X 0xfff0707f #define MATCH_FLW 0x2007 #define MASK_FLW 0x707f #define MATCH_FLD 0x3007 #define MASK_FLD 0x707f #define MATCH_FLQ 0x4007 #define MASK_FLQ 0x707f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f #define MATCH_FSD 0x3027 #define MASK_FSD 0x707f #define MATCH_FSQ 0x4027 #define MASK_FSQ 0x707f #define MATCH_FMADD_S 0x43 #define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 #define MASK_FMSUB_S 0x600007f #define MATCH_FNMSUB_S 0x4b #define MASK_FNMSUB_S 0x600007f #define MATCH_FNMADD_S 0x4f #define MASK_FNMADD_S 0x600007f #define MATCH_FMADD_D 0x2000043 #define MASK_FMADD_D 0x600007f #define MATCH_FMSUB_D 0x2000047 #define MASK_FMSUB_D 0x600007f #define MATCH_FNMSUB_D 0x200004b #define MASK_FNMSUB_D 0x600007f #define MATCH_FNMADD_D 0x200004f #define MASK_FNMADD_D 0x600007f #define MATCH_FMADD_Q 0x6000043 #define MASK_FMADD_Q 0x600007f #define MATCH_FMSUB_Q 0x6000047 #define MASK_FMSUB_Q 0x600007f #define MATCH_FNMSUB_Q 0x600004b #define MASK_FNMSUB_Q 0x600007f #define MATCH_FNMADD_Q 0x600004f #define MASK_FNMADD_Q 0x600007f #define MATCH_C_NOP 0x1 #define MASK_C_NOP 0xffff #define MATCH_C_ADDI16SP 0x6101 #define MASK_C_ADDI16SP 0xef83 #define MATCH_C_JR 0x8002 #define MASK_C_JR 0xf07f #define MATCH_C_JALR 0x9002 #define MASK_C_JALR 0xf07f #define MATCH_C_EBREAK 0x9002 #define MASK_C_EBREAK 0xffff #define MATCH_C_LD 0x6000 #define MASK_C_LD 0xe003 #define MATCH_C_SD 0xe000 #define MASK_C_SD 0xe003 #define MATCH_C_ADDIW 0x2001 #define MASK_C_ADDIW 0xe003 #define MATCH_C_LDSP 0x6002 #define MASK_C_LDSP 0xe003 #define MATCH_C_SDSP 0xe002 #define MASK_C_SDSP 0xe003 #define MATCH_C_ADDI4SPN 0x0 #define MASK_C_ADDI4SPN 0xe003 #define MATCH_C_FLD 0x2000 #define MASK_C_FLD 0xe003 #define MATCH_C_LW 0x4000 #define MASK_C_LW 0xe003 #define MATCH_C_FLW 0x6000 #define MASK_C_FLW 0xe003 #define MATCH_C_FSD 0xa000 #define MASK_C_FSD 0xe003 #define MATCH_C_SW 0xc000 #define MASK_C_SW 0xe003 #define MATCH_C_FSW 0xe000 #define MASK_C_FSW 0xe003 #define MATCH_C_ADDI 0x1 #define MASK_C_ADDI 0xe003 #define MATCH_C_JAL 0x2001 #define MASK_C_JAL 0xe003 #define MATCH_C_LI 0x4001 #define MASK_C_LI 0xe003 #define MATCH_C_LUI 0x6001 #define MASK_C_LUI 0xe003 #define MATCH_C_SRLI 0x8001 #define MASK_C_SRLI 0xec03 #define MATCH_C_SRAI 0x8401 #define MASK_C_SRAI 0xec03 #define MATCH_C_ANDI 0x8801 #define MASK_C_ANDI 0xec03 #define MATCH_C_SUB 0x8c01 #define MASK_C_SUB 0xfc63 #define MATCH_C_XOR 0x8c21 #define MASK_C_XOR 0xfc63 #define MATCH_C_OR 0x8c41 #define MASK_C_OR 0xfc63 #define MATCH_C_AND 0x8c61 #define MASK_C_AND 0xfc63 #define MATCH_C_SUBW 0x9c01 #define MASK_C_SUBW 0xfc63 #define MATCH_C_ADDW 0x9c21 #define MASK_C_ADDW 0xfc63 #define MATCH_C_J 0xa001 #define MASK_C_J 0xe003 #define MATCH_C_BEQZ 0xc001 #define MASK_C_BEQZ 0xe003 #define MATCH_C_BNEZ 0xe001 #define MASK_C_BNEZ 0xe003 #define MATCH_C_SLLI 0x2 #define MASK_C_SLLI 0xe003 #define MATCH_C_FLDSP 0x2002 #define MASK_C_FLDSP 0xe003 #define MATCH_C_LWSP 0x4002 #define MASK_C_LWSP 0xe003 #define MATCH_C_FLWSP 0x6002 #define MASK_C_FLWSP 0xe003 #define MATCH_C_MV 0x8002 #define MASK_C_MV 0xf003 #define MATCH_C_ADD 0x9002 #define MASK_C_ADD 0xf003 #define MATCH_C_FSDSP 0xa002 #define MASK_C_FSDSP 0xe003 #define MATCH_C_SWSP 0xc002 #define MASK_C_SWSP 0xe003 #define MATCH_C_FSWSP 0xe002 #define MASK_C_FSWSP 0xe003 #define MATCH_CUSTOM0 0xb #define MASK_CUSTOM0 0x707f #define MATCH_CUSTOM0_RS1 0x200b #define MASK_CUSTOM0_RS1 0x707f #define MATCH_CUSTOM0_RS1_RS2 0x300b #define MASK_CUSTOM0_RS1_RS2 0x707f #define MATCH_CUSTOM0_RD 0x400b #define MASK_CUSTOM0_RD 0x707f #define MATCH_CUSTOM0_RD_RS1 0x600b #define MASK_CUSTOM0_RD_RS1 0x707f #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b #define MASK_CUSTOM0_RD_RS1_RS2 0x707f #define MATCH_CUSTOM1 0x2b #define MASK_CUSTOM1 0x707f #define MATCH_CUSTOM1_RS1 0x202b #define MASK_CUSTOM1_RS1 0x707f #define MATCH_CUSTOM1_RS1_RS2 0x302b #define MASK_CUSTOM1_RS1_RS2 0x707f #define MATCH_CUSTOM1_RD 0x402b #define MASK_CUSTOM1_RD 0x707f #define MATCH_CUSTOM1_RD_RS1 0x602b #define MASK_CUSTOM1_RD_RS1 0x707f #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b #define MASK_CUSTOM1_RD_RS1_RS2 0x707f #define MATCH_CUSTOM2 0x5b #define MASK_CUSTOM2 0x707f #define MATCH_CUSTOM2_RS1 0x205b #define MASK_CUSTOM2_RS1 0x707f #define MATCH_CUSTOM2_RS1_RS2 0x305b #define MASK_CUSTOM2_RS1_RS2 0x707f #define MATCH_CUSTOM2_RD 0x405b #define MASK_CUSTOM2_RD 0x707f #define MATCH_CUSTOM2_RD_RS1 0x605b #define MASK_CUSTOM2_RD_RS1 0x707f #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b #define MASK_CUSTOM2_RD_RS1_RS2 0x707f #define MATCH_CUSTOM3 0x7b #define MASK_CUSTOM3 0x707f #define MATCH_CUSTOM3_RS1 0x207b #define MASK_CUSTOM3_RS1 0x707f #define MATCH_CUSTOM3_RS1_RS2 0x307b #define MASK_CUSTOM3_RS1_RS2 0x707f #define MATCH_CUSTOM3_RD 0x407b #define MASK_CUSTOM3_RD 0x707f #define MATCH_CUSTOM3_RD_RS1 0x607b #define MASK_CUSTOM3_RD_RS1 0x707f #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b #define MASK_CUSTOM3_RD_RS1_RS2 0x707f #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 #define CSR_HPMCOUNTER3 0xc03 #define CSR_HPMCOUNTER4 0xc04 #define CSR_HPMCOUNTER5 0xc05 #define CSR_HPMCOUNTER6 0xc06 #define CSR_HPMCOUNTER7 0xc07 #define CSR_HPMCOUNTER8 0xc08 #define CSR_HPMCOUNTER9 0xc09 #define CSR_HPMCOUNTER10 0xc0a #define CSR_HPMCOUNTER11 0xc0b #define CSR_HPMCOUNTER12 0xc0c #define CSR_HPMCOUNTER13 0xc0d #define CSR_HPMCOUNTER14 0xc0e #define CSR_HPMCOUNTER15 0xc0f #define CSR_HPMCOUNTER16 0xc10 #define CSR_HPMCOUNTER17 0xc11 #define CSR_HPMCOUNTER18 0xc12 #define CSR_HPMCOUNTER19 0xc13 #define CSR_HPMCOUNTER20 0xc14 #define CSR_HPMCOUNTER21 0xc15 #define CSR_HPMCOUNTER22 0xc16 #define CSR_HPMCOUNTER23 0xc17 #define CSR_HPMCOUNTER24 0xc18 #define CSR_HPMCOUNTER25 0xc19 #define CSR_HPMCOUNTER26 0xc1a #define CSR_HPMCOUNTER27 0xc1b #define CSR_HPMCOUNTER28 0xc1c #define CSR_HPMCOUNTER29 0xc1d #define CSR_HPMCOUNTER30 0xc1e #define CSR_HPMCOUNTER31 0xc1f #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MEDELEG 0x302 #define CSR_MIDELEG 0x303 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG2 0x3a2 #define CSR_PMPCFG3 0x3a3 #define CSR_PMPADDR0 0x3b0 #define CSR_PMPADDR1 0x3b1 #define CSR_PMPADDR2 0x3b2 #define CSR_PMPADDR3 0x3b3 #define CSR_PMPADDR4 0x3b4 #define CSR_PMPADDR5 0x3b5 #define CSR_PMPADDR6 0x3b6 #define CSR_PMPADDR7 0x3b7 #define CSR_PMPADDR8 0x3b8 #define CSR_PMPADDR9 0x3b9 #define CSR_PMPADDR10 0x3ba #define CSR_PMPADDR11 0x3bb #define CSR_PMPADDR12 0x3bc #define CSR_PMPADDR13 0x3bd #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 #define CSR_MCYCLE 0xb00 #define CSR_MINSTRET 0xb02 #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 #define CSR_MHPMCOUNTER5 0xb05 #define CSR_MHPMCOUNTER6 0xb06 #define CSR_MHPMCOUNTER7 0xb07 #define CSR_MHPMCOUNTER8 0xb08 #define CSR_MHPMCOUNTER9 0xb09 #define CSR_MHPMCOUNTER10 0xb0a #define CSR_MHPMCOUNTER11 0xb0b #define CSR_MHPMCOUNTER12 0xb0c #define CSR_MHPMCOUNTER13 0xb0d #define CSR_MHPMCOUNTER14 0xb0e #define CSR_MHPMCOUNTER15 0xb0f #define CSR_MHPMCOUNTER16 0xb10 #define CSR_MHPMCOUNTER17 0xb11 #define CSR_MHPMCOUNTER18 0xb12 #define CSR_MHPMCOUNTER19 0xb13 #define CSR_MHPMCOUNTER20 0xb14 #define CSR_MHPMCOUNTER21 0xb15 #define CSR_MHPMCOUNTER22 0xb16 #define CSR_MHPMCOUNTER23 0xb17 #define CSR_MHPMCOUNTER24 0xb18 #define CSR_MHPMCOUNTER25 0xb19 #define CSR_MHPMCOUNTER26 0xb1a #define CSR_MHPMCOUNTER27 0xb1b #define CSR_MHPMCOUNTER28 0xb1c #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 #define CSR_MHPMEVENT6 0x326 #define CSR_MHPMEVENT7 0x327 #define CSR_MHPMEVENT8 0x328 #define CSR_MHPMEVENT9 0x329 #define CSR_MHPMEVENT10 0x32a #define CSR_MHPMEVENT11 0x32b #define CSR_MHPMEVENT12 0x32c #define CSR_MHPMEVENT13 0x32d #define CSR_MHPMEVENT14 0x32e #define CSR_MHPMEVENT15 0x32f #define CSR_MHPMEVENT16 0x330 #define CSR_MHPMEVENT17 0x331 #define CSR_MHPMEVENT18 0x332 #define CSR_MHPMEVENT19 0x333 #define CSR_MHPMEVENT20 0x334 #define CSR_MHPMEVENT21 0x335 #define CSR_MHPMEVENT22 0x336 #define CSR_MHPMEVENT23 0x337 #define CSR_MHPMEVENT24 0x338 #define CSR_MHPMEVENT25 0x339 #define CSR_MHPMEVENT26 0x33a #define CSR_MHPMEVENT27 0x33b #define CSR_MHPMEVENT28 0x33c #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 #define CSR_HPMCOUNTER3H 0xc83 #define CSR_HPMCOUNTER4H 0xc84 #define CSR_HPMCOUNTER5H 0xc85 #define CSR_HPMCOUNTER6H 0xc86 #define CSR_HPMCOUNTER7H 0xc87 #define CSR_HPMCOUNTER8H 0xc88 #define CSR_HPMCOUNTER9H 0xc89 #define CSR_HPMCOUNTER10H 0xc8a #define CSR_HPMCOUNTER11H 0xc8b #define CSR_HPMCOUNTER12H 0xc8c #define CSR_HPMCOUNTER13H 0xc8d #define CSR_HPMCOUNTER14H 0xc8e #define CSR_HPMCOUNTER15H 0xc8f #define CSR_HPMCOUNTER16H 0xc90 #define CSR_HPMCOUNTER17H 0xc91 #define CSR_HPMCOUNTER18H 0xc92 #define CSR_HPMCOUNTER19H 0xc93 #define CSR_HPMCOUNTER20H 0xc94 #define CSR_HPMCOUNTER21H 0xc95 #define CSR_HPMCOUNTER22H 0xc96 #define CSR_HPMCOUNTER23H 0xc97 #define CSR_HPMCOUNTER24H 0xc98 #define CSR_HPMCOUNTER25H 0xc99 #define CSR_HPMCOUNTER26H 0xc9a #define CSR_HPMCOUNTER27H 0xc9b #define CSR_HPMCOUNTER28H 0xc9c #define CSR_HPMCOUNTER29H 0xc9d #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f #define CSR_MCYCLEH 0xb80 #define CSR_MINSTRETH 0xb82 #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 #define CSR_MHPMCOUNTER6H 0xb86 #define CSR_MHPMCOUNTER7H 0xb87 #define CSR_MHPMCOUNTER8H 0xb88 #define CSR_MHPMCOUNTER9H 0xb89 #define CSR_MHPMCOUNTER10H 0xb8a #define CSR_MHPMCOUNTER11H 0xb8b #define CSR_MHPMCOUNTER12H 0xb8c #define CSR_MHPMCOUNTER13H 0xb8d #define CSR_MHPMCOUNTER14H 0xb8e #define CSR_MHPMCOUNTER15H 0xb8f #define CSR_MHPMCOUNTER16H 0xb90 #define CSR_MHPMCOUNTER17H 0xb91 #define CSR_MHPMCOUNTER18H 0xb92 #define CSR_MHPMCOUNTER19H 0xb93 #define CSR_MHPMCOUNTER20H 0xb94 #define CSR_MHPMCOUNTER21H 0xb95 #define CSR_MHPMCOUNTER22H 0xb96 #define CSR_MHPMCOUNTER23H 0xb97 #define CSR_MHPMCOUNTER24H 0xb98 #define CSR_MHPMCOUNTER25H 0xb99 #define CSR_MHPMCOUNTER26H 0xb9a #define CSR_MHPMCOUNTER27H 0xb9b #define CSR_MHPMCOUNTER28H 0xb9c #define CSR_MHPMCOUNTER29H 0xb9d #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FETCH_ACCESS 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_LOAD_ACCESS 0x5 #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_STORE_ACCESS 0x7 #define CAUSE_USER_ECALL 0x8 #define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd #define CAUSE_STORE_PAGE_FAULT 0xf #endif #ifdef DECLARE_INSN DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) DECLARE_INSN(add, MATCH_ADD, MASK_ADD) DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) DECLARE_INSN(or, MATCH_OR, MASK_OR) DECLARE_INSN(and, MATCH_AND, MASK_AND) DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) DECLARE_INSN(lb, MATCH_LB, MASK_LB) DECLARE_INSN(lh, MATCH_LH, MASK_LH) DECLARE_INSN(lw, MATCH_LW, MASK_LW) DECLARE_INSN(ld, MATCH_LD, MASK_LD) DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) DECLARE_INSN(sb, MATCH_SB, MASK_SB) DECLARE_INSN(sh, MATCH_SH, MASK_SH) DECLARE_INSN(sw, MATCH_SW, MASK_SW) DECLARE_INSN(sd, MATCH_SD, MASK_SD) DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) DECLARE_INSN(div, MATCH_DIV, MASK_DIV) DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) DECLARE_INSN(rem, MATCH_REM, MASK_REM) DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) DECLARE_INSN(uret, MATCH_URET, MASK_URET) DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) #endif #ifdef DECLARE_CSR DECLARE_CSR(fflags, CSR_FFLAGS) DECLARE_CSR(frm, CSR_FRM) DECLARE_CSR(fcsr, CSR_FCSR) DECLARE_CSR(cycle, CSR_CYCLE) DECLARE_CSR(time, CSR_TIME) DECLARE_CSR(instret, CSR_INSTRET) DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) DECLARE_CSR(scounteren, CSR_SCOUNTEREN) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(stval, CSR_STVAL) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mtval, CSR_MTVAL) DECLARE_CSR(mip, CSR_MIP) // DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) // DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) // DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) // DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) // DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) // DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) // DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) // DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) // DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) // DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) // DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) // DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) // DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) // DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) // DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) // DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) // DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) // DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) // DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) // DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) DECLARE_CSR(tselect, CSR_TSELECT) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) DECLARE_CSR(tdata3, CSR_TDATA3) DECLARE_CSR(dcsr, CSR_DCSR) DECLARE_CSR(dpc, CSR_DPC) DECLARE_CSR(dscratch, CSR_DSCRATCH) DECLARE_CSR(mcycle, CSR_MCYCLE) DECLARE_CSR(minstret, CSR_MINSTRET) DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) DECLARE_CSR(mimpid, CSR_MIMPID) DECLARE_CSR(mhartid, CSR_MHARTID) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) DECLARE_CSR(mcycleh, CSR_MCYCLEH) DECLARE_CSR(minstreth, CSR_MINSTRETH) DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) #endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) #endif

// See LICENSE for license details. #include "processor.h" #include "mmu.h" #include <cassert> static void commit_log_stash_privilege(processor_t* p) { #ifdef RISCV_ENABLE_COMMITLOG state_t* state = p->get_state(); state->last_inst_priv = state->prv; state->last_inst_xlen = p->get_xlen(); state->last_inst_flen = p->get_flen(); #endif } static void commit_log_print_value(int width, uint64_t hi, uint64_t lo) { switch (width) { case 16: fprintf(stderr, "0x%04" PRIx16, (uint16_t)lo); break; case 32: fprintf(stderr, "0x%08" PRIx32, (uint32_t)lo); break; case 64: fprintf(stderr, "0x%016" PRIx64, lo); break; case 128: fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64, hi, lo); break; default: abort(); } } static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn) { #ifdef RISCV_ENABLE_COMMITLOG auto& reg = state->log_reg_write; int priv = state->last_inst_priv; int xlen = state->last_inst_xlen; int flen = state->last_inst_flen; state->last_insn = insn.bits(); if (reg.addr) { bool fp = reg.addr & 1; int rd = reg.addr >> 1; int size = fp ? flen : xlen; } #endif } inline void processor_t::update_histogram(reg_t pc) { #ifdef RISCV_ENABLE_HISTOGRAM pc_histogram[pc]++; #endif } // This is expected to be inlined by the compiler so each use of execute_insn // includes a duplicated body of the function to get separate fetch.func // function calls. static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { commit_log_stash_privilege(p); reg_t npc = fetch.func(p, fetch.insn, pc); if (npc != PC_SERIALIZE_BEFORE) { commit_log_print_insn(p->get_state(), pc, fetch.insn); p->update_histogram(pc); } return npc; } bool processor_t::slow_path() { return debug || state.single_step != state.STEP_NONE || state.dcsr.cause; } // fetch/decode/execute loop void processor_t::step(size_t n) { #ifdef RISCV_ENABLE_COMMITLOG state.was_exception = false; #endif if (state.dcsr.cause == DCSR_CAUSE_NONE) { if (halt_request) { enter_debug_mode(DCSR_CAUSE_DEBUGINT); } // !!!The halt bit in DCSR is deprecated. else if (state.dcsr.halt) { enter_debug_mode(DCSR_CAUSE_HALT); } } while (n > 0) { size_t instret = 0; reg_t pc = state.pc; mmu_t* _mmu = mmu; #define advance_pc() \ if (unlikely(invalid_pc(pc))) { \ switch (pc) { \ case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ case PC_SERIALIZE_AFTER: ++instret; break; \ case PC_SERIALIZE_WFI: n = ++instret; break; \ default: abort(); \ } \ pc = state.pc; \ break; \ } else { \ state.pc = pc; \ instret++; \ } try { insn_fetch_t fetch = mmu->load_insn(pc); // check whether the instruction is an AMO, we dpn't take interrupts on AMOs if (likely((fetch.insn.bits() & 0x2f) != 0x2f)) { take_pending_interrupt(); } if (unlikely(slow_path())) { while (instret < n) { if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) { state.single_step = state.STEP_NONE; if (state.dcsr.cause == DCSR_CAUSE_NONE) { enter_debug_mode(DCSR_CAUSE_STEP); // enter_debug_mode changed state.pc, so we can't just continue. break; } } if (unlikely(state.single_step == state.STEP_STEPPING)) { state.single_step = state.STEP_STEPPED; } if (debug && !state.serialized) disasm(fetch.insn); pc = execute_insn(this, pc, fetch); advance_pc(); if (unlikely(state.pc >= DEBUG_ROM_ENTRY && state.pc < DEBUG_END)) { // We're waiting for the debugger to tell us something. return; } } } else while (instret < n) { // This code uses a modified Duff's Device to improve the performance // of executing instructions. While typical Duff's Devices are used // for software pipelining, the switch statement below primarily // benefits from separate call points for the fetch.func function call // found in each execute_insn. This function call is an indirect jump // that depends on the current instruction. By having an indirect jump // dedicated for each icache entry, you improve the performance of the // host's next address predictor. Each case in the switch statement // allows for the program flow to contine to the next case if it // corresponds to the next instruction in the program and instret is // still less than n. // // According to Andrew Waterman's recollection, this optimization // resulted in approximately a 2x performance increase. // This figures out where to jump to in the switch statement size_t idx = _mmu->icache_index(pc); // This gets the cached decoded instruction from the MMU. If the MMU // does not have the current pc cached, it will refill the MMU and // return the correct entry. ic_entry->data.func is the C++ function // corresponding to the instruction. auto ic_entry = _mmu->access_icache(pc); // This macro is included in "icache.h" included within the switch // statement below. The indirect jump corresponding to the instruction // is located within the execute_insn() function call. #define ICACHE_ACCESS(i) { \ insn_fetch_t fetch = ic_entry->data; \ pc = execute_insn(this, pc, fetch); \ ic_entry = ic_entry->next; \ if (i == mmu_t::ICACHE_ENTRIES-1) break; \ if (unlikely(ic_entry->tag != pc)) break; \ if (unlikely(instret+1 == n)) break; \ instret++; \ state.pc = pc; \ } // This switch statement implements the modified Duff's device as // explained above. switch (idx) { // "icache.h" is generated by the gen_icache script #include "icache.h" } advance_pc(); } } catch(trap_t& t) { #ifdef RISCV_ENABLE_COMMITLOG state.was_exception = true; #endif take_trap(t, pc); n = instret; if (unlikely(state.single_step == state.STEP_STEPPED)) { state.single_step = state.STEP_NONE; enter_debug_mode(DCSR_CAUSE_STEP); } } catch (trigger_matched_t& t) { if (mmu->matched_trigger) { // This exception came from the MMU. That means the instruction hasn't // fully executed yet. We start it again, but this time it won't throw // an exception because matched_trigger is already set. (All memory // instructions are idempotent so restarting is safe.) insn_fetch_t fetch = mmu->load_insn(pc); pc = execute_insn(this, pc, fetch); advance_pc(); delete mmu->matched_trigger; mmu->matched_trigger = NULL; } switch (state.mcontrol[t.index].action) { case ACTION_DEBUG_MODE: enter_debug_mode(DCSR_CAUSE_HWBP); break; case ACTION_DEBUG_EXCEPTION: { mem_trap_t trap(CAUSE_BREAKPOINT, t.address); take_trap(trap, pc); break; } default: abort(); } } state.minstret += instret; n -= instret; } }

// See LICENSE for license details. #include "extension.h" #include "trap.h" extension_t::~extension_t() { } void extension_t::illegal_instruction() { throw trap_illegal_instruction(0); } void extension_t::raise_interrupt() { p->take_interrupt((reg_t)1 << IRQ_COP); // must not return throw std::logic_error("a COP exception was posted, but interrupts are disabled!"); } void extension_t::clear_interrupt() { }

// See LICENSE for license details. #ifndef _RISCV_COPROCESSOR_H #define _RISCV_COPROCESSOR_H #include "processor.h" #include "disasm.h" #include <vector> #include <functional> class extension_t { public: virtual std::vector<insn_desc_t> get_instructions() = 0; virtual std::vector<disasm_insn_t*> get_disasms() = 0; virtual const char* name() = 0; virtual void reset() {}; virtual void set_debug(bool value) {}; virtual ~extension_t(); void set_processor(processor_t* _p) { p = _p; } protected: processor_t* p; void illegal_instruction(); void raise_interrupt(); void clear_interrupt(); }; std::function<extension_t*()> find_extension(const char* name); void register_extension(const char* name, std::function<extension_t*()> f); #define REGISTER_EXTENSION(name, constructor) \ class register_##name { \ public: register_##name() { register_extension(#name, constructor); } \ }; static register_##name dummy_##name; #endif

// See LICENSE for license details. #include "extension.h" #include <string> #include <map> #include <dlfcn.h> static std::map<std::string, std::function<extension_t*()>>& extensions() { static std::map<std::string, std::function<extension_t*()>> v; return v; } void register_extension(const char* name, std::function<extension_t*()> f) { extensions()[name] = f; } std::function<extension_t*()> find_extension(const char* name) { if (!extensions().count(name)) { // try to find extension xyz by loading libxyz.so std::string libname = std::string("lib") + name + ".so"; if (!dlopen(libname.c_str(), RTLD_LAZY)) { fprintf(stderr, "couldn't find extension '%s' (or library '%s')\n", name, libname.c_str()); exit(-1); } if (!extensions().count(name)) { fprintf(stderr, "couldn't find extension '%s' in shared library '%s'\n", name, libname.c_str()); exit(-1); } } return extensions()[name]; }

#!/bin/sh n=$(($1-1)) for i in `seq 0 $n` do echo case $i: ICACHE_ACCESS$$i$\; done echo

// See LICENSE for license details. #include "insn_template.h" reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) { int xlen = 32; reg_t npc = sext_xlen(pc + insn_length(OPCODE)); #include "insns/NAME.h" trace_opcode(p, OPCODE, insn); return npc; } reg_t rv64_NAME(processor_t* p, insn_t insn, reg_t pc) { int xlen = 64; reg_t npc = sext_xlen(pc + insn_length(OPCODE)); #include "insns/NAME.h" trace_opcode(p, OPCODE, insn); return npc; }

// See LICENSE for license details. #include "mmu.h" #include "mulhi.h" #include "softfloat.h" #include "internals.h" #include "specialize.h" #include "tracer.h" #include <assert.h>

// See LICENSE for license details. #include "decode.h" #include "disasm.h" #include "sim.h" #include "mmu.h" #include <sys/mman.h> #include <termios.h> #include <map> #include <iostream> #include <climits> #include <cinttypes> #include <assert.h> #include <stdlib.h> #include <unistd.h> #include <sstream> #include <string> #include <vector> #include <algorithm> #include <math.h> DECLARE_TRAP(-1, interactive) processor_t *sim_t::get_core(const std::string& i) { char *ptr; unsigned long p = strtoul(i.c_str(), &ptr, 10); if (*ptr || p >= procs.size()) throw trap_interactive(); return get_core(p); } static std::string readline(int fd) { struct termios tios; bool noncanonical = tcgetattr(fd, &tios) == 0 && (tios.c_lflag & ICANON) == 0; std::string s; for (char ch; read(fd, &ch, 1) == 1; ) { if (ch == '\x7f') { if (s.empty()) continue; s.erase(s.end()-1); if (noncanonical && write(fd, "\b \b", 3) != 3) ; // shut up gcc } else if (noncanonical && write(fd, &ch, 1) != 1) ; // shut up gcc if (ch == '\n') break; if (ch != '\x7f') s += ch; } return s; } void sim_t::interactive() { typedef void (sim_t::*interactive_func)(const std::string&, const std::vector<std::string>&); std::map<std::string,interactive_func> funcs; funcs["run"] = &sim_t::interactive_run_noisy; funcs["r"] = funcs["run"]; funcs["rs"] = &sim_t::interactive_run_silent; funcs["reg"] = &sim_t::interactive_reg; funcs["freg"] = &sim_t::interactive_freg; funcs["fregs"] = &sim_t::interactive_fregs; funcs["fregd"] = &sim_t::interactive_fregd; funcs["pc"] = &sim_t::interactive_pc; funcs["mem"] = &sim_t::interactive_mem; funcs["str"] = &sim_t::interactive_str; funcs["until"] = &sim_t::interactive_until_silent; funcs["untiln"] = &sim_t::interactive_until_noisy; funcs["while"] = &sim_t::interactive_until_silent; funcs["quit"] = &sim_t::interactive_quit; funcs["q"] = funcs["quit"]; funcs["help"] = &sim_t::interactive_help; funcs["h"] = funcs["help"]; while (!done()) { std::cerr << ": " << std::flush; std::string s = readline(2); std::stringstream ss(s); std::string cmd, tmp; std::vector<std::string> args; if (!(ss >> cmd)) { set_procs_debug(true); step(1); continue; } while (ss >> tmp) args.push_back(tmp); try { if(funcs.count(cmd)) (this->*funcs[cmd])(cmd, args); else fprintf(stderr, "Unknown command %s\n", cmd.c_str()); } catch(trap_t t) {} } ctrlc_pressed = false; } void sim_t::interactive_help(const std::string& cmd, const std::vector<std::string>& args) { std::cerr << "Interactive commands:\n" "reg <core> [reg] # Display [reg] (all if omitted) in <core>\n" "fregs <core> <reg> # Display single precision <reg> in <core>\n" "fregd <core> <reg> # Display double precision <reg> in <core>\n" "pc <core> # Show current PC in <core>\n" "mem <hex addr> # Show contents of physical memory\n" "str <hex addr> # Show NUL-terminated C string\n" "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n" "until pc <core> <val> # Stop when PC in <core> hits <val>\n" "untiln pc <core> <val> # Run noisy and stop when PC in <core> hits <val>\n" "until mem <addr> <val> # Stop when memory <addr> becomes <val>\n" "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n" "while pc <core> <val> # Run while PC in <core> is <val>\n" "while mem <addr> <val> # Run while memory <addr> is <val>\n" "run [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n" "r [count] Alias for run\n" "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n" "quit # End the simulation\n" "q Alias for quit\n" "help # This screen!\n" "h Alias for help\n" "Note: Hitting enter is the same as: run 1\n" << std::flush; } void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args) { interactive_run(cmd,args,true); } void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args) { interactive_run(cmd,args,false); } void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy) { size_t steps = args.size() ? atoll(args[0].c_str()) : -1; ctrlc_pressed = false; set_procs_debug(noisy); for (size_t i = 0; i < steps && !ctrlc_pressed && !done(); i++) step(1); } void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args) { exit(0); } reg_t sim_t::get_pc(const std::vector<std::string>& args) { if(args.size() != 1) throw trap_interactive(); processor_t *p = get_core(args[0]); return p->get_state()->pc; } void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args) { fprintf(stderr, "0x%016" PRIx64 "\n", get_pc(args)); } reg_t sim_t::get_reg(const std::vector<std::string>& args) { if(args.size() != 2) throw trap_interactive(); processor_t *p = get_core(args[0]); unsigned long r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name; if (r == NXPR) { char *ptr; r = strtoul(args[1].c_str(), &ptr, 10); if (*ptr) { #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number); #include "encoding.h" // generates if's for all csrs r = NXPR; // else case (csr name not found) #undef DECLARE_CSR } } if (r >= NXPR) throw trap_interactive(); return p->get_state()->XPR[r]; } freg_t sim_t::get_freg(const std::vector<std::string>& args) { if(args.size() != 2) throw trap_interactive(); processor_t *p = get_core(args[0]); int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name; if (r == NFPR) r = atoi(args[1].c_str()); if (r >= NFPR) throw trap_interactive(); return p->get_state()->FPR[r]; } void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { if (args.size() == 1) { // Show all the regs! processor_t *p = get_core(args[0]); for (int r = 0; r < NXPR; ++r) { fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->get_state()->XPR[r]); if ((r + 1) % 4 == 0) fprintf(stderr, "\n"); } } else fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args)); } union fpr { freg_t r; float s; double d; }; void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args) { freg_t r = get_freg(args); fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]); } void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args) { fpr f; f.r = get_freg(args); fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN); } void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args) { fpr f; f.r = get_freg(args); fprintf(stderr, "%g\n", isBoxedF64(f.r) ? f.d : NAN); } reg_t sim_t::get_mem(const std::vector<std::string>& args) { if(args.size() != 1 && args.size() != 2) throw trap_interactive(); std::string addr_str = args[0]; mmu_t* mmu = debug_mmu; if(args.size() == 2) { processor_t *p = get_core(args[0]); mmu = p->get_mmu(); addr_str = args[1]; } reg_t addr = strtol(addr_str.c_str(),NULL,16), val; if(addr == LONG_MAX) addr = strtoul(addr_str.c_str(),NULL,16); switch(addr % 8) { case 0: val = mmu->load_uint64(addr); break; case 4: val = mmu->load_uint32(addr); break; case 2: case 6: val = mmu->load_uint16(addr); break; default: val = mmu->load_uint8(addr); break; } return val; } void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args) { fprintf(stderr, "0x%016" PRIx64 "\n", get_mem(args)); } void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) { if(args.size() != 1) throw trap_interactive(); reg_t addr = strtol(args[0].c_str(),NULL,16); char ch; while((ch = debug_mmu->load_uint8(addr++))) putchar(ch); putchar('\n'); } void sim_t::interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args) { interactive_until(cmd, args, false); } void sim_t::interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args) { interactive_until(cmd, args, true); } void sim_t::interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy) { bool cmd_until = cmd == "until" || cmd == "untiln"; if(args.size() < 3) return; reg_t val = strtol(args[args.size()-1].c_str(),NULL,16); if(val == LONG_MAX) val = strtoul(args[args.size()-1].c_str(),NULL,16); std::vector<std::string> args2; args2 = std::vector<std::string>(args.begin()+1,args.end()-1); auto func = args[0] == "reg" ? &sim_t::get_reg : args[0] == "pc" ? &sim_t::get_pc : args[0] == "mem" ? &sim_t::get_mem : NULL; if (func == NULL) return; ctrlc_pressed = false; while (1) { try { reg_t current = (this->*func)(args2); if (cmd_until == (current == val)) break; if (ctrlc_pressed) break; } catch (trap_t t) {} set_procs_debug(noisy); step(1); } }

#include <stdio.h> #include "decode.h" #include "jtag_dtm.h" #include "debug_module.h" #include "debug_defines.h" #if 0 # define D(x) x #else # define D(x) #endif enum { IR_IDCODE=1, IR_DTMCONTROL=0x10, IR_DBUS=0x11, IR_RESET=0x1c }; #define DTMCONTROL_VERSION 0xf #define DTMCONTROL_ABITS (0x3f << 4) #define DTMCONTROL_DBUSSTAT (3<<10) #define DTMCONTROL_IDLE (7<<12) #define DTMCONTROL_DBUSRESET (1<<16) #define DMI_OP 3 #define DMI_DATA (0xffffffffL<<2) #define DMI_ADDRESS ((1L<<(abits+34)) - (1L<<34)) #define DMI_OP_STATUS_SUCCESS 0 #define DMI_OP_STATUS_RESERVED 1 #define DMI_OP_STATUS_FAILED 2 #define DMI_OP_STATUS_BUSY 3 #define DMI_OP_NOP 0 #define DMI_OP_READ 1 #define DMI_OP_WRITE 2 #define DMI_OP_RESERVED 3 jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) : dm(dm), _tck(false), _tms(false), _tdi(false), _tdo(false), dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) | 1), dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET), _state(TEST_LOGIC_RESET) { } void jtag_dtm_t::reset() { _state = TEST_LOGIC_RESET; } void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) { const jtag_state_t next[16][2] = { /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE, TEST_LOGIC_RESET }, /* RUN_TEST_IDLE */ { RUN_TEST_IDLE, SELECT_DR_SCAN }, /* SELECT_DR_SCAN */ { CAPTURE_DR, SELECT_IR_SCAN }, /* CAPTURE_DR */ { SHIFT_DR, EXIT1_DR }, /* SHIFT_DR */ { SHIFT_DR, EXIT1_DR }, /* EXIT1_DR */ { PAUSE_DR, UPDATE_DR }, /* PAUSE_DR */ { PAUSE_DR, EXIT2_DR }, /* EXIT2_DR */ { SHIFT_DR, UPDATE_DR }, /* UPDATE_DR */ { RUN_TEST_IDLE, SELECT_DR_SCAN }, /* SELECT_IR_SCAN */ { CAPTURE_IR, TEST_LOGIC_RESET }, /* CAPTURE_IR */ { SHIFT_IR, EXIT1_IR }, /* SHIFT_IR */ { SHIFT_IR, EXIT1_IR }, /* EXIT1_IR */ { PAUSE_IR, UPDATE_IR }, /* PAUSE_IR */ { PAUSE_IR, EXIT2_IR }, /* EXIT2_IR */ { SHIFT_IR, UPDATE_IR }, /* UPDATE_IR */ { RUN_TEST_IDLE, SELECT_DR_SCAN } }; if (!_tck && tck) { // Positive clock edge. switch (_state) { case SHIFT_DR: dr >>= 1; dr |= (uint64_t) _tdi << (dr_length-1); break; case SHIFT_IR: ir >>= 1; ir |= _tdi << (ir_length-1); break; default: break; } _state = next[_state][_tms]; switch (_state) { case TEST_LOGIC_RESET: ir = IR_IDCODE; break; case CAPTURE_DR: capture_dr(); break; case SHIFT_DR: _tdo = dr & 1; break; case UPDATE_DR: update_dr(); break; case CAPTURE_IR: break; case SHIFT_IR: _tdo = ir & 1; break; //case UPDATE_IR: //if (ir == IR_RESET) { // Make a reset happen //} //break; default: break; } } D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, " "dr=0x%lx\n", _state, _tdi, _tdo, _tms, _tck, ir, dr)); _tck = tck; _tms = tms; _tdi = tdi; } void jtag_dtm_t::capture_dr() { switch (ir) { case IR_IDCODE: dr = idcode; dr_length = 32; break; case IR_DTMCONTROL: dr = dtmcontrol; dr_length = 32; break; case IR_DBUS: dr = dmi; dr_length = abits + 34; break; default: D(fprintf(stderr, "Unsupported IR: 0x%x\n", ir)); break; } D(fprintf(stderr, "Capture DR; IR=0x%x, DR=0x%lx (%d bits)\n", ir, dr, dr_length)); } void jtag_dtm_t::update_dr() { D(fprintf(stderr, "Update DR; IR=0x%x, DR=0x%lx (%d bits)\n", ir, dr, dr_length)); switch (ir) { case IR_DBUS: { unsigned op = get_field(dr, DMI_OP); uint32_t data = get_field(dr, DMI_DATA); unsigned address = get_field(dr, DMI_ADDRESS); dmi = dr; bool success = true; if (op == DMI_OP_READ) { uint32_t value; if (dm->dmi_read(address, &value)) { dmi = set_field(dmi, DMI_DATA, value); } else { success = false; } } else if (op == DMI_OP_WRITE) { success = dm->dmi_write(address, data); } if (success) { dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_SUCCESS); } else { dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_FAILED); } D(fprintf(stderr, "dmi=0x%lx\n", dmi)); } break; } }

#ifndef JTAG_DTM_H #define JTAG_DTM_H #include <stdint.h> class debug_module_t; typedef enum { TEST_LOGIC_RESET, RUN_TEST_IDLE, SELECT_DR_SCAN, CAPTURE_DR, SHIFT_DR, EXIT1_DR, PAUSE_DR, EXIT2_DR, UPDATE_DR, SELECT_IR_SCAN, CAPTURE_IR, SHIFT_IR, EXIT1_IR, PAUSE_IR, EXIT2_IR, UPDATE_IR } jtag_state_t; class jtag_dtm_t { static const unsigned idcode = 0xdeadbeef; public: jtag_dtm_t(debug_module_t *dm); void reset(); void set_pins(bool tck, bool tms, bool tdi); bool tdo() const { return _tdo; } jtag_state_t state() const { return _state; } private: debug_module_t *dm; bool _tck, _tms, _tdi, _tdo; uint32_t ir; const unsigned ir_length = 5; uint64_t dr; unsigned dr_length; // abits must come before dtmcontrol so it can easily be used in the // constructor. const unsigned abits = 6; uint32_t dtmcontrol; uint64_t dmi; jtag_state_t _state; void capture_dr(); void update_dr(); }; #endif

// See LICENSE for license details. #ifndef _MEMTRACER_H #define _MEMTRACER_H #include <cstdint> #include <string.h> #include <vector> enum access_type { LOAD, STORE, FETCH, }; class memtracer_t { public: memtracer_t() {} virtual ~memtracer_t() {} virtual bool interested_in_range(uint64_t begin, uint64_t end, access_type type) = 0; virtual void trace(uint64_t addr, size_t bytes, access_type type) = 0; }; class memtracer_list_t : public memtracer_t { public: bool empty() { return list.empty(); } bool interested_in_range(uint64_t begin, uint64_t end, access_type type) { for (std::vector<memtracer_t*>::iterator it = list.begin(); it != list.end(); ++it) if ((*it)->interested_in_range(begin, end, type)) return true; return false; } void trace(uint64_t addr, size_t bytes, access_type type) { for (std::vector<memtracer_t*>::iterator it = list.begin(); it != list.end(); ++it) (*it)->trace(addr, bytes, type); } void hook(memtracer_t* h) { list.push_back(h); } private: std::vector<memtracer_t*> list; }; #endif

// See LICENSE for license details. #include "mmu.h" #include "simif.h" #include "processor.h" mmu_t::mmu_t(simif_t* sim, processor_t* proc) : sim(sim), proc(proc), check_triggers_fetch(false), check_triggers_load(false), check_triggers_store(false), matched_trigger(NULL) { flush_tlb(); yield_load_reservation(); } mmu_t::~mmu_t() { } void mmu_t::flush_icache() { for (size_t i = 0; i < ICACHE_ENTRIES; i++) icache[i].tag = -1; } void mmu_t::flush_tlb() { memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag)); memset(tlb_load_tag, -1, sizeof(tlb_load_tag)); memset(tlb_store_tag, -1, sizeof(tlb_store_tag)); flush_icache(); } static void throw_access_exception(reg_t addr, access_type type) { switch (type) { case FETCH: throw trap_instruction_access_fault(addr); case LOAD: throw trap_load_access_fault(addr); case STORE: throw trap_store_access_fault(addr); default: abort(); } } reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type) { if (!proc) return addr; reg_t mode = proc->state.prv; if (type != FETCH) { if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV)) mode = get_field(proc->state.mstatus, MSTATUS_MPP); } reg_t paddr = walk(addr, type, mode) | (addr & (PGSIZE-1)); if (!pmp_ok(paddr, type, mode) || !pmp_homogeneous(paddr, len)) throw_access_exception(addr, type); return paddr; } tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr) { reg_t paddr = translate(vaddr, sizeof(fetch_temp), FETCH); if (auto host_addr = sim->addr_to_mem(paddr)) { return refill_tlb(vaddr, paddr, host_addr, FETCH); } else { if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp)) throw trap_instruction_access_fault(vaddr); tlb_entry_t entry = {(char*)&fetch_temp - vaddr, paddr - vaddr}; return entry; } } reg_t reg_from_bytes(size_t len, const uint8_t* bytes) { switch (len) { case 1: return bytes[0]; case 2: return bytes[0] | (((reg_t) bytes[1]) << 8); case 4: return bytes[0] | (((reg_t) bytes[1]) << 8) | (((reg_t) bytes[2]) << 16) | (((reg_t) bytes[3]) << 24); case 8: return bytes[0] | (((reg_t) bytes[1]) << 8) | (((reg_t) bytes[2]) << 16) | (((reg_t) bytes[3]) << 24) | (((reg_t) bytes[4]) << 32) | (((reg_t) bytes[5]) << 40) | (((reg_t) bytes[6]) << 48) | (((reg_t) bytes[7]) << 56); } abort(); } void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes) { reg_t paddr = translate(addr, len, LOAD); if (auto host_addr = sim->addr_to_mem(paddr)) { memcpy(bytes, host_addr, len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.trace(paddr, len, LOAD); else refill_tlb(addr, paddr, host_addr, LOAD); } else if (!sim->mmio_load(paddr, len, bytes)) { throw trap_load_access_fault(addr); } if (!matched_trigger) { reg_t data = reg_from_bytes(len, bytes); matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); if (matched_trigger) throw *matched_trigger; } } void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes) { reg_t paddr = translate(addr, len, STORE); if (!matched_trigger) { reg_t data = reg_from_bytes(len, bytes); matched_trigger = trigger_exception(OPERATION_STORE, addr, data); if (matched_trigger) throw *matched_trigger; } if (auto host_addr = sim->addr_to_mem(paddr)) { memcpy(host_addr, bytes, len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE)) tracer.trace(paddr, len, STORE); else refill_tlb(addr, paddr, host_addr, STORE); } else if (!sim->mmio_store(paddr, len, bytes)) { throw trap_store_access_fault(addr); } } tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_type type) { reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES; reg_t expected_tag = vaddr >> PGSHIFT; if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_load_tag[idx] = -1; if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_store_tag[idx] = -1; if ((tlb_insn_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_insn_tag[idx] = -1; if ((check_triggers_fetch && type == FETCH) || (check_triggers_load && type == LOAD) || (check_triggers_store && type == STORE)) expected_tag |= TLB_CHECK_TRIGGERS; if (pmp_homogeneous(paddr & ~reg_t(PGSIZE - 1), PGSIZE)) { if (type == FETCH) tlb_insn_tag[idx] = expected_tag; else if (type == STORE) tlb_store_tag[idx] = expected_tag; else tlb_load_tag[idx] = expected_tag; } tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; tlb_data[idx] = entry; return entry; } reg_t mmu_t::pmp_ok(reg_t addr, access_type type, reg_t mode) { if (!proc) return true; reg_t base = 0; for (size_t i = 0; i < proc->state.n_pmp; i++) { reg_t tor = proc->state.pmpaddr[i] << PMP_SHIFT; uint8_t cfg = proc->state.pmpcfg[i]; if (cfg & PMP_A) { bool is_tor = (cfg & PMP_A) == PMP_TOR; bool is_na4 = (cfg & PMP_A) == PMP_NA4; reg_t mask = (proc->state.pmpaddr[i] << 1) | (!is_na4); mask = ~(mask & ~(mask + 1)) << PMP_SHIFT; bool napot_match = ((addr ^ tor) & mask) == 0; bool tor_match = base <= addr && addr < tor; if (is_tor ? tor_match : napot_match) { return (mode == PRV_M && !(cfg & PMP_L)) || (type == LOAD && (cfg & PMP_R)) || (type == STORE && (cfg & PMP_W)) || (type == FETCH && (cfg & PMP_X)); } } base = tor; } return mode == PRV_M; } reg_t mmu_t::pmp_homogeneous(reg_t addr, reg_t len) { if ((addr | len) & (len - 1)) abort(); if (!proc) return true; reg_t base = 0; for (size_t i = 0; i < proc->state.n_pmp; i++) { reg_t tor = proc->state.pmpaddr[i] << PMP_SHIFT; uint8_t cfg = proc->state.pmpcfg[i]; if (cfg & PMP_A) { bool is_tor = (cfg & PMP_A) == PMP_TOR; bool is_na4 = (cfg & PMP_A) == PMP_NA4; bool begins_after_lower = addr >= base; bool begins_after_upper = addr >= tor; bool ends_before_lower = (addr & -len) < (base & -len); bool ends_before_upper = (addr & -len) < (tor & -len); bool tor_homogeneous = ends_before_lower || begins_after_upper || (begins_after_lower && ends_before_upper); reg_t mask = (proc->state.pmpaddr[i] << 1) | (!is_na4); mask = ~(mask & ~(mask + 1)) << PMP_SHIFT; bool mask_homogeneous = ~(mask << 1) & len; bool napot_homogeneous = mask_homogeneous || ((addr ^ tor) / len) != 0; if (!(is_tor ? tor_homogeneous : napot_homogeneous)) return false; } base = tor; } return true; } reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) { vm_info vm = decode_vm_info(proc->max_xlen, mode, proc->get_state()->satp); if (vm.levels == 0) return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen bool s_mode = mode == PRV_S; bool sum = get_field(proc->state.mstatus, MSTATUS_SUM); bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR); // verify bits xlen-1:va_bits-1 are all equal int va_bits = PGSHIFT + vm.levels * vm.idxbits; reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1; reg_t masked_msbs = (addr >> (va_bits-1)) & mask; if (masked_msbs != 0 && masked_msbs != mask) vm.levels = 0; reg_t base = vm.ptbase; for (int i = vm.levels - 1; i >= 0; i--) { int ptshift = i * vm.idxbits; reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << vm.idxbits) - 1); // check that physical address of PTE is legal auto pte_paddr = base + idx * vm.ptesize; auto ppte = sim->addr_to_mem(pte_paddr); if (!ppte || !pmp_ok(pte_paddr, LOAD, PRV_S)) throw_access_exception(addr, type); reg_t pte = vm.ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte; reg_t ppn = pte >> PTE_PPN_SHIFT; if (PTE_TABLE(pte)) { // next level of page table base = ppn << PGSHIFT; } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) { break; } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { break; } else if (type == FETCH ? !(pte & PTE_X) : type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_W))) { break; } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { break; } else { reg_t ad = PTE_A | ((type == STORE) * PTE_D); #ifdef RISCV_ENABLE_DIRTY // set accessed and possibly dirty bits. if ((pte & ad) != ad) { if (!pmp_ok(pte_paddr, STORE, PRV_S)) throw_access_exception(addr, type); *(uint32_t*)ppte |= ad; } #else // take exception if access or possibly dirty bit is not set. if ((pte & ad) != ad) break; #endif // for superpage mappings, make a fake leaf PTE for the TLB's benefit. reg_t vpn = addr >> PGSHIFT; reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT; return value; } } switch (type) { case FETCH: throw trap_instruction_page_fault(addr); case LOAD: throw trap_load_page_fault(addr); case STORE: throw trap_store_page_fault(addr); default: abort(); } } void mmu_t::register_memtracer(memtracer_t* t) { flush_tlb(); tracer.hook(t); }

// See LICENSE for license details. #ifndef _RISCV_MMU_H #define _RISCV_MMU_H #include "decode.h" #include "trap.h" #include "common.h" #include "config.h" #include "simif.h" #include "processor.h" #include "memtracer.h" #include <stdlib.h> #include <vector> // virtual memory configuration #define PGSHIFT 12 const reg_t PGSIZE = 1 << PGSHIFT; const reg_t PGMASK = ~(PGSIZE-1); struct insn_fetch_t { insn_func_t func; insn_t insn; }; struct icache_entry_t { reg_t tag; struct icache_entry_t* next; insn_fetch_t data; }; struct tlb_entry_t { char* host_offset; reg_t target_offset; }; class trigger_matched_t { public: trigger_matched_t(int index, trigger_operation_t operation, reg_t address, reg_t data) : index(index), operation(operation), address(address), data(data) {} int index; trigger_operation_t operation; reg_t address; reg_t data; }; // this class implements a processor's port into the virtual memory system. // an MMU and instruction cache are maintained for simulator performance. class mmu_t { public: mmu_t(simif_t* sim, processor_t* proc); ~mmu_t(); inline reg_t misaligned_load(reg_t addr, size_t size) { #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; for (size_t i = 0; i < size; i++) res += (reg_t)load_uint8(addr + i) << (i * 8); return res; #else throw trap_load_address_misaligned(addr); #endif } inline void misaligned_store(reg_t addr, reg_t data, size_t size) { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) store_uint8(addr + i, data >> (i * 8)); #else throw trap_store_address_misaligned(addr); #endif } // template for functions that load an aligned value from memory #define load_func(type) \ inline type##_t load_##type(reg_t addr) { \ if (unlikely(addr & (sizeof(type##_t)-1))) \ return misaligned_load(addr, sizeof(type##_t)); \ reg_t vpn = addr >> PGSHIFT; \ if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) \ return *(type##_t*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); \ if (unlikely(tlb_load_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { \ type##_t data = *(type##_t*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); \ if (!matched_trigger) { \ matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); \ if (matched_trigger) \ throw *matched_trigger; \ } \ return data; \ } \ type##_t res; \ load_slow_path(addr, sizeof(type##_t), (uint8_t*)&res); \ return res; \ } // load value from memory at aligned address; zero extend to register width load_func(uint8) load_func(uint16) load_func(uint32) load_func(uint64) // load value from memory at aligned address; sign extend to register width load_func(int8) load_func(int16) load_func(int32) load_func(int64) // template for functions that store an aligned value to memory #define store_func(type) \ void store_##type(reg_t addr, type##_t val) { \ if (unlikely(addr & (sizeof(type##_t)-1))) \ return misaligned_store(addr, val, sizeof(type##_t)); \ reg_t vpn = addr >> PGSHIFT; \ if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \ *(type##_t*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr) = val; \ else if (unlikely(tlb_store_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { \ if (!matched_trigger) { \ matched_trigger = trigger_exception(OPERATION_STORE, addr, val); \ if (matched_trigger) \ throw *matched_trigger; \ } \ *(type##_t*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr) = val; \ } \ else \ store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \ } // template for functions that perform an atomic memory operation #define amo_func(type) \ template<typename op> \ type##_t amo_##type(reg_t addr, op f) { \ if (addr & (sizeof(type##_t)-1)) \ throw trap_store_address_misaligned(addr); \ try { \ auto lhs = load_##type(addr); \ store_##type(addr, f(lhs)); \ return lhs; \ } catch (trap_load_page_fault& t) { \ /* AMO faults should be reported as store faults */ \ throw trap_store_page_fault(t.get_tval()); \ } catch (trap_load_access_fault& t) { \ /* AMO faults should be reported as store faults */ \ throw trap_store_access_fault(t.get_tval()); \ } \ } void store_float128(reg_t addr, float128_t val) { #ifndef RISCV_ENABLE_MISALIGNED if (unlikely(addr & (sizeof(float128_t)-1))) throw trap_store_address_misaligned(addr); #endif store_uint64(addr, val.v[0]); store_uint64(addr + 8, val.v[1]); } float128_t load_float128(reg_t addr) { #ifndef RISCV_ENABLE_MISALIGNED if (unlikely(addr & (sizeof(float128_t)-1))) throw trap_load_address_misaligned(addr); #endif return (float128_t){load_uint64(addr), load_uint64(addr + 8)}; } // store value to memory at aligned address store_func(uint8) store_func(uint16) store_func(uint32) store_func(uint64) // perform an atomic memory operation at an aligned address amo_func(uint32) amo_func(uint64) inline void yield_load_reservation() { load_reservation_address = (reg_t)-1; } inline void acquire_load_reservation(reg_t vaddr) { reg_t paddr = translate(vaddr, 1, LOAD); if (auto host_addr = sim->addr_to_mem(paddr)) load_reservation_address = refill_tlb(vaddr, paddr, host_addr, LOAD).target_offset + vaddr; else throw trap_load_access_fault(vaddr); // disallow LR to I/O space } inline bool check_load_reservation(reg_t vaddr) { reg_t paddr = translate(vaddr, 1, STORE); if (auto host_addr = sim->addr_to_mem(paddr)) return load_reservation_address == refill_tlb(vaddr, paddr, host_addr, STORE).target_offset + vaddr; else throw trap_store_access_fault(vaddr); // disallow SC to I/O space } static const reg_t ICACHE_ENTRIES = 1024; inline size_t icache_index(reg_t addr) { return (addr / PC_ALIGN) % ICACHE_ENTRIES; } inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry) { auto tlb_entry = translate_insn_addr(addr); insn_bits_t insn = *(uint16_t*)(tlb_entry.host_offset + addr); int length = insn_length(insn); if (likely(length == 4)) { insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr_to_host(addr + 2) << 16; } else if (length == 2) { insn = (int16_t)insn; } else if (length == 6) { insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr_to_host(addr + 4) << 32; insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr_to_host(addr + 2) << 16; } else { static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t"); insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr_to_host(addr + 6) << 48; insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr_to_host(addr + 4) << 32; insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr_to_host(addr + 2) << 16; } insn_fetch_t fetch = {proc->decode_insn(insn), insn}; entry->tag = addr; entry->next = &icache[icache_index(addr + length)]; entry->data = fetch; reg_t paddr = tlb_entry.target_offset + addr;; if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) { entry->tag = -1; tracer.trace(paddr, length, FETCH); } return entry; } inline icache_entry_t* access_icache(reg_t addr) { icache_entry_t* entry = &icache[icache_index(addr)]; if (likely(entry->tag == addr)) return entry; return refill_icache(addr, entry); } inline insn_fetch_t load_insn(reg_t addr) { icache_entry_t entry; return refill_icache(addr, &entry)->data; } void flush_tlb(); void flush_icache(); void register_memtracer(memtracer_t*); int is_dirty_enabled() { #ifdef RISCV_ENABLE_DIRTY return 1; #else return 0; #endif } int is_misaligned_enabled() { #ifdef RISCV_ENABLE_MISALIGNED return 1; #else return 0; #endif } private: simif_t* sim; processor_t* proc; memtracer_list_t tracer; reg_t load_reservation_address; uint16_t fetch_temp; // implement an instruction cache for simulator performance icache_entry_t icache[ICACHE_ENTRIES]; // implement a TLB for simulator performance static const reg_t TLB_ENTRIES = 256; // If a TLB tag has TLB_CHECK_TRIGGERS set, then the MMU must check for a // trigger match before completing an access. static const reg_t TLB_CHECK_TRIGGERS = reg_t(1) << 63; tlb_entry_t tlb_data[TLB_ENTRIES]; reg_t tlb_insn_tag[TLB_ENTRIES]; reg_t tlb_load_tag[TLB_ENTRIES]; reg_t tlb_store_tag[TLB_ENTRIES]; // finish translation on a TLB miss and update the TLB tlb_entry_t refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_type type); const char* fill_from_mmio(reg_t vaddr, reg_t paddr); // perform a page table walk for a given VA; set referenced/dirty bits reg_t walk(reg_t addr, access_type type, reg_t prv); // handle uncommon cases: TLB misses, page faults, MMIO tlb_entry_t fetch_slow_path(reg_t addr); void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes); void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes); reg_t translate(reg_t addr, reg_t len, access_type type); // ITLB lookup inline tlb_entry_t translate_insn_addr(reg_t addr) { reg_t vpn = addr >> PGSHIFT; if (likely(tlb_insn_tag[vpn % TLB_ENTRIES] == vpn)) return tlb_data[vpn % TLB_ENTRIES]; tlb_entry_t result; if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] != (vpn | TLB_CHECK_TRIGGERS))) { result = fetch_slow_path(addr); } else { result = tlb_data[vpn % TLB_ENTRIES]; } if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { uint16_t* ptr = (uint16_t*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); int match = proc->trigger_match(OPERATION_EXECUTE, addr, *ptr); if (match >= 0) { throw trigger_matched_t(match, OPERATION_EXECUTE, addr, *ptr); } } return result; } inline const uint16_t* translate_insn_addr_to_host(reg_t addr) { return (uint16_t*)(translate_insn_addr(addr).host_offset + addr); } inline trigger_matched_t *trigger_exception(trigger_operation_t operation, reg_t address, reg_t data) { if (!proc) { return NULL; } int match = proc->trigger_match(operation, address, data); if (match == -1) return NULL; if (proc->state.mcontrol[match].timing == 0) { throw trigger_matched_t(match, operation, address, data); } return new trigger_matched_t(match, operation, address, data); } reg_t pmp_homogeneous(reg_t addr, reg_t len); reg_t pmp_ok(reg_t addr, access_type type, reg_t mode); bool check_triggers_fetch; bool check_triggers_load; bool check_triggers_store; // The exception describing a matched trigger, or NULL. trigger_matched_t *matched_trigger; friend class processor_t; }; struct vm_info { int levels; int idxbits; int ptesize; reg_t ptbase; }; inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t satp) { if (prv == PRV_M) { return {0, 0, 0, 0}; } else if (prv <= PRV_S && xlen == 32) { switch (get_field(satp, SATP32_MODE)) { case SATP_MODE_OFF: return {0, 0, 0, 0}; case SATP_MODE_SV32: return {2, 10, 4, (satp & SATP32_PPN) << PGSHIFT}; default: abort(); } } else if (prv <= PRV_S && xlen == 64) { switch (get_field(satp, SATP64_MODE)) { case SATP_MODE_OFF: return {0, 0, 0, 0}; case SATP_MODE_SV39: return {3, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; case SATP_MODE_SV48: return {4, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; case SATP_MODE_SV57: return {5, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; case SATP_MODE_SV64: return {6, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; default: abort(); } } else { abort(); } } #endif

// See LICENSE for license details. #ifndef _RISCV_MULHI_H #define _RISCV_MULHI_H #include <cstdint> inline uint64_t mulhu(uint64_t a, uint64_t b) { uint64_t t; uint32_t y1, y2, y3; uint64_t a0 = (uint32_t)a, a1 = a >> 32; uint64_t b0 = (uint32_t)b, b1 = b >> 32; t = a1*b0 + ((a0*b0) >> 32); y1 = t; y2 = t >> 32; t = a0*b1 + y1; y1 = t; t = a1*b1 + y2 + (t >> 32); y2 = t; y3 = t >> 32; return ((uint64_t)y3 << 32) | y2; } inline int64_t mulh(int64_t a, int64_t b) { int negate = (a < 0) != (b < 0); uint64_t res = mulhu(a < 0 ? -a : a, b < 0 ? -b : b); return negate ? ~res + (a * b == 0) : res; } inline int64_t mulhsu(int64_t a, uint64_t b) { int negate = a < 0; uint64_t res = mulhu(a < 0 ? -a : a, b); return negate ? ~res + (a * b == 0) : res; } #endif

#include "encoding.h" #define ZERO 0 #define T0 5 #define S0 8 #define S1 9 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) { return (value >> lo) & ((1 << (hi+1-lo)) - 1); } static uint32_t bit(uint32_t value, unsigned int b) { return (value >> b) & 1; } static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__ ((unused)); static uint32_t jal(unsigned int rd, uint32_t imm) { return (bit(imm, 20) << 31) | (bits(imm, 10, 1) << 21) | (bit(imm, 11) << 20) | (bits(imm, 19, 12) << 12) | (rd << 7) | MATCH_JAL; } static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__ ((unused)); static uint32_t csrsi(unsigned int csr, uint16_t imm) { return (csr << 20) | (bits(imm, 4, 0) << 15) | MATCH_CSRRSI; } static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (src << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_SW; } static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (src << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_SD; } static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (src << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_SH; } static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (src << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_SB; } static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) | (base << 15) | (bits(rd, 4, 0) << 7) | MATCH_LD; } static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) | (base << 15) | (bits(rd, 4, 0) << 7) | MATCH_LW; } static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) | (base << 15) | (bits(rd, 4, 0) << 7) | MATCH_LH; } static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) | (base << 15) | (bits(rd, 4, 0) << 7) | MATCH_LB; } static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__ ((unused)); static uint32_t csrw(unsigned int source, unsigned int csr) { return (csr << 20) | (source << 15) | MATCH_CSRRW; } static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) { return (bits(imm, 11, 0) << 20) | (src << 15) | (dest << 7) | MATCH_ADDI; } static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__ ((unused)); static uint32_t csrr(unsigned int rd, unsigned int csr) { return (csr << 20) | (rd << 7) | MATCH_CSRRS; } static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (bits(src, 4, 0) << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_FSW; } static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (bits(src, 4, 0) << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_FSD; } static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) | (base << 15) | (bits(dest, 4, 0) << 7) | MATCH_FLW; } static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) { return (bits(offset, 11, 0) << 20) | (base << 15) | (bits(dest, 4, 0) << 7) | MATCH_FLD; } static uint32_t ebreak(void) __attribute__ ((unused)); static uint32_t ebreak(void) { return MATCH_EBREAK; } static uint32_t ebreak_c(void) __attribute__ ((unused)); static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; } static uint32_t dret(void) __attribute__ ((unused)); static uint32_t dret(void) { return MATCH_DRET; } static uint32_t fence_i(void) __attribute__ ((unused)); static uint32_t fence_i(void) { return MATCH_FENCE_I; } /* static uint32_t lui(unsigned int dest, uint32_t imm) __attribute__ ((unused)); static uint32_t lui(unsigned int dest, uint32_t imm) { return (bits(imm, 19, 0) << 12) | (dest << 7) | MATCH_LUI; } static uint32_t csrci(unsigned int csr, uint16_t imm) __attribute__ ((unused)); static uint32_t csrci(unsigned int csr, uint16_t imm) { return (csr << 20) | (bits(imm, 4, 0) << 15) | MATCH_CSRRCI; } static uint32_t li(unsigned int dest, uint16_t imm) __attribute__ ((unused)); static uint32_t li(unsigned int dest, uint16_t imm) { return addi(dest, 0, imm); } static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | (bits(src, 4, 0) << 20) | (base << 15) | (bits(offset, 4, 0) << 7) | MATCH_FSD; } static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm) { return (bits(imm, 11, 0) << 20) | (src << 15) | (dest << 7) | MATCH_ORI; } static uint32_t nop(void) __attribute__ ((unused)); static uint32_t nop(void) { return addi(0, 0, 0); } */ static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) { return (bits(imm, 11, 0) << 20) | (src << 15) | (dest << 7) | MATCH_XORI; } static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__ ((unused)); static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) { return (bits(shamt, 4, 0) << 20) | (src << 15) | (dest << 7) | MATCH_SRLI; }

// See LICENSE for license details. #include "processor.h" #include "extension.h" #include "common.h" #include "config.h" #include "simif.h" #include "mmu.h" #include "disasm.h" #include <cinttypes> #include <cmath> #include <cstdlib> #include <iostream> #include <assert.h> #include <limits.h> #include <stdexcept> #include <algorithm> #undef STATE #define STATE state processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset) : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset), last_pc(1), executions(1) { parse_isa_string(isa); register_base_instructions(); mmu = new mmu_t(sim, this); disassembler = new disassembler_t(max_xlen); if (ext) for (auto disasm_insn : ext->get_disasms()) disassembler->add_insn(disasm_insn); reset(); } processor_t::~processor_t() { #ifdef RISCV_ENABLE_HISTOGRAM if (histogram_enabled) { fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size()); for (auto it : pc_histogram) fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second); } #endif delete mmu; delete disassembler; } static void bad_isa_string(const char* isa) { fprintf(stderr, "error: bad --isa option %s\n", isa); abort(); } void processor_t::parse_isa_string(const char* str) { std::string lowercase, tmp; for (const char *r = str; *r; r++) lowercase += std::tolower(*r); const char* p = lowercase.c_str(); const char* all_subsets = "imafdqc"; max_xlen = 64; state.misa = reg_t(2) << 62; if (strncmp(p, "rv32", 4) == 0) max_xlen = 32, state.misa = reg_t(1) << 30, p += 4; else if (strncmp(p, "rv64", 4) == 0) p += 4; else if (strncmp(p, "rv", 2) == 0) p += 2; if (!*p) { p = "imafdc"; } else if (*p == 'g') { // treat "G" as "IMAFD" tmp = std::string("imafd") + (p+1); p = &tmp[0]; } else if (*p != 'i') { bad_isa_string(str); } isa_string = "rv" + std::to_string(max_xlen) + p; state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode state.misa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { state.misa |= 1L << (*p - 'a'); if (auto next = strchr(all_subsets, *p)) { all_subsets = next + 1; p++; } else if (*p == 'x') { const char* ext = p+1, *end = ext; while (islower(*end)) end++; register_extension(find_extension(std::string(ext, end - ext).c_str())()); p = end; } else { bad_isa_string(str); } } if (supports_extension('D') && !supports_extension('F')) bad_isa_string(str); if (supports_extension('Q') && !supports_extension('D')) bad_isa_string(str); if (supports_extension('Q') && max_xlen < 64) bad_isa_string(str); max_isa = state.misa; } void state_t::reset(reg_t max_isa) { memset(this, 0, sizeof(*this)); misa = max_isa; prv = PRV_M; mstatus = 0; pc = DEFAULT_RSTVEC; tselect = 0; for (unsigned int i = 0; i < num_triggers; i++) mcontrol[i].type = 2; pmpcfg[0] = PMP_R | PMP_W | PMP_X | PMP_NAPOT; pmpaddr[0] = ~reg_t(0); } void processor_t::set_debug(bool value) { debug = value; if (ext) ext->set_debug(value); } void processor_t::set_histogram(bool value) { histogram_enabled = value; #ifndef RISCV_ENABLE_HISTOGRAM if (value) { fprintf(stderr, "PC Histogram support has not been properly enabled;"); fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n"); } #endif } void processor_t::reset() { state.reset(max_isa); state.dcsr.halt = halt_on_reset; halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); if (ext) ext->reset(); // reset the extension if (sim) sim->proc_reset(id); } // Count number of contiguous 0 bits starting from the LSB. static int ctz(reg_t val) { int res = 0; if (val) while ((val & 1) == 0) val >>= 1, res++; return res; } void processor_t::take_interrupt(reg_t pending_interrupts) { reg_t mie = get_field(state.mstatus, MSTATUS_MIE); reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie); reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled; reg_t sie = get_field(state.mstatus, MSTATUS_SIE); reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); // M-ints have highest priority; consider S-ints only if no M-ints pending if (enabled_interrupts == 0) enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; if (state.dcsr.cause == 0 && enabled_interrupts) { // nonstandard interrupts have highest priority if (enabled_interrupts >> IRQ_M_EXT) enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT; // external interrupts have next-highest priority else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP)) enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP); // software interrupts have next-highest priority else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP)) enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP); // timer interrupts have next-highest priority else if (enabled_interrupts & (MIP_MTIP | MIP_STIP)) enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP); else abort(); throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts)); } } static int xlen_to_uxl(int xlen) { if (xlen == 32) return 1; if (xlen == 64) return 2; abort(); } reg_t processor_t::legalize_privilege(reg_t prv) { assert(prv <= PRV_M); if (!supports_extension('U')) return PRV_M; if (prv == PRV_H || !supports_extension('S')) return PRV_U; return prv; } void processor_t::set_privilege(reg_t prv) { // mmu->flush_tlb(); state.prv = legalize_privilege(prv); } void processor_t::enter_debug_mode(uint8_t cause) { state.dcsr.cause = cause; state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; state.pc = DEBUG_ROM_ENTRY; } void processor_t::take_trap(trap_t& t, reg_t epc) { if (debug) { fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); if (t.has_tval()) fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id, t.get_tval()); } if (state.dcsr.cause) { if (t.cause() == CAUSE_BREAKPOINT) { state.pc = DEBUG_ROM_ENTRY; } else { state.pc = DEBUG_ROM_TVEC; } return; } if (t.cause() == CAUSE_BREAKPOINT && ( (state.prv == PRV_M && state.dcsr.ebreakm) || (state.prv == PRV_S && state.dcsr.ebreaks) || (state.prv == PRV_U && state.dcsr.ebreaku))) { enter_debug_mode(DCSR_CAUSE_SWBP); return; } // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0; if (interrupt) deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1)); if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) { // handle the trap in S-mode state.pc = state.stvec; state.scause = t.cause(); state.sepc = epc; state.stval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, state.prv); s = set_field(s, MSTATUS_SIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_S); } else { reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0; state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; state.mcause = t.cause(); state.mtval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, state.prv); s = set_field(s, MSTATUS_MIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_M); } } void processor_t::disasm(insn_t insn) { uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); if (last_pc != state.pc || last_bits != bits) { if (executions != 1) { fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions); } fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", id, state.pc, bits, disassembler->disassemble(insn).c_str()); last_pc = state.pc; last_bits = bits; executions = 1; } else { executions++; } } int processor_t::paddr_bits() { assert(xlen == max_xlen); return max_xlen == 64 ? 50 : 34; } void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | ((ext != NULL) << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; // if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.n_pmp) { // size_t i = which - CSR_PMPADDR0; // bool locked = state.pmpcfg[i] & PMP_L; // bool next_locked = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_L); // bool next_tor = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_A) == PMP_TOR; // if (!locked && !(next_locked && next_tor)) // state.pmpaddr[i] = val; // // mmu->flush_tlb(); // } // if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.n_pmp / 4) { // for (size_t i0 = (which - CSR_PMPCFG0) * 4, i = i0; i < i0 + xlen / 8; i++) { // if (!(state.pmpcfg[i] & PMP_L)) // state.pmpcfg[i] = (val >> (8 * (i - i0))) & (PMP_R | PMP_W | PMP_X | PMP_A | PMP_L); // } // // mmu->flush_tlb(); // } switch (which) { case CSR_FFLAGS: dirty_fp_state; state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT); break; case CSR_FRM: dirty_fp_state; state.frm = val & (FSR_RD >> FSR_RD_SHIFT); break; case CSR_FCSR: dirty_fp_state; state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT; state.frm = (val & FSR_RD) >> FSR_RD_SHIFT; break; case CSR_MSTATUS: { // if ((val ^ state.mstatus) & // (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR)) // mmu->flush_tlb(); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL | (ext ? MSTATUS_XS : 0); reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP)); state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp); if (supports_extension('S')) mask |= MSTATUS_SPP; state.mstatus = (state.mstatus & ~mask) | (val & mask); bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS; dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS; dirty = 0; if (max_xlen == 32) state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty); else state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty); state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen)); // U-XLEN == S-XLEN == M-XLEN xlen = max_xlen; break; } case CSR_MIP: { reg_t mask = MIP_SSIP | MIP_STIP; state.mip = (state.mip & ~mask) | (val & mask); break; } case CSR_MIE: state.mie = (state.mie & ~all_ints) | (val & all_ints); break; case CSR_MIDELEG: state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints); break; case CSR_MEDELEG: { reg_t mask = (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_BREAKPOINT) | (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) | (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT); state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } case CSR_MINSTRET: case CSR_MCYCLE: if (xlen == 32) state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU); else state.minstret = val; // The ISA mandates that if an instruction writes instret, the write // takes precedence over the increment to instret. However, Spike // unconditionally increments instret after executing an instruction. // Correct for this artifact by decrementing instret here. state.minstret--; break; case CSR_MINSTRETH: case CSR_MCYCLEH: state.minstret = (val << 32) | (state.minstret << 32 >> 32); state.minstret--; // See comment above. break; case CSR_SCOUNTEREN: state.scounteren = val; break; case CSR_MCOUNTEREN: state.mcounteren = val; break; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } case CSR_SIP: { reg_t mask = MIP_SSIP & state.mideleg; return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); } case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); case CSR_SATP: { mmu->flush_tlb(); if (max_xlen == 32) state.satp = val & (SATP32_PPN | SATP32_MODE); if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF || get_field(val, SATP64_MODE) == SATP_MODE_SV39 || get_field(val, SATP64_MODE) == SATP_MODE_SV48)) state.satp = val & (SATP64_PPN | SATP64_MODE); break; } case CSR_SEPC: state.sepc = val & ~(reg_t)1; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; case CSR_STVAL: state.stval = val; break; case CSR_MEPC: state.mepc = val & ~(reg_t)1; break; case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MTVAL: state.mtval = val; break; case CSR_MISA: { // the write is ignored if increasing IALIGN would misalign the PC if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2)) break; if (!(val & (1L << ('F' - 'A')))) val &= ~(1L << ('D' - 'A')); // allow MAFDC bits in MISA to be modified reg_t mask = 0; mask |= 1L << ('M' - 'A'); mask |= 1L << ('A' - 'A'); mask |= 1L << ('F' - 'A'); mask |= 1L << ('D' - 'A'); mask |= 1L << ('C' - 'A'); mask &= max_isa; state.misa = (val & mask) | (state.misa & ~mask); break; } case CSR_TSELECT: if (val < state.num_triggers) { state.tselect = val; } break; case CSR_TDATA1: { mcontrol_t *mc = &state.mcontrol[state.tselect]; if (mc->dmode && !state.dcsr.cause) { break; } mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); mc->select = get_field(val, MCONTROL_SELECT); mc->timing = get_field(val, MCONTROL_TIMING); mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); mc->chain = get_field(val, MCONTROL_CHAIN); mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH); mc->m = get_field(val, MCONTROL_M); mc->h = get_field(val, MCONTROL_H); mc->s = get_field(val, MCONTROL_S); mc->u = get_field(val, MCONTROL_U); mc->execute = get_field(val, MCONTROL_EXECUTE); mc->store = get_field(val, MCONTROL_STORE); mc->load = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. if (mc->execute) mc->timing = 0; trigger_updated(); } break; case CSR_TDATA2: if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) { break; } if (state.tselect < state.num_triggers) { state.tdata2[state.tselect] = val; } break; case CSR_DCSR: state.dcsr.prv = get_field(val, DCSR_PRV); state.dcsr.step = get_field(val, DCSR_STEP); // TODO: ndreset and fullreset state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM); state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH); state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS); state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU); state.dcsr.halt = get_field(val, DCSR_HALT); break; case CSR_DPC: state.dpc = val & ~(reg_t)1; break; case CSR_DSCRATCH: state.dscratch = val; break; } } // Note that get_csr is sometimes called when read side-effects should not // be actioned. In other words, Spike cannot currently support CSRs with // side effects on reads. reg_t processor_t::get_csr(int which) { uint32_t ctr_en = -1; if (state.prv < PRV_M) ctr_en &= state.mcounteren; if (state.prv < PRV_S) ctr_en &= state.scounteren; bool ctr_ok = (ctr_en >> (which & 31)) & 1; if (ctr_ok) { if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31) return 0; if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H) return 0; } if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31) return 0; if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H) return 0; if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31) return 0; // if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.n_pmp) // return state.pmpaddr[which - CSR_PMPADDR0]; // if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.n_pmp / 4) { // require((which & ((xlen / 32) - 1)) == 0); // reg_t res = 0; // for (size_t i0 = (which - CSR_PMPCFG0) * 4, i = i0; i < i0 + xlen / 8 && i < state.n_pmp; i++) // res |= reg_t(state.pmpcfg[i]) << (8 * (i - i0)); // return res; // } switch (which) { case CSR_FFLAGS: require_fp; if (!supports_extension('F')) break; return state.fflags; case CSR_FRM: require_fp; if (!supports_extension('F')) break; return state.frm; case CSR_FCSR: require_fp; if (!supports_extension('F')) break; return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); case CSR_INSTRET: case CSR_CYCLE: if (ctr_ok) return state.minstret; break; case CSR_MINSTRET: case CSR_MCYCLE: return state.minstret; case CSR_INSTRETH: case CSR_CYCLEH: if (ctr_ok && xlen == 32) return state.minstret >> 32; break; case CSR_MINSTRETH: case CSR_MCYCLEH: if (xlen == 32) return state.minstret >> 32; break; case CSR_SCOUNTEREN: return state.scounteren; case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD); return sstatus; } case CSR_SIP: return state.mip & state.mideleg; case CSR_SIE: return state.mie & state.mideleg; case CSR_SEPC: return state.sepc & pc_alignment_mask(); case CSR_STVAL: return state.stval; case CSR_STVEC: return state.stvec; case CSR_SCAUSE: if (max_xlen > xlen) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; case CSR_SATP: if (get_field(state.mstatus, MSTATUS_TVM)) require_privilege(PRV_M); return state.satp; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; case CSR_MIE: return state.mie; case CSR_MEPC: return state.mepc & pc_alignment_mask(); case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; case CSR_MTVAL: return state.mtval; case CSR_MISA: return state.misa; case CSR_MARCHID: return 5; case CSR_MIMPID: return 0; case CSR_MVENDORID: return 0; case CSR_MHARTID: return id; case CSR_MTVEC: return state.mtvec; case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TSELECT: return state.tselect; case CSR_TDATA1: if (state.tselect < state.num_triggers) { reg_t v = 0; mcontrol_t *mc = &state.mcontrol[state.tselect]; v = set_field(v, MCONTROL_TYPE(xlen), mc->type); v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode); v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax); v = set_field(v, MCONTROL_SELECT, mc->select); v = set_field(v, MCONTROL_TIMING, mc->timing); v = set_field(v, MCONTROL_ACTION, mc->action); v = set_field(v, MCONTROL_CHAIN, mc->chain); v = set_field(v, MCONTROL_MATCH, mc->match); v = set_field(v, MCONTROL_M, mc->m); v = set_field(v, MCONTROL_H, mc->h); v = set_field(v, MCONTROL_S, mc->s); v = set_field(v, MCONTROL_U, mc->u); v = set_field(v, MCONTROL_EXECUTE, mc->execute); v = set_field(v, MCONTROL_STORE, mc->store); v = set_field(v, MCONTROL_LOAD, mc->load); return v; } else { return 0; } break; case CSR_TDATA2: if (state.tselect < state.num_triggers) { return state.tdata2[state.tselect]; } else { return 0; } break; case CSR_TDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; v = set_field(v, DCSR_XDEBUGVER, 1); v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); v = set_field(v, DCSR_STOPCYCLE, 0); v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_CAUSE, state.dcsr.cause); v = set_field(v, DCSR_STEP, state.dcsr.step); v = set_field(v, DCSR_PRV, state.dcsr.prv); return v; } case CSR_DPC: return state.dpc & pc_alignment_mask(); case CSR_DSCRATCH: return state.dscratch; } throw trap_illegal_instruction(0); } reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) { throw trap_illegal_instruction(0); } insn_func_t processor_t::decode_insn(insn_t insn) { // look up opcode in hash table size_t idx = insn.bits() % OPCODE_CACHE_SIZE; insn_desc_t desc = opcode_cache[idx]; if (unlikely(insn.bits() != desc.match)) { // fall back to linear search insn_desc_t* p = &instructions[0]; while ((insn.bits() & p->mask) != p->match) p++; desc = *p; if (p->mask != 0 && p > &instructions[0]) { if (p->match != (p-1)->match && p->match != (p+1)->match) { // move to front of opcode list to reduce miss penalty while (--p >= &instructions[0]) *(p+1) = *p; instructions[0] = desc; } } opcode_cache[idx] = desc; opcode_cache[idx].match = insn.bits(); } return xlen == 64 ? desc.rv64 : desc.rv32; } void processor_t::register_insn(insn_desc_t desc) { instructions.push_back(desc); } void processor_t::build_opcode_map() { struct cmp { bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) { if (lhs.match == rhs.match) return lhs.mask > rhs.mask; return lhs.match > rhs.match; } }; std::sort(instructions.begin(), instructions.end(), cmp()); for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction}; } void processor_t::register_extension(extension_t* x) { for (auto insn : x->get_instructions()) register_insn(insn); build_opcode_map(); for (auto disasm_insn : x->get_disasms()) disassembler->add_insn(disasm_insn); if (ext != NULL) throw std::logic_error("only one extension may be registered"); ext = x; x->set_processor(this); } void processor_t::register_base_instructions() { #define DECLARE_INSN(name, match, mask) \ insn_bits_t name##_match = (match), name##_mask = (mask); #include "encoding.h" #undef DECLARE_INSN #define DEFINE_INSN(name) \ REGISTER_INSN(this, name, name##_match, name##_mask) #include "insn_list.h" #undef DEFINE_INSN register_insn({0, 0, &illegal_instruction, &illegal_instruction}); build_opcode_map(); } bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes) { switch (addr) { case 0: if (len <= 4) { memset(bytes, 0, len); bytes[0] = get_field(state.mip, MIP_MSIP); return true; } break; } return false; } bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) { switch (addr) { case 0: if (len <= 4) { state.mip = set_field(state.mip, MIP_MSIP, bytes[0]); return true; } break; } return false; } void processor_t::trigger_updated() { // mmu->flush_tlb(); mmu->check_triggers_fetch = false; mmu->check_triggers_load = false; mmu->check_triggers_store = false; for (unsigned i = 0; i < state.num_triggers; i++) { if (state.mcontrol[i].execute) { mmu->check_triggers_fetch = true; } if (state.mcontrol[i].load) { mmu->check_triggers_load = true; } if (state.mcontrol[i].store) { mmu->check_triggers_store = true; } } }

// See LICENSE for license details. #ifndef _RISCV_PROCESSOR_H #define _RISCV_PROCESSOR_H #include "decode.h" #include "config.h" #include "devices.h" #include "trap.h" #include <string> #include <vector> #include <map> #include "debug_rom_defines.h" class processor_t; class mmu_t; typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t); class simif_t; class trap_t; class extension_t; class disassembler_t; struct insn_desc_t { insn_bits_t match; insn_bits_t mask; insn_func_t rv32; insn_func_t rv64; }; struct commit_log_reg_t { reg_t addr; freg_t data; }; typedef struct { uint8_t prv; bool step; bool ebreakm; bool ebreakh; bool ebreaks; bool ebreaku; bool halt; uint8_t cause; } dcsr_t; typedef enum { ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE, ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START, ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP, ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT } mcontrol_action_t; typedef enum { MATCH_EQUAL = MCONTROL_MATCH_EQUAL, MATCH_NAPOT = MCONTROL_MATCH_NAPOT, MATCH_GE = MCONTROL_MATCH_GE, MATCH_LT = MCONTROL_MATCH_LT, MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW, MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH } mcontrol_match_t; typedef struct { uint8_t type; bool dmode; uint8_t maskmax; bool select; bool timing; mcontrol_action_t action; bool chain; mcontrol_match_t match; bool m; bool h; bool s; bool u; bool execute; bool store; bool load; } mcontrol_t; // architectural state of a RISC-V hart struct state_t { void reset(reg_t max_isa); static const int num_triggers = 4; reg_t pc; regfile_t<reg_t, NXPR, true> XPR; regfile_t<freg_t, NFPR, false> FPR; // control and status registers reg_t prv; // TODO: Can this be an enum instead? reg_t misa; reg_t mstatus; reg_t mepc; reg_t mtval; reg_t mscratch; reg_t mtvec; reg_t mcause; reg_t minstret; reg_t mie; reg_t mip; reg_t medeleg; reg_t mideleg; uint32_t mcounteren; uint32_t scounteren; reg_t sepc; reg_t stval; reg_t sscratch; reg_t stvec; reg_t satp; reg_t scause; reg_t dpc; reg_t dscratch; dcsr_t dcsr; reg_t tselect; mcontrol_t mcontrol[num_triggers]; reg_t tdata2[num_triggers]; static const int n_pmp = 16; uint8_t pmpcfg[n_pmp]; reg_t pmpaddr[n_pmp]; uint32_t fflags; uint32_t frm; bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This // can only be set by executing dret. enum { STEP_NONE, STEP_STEPPING, STEP_STEPPED } single_step; #ifdef RISCV_ENABLE_COMMITLOG commit_log_reg_t log_reg_write; reg_t last_inst_priv; int last_inst_xlen; int last_inst_flen; uint32_t last_insn; bool was_exception; #endif }; typedef enum { OPERATION_EXECUTE, OPERATION_STORE, OPERATION_LOAD, } trigger_operation_t; // Count number of contiguous 1 bits starting from the LSB. static int cto(reg_t val) { int res = 0; while ((val & 1) == 1) val >>= 1, res++; return res; } // this class represents one processor in a RISC-V machine. class processor_t : public abstract_device_t { public: processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset=false); ~processor_t(); void set_debug(bool value); void set_histogram(bool value); void reset(); void step(size_t n); // run for n cycles void set_csr(int which, reg_t val); reg_t get_csr(int which); mmu_t* get_mmu() { return mmu; } state_t* get_state() { return &state; } unsigned get_xlen() { return xlen; } unsigned get_max_xlen() { return max_xlen; } std::string get_isa_string() { return isa_string; } unsigned get_flen() { return supports_extension('Q') ? 128 : supports_extension('D') ? 64 : supports_extension('F') ? 32 : 0; } extension_t* get_extension() { return ext; } bool supports_extension(unsigned char ext) { if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a'; return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1); } reg_t pc_alignment_mask() { return ~(reg_t)(supports_extension('C') ? 0 : 2); } void check_pc_alignment(reg_t pc) { if (unlikely(pc & ~pc_alignment_mask())) throw trap_instruction_address_misaligned(pc); } reg_t legalize_privilege(reg_t); void set_privilege(reg_t); void update_histogram(reg_t pc); const disassembler_t* get_disassembler() { return disassembler; } void register_insn(insn_desc_t); void register_extension(extension_t*); // MMIO slave interface bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); // When true, display disassembly of each instruction that's executed. bool debug; // When true, take the slow simulation path. bool slow_path(); bool halted() { return state.dcsr.cause ? true : false; } bool halt_request; // Return the index of a trigger that matched, or -1. inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data) { if (state.dcsr.cause) return -1; bool chain_ok = true; for (unsigned int i = 0; i < state.num_triggers; i++) { if (!chain_ok) { chain_ok |= !state.mcontrol[i].chain; continue; } if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) || (operation == OPERATION_STORE && !state.mcontrol[i].store) || (operation == OPERATION_LOAD && !state.mcontrol[i].load) || (state.prv == PRV_M && !state.mcontrol[i].m) || (state.prv == PRV_S && !state.mcontrol[i].s) || (state.prv == PRV_U && !state.mcontrol[i].u)) { continue; } reg_t value; if (state.mcontrol[i].select) { value = data; } else { value = address; } // We need this because in 32-bit mode sometimes the PC bits get sign // extended. if (xlen == 32) { value &= 0xffffffff; } switch (state.mcontrol[i].match) { case MATCH_EQUAL: if (value != state.tdata2[i]) continue; break; case MATCH_NAPOT: { reg_t mask = ~((1 << cto(state.tdata2[i])) - 1); if ((value & mask) != (state.tdata2[i] & mask)) continue; } break; case MATCH_GE: if (value < state.tdata2[i]) continue; break; case MATCH_LT: if (value >= state.tdata2[i]) continue; break; case MATCH_MASK_LOW: { reg_t mask = state.tdata2[i] >> (xlen/2); if ((value & mask) != (state.tdata2[i] & mask)) continue; } break; case MATCH_MASK_HIGH: { reg_t mask = state.tdata2[i] >> (xlen/2); if (((value >> (xlen/2)) & mask) != (state.tdata2[i] & mask)) continue; } break; } if (!state.mcontrol[i].chain) { return i; } chain_ok = true; } return -1; } void trigger_updated(); private: simif_t* sim; mmu_t* mmu; // main memory is always accessed via the mmu extension_t* ext; disassembler_t* disassembler; state_t state; uint32_t id; unsigned max_xlen; unsigned xlen; reg_t max_isa; std::string isa_string; bool histogram_enabled; bool halt_on_reset; std::vector<insn_desc_t> instructions; std::map<reg_t,uint64_t> pc_histogram; static const size_t OPCODE_CACHE_SIZE = 8191; insn_desc_t opcode_cache[OPCODE_CACHE_SIZE]; void take_pending_interrupt() { take_interrupt(state.mip & state.mie); } void take_interrupt(reg_t mask); // take first enabled interrupt in mask void take_trap(trap_t& t, reg_t epc); // take an exception void disasm(insn_t insn); // disassemble and print an instruction int paddr_bits(); void enter_debug_mode(uint8_t cause); friend class mmu_t; friend class clint_t; friend class extension_t; void parse_isa_string(const char* isa); void build_opcode_map(); void register_base_instructions(); insn_func_t decode_insn(insn_t insn); // Track repeated executions for processor_t::disasm() uint64_t last_pc, last_bits, executions; }; reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); #define REGISTER_INSN(proc, name, match, mask) \ extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \ proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name}); #endif

// See LICENSE for license details. #include "disasm.h" const char* xpr_name[] = { "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" }; const char* fpr_name[] = { "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" }; const char* csr_name(int which) { switch (which) { #define DECLARE_CSR(name, number) case number: return #name; #include "encoding.h" #undef DECLARE_CSR } return "unknown-csr"; }

#include <arpa/inet.h> #include <errno.h> #include <fcntl.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <algorithm> #include <cassert> #include <cstdio> #include "remote_bitbang.h" #if 1 # define D(x) x #else # define D(x) #endif /////////// remote_bitbang_t remote_bitbang_t::remote_bitbang_t(uint16_t port, jtag_dtm_t *tap) : tap(tap), socket_fd(0), client_fd(0), recv_start(0), recv_end(0) { socket_fd = socket(AF_INET, SOCK_STREAM, 0); if (socket_fd == -1) { fprintf(stderr, "remote_bitbang failed to make socket: %s (%d)\n", strerror(errno), errno); abort(); } fcntl(socket_fd, F_SETFL, O_NONBLOCK); int reuseaddr = 1; if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr, sizeof(int)) == -1) { fprintf(stderr, "remote_bitbang failed setsockopt: %s (%d)\n", strerror(errno), errno); abort(); } struct sockaddr_in addr; memset(&addr, 0, sizeof(addr)); addr.sin_family = AF_INET; addr.sin_addr.s_addr = INADDR_ANY; addr.sin_port = htons(port); if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) { fprintf(stderr, "remote_bitbang failed to bind socket: %s (%d)\n", strerror(errno), errno); abort(); } if (listen(socket_fd, 1) == -1) { fprintf(stderr, "remote_bitbang failed to listen on socket: %s (%d)\n", strerror(errno), errno); abort(); } socklen_t addrlen = sizeof(addr); if (getsockname(socket_fd, (struct sockaddr *) &addr, &addrlen) == -1) { fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n", strerror(errno), errno); abort(); } printf("Listening for remote bitbang connection on port %d.\n", ntohs(addr.sin_port)); fflush(stdout); } void remote_bitbang_t::accept() { client_fd = ::accept(socket_fd, NULL, NULL); if (client_fd == -1) { if (errno == EAGAIN) { // No client waiting to connect right now. } else { fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno), errno); abort(); } } else { fcntl(client_fd, F_SETFL, O_NONBLOCK); } } void remote_bitbang_t::tick() { if (client_fd > 0) { execute_commands(); } else { this->accept(); } } void remote_bitbang_t::execute_commands() { static char send_buf[buf_size]; unsigned total_processed = 0; bool quit = false; bool in_rti = tap->state() == RUN_TEST_IDLE; bool entered_rti = false; while (1) { if (recv_start < recv_end) { unsigned send_offset = 0; while (recv_start < recv_end) { uint8_t command = recv_buf[recv_start]; switch (command) { case 'B': /* fprintf(stderr, "*BLINK*\n"); */ break; case 'b': /* fprintf(stderr, "_______\n"); */ break; case 'r': tap->reset(); break; case '0': tap->set_pins(0, 0, 0); break; case '1': tap->set_pins(0, 0, 1); break; case '2': tap->set_pins(0, 1, 0); break; case '3': tap->set_pins(0, 1, 1); break; case '4': tap->set_pins(1, 0, 0); break; case '5': tap->set_pins(1, 0, 1); break; case '6': tap->set_pins(1, 1, 0); break; case '7': tap->set_pins(1, 1, 1); break; case 'R': send_buf[send_offset++] = tap->tdo() ? '1' : '0'; break; case 'Q': quit = true; break; default: fprintf(stderr, "remote_bitbang got unsupported command '%c'\n", command); } recv_start++; total_processed++; if (!in_rti && tap->state() == RUN_TEST_IDLE) { entered_rti = true; break; } in_rti = false; } unsigned sent = 0; while (sent < send_offset) { ssize_t bytes = write(client_fd, send_buf + sent, send_offset); if (bytes == -1) { fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno); abort(); } sent += bytes; } } if (total_processed > buf_size || quit || entered_rti) { // Don't go forever, because that could starve the main simulation. break; } recv_start = 0; recv_end = read(client_fd, recv_buf, buf_size); if (recv_end == -1) { if (errno == EAGAIN) { break; } else { fprintf(stderr, "remote_bitbang failed to read on socket: %s (%d)\n", strerror(errno), errno); abort(); } } if (quit) { fprintf(stderr, "Remote Bitbang received 'Q'\n"); } if (recv_end == 0 || quit) { // The remote disconnected. fprintf(stderr, "Received nothing. Quitting.\n"); close(client_fd); client_fd = 0; break; } } }

#ifndef REMOTE_BITBANG_H #define REMOTE_BITBANG_H #include <stdint.h> #include "jtag_dtm.h" class remote_bitbang_t { public: // Create a new server, listening for connections from localhost on the given // port. remote_bitbang_t(uint16_t port, jtag_dtm_t *tap); // Do a bit of work. void tick(); private: jtag_dtm_t *tap; int socket_fd; int client_fd; static const ssize_t buf_size = 64 * 1024; char recv_buf[buf_size]; ssize_t recv_start, recv_end; // Check for a client connecting, and accept if there is one. void accept(); // Execute any commands the client has for us. void execute_commands(); }; #endif

AC_LANG_CPLUSPLUS AC_ARG_WITH(isa, [AS_HELP_STRING([--with-isa=RV64IMAFDC], [Sets the default RISC-V ISA])], AC_DEFINE_UNQUOTED([DEFAULT_ISA], "$withval", [Default value for --isa switch]), AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC", [Default value for --isa switch])) AC_SEARCH_LIBS([dlopen], [dl dld], [], [ AC_MSG_ERROR([unable to find the dlopen() function]) ]) AC_ARG_WITH([fesvr], [AS_HELP_STRING([--with-fesvr], [path to your fesvr installation if not in a standard location])], [ LDFLAGS="-L$withval/lib $LDFLAGS" CPPFLAGS="-I$withval/include $CPPFLAGS" ] ) AC_CHECK_LIB(fesvr, libfesvr_is_present, [], [AC_MSG_ERROR([libfesvr is required])], [-pthread]) AC_CHECK_LIB(pthread, pthread_create, [], [AC_MSG_ERROR([libpthread is required])]) AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit log generation])) AS_IF([test "x$enable_commitlog" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation]) ]) AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histogram generation])) AS_IF([test "x$enable_histogram" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation]) ]) AC_ARG_ENABLE([dirty], AS_HELP_STRING([--enable-dirty], [Enable hardware management of PTE accessed and dirty bits])) AS_IF([test "x$enable_dirty" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits]) ]) AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores])) AS_IF([test "x$enable_misaligned" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores]) ])

get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN($.*$,.*,.*)/\1/') get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,$.*$,.*)/\1/') riscv_subproject_deps = \ softfloat \ riscv_install_prog_srcs = \ riscv_hdrs = \ common.h \ decode.h \ devices.h \ disasm.h \ dts.h \ mmu.h \ processor.h \ sim.h \ simif.h \ trap.h \ encoding.h \ cachesim.h \ memtracer.h \ tracer.h \ extension.h \ rocc.h \ insn_template.h \ mulhi.h \ debug_module.h \ debug_rom_defines.h \ remote_bitbang.h \ jtag_dtm.h \ riscv_precompiled_hdrs = \ insn_template.h \ riscv_srcs = \ processor.cc \ execute.cc \ dts.cc \ sim.cc \ interactive.cc \ trap.cc \ cachesim.cc \ mmu.cc \ disasm.cc \ extension.cc \ extensions.cc \ rocc.cc \ regnames.cc \ devices.cc \ rom.cc \ clint.cc \ uart.cc \ dump.cc \ debug_module.cc \ remote_bitbang.cc \ jtag_dtm.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = riscv_gen_hdrs = \ icache.h \ insn_list.h \ riscv_insn_list = \ add \ addi \ addiw \ addw \ amoadd_d \ amoadd_w \ amoand_d \ amoand_w \ amomax_d \ amomaxu_d \ amomaxu_w \ amomax_w \ amomin_d \ amominu_d \ amominu_w \ amomin_w \ amoor_d \ amoor_w \ amoswap_d \ amoswap_w \ amoxor_d \ amoxor_w \ and \ andi \ auipc \ beq \ bge \ bgeu \ blt \ bltu \ bne \ c_add \ c_addi4spn \ c_addi \ c_addw \ c_and \ c_andi \ c_beqz \ c_bnez \ c_ebreak \ c_fld \ c_fldsp \ c_flw \ c_flwsp \ c_fsd \ c_fsdsp \ c_fsw \ c_fswsp \ c_jal \ c_jalr \ c_j \ c_jr \ c_li \ c_lui \ c_lw \ c_lwsp \ c_mv \ c_or \ c_slli \ c_srai \ c_srli \ c_sub \ c_subw \ c_xor \ csrrc \ csrrci \ csrrs \ csrrsi \ csrrw \ csrrwi \ c_sw \ c_swsp \ div \ divu \ divuw \ divw \ dret \ ebreak \ ecall \ fadd_d \ fadd_q \ fadd_s \ fclass_d \ fclass_q \ fclass_s \ fcvt_d_l \ fcvt_d_lu \ fcvt_d_q \ fcvt_d_s \ fcvt_d_w \ fcvt_d_wu \ fcvt_l_d \ fcvt_l_q \ fcvt_l_s \ fcvt_lu_d \ fcvt_lu_q \ fcvt_lu_s \ fcvt_q_d \ fcvt_q_l \ fcvt_q_lu \ fcvt_q_s \ fcvt_q_w \ fcvt_q_wu \ fcvt_s_d \ fcvt_s_l \ fcvt_s_lu \ fcvt_s_q \ fcvt_s_w \ fcvt_s_wu \ fcvt_w_d \ fcvt_w_q \ fcvt_w_s \ fcvt_wu_d \ fcvt_wu_q \ fcvt_wu_s \ fdiv_d \ fdiv_q \ fdiv_s \ fence \ fence_i \ feq_d \ feq_q \ feq_s \ fld \ fle_d \ fle_q \ fle_s \ flq \ flt_d \ flt_q \ flt_s \ flw \ fmadd_d \ fmadd_q \ fmadd_s \ fmax_d \ fmax_q \ fmax_s \ fmin_d \ fmin_q \ fmin_s \ fmsub_d \ fmsub_q \ fmsub_s \ fmul_d \ fmul_q \ fmul_s \ fmv_d_x \ fmv_w_x \ fmv_x_d \ fmv_x_w \ fnmadd_d \ fnmadd_q \ fnmadd_s \ fnmsub_d \ fnmsub_q \ fnmsub_s \ fsd \ fsgnj_d \ fsgnj_q \ fsgnjn_d \ fsgnjn_q \ fsgnjn_s \ fsgnj_s \ fsgnjx_d \ fsgnjx_q \ fsgnjx_s \ fsq \ fsqrt_d \ fsqrt_q \ fsqrt_s \ fsub_d \ fsub_q \ fsub_s \ fsw \ jal \ jalr \ lb \ lbu \ ld \ lh \ lhu \ lr_d \ lr_w \ lui \ lw \ lwu \ mret \ mul \ mulh \ mulhsu \ mulhu \ mulw \ or \ ori \ rem \ remu \ remuw \ remw \ sb \ sc_d \ sc_w \ sd \ sfence_vma \ sh \ sll \ slli \ slliw \ sllw \ slt \ slti \ sltiu \ sltu \ sra \ srai \ sraiw \ sraw \ sret \ srl \ srli \ srliw \ srlw \ sub \ subw \ sw \ wfi \ xor \ xori \ riscv_gen_srcs = \ $(addsuffix .cc,$(riscv_insn_list)) icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = $.*$;/\1/'` icache.h: mmu.h $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp mv $@.tmp $@ insn_list.h: $(src_dir)/riscv/riscv.mk.in for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \ printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \ done > $@.tmp mv $@.tmp $@ $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@ riscv_junk = \ $(riscv_gen_srcs) \

// See LICENSE for license details. #include "rocc.h" #include "trap.h" #include <cstdlib> #define customX(n) \ static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ { \ rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \ rocc_insn_union_t u; \ u.i = insn; \ reg_t xs1 = u.r.xs1 ? RS1 : -1; \ reg_t xs2 = u.r.xs2 ? RS2 : -1; \ reg_t xd = rocc->custom##n(u.r, xs1, xs2); \ if (u.r.xd) \ WRITE_RD(xd); \ return pc+4; \ } \ \ reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \ { \ illegal_instruction(); \ return 0; \ } customX(0) customX(1) customX(2) customX(3) std::vector<insn_desc_t> rocc_t::get_instructions() { std::vector<insn_desc_t> insns; insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0}); insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1}); insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2}); insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3}); return insns; } std::vector<disasm_insn_t*> rocc_t::get_disasms() { std::vector<disasm_insn_t*> insns; return insns; }

#ifndef _RISCV_ROCC_H #define _RISCV_ROCC_H #include "extension.h" struct rocc_insn_t { unsigned opcode : 7; unsigned rd : 5; unsigned xs2 : 1; unsigned xs1 : 1; unsigned xd : 1; unsigned rs1 : 5; unsigned rs2 : 5; unsigned funct : 7; }; union rocc_insn_union_t { rocc_insn_t r; insn_t i; }; class rocc_t : public extension_t { public: virtual reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2); virtual reg_t custom1(rocc_insn_t insn, reg_t xs1, reg_t xs2); virtual reg_t custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2); virtual reg_t custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2); std::vector<insn_desc_t> get_instructions(); std::vector<disasm_insn_t*> get_disasms(); }; #endif

#include "devices.h" rom_device_t::rom_device_t(std::vector<char> data) : data(data) { } bool rom_device_t::load(reg_t addr, size_t len, uint8_t* bytes) { if (addr + len > data.size()) return false; memcpy(bytes, &data[addr], len); return true; } bool rom_device_t::store(reg_t addr, size_t len, const uint8_t* bytes) { return false; }

// See LICENSE for license details. #include "sim.h" #include "mmu.h" #include "dts.h" #include "remote_bitbang.h" #include <map> #include <iostream> #include <sstream> #include <climits> #include <cstdlib> #include <cassert> #include <signal.h> #include <unistd.h> #include <sys/wait.h> #include <sys/types.h> volatile bool ctrlc_pressed = false; static void handle_signal(int sig) { if (ctrlc_pressed) exit(-1); ctrlc_pressed = true; signal(sig, &handle_signal); } sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, std::vector<int> const hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication) : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))), start_pc(start_pc), current_step(0), current_proc(0), debug(false), histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits, require_authentication) { signal(SIGINT, &handle_signal); for (auto& x : mems) bus.add_device(x.first, x.second); debug_module.add_device(&bus); debug_mmu = new mmu_t(this, NULL); if (hartids.size() == 0) { for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, i, halted); } } else { if (hartids.size() != procs.size()) { std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl; exit(1); } for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, hartids[i], halted); } } clint.reset(new clint_t(procs)); bus.add_device(CLINT_BASE, clint.get()); uart.reset(new uart_t()); bus.add_device(UART_BASE, uart.get()); dump.reset(new dump_t()); bus.add_device(DUMP_BASE, dump.get()); } sim_t::~sim_t() { for (size_t i = 0; i < procs.size(); i++) delete procs[i]; delete debug_mmu; } void sim_thread_main(void* arg) { ((sim_t*)arg)->main(); } void sim_t::main() { if (!debug && log) set_procs_debug(true); while (!done()) { if (debug || ctrlc_pressed) interactive(); else step(INTERLEAVE); if (remote_bitbang) { remote_bitbang->tick(); } } } int sim_t::run() { host = context_t::current(); target.init(sim_thread_main, this); return htif_t::run(); } void sim_t::step(size_t n) { for (size_t i = 0, steps = 0; i < n; i += steps) { steps = std::min(n - i, INTERLEAVE - current_step); procs[current_proc]->step(steps); current_step += steps; if (current_step == INTERLEAVE) { current_step = 0; procs[current_proc]->get_mmu()->yield_load_reservation(); if (++current_proc == procs.size()) { current_proc = 0; clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); } host->switch_to(); } } } void sim_t::set_debug(bool value) { debug = value; } void sim_t::set_log(bool value) { log = value; } void sim_t::set_histogram(bool value) { histogram_enabled = value; for (size_t i = 0; i < procs.size(); i++) { procs[i]->set_histogram(histogram_enabled); } } void sim_t::set_procs_debug(bool value) { for (size_t i=0; i< procs.size(); i++) procs[i]->set_debug(value); } bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { if (addr + len < addr) return false; return bus.load(addr, len, bytes); } bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { if (addr + len < addr) return false; return bus.store(addr, len, bytes); } void sim_t::make_dtb() { start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; #include "bootrom.h" std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); // dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, procs, mems); // std::string dtb = dts_compile(dts); // rom.insert(rom.end(), dtb.begin(), dtb.end()); const int align = 0x1000; rom.resize((rom.size() + align - 1) / align * align); boot_rom.reset(new rom_device_t(rom)); bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } char* sim_t::addr_to_mem(reg_t addr) { auto desc = bus.find_device(addr); if (auto mem = dynamic_cast<mem_t*>(desc.second)) if (addr - desc.first < mem->size()) return mem->contents() + (addr - desc.first); return NULL; } // htif void sim_t::reset() { if (dtb_enabled) make_dtb(); } void sim_t::idle() { target.switch_to(); } void sim_t::read_chunk(addr_t taddr, size_t len, void* dst) { assert(len == 8); auto data = debug_mmu->load_uint64(taddr); memcpy(dst, &data, sizeof data); } void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) { assert(len == 8); uint64_t data; memcpy(&data, src, sizeof data); debug_mmu->store_uint64(taddr, data); } void sim_t::proc_reset(unsigned id) { debug_module.proc_reset(id); }

// See LICENSE for license details. #ifndef _RISCV_SIM_H #define _RISCV_SIM_H #include "processor.h" #include "devices.h" #include "debug_module.h" #include "simif.h" #include <fesvr/htif.h> #include <fesvr/context.h> #include <vector> #include <string> #include <memory> class mmu_t; class remote_bitbang_t; // this class encapsulates the processors and memory in a RISC-V machine. class sim_t : public htif_t, public simif_t { public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication); ~sim_t(); // run the simulation to completion int run(); void set_debug(bool value); void set_log(bool value); void set_histogram(bool value); void set_procs_debug(bool value); void set_dtb_enabled(bool value) { this->dtb_enabled = value; } void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { this->remote_bitbang = remote_bitbang; } const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } // Callback for processors to let the simulation know they were reset. void proc_reset(unsigned id); private: std::vector<std::pair<reg_t, mem_t*>> mems; mmu_t* debug_mmu; // debug port into main memory std::vector<processor_t*> procs; reg_t start_pc; std::string dts; std::unique_ptr<rom_device_t> boot_rom; std::unique_ptr<clint_t> clint; std::unique_ptr<dump_t> dump; std::unique_ptr<uart_t> uart; bus_t bus; processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; bool log; bool histogram_enabled; // provide a histogram of PCs bool dtb_enabled; remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines char* addr_to_mem(reg_t addr); bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); void make_dtb(); // presents a prompt for introspection into the simulation void interactive(); // functions that help implement interactive() void interactive_help(const std::string& cmd, const std::vector<std::string>& args); void interactive_quit(const std::string& cmd, const std::vector<std::string>& args); void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy); void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args); void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args); void interactive_reg(const std::string& cmd, const std::vector<std::string>& args); void interactive_freg(const std::string& cmd, const std::vector<std::string>& args); void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args); void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args); void interactive_pc(const std::string& cmd, const std::vector<std::string>& args); void interactive_mem(const std::string& cmd, const std::vector<std::string>& args); void interactive_str(const std::string& cmd, const std::vector<std::string>& args); void interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy); void interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args); void interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args); reg_t get_reg(const std::vector<std::string>& args); freg_t get_freg(const std::vector<std::string>& args); reg_t get_mem(const std::vector<std::string>& args); reg_t get_pc(const std::vector<std::string>& args); friend class processor_t; friend class mmu_t; friend class debug_module_t; // htif friend void sim_thread_main(void*); void main(); context_t* host; context_t target; void reset(); void idle(); void read_chunk(addr_t taddr, size_t len, void* dst); void write_chunk(addr_t taddr, size_t len, const void* src); size_t chunk_align() { return 8; } size_t chunk_max_size() { return 8; } public: // Initialize this after procs, because in debug_module_t::reset() we // enumerate processors, which segfaults if procs hasn't been initialized // yet. debug_module_t debug_module; }; extern volatile bool ctrlc_pressed; #endif

// See LICENSE for license details. #ifndef _RISCV_SIMIF_H #define _RISCV_SIMIF_H #include "decode.h" // this is the interface to the simulator used by the processors and memory class simif_t { public: // should return NULL for MMIO addresses virtual char* addr_to_mem(reg_t addr) = 0; // used for MMIO addresses virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) = 0; }; #endif

// See LICENSE for license details. #ifndef _RISCV_TRACER_H #define _RISCV_TRACER_H #include "processor.h" static inline void trace_opcode(processor_t* p, insn_bits_t opc, insn_t insn) { } #endif

// See LICENSE for license details. #include "trap.h" #include "processor.h" #include <cstdio> const char* trap_t::name() { const char* fmt = uint8_t(which) == which ? "trap #%u" : "interrupt #%u"; sprintf(_name, fmt, uint8_t(which)); return _name; }

// See LICENSE for license details. #ifndef _RISCV_TRAP_H #define _RISCV_TRAP_H #include "decode.h" #include <stdlib.h> struct state_t; class trap_t { public: trap_t(reg_t which) : which(which) {} virtual const char* name(); virtual bool has_tval() { return false; } virtual reg_t get_tval() { return 0; } reg_t cause() { return which; } private: char _name[16]; reg_t which; }; class mem_trap_t : public trap_t { public: mem_trap_t(reg_t which, reg_t tval) : trap_t(which), tval(tval) {} bool has_tval() override { return true; } reg_t get_tval() override { return tval; } private: reg_t tval; }; #define DECLARE_TRAP(n, x) class trap_##x : public trap_t { \ public: \ trap_##x() : trap_t(n) {} \ const char* name() { return "trap_"#x; } \ }; #define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \ public: \ trap_##x(reg_t tval) : mem_trap_t(n, tval) {} \ const char* name() { return "trap_"#x; } \ }; DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault) DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) DECLARE_MEM_TRAP(CAUSE_STORE_PAGE_FAULT, store_page_fault) #endif

#include "devices.h" #include "processor.h" #define RBR 0 #define THR 0 #define IER 1 #define IIR 2 #define FCR 2 #define LCR 3 #define MCR 4 #define LSR 5 #define MSR 6 #define SCR 7 #define DLL 0 #define DLM 1 #define THRE 5 // transmit holding register empty #define TEMT 6 // transmit holding register empty uart_t::uart_t() { dll = 0; dlm = 0; ier = 0; lcr = 0; mcr = 0; lsr = 0; msr = 0; scr = 0; } // set {char} 0x10000004 = 0x00 // set {char} 0x1000000C = 0x80 // set {char} 0x10000000 = 0x1B // set {char} 0x10000004 = 0x00 // set {char} 0x1000000C = 0x03 // set {char} 0x10000008 = 0xC7 bool uart_t::load(reg_t addr, size_t len, uint8_t* bytes) { // we do not support unaligned stores if ((addr & 0x3) != 0) { return false; } switch ((addr >> 0x2) & 0x7) { case THR: // access DLL if (lcr & 0x80) { bytes[0] = dll; } else { // TODO(zarubaf) // printf("%c", bytes[0]); bytes[0] = 0; } break; case IER: // access DLM if (lcr & 0x80) { bytes[0] = dlm; } else { bytes[0] = ier; } break; case IIR: if (fifo_enabled) { bytes[0] = 0xC0; } else { bytes[0] = 0x00; } break; case LCR: bytes[0] = lcr; break; case MCR: bytes[0] = mcr; break; case LSR: bytes[0] = lsr | (1 << THRE) | (1 << TEMT); break; case MSR: bytes[0] = msr; break; case SCR: bytes[0] = scr; break; } return true; } bool uart_t::store(reg_t addr, size_t len, const uint8_t* bytes) { // we do not support unaligned stores if ((addr & 0x3) != 0) { return false; } switch ((addr >> 0x2) & 0x7) { case THR: // access DLL if (lcr & 0x80) { dll = bytes[0]; } else { printf("%c", bytes[0]); } break; case IER: // access DLM if (lcr & 0x80) { dlm = bytes[0]; } else { ier = bytes[0] & 0xF; } break; case FCR: if (bytes[0] & 0x1) { fifo_enabled = true; } else { fifo_enabled = false; } break; case LCR: lcr = bytes[0]; break; case MCR: mcr = bytes[0] & 0x1F; break; case LSR: lsr = bytes[0]; break; case MSR: msr = bytes[0]; break; case SCR: scr = bytes[0]; break; } return true; }

WRITE_RD(sext_xlen(RS1 + RS2));

WRITE_RD(sext_xlen(RS1 + insn.i_imm()));

require_rv64; WRITE_RD(sext32(insn.i_imm() + RS1));

require_rv64; WRITE_RD(sext32(RS1 + RS2));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs + RS2; }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs + RS2; })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs & RS2; }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs | RS2; }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs | RS2; })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; })));

require_extension('A'); require_rv64; WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs ^ RS2; }));

require_extension('A'); WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs ^ RS2; })));

WRITE_RD(RS1 & RS2);

WRITE_RD(insn.i_imm() & RS1);

WRITE_RD(sext_xlen(insn.u_imm() + pc));

if(RS1 == RS2) set_pc(BRANCH_TARGET);

if(sreg_t(RS1) >= sreg_t(RS2)) set_pc(BRANCH_TARGET);

if(RS1 >= RS2) set_pc(BRANCH_TARGET);

if(sreg_t(RS1) < sreg_t(RS2)) set_pc(BRANCH_TARGET);

if(RS1 < RS2) set_pc(BRANCH_TARGET);

if(RS1 != RS2) set_pc(BRANCH_TARGET);

bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old & ~RS1); } WRITE_RD(sext_xlen(old)); serialize();

bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old & ~(reg_t)insn.rs1()); } WRITE_RD(sext_xlen(old)); serialize();

bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old | RS1); } WRITE_RD(sext_xlen(old)); serialize();

bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); if (write) { p->set_csr(csr, old | insn.rs1()); } WRITE_RD(sext_xlen(old)); serialize();

int csr = validate_csr(insn.csr(), true); reg_t old = p->get_csr(csr); p->set_csr(csr, RS1); WRITE_RD(sext_xlen(old)); serialize();

int csr = validate_csr(insn.csr(), true); reg_t old = p->get_csr(csr); p->set_csr(csr, insn.rs1()); WRITE_RD(sext_xlen(old)); serialize();

require_extension('C'); require(insn.rvc_rs2() != 0); WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));

require_extension('C'); WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm()));

require_extension('C'); require(insn.rvc_addi4spn_imm() != 0); WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm()));

require_extension('C'); require_rv64; WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S));