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// Copyright 2018 Robert Balas <balasr@student.ethz.ch>
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Top level wrapper for a verilator RI5CY testbench
// Contributor: Robert Balas <balasr@student.ethz.ch>
#include "svdpi.h"
#include "Vtb_top_verilator__Dpi.h"
#include "Vtb_top_verilator.h"
#include "verilated_vcd_c.h"
#include "verilated.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <exception>
#include <cstdio>
#include <cstdint>
#include <cerrno>
void dump_memory();
double sc_time_stamp();
static vluint64_t t = 0;
Vtb_top_verilator *top;
int main(int argc, char **argv, char **env)
{
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
top = new Vtb_top_verilator();
svSetScope(svGetScopeFromName(
"TOP.tb_top_verilator.mm_ram_i.dp_ram_i"));
Verilated::scopesDump();
#ifdef VCD_TRACE
VerilatedVcdC *tfp = new VerilatedVcdC;
top->trace(tfp, 99);
tfp->open("verilator_tb.vcd");
#endif
top->fetch_enable_i = 1;
top->clk_i = 0;
top->rst_ni = 0;
top->eval();
dump_memory();
while (!Verilated::gotFinish()) {
if (t > 40)
top->rst_ni = 1;
top->clk_i = !top->clk_i;
top->eval();
#ifdef VCD_TRACE
tfp->dump(t);
#endif
t += 5;
}
#ifdef VCD_TRACE
tfp->close();
#endif
delete top;
exit(0);
}
double sc_time_stamp()
{
return t;
}
void dump_memory()
{
errno = 0;
std::ofstream mem_file;
svLogicVecVal addr = {0};
mem_file.exceptions(std::ofstream::failbit | std::ofstream::badbit);
try {
mem_file.open("memory_dump.bin");
for (size_t i = 0; i < 1048576; i++) {
addr.aval = i;
uint32_t val = read_byte(&addr);
mem_file << std::setfill('0') << std::setw(2) << std::hex << val
<< std::endl;
}
mem_file.close();
std::cout << "finished dumping memory" << std::endl;
} catch (std::ofstream::failure e) {
std::cerr << "exception opening/reading/closing file memory_dump.bin\n";
}
}
|
// Copyright 2018 Robert Balas <balasr@student.ethz.ch>
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Top level wrapper for a verilator RI5CY testbench
// Contributor: Robert Balas <balasr@student.ethz.ch>
module tb_top_verilator #(
parameter int unsigned INSTR_RDATA_WIDTH = 32,
parameter int unsigned RAM_ADDR_WIDTH = 22,
parameter logic [31:0] BOOT_ADDR = 'h1A00_0180,
parameter bit JTAG_BOOT = 1,
parameter int unsigned OPENOCD_PORT = 9999
) (
input logic clk_i,
input logic rst_ni,
input logic fetch_enable_i,
output logic tests_passed_o,
output logic tests_failed_o
);
// defs from pulpissimo
// localparam CLUSTER_ID = 6'd31;
// localparam CORE_ID = 4'd0;
// test defs
localparam CLUSTER_ID = 6'd0;
localparam CORE_ID = 4'd0;
localparam CORE_MHARTID = {21'b0, CLUSTER_ID, 1'b0, CORE_ID};
localparam NrHarts = 1;
localparam logic [NrHarts-1:0] SELECTABLE_HARTS = 1 << CORE_MHARTID;
localparam HARTINFO = {8'h0, 4'h2, 3'b0, 1'b1, dm::DataCount, dm::DataAddr};
// signals connecting core to memory
logic instr_req;
logic instr_gnt;
logic instr_rvalid;
logic [31:0] instr_addr;
logic [INSTR_RDATA_WIDTH-1:0] instr_rdata;
logic data_req;
logic data_gnt;
logic data_rvalid;
logic [31:0] data_addr;
logic data_we;
logic [3:0] data_be;
logic [31:0] data_rdata;
logic [31:0] data_wdata;
// jtag openocd bridge signals
logic sim_jtag_tck;
logic sim_jtag_tms;
logic sim_jtag_tdi;
logic sim_jtag_trstn;
logic sim_jtag_tdo;
logic [31:0] sim_jtag_exit;
logic sim_jtag_enable;
// signals for debug unit
logic debug_req_ready;
dm::dmi_resp_t debug_resp;
logic jtag_req_valid;
dm::dmi_req_t jtag_dmi_req;
logic jtag_resp_ready;
logic jtag_resp_valid;
logic [NrHarts-1:0] dm_debug_req;
logic ndmreset, ndmreset_n;
// debug unit slave interface
logic dm_grant;
logic dm_rvalid;
logic dm_req;
logic dm_we;
logic [31:0] dm_addr;
logic [31:0] dm_wdata;
logic [31:0] dm_rdata;
logic [3:0] dm_be;
// debug unit master interface (system bus access)
logic sb_req;
logic [31:0] sb_addr;
logic sb_we;
logic [31:0] sb_wdata;
logic [3:0] sb_be;
logic sb_gnt;
logic sb_rvalid;
logic [31:0] sb_rdata;
// irq signals (not used)
logic irq;
logic [0:4] irq_id_in;
logic irq_ack;
logic [0:4] irq_id_out;
// make jtag bridge work
assign sim_jtag_enable = JTAG_BOOT;
// instantiate the core
cv32e40p_core #(
.PULP_XPULP ( 0 ),
.PULP_CLUSTER ( 0 ),
.FPU ( 0 ),
.PULP_ZFINX ( 0 ),
.NUM_MHPMCOUNTERS ( 1 )
) riscv_core_i (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.pulp_clock_en_i ( '1 ),
.scan_cg_en_i ( '0 ),
.boot_addr_i ( BOOT_ADDR ),
.mtvec_addr_i ( 32'h00000000 ),
.dm_halt_addr_i ( 32'h1A110800 ),
.hart_id_i ( CORE_MHARTID ),
.dm_exception_addr_i ( 32'h00000000 ),
.instr_addr_o ( instr_addr ),
.instr_req_o ( instr_req ),
.instr_rdata_i ( instr_rdata ),
.instr_gnt_i ( instr_gnt ),
.instr_rvalid_i ( instr_rvalid ),
.data_addr_o ( data_addr ),
.data_wdata_o ( data_wdata ),
.data_we_o ( data_we ),
.data_req_o ( data_req ),
.data_be_o ( data_be ),
.data_rdata_i ( data_rdata ),
.data_gnt_i ( data_gnt ),
.data_rvalid_i ( data_rvalid ),
.apu_master_req_o ( ),
.apu_master_ready_o ( ),
.apu_master_gnt_i ( ),
.apu_master_operands_o ( ),
.apu_master_op_o ( ),
.apu_master_type_o ( ),
.apu_master_flags_o ( ),
.apu_master_valid_i ( ),
.apu_master_result_i ( ),
.apu_master_flags_i ( ),
.irq_i ( 32'b0 ),
.irq_ack_o ( irq_ack ),
.irq_id_o ( irq_id_out ),
.debug_req_i ( dm_debug_req[CORE_MHARTID] ),
.fetch_enable_i ( fetch_enable_i ),
.core_sleep_o ( core_sleep_o ));
// this handles read to RAM and memory mapped pseudo peripherals
mm_ram #(
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH),
.INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH),
.JTAG_BOOT(JTAG_BOOT)
) mm_ram_i (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
// core instruction access
.instr_req_i ( instr_req ),
.instr_addr_i ( instr_addr ),
.instr_rdata_o ( instr_rdata ),
.instr_rvalid_o ( instr_rvalid ),
.instr_gnt_o ( instr_gnt ),
// core data access
.data_req_i ( data_req ),
.data_addr_i ( data_addr ),
.data_we_i ( data_we ),
.data_be_i ( data_be ),
.data_wdata_i ( data_wdata ),
.data_rdata_o ( data_rdata ),
.data_rvalid_o ( data_rvalid ),
.data_gnt_o ( data_gnt ),
// system bus access from debug unit
.sb_req_i ( sb_req ),
.sb_addr_i ( sb_addr ),
.sb_we_i ( sb_we ),
.sb_be_i ( sb_be ),
.sb_wdata_i ( sb_wdata ),
.sb_rdata_o ( sb_rdata ),
.sb_rvalid_o ( sb_rvalid ),
.sb_gnt_o ( sb_gnt ),
// access to debug unit
.dm_req_o ( dm_req ),
.dm_addr_o ( dm_addr ),
.dm_we_o ( dm_we ),
.dm_be_o ( dm_be ),
.dm_wdata_o ( dm_wdata ),
.dm_rdata_i ( dm_rdata ),
.dm_rvalid_i ( dm_rvalid ),
.dm_gnt_i ( dm_gnt ),
.irq_id_i ( irq_id_out ),
.irq_ack_i ( irq_ack ),
.irq_id_o ( irq_id_in ),
.irq_o ( irq ),
.tests_passed_o ( tests_passed_o ),
.tests_failed_o ( tests_failed_o ));
// debug subsystem
dmi_jtag #(
.IdcodeValue ( 32'h249511C3 )
) i_dmi_jtag (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( 1'b0 ),
.dmi_req_o ( jtag_dmi_req ),
.dmi_req_valid_o ( jtag_req_valid ),
.dmi_req_ready_i ( debug_req_ready ),
.dmi_resp_i ( debug_resp ),
.dmi_resp_ready_o ( jtag_resp_ready ),
.dmi_resp_valid_i ( jtag_resp_valid ),
.dmi_rst_no ( ), // not connected
.tck_i ( sim_jtag_tck ),
.tms_i ( sim_jtag_tms ),
.trst_ni ( sim_jtag_trstn ),
.td_i ( sim_jtag_tdi ),
.td_o ( sim_jtag_tdo ),
.tdo_oe_o ( )
);
dm_top #(
.NrHarts ( NrHarts ),
.BusWidth ( 32 ),
.SelectableHarts ( SELECTABLE_HARTS )
) i_dm_top (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( 1'b0 ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session TODO
.debug_req_o ( dm_debug_req ),
.unavailable_i ( ~SELECTABLE_HARTS ),
.hartinfo_i ( HARTINFO ),
.slave_req_i ( dm_req ),
.slave_we_i ( dm_we ),
.slave_addr_i ( dm_addr ),
.slave_be_i ( dm_be ),
.slave_wdata_i ( dm_wdata ),
.slave_rdata_o ( dm_rdata ),
.master_req_o ( sb_req ),
.master_add_o ( sb_addr ),
.master_we_o ( sb_we ),
.master_wdata_o ( sb_wdata ),
.master_be_o ( sb_be ),
.master_gnt_i ( sb_gnt ),
.master_r_valid_i ( sb_rvalid ),
.master_r_rdata_i ( sb_rdata ),
.dmi_rst_ni ( rst_ni ),
.dmi_req_valid_i ( jtag_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( jtag_dmi_req ),
.dmi_resp_valid_o ( jtag_resp_valid ),
.dmi_resp_ready_i ( jtag_resp_ready ),
.dmi_resp_o ( debug_resp )
);
// grant in the same cycle
assign dm_gnt = dm_req;
// valid read/write in the next cycle
always_ff @(posedge clk_i or negedge rst_ni) begin : dm_valid_handler
if(~rst_ni) begin
dm_rvalid <= '0;
end else begin
dm_rvalid <= dm_gnt;
end
end
// reset handling with ndmreset
rstgen i_rstgen_main (
.clk_i ( clk_i ),
.rst_ni ( rst_ni & (~ndmreset) ),
.test_mode_i ( '0 ),
.rst_no ( ndmreset_n ),
.init_no ( ) // keep open
);
// jtag calls from dpi
SimJTAG #(
.TICK_DELAY (1),
.PORT(OPENOCD_PORT)
) i_sim_jtag (
.clock ( clk_i ),
.reset ( ~rst_ni ),
.enable ( sim_jtag_enable ),
.init_done ( rst_ni ),
.jtag_TCK ( sim_jtag_tck ),
.jtag_TMS ( sim_jtag_tms ),
.jtag_TDI ( sim_jtag_tdi ),
.jtag_TRSTn ( sim_jtag_trstn ),
.jtag_TDO_data ( sim_jtag_tdo ),
.jtag_TDO_driven ( 1'b1 ),
.exit ( sim_jtag_exit )
);
always_comb begin : jtag_exit_handler
if (sim_jtag_exit)
$finish(2); // print stats too
end
endmodule // tb_top_verilator
|
# Copyright 2020 ETH Zurich and University of Bologna.
# Copyright and related rights are licensed under the Solderpad Hardware
# License, Version 0.51 (the "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of the License at
# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
# or agreed to in writing, software, hardware and materials distributed under
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
# Author: Robert Balas (balasr@student.ethz.ch)
# Description: TCL scripts to facilitate simulations
set NoQuitOnFinish 1
run -all
|
# Copyright 2019 ETH Zurich and University of Bologna.
# Copyright and related rights are licensed under the Solderpad Hardware
# License, Version 0.51 (the "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of the License at
# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
# or agreed to in writing, software, hardware and materials distributed under
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
# Author: Robert Balas (balasr@student.ethz.ch)
# Description: TCL scripts to facilitate simulations
set NoQuitOnFinish 1
source waves.tcl
run -all
|
# Copyright 2020 ETH Zurich and University of Bologna.
# Copyright and related rights are licensed under the Solderpad Hardware
# License, Version 0.51 (the "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of the License at
# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
# or agreed to in writing, software, hardware and materials distributed under
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
# Author: Robert Balas (balasr@iis.ee.ethz.ch)
# Description: TCL scripts to facilitate simulations
# catch {
# if {$trdb_all ne ""} {
# foreach inst $trdb_all {
# add wave -group [file tail $inst] $inst/*
# }
# }
# } err
# if {$err ne ""} {
# puts "\[TCL\]: Suppressed error: $err"
# }
# add fc
set rvcores [find instances -recursive -bydu cv32e40p_core -nodu]
set tb_top [find instances -recursive -bydu tb_top -nod]
set mm_ram [find instances -recursive -bydu mm_ram -nod]
set dp_ram [find instances -recursive -bydu dp_ram -nod]
if {$tb_top ne ""} {
foreach inst $tb_top {
add wave -group [file tail $inst] $inst/*
}
}
if {$mm_ram ne ""} {
foreach inst $mm_ram {
add wave -group [file tail $inst] $inst/*
}
}
if {$dp_ram ne ""} {
foreach inst $dp_ram {
add wave -group [file tail $inst] $inst/*
}
}
if {$rvcores ne ""} {
add wave -group "Core" $rvcores/*
add wave -group "IF Stage" -group "Prefetch" $rvcores/if_stage_i/prefetch_buffer_i/*
add wave -group "IF Stage" -group "Prefetch" -group "FIFO" $rvcores/if_stage_i/prefetch_buffer_i/fifo_i/*
add wave -group "IF Stage" -group "Prefetch" -group "OBI" $rvcores/if_stage_i/prefetch_buffer_i/instruction_obi_i/*
add wave -group "IF Stage" $rvcores/if_stage_i/*
add wave -group "Aligner" $rvcores/if_stage_i/aligner_i/*
add wave -group "RVCDecoder" $rvcores/if_stage_i/compressed_decoder_i/*
add wave -group "ID Stage" $rvcores/id_stage_i/*
add wave -group "RF" $rvcores/id_stage_i/register_file_i/mem
add wave -group "RF_FP" $rvcores/id_stage_i/register_file_i/mem_fp
add wave -group "Decoder" $rvcores/id_stage_i/decoder_i/*
add wave -group "Controller" $rvcores/id_stage_i/controller_i/*
add wave -group "Int Ctrl" $rvcores/id_stage_i/int_controller_i/*
add wave -group "EX Stage" -group "ALU" $rvcores/ex_stage_i/alu_i/*
add wave -group "EX Stage" -group "ALU_DIV" $rvcores/ex_stage_i/alu_i/alu_div_i/*
add wave -group "EX Stage" -group "MUL" $rvcores/ex_stage_i/mult_i/*
add wave -group "EX Stage" $rvcores/ex_stage_i/*
add wave -group "LSU" $rvcores/load_store_unit_i/*
add wave -group "CSR" $rvcores/cs_registers_i/*
}
# add dm
set dm [find instances -recursive -bydu dm_top -nodu]
set dm_mem [find instances -recursive -bydu dm_mem -nodu]
set dm_csrs [find instances -recursive -bydu dm_csrs -nodu]
set dm_sba [find instances -recursive -bydu dm_sba -nodu]
if {$dm ne ""} {
add wave -group "DM" $dm/*
}
if {$dm_mem ne ""} {
add wave -group "DM" -group "dm_mem" $dm_mem/*
}
if {$dm_csrs ne ""} {
add wave -group "DM" -group "dm_csrs" $dm_csrs/*
}
if {$dm_sba ne ""} {
add wave -group "DM" -group "dm_sba" $dm_sba/*
}
# add dmi_jtag
set dmi [find instances -recursive -bydu dmi_jtag -nodu]
set dmi_tap [find instances -recursive -bydu dmi_jtag_tap -nodu]
if {$dmi ne ""} {
add wave -group "DMI" $dmi/*
}
if {$dmi_tap ne ""} {
add wave -group "DMI" -group "dmi_tap" $dmi_tap/*
}
configure wave -namecolwidth 250
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -timelineunits ns
|
/* Copyright (c) 2017 SiFive Inc. All rights reserved.
* Copyright (c) 2019 ETH Z眉rich and University of Bologna
* This copyrighted material is made available to anyone wishing to use,
* modify, copy, or redistribute it subject to the terms and conditions
* of the FreeBSD License. This program is distributed in the hope that
* it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
* including the implied warranties of MERCHANTABILITY or FITNESS FOR
* A PARTICULAR PURPOSE. A copy of this license is available at
* http://www.opensource.org/licenses.
*/
/* Entry point for bare metal programs */
.section .text.start
.global _start
.type _start, @function
_start:
/* initialize global pointer */
.option push
.option norelax
1: auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b)
.option pop
/* initialize stack pointer */
la sp, _sp
/* set vector table address */
la a0, __vector_start
csrw mtvec, a0
/* set vector table address for CLINTx */
la a0, __vector_x_start
csrw 0x307, a0
/* clear the bss segment */
la a0, __bss_start
la a2, __bss_end
sub a2, a2, a0
li a1, 0
call memset
/* new-style constructors and destructors */
la a0, __libc_fini_array
call atexit
call __libc_init_array
/* call main */
lw a0, 0(sp) /* a0 = argc */
addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
li a2, 0 /* a2 = envp = NULL */
call main
tail exit
.size _start, .-_start
.global _init
.type _init, @function
.global _fini
.type _fini, @function
_init:
_fini:
/* These don't have to do anything since we use init_array/fini_array. Prevent
missing symbol error */
ret
.size _init, .-_init
.size _fini, .-_fini
|
/* Script for -z combreloc: combine and sort reloc sections */
/* Copyright (C) 2014-2018 Free Software Foundation, Inc.
Copyright (C) 2019 ETH Z眉rich and University of Bologna
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */
/* This linker script is derived from the default linker script of the RISC-V
gcc compiler. We have made a few changes to make it suitable for linking bare
metal programs. These are mostly removing dynamic linking related sections and
putting sections into our memory regions. */
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
"elf32-littleriscv")
OUTPUT_ARCH(riscv)
ENTRY(_start)
MEMORY
{
/* the memory in the testbench is 1024k in size;
* set LENGTH=1008k and leave at least 16k for stack */
ram (rwxai) : ORIGIN = 0x1c000000, LENGTH = 0x000fc000
}
SECTIONS
{
/* we want a fixed entry point */
PROVIDE(__boot_address = ORIGIN(ram) + 0x180);
/* stack and heap related settings */
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS;
/* We don't do any dynamic linking so we remove everything related to it */
/*
.interp : { *(.interp) }
.note.gnu.build-id : { *(.note.gnu.build-id) }
.hash : { *(.hash) }
.gnu.hash : { *(.gnu.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
PROVIDE_HIDDEN (__rela_iplt_start = .);
*(.rela.iplt)
PROVIDE_HIDDEN (__rela_iplt_end = .);
}
.rela.plt :
{
*(.rela.plt)
}
*/
/* interrupt vectors */
.vectors (ORIGIN(ram)):
{
PROVIDE(__vector_start = .);
KEEP(*(.vectors));
} >ram
/* interrupt vectors x*/
.vectors_x (ORIGIN(ram) + 0x100):
{
PROVIDE(__vector_x_start = .);
KEEP(*(.vectors_x));
} >ram
/* crt0 init code */
.init (__boot_address):
{
KEEP (*(SORT_NONE(.init)))
KEEP (*(.text.start))
} >ram
/* More dynamic linking sections */
/*
.plt : { *(.plt) }
.iplt : { *(.iplt) }
*/
/* the bulk of the program: main, libc, functions etc. */
.text :
{
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >ram
/* not used by RISC-V*/
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >ram
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
/* read-only sections */
.rodata :
{
*(.rodata .rodata.* .gnu.linkonce.r.*)
} >ram
.rodata1 :
{
*(.rodata1)
} >ram
/* second level sbss and sdata, I don't think we need this */
/* .sdata2 : {*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)} */
/* .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } */
/* gcc language agnostic exception related sections (try-catch-finally) */
.eh_frame_hdr :
{
*(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*)
} >ram
.eh_frame : ONLY_IF_RO
{
KEEP (*(.eh_frame)) *(.eh_frame.*)
} >ram
.gcc_except_table : ONLY_IF_RO
{
*(.gcc_except_table .gcc_except_table.*)
} >ram
.gnu_extab : ONLY_IF_RO
{
*(.gnu_extab*)
} >ram
/* These sections are generated by the Sun/Oracle C++ compiler. */
/*
.exception_ranges : ONLY_IF_RO { *(.exception_ranges
.exception_ranges*) }
*/
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
/* Exception handling */
.eh_frame : ONLY_IF_RW
{
KEEP (*(.eh_frame)) *(.eh_frame.*)
} >ram
.gnu_extab : ONLY_IF_RW
{
*(.gnu_extab)
} >ram
.gcc_except_table : ONLY_IF_RW
{
*(.gcc_except_table .gcc_except_table.*)
} >ram
.exception_ranges : ONLY_IF_RW
{
*(.exception_ranges .exception_ranges*)
} >ram
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >ram
.tbss :
{
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
} >ram
/* initialization and termination routines */
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >ram
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >ram
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >ram
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >ram
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >ram
/* .jcr : { KEEP (*(.jcr)) } */
/* .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } */
/* .dynamic : { *(.dynamic) } */
. = DATA_SEGMENT_RELRO_END (0, .);
/* data sections for initalized data */
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.* .gnu.linkonce.d.*)
SORT(CONSTRUCTORS)
} >ram
.data1 :
{
*(.data1)
} > ram
/* no dynamic linking, no object tables required */
/* .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } */
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata :
{
__SDATA_BEGIN__ = .;
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
} >ram
_edata = .; PROVIDE (edata = .);
. = .;
/* zero initialized sections */
__bss_start = .;
.sbss :
{
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
} >ram
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections.
FIXME: Why do we need it? When there is no .bss section, we don't
pad the .data section. */
. = ALIGN(. != 0 ? 32 / 8 : 1);
} >ram
. = ALIGN(32 / 8);
. = SEGMENT_START("ldata-segment", .);
. = ALIGN(32 / 8);
__BSS_END__ = .;
__bss_end = .;
/* The compiler uses this to access data in the .sdata, .data, .sbss and .bss
sections with fewer instructions (relaxation). This reduces code size. */
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
_end = .; PROVIDE (end = .);
. = DATA_SEGMENT_END (.);
/* heap: we should consider putting this to the bottom of the address space */
.heap :
{
PROVIDE(__heap_start = .);
. = __heap_size;
PROVIDE(__heap_end = .);
} >ram
/* stack: we should consider putting this further to the top of the address
space */
.stack : ALIGN(16) /* this is a requirement of the ABI(?) */
{
PROVIDE(__stack_start = .);
. = __stack_size;
PROVIDE(_sp = .);
PROVIDE(__stack_end = .);
} >ram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}
|
/* An extremely minimalist syscalls.c for newlib
* Based on riscv newlib libgloss/riscv/sys_*.c
*
* Copyright 2019 Clifford Wolf
* Copyright 2019 ETH Z眉rich and University of Bologna
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/stat.h>
#include <newlib.h>
#include <unistd.h>
#include <errno.h>
#undef errno
extern int errno;
/* write to this reg for outputting strings */
#define STDOUT_REG 0x10000000
/* write test result of program to this reg */
#define RESULT_REG 0x20000000
/* write exit value of program to this reg */
#define EXIT_REG 0x20000004
#define STDOUT_FILENO 1
/* It turns out that older newlib versions use different symbol names which goes
* against newlib recommendations. Anyway this is fixed in later version.
*/
#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5
# define _sbrk sbrk
# define _write write
# define _close close
# define _lseek lseek
# define _read read
# define _fstat fstat
# define _isatty isatty
#endif
void unimplemented_syscall()
{
const char *p = "Unimplemented system call called!\n";
while (*p)
*(volatile int *)STDOUT_REG = *(p++);
}
int nanosleep(const struct timespec *rqtp, struct timespec *rmtp)
{
errno = ENOSYS;
return -1;
}
int _access(const char *file, int mode)
{
errno = ENOSYS;
return -1;
}
int _chdir(const char *path)
{
errno = ENOSYS;
return -1;
}
int _chmod(const char *path, mode_t mode)
{
errno = ENOSYS;
return -1;
}
int _chown(const char *path, uid_t owner, gid_t group)
{
errno = ENOSYS;
return -1;
}
int _close(int file)
{
return -1;
}
int _execve(const char *name, char *const argv[], char *const env[])
{
errno = ENOMEM;
return -1;
}
void _exit(int exit_status)
{
*(volatile int *)EXIT_REG = exit_status;
asm volatile("wfi");
}
int _faccessat(int dirfd, const char *file, int mode, int flags)
{
errno = ENOSYS;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
// errno = -ENOSYS;
// return -1;
}
int _fstatat(int dirfd, const char *file, struct stat *st, int flags)
{
errno = ENOSYS;
return -1;
}
int _ftime(struct timeb *tp)
{
errno = ENOSYS;
return -1;
}
char *_getcwd(char *buf, size_t size)
{
errno = -ENOSYS;
return NULL;
}
int _getpid()
{
return 1;
}
int _gettimeofday(struct timeval *tp, void *tzp)
{
errno = -ENOSYS;
return -1;
}
int _isatty(int file)
{
return (file == STDOUT_FILENO);
}
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
}
int _link(const char *old_name, const char *new_name)
{
errno = EMLINK;
return -1;
}
off_t _lseek(int file, off_t ptr, int dir)
{
return 0;
}
int _lstat(const char *file, struct stat *st)
{
errno = ENOSYS;
return -1;
}
int _open(const char *name, int flags, int mode)
{
return -1;
}
int _openat(int dirfd, const char *name, int flags, int mode)
{
errno = ENOSYS;
return -1;
}
ssize_t _read(int file, void *ptr, size_t len)
{
return 0;
}
int _stat(const char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
// errno = ENOSYS;
// return -1;
}
long _sysconf(int name)
{
return -1;
}
clock_t _times(struct tms *buf)
{
return -1;
}
int _unlink(const char *name)
{
errno = ENOENT;
return -1;
}
int _utime(const char *path, const struct utimbuf *times)
{
errno = ENOSYS;
return -1;
}
int _wait(int *status)
{
errno = ECHILD;
return -1;
}
ssize_t _write(int file, const void *ptr, size_t len)
{
if (file != STDOUT_FILENO) {
errno = ENOSYS;
return -1;
}
const void *eptr = ptr + len;
while (ptr != eptr)
*(volatile int *)STDOUT_REG = *(char *)(ptr++);
return len;
}
extern char __heap_start[];
extern char __heap_end[];
static char *brk = __heap_start;
int _brk(void *addr)
{
brk = addr;
return 0;
}
void *_sbrk(ptrdiff_t incr)
{
char *old_brk = brk;
if (__heap_start == __heap_end) {
return NULL;
}
if ((brk += incr) < __heap_end) {
brk += incr;
} else {
brk = __heap_end;
}
return old_brk;
}
|
#include <stdio.h>
int main(){
printf("hello world!\n");
return 0;
}
|
/*
* Copyright 2019 ETH Z眉rich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.section .vectors, "ax"
.option norvc
vector_table:
j sw_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j verification_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
j __no_irq_handler
/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
new vector table (which is at mtvec) */
/* .section .legacy_irq, "ax" */
/* j vector_table */
/* j __no_irq_handler */
/* j __no_irq_handler */
/* j __no_irq_handler */
.section .text.vecs
/* exception handling */
__no_irq_handler:
la a0, no_exception_handler_msg
jal ra, puts
j __no_irq_handler
sw_irq_handler:
csrr t0, mcause
slli t0, t0, 1 /* shift off the high bit */
srli t0, t0, 1
li t1, 2
beq t0, t1, handle_illegal_insn
li t1, 11
beq t0, t1, handle_ecall
li t1, 3
beq t0, t1, handle_ebreak
j handle_unknown
handle_ecall:
la a0, ecall_msg
jal ra, puts
j end_handler
handle_ebreak:
la a0, ebreak_msg
jal ra, puts
j end_handler
handle_illegal_insn:
la a0, illegal_insn_msg
jal ra, puts
j end_handler
handle_unknown:
la a0, unknown_msg
jal ra, puts
j end_handler
end_handler:
csrr a0, mepc
addi a0, a0, 4
csrw mepc, a0
mret
/* this interrupt can be generated for verification purposes, random or when the PC is equal to a given value*/
verification_irq_handler:
mret
.section .rodata
illegal_insn_msg:
.string "illegal instruction exception handler entered\n"
ecall_msg:
.string "ecall exception handler entered\n"
ebreak_msg:
.string "ebreak exception handler entered\n"
unknown_msg:
.string "unknown exception handler entered\n"
no_exception_handler_msg:
.string "no exception handler installed\n"
|
*.o
*.d
*.so |
# Copyright (C) 2020 ETH Zurich and University of Bologna
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
#
# Author: Robert Balas (balasr@iis.ee.ethz.ch)
CFLAGS = -Wall -Wextra -Wno-missing-field-initializers \
-Wno-unused-function -Wno-missing-braces \
-O2 -g -march=native \
-DENABLE_LOGGING -DNDEBUG
CFLAGS_DBG =
# we need gnu11 and no-strict-aliasing
ALL_CFLAGS = -std=gnu11 -fno-strict-aliasing $(CFLAGS)
ALL_CFLAGS_DBG = -std=gnu11 -Wall -Wextra -Wno-missing-field-initializers \
-Wno-unused-function -Wno-missing-braces \
-O0 -g -fno-strict-aliasing \
-fsanitize=address -fno-omit-frame-pointer \
-DENABLE_LOGGING -DENABLE_DEBUG $(CFLAGS_DBG)\
# -fsanitize=undefined \
# -fsanitize=leak \
# TODO: better path?
LIB_DIRS =
LIBS =
INCLUDE_DIRS = ./
LDFLAGS = $(addprefix -L, $(LIB_DIRS))
LDLIBS = $(addprefix -l, $(LIBS))
SRCS = remote_bitbang.c sim_jtag.c
OBJS = $(SRCS:.c=.o)
INCLUDES = $(addprefix -I, $(INCLUDE_DIRS))
HEADERS = $(wildcard *.h)
# libs
SV_LIB = librbs.so
# header file dependency generation
DEPDIR := .d
DEPDIRS := $(addsuffix /$(DEPDIR),.)
# goal: make gcc put a dependency file called obj.Td (derived from subdir/obj.o)
# in subdir/.d/
DEPFLAGS = -MT $@ -MMD -MP -MF $(@D)/$(DEPDIR)/$(patsubst %.o,%.Td,$(@F))
# move gcc generated header dependencies to DEPDIR
# this rename step is here to make the header dependency generation "atomic"
POSTCOMPILE = @mv -f $(@D)/$(DEPDIR)/$(patsubst %.o,%.Td,$(@F)) \
$(@D)/$(DEPDIR)/$(patsubst %.o,%.d,$(@F)) && touch $@
# GNU recommendations for install targets
prefix = /usr/local
exec_prefix = $(prefix)
bindir = $(exec_prefix)/bin
libdir = $(exec_prefix)/lib
includedir = $(prefix)/include
INSTALL = install
INSTALL_PROGRAM = $(INSTALL)
INSTALL_DATA = ${INSTALL} -m 644
CTAGS = ctags
# compilation targets
all: sv-lib
debug: ALL_CFLAGS = $(ALL_CFLAGS_DBG)
debug: all
sv-lib: ALL_CFLAGS += -fPIC
sv-lib: $(SV_LIB)
#compilation boilerplate
$(SV_LIB): $(OBJS)
$(LD) -shared -E --exclude-libs ALL -o $(SV_LIB) $(LDFLAGS) \
$(OBJS) $(LDLIBS)
# $@ = name of target
# $< = first dependency
%.o: %.c
%.o: %.c $(DEPDIR)/%.d $(DEPDIRS)
$(CC) $(DEPFLAGS) $(ALL_CFLAGS) $(INCLUDES) $(LDFLAGS) \
-c $(CPPFLAGS) $< -o $@ $(LDLIBS)
$(POSTCOMPILE)
# check if we need to create the dependencies folders (gcc doesn't)
$(DEPDIRS):
$(shell mkdir -p $(DEPDIRS) > /dev/null)
# make won't fail if the dependency file doesn't exist
$(addsuffix /$(DEPDIR)/%.d,. main benchmark test dpi): ;
# prevent automatic deletion as intermediate file
.PRECIOUS: $(addsuffix /$(DEPDIR)/%.d,. main benchmark test dpi)
# emacs tag generation
.PHONY: TAGS
TAGS:
$(CTAGS) -R -e -h=".c.h" --tag-relative=always \
. $(LIB_DIRS) $(INCLUDE_DIRS) $(BINUTILS_PATH)/bfd
# TODO: missing install targets
# cleanup
.PHONY: clean
clean:
rm -rf $(SV_LIB) $(OBJS) $(DEPDIRS)
.PHONY: distclean
distclean: clean
rm -f TAGS
# include auto generated header dependency information
include $(wildcard $(addsuffix /*.d,$(DEPDIRS)))
|
/* Copyright (C) 2020 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include <stdio.h>
#include "remote_bitbang.h"
int main()
{
unsigned char jtag_TCK, jtag_TMS, jtag_TDI, jtag_TRSTn;
unsigned char jtag_TDO = 0;
printf("calling rbs_init\n");
int v = rbs_init(0);
printf("tick 1\n");
rbs_tick(&jtag_TCK, &jtag_TMS, &jtag_TDI, &jtag_TRSTn, jtag_TDO);
printf("jtag exit is %d\n", rbs_done());
return 0;
}
|
// See LICENSE.Berkeley for license details.
#include <arpa/inet.h>
#include <errno.h>
#include <fcntl.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <assert.h>
#include <stdio.h>
#include <stdlib.h>
#include "remote_bitbang.h"
int rbs_init(uint16_t port)
{
socket_fd = 0;
client_fd = 0;
recv_start = 0;
recv_end = 0;
rbs_err = 0;
socket_fd = socket(AF_INET, SOCK_STREAM, 0);
if (socket_fd == -1) {
fprintf(stderr, "remote_bitbang failed to make socket: %s (%d)\n",
strerror(errno), errno);
abort();
}
fcntl(socket_fd, F_SETFL, O_NONBLOCK);
int reuseaddr = 1;
if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
sizeof(int)) == -1) {
fprintf(stderr, "remote_bitbang failed setsockopt: %s (%d)\n",
strerror(errno), errno);
abort();
}
struct sockaddr_in addr;
memset(&addr, 0, sizeof(addr));
addr.sin_family = AF_INET;
addr.sin_addr.s_addr = INADDR_ANY;
addr.sin_port = htons(port);
if (bind(socket_fd, (struct sockaddr *)&addr, sizeof(addr)) == -1) {
fprintf(stderr, "remote_bitbang failed to bind socket: %s (%d)\n",
strerror(errno), errno);
abort();
}
if (listen(socket_fd, 1) == -1) {
fprintf(stderr, "remote_bitbang failed to listen on socket: %s (%d)\n",
strerror(errno), errno);
abort();
}
socklen_t addrlen = sizeof(addr);
if (getsockname(socket_fd, (struct sockaddr *)&addr, &addrlen) == -1) {
fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n",
strerror(errno), errno);
abort();
}
tck = 1;
tms = 1;
tdi = 1;
trstn = 1;
quit = 0;
fprintf(stderr, "JTAG remote bitbang server is ready\n");
fprintf(stderr, "Listening on port %d\n", ntohs(addr.sin_port));
return 1;
}
void rbs_accept()
{
fprintf(stderr, "Attempting to accept client socket\n");
int again = 1;
while (again != 0) {
client_fd = accept(socket_fd, NULL, NULL);
if (client_fd == -1) {
if (errno == EAGAIN) {
// No client waiting to connect right now.
} else {
fprintf(stderr, "failed to accept on socket: %s (%d)\n",
strerror(errno), errno);
again = 0;
abort();
}
} else {
fcntl(client_fd, F_SETFL, O_NONBLOCK);
fprintf(stderr, "Accepted successfully.");
again = 0;
}
}
}
void rbs_tick(unsigned char *jtag_tck, unsigned char *jtag_tms,
unsigned char *jtag_tdi, unsigned char *jtag_trstn,
unsigned char jtag_tdo)
{
if (client_fd > 0) {
tdo = jtag_tdo;
rbs_execute_command();
} else {
rbs_accept();
}
*jtag_tck = tck;
*jtag_tms = tms;
*jtag_tdi = tdi;
*jtag_trstn = trstn;
}
void rbs_reset()
{
// trstn = 0;
}
void rbs_set_pins(char _tck, char _tms, char _tdi)
{
tck = _tck;
tms = _tms;
tdi = _tdi;
}
void rbs_execute_command()
{
char command;
int again = 1;
while (again) {
ssize_t num_read = read(client_fd, &command, sizeof(command));
if (num_read == -1) {
if (errno == EAGAIN) {
// We'll try again the next call.
if (VERBOSE)
fprintf(
stderr,
"Received no command. Will try again on the next call\n");
} else {
fprintf(stderr,
"remote_bitbang failed to read on socket: %s (%d)\n",
strerror(errno), errno);
again = 0;
abort();
}
} else if (num_read == 0) {
fprintf(stderr, "No command received. Stopping further reads.\n");
// again = 1;
return;
} else {
again = 0;
}
}
int dosend = 0;
char tosend = '?';
switch (command) {
case 'B':
if (VERBOSE)
fprintf(stderr, "*BLINK*\n");
break;
case 'b':
if (VERBOSE)
fprintf(stderr, "blink off\n");
break;
case 'r':
if (VERBOSE)
fprintf(stderr, "r-reset\n");
rbs_reset();
break; // This is wrong. 'r' has other bits that indicated TRST and
// SRST.
case 's':
if (VERBOSE)
fprintf(stderr, "s-reset\n");
rbs_reset();
break; // This is wrong.
case 't':
if (VERBOSE)
fprintf(stderr, "t-reset\n");
rbs_reset();
break; // This is wrong.
case 'u':
if (VERBOSE)
fprintf(stderr, "u-reset\n");
rbs_reset();
break; // This is wrong.
case '0':
if (VERBOSE)
fprintf(stderr, "Write 0 0 0\n");
rbs_set_pins(0, 0, 0);
break;
case '1':
if (VERBOSE)
fprintf(stderr, "Write 0 0 1\n");
rbs_set_pins(0, 0, 1);
break;
case '2':
if (VERBOSE)
fprintf(stderr, "Write 0 1 0\n");
rbs_set_pins(0, 1, 0);
break;
case '3':
if (VERBOSE)
fprintf(stderr, "Write 0 1 1\n");
rbs_set_pins(0, 1, 1);
break;
case '4':
if (VERBOSE)
fprintf(stderr, "Write 1 0 0\n");
rbs_set_pins(1, 0, 0);
break;
case '5':
if (VERBOSE)
fprintf(stderr, "Write 1 0 1\n");
rbs_set_pins(1, 0, 1);
break;
case '6':
if (VERBOSE)
fprintf(stderr, "Write 1 1 0\n");
rbs_set_pins(1, 1, 0);
break;
case '7':
if (VERBOSE)
fprintf(stderr, "Write 1 1 1\n");
rbs_set_pins(1, 1, 1);
break;
case 'R':
if (VERBOSE)
fprintf(stderr, "Read req\n");
dosend = 1;
tosend = tdo ? '1' : '0';
break;
case 'Q':
if (VERBOSE)
fprintf(stderr, "Quit req\n");
quit = 1;
break;
default:
fprintf(stderr, "remote_bitbang got unsupported command '%c'\n",
command);
}
if (dosend) {
while (1) {
ssize_t bytes = write(client_fd, &tosend, sizeof(tosend));
if (bytes == -1) {
fprintf(stderr, "failed to write to socket: %s (%d)\n",
strerror(errno), errno);
abort();
}
if (bytes > 0) {
break;
}
}
}
if (quit) {
fprintf(stderr, "Remote end disconnected\n");
close(client_fd);
client_fd = 0;
}
}
unsigned char rbs_done()
{
return quit;
}
int rbs_exit_code()
{
return rbs_err;
}
|
// See LICENSE.Berkeley for license details.
#ifndef REMOTE_BITBANG_H
#define REMOTE_BITBANG_H
#include <stdint.h>
#include <sys/types.h>
#define VERBOSE 0
int rbs_err;
unsigned char tck;
unsigned char tms;
unsigned char tdi;
unsigned char trstn;
unsigned char tdo;
unsigned char quit;
int socket_fd;
int client_fd;
static const ssize_t buf_size = 64 * 1024;
char recv_buf[64 * 1024];
ssize_t recv_start, recv_end;
// Create a new server, listening for connections from localhost on the given
// port.
int rbs_init(uint16_t port);
// Do a bit of work.
void rbs_tick(unsigned char *jtag_tck, unsigned char *jtag_tms,
unsigned char *jtag_tdi, unsigned char *jtag_trstn,
unsigned char jtag_tdo);
unsigned char rbs_done();
int rbs_exit_code();
// Check for a client connecting, and accept if there is one.
void rbs_accept();
// Execute any commands the client has for us.
// But we only execute 1 because we need time for the
// simulation to run.
void rbs_execute_command();
// Reset. Currently does nothing.
void rbs_reset();
void rbs_set_pins(char _tck, char _tms, char _tdi);
#endif
|
// See LICENSE.SiFive for license details.
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include "remote_bitbang.h"
int init = 0;
int jtag_tick(int port, unsigned char *jtag_TCK, unsigned char *jtag_TMS,
unsigned char *jtag_TDI, unsigned char *jtag_TRSTn,
unsigned char jtag_TDO)
{
if (!init) {
if (port < 0 || port > UINT16_MAX)
fprintf(stderr, "Port number of out range: %d\n", port);
init = rbs_init(port);
}
rbs_tick(jtag_TCK, jtag_TMS, jtag_TDI, jtag_TRSTn, jtag_TDO);
if (VERBOSE)
fprintf(
stderr,
"Tick with: TCK=%hhd TMS=%hhd TDI=%hhd TRSTn=%hhd --> TDO=%hhd\n",
*jtag_TCK, *jtag_TMS, *jtag_TDI, *jtag_TRSTn, jtag_TDO);
return rbs_done() ? (rbs_exit_code() << 1 | 1) : 0;
}
|
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
import "DPI-C" function int debug_tick
(
output bit debug_req_valid,
input bit debug_req_ready,
output int debug_req_bits_addr,
output int debug_req_bits_op,
output int debug_req_bits_data,
input bit debug_resp_valid,
output bit debug_resp_ready,
input int debug_resp_bits_resp,
input int debug_resp_bits_data
);
module SimDTM(
input clk,
input reset,
output debug_req_valid,
input debug_req_ready,
output [ 6:0] debug_req_bits_addr,
output [ 1:0] debug_req_bits_op,
output [31:0] debug_req_bits_data,
input debug_resp_valid,
output debug_resp_ready,
input [ 1:0] debug_resp_bits_resp,
input [31:0] debug_resp_bits_data,
output [31:0] exit
);
bit r_reset;
wire #0.1 __debug_req_ready = debug_req_ready;
wire #0.1 __debug_resp_valid = debug_resp_valid;
wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
bit __debug_req_valid;
int __debug_req_bits_addr;
int __debug_req_bits_op;
int __debug_req_bits_data;
bit __debug_resp_ready;
int __exit;
assign #0.1 debug_req_valid = __debug_req_valid;
assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
assign #0.1 debug_resp_ready = __debug_resp_ready;
assign #0.1 exit = __exit;
always @(posedge clk)
begin
r_reset <= reset;
if (reset || r_reset)
begin
__debug_req_valid = 0;
__debug_resp_ready = 0;
__exit = 0;
end
else
begin
__exit = debug_tick(
__debug_req_valid,
__debug_req_ready,
__debug_req_bits_addr,
__debug_req_bits_op,
__debug_req_bits_data,
__debug_resp_valid,
__debug_resp_ready,
__debug_resp_bits_resp,
__debug_resp_bits_data
);
end
end
endmodule
|
gitdir: ../../.git/modules/corev_apu/rv_plic
|
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|
# RISC-V Platform-Level Interrupt Controller
RV_PLIC module is to manage multiple interrupt events generated from the
peripherals. It implements [Platform-Level Interrupt Controller in RISC-V
Privileges specification Section
7](https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.pdf#page=73).
## `reg_rv_plic.py`
The tool is to create register hjson file given values of number of sources,
number of targets, and max value of priority. By default `target` is **1** and
`priority` is **7** (8 level of priorities supported)
To change the value and to re-create hjson,
$ reg_rv_plic.py -s 64 -t 2 -p 15 rv_plic_reg.tpl.hjson > rv_plic_reg.hjson
|
#!/usr/bin/env python3
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
r"""Mako template to hjson register description
"""
import sys
import argparse
from io import StringIO
from mako.template import Template
def main():
parser = argparse.ArgumentParser(prog="reg_rv_plic")
parser.add_argument('input', nargs='?', metavar='file',
type=argparse.FileType('r'),
default=sys.stdin,
help='input template file')
parser.add_argument('--sources', '-s', type=int,
help='Number of Interrupt Sources')
parser.add_argument('--targets', '-t', type=int,
default=1,
help='Number of Interrupt Targets')
parser.add_argument('--priority', '-p', type=int,
default=7,
help='Max value of interrupt priorities')
args = parser.parse_args()
# Determine output: if stdin then stdout if not then ??
out = StringIO()
reg_tpl = Template(args.input.read())
out.write(reg_tpl.render(src=args.sources,
target=args.targets,
prio=args.priority))
print(out.getvalue())
out.close()
if __name__ == "__main__":
main()
|
# RV_PLIC register template
#
# Parameter (given by python tool)
# - src: Number of Interrupt Sources
# - target: Number of Targets that handle interrupt requests
# - prio: Max value of interrupt priorities
{
name: "RV_PLIC",
clock_primary: "clk_fixed",
bus_device: "tlul",
regwidth: "32",
"registers": [
{ multireg: {
name: "IP",
desc: "Interrupt Pending",
count: 32,
cname: "RV_PLIC",
swaccess: "ro",
hwaccess: "hwo",
fields: [
{ bits: "0", name: "P", desc: "Interrupt Pending of Source" }
],
}
},
{ multireg: {
name: "LE",
desc: "Interrupt Source mode. 0: Level, 1: Edge-triggered",
count: 32,
cname: "RV_PLIC",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "0", name: "LE", desc: "L0E1" }
],
}
},
{ name: "PRIO0",
desc: "Interrupt Source 0 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO1",
desc: "Interrupt Source 1 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO2",
desc: "Interrupt Source 2 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO3",
desc: "Interrupt Source 3 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO4",
desc: "Interrupt Source 4 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO5",
desc: "Interrupt Source 5 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO6",
desc: "Interrupt Source 6 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO7",
desc: "Interrupt Source 7 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO8",
desc: "Interrupt Source 8 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO9",
desc: "Interrupt Source 9 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO10",
desc: "Interrupt Source 10 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO11",
desc: "Interrupt Source 11 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO12",
desc: "Interrupt Source 12 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO13",
desc: "Interrupt Source 13 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO14",
desc: "Interrupt Source 14 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO15",
desc: "Interrupt Source 15 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO16",
desc: "Interrupt Source 16 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO17",
desc: "Interrupt Source 17 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO18",
desc: "Interrupt Source 18 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO19",
desc: "Interrupt Source 19 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO20",
desc: "Interrupt Source 20 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO21",
desc: "Interrupt Source 21 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO22",
desc: "Interrupt Source 22 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO23",
desc: "Interrupt Source 23 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO24",
desc: "Interrupt Source 24 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO25",
desc: "Interrupt Source 25 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO26",
desc: "Interrupt Source 26 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO27",
desc: "Interrupt Source 27 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO28",
desc: "Interrupt Source 28 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO29",
desc: "Interrupt Source 29 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO30",
desc: "Interrupt Source 30 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "PRIO31",
desc: "Interrupt Source 31 Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ multireg: {
name: "IE0",
desc: "Interrupt Enable for Target 0",
count: 32,
cname: "RV_PLIC",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "0", name: "E", desc: "Interrupt Enable of Source" }
],
}
}
{ name: "THRESHOLD0",
desc: "Threshold of priority for Target 0",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "2:0" }
],
}
{ name: "CC0",
desc: "Claim by read, complete by write for Target 0",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
hwre: "true",
fields: [
{ bits: "5:0" }
],
}
],
}
|
# RV_PLIC register template
#
# Parameter (given by python tool)
# - src: Number of Interrupt Sources
# - target: Number of Targets that handle interrupt requests
# - prio: Max value of interrupt priorities
{
name: "RV_PLIC",
clock_primary: "clk_fixed",
bus_device: "tlul",
regwidth: "32",
registers: [
{ multireg: {
name: "IP",
desc: "Interrupt Pending",
count: ${src},
cname: "RV_PLIC",
swaccess: "ro",
hwaccess: "hwo",
fields: [
{ bits: "0", name: "P", desc: "Interrupt Pending of Source" }
],
}
},
{ multireg: {
name: "LE",
desc: "Interrupt Source mode. 0: Level, 1: Edge-triggered",
count: ${src},
cname: "RV_PLIC",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "0", name: "LE", desc: "L0E1" }
],
}
},
% for i in range(src):
{ name: "PRIO${i}",
desc: "Interrupt Source ${i} Priority",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "${(prio).bit_length()-1}:0" }
],
}
% endfor
% for i in range(target):
{ multireg: {
name: "IE${i}",
desc: "Interrupt Enable for Target ${i}",
count: ${src},
cname: "RV_PLIC",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "0", name: "E", desc: "Interrupt Enable of Source" }
],
}
}
% endfor
% for i in range(target):
{ name: "THRESHOLD${i}",
desc: "Threshold of priority for Target ${i}",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "${(prio).bit_length()-1}:0" }
],
}
% endfor
% for i in range(target):
{ name: "CC${i}",
desc: "Claim by read, complete by write for Target ${i}",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
hwre: "true",
fields: [
{ bits: "${(src).bit_length()-1}:0" }
],
}
% endfor
],
}
|
#!/usr/bin/env python3
# Copyright 2019 ETH Zurich and University of Bologna.
# SPDX-License-Identifier: Apache-2.0
import argparse
from enum import Enum
from math import ceil, log
MAX_DEVICES = 1023
def clog2(x):
return ceil(log(x, 2))
class Access(Enum):
RO = 1
RW = 2
class AddrMapEntry(object):
"""Represents an Entry in an Address Map"""
def __init__(self, addr, name, description, access, width):
super(AddrMapEntry, self).__init__()
self.addr = addr
self.description = description
self.access = access
self.width = width
self.name = name
def __str__(self):
return '{} | {} | {} | {}'.format(hex(self.addr), self.width, self.access, self.description)
def get_list_elem(self):
return [hex(self.addr), self.width, self.access, self.description]
class AddrMap:
def __init__(self, name, description, access_width=32):
self.access_width = access_width
self.name = name
self.description = description
self.addrmap = []
self.ports = []
def addEntries(self, num, addr, name, description, access, width):
# register port
self.ports.append((name, num, width, access))
for i in range(0, num):
effect_addr = addr(i)
# we need to split the entry into multiple aligned entries as otherwise we would
# violate the access_width constraints
if (width / self.access_width) > 1.0:
for i in range(0, int(ceil(width / self.access_width))):
if (width - self.access_width * i < self.access_width):
self.addrmap.append(AddrMapEntry(effect_addr + int(self.access_width/8) * i, name, description.format(i), access, width - self.access_width * i))
else:
self.addrmap.append(AddrMapEntry(effect_addr + int(self.access_width/8) * i, name, description.format(i), access, self.access_width))
else:
self.addrmap.append(AddrMapEntry(effect_addr, name, description.format(i), access, width))
def addEntry(self, addr, name, description, access, width):
self.addEntries(1, addr, name, description, access, width)
"""Dump Verilog"""
def emit_verilog(self):
output = "// Do not edit - auto-generated\n"
params =",\n".join(map(lambda x: " " + x, [
"parameter type reg_req_t = logic",
"parameter type reg_rsp_t = logic"]))
output += "module {} {}(\n".format(self.name, "#(\n{}\n)".format(params))
for i in self.ports:
# self.ports.append((name, num, width, access))
if i[3] == Access.RO:
output += " input logic [{}:0][{}:0] {}_i,\n".format(i[1]-1, i[2]-1, i[0])
output += " output logic [{}:0] {}_re_o,\n".format(i[1]-1, i[0])
elif i[3] == Access.RW:
output += " input logic [{}:0][{}:0] {}_i,\n".format(i[1]-1, i[2]-1, i[0])
output += " output logic [{}:0][{}:0] {}_o,\n".format(i[1]-1, i[2]-1, i[0])
output += " output logic [{}:0] {}_we_o,\n".format(i[1]-1, i[0])
output += " output logic [{}:0] {}_re_o,\n".format(i[1]-1, i[0])
output += " // Bus Interface\n"
output += " input reg_req_t req_i,\n"
output += " output reg_rsp_t resp_o\n"
output += ");\n"
output += "always_comb begin\n"
output += " resp_o.ready = 1'b1;\n"
output += " resp_o.rdata = '0;\n"
output += " resp_o.error = '0;\n"
for i in self.ports:
if i[3] != Access.RO:
output += " {}_o = '0;\n".format(i[0])
output += " {}_we_o = '0;\n".format(i[0])
output += " {}_re_o = '0;\n".format(i[0])
output += " if (req_i.valid) begin\n"
output += " if (req_i.write) begin\n"
output += " unique case(req_i.addr)\n"
j = 0
last_name = ""
for i in self.addrmap:
if i.access != Access.RO:
if last_name != i.name:
j = 0
output += " {}'h{}: begin\n".format(self.access_width, hex(i.addr)[2:])
output += " {}_o[{}][{}:0] = req_i.wdata[{}:0];\n".format(i.name, j, i.width - 1, i.width - 1)
output += " {}_we_o[{}] = 1'b1;\n".format(i.name, j)
output += " end\n"
j += 1
last_name = i.name
output += " default: resp_o.error = 1'b1;\n"
output += " endcase\n"
output += " end else begin\n"
output += " unique case(req_i.addr)\n"
j = 0
last_name = ""
for i in self.addrmap:
if last_name != i.name:
j = 0
output += " {}'h{}: begin\n".format(self.access_width, hex(i.addr)[2:])
output += " resp_o.rdata[{}:0] = {}_i[{}][{}:0];\n".format(i.width - 1, i.name, j, i.width - 1)
output += " {}_re_o[{}] = 1'b1;\n".format(i.name, j)
output += " end\n"
j += 1
last_name = i.name
output += " default: resp_o.error = 1'b1;\n"
output += " endcase\n"
output += " end\n"
output += " end\n"
output += "end\n"
output += "endmodule\n"
return output
#
# Generate PLIC address map
#
if __name__ == "__main__":
# Parse the command line arguments.
parser = argparse.ArgumentParser()
parser.add_argument("-t", "--nr_targets", metavar="NrTargets", help="number of targets (default 2)", default=2)
parser.add_argument("-s", "--nr_sources", metavar="NrSources", help="number of sources (default 30)", default=30)
parser.add_argument("-p", "--max_priority", metavar="MaxPriority", help="maximum number of priority (default 7)", default=7)
args = parser.parse_args()
plic_base = 0xC000000
if args.nr_targets:
nr_target = int(args.nr_targets)
if args.nr_sources:
nr_src = int(args.nr_sources)
if args.max_priority:
max_prio = int(args.max_priority)
priority_width = clog2(max_prio + 1)
# interrupt source 0 is reserved, so add another source
nr_src_eff = nr_src + 1
source_width = clog2(nr_src_eff)
addrmap = AddrMap("plic_regs", "PLIC Address Map")
assert nr_src <= 31, "Not more than 31 interrupt sources are supported at the moment"
assert nr_target <= MAX_DEVICES, "Maximum allowed targets are {}".format(MAX_DEVICES)
priorityBase = plic_base + 0x0
enableBase = plic_base + 0x2000
hartBase = plic_base + 0x200000
def pendingAddr(i):
return plic_base + 0x1000
def enableOffset(i):
return i * int(((MAX_DEVICES+7)/8))
def hartOffset(i):
return i * 0x1000
def priorityAddr(i):
return priorityBase + i * 4
def enableAddr(i):
return enableOffset(i) + enableBase
def hartAddr(i):
return hartOffset(i) + hartBase
def hartCC(i):
return hartAddr(i) + 4
# add priority fields
addrmap.addEntries(nr_src_eff, priorityAddr, "prio", "source {} priority", Access.RW, priority_width)
# pending array
addrmap.addEntry(pendingAddr, "ip", "pending array", Access.RO, nr_src_eff)
# # generate per target interrupt enables
addrmap.addEntries(nr_target, enableAddr, "ie", "Target {} interrupt enable", Access.RW, nr_src_eff)
# # generate claim/complete registers + thresholds
addrmap.addEntries(nr_target, hartAddr, "threshold", "Hart {} priority threshold", Access.RW, priority_width)
addrmap.addEntries(nr_target, hartCC, "cc", "Hart {} claim/complete", Access.RW, source_width)
print(addrmap.emit_verilog())
|
// Do not edit - auto-generated
module plic_regs #(
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic
)(
input logic [30:0][2:0] prio_i,
output logic [30:0][2:0] prio_o,
output logic [30:0] prio_we_o,
output logic [30:0] prio_re_o,
input logic [0:0][30:0] ip_i,
output logic [0:0] ip_re_o,
input logic [1:0][30:0] ie_i,
output logic [1:0][30:0] ie_o,
output logic [1:0] ie_we_o,
output logic [1:0] ie_re_o,
input logic [1:0][2:0] threshold_i,
output logic [1:0][2:0] threshold_o,
output logic [1:0] threshold_we_o,
output logic [1:0] threshold_re_o,
input logic [1:0][4:0] cc_i,
output logic [1:0][4:0] cc_o,
output logic [1:0] cc_we_o,
output logic [1:0] cc_re_o,
// Bus Interface
input reg_req_t req_i,
output reg_rsp_t resp_o
);
always_comb begin
resp_o.ready = 1'b1;
resp_o.rdata = '0;
resp_o.error = '0;
prio_o = '0;
prio_we_o = '0;
prio_re_o = '0;
ie_o = '0;
ie_we_o = '0;
ie_re_o = '0;
threshold_o = '0;
threshold_we_o = '0;
threshold_re_o = '0;
cc_o = '0;
cc_we_o = '0;
cc_re_o = '0;
if (req_i.valid) begin
if (req_i.write) begin
unique case(req_i.addr)
32'hc000000: begin
prio_o[0][2:0] = req_i.wdata[2:0];
prio_we_o[0] = 1'b1;
end
32'hc000004: begin
prio_o[1][2:0] = req_i.wdata[2:0];
prio_we_o[1] = 1'b1;
end
32'hc000008: begin
prio_o[2][2:0] = req_i.wdata[2:0];
prio_we_o[2] = 1'b1;
end
32'hc00000c: begin
prio_o[3][2:0] = req_i.wdata[2:0];
prio_we_o[3] = 1'b1;
end
32'hc000010: begin
prio_o[4][2:0] = req_i.wdata[2:0];
prio_we_o[4] = 1'b1;
end
32'hc000014: begin
prio_o[5][2:0] = req_i.wdata[2:0];
prio_we_o[5] = 1'b1;
end
32'hc000018: begin
prio_o[6][2:0] = req_i.wdata[2:0];
prio_we_o[6] = 1'b1;
end
32'hc00001c: begin
prio_o[7][2:0] = req_i.wdata[2:0];
prio_we_o[7] = 1'b1;
end
32'hc000020: begin
prio_o[8][2:0] = req_i.wdata[2:0];
prio_we_o[8] = 1'b1;
end
32'hc000024: begin
prio_o[9][2:0] = req_i.wdata[2:0];
prio_we_o[9] = 1'b1;
end
32'hc000028: begin
prio_o[10][2:0] = req_i.wdata[2:0];
prio_we_o[10] = 1'b1;
end
32'hc00002c: begin
prio_o[11][2:0] = req_i.wdata[2:0];
prio_we_o[11] = 1'b1;
end
32'hc000030: begin
prio_o[12][2:0] = req_i.wdata[2:0];
prio_we_o[12] = 1'b1;
end
32'hc000034: begin
prio_o[13][2:0] = req_i.wdata[2:0];
prio_we_o[13] = 1'b1;
end
32'hc000038: begin
prio_o[14][2:0] = req_i.wdata[2:0];
prio_we_o[14] = 1'b1;
end
32'hc00003c: begin
prio_o[15][2:0] = req_i.wdata[2:0];
prio_we_o[15] = 1'b1;
end
32'hc000040: begin
prio_o[16][2:0] = req_i.wdata[2:0];
prio_we_o[16] = 1'b1;
end
32'hc000044: begin
prio_o[17][2:0] = req_i.wdata[2:0];
prio_we_o[17] = 1'b1;
end
32'hc000048: begin
prio_o[18][2:0] = req_i.wdata[2:0];
prio_we_o[18] = 1'b1;
end
32'hc00004c: begin
prio_o[19][2:0] = req_i.wdata[2:0];
prio_we_o[19] = 1'b1;
end
32'hc000050: begin
prio_o[20][2:0] = req_i.wdata[2:0];
prio_we_o[20] = 1'b1;
end
32'hc000054: begin
prio_o[21][2:0] = req_i.wdata[2:0];
prio_we_o[21] = 1'b1;
end
32'hc000058: begin
prio_o[22][2:0] = req_i.wdata[2:0];
prio_we_o[22] = 1'b1;
end
32'hc00005c: begin
prio_o[23][2:0] = req_i.wdata[2:0];
prio_we_o[23] = 1'b1;
end
32'hc000060: begin
prio_o[24][2:0] = req_i.wdata[2:0];
prio_we_o[24] = 1'b1;
end
32'hc000064: begin
prio_o[25][2:0] = req_i.wdata[2:0];
prio_we_o[25] = 1'b1;
end
32'hc000068: begin
prio_o[26][2:0] = req_i.wdata[2:0];
prio_we_o[26] = 1'b1;
end
32'hc00006c: begin
prio_o[27][2:0] = req_i.wdata[2:0];
prio_we_o[27] = 1'b1;
end
32'hc000070: begin
prio_o[28][2:0] = req_i.wdata[2:0];
prio_we_o[28] = 1'b1;
end
32'hc000074: begin
prio_o[29][2:0] = req_i.wdata[2:0];
prio_we_o[29] = 1'b1;
end
32'hc000078: begin
prio_o[30][2:0] = req_i.wdata[2:0];
prio_we_o[30] = 1'b1;
end
32'hc002000: begin
ie_o[0][30:0] = req_i.wdata[30:0];
ie_we_o[0] = 1'b1;
end
32'hc002080: begin
ie_o[1][30:0] = req_i.wdata[30:0];
ie_we_o[1] = 1'b1;
end
32'hc200000: begin
threshold_o[0][2:0] = req_i.wdata[2:0];
threshold_we_o[0] = 1'b1;
end
32'hc201000: begin
threshold_o[1][2:0] = req_i.wdata[2:0];
threshold_we_o[1] = 1'b1;
end
32'hc200004: begin
cc_o[0][4:0] = req_i.wdata[4:0];
cc_we_o[0] = 1'b1;
end
32'hc201004: begin
cc_o[1][4:0] = req_i.wdata[4:0];
cc_we_o[1] = 1'b1;
end
default: resp_o.error = 1'b1;
endcase
end else begin
unique case(req_i.addr)
32'hc000000: begin
resp_o.rdata[2:0] = prio_i[0][2:0];
prio_re_o[0] = 1'b1;
end
32'hc000004: begin
resp_o.rdata[2:0] = prio_i[1][2:0];
prio_re_o[1] = 1'b1;
end
32'hc000008: begin
resp_o.rdata[2:0] = prio_i[2][2:0];
prio_re_o[2] = 1'b1;
end
32'hc00000c: begin
resp_o.rdata[2:0] = prio_i[3][2:0];
prio_re_o[3] = 1'b1;
end
32'hc000010: begin
resp_o.rdata[2:0] = prio_i[4][2:0];
prio_re_o[4] = 1'b1;
end
32'hc000014: begin
resp_o.rdata[2:0] = prio_i[5][2:0];
prio_re_o[5] = 1'b1;
end
32'hc000018: begin
resp_o.rdata[2:0] = prio_i[6][2:0];
prio_re_o[6] = 1'b1;
end
32'hc00001c: begin
resp_o.rdata[2:0] = prio_i[7][2:0];
prio_re_o[7] = 1'b1;
end
32'hc000020: begin
resp_o.rdata[2:0] = prio_i[8][2:0];
prio_re_o[8] = 1'b1;
end
32'hc000024: begin
resp_o.rdata[2:0] = prio_i[9][2:0];
prio_re_o[9] = 1'b1;
end
32'hc000028: begin
resp_o.rdata[2:0] = prio_i[10][2:0];
prio_re_o[10] = 1'b1;
end
32'hc00002c: begin
resp_o.rdata[2:0] = prio_i[11][2:0];
prio_re_o[11] = 1'b1;
end
32'hc000030: begin
resp_o.rdata[2:0] = prio_i[12][2:0];
prio_re_o[12] = 1'b1;
end
32'hc000034: begin
resp_o.rdata[2:0] = prio_i[13][2:0];
prio_re_o[13] = 1'b1;
end
32'hc000038: begin
resp_o.rdata[2:0] = prio_i[14][2:0];
prio_re_o[14] = 1'b1;
end
32'hc00003c: begin
resp_o.rdata[2:0] = prio_i[15][2:0];
prio_re_o[15] = 1'b1;
end
32'hc000040: begin
resp_o.rdata[2:0] = prio_i[16][2:0];
prio_re_o[16] = 1'b1;
end
32'hc000044: begin
resp_o.rdata[2:0] = prio_i[17][2:0];
prio_re_o[17] = 1'b1;
end
32'hc000048: begin
resp_o.rdata[2:0] = prio_i[18][2:0];
prio_re_o[18] = 1'b1;
end
32'hc00004c: begin
resp_o.rdata[2:0] = prio_i[19][2:0];
prio_re_o[19] = 1'b1;
end
32'hc000050: begin
resp_o.rdata[2:0] = prio_i[20][2:0];
prio_re_o[20] = 1'b1;
end
32'hc000054: begin
resp_o.rdata[2:0] = prio_i[21][2:0];
prio_re_o[21] = 1'b1;
end
32'hc000058: begin
resp_o.rdata[2:0] = prio_i[22][2:0];
prio_re_o[22] = 1'b1;
end
32'hc00005c: begin
resp_o.rdata[2:0] = prio_i[23][2:0];
prio_re_o[23] = 1'b1;
end
32'hc000060: begin
resp_o.rdata[2:0] = prio_i[24][2:0];
prio_re_o[24] = 1'b1;
end
32'hc000064: begin
resp_o.rdata[2:0] = prio_i[25][2:0];
prio_re_o[25] = 1'b1;
end
32'hc000068: begin
resp_o.rdata[2:0] = prio_i[26][2:0];
prio_re_o[26] = 1'b1;
end
32'hc00006c: begin
resp_o.rdata[2:0] = prio_i[27][2:0];
prio_re_o[27] = 1'b1;
end
32'hc000070: begin
resp_o.rdata[2:0] = prio_i[28][2:0];
prio_re_o[28] = 1'b1;
end
32'hc000074: begin
resp_o.rdata[2:0] = prio_i[29][2:0];
prio_re_o[29] = 1'b1;
end
32'hc000078: begin
resp_o.rdata[2:0] = prio_i[30][2:0];
prio_re_o[30] = 1'b1;
end
32'hc001000: begin
resp_o.rdata[30:0] = ip_i[0][30:0];
ip_re_o[0] = 1'b1;
end
32'hc002000: begin
resp_o.rdata[30:0] = ie_i[0][30:0];
ie_re_o[0] = 1'b1;
end
32'hc002080: begin
resp_o.rdata[30:0] = ie_i[1][30:0];
ie_re_o[1] = 1'b1;
end
32'hc200000: begin
resp_o.rdata[2:0] = threshold_i[0][2:0];
threshold_re_o[0] = 1'b1;
end
32'hc201000: begin
resp_o.rdata[2:0] = threshold_i[1][2:0];
threshold_re_o[1] = 1'b1;
end
32'hc200004: begin
resp_o.rdata[4:0] = cc_i[0][4:0];
cc_re_o[0] = 1'b1;
end
32'hc201004: begin
resp_o.rdata[4:0] = cc_i[1][4:0];
cc_re_o[1] = 1'b1;
end
default: resp_o.error = 1'b1;
endcase
end
end
end
endmodule
|
// Copyright 2022 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba <zaruabf@iis.ee.ethz.ch>
//
// Description: Platform level interrupt controller
module plic_top #(
parameter int N_SOURCE = 30,
parameter int N_TARGET = 2,
parameter int MAX_PRIO = 7,
parameter int SRCW = $clog2(N_SOURCE+1),
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// Bus Interface
input reg_req_t req_i,
output reg_rsp_t resp_o,
input logic [N_SOURCE-1:0] le_i, // 0:level 1:edge
// Interrupt Sources
input logic [N_SOURCE-1:0] irq_sources_i,
// Interrupt notification to targets
output logic [N_TARGET-1:0] eip_targets_o
);
localparam PRIOW = $clog2(MAX_PRIO+1);
logic [N_SOURCE-1:0] ip;
logic [N_TARGET-1:0][PRIOW-1:0] threshold_q;
logic [N_TARGET-1:0] claim_re; //Target read indicator
logic [N_TARGET-1:0][SRCW-1:0] claim_id;
logic [N_SOURCE-1:0] claim; //Converted from claim_re/claim_id
logic [N_TARGET-1:0] complete_we; //Target write indicator
logic [N_TARGET-1:0][SRCW-1:0] complete_id;
logic [N_SOURCE-1:0] complete; //Converted from complete_re/complete_id
logic [N_SOURCE-1:0][PRIOW-1:0] prio_q;
logic [N_TARGET-1:0][N_SOURCE-1:0] ie_q;
always_comb begin
claim = '0;
complete = '0;
for (int i = 0 ; i < N_TARGET ; i++) begin
if (claim_re[i] && claim_id[i] != 0) claim[claim_id[i]-1] = 1'b1;
if (complete_we[i] && complete_id[i] != 0) complete[complete_id[i]-1] = 1'b1;
end
end
// Gateways
rv_plic_gateway #(
.N_SOURCE (N_SOURCE)
) i_rv_plic_gateway (
.clk_i,
.rst_ni,
.src(irq_sources_i),
.le(le_i),
.claim(claim),
.complete(complete),
.ip(ip)
);
// Target interrupt notification
for (genvar i = 0 ; i < N_TARGET; i++) begin : gen_target
rv_plic_target #(
.N_SOURCE ( N_SOURCE ),
.MAX_PRIO ( MAX_PRIO ),
.ALGORITHM ( "SEQUENTIAL" )
) i_target (
.clk_i,
.rst_ni,
.ip(ip),
.ie(ie_q[i]),
.prio(prio_q),
.threshold(threshold_q[i]),
.irq(eip_targets_o[i]),
.irq_id(claim_id[i])
);
end
logic [N_TARGET-1:0] threshold_we_o;
logic [N_TARGET-1:0][PRIOW-1:0] threshold_o;
logic [N_SOURCE:0][PRIOW-1:0] prio_i, prio_o;
logic [N_SOURCE:0] prio_we_o;
// TODO(zarubaf): This needs more graceful handling
// it will break if the number of sources is larger than 32
logic [N_TARGET-1:0][N_SOURCE:0] ie_i, ie_o;
logic [N_TARGET-1:0] ie_we_o;
plic_regs #(
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_plic_regs (
.prio_i(prio_i),
.prio_o(prio_o),
.prio_we_o(prio_we_o),
.prio_re_o(), // don't care
// source zero is always zero
.ip_i({ip, 1'b0}),
.ip_re_o(), // don't care
.ie_i(ie_i),
.ie_o(ie_o),
.ie_we_o(ie_we_o),
.ie_re_o(), // don't care
.threshold_i(threshold_q),
.threshold_o(threshold_o),
.threshold_we_o(threshold_we_o),
.threshold_re_o(), // don't care
.cc_i(claim_id),
.cc_o(complete_id),
.cc_we_o(complete_we),
.cc_re_o(claim_re),
.req_i,
.resp_o
);
assign prio_i[0] = '0;
for (genvar i = 0; i < N_TARGET; i++) begin
assign ie_i[i] = {ie_q[i][N_SOURCE-1:0], 1'b0};
end
for (genvar i = 1; i < N_SOURCE + 1; i++) begin
assign prio_i[i] = prio_q[i - 1];
end
// registers
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
prio_q <= '0;
ie_q <= '0;
threshold_q <= '0;
end else begin
// source zero is 0
for (int i = 0; i < N_SOURCE; i++) begin
prio_q[i] <= prio_we_o[i + 1] ? prio_o[i + 1] : prio_q[i];
end
for (int i = 0; i < N_TARGET; i++) begin
threshold_q[i] <= threshold_we_o[i] ? threshold_o[i] : threshold_q[i];
ie_q[i] <= ie_we_o[i] ? ie_o[i][N_SOURCE:1] : ie_q[i];
end
end
end
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register slice conforming STWG verilog guide.
module prim_subreg #(
parameter DW = 32 ,
parameter SWACCESS = "RW", // {RW, RO, WO, W1C, W1S, W0C, RC}
parameter logic [DW-1:0] RESVAL = '0 // Reset value
) (
input clk_i,
input rst_ni,
// From SW: valid for RW, WO, W1C, W1S, W0C, RC
// In case of RC, Top connects Read Pulse to we
input we,
input [DW-1:0] wd,
// From HW: valid for HRW, HWO
input de,
input [DW-1:0] d,
// output to HW and Reg Read
output logic qe,
output logic [DW-1:0] q,
output logic [DW-1:0] qs
);
logic wr_en ;
logic [DW-1:0] wr_data;
if ((SWACCESS == "RW") || (SWACCESS == "WO")) begin : gen_w
assign wr_en = we | de ;
assign wr_data = (we == 1'b1) ? wd : d ; // SW higher priority
end else if (SWACCESS == "RO") begin : gen_ro
// Unused we, wd
assign wr_en = de ;
assign wr_data = d ;
end else if (SWACCESS == "W1S") begin : gen_w1s
// If SWACCESS is W1S, then assume hw tries to clear.
// So, give a chance HW to clear when SW tries to set.
// If both try to set/clr at the same bit pos, SW wins.
assign wr_en = we | de ;
assign wr_data = (de ? d : q) | (we ? wd : '0);
end else if (SWACCESS == "W1C") begin : gen_w1c
// If SWACCESS is W1C, then assume hw tries to set.
// So, give a chance HW to set when SW tries to clear.
// If both try to set/clr at the same bit pos, SW wins.
assign wr_en = we | de ;
assign wr_data = (de ? d : q) & (we ? ~wd : '1);
end else if (SWACCESS == "W0C") begin : gen_w0c
assign wr_en = we | de ;
assign wr_data = (de ? d : q) & (we ? wd : '1);
end else if (SWACCESS == "RC") begin : gen_rc
// This swtype is not recommended but exists for compatibility.
// WARN: we signal is actually read signal not write enable.
assign wr_en = we | de ;
assign wr_data = (de ? d : q) & (we ? '0 : '1);
end else begin : gen_hw
assign wr_en = de ;
assign wr_data = d ;
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) qe <= 1'b0;
else qe <= we ;
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) q <= RESVAL ;
else if (wr_en) q <= wr_data;
end
assign qs = q;
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register slice conforming STWG verilog guide.
module prim_subreg_ext #(
parameter DW = 32
) (
input re,
input we,
input [DW-1:0] wd,
input [DW-1:0] d,
// output to HW and Reg Read
output logic qe,
output logic qre,
output logic [DW-1:0] q,
output logic [DW-1:0] qs
);
assign qs = d;
assign q = wd;
assign qe = we;
assign qre = re;
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// RISC-V Platform-Level Interrupt Controller compliant INTC
//
// Current version doesn't support MSI interrupt but it is easy to add
// the feature. Create one external register and connect qe signal to the
// gateway module (as edge-triggered)
//
// Consider to set MAX_PRIO as small number as possible. It is main factor
// of area increase if edge-triggered counter isn't implemented.
//
// verilog parameter
// N_SOURCE: Number of interrupt sources
// N_TARGET: Number of interrupt targets (#receptor)
// MAX_PRIO: Maximum value of interrupt priority
// SRCW: Do not specify this parameter. It is bit width to cover MAX_ID+1
module rv_plic #(
parameter int N_SOURCE = 32,
parameter int N_TARGET = 1,
parameter int MAX_PRIO = 7,
parameter FIND_MAX = "SEQUENTIAL", // SEQUENTIAL | MATRIX
// Local param (Do not change this through parameter)
parameter int SRCW = $clog2(N_SOURCE+1)
) (
input clk_i,
input rst_ni,
// Bus Interface (device)
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// Interrupt Sources
input [N_SOURCE-1:0] intr_src_i,
// Interrupt notification to targets
output irq_o [N_TARGET],
output [SRCW-1:0] irq_id_o [N_TARGET]
);
import rv_plic_reg_pkg::*;
rv_plic_reg2hw_t reg2hw;
rv_plic_hw2reg_t hw2reg;
localparam PRIOW = $clog2(MAX_PRIO+1);
logic [N_SOURCE-1:0] le; // 0:level 1:edge
logic [N_SOURCE-1:0] ip;
logic [N_SOURCE-1:0] ie [N_TARGET];
logic claim_re [N_TARGET]; // Target read indicator
logic [SRCW-1:0] claim_id [N_TARGET];
logic [N_SOURCE-1:0] claim ; // Converted from claim_re/claim_id
logic complete_we [N_TARGET]; // Target write indicator
logic [SRCW-1:0] complete_id [N_TARGET];
logic [N_SOURCE-1:0] complete ; // Converted from complete_re/complete_id
logic [SRCW-1:0] cc_id [N_TARGET]; // Write ID
logic [PRIOW-1:0] prio [N_SOURCE];
logic [PRIOW-1:0] threshold [N_TARGET];
// Glue logic between rv_plic_reg_top and others
assign cc_id = irq_id_o;
always_comb begin
claim = '0;
for (int i = 0 ; i < N_TARGET ; i++) begin
if (claim_re[i]) claim[claim_id[i] -1] = 1'b1;
end
end
always_comb begin
complete = '0;
for (int i = 0 ; i < N_TARGET ; i++) begin
if (complete_we[i]) complete[complete_id[i] -1] = 1'b1;
end
end
`ifndef VERILATOR
//sequence pulse_seq (sig);
// sig ##1 ~sig;
//endsequence
property pulse_prop (sig);
@(posedge clk_i)
sig |=> ##1 ~sig;
endproperty
//claim_pulse_assert: assert property (pulse_prop(claim_re[i]));
//complete_pulse_assert: assert property (pulse_prop(complete_we[i]));
onehot0_claim_assert: assert property (
@(posedge clk_i) disable iff (!rst_ni)
$onehot0(claim_re)
);
onehot0_complete_assert: assert property (
@(posedge clk_i) disable iff (!rst_ni)
$onehot0(complete_we)
);
`endif // VERILATOR
//pragma translate_off
if(SRCW != $clog2(N_SOURCE+1)) $fatal("SRCW shouldn't be modified");
//pragma translate_on
////////////////////////////////////////////////////////////////////////////////
// PRIORITY : Need to connect manually
assign prio[ 0] = reg2hw.prio0.q;
assign prio[ 1] = reg2hw.prio1.q;
assign prio[ 2] = reg2hw.prio2.q;
assign prio[ 3] = reg2hw.prio3.q;
assign prio[ 4] = reg2hw.prio4.q;
assign prio[ 5] = reg2hw.prio5.q;
assign prio[ 6] = reg2hw.prio6.q;
assign prio[ 7] = reg2hw.prio7.q;
assign prio[ 8] = reg2hw.prio8.q;
assign prio[ 9] = reg2hw.prio9.q;
assign prio[10] = reg2hw.prio10.q;
assign prio[11] = reg2hw.prio11.q;
assign prio[12] = reg2hw.prio12.q;
assign prio[13] = reg2hw.prio13.q;
assign prio[14] = reg2hw.prio14.q;
assign prio[15] = reg2hw.prio15.q;
assign prio[16] = reg2hw.prio16.q;
assign prio[17] = reg2hw.prio17.q;
assign prio[18] = reg2hw.prio18.q;
assign prio[19] = reg2hw.prio19.q;
assign prio[20] = reg2hw.prio20.q;
assign prio[21] = reg2hw.prio21.q;
assign prio[22] = reg2hw.prio22.q;
assign prio[23] = reg2hw.prio23.q;
assign prio[24] = reg2hw.prio24.q;
assign prio[25] = reg2hw.prio25.q;
assign prio[26] = reg2hw.prio26.q;
assign prio[27] = reg2hw.prio27.q;
assign prio[28] = reg2hw.prio28.q;
assign prio[29] = reg2hw.prio29.q;
assign prio[30] = reg2hw.prio30.q;
assign prio[31] = reg2hw.prio31.q;
//------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
// Interrupt Enable : Need to connect manually
assign ie[0][ 0] = reg2hw.ie0.e0.q;
assign ie[0][ 1] = reg2hw.ie0.e1.q;
assign ie[0][ 2] = reg2hw.ie0.e2.q;
assign ie[0][ 3] = reg2hw.ie0.e3.q;
assign ie[0][ 4] = reg2hw.ie0.e4.q;
assign ie[0][ 5] = reg2hw.ie0.e5.q;
assign ie[0][ 6] = reg2hw.ie0.e6.q;
assign ie[0][ 7] = reg2hw.ie0.e7.q;
assign ie[0][ 8] = reg2hw.ie0.e8.q;
assign ie[0][ 9] = reg2hw.ie0.e9.q;
assign ie[0][10] = reg2hw.ie0.e10.q;
assign ie[0][11] = reg2hw.ie0.e11.q;
assign ie[0][12] = reg2hw.ie0.e12.q;
assign ie[0][13] = reg2hw.ie0.e13.q;
assign ie[0][14] = reg2hw.ie0.e14.q;
assign ie[0][15] = reg2hw.ie0.e15.q;
assign ie[0][16] = reg2hw.ie0.e16.q;
assign ie[0][17] = reg2hw.ie0.e17.q;
assign ie[0][18] = reg2hw.ie0.e18.q;
assign ie[0][19] = reg2hw.ie0.e19.q;
assign ie[0][20] = reg2hw.ie0.e20.q;
assign ie[0][21] = reg2hw.ie0.e21.q;
assign ie[0][22] = reg2hw.ie0.e22.q;
assign ie[0][23] = reg2hw.ie0.e23.q;
assign ie[0][24] = reg2hw.ie0.e24.q;
assign ie[0][25] = reg2hw.ie0.e25.q;
assign ie[0][26] = reg2hw.ie0.e26.q;
assign ie[0][27] = reg2hw.ie0.e27.q;
assign ie[0][28] = reg2hw.ie0.e28.q;
assign ie[0][29] = reg2hw.ie0.e29.q;
assign ie[0][30] = reg2hw.ie0.e30.q;
assign ie[0][31] = reg2hw.ie0.e31.q;
//------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
// THRESHOLD : Need to connect manually
assign threshold[0] = reg2hw.threshold0.q;
//------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
// CC : Need to connect manually
assign claim_re[0] = reg2hw.cc0.re;
assign claim_id[0] = irq_id_o[0];
assign complete_we[0] = reg2hw.cc0.qe;
assign complete_id[0] = reg2hw.cc0.q;
assign hw2reg.cc0.d = cc_id[0];
//------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
// IP : Need to connect manually
assign hw2reg.ip.p0.de = 1'b1; // Always write
assign hw2reg.ip.p1.de = 1'b1; // Always write
assign hw2reg.ip.p2.de = 1'b1; // Always write
assign hw2reg.ip.p3.de = 1'b1; // Always write
assign hw2reg.ip.p4.de = 1'b1; // Always write
assign hw2reg.ip.p5.de = 1'b1; // Always write
assign hw2reg.ip.p6.de = 1'b1; // Always write
assign hw2reg.ip.p7.de = 1'b1; // Always write
assign hw2reg.ip.p8.de = 1'b1; // Always write
assign hw2reg.ip.p9.de = 1'b1; // Always write
assign hw2reg.ip.p10.de = 1'b1; // Always write
assign hw2reg.ip.p11.de = 1'b1; // Always write
assign hw2reg.ip.p12.de = 1'b1; // Always write
assign hw2reg.ip.p13.de = 1'b1; // Always write
assign hw2reg.ip.p14.de = 1'b1; // Always write
assign hw2reg.ip.p15.de = 1'b1; // Always write
assign hw2reg.ip.p16.de = 1'b1; // Always write
assign hw2reg.ip.p17.de = 1'b1; // Always write
assign hw2reg.ip.p18.de = 1'b1; // Always write
assign hw2reg.ip.p19.de = 1'b1; // Always write
assign hw2reg.ip.p20.de = 1'b1; // Always write
assign hw2reg.ip.p21.de = 1'b1; // Always write
assign hw2reg.ip.p22.de = 1'b1; // Always write
assign hw2reg.ip.p23.de = 1'b1; // Always write
assign hw2reg.ip.p24.de = 1'b1; // Always write
assign hw2reg.ip.p25.de = 1'b1; // Always write
assign hw2reg.ip.p26.de = 1'b1; // Always write
assign hw2reg.ip.p27.de = 1'b1; // Always write
assign hw2reg.ip.p28.de = 1'b1; // Always write
assign hw2reg.ip.p29.de = 1'b1; // Always write
assign hw2reg.ip.p30.de = 1'b1; // Always write
assign hw2reg.ip.p31.de = 1'b1; // Always write
assign hw2reg.ip.p0.d = ip[0];
assign hw2reg.ip.p1.d = ip[1];
assign hw2reg.ip.p2.d = ip[2];
assign hw2reg.ip.p3.d = ip[3];
assign hw2reg.ip.p4.d = ip[4];
assign hw2reg.ip.p5.d = ip[5];
assign hw2reg.ip.p6.d = ip[6];
assign hw2reg.ip.p7.d = ip[7];
assign hw2reg.ip.p8.d = ip[8];
assign hw2reg.ip.p9.d = ip[9];
assign hw2reg.ip.p10.d = ip[10];
assign hw2reg.ip.p11.d = ip[11];
assign hw2reg.ip.p12.d = ip[12];
assign hw2reg.ip.p13.d = ip[13];
assign hw2reg.ip.p14.d = ip[14];
assign hw2reg.ip.p15.d = ip[15];
assign hw2reg.ip.p16.d = ip[16];
assign hw2reg.ip.p17.d = ip[17];
assign hw2reg.ip.p18.d = ip[18];
assign hw2reg.ip.p19.d = ip[19];
assign hw2reg.ip.p20.d = ip[20];
assign hw2reg.ip.p21.d = ip[21];
assign hw2reg.ip.p22.d = ip[22];
assign hw2reg.ip.p23.d = ip[23];
assign hw2reg.ip.p24.d = ip[24];
assign hw2reg.ip.p25.d = ip[25];
assign hw2reg.ip.p26.d = ip[26];
assign hw2reg.ip.p27.d = ip[27];
assign hw2reg.ip.p28.d = ip[28];
assign hw2reg.ip.p29.d = ip[29];
assign hw2reg.ip.p30.d = ip[30];
assign hw2reg.ip.p31.d = ip[31];
//------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
// LE : Need to connect manually
assign le[0] = reg2hw.le.le0.q;
assign le[1] = reg2hw.le.le1.q;
assign le[2] = reg2hw.le.le2.q;
assign le[3] = reg2hw.le.le3.q;
assign le[4] = reg2hw.le.le4.q;
assign le[5] = reg2hw.le.le5.q;
assign le[6] = reg2hw.le.le6.q;
assign le[7] = reg2hw.le.le7.q;
assign le[8] = reg2hw.le.le8.q;
assign le[9] = reg2hw.le.le9.q;
assign le[10] = reg2hw.le.le10.q;
assign le[11] = reg2hw.le.le11.q;
assign le[12] = reg2hw.le.le12.q;
assign le[13] = reg2hw.le.le13.q;
assign le[14] = reg2hw.le.le14.q;
assign le[15] = reg2hw.le.le15.q;
assign le[16] = reg2hw.le.le16.q;
assign le[17] = reg2hw.le.le17.q;
assign le[18] = reg2hw.le.le18.q;
assign le[19] = reg2hw.le.le19.q;
assign le[20] = reg2hw.le.le20.q;
assign le[21] = reg2hw.le.le21.q;
assign le[22] = reg2hw.le.le22.q;
assign le[23] = reg2hw.le.le23.q;
assign le[24] = reg2hw.le.le24.q;
assign le[25] = reg2hw.le.le25.q;
assign le[26] = reg2hw.le.le26.q;
assign le[27] = reg2hw.le.le27.q;
assign le[28] = reg2hw.le.le28.q;
assign le[29] = reg2hw.le.le29.q;
assign le[30] = reg2hw.le.le30.q;
assign le[31] = reg2hw.le.le31.q;
//------------------------------------------------------------------------------
// Gateways
rv_plic_gateway #(
.N_SOURCE (N_SOURCE)
) u_gateway (
.clk_i,
.rst_ni,
.src (intr_src_i),
.le,
.claim,
.complete,
.ip
);
// Target interrupt notification
for (genvar i = 0 ; i < N_TARGET ; i++) begin : gen_target
rv_plic_target #(
.N_SOURCE (N_SOURCE),
.MAX_PRIO (MAX_PRIO),
.ALGORITHM(FIND_MAX)
) u_target (
.clk_i,
.rst_ni,
.ip,
.ie (ie[i]),
.prio,
.threshold (threshold[i]),
.irq (irq_o[i]),
.irq_id (irq_id_o[i])
);
end
// Register interface
// Limitation of register tool prevents the module from having flexibility to parameters
// So, signals are manually tied at the top.
rv_plic_reg_top u_reg (
.clk_i,
.rst_ni,
.tl_i,
.tl_o,
.reg2hw,
.hw2reg
);
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// RISC-V Platform-Level Interrupt Gateways module
module rv_plic_gateway #(
parameter int N_SOURCE = 32
) (
input clk_i,
input rst_ni,
input [N_SOURCE-1:0] src,
input [N_SOURCE-1:0] le, // Level0 Edge1
input [N_SOURCE-1:0] claim, // $onehot0(claim)
input [N_SOURCE-1:0] complete, // $onehot0(complete)
output logic [N_SOURCE-1:0] ip
);
logic [N_SOURCE-1:0] ia; // Interrupt Active
logic [N_SOURCE-1:0] set; // Set: (le) ? src & ~src_d : src ;
logic [N_SOURCE-1:0] src_d;
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) src_d <= '0;
else src_d <= src;
end
always_comb begin
for (int i = 0 ; i < N_SOURCE; i++) begin
set[i] = (le[i]) ? src[i] & ~src_d[i] : src[i] ;
end
end
// Interrupt pending is set by source (depends on le), cleared by claim.
// Until interrupt is claimed, set doesn't affect ip.
// RISC-V PLIC spec mentioned it can have counter for edge triggered
// But skipped the feature as counter consumes substantial logic size.
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
ip <= '0;
end else begin
ip <= (ip | (set & ~ia & ~ip)) & (~claim);
end
end
// Interrupt active is to control ip. If ip is set then until completed
// by target, ip shouldn't be set by source even claim can clear ip.
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
ia <= '0;
end else begin
ia <= (ia | (set & ~ia)) & (~complete);
end
end
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Package auto-generated by `reggen` containing data structure
package rv_plic_reg_pkg;
// Register to internal design logic
typedef struct packed {
struct packed {
struct packed {
logic q;
} le0;
struct packed {
logic q;
} le1;
struct packed {
logic q;
} le2;
struct packed {
logic q;
} le3;
struct packed {
logic q;
} le4;
struct packed {
logic q;
} le5;
struct packed {
logic q;
} le6;
struct packed {
logic q;
} le7;
struct packed {
logic q;
} le8;
struct packed {
logic q;
} le9;
struct packed {
logic q;
} le10;
struct packed {
logic q;
} le11;
struct packed {
logic q;
} le12;
struct packed {
logic q;
} le13;
struct packed {
logic q;
} le14;
struct packed {
logic q;
} le15;
struct packed {
logic q;
} le16;
struct packed {
logic q;
} le17;
struct packed {
logic q;
} le18;
struct packed {
logic q;
} le19;
struct packed {
logic q;
} le20;
struct packed {
logic q;
} le21;
struct packed {
logic q;
} le22;
struct packed {
logic q;
} le23;
struct packed {
logic q;
} le24;
struct packed {
logic q;
} le25;
struct packed {
logic q;
} le26;
struct packed {
logic q;
} le27;
struct packed {
logic q;
} le28;
struct packed {
logic q;
} le29;
struct packed {
logic q;
} le30;
struct packed {
logic q;
} le31;
} le;
struct packed {
logic [2:0] q;
} prio0;
struct packed {
logic [2:0] q;
} prio1;
struct packed {
logic [2:0] q;
} prio2;
struct packed {
logic [2:0] q;
} prio3;
struct packed {
logic [2:0] q;
} prio4;
struct packed {
logic [2:0] q;
} prio5;
struct packed {
logic [2:0] q;
} prio6;
struct packed {
logic [2:0] q;
} prio7;
struct packed {
logic [2:0] q;
} prio8;
struct packed {
logic [2:0] q;
} prio9;
struct packed {
logic [2:0] q;
} prio10;
struct packed {
logic [2:0] q;
} prio11;
struct packed {
logic [2:0] q;
} prio12;
struct packed {
logic [2:0] q;
} prio13;
struct packed {
logic [2:0] q;
} prio14;
struct packed {
logic [2:0] q;
} prio15;
struct packed {
logic [2:0] q;
} prio16;
struct packed {
logic [2:0] q;
} prio17;
struct packed {
logic [2:0] q;
} prio18;
struct packed {
logic [2:0] q;
} prio19;
struct packed {
logic [2:0] q;
} prio20;
struct packed {
logic [2:0] q;
} prio21;
struct packed {
logic [2:0] q;
} prio22;
struct packed {
logic [2:0] q;
} prio23;
struct packed {
logic [2:0] q;
} prio24;
struct packed {
logic [2:0] q;
} prio25;
struct packed {
logic [2:0] q;
} prio26;
struct packed {
logic [2:0] q;
} prio27;
struct packed {
logic [2:0] q;
} prio28;
struct packed {
logic [2:0] q;
} prio29;
struct packed {
logic [2:0] q;
} prio30;
struct packed {
logic [2:0] q;
} prio31;
struct packed {
struct packed {
logic q;
} e0;
struct packed {
logic q;
} e1;
struct packed {
logic q;
} e2;
struct packed {
logic q;
} e3;
struct packed {
logic q;
} e4;
struct packed {
logic q;
} e5;
struct packed {
logic q;
} e6;
struct packed {
logic q;
} e7;
struct packed {
logic q;
} e8;
struct packed {
logic q;
} e9;
struct packed {
logic q;
} e10;
struct packed {
logic q;
} e11;
struct packed {
logic q;
} e12;
struct packed {
logic q;
} e13;
struct packed {
logic q;
} e14;
struct packed {
logic q;
} e15;
struct packed {
logic q;
} e16;
struct packed {
logic q;
} e17;
struct packed {
logic q;
} e18;
struct packed {
logic q;
} e19;
struct packed {
logic q;
} e20;
struct packed {
logic q;
} e21;
struct packed {
logic q;
} e22;
struct packed {
logic q;
} e23;
struct packed {
logic q;
} e24;
struct packed {
logic q;
} e25;
struct packed {
logic q;
} e26;
struct packed {
logic q;
} e27;
struct packed {
logic q;
} e28;
struct packed {
logic q;
} e29;
struct packed {
logic q;
} e30;
struct packed {
logic q;
} e31;
} ie0;
struct packed {
logic [2:0] q;
} threshold0;
struct packed {
logic [5:0] q;
logic qe;
logic re;
} cc0;
} rv_plic_reg2hw_t;
// Internal design logic to register
typedef struct packed {
struct packed {
struct packed {
logic d;
logic de;
} p0;
struct packed {
logic d;
logic de;
} p1;
struct packed {
logic d;
logic de;
} p2;
struct packed {
logic d;
logic de;
} p3;
struct packed {
logic d;
logic de;
} p4;
struct packed {
logic d;
logic de;
} p5;
struct packed {
logic d;
logic de;
} p6;
struct packed {
logic d;
logic de;
} p7;
struct packed {
logic d;
logic de;
} p8;
struct packed {
logic d;
logic de;
} p9;
struct packed {
logic d;
logic de;
} p10;
struct packed {
logic d;
logic de;
} p11;
struct packed {
logic d;
logic de;
} p12;
struct packed {
logic d;
logic de;
} p13;
struct packed {
logic d;
logic de;
} p14;
struct packed {
logic d;
logic de;
} p15;
struct packed {
logic d;
logic de;
} p16;
struct packed {
logic d;
logic de;
} p17;
struct packed {
logic d;
logic de;
} p18;
struct packed {
logic d;
logic de;
} p19;
struct packed {
logic d;
logic de;
} p20;
struct packed {
logic d;
logic de;
} p21;
struct packed {
logic d;
logic de;
} p22;
struct packed {
logic d;
logic de;
} p23;
struct packed {
logic d;
logic de;
} p24;
struct packed {
logic d;
logic de;
} p25;
struct packed {
logic d;
logic de;
} p26;
struct packed {
logic d;
logic de;
} p27;
struct packed {
logic d;
logic de;
} p28;
struct packed {
logic d;
logic de;
} p29;
struct packed {
logic d;
logic de;
} p30;
struct packed {
logic d;
logic de;
} p31;
} ip;
struct packed {
logic [5:0] d;
} cc0;
} rv_plic_hw2reg_t;
// Register Address
parameter RV_PLIC_IP_OFFSET = 9'h 0;
parameter RV_PLIC_LE_OFFSET = 9'h 4;
parameter RV_PLIC_PRIO0_OFFSET = 9'h 8;
parameter RV_PLIC_PRIO1_OFFSET = 9'h c;
parameter RV_PLIC_PRIO2_OFFSET = 9'h 10;
parameter RV_PLIC_PRIO3_OFFSET = 9'h 14;
parameter RV_PLIC_PRIO4_OFFSET = 9'h 18;
parameter RV_PLIC_PRIO5_OFFSET = 9'h 1c;
parameter RV_PLIC_PRIO6_OFFSET = 9'h 20;
parameter RV_PLIC_PRIO7_OFFSET = 9'h 24;
parameter RV_PLIC_PRIO8_OFFSET = 9'h 28;
parameter RV_PLIC_PRIO9_OFFSET = 9'h 2c;
parameter RV_PLIC_PRIO10_OFFSET = 9'h 30;
parameter RV_PLIC_PRIO11_OFFSET = 9'h 34;
parameter RV_PLIC_PRIO12_OFFSET = 9'h 38;
parameter RV_PLIC_PRIO13_OFFSET = 9'h 3c;
parameter RV_PLIC_PRIO14_OFFSET = 9'h 40;
parameter RV_PLIC_PRIO15_OFFSET = 9'h 44;
parameter RV_PLIC_PRIO16_OFFSET = 9'h 48;
parameter RV_PLIC_PRIO17_OFFSET = 9'h 4c;
parameter RV_PLIC_PRIO18_OFFSET = 9'h 50;
parameter RV_PLIC_PRIO19_OFFSET = 9'h 54;
parameter RV_PLIC_PRIO20_OFFSET = 9'h 58;
parameter RV_PLIC_PRIO21_OFFSET = 9'h 5c;
parameter RV_PLIC_PRIO22_OFFSET = 9'h 60;
parameter RV_PLIC_PRIO23_OFFSET = 9'h 64;
parameter RV_PLIC_PRIO24_OFFSET = 9'h 68;
parameter RV_PLIC_PRIO25_OFFSET = 9'h 6c;
parameter RV_PLIC_PRIO26_OFFSET = 9'h 70;
parameter RV_PLIC_PRIO27_OFFSET = 9'h 74;
parameter RV_PLIC_PRIO28_OFFSET = 9'h 78;
parameter RV_PLIC_PRIO29_OFFSET = 9'h 7c;
parameter RV_PLIC_PRIO30_OFFSET = 9'h 80;
parameter RV_PLIC_PRIO31_OFFSET = 9'h 84;
parameter RV_PLIC_IE0_OFFSET = 9'h 88;
parameter RV_PLIC_THRESHOLD0_OFFSET = 9'h 8c;
parameter RV_PLIC_CC0_OFFSET = 9'h 90;
endpackage
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
module rv_plic_reg_top (
input clk_i,
input rst_ni,
// Below Regster interface can be changed
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg // Read
);
import rv_plic_reg_pkg::* ;
localparam AW = 9;
localparam IW = $bits(tl_i.a_source);
localparam DW = 32;
localparam DBW = DW/8; // Byte Width
localparam logic [$clog2($clog2(DBW)+1)-1:0] FSZ = $clog2(DBW); // Full Size 2^(FSZ) = DBW;
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic reg_valid;
logic [DW-1:0] reg_rdata;
logic tl_malformed, tl_addrmiss;
// Bus signals
tlul_pkg::tl_d_op_e rsp_opcode; // AccessAck or AccessAckData
logic reqready;
logic [IW-1:0] reqid;
logic [IW-1:0] rspid;
logic parity_en;
logic outstanding;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
assign tl_reg_h2d = tl_i;
assign tl_o = tl_reg_d2h;
// TODO(eunchan): Fix it after bus interface is finalized
assign reg_we = tl_reg_h2d.a_valid && tl_reg_d2h.a_ready &&
((tl_reg_h2d.a_opcode == tlul_pkg::PutFullData) ||
(tl_reg_h2d.a_opcode == tlul_pkg::PutPartialData));
assign reg_re = tl_reg_h2d.a_valid && tl_reg_d2h.a_ready && (tl_reg_h2d.a_opcode == tlul_pkg::Get);
assign reg_addr = tl_reg_h2d.a_address[AW-1:0];
assign reg_wdata = tl_reg_h2d.a_data;
assign tl_reg_d2h.d_valid = reg_valid;
assign tl_reg_d2h.d_opcode = rsp_opcode;
assign tl_reg_d2h.d_param = '0;
assign tl_reg_d2h.d_size = FSZ; // always Full Size
assign tl_reg_d2h.d_source = rspid;
assign tl_reg_d2h.d_sink = '0; // Used in TL-C
assign tl_reg_d2h.d_data = reg_rdata;
assign tl_reg_d2h.d_user = '0; // Doesn't allow additional features yet
assign tl_reg_d2h.d_error = tl_malformed | tl_addrmiss;
assign tl_reg_d2h.a_ready = reqready;
assign reqid = tl_reg_h2d.a_source;
assign parity_en = tl_reg_h2d.a_user[8]; // parity is not supported
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
tl_malformed <= 1'b1;
end else if (tl_reg_h2d.a_valid && tl_reg_d2h.a_ready) begin
if ((tl_reg_h2d.a_opcode != tlul_pkg::Get) &&
(tl_reg_h2d.a_opcode != tlul_pkg::PutFullData) &&
(tl_reg_h2d.a_opcode != tlul_pkg::PutPartialData)) begin
tl_malformed <= 1'b1;
// Only allow Full Write with full mask
end else if (tl_reg_h2d.a_size != FSZ || tl_reg_h2d.a_mask != {DBW{1'b1}}) begin
tl_malformed <= 1'b1;
end else if (parity_en == 1'b1) begin
tl_malformed <= 1'b1;
end else begin
tl_malformed <= 1'b0;
end
end
end
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
// 1. Write: No response, so that it can guarantee a request completes a clock after we
// It means, bus_reg_ready doesn't have to be lowered.
// 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
// _____ _____
// a_valid _____/ \_______/ \______
// ___________ _____
// a_ready \_______/ \______ <- ERR though no logic malfunction
// _____________
// d_valid ___________/ \______
// _____
// d_ready ___________________/ \______
//
// Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
always_ff @(posedge clk_i, negedge rst_ni) begin
// Not to accept new request when a request is handling
// #Outstanding := 1
if (!rst_ni) begin
reqready <= 1'b0;
end else if (reg_we || reg_re) begin
reqready <= 1'b0;
end else if (outstanding == 1'b0) begin
reqready <= 1'b1;
end
end
// Request/ Response ID
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
rspid <= '0;
end else if (reg_we || reg_re) begin
rspid <= reqid;
end
end
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic ip_p0_qs;
logic ip_p1_qs;
logic ip_p2_qs;
logic ip_p3_qs;
logic ip_p4_qs;
logic ip_p5_qs;
logic ip_p6_qs;
logic ip_p7_qs;
logic ip_p8_qs;
logic ip_p9_qs;
logic ip_p10_qs;
logic ip_p11_qs;
logic ip_p12_qs;
logic ip_p13_qs;
logic ip_p14_qs;
logic ip_p15_qs;
logic ip_p16_qs;
logic ip_p17_qs;
logic ip_p18_qs;
logic ip_p19_qs;
logic ip_p20_qs;
logic ip_p21_qs;
logic ip_p22_qs;
logic ip_p23_qs;
logic ip_p24_qs;
logic ip_p25_qs;
logic ip_p26_qs;
logic ip_p27_qs;
logic ip_p28_qs;
logic ip_p29_qs;
logic ip_p30_qs;
logic ip_p31_qs;
logic le_le0_qs;
logic le_le0_wd;
logic le_le0_we;
logic le_le1_qs;
logic le_le1_wd;
logic le_le1_we;
logic le_le2_qs;
logic le_le2_wd;
logic le_le2_we;
logic le_le3_qs;
logic le_le3_wd;
logic le_le3_we;
logic le_le4_qs;
logic le_le4_wd;
logic le_le4_we;
logic le_le5_qs;
logic le_le5_wd;
logic le_le5_we;
logic le_le6_qs;
logic le_le6_wd;
logic le_le6_we;
logic le_le7_qs;
logic le_le7_wd;
logic le_le7_we;
logic le_le8_qs;
logic le_le8_wd;
logic le_le8_we;
logic le_le9_qs;
logic le_le9_wd;
logic le_le9_we;
logic le_le10_qs;
logic le_le10_wd;
logic le_le10_we;
logic le_le11_qs;
logic le_le11_wd;
logic le_le11_we;
logic le_le12_qs;
logic le_le12_wd;
logic le_le12_we;
logic le_le13_qs;
logic le_le13_wd;
logic le_le13_we;
logic le_le14_qs;
logic le_le14_wd;
logic le_le14_we;
logic le_le15_qs;
logic le_le15_wd;
logic le_le15_we;
logic le_le16_qs;
logic le_le16_wd;
logic le_le16_we;
logic le_le17_qs;
logic le_le17_wd;
logic le_le17_we;
logic le_le18_qs;
logic le_le18_wd;
logic le_le18_we;
logic le_le19_qs;
logic le_le19_wd;
logic le_le19_we;
logic le_le20_qs;
logic le_le20_wd;
logic le_le20_we;
logic le_le21_qs;
logic le_le21_wd;
logic le_le21_we;
logic le_le22_qs;
logic le_le22_wd;
logic le_le22_we;
logic le_le23_qs;
logic le_le23_wd;
logic le_le23_we;
logic le_le24_qs;
logic le_le24_wd;
logic le_le24_we;
logic le_le25_qs;
logic le_le25_wd;
logic le_le25_we;
logic le_le26_qs;
logic le_le26_wd;
logic le_le26_we;
logic le_le27_qs;
logic le_le27_wd;
logic le_le27_we;
logic le_le28_qs;
logic le_le28_wd;
logic le_le28_we;
logic le_le29_qs;
logic le_le29_wd;
logic le_le29_we;
logic le_le30_qs;
logic le_le30_wd;
logic le_le30_we;
logic le_le31_qs;
logic le_le31_wd;
logic le_le31_we;
logic [2:0] prio0_qs;
logic [2:0] prio0_wd;
logic prio0_we;
logic [2:0] prio1_qs;
logic [2:0] prio1_wd;
logic prio1_we;
logic [2:0] prio2_qs;
logic [2:0] prio2_wd;
logic prio2_we;
logic [2:0] prio3_qs;
logic [2:0] prio3_wd;
logic prio3_we;
logic [2:0] prio4_qs;
logic [2:0] prio4_wd;
logic prio4_we;
logic [2:0] prio5_qs;
logic [2:0] prio5_wd;
logic prio5_we;
logic [2:0] prio6_qs;
logic [2:0] prio6_wd;
logic prio6_we;
logic [2:0] prio7_qs;
logic [2:0] prio7_wd;
logic prio7_we;
logic [2:0] prio8_qs;
logic [2:0] prio8_wd;
logic prio8_we;
logic [2:0] prio9_qs;
logic [2:0] prio9_wd;
logic prio9_we;
logic [2:0] prio10_qs;
logic [2:0] prio10_wd;
logic prio10_we;
logic [2:0] prio11_qs;
logic [2:0] prio11_wd;
logic prio11_we;
logic [2:0] prio12_qs;
logic [2:0] prio12_wd;
logic prio12_we;
logic [2:0] prio13_qs;
logic [2:0] prio13_wd;
logic prio13_we;
logic [2:0] prio14_qs;
logic [2:0] prio14_wd;
logic prio14_we;
logic [2:0] prio15_qs;
logic [2:0] prio15_wd;
logic prio15_we;
logic [2:0] prio16_qs;
logic [2:0] prio16_wd;
logic prio16_we;
logic [2:0] prio17_qs;
logic [2:0] prio17_wd;
logic prio17_we;
logic [2:0] prio18_qs;
logic [2:0] prio18_wd;
logic prio18_we;
logic [2:0] prio19_qs;
logic [2:0] prio19_wd;
logic prio19_we;
logic [2:0] prio20_qs;
logic [2:0] prio20_wd;
logic prio20_we;
logic [2:0] prio21_qs;
logic [2:0] prio21_wd;
logic prio21_we;
logic [2:0] prio22_qs;
logic [2:0] prio22_wd;
logic prio22_we;
logic [2:0] prio23_qs;
logic [2:0] prio23_wd;
logic prio23_we;
logic [2:0] prio24_qs;
logic [2:0] prio24_wd;
logic prio24_we;
logic [2:0] prio25_qs;
logic [2:0] prio25_wd;
logic prio25_we;
logic [2:0] prio26_qs;
logic [2:0] prio26_wd;
logic prio26_we;
logic [2:0] prio27_qs;
logic [2:0] prio27_wd;
logic prio27_we;
logic [2:0] prio28_qs;
logic [2:0] prio28_wd;
logic prio28_we;
logic [2:0] prio29_qs;
logic [2:0] prio29_wd;
logic prio29_we;
logic [2:0] prio30_qs;
logic [2:0] prio30_wd;
logic prio30_we;
logic [2:0] prio31_qs;
logic [2:0] prio31_wd;
logic prio31_we;
logic ie0_e0_qs;
logic ie0_e0_wd;
logic ie0_e0_we;
logic ie0_e1_qs;
logic ie0_e1_wd;
logic ie0_e1_we;
logic ie0_e2_qs;
logic ie0_e2_wd;
logic ie0_e2_we;
logic ie0_e3_qs;
logic ie0_e3_wd;
logic ie0_e3_we;
logic ie0_e4_qs;
logic ie0_e4_wd;
logic ie0_e4_we;
logic ie0_e5_qs;
logic ie0_e5_wd;
logic ie0_e5_we;
logic ie0_e6_qs;
logic ie0_e6_wd;
logic ie0_e6_we;
logic ie0_e7_qs;
logic ie0_e7_wd;
logic ie0_e7_we;
logic ie0_e8_qs;
logic ie0_e8_wd;
logic ie0_e8_we;
logic ie0_e9_qs;
logic ie0_e9_wd;
logic ie0_e9_we;
logic ie0_e10_qs;
logic ie0_e10_wd;
logic ie0_e10_we;
logic ie0_e11_qs;
logic ie0_e11_wd;
logic ie0_e11_we;
logic ie0_e12_qs;
logic ie0_e12_wd;
logic ie0_e12_we;
logic ie0_e13_qs;
logic ie0_e13_wd;
logic ie0_e13_we;
logic ie0_e14_qs;
logic ie0_e14_wd;
logic ie0_e14_we;
logic ie0_e15_qs;
logic ie0_e15_wd;
logic ie0_e15_we;
logic ie0_e16_qs;
logic ie0_e16_wd;
logic ie0_e16_we;
logic ie0_e17_qs;
logic ie0_e17_wd;
logic ie0_e17_we;
logic ie0_e18_qs;
logic ie0_e18_wd;
logic ie0_e18_we;
logic ie0_e19_qs;
logic ie0_e19_wd;
logic ie0_e19_we;
logic ie0_e20_qs;
logic ie0_e20_wd;
logic ie0_e20_we;
logic ie0_e21_qs;
logic ie0_e21_wd;
logic ie0_e21_we;
logic ie0_e22_qs;
logic ie0_e22_wd;
logic ie0_e22_we;
logic ie0_e23_qs;
logic ie0_e23_wd;
logic ie0_e23_we;
logic ie0_e24_qs;
logic ie0_e24_wd;
logic ie0_e24_we;
logic ie0_e25_qs;
logic ie0_e25_wd;
logic ie0_e25_we;
logic ie0_e26_qs;
logic ie0_e26_wd;
logic ie0_e26_we;
logic ie0_e27_qs;
logic ie0_e27_wd;
logic ie0_e27_we;
logic ie0_e28_qs;
logic ie0_e28_wd;
logic ie0_e28_we;
logic ie0_e29_qs;
logic ie0_e29_wd;
logic ie0_e29_we;
logic ie0_e30_qs;
logic ie0_e30_wd;
logic ie0_e30_we;
logic ie0_e31_qs;
logic ie0_e31_wd;
logic ie0_e31_we;
logic [2:0] threshold0_qs;
logic [2:0] threshold0_wd;
logic threshold0_we;
logic [5:0] cc0_qs;
logic [5:0] cc0_wd;
logic cc0_we;
logic cc0_re;
// Register instances
// R[ip]: V(False)
// F[p0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p0.de),
.d (hw2reg.ip.p0.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p0_qs)
);
// F[p1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p1.de),
.d (hw2reg.ip.p1.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p1_qs)
);
// F[p2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p2.de),
.d (hw2reg.ip.p2.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p2_qs)
);
// F[p3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p3.de),
.d (hw2reg.ip.p3.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p3_qs)
);
// F[p4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p4.de),
.d (hw2reg.ip.p4.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p4_qs)
);
// F[p5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p5.de),
.d (hw2reg.ip.p5.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p5_qs)
);
// F[p6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p6.de),
.d (hw2reg.ip.p6.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p6_qs)
);
// F[p7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p7.de),
.d (hw2reg.ip.p7.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p7_qs)
);
// F[p8]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p8.de),
.d (hw2reg.ip.p8.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p8_qs)
);
// F[p9]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p9.de),
.d (hw2reg.ip.p9.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p9_qs)
);
// F[p10]: 10:10
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p10.de),
.d (hw2reg.ip.p10.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p10_qs)
);
// F[p11]: 11:11
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p11.de),
.d (hw2reg.ip.p11.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p11_qs)
);
// F[p12]: 12:12
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p12.de),
.d (hw2reg.ip.p12.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p12_qs)
);
// F[p13]: 13:13
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p13.de),
.d (hw2reg.ip.p13.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p13_qs)
);
// F[p14]: 14:14
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p14.de),
.d (hw2reg.ip.p14.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p14_qs)
);
// F[p15]: 15:15
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p15.de),
.d (hw2reg.ip.p15.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p15_qs)
);
// F[p16]: 16:16
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p16.de),
.d (hw2reg.ip.p16.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p16_qs)
);
// F[p17]: 17:17
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p17.de),
.d (hw2reg.ip.p17.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p17_qs)
);
// F[p18]: 18:18
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p18.de),
.d (hw2reg.ip.p18.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p18_qs)
);
// F[p19]: 19:19
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p19.de),
.d (hw2reg.ip.p19.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p19_qs)
);
// F[p20]: 20:20
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p20.de),
.d (hw2reg.ip.p20.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p20_qs)
);
// F[p21]: 21:21
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p21.de),
.d (hw2reg.ip.p21.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p21_qs)
);
// F[p22]: 22:22
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p22.de),
.d (hw2reg.ip.p22.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p22_qs)
);
// F[p23]: 23:23
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p23.de),
.d (hw2reg.ip.p23.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p23_qs)
);
// F[p24]: 24:24
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p24.de),
.d (hw2reg.ip.p24.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p24_qs)
);
// F[p25]: 25:25
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p25.de),
.d (hw2reg.ip.p25.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p25_qs)
);
// F[p26]: 26:26
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p26.de),
.d (hw2reg.ip.p26.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p26_qs)
);
// F[p27]: 27:27
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p27.de),
.d (hw2reg.ip.p27.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p27_qs)
);
// F[p28]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p28.de),
.d (hw2reg.ip.p28.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p28_qs)
);
// F[p29]: 29:29
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p29.de),
.d (hw2reg.ip.p29.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p29_qs)
);
// F[p30]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p30.de),
.d (hw2reg.ip.p30.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p30_qs)
);
// F[p31]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (1'b0),
.wd ('0 ),
// from internal hardware
.de (hw2reg.ip.p31.de),
.d (hw2reg.ip.p31.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (ip_p31_qs)
);
// R[le]: V(False)
// F[le0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le0_we),
.wd (le_le0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le0.q ),
// to register interface (read)
.qs (le_le0_qs)
);
// F[le1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le1_we),
.wd (le_le1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le1.q ),
// to register interface (read)
.qs (le_le1_qs)
);
// F[le2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le2_we),
.wd (le_le2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le2.q ),
// to register interface (read)
.qs (le_le2_qs)
);
// F[le3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le3_we),
.wd (le_le3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le3.q ),
// to register interface (read)
.qs (le_le3_qs)
);
// F[le4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le4_we),
.wd (le_le4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le4.q ),
// to register interface (read)
.qs (le_le4_qs)
);
// F[le5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le5_we),
.wd (le_le5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le5.q ),
// to register interface (read)
.qs (le_le5_qs)
);
// F[le6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le6_we),
.wd (le_le6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le6.q ),
// to register interface (read)
.qs (le_le6_qs)
);
// F[le7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le7_we),
.wd (le_le7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le7.q ),
// to register interface (read)
.qs (le_le7_qs)
);
// F[le8]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le8_we),
.wd (le_le8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le8.q ),
// to register interface (read)
.qs (le_le8_qs)
);
// F[le9]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le9_we),
.wd (le_le9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le9.q ),
// to register interface (read)
.qs (le_le9_qs)
);
// F[le10]: 10:10
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le10_we),
.wd (le_le10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le10.q ),
// to register interface (read)
.qs (le_le10_qs)
);
// F[le11]: 11:11
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le11_we),
.wd (le_le11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le11.q ),
// to register interface (read)
.qs (le_le11_qs)
);
// F[le12]: 12:12
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le12_we),
.wd (le_le12_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le12.q ),
// to register interface (read)
.qs (le_le12_qs)
);
// F[le13]: 13:13
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le13_we),
.wd (le_le13_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le13.q ),
// to register interface (read)
.qs (le_le13_qs)
);
// F[le14]: 14:14
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le14_we),
.wd (le_le14_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le14.q ),
// to register interface (read)
.qs (le_le14_qs)
);
// F[le15]: 15:15
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le15_we),
.wd (le_le15_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le15.q ),
// to register interface (read)
.qs (le_le15_qs)
);
// F[le16]: 16:16
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le16_we),
.wd (le_le16_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le16.q ),
// to register interface (read)
.qs (le_le16_qs)
);
// F[le17]: 17:17
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le17_we),
.wd (le_le17_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le17.q ),
// to register interface (read)
.qs (le_le17_qs)
);
// F[le18]: 18:18
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le18_we),
.wd (le_le18_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le18.q ),
// to register interface (read)
.qs (le_le18_qs)
);
// F[le19]: 19:19
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le19_we),
.wd (le_le19_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le19.q ),
// to register interface (read)
.qs (le_le19_qs)
);
// F[le20]: 20:20
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le20_we),
.wd (le_le20_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le20.q ),
// to register interface (read)
.qs (le_le20_qs)
);
// F[le21]: 21:21
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le21_we),
.wd (le_le21_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le21.q ),
// to register interface (read)
.qs (le_le21_qs)
);
// F[le22]: 22:22
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le22_we),
.wd (le_le22_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le22.q ),
// to register interface (read)
.qs (le_le22_qs)
);
// F[le23]: 23:23
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le23_we),
.wd (le_le23_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le23.q ),
// to register interface (read)
.qs (le_le23_qs)
);
// F[le24]: 24:24
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le24_we),
.wd (le_le24_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le24.q ),
// to register interface (read)
.qs (le_le24_qs)
);
// F[le25]: 25:25
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le25_we),
.wd (le_le25_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le25.q ),
// to register interface (read)
.qs (le_le25_qs)
);
// F[le26]: 26:26
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le26_we),
.wd (le_le26_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le26.q ),
// to register interface (read)
.qs (le_le26_qs)
);
// F[le27]: 27:27
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le27_we),
.wd (le_le27_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le27.q ),
// to register interface (read)
.qs (le_le27_qs)
);
// F[le28]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le28_we),
.wd (le_le28_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le28.q ),
// to register interface (read)
.qs (le_le28_qs)
);
// F[le29]: 29:29
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le29_we),
.wd (le_le29_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le29.q ),
// to register interface (read)
.qs (le_le29_qs)
);
// F[le30]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le30_we),
.wd (le_le30_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le30.q ),
// to register interface (read)
.qs (le_le30_qs)
);
// F[le31]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (le_le31_we),
.wd (le_le31_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.le.le31.q ),
// to register interface (read)
.qs (le_le31_qs)
);
// R[prio0]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio0_we),
.wd (prio0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio0.q ),
// to register interface (read)
.qs (prio0_qs)
);
// R[prio1]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio1_we),
.wd (prio1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio1.q ),
// to register interface (read)
.qs (prio1_qs)
);
// R[prio2]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio2_we),
.wd (prio2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio2.q ),
// to register interface (read)
.qs (prio2_qs)
);
// R[prio3]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio3_we),
.wd (prio3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio3.q ),
// to register interface (read)
.qs (prio3_qs)
);
// R[prio4]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio4_we),
.wd (prio4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio4.q ),
// to register interface (read)
.qs (prio4_qs)
);
// R[prio5]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio5_we),
.wd (prio5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio5.q ),
// to register interface (read)
.qs (prio5_qs)
);
// R[prio6]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio6_we),
.wd (prio6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio6.q ),
// to register interface (read)
.qs (prio6_qs)
);
// R[prio7]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio7_we),
.wd (prio7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio7.q ),
// to register interface (read)
.qs (prio7_qs)
);
// R[prio8]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio8_we),
.wd (prio8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio8.q ),
// to register interface (read)
.qs (prio8_qs)
);
// R[prio9]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio9_we),
.wd (prio9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio9.q ),
// to register interface (read)
.qs (prio9_qs)
);
// R[prio10]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio10_we),
.wd (prio10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio10.q ),
// to register interface (read)
.qs (prio10_qs)
);
// R[prio11]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio11_we),
.wd (prio11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio11.q ),
// to register interface (read)
.qs (prio11_qs)
);
// R[prio12]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio12_we),
.wd (prio12_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio12.q ),
// to register interface (read)
.qs (prio12_qs)
);
// R[prio13]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio13_we),
.wd (prio13_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio13.q ),
// to register interface (read)
.qs (prio13_qs)
);
// R[prio14]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio14_we),
.wd (prio14_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio14.q ),
// to register interface (read)
.qs (prio14_qs)
);
// R[prio15]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio15_we),
.wd (prio15_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio15.q ),
// to register interface (read)
.qs (prio15_qs)
);
// R[prio16]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio16_we),
.wd (prio16_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio16.q ),
// to register interface (read)
.qs (prio16_qs)
);
// R[prio17]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio17_we),
.wd (prio17_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio17.q ),
// to register interface (read)
.qs (prio17_qs)
);
// R[prio18]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio18_we),
.wd (prio18_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio18.q ),
// to register interface (read)
.qs (prio18_qs)
);
// R[prio19]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio19_we),
.wd (prio19_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio19.q ),
// to register interface (read)
.qs (prio19_qs)
);
// R[prio20]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio20_we),
.wd (prio20_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio20.q ),
// to register interface (read)
.qs (prio20_qs)
);
// R[prio21]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio21_we),
.wd (prio21_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio21.q ),
// to register interface (read)
.qs (prio21_qs)
);
// R[prio22]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio22_we),
.wd (prio22_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio22.q ),
// to register interface (read)
.qs (prio22_qs)
);
// R[prio23]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio23_we),
.wd (prio23_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio23.q ),
// to register interface (read)
.qs (prio23_qs)
);
// R[prio24]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio24_we),
.wd (prio24_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio24.q ),
// to register interface (read)
.qs (prio24_qs)
);
// R[prio25]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio25_we),
.wd (prio25_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio25.q ),
// to register interface (read)
.qs (prio25_qs)
);
// R[prio26]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio26_we),
.wd (prio26_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio26.q ),
// to register interface (read)
.qs (prio26_qs)
);
// R[prio27]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio27_we),
.wd (prio27_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio27.q ),
// to register interface (read)
.qs (prio27_qs)
);
// R[prio28]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio28_we),
.wd (prio28_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio28.q ),
// to register interface (read)
.qs (prio28_qs)
);
// R[prio29]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio29_we),
.wd (prio29_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio29.q ),
// to register interface (read)
.qs (prio29_qs)
);
// R[prio30]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio30_we),
.wd (prio30_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio30.q ),
// to register interface (read)
.qs (prio30_qs)
);
// R[prio31]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (prio31_we),
.wd (prio31_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.prio31.q ),
// to register interface (read)
.qs (prio31_qs)
);
// R[ie0]: V(False)
// F[e0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e0_we),
.wd (ie0_e0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e0.q ),
// to register interface (read)
.qs (ie0_e0_qs)
);
// F[e1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e1_we),
.wd (ie0_e1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e1.q ),
// to register interface (read)
.qs (ie0_e1_qs)
);
// F[e2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e2_we),
.wd (ie0_e2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e2.q ),
// to register interface (read)
.qs (ie0_e2_qs)
);
// F[e3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e3_we),
.wd (ie0_e3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e3.q ),
// to register interface (read)
.qs (ie0_e3_qs)
);
// F[e4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e4_we),
.wd (ie0_e4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e4.q ),
// to register interface (read)
.qs (ie0_e4_qs)
);
// F[e5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e5_we),
.wd (ie0_e5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e5.q ),
// to register interface (read)
.qs (ie0_e5_qs)
);
// F[e6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e6_we),
.wd (ie0_e6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e6.q ),
// to register interface (read)
.qs (ie0_e6_qs)
);
// F[e7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e7_we),
.wd (ie0_e7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e7.q ),
// to register interface (read)
.qs (ie0_e7_qs)
);
// F[e8]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e8_we),
.wd (ie0_e8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e8.q ),
// to register interface (read)
.qs (ie0_e8_qs)
);
// F[e9]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e9_we),
.wd (ie0_e9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e9.q ),
// to register interface (read)
.qs (ie0_e9_qs)
);
// F[e10]: 10:10
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e10_we),
.wd (ie0_e10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e10.q ),
// to register interface (read)
.qs (ie0_e10_qs)
);
// F[e11]: 11:11
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e11_we),
.wd (ie0_e11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e11.q ),
// to register interface (read)
.qs (ie0_e11_qs)
);
// F[e12]: 12:12
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e12_we),
.wd (ie0_e12_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e12.q ),
// to register interface (read)
.qs (ie0_e12_qs)
);
// F[e13]: 13:13
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e13_we),
.wd (ie0_e13_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e13.q ),
// to register interface (read)
.qs (ie0_e13_qs)
);
// F[e14]: 14:14
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e14_we),
.wd (ie0_e14_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e14.q ),
// to register interface (read)
.qs (ie0_e14_qs)
);
// F[e15]: 15:15
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e15_we),
.wd (ie0_e15_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e15.q ),
// to register interface (read)
.qs (ie0_e15_qs)
);
// F[e16]: 16:16
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e16_we),
.wd (ie0_e16_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e16.q ),
// to register interface (read)
.qs (ie0_e16_qs)
);
// F[e17]: 17:17
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e17_we),
.wd (ie0_e17_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e17.q ),
// to register interface (read)
.qs (ie0_e17_qs)
);
// F[e18]: 18:18
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e18_we),
.wd (ie0_e18_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e18.q ),
// to register interface (read)
.qs (ie0_e18_qs)
);
// F[e19]: 19:19
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e19_we),
.wd (ie0_e19_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e19.q ),
// to register interface (read)
.qs (ie0_e19_qs)
);
// F[e20]: 20:20
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e20_we),
.wd (ie0_e20_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e20.q ),
// to register interface (read)
.qs (ie0_e20_qs)
);
// F[e21]: 21:21
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e21_we),
.wd (ie0_e21_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e21.q ),
// to register interface (read)
.qs (ie0_e21_qs)
);
// F[e22]: 22:22
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e22_we),
.wd (ie0_e22_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e22.q ),
// to register interface (read)
.qs (ie0_e22_qs)
);
// F[e23]: 23:23
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e23_we),
.wd (ie0_e23_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e23.q ),
// to register interface (read)
.qs (ie0_e23_qs)
);
// F[e24]: 24:24
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e24_we),
.wd (ie0_e24_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e24.q ),
// to register interface (read)
.qs (ie0_e24_qs)
);
// F[e25]: 25:25
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e25_we),
.wd (ie0_e25_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e25.q ),
// to register interface (read)
.qs (ie0_e25_qs)
);
// F[e26]: 26:26
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e26_we),
.wd (ie0_e26_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e26.q ),
// to register interface (read)
.qs (ie0_e26_qs)
);
// F[e27]: 27:27
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e27_we),
.wd (ie0_e27_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e27.q ),
// to register interface (read)
.qs (ie0_e27_qs)
);
// F[e28]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e28_we),
.wd (ie0_e28_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e28.q ),
// to register interface (read)
.qs (ie0_e28_qs)
);
// F[e29]: 29:29
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e29_we),
.wd (ie0_e29_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e29.q ),
// to register interface (read)
.qs (ie0_e29_qs)
);
// F[e30]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e30_we),
.wd (ie0_e30_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e30.q ),
// to register interface (read)
.qs (ie0_e30_qs)
);
// F[e31]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (ie0_e31_we),
.wd (ie0_e31_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.ie0.e31.q ),
// to register interface (read)
.qs (ie0_e31_qs)
);
// R[threshold0]: V(False)
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_threshold0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (threshold0_we),
.wd (threshold0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.threshold0.q ),
// to register interface (read)
.qs (threshold0_qs)
);
// R[cc0]: V(True)
prim_subreg_ext #(
.DW (6)
) u_cc0 (
.re (cc0_re),
.we (cc0_we),
.wd (cc0_wd),
.d (hw2reg.cc0.d),
.qre (reg2hw.cc0.re),
.qe (reg2hw.cc0.qe),
.q (reg2hw.cc0.q ),
.qs (cc0_qs)
);
logic [36:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[0] = (reg_addr == RV_PLIC_IP_OFFSET);
addr_hit[1] = (reg_addr == RV_PLIC_LE_OFFSET);
addr_hit[2] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
addr_hit[3] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
addr_hit[4] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
addr_hit[5] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
addr_hit[6] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
addr_hit[7] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
addr_hit[8] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
addr_hit[9] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
addr_hit[10] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
addr_hit[11] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
addr_hit[12] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
addr_hit[13] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
addr_hit[14] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
addr_hit[15] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
addr_hit[16] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
addr_hit[17] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
addr_hit[18] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
addr_hit[19] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
addr_hit[20] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
addr_hit[21] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
addr_hit[22] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
addr_hit[23] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
addr_hit[24] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
addr_hit[25] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
addr_hit[26] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
addr_hit[27] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
addr_hit[28] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
addr_hit[29] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
addr_hit[30] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
addr_hit[31] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
addr_hit[32] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
addr_hit[33] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
addr_hit[34] = (reg_addr == RV_PLIC_IE0_OFFSET);
addr_hit[35] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
addr_hit[36] = (reg_addr == RV_PLIC_CC0_OFFSET);
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
tl_addrmiss <= 1'b0;
end else if (reg_re || reg_we) begin
tl_addrmiss <= ~|addr_hit;
end
end
// Write Enable signal
assign le_le0_we = addr_hit[1] && reg_we;
assign le_le0_wd = reg_wdata[0];
assign le_le1_we = addr_hit[1] && reg_we;
assign le_le1_wd = reg_wdata[1];
assign le_le2_we = addr_hit[1] && reg_we;
assign le_le2_wd = reg_wdata[2];
assign le_le3_we = addr_hit[1] && reg_we;
assign le_le3_wd = reg_wdata[3];
assign le_le4_we = addr_hit[1] && reg_we;
assign le_le4_wd = reg_wdata[4];
assign le_le5_we = addr_hit[1] && reg_we;
assign le_le5_wd = reg_wdata[5];
assign le_le6_we = addr_hit[1] && reg_we;
assign le_le6_wd = reg_wdata[6];
assign le_le7_we = addr_hit[1] && reg_we;
assign le_le7_wd = reg_wdata[7];
assign le_le8_we = addr_hit[1] && reg_we;
assign le_le8_wd = reg_wdata[8];
assign le_le9_we = addr_hit[1] && reg_we;
assign le_le9_wd = reg_wdata[9];
assign le_le10_we = addr_hit[1] && reg_we;
assign le_le10_wd = reg_wdata[10];
assign le_le11_we = addr_hit[1] && reg_we;
assign le_le11_wd = reg_wdata[11];
assign le_le12_we = addr_hit[1] && reg_we;
assign le_le12_wd = reg_wdata[12];
assign le_le13_we = addr_hit[1] && reg_we;
assign le_le13_wd = reg_wdata[13];
assign le_le14_we = addr_hit[1] && reg_we;
assign le_le14_wd = reg_wdata[14];
assign le_le15_we = addr_hit[1] && reg_we;
assign le_le15_wd = reg_wdata[15];
assign le_le16_we = addr_hit[1] && reg_we;
assign le_le16_wd = reg_wdata[16];
assign le_le17_we = addr_hit[1] && reg_we;
assign le_le17_wd = reg_wdata[17];
assign le_le18_we = addr_hit[1] && reg_we;
assign le_le18_wd = reg_wdata[18];
assign le_le19_we = addr_hit[1] && reg_we;
assign le_le19_wd = reg_wdata[19];
assign le_le20_we = addr_hit[1] && reg_we;
assign le_le20_wd = reg_wdata[20];
assign le_le21_we = addr_hit[1] && reg_we;
assign le_le21_wd = reg_wdata[21];
assign le_le22_we = addr_hit[1] && reg_we;
assign le_le22_wd = reg_wdata[22];
assign le_le23_we = addr_hit[1] && reg_we;
assign le_le23_wd = reg_wdata[23];
assign le_le24_we = addr_hit[1] && reg_we;
assign le_le24_wd = reg_wdata[24];
assign le_le25_we = addr_hit[1] && reg_we;
assign le_le25_wd = reg_wdata[25];
assign le_le26_we = addr_hit[1] && reg_we;
assign le_le26_wd = reg_wdata[26];
assign le_le27_we = addr_hit[1] && reg_we;
assign le_le27_wd = reg_wdata[27];
assign le_le28_we = addr_hit[1] && reg_we;
assign le_le28_wd = reg_wdata[28];
assign le_le29_we = addr_hit[1] && reg_we;
assign le_le29_wd = reg_wdata[29];
assign le_le30_we = addr_hit[1] && reg_we;
assign le_le30_wd = reg_wdata[30];
assign le_le31_we = addr_hit[1] && reg_we;
assign le_le31_wd = reg_wdata[31];
assign prio0_we = addr_hit[2] && reg_we;
assign prio0_wd = reg_wdata[2:0];
assign prio1_we = addr_hit[3] && reg_we;
assign prio1_wd = reg_wdata[2:0];
assign prio2_we = addr_hit[4] && reg_we;
assign prio2_wd = reg_wdata[2:0];
assign prio3_we = addr_hit[5] && reg_we;
assign prio3_wd = reg_wdata[2:0];
assign prio4_we = addr_hit[6] && reg_we;
assign prio4_wd = reg_wdata[2:0];
assign prio5_we = addr_hit[7] && reg_we;
assign prio5_wd = reg_wdata[2:0];
assign prio6_we = addr_hit[8] && reg_we;
assign prio6_wd = reg_wdata[2:0];
assign prio7_we = addr_hit[9] && reg_we;
assign prio7_wd = reg_wdata[2:0];
assign prio8_we = addr_hit[10] && reg_we;
assign prio8_wd = reg_wdata[2:0];
assign prio9_we = addr_hit[11] && reg_we;
assign prio9_wd = reg_wdata[2:0];
assign prio10_we = addr_hit[12] && reg_we;
assign prio10_wd = reg_wdata[2:0];
assign prio11_we = addr_hit[13] && reg_we;
assign prio11_wd = reg_wdata[2:0];
assign prio12_we = addr_hit[14] && reg_we;
assign prio12_wd = reg_wdata[2:0];
assign prio13_we = addr_hit[15] && reg_we;
assign prio13_wd = reg_wdata[2:0];
assign prio14_we = addr_hit[16] && reg_we;
assign prio14_wd = reg_wdata[2:0];
assign prio15_we = addr_hit[17] && reg_we;
assign prio15_wd = reg_wdata[2:0];
assign prio16_we = addr_hit[18] && reg_we;
assign prio16_wd = reg_wdata[2:0];
assign prio17_we = addr_hit[19] && reg_we;
assign prio17_wd = reg_wdata[2:0];
assign prio18_we = addr_hit[20] && reg_we;
assign prio18_wd = reg_wdata[2:0];
assign prio19_we = addr_hit[21] && reg_we;
assign prio19_wd = reg_wdata[2:0];
assign prio20_we = addr_hit[22] && reg_we;
assign prio20_wd = reg_wdata[2:0];
assign prio21_we = addr_hit[23] && reg_we;
assign prio21_wd = reg_wdata[2:0];
assign prio22_we = addr_hit[24] && reg_we;
assign prio22_wd = reg_wdata[2:0];
assign prio23_we = addr_hit[25] && reg_we;
assign prio23_wd = reg_wdata[2:0];
assign prio24_we = addr_hit[26] && reg_we;
assign prio24_wd = reg_wdata[2:0];
assign prio25_we = addr_hit[27] && reg_we;
assign prio25_wd = reg_wdata[2:0];
assign prio26_we = addr_hit[28] && reg_we;
assign prio26_wd = reg_wdata[2:0];
assign prio27_we = addr_hit[29] && reg_we;
assign prio27_wd = reg_wdata[2:0];
assign prio28_we = addr_hit[30] && reg_we;
assign prio28_wd = reg_wdata[2:0];
assign prio29_we = addr_hit[31] && reg_we;
assign prio29_wd = reg_wdata[2:0];
assign prio30_we = addr_hit[32] && reg_we;
assign prio30_wd = reg_wdata[2:0];
assign prio31_we = addr_hit[33] && reg_we;
assign prio31_wd = reg_wdata[2:0];
assign ie0_e0_we = addr_hit[34] && reg_we;
assign ie0_e0_wd = reg_wdata[0];
assign ie0_e1_we = addr_hit[34] && reg_we;
assign ie0_e1_wd = reg_wdata[1];
assign ie0_e2_we = addr_hit[34] && reg_we;
assign ie0_e2_wd = reg_wdata[2];
assign ie0_e3_we = addr_hit[34] && reg_we;
assign ie0_e3_wd = reg_wdata[3];
assign ie0_e4_we = addr_hit[34] && reg_we;
assign ie0_e4_wd = reg_wdata[4];
assign ie0_e5_we = addr_hit[34] && reg_we;
assign ie0_e5_wd = reg_wdata[5];
assign ie0_e6_we = addr_hit[34] && reg_we;
assign ie0_e6_wd = reg_wdata[6];
assign ie0_e7_we = addr_hit[34] && reg_we;
assign ie0_e7_wd = reg_wdata[7];
assign ie0_e8_we = addr_hit[34] && reg_we;
assign ie0_e8_wd = reg_wdata[8];
assign ie0_e9_we = addr_hit[34] && reg_we;
assign ie0_e9_wd = reg_wdata[9];
assign ie0_e10_we = addr_hit[34] && reg_we;
assign ie0_e10_wd = reg_wdata[10];
assign ie0_e11_we = addr_hit[34] && reg_we;
assign ie0_e11_wd = reg_wdata[11];
assign ie0_e12_we = addr_hit[34] && reg_we;
assign ie0_e12_wd = reg_wdata[12];
assign ie0_e13_we = addr_hit[34] && reg_we;
assign ie0_e13_wd = reg_wdata[13];
assign ie0_e14_we = addr_hit[34] && reg_we;
assign ie0_e14_wd = reg_wdata[14];
assign ie0_e15_we = addr_hit[34] && reg_we;
assign ie0_e15_wd = reg_wdata[15];
assign ie0_e16_we = addr_hit[34] && reg_we;
assign ie0_e16_wd = reg_wdata[16];
assign ie0_e17_we = addr_hit[34] && reg_we;
assign ie0_e17_wd = reg_wdata[17];
assign ie0_e18_we = addr_hit[34] && reg_we;
assign ie0_e18_wd = reg_wdata[18];
assign ie0_e19_we = addr_hit[34] && reg_we;
assign ie0_e19_wd = reg_wdata[19];
assign ie0_e20_we = addr_hit[34] && reg_we;
assign ie0_e20_wd = reg_wdata[20];
assign ie0_e21_we = addr_hit[34] && reg_we;
assign ie0_e21_wd = reg_wdata[21];
assign ie0_e22_we = addr_hit[34] && reg_we;
assign ie0_e22_wd = reg_wdata[22];
assign ie0_e23_we = addr_hit[34] && reg_we;
assign ie0_e23_wd = reg_wdata[23];
assign ie0_e24_we = addr_hit[34] && reg_we;
assign ie0_e24_wd = reg_wdata[24];
assign ie0_e25_we = addr_hit[34] && reg_we;
assign ie0_e25_wd = reg_wdata[25];
assign ie0_e26_we = addr_hit[34] && reg_we;
assign ie0_e26_wd = reg_wdata[26];
assign ie0_e27_we = addr_hit[34] && reg_we;
assign ie0_e27_wd = reg_wdata[27];
assign ie0_e28_we = addr_hit[34] && reg_we;
assign ie0_e28_wd = reg_wdata[28];
assign ie0_e29_we = addr_hit[34] && reg_we;
assign ie0_e29_wd = reg_wdata[29];
assign ie0_e30_we = addr_hit[34] && reg_we;
assign ie0_e30_wd = reg_wdata[30];
assign ie0_e31_we = addr_hit[34] && reg_we;
assign ie0_e31_wd = reg_wdata[31];
assign threshold0_we = addr_hit[35] && reg_we;
assign threshold0_wd = reg_wdata[2:0];
assign cc0_we = addr_hit[36] && reg_we;
assign cc0_wd = reg_wdata[5:0];
assign cc0_re = addr_hit[36] && reg_re;
// Read data return
logic [DW-1:0] reg_rdata_next;
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = ip_p0_qs;
reg_rdata_next[1] = ip_p1_qs;
reg_rdata_next[2] = ip_p2_qs;
reg_rdata_next[3] = ip_p3_qs;
reg_rdata_next[4] = ip_p4_qs;
reg_rdata_next[5] = ip_p5_qs;
reg_rdata_next[6] = ip_p6_qs;
reg_rdata_next[7] = ip_p7_qs;
reg_rdata_next[8] = ip_p8_qs;
reg_rdata_next[9] = ip_p9_qs;
reg_rdata_next[10] = ip_p10_qs;
reg_rdata_next[11] = ip_p11_qs;
reg_rdata_next[12] = ip_p12_qs;
reg_rdata_next[13] = ip_p13_qs;
reg_rdata_next[14] = ip_p14_qs;
reg_rdata_next[15] = ip_p15_qs;
reg_rdata_next[16] = ip_p16_qs;
reg_rdata_next[17] = ip_p17_qs;
reg_rdata_next[18] = ip_p18_qs;
reg_rdata_next[19] = ip_p19_qs;
reg_rdata_next[20] = ip_p20_qs;
reg_rdata_next[21] = ip_p21_qs;
reg_rdata_next[22] = ip_p22_qs;
reg_rdata_next[23] = ip_p23_qs;
reg_rdata_next[24] = ip_p24_qs;
reg_rdata_next[25] = ip_p25_qs;
reg_rdata_next[26] = ip_p26_qs;
reg_rdata_next[27] = ip_p27_qs;
reg_rdata_next[28] = ip_p28_qs;
reg_rdata_next[29] = ip_p29_qs;
reg_rdata_next[30] = ip_p30_qs;
reg_rdata_next[31] = ip_p31_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = le_le0_qs;
reg_rdata_next[1] = le_le1_qs;
reg_rdata_next[2] = le_le2_qs;
reg_rdata_next[3] = le_le3_qs;
reg_rdata_next[4] = le_le4_qs;
reg_rdata_next[5] = le_le5_qs;
reg_rdata_next[6] = le_le6_qs;
reg_rdata_next[7] = le_le7_qs;
reg_rdata_next[8] = le_le8_qs;
reg_rdata_next[9] = le_le9_qs;
reg_rdata_next[10] = le_le10_qs;
reg_rdata_next[11] = le_le11_qs;
reg_rdata_next[12] = le_le12_qs;
reg_rdata_next[13] = le_le13_qs;
reg_rdata_next[14] = le_le14_qs;
reg_rdata_next[15] = le_le15_qs;
reg_rdata_next[16] = le_le16_qs;
reg_rdata_next[17] = le_le17_qs;
reg_rdata_next[18] = le_le18_qs;
reg_rdata_next[19] = le_le19_qs;
reg_rdata_next[20] = le_le20_qs;
reg_rdata_next[21] = le_le21_qs;
reg_rdata_next[22] = le_le22_qs;
reg_rdata_next[23] = le_le23_qs;
reg_rdata_next[24] = le_le24_qs;
reg_rdata_next[25] = le_le25_qs;
reg_rdata_next[26] = le_le26_qs;
reg_rdata_next[27] = le_le27_qs;
reg_rdata_next[28] = le_le28_qs;
reg_rdata_next[29] = le_le29_qs;
reg_rdata_next[30] = le_le30_qs;
reg_rdata_next[31] = le_le31_qs;
end
addr_hit[2]: begin
reg_rdata_next[2:0] = prio0_qs;
end
addr_hit[3]: begin
reg_rdata_next[2:0] = prio1_qs;
end
addr_hit[4]: begin
reg_rdata_next[2:0] = prio2_qs;
end
addr_hit[5]: begin
reg_rdata_next[2:0] = prio3_qs;
end
addr_hit[6]: begin
reg_rdata_next[2:0] = prio4_qs;
end
addr_hit[7]: begin
reg_rdata_next[2:0] = prio5_qs;
end
addr_hit[8]: begin
reg_rdata_next[2:0] = prio6_qs;
end
addr_hit[9]: begin
reg_rdata_next[2:0] = prio7_qs;
end
addr_hit[10]: begin
reg_rdata_next[2:0] = prio8_qs;
end
addr_hit[11]: begin
reg_rdata_next[2:0] = prio9_qs;
end
addr_hit[12]: begin
reg_rdata_next[2:0] = prio10_qs;
end
addr_hit[13]: begin
reg_rdata_next[2:0] = prio11_qs;
end
addr_hit[14]: begin
reg_rdata_next[2:0] = prio12_qs;
end
addr_hit[15]: begin
reg_rdata_next[2:0] = prio13_qs;
end
addr_hit[16]: begin
reg_rdata_next[2:0] = prio14_qs;
end
addr_hit[17]: begin
reg_rdata_next[2:0] = prio15_qs;
end
addr_hit[18]: begin
reg_rdata_next[2:0] = prio16_qs;
end
addr_hit[19]: begin
reg_rdata_next[2:0] = prio17_qs;
end
addr_hit[20]: begin
reg_rdata_next[2:0] = prio18_qs;
end
addr_hit[21]: begin
reg_rdata_next[2:0] = prio19_qs;
end
addr_hit[22]: begin
reg_rdata_next[2:0] = prio20_qs;
end
addr_hit[23]: begin
reg_rdata_next[2:0] = prio21_qs;
end
addr_hit[24]: begin
reg_rdata_next[2:0] = prio22_qs;
end
addr_hit[25]: begin
reg_rdata_next[2:0] = prio23_qs;
end
addr_hit[26]: begin
reg_rdata_next[2:0] = prio24_qs;
end
addr_hit[27]: begin
reg_rdata_next[2:0] = prio25_qs;
end
addr_hit[28]: begin
reg_rdata_next[2:0] = prio26_qs;
end
addr_hit[29]: begin
reg_rdata_next[2:0] = prio27_qs;
end
addr_hit[30]: begin
reg_rdata_next[2:0] = prio28_qs;
end
addr_hit[31]: begin
reg_rdata_next[2:0] = prio29_qs;
end
addr_hit[32]: begin
reg_rdata_next[2:0] = prio30_qs;
end
addr_hit[33]: begin
reg_rdata_next[2:0] = prio31_qs;
end
addr_hit[34]: begin
reg_rdata_next[0] = ie0_e0_qs;
reg_rdata_next[1] = ie0_e1_qs;
reg_rdata_next[2] = ie0_e2_qs;
reg_rdata_next[3] = ie0_e3_qs;
reg_rdata_next[4] = ie0_e4_qs;
reg_rdata_next[5] = ie0_e5_qs;
reg_rdata_next[6] = ie0_e6_qs;
reg_rdata_next[7] = ie0_e7_qs;
reg_rdata_next[8] = ie0_e8_qs;
reg_rdata_next[9] = ie0_e9_qs;
reg_rdata_next[10] = ie0_e10_qs;
reg_rdata_next[11] = ie0_e11_qs;
reg_rdata_next[12] = ie0_e12_qs;
reg_rdata_next[13] = ie0_e13_qs;
reg_rdata_next[14] = ie0_e14_qs;
reg_rdata_next[15] = ie0_e15_qs;
reg_rdata_next[16] = ie0_e16_qs;
reg_rdata_next[17] = ie0_e17_qs;
reg_rdata_next[18] = ie0_e18_qs;
reg_rdata_next[19] = ie0_e19_qs;
reg_rdata_next[20] = ie0_e20_qs;
reg_rdata_next[21] = ie0_e21_qs;
reg_rdata_next[22] = ie0_e22_qs;
reg_rdata_next[23] = ie0_e23_qs;
reg_rdata_next[24] = ie0_e24_qs;
reg_rdata_next[25] = ie0_e25_qs;
reg_rdata_next[26] = ie0_e26_qs;
reg_rdata_next[27] = ie0_e27_qs;
reg_rdata_next[28] = ie0_e28_qs;
reg_rdata_next[29] = ie0_e29_qs;
reg_rdata_next[30] = ie0_e30_qs;
reg_rdata_next[31] = ie0_e31_qs;
end
addr_hit[35]: begin
reg_rdata_next[2:0] = threshold0_qs;
end
addr_hit[36]: begin
reg_rdata_next[5:0] = cc0_qs;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
reg_valid <= 1'b0;
reg_rdata <= '0;
rsp_opcode <= tlul_pkg::AccessAck;
end else if (reg_re || reg_we) begin
// Guarantee to return data in a cycle
reg_valid <= 1'b1;
if (reg_re) begin
reg_rdata <= reg_rdata_next;
rsp_opcode <= tlul_pkg::AccessAckData;
end else begin
rsp_opcode <= tlul_pkg::AccessAck;
end
end else if (tl_reg_h2d.d_ready) begin
reg_valid <= 1'b0;
end
end
// Outstanding: 1 outstanding at a time. Identical to `reg_valid`
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
outstanding <= 1'b0;
end else if (tl_reg_h2d.a_valid && tl_reg_d2h.a_ready) begin
outstanding <= 1'b1;
end else if (tl_reg_d2h.d_valid && tl_reg_h2d.d_ready) begin
outstanding <= 1'b0;
end
end
//pragma translate_off
`ifndef verilator
// Assertion property
// Register Interface
property pulse_prop(sig);
@(posedge clk_i) disable iff (!rst_ni)
$rose(sig) |=> !sig;
endproperty
we_pulse_assert: assert property(pulse_prop(reg_we));
re_pulse_assert: assert property(pulse_prop(reg_re));
property re_after_rv_prop;
@(posedge clk_i) disable iff (!rst_ni)
$rose(reg_re || reg_we) |=> reg_valid;
endproperty
re2rv_assert: assert property(re_after_rv_prop);
property en2addr_prop;
@(posedge clk_i) disable iff (!rst_ni)
(reg_we | reg_re) |-> $onehot0(addr_hit);
endproperty
en2addr_hit_assert: assert property (en2addr_prop);
property reqparity_prop;
@(posedge clk_i) disable iff (!rst_ni)
(tl_i.a_valid & tl_i.a_user[8]) == 1'b0;
endproperty
reqparity_assert: assert property (reqparity_prop);
`endif
//pragma translate_on
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// RISC-V Platform-Level Interrupt Generator for Target
//
// This module basically doing IE & IP based on priority and threshold.
// Keep in mind that increasing MAX_PRIO affects logic size a lot.
module rv_plic_target #(
parameter int N_SOURCE = 32,
parameter int MAX_PRIO = 7,
parameter ALGORITHM = "SEQUENTIAL", // SEQUENTIAL | MATRIX
// Local param (Do not change this through parameter
parameter int unsigned SRCW = $clog2(N_SOURCE+1),
parameter int unsigned PRIOW = $clog2(MAX_PRIO+1) // Bits to represent MAX_PRIO
) (
input clk_i,
input rst_ni,
input [N_SOURCE-1:0] ip,
input [N_SOURCE-1:0] ie,
input [N_SOURCE-1:0][PRIOW-1:0] prio,
input [PRIOW-1:0] threshold,
output logic irq,
output logic [SRCW-1:0] irq_id
);
//always_ff @(posedge clk_i, negedge rst_ni) begin
// if (!rst_ni) begin
// gt_th <= '0;
// end else begin
// for (int i = 0 ; i < N_SOURCE ; i++) begin
// gt_th[i] = (prio[i] > threshold) ? 1'b1 : 1'b0 ;
// end
// end
//end
if (ALGORITHM == "SEQUENTIAL") begin : gen_sequential
// Let first implementation be brute-force
// As N_SOURCE increasing logic depth increases O(logN)
// This approach slows down the simulation.
logic [PRIOW-1:0] max_prio;
logic irq_next;
logic [SRCW-1:0] irq_id_next;
always_comb begin
max_prio = threshold + 1'b1; // Priority strictly greater than threshold
irq_id_next = '0; // default: No Interrupt
irq_next = 1'b0;
for (int i = N_SOURCE-1 ; i >= 0 ; i--) begin
if ((ip[i] & ie[i]) == 1'b1 && prio[i] >= max_prio) begin
max_prio = prio[i];
irq_id_next = SRCW'(i+1);
irq_next = 1'b1;
end
end // for i
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
irq <= 1'b0;
irq_id <= '0;
end else begin
irq <= irq_next;
irq_id <= irq_id_next;
end
end
end else if (ALGORITHM == "MATRIX") begin : gen_mat
// Second trial : N X N matrix
// Set mat[i][j] to 1 if prio[i] >= prio[j] and ip[i] & ie[i] & ip[j] & ie[j]
// Comparator depth is just 1 then logN AND gate then Leading One detector
// It is to find the max value of priority
//
// This uses a lot of comparators: (N x (N-1))/2.
// So if above approach(ALGORITHM 1) meets timing, don't use this algorithm.
logic [N_SOURCE-1:0] is;
logic [N_SOURCE-1:0][N_SOURCE-1:0] mat;
logic [N_SOURCE-1:0] merged_row;
assign is = ip & ie;
always_comb begin
merged_row[N_SOURCE-1] = is[N_SOURCE-1] & (prio[N_SOURCE-1] > threshold);
for (int i = 0 ; i < N_SOURCE-1 ; i++) begin
merged_row[i] = 1'b1;
for (int j = i+1 ; j < N_SOURCE ; j++) begin
mat[i][j] = (prio[i] <= threshold) ? 1'b0 : // No compare if less than TH
(is[i] & is[j]) ? prio[i] >= prio[j] :
(is[i]) ? 1'b 1 : 1'b 0 ;
merged_row[i] = merged_row[i] & mat[i][j]; // all should be 1
end // for j
end // for i
end // always_comb
// Leading One detector
logic [N_SOURCE-1:0] lod;
assign lod = merged_row & (~merged_row + 1'b1);
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
irq <= 1'b0;
irq_id <= '0; // No interrupt
end else if (|lod) begin
// as $onehot0(lod), at most one bit set.
// so, safely run for loop
for (int i = N_SOURCE-1 ; i >= 0 ; i--) begin
if (lod[i] == 1'b1) begin
irq <= 1'b 1;
irq_id <= SRCW'(i + 1);
end
end // for
end else begin
// No pending interrupt
irq <= 1'b0;
irq_id <= '0;
end
end // always_ff
end // ALGORITHM
endmodule
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
package tlul_pkg;
typedef enum logic [2:0] {
PutFullData = 3'h 0,
PutPartialData = 3'h 1,
Get = 3'h 4
} tl_a_op_e;
typedef enum logic [2:0] {
AccessAck = 3'h 0,
AccessAckData = 3'h 1
} tl_d_op_e;
typedef struct packed {
logic a_valid;
tl_a_op_e a_opcode;
logic [2:0] a_param;
logic [top_pkg::TL_SZW-1:0] a_size;
logic [top_pkg::TL_AIW-1:0] a_source;
logic [top_pkg::TL_AW-1:0] a_address;
logic [top_pkg::TL_DBW-1:0] a_mask;
logic [top_pkg::TL_DW-1:0] a_data;
logic [top_pkg::TL_AUW-1:0] a_user;
logic d_ready;
} tl_h2d_t;
typedef struct packed {
logic d_valid;
tl_d_op_e d_opcode;
logic [2:0] d_param;
logic [top_pkg::TL_SZW-1:0] d_size; // Bouncing back a_size
logic [top_pkg::TL_AIW-1:0] d_source;
logic [top_pkg::TL_DIW-1:0] d_sink;
logic [top_pkg::TL_DW-1:0] d_data;
logic [top_pkg::TL_DUW-1:0] d_user;
logic d_error;
logic a_ready;
} tl_d2h_t;
endpackage
|
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
package top_pkg;
localparam TL_AW=32;
localparam TL_DW=32;
localparam TL_AIW=8; // a_source, d_source
localparam TL_DIW=1; // d_sink
localparam TL_AUW=16; // a_user
localparam TL_DUW=16; // d_user
localparam TL_DBW=(TL_DW>>3);
localparam TL_SZW=$clog2($clog2(TL_DBW)+1);
endpackage
|
# EditorConfig (http://editorconfig.org/)
root = true
# Default Settings
[*]
charset = utf-8
end_of_line = lf
indent_size = 4
indent_style = space
insert_final_newline = true
tab_width = 4
trim_trailing_whitespace = true
max_line_length = 100
[Makefile]
indent_style = tab
[*.yml]
indent_size = 2
|
gitdir: ../../../.git/modules/corev_apu/src/axi_riscv_atomics
|
package:
name: axi_riscv_atomics
authors: ["Andreas Kurth <akurth@iis.ee.ethz.ch>", "Samuel Riedel <sriedel@student.ethz.ch>"]
dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.6.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.10.0 }
sources:
# Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
# Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
# etc. Files within a level are ordered alphabetically.
# Level 0
- src/axi_res_tbl.sv
- src/axi_riscv_amos_alu.sv
# Level 1
- src/axi_riscv_amos.sv
- src/axi_riscv_lrsc.sv
# Level 2
- src/axi_riscv_atomics.sv
- src/axi_riscv_lrsc_wrap.sv
# Level 3
- src/axi_riscv_atomics_wrap.sv
|
# Change Log
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/), and this project adheres to
[Semantic Versioning](http://semver.org).
## Unreleased
## v0.2.2 - 2019-02-28
### Changed
- Update `axi` dependency to v0.6.0 (from an intermediary commit).
## v0.2.1 - 2019-02-25
### Fixed
- `axi_riscv_amos`: Fixed timing of R response (#10).
## v0.2.0 - 2019-02-21
### Changed
- Made SystemVerilog interfaces optional. Top-level modules now expose a flattened port list, and
an optional wrapper provides SystemVerilog interfaces. This improves compatibility with tools
that have poor support for SystemVerilog interfaces.
## Fixed
- `axi_riscv_amos`: Fixed burst, cache, lock, prot, qos, region, size, and user of ARs.
## v0.1.1 - 2019-02-20
### Fixed
- `axi_res_tbl`: Fixed assignments in `always_ff` process.
- `axi_riscv_amos`: Removed unused register.
- `axi_riscv_amos`: Added missing default assignments in AW FSM.
- `axi_riscv_amos`: Fixed sign extension of 32bit AMOs on 64bit ALU.
- `axi_riscv_amos`: Removed unused signals.
- `axi_riscv_atomics_wrap`: Fixed syntax of interface signal assignments.
- `axi_riscv_lrsc`: Added missing feedthrough of `aw_atop`.
- `axi_riscv_lrsc`: Fixed assignments in `always_ff` process.
- `axi_riscv_lrsc_wrap`: Fixed syntax of interface signal assignments.
### Added
- Added simple standalone synthesis bench for `axi_riscv_atomics`.
- Added simple standalone synthesis bench for `axi_riscv_lrsc`.
## v0.1.0 - 2019-02-19
Initial public development release
|
# AXI Adapter(s) for RISC-V Atomic Operations
**Disclaimer**: This repository is under active development and not yet stabilized. Use only if you
know what you are doing and are prepared to adapt to wide-reaching changes as the project evolves.
Limited support is available for the latest v0.x version, but only for the latest, and we give no
backwards compatibility guarantees for versions before v1.0.
The modules in this repository implement atomic operations (AMOs) for RISC-V processors ("A"
extension version 2.0) on the AXI protocol. The modules adheres to the RISC-V Weak Memory Ordering
(RVWMO) memory consistency model (version 0.1).
## Usage
Place one of the following modules in your memory hierarchy between an AXI master and slave, where
the slave owns a particular memory location (e.g., exclusive access to a memory controller or
adherence to a cache coherency protocol). Choose depending on your needs:
- `axi_riscv_lrsc` tracks memory reservations for LR/SC, forwards only successful SCs, and responds
accordingly. This is sufficient to support LR/SC if the processor encodes them as AXI exclusive
memory accesses. Downstream modules do not have to support AXI exclusive memory accesses.
- `axi_riscv_atomics` implements all RISC-V AMOs in addition to LR/SC. The processor needs to
encode RISC-V AMOs as AXI atomic transactions (`AtomicSwap` for `AMOSWAP`, `AtomicLoad` with the
corresponding opcode for all other AMOs). This is sufficient to support the entire RISC-V "A"
extension. Downstream modules do not have to support AXI atomic transactions or exclusive
memory accesses.
For each of those modules we additionally provide a wrapper (`_wrap` filename suffix) that exposes
SystemVerilog interfaces instead of `logic` ports.
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// AXI Reservation Table
module axi_res_tbl #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 0
) (
input logic clk_i,
input logic rst_ni,
input logic [AXI_ADDR_WIDTH-1:0] clr_addr_i,
input logic clr_req_i,
output logic clr_gnt_o,
input logic [AXI_ADDR_WIDTH-1:0] set_addr_i,
input logic [AXI_ID_WIDTH-1:0] set_id_i,
input logic set_req_i,
output logic set_gnt_o,
input logic [AXI_ADDR_WIDTH-1:0] check_addr_i,
input logic [AXI_ID_WIDTH-1:0] check_id_i,
output logic check_res_o,
input logic check_req_i,
output logic check_gnt_o
);
localparam integer N_IDS = 2**AXI_ID_WIDTH;
// Declarations of Signals and Types
logic [N_IDS-1:0][AXI_ADDR_WIDTH-1:0] tbl_d, tbl_q;
logic clr,
set;
generate for (genvar i = 0; i < N_IDS; ++i) begin: gen_tbl
always_comb begin
tbl_d[i] = tbl_q[i];
if (set && i == set_id_i) begin
tbl_d[i] = set_addr_i;
end else if (clr && tbl_q[i] == clr_addr_i) begin
tbl_d[i] = '0;
end
end
end endgenerate
// Table-Managing Logic
always_comb begin
clr = 1'b0;
set = 1'b0;
clr_gnt_o = 1'b0;
set_gnt_o = 1'b0;
check_res_o = 1'b0;
check_gnt_o = 1'b0;
if (clr_req_i) begin
clr = 1'b1;
clr_gnt_o = 1'b1;
end else if (set_req_i) begin
set = 1'b1;
set_gnt_o = 1'b1;
end else if (check_req_i) begin
check_res_o = (tbl_q[check_id_i] == check_addr_i);
check_gnt_o = 1'b1;
end
end
// Registers
always_ff @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
tbl_q <= '0;
end else begin
tbl_q <= tbl_d;
end
end
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: validate_params
assert (AXI_ADDR_WIDTH > 0)
else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!");
assert (AXI_ID_WIDTH > 0)
else $fatal(1, "AXI_ID_WIDTH must be greater than 0!");
end
`endif
// pragma translate_on
endmodule
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// AXI RISC-V Atomic Operations (AMOs) Adapter
//
// This adapter implements atomic memory operations in accordance with the RVWMO memory consistency
// model.
//
// Interface notes:
// - This module has combinational paths between AXI inputs and outputs for minimum latency. Add
// slices upstream or downstream or in both directions if combinatorial paths become too long.
// The module adheres to the AXI ready/valid dependency specification to prevent combinatorial
// loops.
module axi_riscv_amos #(
// AXI Parameters
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
// Maximum number of AXI write transactions outstanding at the same time
parameter int unsigned AXI_MAX_WRITE_TXNS = 0,
// Word width of the widest RISC-V processor that can issue requests to this module.
// 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are
// supported if `aw_strb` is set correctly.
parameter int unsigned RISCV_WORD_WIDTH = 0,
/// Derived Parameters (do NOT change manually!)
localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input logic clk_i,
input logic rst_ni,
/// Slave Interface
input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i,
input logic [2:0] slv_aw_prot_i,
input logic [3:0] slv_aw_region_i,
input logic [5:0] slv_aw_atop_i,
input logic [7:0] slv_aw_len_i,
input logic [2:0] slv_aw_size_i,
input logic [1:0] slv_aw_burst_i,
input logic slv_aw_lock_i,
input logic [3:0] slv_aw_cache_i,
input logic [3:0] slv_aw_qos_i,
input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i,
input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i,
output logic slv_aw_ready_o,
input logic slv_aw_valid_i,
input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i,
input logic [2:0] slv_ar_prot_i,
input logic [3:0] slv_ar_region_i,
input logic [7:0] slv_ar_len_i,
input logic [2:0] slv_ar_size_i,
input logic [1:0] slv_ar_burst_i,
input logic slv_ar_lock_i,
input logic [3:0] slv_ar_cache_i,
input logic [3:0] slv_ar_qos_i,
input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i,
input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i,
output logic slv_ar_ready_o,
input logic slv_ar_valid_i,
input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i,
input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i,
input logic [AXI_USER_WIDTH-1:0] slv_w_user_i,
input logic slv_w_last_i,
output logic slv_w_ready_o,
input logic slv_w_valid_i,
output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o,
output logic [1:0] slv_r_resp_o,
output logic slv_r_last_o,
output logic [AXI_ID_WIDTH-1:0] slv_r_id_o,
output logic [AXI_USER_WIDTH-1:0] slv_r_user_o,
input logic slv_r_ready_i,
output logic slv_r_valid_o,
output logic [1:0] slv_b_resp_o,
output logic [AXI_ID_WIDTH-1:0] slv_b_id_o,
output logic [AXI_USER_WIDTH-1:0] slv_b_user_o,
input logic slv_b_ready_i,
output logic slv_b_valid_o,
/// Master Interface
output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o,
output logic [2:0] mst_aw_prot_o,
output logic [3:0] mst_aw_region_o,
output logic [5:0] mst_aw_atop_o,
output logic [7:0] mst_aw_len_o,
output logic [2:0] mst_aw_size_o,
output logic [1:0] mst_aw_burst_o,
output logic mst_aw_lock_o,
output logic [3:0] mst_aw_cache_o,
output logic [3:0] mst_aw_qos_o,
output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o,
output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o,
input logic mst_aw_ready_i,
output logic mst_aw_valid_o,
output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o,
output logic [2:0] mst_ar_prot_o,
output logic [3:0] mst_ar_region_o,
output logic [7:0] mst_ar_len_o,
output logic [2:0] mst_ar_size_o,
output logic [1:0] mst_ar_burst_o,
output logic mst_ar_lock_o,
output logic [3:0] mst_ar_cache_o,
output logic [3:0] mst_ar_qos_o,
output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o,
output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o,
input logic mst_ar_ready_i,
output logic mst_ar_valid_o,
output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o,
output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o,
output logic [AXI_USER_WIDTH-1:0] mst_w_user_o,
output logic mst_w_last_o,
input logic mst_w_ready_i,
output logic mst_w_valid_o,
input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i,
input logic [1:0] mst_r_resp_i,
input logic mst_r_last_i,
input logic [AXI_ID_WIDTH-1:0] mst_r_id_i,
input logic [AXI_USER_WIDTH-1:0] mst_r_user_i,
output logic mst_r_ready_o,
input logic mst_r_valid_i,
input logic [1:0] mst_b_resp_i,
input logic [AXI_ID_WIDTH-1:0] mst_b_id_i,
input logic [AXI_USER_WIDTH-1:0] mst_b_user_i,
output logic mst_b_ready_o,
input logic mst_b_valid_i
);
localparam int unsigned OUTSTND_BURSTS_WIDTH = $clog2(AXI_MAX_WRITE_TXNS+1);
localparam int unsigned AXI_ALU_RATIO = AXI_DATA_WIDTH/RISCV_WORD_WIDTH;
// State types
typedef enum logic [1:0] { FEEDTHROUGH_AW, WAIT_RESULT_AW, SEND_AW } aw_state_t;
aw_state_t aw_state_d, aw_state_q;
typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA_W, WAIT_RESULT_W, WAIT_CHANNEL_W, SEND_W } w_state_t;
w_state_t w_state_d, w_state_q;
typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_COMPLETE_B, WAIT_CHANNEL_B, SEND_B } b_state_t;
b_state_t b_state_d, b_state_q;
typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_CHANNEL_AR, SEND_AR } ar_state_t;
ar_state_t ar_state_d, ar_state_q;
typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_CHANNEL_R, SEND_R } r_state_t;
r_state_t r_state_d, r_state_q;
typedef enum logic [1:0] { NONE, INVALID, LOAD, STORE } atop_req_t;
atop_req_t atop_valid_d, atop_valid_q;
// Signal declarations
// Transaction FF
logic [AXI_ADDR_WIDTH-1:0] addr_d, addr_q;
logic [AXI_ID_WIDTH-1:0] id_d, id_q;
logic [AXI_STRB_WIDTH-1:0] strb_d, strb_q;
logic [2:0] size_d, size_q;
logic [5:0] atop_d, atop_q;
logic [3:0] cache_d, cache_q;
logic [2:0] prot_d, prot_q;
logic [3:0] qos_d, qos_q;
logic [3:0] region_d, region_q;
logic [1:0] r_resp_d, r_resp_q;
logic [AXI_USER_WIDTH-1:0] aw_user_d, aw_user_q,
w_user_d, w_user_q,
r_user_d, r_user_q;
// Data FF
logic [AXI_DATA_WIDTH-1:0] w_data_d, w_data_q; // AMO operand
logic [AXI_DATA_WIDTH-1:0] r_data_d, r_data_q; // Data from memory
logic [AXI_DATA_WIDTH-1:0] result_d, result_q; // Result of AMO operation
logic w_d_valid_d, w_d_valid_q, // AMO operand valid
r_d_valid_d, r_d_valid_q; // Data from memory valid
// Counters
logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_d, w_cnt_q; // Outstanding W beats
logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_req_d, w_cnt_req_q; // W beats until AMO can read W
logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_inj_d, w_cnt_inj_q; // W beats until AMO can insert its W
// States
logic adapter_ready;
logic transaction_collision;
logic aw_valid, aw_ready, aw_free,
w_valid, w_ready, w_free,
b_valid, b_ready, b_free,
ar_valid, ar_ready, ar_free,
r_valid, r_ready, r_free;
// ALU Signals
logic [RISCV_WORD_WIDTH-1:0] alu_operand_a;
logic [RISCV_WORD_WIDTH-1:0] alu_operand_b;
logic [RISCV_WORD_WIDTH-1:0] alu_result;
logic [AXI_DATA_WIDTH-1:0] alu_result_ext;
logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a;
logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b;
logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a_sign_ext;
logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b_sign_ext;
logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] res;
logic [AXI_STRB_WIDTH-1:0][7:0] strb_ext;
logic sign_a;
logic sign_b;
/**
* Calculate ready signals and channel states
*/
// Check if all state machines are ready for the next atomic request
assign adapter_ready = (aw_state_q == FEEDTHROUGH_AW) &&
( w_state_q == FEEDTHROUGH_W ) &&
( b_state_q == FEEDTHROUGH_B ) &&
(ar_state_q == FEEDTHROUGH_AR) &&
( r_state_q == FEEDTHROUGH_R );
// Calculate if the channels are free
assign aw_free = ~aw_valid | aw_ready;
assign w_free = ~ w_valid | w_ready;
assign b_free = ~ b_valid | b_ready;
assign ar_free = ~ar_valid | ar_ready;
assign r_free = ~ r_valid | r_ready;
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
aw_valid <= 0;
aw_ready <= 0;
w_valid <= 0;
w_ready <= 0;
b_valid <= 0;
b_ready <= 0;
ar_valid <= 0;
ar_ready <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
aw_valid <= mst_aw_valid_o;
aw_ready <= mst_aw_ready_i;
w_valid <= mst_w_valid_o;
w_ready <= mst_w_ready_i;
b_valid <= slv_b_valid_o;
b_ready <= slv_b_ready_i;
ar_valid <= mst_ar_valid_o;
ar_ready <= mst_ar_ready_i;
r_valid <= slv_r_valid_o;
r_ready <= slv_r_ready_i;
end
end
// Calculate if the request interferes with the ongoing atomic transaction
// The protected bytes go from addr_q up to addr_q + (1 << size_q) - 1
// TODO Bursts need special treatment
assign transaction_collision = (slv_aw_addr_i < ( addr_q + (8'h01 << size_q))) &
( addr_q < (slv_aw_addr_i + (8'h01 << slv_aw_size_i)));
always_comb begin : calc_atop_valid
atop_valid_d = atop_valid_q;
if (adapter_ready) begin
atop_valid_d = NONE;
if (slv_aw_valid_i && slv_aw_atop_i) begin
// Default is invalid request
atop_valid_d = INVALID;
// Valid load operation
if ((slv_aw_atop_i == axi_pkg::ATOP_ATOMICSWAP) ||
(slv_aw_atop_i[5:3] == {axi_pkg::ATOP_ATOMICLOAD , axi_pkg::ATOP_LITTLE_END})) begin
atop_valid_d = LOAD;
end
// Valid store operation
if (slv_aw_atop_i[5:3] == {axi_pkg::ATOP_ATOMICSTORE, axi_pkg::ATOP_LITTLE_END}) begin
atop_valid_d = STORE;
end
// Invalidate valid request if control signals do not match
// Burst or exclusive access
if (slv_aw_len_i | slv_aw_lock_i) begin
atop_valid_d = INVALID;
end
// Unsupported size
if (slv_aw_size_i > $clog2(RISCV_WORD_WIDTH/8)) begin
atop_valid_d = INVALID;
end
end
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_atop_valid
if(~rst_ni) begin
atop_valid_q <= NONE;
end else begin
atop_valid_q <= atop_valid_d;
end
end
/**
* Write Channel: AW, W, B
*/
/*====================================================================
= AW =
====================================================================*/
always_comb begin : axi_aw_channel
// Defaults AXI Bus
mst_aw_id_o = slv_aw_id_i;
mst_aw_addr_o = slv_aw_addr_i;
mst_aw_len_o = slv_aw_len_i;
mst_aw_size_o = slv_aw_size_i;
mst_aw_burst_o = slv_aw_burst_i;
mst_aw_lock_o = slv_aw_lock_i;
mst_aw_cache_o = slv_aw_cache_i;
mst_aw_prot_o = slv_aw_prot_i;
mst_aw_qos_o = slv_aw_qos_i;
mst_aw_region_o = slv_aw_region_i;
mst_aw_atop_o = 6'b0;
mst_aw_user_o = slv_aw_user_i;
// Defaults FF
addr_d = addr_q;
id_d = id_q;
size_d = size_q;
atop_d = atop_q;
cache_d = cache_q;
prot_d = prot_q;
qos_d = qos_q;
region_d = region_q;
aw_user_d = aw_user_q;
w_cnt_inj_d = w_cnt_inj_q;
// State Machine
aw_state_d = aw_state_q;
// Default control: Block AW channel if...
if (slv_aw_valid_i && slv_aw_atop_i) begin
// Block if atomic request
mst_aw_valid_o = 1'b0;
slv_aw_ready_o = 1'b0;
end else if (w_cnt_q == AXI_MAX_WRITE_TXNS) begin
// Block if counter is overflowing
mst_aw_valid_o = 1'b0;
slv_aw_ready_o = 1'b0;
end else if (slv_aw_valid_i && transaction_collision && !adapter_ready) begin
// Block requests to the same address as current atomic transaction
mst_aw_valid_o = 1'b0;
slv_aw_ready_o = 1'b0;
end else begin
// Forward
mst_aw_valid_o = slv_aw_valid_i;
slv_aw_ready_o = mst_aw_ready_i;
end
// Count W burst to know when to inject the W data
if (w_cnt_inj_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
w_cnt_inj_d = w_cnt_inj_q - 1;
end
unique case (aw_state_q)
FEEDTHROUGH_AW: begin
// Feedthrough slave to master until atomic operation is detected
if (slv_aw_valid_i && slv_aw_atop_i && adapter_ready) begin
// Acknowledge atomic transaction
slv_aw_ready_o = 1'b1;
// Remember request
atop_d = slv_aw_atop_i;
addr_d = slv_aw_addr_i;
id_d = slv_aw_id_i;
size_d = slv_aw_size_i;
cache_d = slv_aw_cache_i;
prot_d = slv_aw_prot_i;
qos_d = slv_aw_qos_i;
region_d = slv_aw_region_i;
aw_user_d = slv_aw_user_i;
// If valid AMO --> wait for result
if (atop_valid_d != INVALID) begin
aw_state_d = WAIT_RESULT_AW;
end
end
end // FEEDTHROUGH_AW
WAIT_RESULT_AW, SEND_AW: begin
// If the result is ready and the channel is free --> inject AW request
if ((r_d_valid_q && w_d_valid_q && aw_free) || (aw_state_q == SEND_AW)) begin
// Block
slv_aw_ready_o = 1'b0;
// Make write request
mst_aw_valid_o = 1'b1;
mst_aw_addr_o = addr_q;
mst_aw_len_o = 8'h00;
mst_aw_id_o = id_q;
mst_aw_size_o = size_q;
mst_aw_burst_o = 2'b00;
mst_aw_lock_o = 1'b0;
mst_aw_cache_o = cache_q;
mst_aw_prot_o = prot_q;
mst_aw_qos_o = qos_q;
mst_aw_region_o = region_q;
mst_aw_user_o = aw_user_q;
// Check if request is acknowledged
if (mst_aw_ready_i) begin
aw_state_d = FEEDTHROUGH_AW;
end else begin
aw_state_d = SEND_AW;
end
// Remember outstanding W beats before injected request
if (aw_state_q == WAIT_RESULT_AW) begin
if (w_cnt_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
w_cnt_inj_d = w_cnt_q - 1;
end else begin
w_cnt_inj_d = w_cnt_q;
end
end
end
end // WAIT_RESULT_AW, SEND_AW
default: aw_state_d = FEEDTHROUGH_AW;
endcase
end // axi_aw_channel
/*====================================================================
= W =
====================================================================*/
always_comb begin : axi_w_channel
// Defaults AXI Bus
mst_w_data_o = slv_w_data_i;
mst_w_strb_o = slv_w_strb_i;
mst_w_last_o = slv_w_last_i;
mst_w_user_o = slv_w_user_i;
// Defaults FF
strb_d = strb_q;
w_user_d = w_user_q;
w_data_d = w_data_q;
result_d = result_q;
w_d_valid_d = w_d_valid_q;
w_cnt_req_d = w_cnt_req_q;
// State Machine
w_state_d = w_state_q;
// Default control
// Make sure no data is sent without knowing if it's atomic
if (w_cnt_q == 0) begin
// Stall W as it precedes the AW request
slv_w_ready_o = 1'b0;
mst_w_valid_o = 1'b0;
end else begin
mst_w_valid_o = slv_w_valid_i;
slv_w_ready_o = mst_w_ready_i;
end
unique case (w_state_q)
FEEDTHROUGH_W: begin
if (adapter_ready) begin
// Reset read flag
w_d_valid_d = 1'b0;
result_d = '0;
if (atop_valid_d != NONE) begin
// Check if data is also available and does not belong to previous request
if (w_cnt_q == 0) begin
// Block downstream
mst_w_valid_o = 1'b0;
// Fetch data and wait for all data
slv_w_ready_o = 1'b1;
if (slv_w_valid_i) begin
if (atop_valid_d != INVALID) begin
w_data_d = slv_w_data_i;
strb_d = slv_w_strb_i;
w_user_d = slv_w_user_i;
w_d_valid_d = 1'b1;
w_state_d = WAIT_RESULT_W;
end
end else begin
w_cnt_req_d = '0;
w_state_d = WAIT_DATA_W;
end
end else begin
// Remember the amount of outstanding bursts and count down
if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
w_cnt_req_d = w_cnt_q - 1;
end else begin
w_cnt_req_d = w_cnt_q;
end
w_state_d = WAIT_DATA_W;
end
end
end
end // FEEDTHROUGH_W
WAIT_DATA_W: begin
// Count W beats until data arrives that belongs to the AMO request
if (w_cnt_req_q == 0) begin
// Block downstream
mst_w_valid_o = 1'b0;
// Ready upstream
slv_w_ready_o = 1'b1;
if (slv_w_valid_i) begin
if (atop_valid_q == INVALID) begin
w_state_d = FEEDTHROUGH_W;
end else begin
w_data_d = slv_w_data_i;
strb_d = slv_w_strb_i;
w_user_d = slv_w_user_i;
w_d_valid_d = 1'b1;
w_state_d = WAIT_RESULT_W;
end
end
end else if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
w_cnt_req_d = w_cnt_req_q - 1;
end
end // WAIT_DATA_W
WAIT_RESULT_W: begin
// If the result is ready, try to write it
if (r_d_valid_q && w_d_valid_q && aw_free) begin
// Check if W channel is free and make sure data is not interleaved
result_d = alu_result_ext;
if (w_free && w_cnt_q == 0) begin
// Block
slv_w_ready_o = 1'b0;
// Send write data
mst_w_valid_o = 1'b1;
mst_w_data_o = alu_result_ext;
mst_w_last_o = 1'b1;
mst_w_strb_o = strb_q;
mst_w_user_o = w_user_q;
if (mst_w_ready_i) begin
w_state_d = FEEDTHROUGH_W;
end else begin
w_state_d = SEND_W;
end
end else begin
w_state_d = WAIT_CHANNEL_W;
end
end
end // WAIT_RESULT_W
WAIT_CHANNEL_W, SEND_W: begin
// Wait to not interleave the data
if ((w_free && w_cnt_inj_q == 0) || (w_state_q == SEND_W)) begin
// Block
slv_w_ready_o = 1'b0;
// Send write data
mst_w_valid_o = 1'b1;
mst_w_data_o = result_q;
mst_w_last_o = 1'b1;
mst_w_strb_o = strb_q;
mst_w_user_o = w_user_q;
if (mst_w_ready_i) begin
w_state_d = FEEDTHROUGH_W;
end else begin
w_state_d = SEND_W;
end
end
end // WAIT_CHANNEL_W, SEND_W
default: w_state_d = FEEDTHROUGH_W;
endcase
end // axi_w_channel
/*====================================================================
= B =
====================================================================*/
always_comb begin : axi_b_channel
// Defaults AXI Bus
mst_b_ready_o = slv_b_ready_i;
slv_b_id_o = mst_b_id_i;
slv_b_resp_o = mst_b_resp_i;
slv_b_user_o = mst_b_user_i;
slv_b_valid_o = mst_b_valid_i;
// State Machine
b_state_d = b_state_q;
unique case (b_state_q)
FEEDTHROUGH_B: begin
if (adapter_ready) begin
if (atop_valid_d == LOAD || atop_valid_d == STORE) begin
// Wait until write is complete
b_state_d = WAIT_COMPLETE_B;
end else if (atop_valid_d == INVALID) begin
// Inject B error resp once the channel is free
if (b_free) begin
// Block downstream
mst_b_ready_o = 1'b0;
// Write B response
slv_b_valid_o = 1'b1;
slv_b_id_o = slv_aw_id_i;
slv_b_resp_o = axi_pkg::RESP_SLVERR;
slv_b_user_o = '0;
if (!slv_b_ready_i) begin
b_state_d = SEND_B;
end
end else begin
b_state_d = WAIT_CHANNEL_B;
end
end
end
end // FEEDTHROUGH_B
WAIT_CHANNEL_B, SEND_B: begin
if (b_free || (b_state_q == SEND_B)) begin
// Block downstream
mst_b_ready_o = 1'b0;
// Write B response
slv_b_valid_o = 1'b1;
slv_b_id_o = id_q;
slv_b_resp_o = axi_pkg::RESP_SLVERR;
slv_b_user_o = '0;
if (slv_b_ready_i) begin
b_state_d = FEEDTHROUGH_B;
end else begin
b_state_d = SEND_B;
end
end
end // WAIT_CHANNEL_B, SEND_B
WAIT_COMPLETE_B: begin
if (mst_b_valid_i && (mst_b_id_i == id_q)) begin
b_state_d = FEEDTHROUGH_B;
end
end // WAIT_COMPLETE_B
default: b_state_d = FEEDTHROUGH_B;
endcase
end // axi_b_channel
// Keep track of outstanding downstream write bursts and responses.
always_comb begin
w_cnt_d = w_cnt_q;
if (mst_aw_valid_o && mst_aw_ready_i) begin
w_cnt_d += 1;
end
if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
w_cnt_d -= 1;
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin : axi_write_channel_ff
if(~rst_ni) begin
aw_state_q <= FEEDTHROUGH_AW;
w_state_q <= FEEDTHROUGH_W;
b_state_q <= FEEDTHROUGH_B;
w_cnt_q <= '0;
w_cnt_req_q <= '0;
w_cnt_inj_q <= '0;
addr_q <= '0;
id_q <= '0;
size_q <= '0;
strb_q <= '0;
cache_q <= '0;
prot_q <= '0;
qos_q <= '0;
region_q <= '0;
aw_user_q <= '0;
w_user_q <= '0;
w_data_q <= '0;
result_q <= '0;
w_d_valid_q <= '0;
atop_q <= 6'b0;
end else begin
aw_state_q <= aw_state_d;
w_state_q <= w_state_d;
b_state_q <= b_state_d;
w_cnt_q <= w_cnt_d;
w_cnt_req_q <= w_cnt_req_d;
w_cnt_inj_q <= w_cnt_inj_d;
addr_q <= addr_d;
id_q <= id_d;
size_q <= size_d;
strb_q <= strb_d;
cache_q <= cache_d;
prot_q <= prot_d;
qos_q <= qos_d;
region_q <= region_d;
aw_user_q <= aw_user_d;
w_user_q <= w_user_d;
w_data_q <= w_data_d;
result_q <= result_d;
w_d_valid_q <= w_d_valid_d;
atop_q <= atop_d;
end
end
/**
* Read Channel: AR, R
*/
/*====================================================================
= AR =
====================================================================*/
always_comb begin : axi_ar_channel
// Defaults AXI Bus
mst_ar_id_o = slv_ar_id_i;
mst_ar_addr_o = slv_ar_addr_i;
mst_ar_len_o = slv_ar_len_i;
mst_ar_size_o = slv_ar_size_i;
mst_ar_burst_o = slv_ar_burst_i;
mst_ar_lock_o = slv_ar_lock_i;
mst_ar_cache_o = slv_ar_cache_i;
mst_ar_prot_o = slv_ar_prot_i;
mst_ar_qos_o = slv_ar_qos_i;
mst_ar_region_o = slv_ar_region_i;
mst_ar_user_o = slv_ar_user_i;
mst_ar_valid_o = 1'b0;
slv_ar_ready_o = 1'b0;
// State Machine
ar_state_d = ar_state_q;
unique case (ar_state_q)
FEEDTHROUGH_AR: begin
// Feed through
mst_ar_valid_o = slv_ar_valid_i;
slv_ar_ready_o = mst_ar_ready_i;
if (adapter_ready) begin
if (atop_valid_d == LOAD | atop_valid_d == STORE) begin
if (ar_free) begin
// Acquire channel
slv_ar_ready_o = 1'b0;
// Immediately start read request
mst_ar_valid_o = 1'b1;
mst_ar_addr_o = slv_aw_addr_i;
mst_ar_id_o = slv_aw_id_i;
mst_ar_len_o = 8'h00;
mst_ar_size_o = slv_aw_size_i;
mst_ar_burst_o = 2'b00;
mst_ar_lock_o = 1'h0;
mst_ar_cache_o = slv_aw_cache_i;
mst_ar_prot_o = slv_aw_prot_i;
mst_ar_qos_o = slv_aw_qos_i;
mst_ar_region_o = slv_aw_region_i;
mst_ar_user_o = slv_aw_user_i;
if (!mst_ar_ready_i) begin
// Hold read request but do not depend on AW
ar_state_d = SEND_AR;
end
end else begin
// Wait until AR is free
ar_state_d = WAIT_CHANNEL_AR;
end
end
end
end // FEEDTHROUGH_AR
WAIT_CHANNEL_AR, SEND_AR: begin
// Issue read request
if (ar_free || (ar_state_q == SEND_AR)) begin
// Inject read request
mst_ar_valid_o = 1'b1;
mst_ar_addr_o = addr_q;
mst_ar_id_o = id_q;
mst_ar_len_o = 8'h00;
mst_ar_size_o = size_q;
mst_ar_burst_o = 2'b00;
mst_ar_lock_o = 1'h0;
mst_ar_cache_o = cache_q;
mst_ar_prot_o = prot_q;
mst_ar_qos_o = qos_q;
mst_ar_region_o = region_q;
mst_ar_user_o = aw_user_q;
if (mst_ar_ready_i) begin
// Request acknowledged
ar_state_d = FEEDTHROUGH_AR;
end else begin
// Hold read request
ar_state_d = SEND_AR;
end
end else begin
// Wait until AR is free
mst_ar_valid_o = slv_ar_valid_i;
slv_ar_ready_o = mst_ar_ready_i;
end
end // WAIT_CHANNEL_AR, SEND_AR
default: ar_state_d = FEEDTHROUGH_AR;
endcase
end // axi_ar_channel
/*====================================================================
= R =
====================================================================*/
always_comb begin : axi_r_channel
// Defaults AXI Bus
mst_r_ready_o = slv_r_ready_i;
slv_r_id_o = mst_r_id_i;
slv_r_data_o = mst_r_data_i;
slv_r_resp_o = mst_r_resp_i;
slv_r_last_o = mst_r_last_i;
slv_r_user_o = mst_r_user_i;
slv_r_valid_o = mst_r_valid_i;
// Defaults FF
r_data_d = r_data_q;
r_resp_d = r_resp_q;
r_user_d = r_user_q;
r_d_valid_d = r_d_valid_q;
// State Machine
r_state_d = r_state_q;
unique case (r_state_q)
FEEDTHROUGH_R: begin
if (adapter_ready) begin
// Reset read flag
r_d_valid_d = 1'b0;
if (atop_valid_d == LOAD || atop_valid_d == STORE) begin
// Wait for R response to read data
r_state_d = WAIT_DATA_R;
end else if (atop_valid_d == INVALID) begin
// Send R response once channel is free
if (r_free) begin
// Acquire the R channel
// Block downstream
mst_r_ready_o = 1'b0;
// Send R error response
slv_r_valid_o = 1'b1;
slv_r_data_o = '0;
slv_r_id_o = slv_aw_id_i;
slv_r_last_o = 1'b1;
slv_r_resp_o = axi_pkg::RESP_SLVERR;
slv_r_user_o = '0;
if (!slv_r_ready_i) begin
// Hold R response
r_state_d = SEND_R;
end
end else begin
r_state_d = WAIT_CHANNEL_R;
end
end
end
end // FEEDTHROUGH_R
WAIT_DATA_R: begin
// Read data
if (mst_r_valid_i && (mst_r_id_i == id_q)) begin
// Acknowledge downstream and block upstream
mst_r_ready_o = 1'b1;
slv_r_valid_o = 1'b0;
// Store data
r_data_d = mst_r_data_i;
r_resp_d = mst_r_resp_i;
r_user_d = mst_r_user_i;
r_d_valid_d = 1'b1;
if (atop_valid_q == STORE) begin
r_state_d = FEEDTHROUGH_R;
end else begin
// Wait for B resp before injecting R
r_state_d = WAIT_CHANNEL_R;
end
end
end // WAIT_DATA_R
WAIT_CHANNEL_R, SEND_R: begin
// Wait for the R channel to become free and B response to be valid
// TODO: Use b_state_d to be one cycle quicker
if ((r_free && (b_state_q != WAIT_COMPLETE_B)) || (r_state_q == SEND_R)) begin
// Block downstream
mst_r_ready_o = 1'b0;
// Send R response
slv_r_valid_o = 1'b1;
slv_r_data_o = r_data_q;
slv_r_id_o = id_q;
slv_r_last_o = 1'b1;
slv_r_resp_o = r_resp_q;
slv_r_user_o = r_user_q;
if (atop_valid_q == INVALID) begin
slv_r_data_o = '0;
slv_r_resp_o = axi_pkg::RESP_SLVERR;
slv_r_user_o = '0;
end
if (slv_r_ready_i) begin
r_state_d = FEEDTHROUGH_R;
end else begin
r_state_d = SEND_R;
end
end
end // WAIT_CHANNEL_R, SEND_R
default: r_state_d = FEEDTHROUGH_R;
endcase
end // axi_r_channel
always_ff @(posedge clk_i or negedge rst_ni) begin : axi_read_channel_ff
if(~rst_ni) begin
ar_state_q <= FEEDTHROUGH_AR;
r_state_q <= FEEDTHROUGH_R;
r_data_q <= '0;
r_resp_q <= '0;
r_user_q <= '0;
r_d_valid_q <= 1'b0;
end else begin
ar_state_q <= ar_state_d;
r_state_q <= r_state_d;
r_data_q <= r_data_d;
r_resp_q <= r_resp_d;
r_user_q <= r_user_d;
r_d_valid_q <= r_d_valid_d;
end
end
/**
* ALU
*/
assign op_a = r_data_q & strb_ext;
assign op_b = w_data_q & strb_ext;
assign sign_a = |(op_a & ~(strb_ext >> 1));
assign sign_b = |(op_b & ~(strb_ext >> 1));
assign alu_result_ext = res;
generate
if (AXI_ALU_RATIO == 1 && RISCV_WORD_WIDTH == 32) begin
assign alu_operand_a = op_a;
assign alu_operand_b = op_b;
assign res = alu_result;
end else if (AXI_ALU_RATIO == 1 && RISCV_WORD_WIDTH == 64) begin
assign res = alu_result;
always_comb begin
op_a_sign_ext = op_a | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_a}} & ~strb_ext);
op_b_sign_ext = op_b | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_b}} & ~strb_ext);
if (atop_q[2:0] == axi_pkg::ATOP_SMAX || atop_q[2:0] == axi_pkg::ATOP_SMIN) begin
// Sign extend
alu_operand_a = op_a_sign_ext;
alu_operand_b = op_b_sign_ext;
end else begin
// No sign extension necessary
alu_operand_a = op_a;
alu_operand_b = op_b;
end
end
end else begin
always_comb begin
op_a_sign_ext = op_a | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_a}} & ~strb_ext);
op_b_sign_ext = op_b | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_b}} & ~strb_ext);
if (atop_q[2:0] == axi_pkg::ATOP_SMAX || atop_q[2:0] == axi_pkg::ATOP_SMIN) begin
// Sign extend
alu_operand_a = op_a_sign_ext[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]];
alu_operand_b = op_b_sign_ext[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]];
end else begin
// No sign extension necessary
alu_operand_a = op_a[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]];
alu_operand_b = op_b[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]];
end
res = '0;
res[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]] = alu_result;
end
end
endgenerate
generate
for (genvar i = 0; i < AXI_STRB_WIDTH; i++) begin
always_comb begin
if (strb_q[i]) begin
strb_ext[i] = 8'hFF;
end else begin
strb_ext[i] = 8'h00;
end
end
end
endgenerate
axi_riscv_amos_alu #(
.DATA_WIDTH ( RISCV_WORD_WIDTH )
) i_amo_alu (
.amo_op_i ( atop_q ),
.amo_operand_a_i ( alu_operand_a ),
.amo_operand_b_i ( alu_operand_b ),
.amo_result_o ( alu_result )
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: validate_params
assert (AXI_ADDR_WIDTH > 0)
else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!");
assert (AXI_DATA_WIDTH > 0)
else $fatal(1, "AXI_DATA_WIDTH must be greater than 0!");
assert (AXI_ID_WIDTH > 0)
else $fatal(1, "AXI_ID_WIDTH must be greater than 0!");
assert (AXI_MAX_WRITE_TXNS > 0)
else $fatal(1, "AXI_MAX_WRITE_TXNS must be greater than 0!");
assert (RISCV_WORD_WIDTH == 32 || RISCV_WORD_WIDTH == 64)
else $fatal(1, "RISCV_WORD_WIDTH must be 32 or 64!");
assert (RISCV_WORD_WIDTH <= AXI_DATA_WIDTH)
else $fatal(1, "RISCV_WORD_WIDTH must not be greater than AXI_DATA_WIDTH!");
end
`endif
// pragma translate_on
endmodule
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// AXI RISC-V Atomic Operations (AMOs) ALU
module axi_riscv_amos_alu # (
parameter int unsigned DATA_WIDTH = 0
) (
input logic [5:0] amo_op_i,
input logic [DATA_WIDTH-1:0] amo_operand_a_i,
input logic [DATA_WIDTH-1:0] amo_operand_b_i,
output logic [DATA_WIDTH-1:0] amo_result_o
);
logic [DATA_WIDTH:0] adder_sum;
logic [DATA_WIDTH:0] adder_operand_a, adder_operand_b;
assign adder_sum = adder_operand_a + adder_operand_b;
always_comb begin
adder_operand_a = $signed(amo_operand_a_i);
adder_operand_b = $signed(amo_operand_b_i);
amo_result_o = amo_operand_a_i;
if (amo_op_i == axi_pkg::ATOP_ATOMICSWAP) begin
// Swap operation
amo_result_o = amo_operand_b_i;
end else if ((amo_op_i[5:4] == axi_pkg::ATOP_ATOMICLOAD) | (amo_op_i[5:4] == axi_pkg::ATOP_ATOMICSTORE)) begin
// Load operation
unique case (amo_op_i[2:0])
// the default is to output operand_a
axi_pkg::ATOP_ADD: amo_result_o = adder_sum[DATA_WIDTH-1:0];
axi_pkg::ATOP_CLR: amo_result_o = amo_operand_a_i & (~amo_operand_b_i);
axi_pkg::ATOP_SET: amo_result_o = amo_operand_a_i | amo_operand_b_i;
axi_pkg::ATOP_EOR: amo_result_o = amo_operand_a_i ^ amo_operand_b_i;
axi_pkg::ATOP_SMAX: begin
adder_operand_b = -$signed(amo_operand_b_i);
amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_b_i : amo_operand_a_i;
end
axi_pkg::ATOP_SMIN: begin
adder_operand_b = -$signed(amo_operand_b_i);
amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_a_i : amo_operand_b_i;
end
axi_pkg::ATOP_UMAX: begin
adder_operand_a = $unsigned(amo_operand_a_i);
adder_operand_b = -$unsigned(amo_operand_b_i);
amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_b_i : amo_operand_a_i;
end
axi_pkg::ATOP_UMIN: begin
adder_operand_a = $unsigned(amo_operand_a_i);
adder_operand_b = -$unsigned(amo_operand_b_i);
amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_a_i : amo_operand_b_i;
end
default: amo_result_o = '0;
endcase
end
end
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: validate_params
assert (DATA_WIDTH > 0)
else $fatal(1, "DATA_WIDTH must be greater than 0!");
end
`endif
// pragma translate_on
endmodule
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// AXI RISC-V Atomics ("A" Extension) Adapter
//
// This AXI adapter implements the RISC-V "A" extension and adheres to the RVWMO memory consistency
// model.
//
// Maintainer: Andreas Kurth <akurth@iis.ee.ethz.ch>
module axi_riscv_atomics #(
/// AXI Parameters
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
// Maximum number of AXI write bursts outstanding at the same time
parameter int unsigned AXI_MAX_WRITE_TXNS = 0,
// Word width of the widest RISC-V processor that can issue requests to this module.
// 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are
// supported if `aw_strb` is set correctly.
parameter int unsigned RISCV_WORD_WIDTH = 0,
/// Derived Parameters (do NOT change manually!)
localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input logic clk_i,
input logic rst_ni,
/// Slave Interface
input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i,
input logic [2:0] slv_aw_prot_i,
input logic [3:0] slv_aw_region_i,
input logic [5:0] slv_aw_atop_i,
input logic [7:0] slv_aw_len_i,
input logic [2:0] slv_aw_size_i,
input logic [1:0] slv_aw_burst_i,
input logic slv_aw_lock_i,
input logic [3:0] slv_aw_cache_i,
input logic [3:0] slv_aw_qos_i,
input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i,
input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i,
output logic slv_aw_ready_o,
input logic slv_aw_valid_i,
input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i,
input logic [2:0] slv_ar_prot_i,
input logic [3:0] slv_ar_region_i,
input logic [7:0] slv_ar_len_i,
input logic [2:0] slv_ar_size_i,
input logic [1:0] slv_ar_burst_i,
input logic slv_ar_lock_i,
input logic [3:0] slv_ar_cache_i,
input logic [3:0] slv_ar_qos_i,
input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i,
input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i,
output logic slv_ar_ready_o,
input logic slv_ar_valid_i,
input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i,
input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i,
input logic [AXI_USER_WIDTH-1:0] slv_w_user_i,
input logic slv_w_last_i,
output logic slv_w_ready_o,
input logic slv_w_valid_i,
output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o,
output logic [1:0] slv_r_resp_o,
output logic slv_r_last_o,
output logic [AXI_ID_WIDTH-1:0] slv_r_id_o,
output logic [AXI_USER_WIDTH-1:0] slv_r_user_o,
input logic slv_r_ready_i,
output logic slv_r_valid_o,
output logic [1:0] slv_b_resp_o,
output logic [AXI_ID_WIDTH-1:0] slv_b_id_o,
output logic [AXI_USER_WIDTH-1:0] slv_b_user_o,
input logic slv_b_ready_i,
output logic slv_b_valid_o,
/// Master Interface
output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o,
output logic [2:0] mst_aw_prot_o,
output logic [3:0] mst_aw_region_o,
output logic [5:0] mst_aw_atop_o,
output logic [7:0] mst_aw_len_o,
output logic [2:0] mst_aw_size_o,
output logic [1:0] mst_aw_burst_o,
output logic mst_aw_lock_o,
output logic [3:0] mst_aw_cache_o,
output logic [3:0] mst_aw_qos_o,
output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o,
output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o,
input logic mst_aw_ready_i,
output logic mst_aw_valid_o,
output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o,
output logic [2:0] mst_ar_prot_o,
output logic [3:0] mst_ar_region_o,
output logic [7:0] mst_ar_len_o,
output logic [2:0] mst_ar_size_o,
output logic [1:0] mst_ar_burst_o,
output logic mst_ar_lock_o,
output logic [3:0] mst_ar_cache_o,
output logic [3:0] mst_ar_qos_o,
output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o,
output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o,
input logic mst_ar_ready_i,
output logic mst_ar_valid_o,
output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o,
output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o,
output logic [AXI_USER_WIDTH-1:0] mst_w_user_o,
output logic mst_w_last_o,
input logic mst_w_ready_i,
output logic mst_w_valid_o,
input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i,
input logic [1:0] mst_r_resp_i,
input logic mst_r_last_i,
input logic [AXI_ID_WIDTH-1:0] mst_r_id_i,
input logic [AXI_USER_WIDTH-1:0] mst_r_user_i,
output logic mst_r_ready_o,
input logic mst_r_valid_i,
input logic [1:0] mst_b_resp_i,
input logic [AXI_ID_WIDTH-1:0] mst_b_id_i,
input logic [AXI_USER_WIDTH-1:0] mst_b_user_i,
output logic mst_b_ready_o,
input logic mst_b_valid_i
);
// Make the entire address range exclusively accessible. Since the AMO adapter does not support
// address ranges, it would not make sense to expose the address range as a parameter of this
// module.
localparam longint unsigned ADDR_BEGIN = '0;
localparam longint unsigned ADDR_END = {AXI_ADDR_WIDTH{1'b1}};
logic [AXI_ADDR_WIDTH-1:0] int_axi_aw_addr;
logic [2:0] int_axi_aw_prot;
logic [3:0] int_axi_aw_region;
logic [5:0] int_axi_aw_atop;
logic [7:0] int_axi_aw_len;
logic [2:0] int_axi_aw_size;
logic [1:0] int_axi_aw_burst;
logic int_axi_aw_lock;
logic [3:0] int_axi_aw_cache;
logic [3:0] int_axi_aw_qos;
logic [AXI_ID_WIDTH-1:0] int_axi_aw_id;
logic [AXI_USER_WIDTH-1:0] int_axi_aw_user;
logic int_axi_aw_ready;
logic int_axi_aw_valid;
logic [AXI_ADDR_WIDTH-1:0] int_axi_ar_addr;
logic [2:0] int_axi_ar_prot;
logic [3:0] int_axi_ar_region;
logic [7:0] int_axi_ar_len;
logic [2:0] int_axi_ar_size;
logic [1:0] int_axi_ar_burst;
logic int_axi_ar_lock;
logic [3:0] int_axi_ar_cache;
logic [3:0] int_axi_ar_qos;
logic [AXI_ID_WIDTH-1:0] int_axi_ar_id;
logic [AXI_USER_WIDTH-1:0] int_axi_ar_user;
logic int_axi_ar_ready;
logic int_axi_ar_valid;
logic [AXI_DATA_WIDTH-1:0] int_axi_w_data;
logic [AXI_STRB_WIDTH-1:0] int_axi_w_strb;
logic [AXI_USER_WIDTH-1:0] int_axi_w_user;
logic int_axi_w_last;
logic int_axi_w_ready;
logic int_axi_w_valid;
logic [AXI_DATA_WIDTH-1:0] int_axi_r_data;
logic [1:0] int_axi_r_resp;
logic int_axi_r_last;
logic [AXI_ID_WIDTH-1:0] int_axi_r_id;
logic [AXI_USER_WIDTH-1:0] int_axi_r_user;
logic int_axi_r_ready;
logic int_axi_r_valid;
logic [1:0] int_axi_b_resp;
logic [AXI_ID_WIDTH-1:0] int_axi_b_id;
logic [AXI_USER_WIDTH-1:0] int_axi_b_user;
logic int_axi_b_ready;
logic int_axi_b_valid;
axi_riscv_amos #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH),
.AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS),
.RISCV_WORD_WIDTH (RISCV_WORD_WIDTH)
) i_amos (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slv_aw_addr_i ( slv_aw_addr_i ),
.slv_aw_prot_i ( slv_aw_prot_i ),
.slv_aw_region_i ( slv_aw_region_i ),
.slv_aw_atop_i ( slv_aw_atop_i ),
.slv_aw_len_i ( slv_aw_len_i ),
.slv_aw_size_i ( slv_aw_size_i ),
.slv_aw_burst_i ( slv_aw_burst_i ),
.slv_aw_lock_i ( slv_aw_lock_i ),
.slv_aw_cache_i ( slv_aw_cache_i ),
.slv_aw_qos_i ( slv_aw_qos_i ),
.slv_aw_id_i ( slv_aw_id_i ),
.slv_aw_user_i ( slv_aw_user_i ),
.slv_aw_ready_o ( slv_aw_ready_o ),
.slv_aw_valid_i ( slv_aw_valid_i ),
.slv_ar_addr_i ( slv_ar_addr_i ),
.slv_ar_prot_i ( slv_ar_prot_i ),
.slv_ar_region_i ( slv_ar_region_i ),
.slv_ar_len_i ( slv_ar_len_i ),
.slv_ar_size_i ( slv_ar_size_i ),
.slv_ar_burst_i ( slv_ar_burst_i ),
.slv_ar_lock_i ( slv_ar_lock_i ),
.slv_ar_cache_i ( slv_ar_cache_i ),
.slv_ar_qos_i ( slv_ar_qos_i ),
.slv_ar_id_i ( slv_ar_id_i ),
.slv_ar_user_i ( slv_ar_user_i ),
.slv_ar_ready_o ( slv_ar_ready_o ),
.slv_ar_valid_i ( slv_ar_valid_i ),
.slv_w_data_i ( slv_w_data_i ),
.slv_w_strb_i ( slv_w_strb_i ),
.slv_w_user_i ( slv_w_user_i ),
.slv_w_last_i ( slv_w_last_i ),
.slv_w_ready_o ( slv_w_ready_o ),
.slv_w_valid_i ( slv_w_valid_i ),
.slv_r_data_o ( slv_r_data_o ),
.slv_r_resp_o ( slv_r_resp_o ),
.slv_r_last_o ( slv_r_last_o ),
.slv_r_id_o ( slv_r_id_o ),
.slv_r_user_o ( slv_r_user_o ),
.slv_r_ready_i ( slv_r_ready_i ),
.slv_r_valid_o ( slv_r_valid_o ),
.slv_b_resp_o ( slv_b_resp_o ),
.slv_b_id_o ( slv_b_id_o ),
.slv_b_user_o ( slv_b_user_o ),
.slv_b_ready_i ( slv_b_ready_i ),
.slv_b_valid_o ( slv_b_valid_o ),
.mst_aw_addr_o ( int_axi_aw_addr ),
.mst_aw_prot_o ( int_axi_aw_prot ),
.mst_aw_region_o ( int_axi_aw_region ),
.mst_aw_atop_o ( int_axi_aw_atop ),
.mst_aw_len_o ( int_axi_aw_len ),
.mst_aw_size_o ( int_axi_aw_size ),
.mst_aw_burst_o ( int_axi_aw_burst ),
.mst_aw_lock_o ( int_axi_aw_lock ),
.mst_aw_cache_o ( int_axi_aw_cache ),
.mst_aw_qos_o ( int_axi_aw_qos ),
.mst_aw_id_o ( int_axi_aw_id ),
.mst_aw_user_o ( int_axi_aw_user ),
.mst_aw_ready_i ( int_axi_aw_ready ),
.mst_aw_valid_o ( int_axi_aw_valid ),
.mst_ar_addr_o ( int_axi_ar_addr ),
.mst_ar_prot_o ( int_axi_ar_prot ),
.mst_ar_region_o ( int_axi_ar_region ),
.mst_ar_len_o ( int_axi_ar_len ),
.mst_ar_size_o ( int_axi_ar_size ),
.mst_ar_burst_o ( int_axi_ar_burst ),
.mst_ar_lock_o ( int_axi_ar_lock ),
.mst_ar_cache_o ( int_axi_ar_cache ),
.mst_ar_qos_o ( int_axi_ar_qos ),
.mst_ar_id_o ( int_axi_ar_id ),
.mst_ar_user_o ( int_axi_ar_user ),
.mst_ar_ready_i ( int_axi_ar_ready ),
.mst_ar_valid_o ( int_axi_ar_valid ),
.mst_w_data_o ( int_axi_w_data ),
.mst_w_strb_o ( int_axi_w_strb ),
.mst_w_user_o ( int_axi_w_user ),
.mst_w_last_o ( int_axi_w_last ),
.mst_w_ready_i ( int_axi_w_ready ),
.mst_w_valid_o ( int_axi_w_valid ),
.mst_r_data_i ( int_axi_r_data ),
.mst_r_resp_i ( int_axi_r_resp ),
.mst_r_last_i ( int_axi_r_last ),
.mst_r_id_i ( int_axi_r_id ),
.mst_r_user_i ( int_axi_r_user ),
.mst_r_ready_o ( int_axi_r_ready ),
.mst_r_valid_i ( int_axi_r_valid ),
.mst_b_resp_i ( int_axi_b_resp ),
.mst_b_id_i ( int_axi_b_id ),
.mst_b_user_i ( int_axi_b_user ),
.mst_b_ready_o ( int_axi_b_ready ),
.mst_b_valid_i ( int_axi_b_valid )
);
axi_riscv_lrsc #(
.ADDR_BEGIN (ADDR_BEGIN),
.ADDR_END (ADDR_END),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) i_lrsc (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slv_aw_addr_i ( int_axi_aw_addr ),
.slv_aw_prot_i ( int_axi_aw_prot ),
.slv_aw_region_i ( int_axi_aw_region ),
.slv_aw_atop_i ( int_axi_aw_atop ),
.slv_aw_len_i ( int_axi_aw_len ),
.slv_aw_size_i ( int_axi_aw_size ),
.slv_aw_burst_i ( int_axi_aw_burst ),
.slv_aw_lock_i ( int_axi_aw_lock ),
.slv_aw_cache_i ( int_axi_aw_cache ),
.slv_aw_qos_i ( int_axi_aw_qos ),
.slv_aw_id_i ( int_axi_aw_id ),
.slv_aw_user_i ( int_axi_aw_user ),
.slv_aw_ready_o ( int_axi_aw_ready ),
.slv_aw_valid_i ( int_axi_aw_valid ),
.slv_ar_addr_i ( int_axi_ar_addr ),
.slv_ar_prot_i ( int_axi_ar_prot ),
.slv_ar_region_i ( int_axi_ar_region ),
.slv_ar_len_i ( int_axi_ar_len ),
.slv_ar_size_i ( int_axi_ar_size ),
.slv_ar_burst_i ( int_axi_ar_burst ),
.slv_ar_lock_i ( int_axi_ar_lock ),
.slv_ar_cache_i ( int_axi_ar_cache ),
.slv_ar_qos_i ( int_axi_ar_qos ),
.slv_ar_id_i ( int_axi_ar_id ),
.slv_ar_user_i ( int_axi_ar_user ),
.slv_ar_ready_o ( int_axi_ar_ready ),
.slv_ar_valid_i ( int_axi_ar_valid ),
.slv_w_data_i ( int_axi_w_data ),
.slv_w_strb_i ( int_axi_w_strb ),
.slv_w_user_i ( int_axi_w_user ),
.slv_w_last_i ( int_axi_w_last ),
.slv_w_ready_o ( int_axi_w_ready ),
.slv_w_valid_i ( int_axi_w_valid ),
.slv_r_data_o ( int_axi_r_data ),
.slv_r_resp_o ( int_axi_r_resp ),
.slv_r_last_o ( int_axi_r_last ),
.slv_r_id_o ( int_axi_r_id ),
.slv_r_user_o ( int_axi_r_user ),
.slv_r_ready_i ( int_axi_r_ready ),
.slv_r_valid_o ( int_axi_r_valid ),
.slv_b_resp_o ( int_axi_b_resp ),
.slv_b_id_o ( int_axi_b_id ),
.slv_b_user_o ( int_axi_b_user ),
.slv_b_ready_i ( int_axi_b_ready ),
.slv_b_valid_o ( int_axi_b_valid ),
.mst_aw_addr_o ( mst_aw_addr_o ),
.mst_aw_prot_o ( mst_aw_prot_o ),
.mst_aw_region_o ( mst_aw_region_o ),
.mst_aw_atop_o ( mst_aw_atop_o ),
.mst_aw_len_o ( mst_aw_len_o ),
.mst_aw_size_o ( mst_aw_size_o ),
.mst_aw_burst_o ( mst_aw_burst_o ),
.mst_aw_lock_o ( mst_aw_lock_o ),
.mst_aw_cache_o ( mst_aw_cache_o ),
.mst_aw_qos_o ( mst_aw_qos_o ),
.mst_aw_id_o ( mst_aw_id_o ),
.mst_aw_user_o ( mst_aw_user_o ),
.mst_aw_ready_i ( mst_aw_ready_i ),
.mst_aw_valid_o ( mst_aw_valid_o ),
.mst_ar_addr_o ( mst_ar_addr_o ),
.mst_ar_prot_o ( mst_ar_prot_o ),
.mst_ar_region_o ( mst_ar_region_o ),
.mst_ar_len_o ( mst_ar_len_o ),
.mst_ar_size_o ( mst_ar_size_o ),
.mst_ar_burst_o ( mst_ar_burst_o ),
.mst_ar_lock_o ( mst_ar_lock_o ),
.mst_ar_cache_o ( mst_ar_cache_o ),
.mst_ar_qos_o ( mst_ar_qos_o ),
.mst_ar_id_o ( mst_ar_id_o ),
.mst_ar_user_o ( mst_ar_user_o ),
.mst_ar_ready_i ( mst_ar_ready_i ),
.mst_ar_valid_o ( mst_ar_valid_o ),
.mst_w_data_o ( mst_w_data_o ),
.mst_w_strb_o ( mst_w_strb_o ),
.mst_w_user_o ( mst_w_user_o ),
.mst_w_last_o ( mst_w_last_o ),
.mst_w_ready_i ( mst_w_ready_i ),
.mst_w_valid_o ( mst_w_valid_o ),
.mst_r_data_i ( mst_r_data_i ),
.mst_r_resp_i ( mst_r_resp_i ),
.mst_r_last_i ( mst_r_last_i ),
.mst_r_id_i ( mst_r_id_i ),
.mst_r_user_i ( mst_r_user_i ),
.mst_r_ready_o ( mst_r_ready_o ),
.mst_r_valid_i ( mst_r_valid_i ),
.mst_b_resp_i ( mst_b_resp_i ),
.mst_b_id_i ( mst_b_id_i ),
.mst_b_user_i ( mst_b_user_i ),
.mst_b_ready_o ( mst_b_ready_o ),
.mst_b_valid_i ( mst_b_valid_i )
);
endmodule
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Wrapper for the AXI RISC-V Atomics Adapter that exposes AXI SystemVerilog interfaces.
//
// See the header of `axi_riscv_atomics` for a description.
//
// Maintainer: Andreas Kurth <akurth@iis.ee.ethz.ch>
module axi_riscv_atomics_wrap #(
/// AXI Parameters
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Maximum number of AXI bursts outstanding at the same time
parameter int unsigned AXI_MAX_WRITE_TXNS = 0,
// Word width of the widest RISC-V processor that can issue requests to this module.
// 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are
// supported if `aw_strb` is set correctly.
parameter int unsigned RISCV_WORD_WIDTH = 0,
/// Derived Parameters (do NOT change manually!)
localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input logic clk_i,
input logic rst_ni,
AXI_BUS.Master mst,
AXI_BUS.Slave slv
);
axi_riscv_atomics #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH),
.AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS),
.RISCV_WORD_WIDTH (RISCV_WORD_WIDTH)
) i_atomics (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slv_aw_addr_i ( slv.aw_addr ),
.slv_aw_prot_i ( slv.aw_prot ),
.slv_aw_region_i ( slv.aw_region ),
.slv_aw_atop_i ( slv.aw_atop ),
.slv_aw_len_i ( slv.aw_len ),
.slv_aw_size_i ( slv.aw_size ),
.slv_aw_burst_i ( slv.aw_burst ),
.slv_aw_lock_i ( slv.aw_lock ),
.slv_aw_cache_i ( slv.aw_cache ),
.slv_aw_qos_i ( slv.aw_qos ),
.slv_aw_id_i ( slv.aw_id ),
.slv_aw_user_i ( slv.aw_user ),
.slv_aw_ready_o ( slv.aw_ready ),
.slv_aw_valid_i ( slv.aw_valid ),
.slv_ar_addr_i ( slv.ar_addr ),
.slv_ar_prot_i ( slv.ar_prot ),
.slv_ar_region_i ( slv.ar_region ),
.slv_ar_len_i ( slv.ar_len ),
.slv_ar_size_i ( slv.ar_size ),
.slv_ar_burst_i ( slv.ar_burst ),
.slv_ar_lock_i ( slv.ar_lock ),
.slv_ar_cache_i ( slv.ar_cache ),
.slv_ar_qos_i ( slv.ar_qos ),
.slv_ar_id_i ( slv.ar_id ),
.slv_ar_user_i ( slv.ar_user ),
.slv_ar_ready_o ( slv.ar_ready ),
.slv_ar_valid_i ( slv.ar_valid ),
.slv_w_data_i ( slv.w_data ),
.slv_w_strb_i ( slv.w_strb ),
.slv_w_user_i ( slv.w_user ),
.slv_w_last_i ( slv.w_last ),
.slv_w_ready_o ( slv.w_ready ),
.slv_w_valid_i ( slv.w_valid ),
.slv_r_data_o ( slv.r_data ),
.slv_r_resp_o ( slv.r_resp ),
.slv_r_last_o ( slv.r_last ),
.slv_r_id_o ( slv.r_id ),
.slv_r_user_o ( slv.r_user ),
.slv_r_ready_i ( slv.r_ready ),
.slv_r_valid_o ( slv.r_valid ),
.slv_b_resp_o ( slv.b_resp ),
.slv_b_id_o ( slv.b_id ),
.slv_b_user_o ( slv.b_user ),
.slv_b_ready_i ( slv.b_ready ),
.slv_b_valid_o ( slv.b_valid ),
.mst_aw_addr_o ( mst.aw_addr ),
.mst_aw_prot_o ( mst.aw_prot ),
.mst_aw_region_o ( mst.aw_region ),
.mst_aw_atop_o ( mst.aw_atop ),
.mst_aw_len_o ( mst.aw_len ),
.mst_aw_size_o ( mst.aw_size ),
.mst_aw_burst_o ( mst.aw_burst ),
.mst_aw_lock_o ( mst.aw_lock ),
.mst_aw_cache_o ( mst.aw_cache ),
.mst_aw_qos_o ( mst.aw_qos ),
.mst_aw_id_o ( mst.aw_id ),
.mst_aw_user_o ( mst.aw_user ),
.mst_aw_ready_i ( mst.aw_ready ),
.mst_aw_valid_o ( mst.aw_valid ),
.mst_ar_addr_o ( mst.ar_addr ),
.mst_ar_prot_o ( mst.ar_prot ),
.mst_ar_region_o ( mst.ar_region ),
.mst_ar_len_o ( mst.ar_len ),
.mst_ar_size_o ( mst.ar_size ),
.mst_ar_burst_o ( mst.ar_burst ),
.mst_ar_lock_o ( mst.ar_lock ),
.mst_ar_cache_o ( mst.ar_cache ),
.mst_ar_qos_o ( mst.ar_qos ),
.mst_ar_id_o ( mst.ar_id ),
.mst_ar_user_o ( mst.ar_user ),
.mst_ar_ready_i ( mst.ar_ready ),
.mst_ar_valid_o ( mst.ar_valid ),
.mst_w_data_o ( mst.w_data ),
.mst_w_strb_o ( mst.w_strb ),
.mst_w_user_o ( mst.w_user ),
.mst_w_last_o ( mst.w_last ),
.mst_w_ready_i ( mst.w_ready ),
.mst_w_valid_o ( mst.w_valid ),
.mst_r_data_i ( mst.r_data ),
.mst_r_resp_i ( mst.r_resp ),
.mst_r_last_i ( mst.r_last ),
.mst_r_id_i ( mst.r_id ),
.mst_r_user_i ( mst.r_user ),
.mst_r_ready_o ( mst.r_ready ),
.mst_r_valid_i ( mst.r_valid ),
.mst_b_resp_i ( mst.b_resp ),
.mst_b_id_i ( mst.b_id ),
.mst_b_user_i ( mst.b_user ),
.mst_b_ready_o ( mst.b_ready ),
.mst_b_valid_i ( mst.b_valid )
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: validate_params
assert (AXI_STRB_WIDTH == AXI_DATA_WIDTH/8)
else $fatal(1, "AXI_STRB_WIDTH must equal AXI_DATA_WIDTH/8!");
end
`endif
// pragma translate_on
endmodule
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// AXI RISC-V LR/SC Adapter
//
// This adapter adds support for AXI4 exclusive accesses to a slave that natively does not support
// exclusive accesses. It is to be placed between that slave and the upstream master port, so that
// the `mst` port of this module drives the slave and the `slv` port of this module is driven by
// the upstream master.
//
// Exclusive accesses are only enabled for a range of addresses specified through parameters. All
// addresses within that range are guaranteed to fulfill the constraints described in A7.2 of the
// AXI4 standard, both for normal and exclusive memory accesses. Addresses outside that range
// behave like a slave that does not support exclusive memory accesses (see AXI4, A7.2.5).
//
// Limitations:
// - The adapter allows at most one read and one write access to be outstanding at any given
// time.
// - The adapter does not support bursts in exclusive accessing. Only single words can be
// reserved.
//
// Maintainer: Andreas Kurth <akurth@iis.ee.ethz.ch>
module axi_riscv_lrsc #(
/// Exclusively-accessible address range (closed interval from ADDR_BEGIN to ADDR_END)
parameter longint unsigned ADDR_BEGIN = 0,
parameter longint unsigned ADDR_END = 0,
/// AXI Parameters
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Derived Parameters (do NOT change manually!)
localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input logic clk_i,
input logic rst_ni,
/// Slave Interface
input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i,
input logic [2:0] slv_aw_prot_i,
input logic [3:0] slv_aw_region_i,
input logic [5:0] slv_aw_atop_i,
input logic [7:0] slv_aw_len_i,
input logic [2:0] slv_aw_size_i,
input logic [1:0] slv_aw_burst_i,
input logic slv_aw_lock_i,
input logic [3:0] slv_aw_cache_i,
input logic [3:0] slv_aw_qos_i,
input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i,
input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i,
output logic slv_aw_ready_o,
input logic slv_aw_valid_i,
input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i,
input logic [2:0] slv_ar_prot_i,
input logic [3:0] slv_ar_region_i,
input logic [7:0] slv_ar_len_i,
input logic [2:0] slv_ar_size_i,
input logic [1:0] slv_ar_burst_i,
input logic slv_ar_lock_i,
input logic [3:0] slv_ar_cache_i,
input logic [3:0] slv_ar_qos_i,
input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i,
input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i,
output logic slv_ar_ready_o,
input logic slv_ar_valid_i,
input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i,
input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i,
input logic [AXI_USER_WIDTH-1:0] slv_w_user_i,
input logic slv_w_last_i,
output logic slv_w_ready_o,
input logic slv_w_valid_i,
output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o,
output logic [1:0] slv_r_resp_o,
output logic slv_r_last_o,
output logic [AXI_ID_WIDTH-1:0] slv_r_id_o,
output logic [AXI_USER_WIDTH-1:0] slv_r_user_o,
input logic slv_r_ready_i,
output logic slv_r_valid_o,
output logic [1:0] slv_b_resp_o,
output logic [AXI_ID_WIDTH-1:0] slv_b_id_o,
output logic [AXI_USER_WIDTH-1:0] slv_b_user_o,
input logic slv_b_ready_i,
output logic slv_b_valid_o,
/// Master Interface
output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o,
output logic [2:0] mst_aw_prot_o,
output logic [3:0] mst_aw_region_o,
output logic [5:0] mst_aw_atop_o,
output logic [7:0] mst_aw_len_o,
output logic [2:0] mst_aw_size_o,
output logic [1:0] mst_aw_burst_o,
output logic mst_aw_lock_o,
output logic [3:0] mst_aw_cache_o,
output logic [3:0] mst_aw_qos_o,
output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o,
output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o,
input logic mst_aw_ready_i,
output logic mst_aw_valid_o,
output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o,
output logic [2:0] mst_ar_prot_o,
output logic [3:0] mst_ar_region_o,
output logic [7:0] mst_ar_len_o,
output logic [2:0] mst_ar_size_o,
output logic [1:0] mst_ar_burst_o,
output logic mst_ar_lock_o,
output logic [3:0] mst_ar_cache_o,
output logic [3:0] mst_ar_qos_o,
output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o,
output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o,
input logic mst_ar_ready_i,
output logic mst_ar_valid_o,
output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o,
output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o,
output logic [AXI_USER_WIDTH-1:0] mst_w_user_o,
output logic mst_w_last_o,
input logic mst_w_ready_i,
output logic mst_w_valid_o,
input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i,
input logic [1:0] mst_r_resp_i,
input logic mst_r_last_i,
input logic [AXI_ID_WIDTH-1:0] mst_r_id_i,
input logic [AXI_USER_WIDTH-1:0] mst_r_user_i,
output logic mst_r_ready_o,
input logic mst_r_valid_i,
input logic [1:0] mst_b_resp_i,
input logic [AXI_ID_WIDTH-1:0] mst_b_id_i,
input logic [AXI_USER_WIDTH-1:0] mst_b_user_i,
output logic mst_b_ready_o,
input logic mst_b_valid_i
);
// Declarations of Signals and Types
logic [AXI_ID_WIDTH-1:0] art_check_id,
art_set_id,
w_id_d, w_id_q;
logic [AXI_ADDR_WIDTH-1:0] art_check_addr,
art_clr_addr,
art_set_addr,
rd_clr_addr,
wr_clr_addr,
w_addr_d, w_addr_q;
logic art_check_req, art_check_gnt,
art_clr_req, art_clr_gnt,
art_set_req, art_set_gnt,
rd_clr_req, rd_clr_gnt,
wr_clr_req, wr_clr_gnt;
logic art_check_res;
logic b_excl_d, b_excl_q,
r_excl_d, r_excl_q;
typedef enum logic [1:0] {R_IDLE, R_WAIT_AR, R_WAIT_R} r_state_t;
r_state_t r_state_d, r_state_q;
typedef enum logic [2:0] {AW_IDLE, W_FORWARD, W_BYPASS, W_WAIT_ART_CLR, W_DROP, B_FORWARD,
B_INJECT} w_state_t;
w_state_t w_state_d, w_state_q;
// AR and R Channel
// Time-Invariant Signal Assignments
assign mst_ar_addr_o = slv_ar_addr_i;
assign mst_ar_prot_o = slv_ar_prot_i;
assign mst_ar_region_o = slv_ar_region_i;
assign mst_ar_len_o = slv_ar_len_i;
assign mst_ar_size_o = slv_ar_size_i;
assign mst_ar_burst_o = slv_ar_burst_i;
assign mst_ar_lock_o = 1'b0;
assign mst_ar_cache_o = slv_ar_cache_i;
assign mst_ar_qos_o = slv_ar_qos_i;
assign mst_ar_id_o = slv_ar_id_i;
assign mst_ar_user_o = slv_ar_user_i;
assign slv_r_data_o = mst_r_data_i;
assign slv_r_last_o = mst_r_last_i;
assign slv_r_id_o = mst_r_id_i;
assign slv_r_user_o = mst_r_user_i;
// FSM for Time-Variant Signal Assignments
always_comb begin
mst_ar_valid_o = 1'b0;
slv_ar_ready_o = 1'b0;
mst_r_ready_o = 1'b0;
slv_r_valid_o = 1'b0;
slv_r_resp_o = '0;
art_set_addr = '0;
art_set_id = '0;
art_set_req = 1'b0;
rd_clr_addr = '0;
rd_clr_req = 1'b0;
r_excl_d = r_excl_q;
r_state_d = r_state_q;
case (r_state_q)
R_IDLE: begin
if (slv_ar_valid_i) begin
if (slv_ar_addr_i >= ADDR_BEGIN && slv_ar_addr_i <= ADDR_END && slv_ar_lock_i &&
slv_ar_len_i == 8'h00) begin
// Inside exclusively-accessible address range and exclusive access and no
// burst
art_set_addr = slv_ar_addr_i;
art_set_id = slv_ar_id_i;
art_set_req = 1'b1;
r_excl_d = 1'b1;
if (art_set_gnt) begin
mst_ar_valid_o = 1'b1;
if (mst_ar_ready_i) begin
slv_ar_ready_o = 1'b1;
r_state_d = R_WAIT_R;
end else begin
r_state_d = R_WAIT_AR;
end
end
end else begin
// Outside exclusively-accessible address range or regular access or burst
r_excl_d = 1'b0;
mst_ar_valid_o = 1'b1;
if (mst_ar_ready_i) begin
slv_ar_ready_o = 1'b1;
r_state_d = R_WAIT_R;
end else begin
r_state_d = R_WAIT_AR;
end
end
end
end
R_WAIT_AR: begin
mst_ar_valid_o = slv_ar_valid_i;
slv_ar_ready_o = mst_ar_ready_i;
if (mst_ar_ready_i && mst_ar_valid_o) begin
r_state_d = R_WAIT_R;
end
end
R_WAIT_R: begin
mst_r_ready_o = slv_r_ready_i;
slv_r_valid_o = mst_r_valid_i;
if (mst_r_resp_i[1] == 1'b0) begin
slv_r_resp_o = {1'b0, r_excl_q};
end else begin
slv_r_resp_o = mst_r_resp_i;
end
if (mst_r_valid_i && mst_r_ready_o && mst_r_last_i) begin
r_excl_d = 1'b0;
r_state_d = R_IDLE;
end
end
default: begin
r_state_d = R_IDLE;
end
endcase
end
// AW, W and B Channel
// Time-Invariant Signal Assignments
assign mst_aw_addr_o = slv_aw_addr_i;
assign mst_aw_prot_o = slv_aw_prot_i;
assign mst_aw_region_o = slv_aw_region_i;
assign mst_aw_atop_o = slv_aw_atop_i;
assign mst_aw_len_o = slv_aw_len_i;
assign mst_aw_size_o = slv_aw_size_i;
assign mst_aw_burst_o = slv_aw_burst_i;
assign mst_aw_lock_o = 1'b0;
assign mst_aw_cache_o = slv_aw_cache_i;
assign mst_aw_qos_o = slv_aw_qos_i;
assign mst_aw_id_o = slv_aw_id_i;
assign mst_aw_user_o = slv_aw_user_i;
assign mst_w_data_o = slv_w_data_i;
assign mst_w_strb_o = slv_w_strb_i;
assign mst_w_user_o = slv_w_user_i;
assign mst_w_last_o = slv_w_last_i;
always_comb begin
w_addr_d = w_addr_q;
w_id_d = w_id_q;
if (slv_aw_valid_i && slv_aw_ready_o) begin
w_addr_d = slv_aw_addr_i;
w_id_d = slv_aw_id_i;
end
end
// FSM for Time-Variant Signal Assignments
always_comb begin
mst_aw_valid_o = 1'b0;
slv_aw_ready_o = 1'b0;
mst_w_valid_o = 1'b0;
slv_w_ready_o = 1'b0;
slv_b_valid_o = 1'b0;
mst_b_ready_o = 1'b0;
slv_b_resp_o = '0;
slv_b_id_o = '0;
slv_b_user_o = '0;
art_check_addr = '0;
art_check_id = '0;
art_check_req = 1'b0;
wr_clr_addr = '0;
wr_clr_req = 1'b0;
b_excl_d = b_excl_q;
w_state_d = w_state_q;
case (w_state_q)
AW_IDLE: begin
if (slv_aw_valid_i) begin
// New AW, and W channel is idle
if (slv_aw_addr_i >= ADDR_BEGIN && slv_aw_addr_i <= ADDR_END) begin
// Inside exclusively-accessible address range
if (slv_aw_lock_i && slv_aw_len_i == 8'h00) begin
// Exclusive access and no burst, so check if reservation exists
art_check_addr = slv_aw_addr_i;
art_check_id = slv_aw_id_i;
art_check_req = 1'b1;
if (art_check_gnt) begin
if (art_check_res) begin
// Yes, so forward downstream
mst_aw_valid_o = 1'b1;
if (mst_aw_ready_i) begin
slv_aw_ready_o = 1'b1;
b_excl_d = 1'b1;
w_state_d = W_FORWARD;
end
end else begin
// No, drop in W channel.
slv_aw_ready_o = 1'b1;
w_state_d = W_DROP;
end
end
end else begin
// Non-exclusive access or burst, so forward downstream
mst_aw_valid_o = 1'b1;
if (mst_aw_ready_i) begin
slv_aw_ready_o = 1'b1;
w_state_d = W_FORWARD;
end
end
end else begin
// Outside exclusively-accessible address range, so bypass any
// modifications.
mst_aw_valid_o = 1'b1;
slv_aw_ready_o = mst_aw_ready_i;
if (slv_aw_ready_o) begin
w_state_d = W_BYPASS;
end
end
end
end
W_FORWARD: begin
mst_w_valid_o = slv_w_valid_i;
slv_w_ready_o = mst_w_ready_i;
if (slv_w_valid_i && slv_w_ready_o && slv_w_last_i) begin
wr_clr_addr = w_addr_q;
wr_clr_req = 1'b1;
if (wr_clr_gnt) begin
w_state_d = B_FORWARD;
end else begin
w_state_d = W_WAIT_ART_CLR;
end
end
end
W_BYPASS: begin
mst_w_valid_o = slv_w_valid_i;
slv_w_ready_o = mst_w_ready_i;
if (slv_w_valid_i && slv_w_ready_o && slv_w_last_i) begin
w_state_d = B_FORWARD;
end
end
W_WAIT_ART_CLR: begin
wr_clr_addr = w_addr_q;
wr_clr_req = 1'b1;
if (wr_clr_gnt) begin
w_state_d = B_FORWARD;
end
end
W_DROP: begin
slv_w_ready_o = 1'b1;
if (slv_w_valid_i && slv_w_last_i) begin
w_state_d = B_INJECT;
end
end
B_FORWARD: begin
mst_b_ready_o = slv_b_ready_i;
slv_b_valid_o = mst_b_valid_i;
slv_b_resp_o[1] = mst_b_resp_i[1];
slv_b_resp_o[0] = (mst_b_resp_i[1] == 1'b0) ? b_excl_q : mst_b_resp_i[0];
slv_b_user_o = mst_b_user_i;
slv_b_id_o = mst_b_id_i;
if (slv_b_valid_o && slv_b_ready_i) begin
b_excl_d = 1'b0;
w_state_d = AW_IDLE;
end
end
B_INJECT: begin
slv_b_id_o = w_id_q;
slv_b_resp_o = 2'b00;
slv_b_valid_o = 1'b1;
if (slv_b_ready_i) begin
w_state_d = AW_IDLE;
end
end
default: begin
w_state_d = AW_IDLE;
end
endcase
end
// AXI Reservation Table
axi_res_tbl #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH)
) i_art (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clr_addr_i (art_clr_addr),
.clr_req_i (art_clr_req),
.clr_gnt_o (art_clr_gnt),
.set_addr_i (art_set_addr),
.set_id_i (art_set_id),
.set_req_i (art_set_req),
.set_gnt_o (art_set_gnt),
.check_addr_i (art_check_addr),
.check_id_i (art_check_id),
.check_res_o (art_check_res),
.check_req_i (art_check_req),
.check_gnt_o (art_check_gnt)
);
// ART Clear Arbiter
stream_arbiter #(
.DATA_T (logic[AXI_ADDR_WIDTH-1:0]),
.N_INP (2)
) i_non_excl_acc_arb (
.clk_i (clk_i),
.rst_ni (rst_ni),
.inp_data_i ({rd_clr_addr, wr_clr_addr}),
.inp_valid_i ({rd_clr_req, wr_clr_req}),
.inp_ready_o ({rd_clr_gnt, wr_clr_gnt}),
.oup_data_o (art_clr_addr),
.oup_valid_o (art_clr_req),
.oup_ready_i (art_clr_gnt)
);
// Registers
always_ff @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
b_excl_q <= 1'b0;
r_excl_q <= 1'b0;
r_state_q <= R_IDLE;
w_addr_q <= '0;
w_id_q <= '0;
w_state_q <= AW_IDLE;
end else begin
b_excl_q <= b_excl_d;
r_excl_q <= r_excl_d;
r_state_q <= r_state_d;
w_addr_q <= w_addr_d;
w_id_q <= w_id_d;
w_state_q <= w_state_d;
end
end
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: validate_params
assert (ADDR_END > ADDR_BEGIN)
else $fatal(1, "ADDR_END must be greater than ADDR_BEGIN!");
assert (AXI_ADDR_WIDTH > 0)
else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!");
assert (AXI_DATA_WIDTH > 0)
else $fatal(1, "AXI_DATA_WIDTH must be greater than 0!");
assert (AXI_ID_WIDTH > 0)
else $fatal(1, "AXI_ID_WIDTH must be greater than 0!");
end
`endif
// pragma translate_on
endmodule
|
// Copyright (c) 2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Wrapper for the AXI RISC-V LR/SC Adapter that exposes AXI SystemVerilog interfaces.
//
// See the header of `axi_riscv_lrsc` for a description.
//
// Maintainer: Andreas Kurth <akurth@iis.ee.ethz.ch>
module axi_riscv_lrsc_wrap #(
/// Exclusively-accessible address range (closed interval from ADDR_BEGIN to ADDR_END)
parameter longint unsigned ADDR_BEGIN = 0,
parameter longint unsigned ADDR_END = 0,
/// AXI Parameters
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Derived Parameters (do NOT change manually!)
localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input logic clk_i,
input logic rst_ni,
AXI_BUS.Master mst,
AXI_BUS.Slave slv
);
axi_riscv_lrsc #(
.ADDR_BEGIN (ADDR_BEGIN),
.ADDR_END (ADDR_END),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) i_lrsc (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slv_aw_addr_i ( slv.aw_addr ),
.slv_aw_prot_i ( slv.aw_prot ),
.slv_aw_region_i ( slv.aw_region ),
.slv_aw_atop_i ( slv.aw_atop ),
.slv_aw_len_i ( slv.aw_len ),
.slv_aw_size_i ( slv.aw_size ),
.slv_aw_burst_i ( slv.aw_burst ),
.slv_aw_lock_i ( slv.aw_lock ),
.slv_aw_cache_i ( slv.aw_cache ),
.slv_aw_qos_i ( slv.aw_qos ),
.slv_aw_id_i ( slv.aw_id ),
.slv_aw_user_i ( slv.aw_user ),
.slv_aw_ready_o ( slv.aw_ready ),
.slv_aw_valid_i ( slv.aw_valid ),
.slv_ar_addr_i ( slv.ar_addr ),
.slv_ar_prot_i ( slv.ar_prot ),
.slv_ar_region_i ( slv.ar_region ),
.slv_ar_len_i ( slv.ar_len ),
.slv_ar_size_i ( slv.ar_size ),
.slv_ar_burst_i ( slv.ar_burst ),
.slv_ar_lock_i ( slv.ar_lock ),
.slv_ar_cache_i ( slv.ar_cache ),
.slv_ar_qos_i ( slv.ar_qos ),
.slv_ar_id_i ( slv.ar_id ),
.slv_ar_user_i ( slv.ar_user ),
.slv_ar_ready_o ( slv.ar_ready ),
.slv_ar_valid_i ( slv.ar_valid ),
.slv_w_data_i ( slv.w_data ),
.slv_w_strb_i ( slv.w_strb ),
.slv_w_user_i ( slv.w_user ),
.slv_w_last_i ( slv.w_last ),
.slv_w_ready_o ( slv.w_ready ),
.slv_w_valid_i ( slv.w_valid ),
.slv_r_data_o ( slv.r_data ),
.slv_r_resp_o ( slv.r_resp ),
.slv_r_last_o ( slv.r_last ),
.slv_r_id_o ( slv.r_id ),
.slv_r_user_o ( slv.r_user ),
.slv_r_ready_i ( slv.r_ready ),
.slv_r_valid_o ( slv.r_valid ),
.slv_b_resp_o ( slv.b_resp ),
.slv_b_id_o ( slv.b_id ),
.slv_b_user_o ( slv.b_user ),
.slv_b_ready_i ( slv.b_ready ),
.slv_b_valid_o ( slv.b_valid ),
.mst_aw_addr_o ( mst.aw_addr ),
.mst_aw_prot_o ( mst.aw_prot ),
.mst_aw_region_o ( mst.aw_region ),
.mst_aw_atop_o ( mst.aw_atop ),
.mst_aw_len_o ( mst.aw_len ),
.mst_aw_size_o ( mst.aw_size ),
.mst_aw_burst_o ( mst.aw_burst ),
.mst_aw_lock_o ( mst.aw_lock ),
.mst_aw_cache_o ( mst.aw_cache ),
.mst_aw_qos_o ( mst.aw_qos ),
.mst_aw_id_o ( mst.aw_id ),
.mst_aw_user_o ( mst.aw_user ),
.mst_aw_ready_i ( mst.aw_ready ),
.mst_aw_valid_o ( mst.aw_valid ),
.mst_ar_addr_o ( mst.ar_addr ),
.mst_ar_prot_o ( mst.ar_prot ),
.mst_ar_region_o ( mst.ar_region ),
.mst_ar_len_o ( mst.ar_len ),
.mst_ar_size_o ( mst.ar_size ),
.mst_ar_burst_o ( mst.ar_burst ),
.mst_ar_lock_o ( mst.ar_lock ),
.mst_ar_cache_o ( mst.ar_cache ),
.mst_ar_qos_o ( mst.ar_qos ),
.mst_ar_id_o ( mst.ar_id ),
.mst_ar_user_o ( mst.ar_user ),
.mst_ar_ready_i ( mst.ar_ready ),
.mst_ar_valid_o ( mst.ar_valid ),
.mst_w_data_o ( mst.w_data ),
.mst_w_strb_o ( mst.w_strb ),
.mst_w_user_o ( mst.w_user ),
.mst_w_last_o ( mst.w_last ),
.mst_w_ready_i ( mst.w_ready ),
.mst_w_valid_o ( mst.w_valid ),
.mst_r_data_i ( mst.r_data ),
.mst_r_resp_i ( mst.r_resp ),
.mst_r_last_i ( mst.r_last ),
.mst_r_id_i ( mst.r_id ),
.mst_r_user_i ( mst.r_user ),
.mst_r_ready_o ( mst.r_ready ),
.mst_r_valid_i ( mst.r_valid ),
.mst_b_resp_i ( mst.b_resp ),
.mst_b_id_i ( mst.b_id ),
.mst_b_user_i ( mst.b_user ),
.mst_b_ready_o ( mst.b_ready ),
.mst_b_valid_i ( mst.b_valid )
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: validate_params
assert (AXI_STRB_WIDTH == AXI_DATA_WIDTH/8)
else $fatal(1, "AXI_STRB_WIDTH must equal AXI_DATA_WIDTH/8!");
end
`endif
// pragma translate_on
endmodule
|
// Copyright (c) 2019 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Simple standalone synthesis bench for axi_riscv_atomics
module axi_riscv_atomics_synth #(
/// AXI Parameters
parameter integer AXI_ADDR_WIDTH = 64,
parameter integer AXI_DATA_WIDTH = 64,
parameter integer AXI_ID_WIDTH = 4,
parameter integer AXI_USER_WIDTH = 0,
/// Maximum number of AXI bursts outstanding at the same time
parameter integer AXI_MAX_WRITE_TXNS = 4,
// Word width of the widest RISC-V processor that can issue requests to this module.
// 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are
// supported if `aw_strb` is set correctly.
parameter integer RISCV_WORD_WIDTH = 64,
/// Derived Parameters (do NOT change manually!)
localparam integer AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input clk_i,
input rst_ni,
/// Slave Interface
input [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i,
input [2:0] slv_aw_prot_i,
input [3:0] slv_aw_region_i,
input [5:0] slv_aw_atop_i,
input [7:0] slv_aw_len_i,
input [2:0] slv_aw_size_i,
input [1:0] slv_aw_burst_i,
input slv_aw_lock_i,
input [3:0] slv_aw_cache_i,
input [3:0] slv_aw_qos_i,
input [AXI_ID_WIDTH-1:0] slv_aw_id_i,
input [AXI_USER_WIDTH-1:0] slv_aw_user_i,
output slv_aw_ready_o,
input slv_aw_valid_i,
input [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i,
input [2:0] slv_ar_prot_i,
input [3:0] slv_ar_region_i,
input [7:0] slv_ar_len_i,
input [2:0] slv_ar_size_i,
input [1:0] slv_ar_burst_i,
input slv_ar_lock_i,
input [3:0] slv_ar_cache_i,
input [3:0] slv_ar_qos_i,
input [AXI_ID_WIDTH-1:0] slv_ar_id_i,
input [AXI_USER_WIDTH-1:0] slv_ar_user_i,
output slv_ar_ready_o,
input slv_ar_valid_i,
input [AXI_DATA_WIDTH-1:0] slv_w_data_i,
input [AXI_STRB_WIDTH-1:0] slv_w_strb_i,
input [AXI_USER_WIDTH-1:0] slv_w_user_i,
input slv_w_last_i,
output slv_w_ready_o,
input slv_w_valid_i,
output [AXI_DATA_WIDTH-1:0] slv_r_data_o,
output [1:0] slv_r_resp_o,
output slv_r_last_o,
output [AXI_ID_WIDTH-1:0] slv_r_id_o,
output [AXI_USER_WIDTH-1:0] slv_r_user_o,
input slv_r_ready_i,
output slv_r_valid_o,
output [1:0] slv_b_resp_o,
output [AXI_ID_WIDTH-1:0] slv_b_id_o,
output [AXI_USER_WIDTH-1:0] slv_b_user_o,
input slv_b_ready_i,
output slv_b_valid_o,
/// Master Interface
output [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o,
output [2:0] mst_aw_prot_o,
output [3:0] mst_aw_region_o,
output [5:0] mst_aw_atop_o,
output [7:0] mst_aw_len_o,
output [2:0] mst_aw_size_o,
output [1:0] mst_aw_burst_o,
output mst_aw_lock_o,
output [3:0] mst_aw_cache_o,
output [3:0] mst_aw_qos_o,
output [AXI_ID_WIDTH-1:0] mst_aw_id_o,
output [AXI_USER_WIDTH-1:0] mst_aw_user_o,
input mst_aw_ready_i,
output mst_aw_valid_o,
output [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o,
output [2:0] mst_ar_prot_o,
output [3:0] mst_ar_region_o,
output [7:0] mst_ar_len_o,
output [2:0] mst_ar_size_o,
output [1:0] mst_ar_burst_o,
output mst_ar_lock_o,
output [3:0] mst_ar_cache_o,
output [3:0] mst_ar_qos_o,
output [AXI_ID_WIDTH-1:0] mst_ar_id_o,
output [AXI_USER_WIDTH-1:0] mst_ar_user_o,
input mst_ar_ready_i,
output mst_ar_valid_o,
output [AXI_DATA_WIDTH-1:0] mst_w_data_o,
output [AXI_STRB_WIDTH-1:0] mst_w_strb_o,
output [AXI_USER_WIDTH-1:0] mst_w_user_o,
output mst_w_last_o,
input mst_w_ready_i,
output mst_w_valid_o,
input [AXI_DATA_WIDTH-1:0] mst_r_data_i,
input [1:0] mst_r_resp_i,
input mst_r_last_i,
input [AXI_ID_WIDTH-1:0] mst_r_id_i,
input [AXI_USER_WIDTH-1:0] mst_r_user_i,
output mst_r_ready_o,
input mst_r_valid_i,
input [1:0] mst_b_resp_i,
input [AXI_ID_WIDTH-1:0] mst_b_id_i,
input [AXI_USER_WIDTH-1:0] mst_b_user_i,
output mst_b_ready_o,
input mst_b_valid_i
);
axi_riscv_atomics #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH),
.AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS),
.RISCV_WORD_WIDTH (RISCV_WORD_WIDTH)
) i_axi_riscv_atomics (
.clk_i(clk_i),
.rst_ni(rst_ni),
/// Slave Interface
.slv_aw_addr_i(slv_aw_addr_i),
.slv_aw_prot_i(slv_aw_prot_i),
.slv_aw_region_i(slv_aw_region_i),
.slv_aw_atop_i(slv_aw_atop_i),
.slv_aw_len_i(slv_aw_len_i),
.slv_aw_size_i(slv_aw_size_i),
.slv_aw_burst_i(slv_aw_burst_i),
.slv_aw_lock_i(slv_aw_lock_i),
.slv_aw_cache_i(slv_aw_cache_i),
.slv_aw_qos_i(slv_aw_qos_i),
.slv_aw_id_i(slv_aw_id_i),
.slv_aw_user_i(slv_aw_user_i),
.slv_aw_ready_o(slv_aw_ready_o),
.slv_aw_valid_i(slv_aw_valid_i),
.slv_ar_addr_i(slv_ar_addr_i),
.slv_ar_prot_i(slv_ar_prot_i),
.slv_ar_region_i(slv_ar_region_i),
.slv_ar_len_i(slv_ar_len_i),
.slv_ar_size_i(slv_ar_size_i),
.slv_ar_burst_i(slv_ar_burst_i),
.slv_ar_lock_i(slv_ar_lock_i),
.slv_ar_cache_i(slv_ar_cache_i),
.slv_ar_qos_i(slv_ar_qos_i),
.slv_ar_id_i(slv_ar_id_i),
.slv_ar_user_i(slv_ar_user_i),
.slv_ar_ready_o(slv_ar_ready_o),
.slv_ar_valid_i(slv_ar_valid_i),
.slv_w_data_i(slv_w_data_i),
.slv_w_strb_i(slv_w_strb_i),
.slv_w_user_i(slv_w_user_i),
.slv_w_last_i(slv_w_last_i),
.slv_w_ready_o(slv_w_ready_o),
.slv_w_valid_i(slv_w_valid_i),
.slv_r_data_o(slv_r_data_o),
.slv_r_resp_o(slv_r_resp_o),
.slv_r_last_o(slv_r_last_o),
.slv_r_id_o(slv_r_id_o),
.slv_r_user_o(slv_r_user_o),
.slv_r_ready_i(slv_r_ready_i),
.slv_r_valid_o(slv_r_valid_o),
.slv_b_resp_o(slv_b_resp_o),
.slv_b_id_o(slv_b_id_o),
.slv_b_user_o(slv_b_user_o),
.slv_b_ready_i(slv_b_ready_i),
.slv_b_valid_o(slv_b_valid_o),
/// Master Interface
.mst_aw_addr_o(mst_aw_addr_o),
.mst_aw_prot_o(mst_aw_prot_o),
.mst_aw_region_o(mst_aw_region_o),
.mst_aw_atop_o(mst_aw_atop_o),
.mst_aw_len_o(mst_aw_len_o),
.mst_aw_size_o(mst_aw_size_o),
.mst_aw_burst_o(mst_aw_burst_o),
.mst_aw_lock_o(mst_aw_lock_o),
.mst_aw_cache_o(mst_aw_cache_o),
.mst_aw_qos_o(mst_aw_qos_o),
.mst_aw_id_o(mst_aw_id_o),
.mst_aw_user_o(mst_aw_user_o),
.mst_aw_ready_i(mst_aw_ready_i),
.mst_aw_valid_o(mst_aw_valid_o),
.mst_ar_addr_o(mst_ar_addr_o),
.mst_ar_prot_o(mst_ar_prot_o),
.mst_ar_region_o(mst_ar_region_o),
.mst_ar_len_o(mst_ar_len_o),
.mst_ar_size_o(mst_ar_size_o),
.mst_ar_burst_o(mst_ar_burst_o),
.mst_ar_lock_o(mst_ar_lock_o),
.mst_ar_cache_o(mst_ar_cache_o),
.mst_ar_qos_o(mst_ar_qos_o),
.mst_ar_id_o(mst_ar_id_o),
.mst_ar_user_o(mst_ar_user_o),
.mst_ar_ready_i(mst_ar_ready_i),
.mst_ar_valid_o(mst_ar_valid_o),
.mst_w_data_o(mst_w_data_o),
.mst_w_strb_o(mst_w_strb_o),
.mst_w_user_o(mst_w_user_o),
.mst_w_last_o(mst_w_last_o),
.mst_w_ready_i(mst_w_ready_i),
.mst_w_valid_o(mst_w_valid_o),
.mst_r_data_i(mst_r_data_i),
.mst_r_resp_i(mst_r_resp_i),
.mst_r_last_i(mst_r_last_i),
.mst_r_id_i(mst_r_id_i),
.mst_r_user_i(mst_r_user_i),
.mst_r_ready_o(mst_r_ready_o),
.mst_r_valid_i(mst_r_valid_i),
.mst_b_resp_i(mst_b_resp_i),
.mst_b_id_i(mst_b_id_i),
.mst_b_user_i(mst_b_user_i),
.mst_b_ready_o(mst_b_ready_o),
.mst_b_valid_i(mst_b_valid_i)
);
endmodule
|
// Copyright (c) 2019 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Simple standalone synthesis bench for axi_riscv_lrsc
module axi_riscv_lrsc_synth #(
/// Exclusively-accessible address range (closed interval from ADDR_BEGIN to ADDR_END)
parameter integer ADDR_BEGIN = 64'h0000_0000_0000_0000,
parameter integer ADDR_END = 64'h0000_7fff_ffff_ffff,
/// AXI Parameters
parameter integer AXI_ADDR_WIDTH = 64,
parameter integer AXI_DATA_WIDTH = 64,
parameter integer AXI_ID_WIDTH = 4,
parameter integer AXI_USER_WIDTH = 0,
/// Derived Parameters (do NOT change manually!)
localparam integer AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
) (
input clk_i,
input rst_ni,
/// Slave Interface
input [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i,
input [2:0] slv_aw_prot_i,
input [3:0] slv_aw_region_i,
input [5:0] slv_aw_atop_i,
input [7:0] slv_aw_len_i,
input [2:0] slv_aw_size_i,
input [1:0] slv_aw_burst_i,
input slv_aw_lock_i,
input [3:0] slv_aw_cache_i,
input [3:0] slv_aw_qos_i,
input [AXI_ID_WIDTH-1:0] slv_aw_id_i,
input [AXI_USER_WIDTH-1:0] slv_aw_user_i,
output slv_aw_ready_o,
input slv_aw_valid_i,
input [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i,
input [2:0] slv_ar_prot_i,
input [3:0] slv_ar_region_i,
input [7:0] slv_ar_len_i,
input [2:0] slv_ar_size_i,
input [1:0] slv_ar_burst_i,
input slv_ar_lock_i,
input [3:0] slv_ar_cache_i,
input [3:0] slv_ar_qos_i,
input [AXI_ID_WIDTH-1:0] slv_ar_id_i,
input [AXI_USER_WIDTH-1:0] slv_ar_user_i,
output slv_ar_ready_o,
input slv_ar_valid_i,
input [AXI_DATA_WIDTH-1:0] slv_w_data_i,
input [AXI_STRB_WIDTH-1:0] slv_w_strb_i,
input [AXI_USER_WIDTH-1:0] slv_w_user_i,
input slv_w_last_i,
output slv_w_ready_o,
input slv_w_valid_i,
output [AXI_DATA_WIDTH-1:0] slv_r_data_o,
output [1:0] slv_r_resp_o,
output slv_r_last_o,
output [AXI_ID_WIDTH-1:0] slv_r_id_o,
output [AXI_USER_WIDTH-1:0] slv_r_user_o,
input slv_r_ready_i,
output slv_r_valid_o,
output [1:0] slv_b_resp_o,
output [AXI_ID_WIDTH-1:0] slv_b_id_o,
output [AXI_USER_WIDTH-1:0] slv_b_user_o,
input slv_b_ready_i,
output slv_b_valid_o,
/// Master Interface
output [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o,
output [2:0] mst_aw_prot_o,
output [3:0] mst_aw_region_o,
output [5:0] mst_aw_atop_o,
output [7:0] mst_aw_len_o,
output [2:0] mst_aw_size_o,
output [1:0] mst_aw_burst_o,
output mst_aw_lock_o,
output [3:0] mst_aw_cache_o,
output [3:0] mst_aw_qos_o,
output [AXI_ID_WIDTH-1:0] mst_aw_id_o,
output [AXI_USER_WIDTH-1:0] mst_aw_user_o,
input mst_aw_ready_i,
output mst_aw_valid_o,
output [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o,
output [2:0] mst_ar_prot_o,
output [3:0] mst_ar_region_o,
output [7:0] mst_ar_len_o,
output [2:0] mst_ar_size_o,
output [1:0] mst_ar_burst_o,
output mst_ar_lock_o,
output [3:0] mst_ar_cache_o,
output [3:0] mst_ar_qos_o,
output [AXI_ID_WIDTH-1:0] mst_ar_id_o,
output [AXI_USER_WIDTH-1:0] mst_ar_user_o,
input mst_ar_ready_i,
output mst_ar_valid_o,
output [AXI_DATA_WIDTH-1:0] mst_w_data_o,
output [AXI_STRB_WIDTH-1:0] mst_w_strb_o,
output [AXI_USER_WIDTH-1:0] mst_w_user_o,
output mst_w_last_o,
input mst_w_ready_i,
output mst_w_valid_o,
input [AXI_DATA_WIDTH-1:0] mst_r_data_i,
input [1:0] mst_r_resp_i,
input mst_r_last_i,
input [AXI_ID_WIDTH-1:0] mst_r_id_i,
input [AXI_USER_WIDTH-1:0] mst_r_user_i,
output mst_r_ready_o,
input mst_r_valid_i,
input [1:0] mst_b_resp_i,
input [AXI_ID_WIDTH-1:0] mst_b_id_i,
input [AXI_USER_WIDTH-1:0] mst_b_user_i,
output mst_b_ready_o,
input mst_b_valid_i
);
axi_riscv_lrsc #(
.ADDR_BEGIN (ADDR_BEGIN),
.ADDR_END (ADDR_END),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) i_axi_riscv_lrsc (
.clk_i(clk_i),
.rst_ni(rst_ni),
/// Slave Interface
.slv_aw_addr_i(slv_aw_addr_i),
.slv_aw_prot_i(slv_aw_prot_i),
.slv_aw_region_i(slv_aw_region_i),
.slv_aw_atop_i(slv_aw_atop_i),
.slv_aw_len_i(slv_aw_len_i),
.slv_aw_size_i(slv_aw_size_i),
.slv_aw_burst_i(slv_aw_burst_i),
.slv_aw_lock_i(slv_aw_lock_i),
.slv_aw_cache_i(slv_aw_cache_i),
.slv_aw_qos_i(slv_aw_qos_i),
.slv_aw_id_i(slv_aw_id_i),
.slv_aw_user_i(slv_aw_user_i),
.slv_aw_ready_o(slv_aw_ready_o),
.slv_aw_valid_i(slv_aw_valid_i),
.slv_ar_addr_i(slv_ar_addr_i),
.slv_ar_prot_i(slv_ar_prot_i),
.slv_ar_region_i(slv_ar_region_i),
.slv_ar_len_i(slv_ar_len_i),
.slv_ar_size_i(slv_ar_size_i),
.slv_ar_burst_i(slv_ar_burst_i),
.slv_ar_lock_i(slv_ar_lock_i),
.slv_ar_cache_i(slv_ar_cache_i),
.slv_ar_qos_i(slv_ar_qos_i),
.slv_ar_id_i(slv_ar_id_i),
.slv_ar_user_i(slv_ar_user_i),
.slv_ar_ready_o(slv_ar_ready_o),
.slv_ar_valid_i(slv_ar_valid_i),
.slv_w_data_i(slv_w_data_i),
.slv_w_strb_i(slv_w_strb_i),
.slv_w_user_i(slv_w_user_i),
.slv_w_last_i(slv_w_last_i),
.slv_w_ready_o(slv_w_ready_o),
.slv_w_valid_i(slv_w_valid_i),
.slv_r_data_o(slv_r_data_o),
.slv_r_resp_o(slv_r_resp_o),
.slv_r_last_o(slv_r_last_o),
.slv_r_id_o(slv_r_id_o),
.slv_r_user_o(slv_r_user_o),
.slv_r_ready_i(slv_r_ready_i),
.slv_r_valid_o(slv_r_valid_o),
.slv_b_resp_o(slv_b_resp_o),
.slv_b_id_o(slv_b_id_o),
.slv_b_user_o(slv_b_user_o),
.slv_b_ready_i(slv_b_ready_i),
.slv_b_valid_o(slv_b_valid_o),
/// Master Interface
.mst_aw_addr_o(mst_aw_addr_o),
.mst_aw_prot_o(mst_aw_prot_o),
.mst_aw_region_o(mst_aw_region_o),
.mst_aw_atop_o(mst_aw_atop_o),
.mst_aw_len_o(mst_aw_len_o),
.mst_aw_size_o(mst_aw_size_o),
.mst_aw_burst_o(mst_aw_burst_o),
.mst_aw_lock_o(mst_aw_lock_o),
.mst_aw_cache_o(mst_aw_cache_o),
.mst_aw_qos_o(mst_aw_qos_o),
.mst_aw_id_o(mst_aw_id_o),
.mst_aw_user_o(mst_aw_user_o),
.mst_aw_ready_i(mst_aw_ready_i),
.mst_aw_valid_o(mst_aw_valid_o),
.mst_ar_addr_o(mst_ar_addr_o),
.mst_ar_prot_o(mst_ar_prot_o),
.mst_ar_region_o(mst_ar_region_o),
.mst_ar_len_o(mst_ar_len_o),
.mst_ar_size_o(mst_ar_size_o),
.mst_ar_burst_o(mst_ar_burst_o),
.mst_ar_lock_o(mst_ar_lock_o),
.mst_ar_cache_o(mst_ar_cache_o),
.mst_ar_qos_o(mst_ar_qos_o),
.mst_ar_id_o(mst_ar_id_o),
.mst_ar_user_o(mst_ar_user_o),
.mst_ar_ready_i(mst_ar_ready_i),
.mst_ar_valid_o(mst_ar_valid_o),
.mst_w_data_o(mst_w_data_o),
.mst_w_strb_o(mst_w_strb_o),
.mst_w_user_o(mst_w_user_o),
.mst_w_last_o(mst_w_last_o),
.mst_w_ready_i(mst_w_ready_i),
.mst_w_valid_o(mst_w_valid_o),
.mst_r_data_i(mst_r_data_i),
.mst_r_resp_i(mst_r_resp_i),
.mst_r_last_i(mst_r_last_i),
.mst_r_id_i(mst_r_id_i),
.mst_r_user_i(mst_r_user_i),
.mst_r_ready_o(mst_r_ready_o),
.mst_r_valid_i(mst_r_valid_i),
.mst_b_resp_i(mst_b_resp_i),
.mst_b_id_i(mst_b_id_i),
.mst_b_user_i(mst_b_user_i),
.mst_b_ready_o(mst_b_ready_o),
.mst_b_valid_i(mst_b_valid_i)
);
endmodule
|
gitdir: ../../../.git/modules/corev_apu/src/tech_cells_generic
|
.*
!.git*
build
/Bender.lock
/Bender.local
|
package:
name: tech_cells_generic
description: "Technology-agnostic building blocks."
sources:
- target: all(fpga, xilinx)
files:
- src/cluster_clock_gating_xilinx.sv
- src/pulp_clock_gating_xilinx.sv
- src/pulp_clock_mux2_xilinx.sv
- target: not(all(fpga, xilinx))
files:
- src/cluster_clock_gating.sv
- src/pulp_clock_gating.sv
- src/pulp_clock_mux2.sv
- target: not(synthesis)
files:
- src/cluster_clock_and2.sv
- src/cluster_clock_buffer.sv
- src/cluster_clock_inverter.sv
- src/cluster_clock_mux2.sv
- src/cluster_clock_xor2.sv
- src/cluster_level_shifter_in.sv
- src/cluster_level_shifter_in_clamp.sv
- src/cluster_level_shifter_inout.sv
- src/cluster_level_shifter_out.sv
- src/cluster_level_shifter_out_clamp.sv
- src/generic_memory.sv
- src/generic_rom.sv
- src/pad_functional.sv
- src/pulp_buffer.sv
- src/pulp_clock_and2.sv
- src/pulp_clock_buffer.sv
- src/pulp_clock_gating_async.sv
- src/pulp_clock_inverter.sv
- src/pulp_clock_xor2.sv
- src/pulp_level_shifter_in.sv
- src/pulp_level_shifter_in_clamp.sv
- src/pulp_level_shifter_out.sv
- src/pulp_level_shifter_out_clamp.sv
- src/pulp_power_gating.sv
|
# Changelog
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
## Unreleased
## 0.1.1 - 2018-09-12
### Changed
- Polish release
- Keep Changelog
- Move to sources subfolder
## 0.1.0 - 2018-09-12
### Added
- Initial commit. |
SOLDERPAD HARDWARE LICENSE version 0.51
This license is based closely on the Apache License Version 2.0, but is not
approved or endorsed by the Apache Foundation. A copy of the non-modified
Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0.
As this license is not currently OSI or FSF approved, the Licensor permits any
Work licensed under this License, at the option of the Licensee, to be treated
as licensed under the Apache License Version 2.0 (which is so approved).
This License is licensed under the terms of this License and in particular
clause 7 below (Disclaimer of Warranties) applies in relation to its use.
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction, and
distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the Rights owner or entity authorized by the Rights owner
that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all other entities
that control, are controlled by, or are under common control with that entity.
For the purposes of this definition, "control" means (i) the power, direct or
indirect, to cause the direction or management of such entity, whether by
contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the
outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity exercising
permissions granted by this License.
"Rights" means copyright and any similar right including design right (whether
registered or unregistered), semiconductor topography (mask) rights and
database rights (but excluding Patents and Trademarks).
"Source" form shall mean the preferred form for making modifications, including
but not limited to source code, net lists, board layouts, CAD files,
documentation source, and configuration files.
"Object" form shall mean any form resulting from mechanical transformation or
translation of a Source form, including but not limited to compiled object
code, generated documentation, the instantiation of a hardware design and
conversions to other media types, including intermediate forms such as
bytecodes, FPGA bitstreams, artwork and semiconductor topographies (mask
works).
"Work" shall mean the work of authorship, whether in Source form or other
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responsibility, not on behalf of any other Contributor, and only if You agree
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END OF TERMS AND CONDITIONS
|
tech_cells_rtl:
flags: [
skip_synthesis,
]
files: [
src/cluster_clock_gating.sv,
src/pulp_clock_gating.sv,
src/pulp_clock_mux2.sv,
src/pulp_clock_buffer.sv,
src/pulp_clock_inverter.sv,
src/pulp_clock_xor2.sv,
src/pulp_buffer.sv,
src/pulp_level_shifter_in.sv,
src/pulp_level_shifter_in_clamp.sv,
src/pulp_level_shifter_out.sv,
src/pulp_level_shifter_out_clamp.sv,
src/pulp_clock_and2.sv,
src/cluster_clock_buffer.sv,
src/cluster_clock_inverter.sv,
src/cluster_clock_mux2.sv,
src/cluster_clock_xor2.sv,
src/cluster_level_shifter_in.sv,
src/cluster_level_shifter_in_clamp.sv,
src/cluster_level_shifter_out.sv,
src/cluster_level_shifter_out_clamp.sv,
src/cluster_clock_and2.sv,
src/pulp_power_gating.sv,
src/generic_rom.sv,
src/generic_memory.sv,
src/pad_functional.sv,
]
tech_cells_rtl_synth:
files: [
pulp_clock_gating_async.sv,
pulp_sync.sv,
]
tech_cells_fpga:
targets: [
xilinx,
]
files: [
src/cluster_clock_gating_xilinx.sv,
src/pulp_clock_gating_xilinx.sv,
src/pulp_clock_mux2_xilinx.sv,
src/pulp_clock_buffer.sv,
src/pulp_clock_inverter.sv,
src/pulp_clock_xor2.sv,
src/pulp_buffer.sv,
src/pulp_level_shifter_in.sv,
src/pulp_level_shifter_in_clamp.sv,
src/pulp_level_shifter_out.sv,
src/pulp_level_shifter_out_clamp.sv,
src/pulp_clock_and2.sv,
src/cluster_clock_buffer.sv,
src/cluster_clock_inverter.sv,
src/cluster_clock_mux2.sv,
src/cluster_clock_xor2.sv,
src/cluster_level_shifter_in.sv,
src/cluster_level_shifter_in_clamp.sv,
src/cluster_level_shifter_out.sv,
src/cluster_level_shifter_out_clamp.sv,
src/cluster_clock_and2.sv,
src/pulp_clock_gating_async.sv,
src/pulp_power_gating.sv,
]
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_and2
(
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i & clk1_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_buffer
(
input logic clk_i,
output logic clk_o
);
assign clk_o = clk_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_gating
(
input logic clk_i,
input logic en_i,
input logic test_en_i,
output logic clk_o
);
logic clk_en;
always_latch
begin
if (clk_i == 1'b0)
clk_en <= en_i | test_en_i;
end
assign clk_o = clk_i & clk_en;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_gating
(
input logic clk_i,
input logic en_i,
input logic test_en_i,
output logic clk_o
);
assign clk_o = clk_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_inverter
(
input logic clk_i,
output logic clk_o
);
assign clk_o = ~clk_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_mux2
(
input logic clk0_i,
input logic clk1_i,
input logic clk_sel_i,
output logic clk_o
);
always_comb
begin
if (clk_sel_i == 1'b0)
clk_o = clk0_i;
else
clk_o = clk1_i;
end
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_clock_xor2
(
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i ^ clk1_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_level_shifter_in
(
input logic in_i,
output logic out_o
);
assign out_o = in_i;
endmodule
|
module cluster_level_shifter_inout (
input logic data_i,
output logic data_o
);
assign data_o = data_i;
endmodule |
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_level_shifter_in_clamp
(
input logic in_i,
output logic out_o,
input logic clamp_i
);
assign out_o = clamp_i ? 1'b0 : in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_level_shifter_out
(
input logic in_i,
output logic out_o
);
assign out_o = in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module cluster_level_shifter_out_clamp
(
input logic in_i,
output logic out_o,
input logic clamp_i
);
assign out_o = clamp_i ? 1'b0 : in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module generic_memory
#(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 32,
parameter BE_WIDTH = DATA_WIDTH/8
)
(
input logic CLK,
input logic INITN,
input logic CEN,
input logic [ADDR_WIDTH-1:0] A,
input logic WEN,
input logic [DATA_WIDTH-1:0] D,
input logic [BE_WIDTH-1:0] BEN,
output logic [DATA_WIDTH-1:0] Q
);
localparam NUM_WORDS = 2**ADDR_WIDTH;
logic [DATA_WIDTH-1:0] MEM [NUM_WORDS-1:0];
logic [DATA_WIDTH-1:0] M;
genvar i,j;
generate
for (i=0; i<BE_WIDTH; i++)
begin
for (j=0; j<8; j++)
begin
assign M[i*8+j] = BEN[i];
end
end
endgenerate
generate
for (i=0; i < DATA_WIDTH ; i++)
begin
always @ (posedge CLK)
begin
if ( INITN == 1'b1 )
begin
if ( CEN == 1'b0 )
begin
if ( WEN == 1'b0 )
begin
if ( M[i] == 1'b0 )
begin
MEM[A][i] <= D[i];
end
end
else if(WEN == 1'b1)
begin
Q[i] <= MEM[A][i];
end
end
end
end
end
endgenerate
endmodule |
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module generic_rom
#(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter FILE_NAME = "./boot/boot_code.cde"
)
(
input logic CLK,
input logic CEN,
input logic [ADDR_WIDTH-1:0] A,
output logic [DATA_WIDTH-1:0] Q
);
localparam NUM_WORDS = 2**ADDR_WIDTH;
logic [DATA_WIDTH-1:0] MEM [NUM_WORDS-1:0];
logic [ADDR_WIDTH-1:0] A_Q;
initial
begin
$readmemb(FILE_NAME, MEM);
end
always_ff @(posedge CLK)
begin
if (CEN == 1'b0)
A_Q <= A;
end
assign Q = MEM[A_Q];
endmodule |
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pad_functional_pd
(
input logic OEN,
input logic I,
output logic O,
input logic PEN,
inout logic PAD
);
/*
X Unknown
Z Hi-Z
H Pull High
L Pull Low
*/
/*
OEN I PAD PEN | PAD O
|
0 0 - 0/1 | 0 0
0 1 - 0/1 | 1 1
1 0/1 0 0/1 | - 0
1 0/1 1 0/1 | - 1
1 0/1 Z 0 | L L
1 0/1 Z 1 | - X
*/
wire PAD_wi;
bufif0 (PAD, I, OEN);
buf (O, PAD);
bufif0 (PAD_wi, 1'b0, PEN);
rpmos (PAD, PAD_wi, 1'b0);
endmodule
module pad_functional_pu
(
input logic OEN,
input logic I,
output logic O,
input logic PEN,
inout logic PAD
);
/*
X Unknown
Z Hi-Z
H Pull High
L Pull Low
*/
/*
OEN I PAD PEN | PAD O
|
0 0 - 0/1 | 0 0
0 1 - 0/1 | 1 1
1 0/1 0 0/1 | - 0
1 0/1 1 0/1 | - 1
1 0/1 Z 0 | H H
1 0/1 Z 1 | - X
*/
wire PAD_wi;
bufif0 (PAD, I, OEN);
buf (O, PAD);
bufif0 (PAD_wi, 1'b1, PEN);
rpmos (PAD, PAD_wi, 1'b0);
endmodule |
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_buffer
(
input logic in_i,
output logic out_o
);
assign out_o = in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_and2
(
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i & clk1_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_buffer
(
input logic clk_i,
output logic clk_o
);
assign clk_o = clk_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_gating
(
input logic clk_i,
input logic en_i,
input logic test_en_i,
output logic clk_o
);
logic clk_en;
always_latch
begin
if (clk_i == 1'b0)
clk_en <= en_i | test_en_i;
end
assign clk_o = clk_i & clk_en;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_gating_async
(
input logic clk_i,
input logic rstn_i,
input logic en_async_i,
output logic en_ack_o,
input logic test_en_i,
output logic clk_o
);
logic r_sync_0;
logic r_sync_1;
assign en_ack_o = r_sync_1;
always_ff @ (posedge clk_i or negedge rstn_i)
begin
if(~rstn_i)
begin
r_sync_0 <= 1'b0;
r_sync_1 <= 1'b0;
end
else
begin
r_sync_0 <= en_async_i;
r_sync_1 <= r_sync_0;
end
end
pulp_clock_gating i_clk_gate
(
.clk_i ( clk_i ),
.en_i ( r_sync_1 ),
.test_en_i( test_en_i ),
.clk_o ( clk_o )
);
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_gating
(
input logic clk_i,
input logic en_i,
input logic test_en_i,
output logic clk_o
);
assign clk_o = clk_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_inverter
(
input logic clk_i,
output logic clk_o
);
assign clk_o = ~clk_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_mux2
(
input logic clk0_i,
input logic clk1_i,
input logic clk_sel_i,
output logic clk_o
);
always_comb
begin
if (clk_sel_i == 1'b0)
clk_o = clk0_i;
else
clk_o = clk1_i;
end
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_mux2
(
input logic clk0_i,
input logic clk1_i,
input logic clk_sel_i,
output logic clk_o
);
BUFGMUX bufgmux_i (
.S(clk_sel_i),
.I0(clk0_i),
.I1(clk1_i),
.O(clk_o)
);
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_clock_xor2
(
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i ^ clk1_i;
endmodule
|
module pulp_isolation_0
(
input logic data_i,
input logic ena_i,
output logic data_o
);
assign data_o = ena_i ? data_i : 1'b0;
endmodule |
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_level_shifter_in
(
input logic in_i,
output logic out_o
);
assign out_o = in_i;
endmodule
|
module pulp_level_shifter_inout (
input logic data_i,
output logic data_o
);
assign data_o = data_i;
endmodule |
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_level_shifter_in_clamp
(
input logic in_i,
output logic out_o,
input logic clamp_i
);
assign out_o = clamp_i ? 1'b0 : in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_level_shifter_out
(
input logic in_i,
output logic out_o
);
assign out_o = in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_level_shifter_clamp_out
(
input logic in_i,
output logic out_o,
input logic clamp_i
);
assign out_o = clamp_i ? 1'b0 : in_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module pulp_power_gating
(
input logic sleep_i,
output logic sleepout_o
);
assign sleepout_o = sleep_i;
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Antonio Pullini <pullinia@iis.ee.ethz.ch>
module pulp_sync
#(
parameter STAGES = 2
)
(
input logic clk_i,
input logic rstn_i,
input logic serial_i,
output logic serial_o
);
logic [STAGES-1:0] r_reg;
always_ff @(posedge clk_i, negedge rstn_i)
begin
if(!rstn_i)
r_reg <= 'h0;
else
r_reg <= {r_reg[STAGES-2:0], serial_i};
end
assign serial_o = r_reg[STAGES-1];
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
`include "register_interface/assign.svh"
`include "register_interface/typedef.svh"
// Xilinx Peripherals
module ariane_peripherals #(
parameter int AxiAddrWidth = -1,
parameter int AxiDataWidth = -1,
parameter int AxiIdWidth = -1,
parameter int AxiUserWidth = 1,
parameter bit InclUART = 1,
parameter bit InclSPI = 0,
parameter bit InclEthernet = 0,
parameter bit InclGPIO = 0,
parameter bit InclTimer = 1
) (
input logic clk_i , // Clock
input logic rst_ni , // Asynchronous reset active low
AXI_BUS.Slave plic ,
AXI_BUS.Slave uart ,
AXI_BUS.Slave spi ,
AXI_BUS.Slave ethernet ,
AXI_BUS.Slave timer ,
output logic [1:0] irq_o ,
// UART
input logic rx_i ,
output logic tx_o ,
// Ethernet
input wire eth_txck ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
output wire eth_rst_n ,
output wire eth_tx_en ,
output wire [3:0] eth_txd ,
inout wire phy_mdio ,
output logic eth_mdc ,
// MDIO Interface
inout mdio ,
output mdc ,
// SPI
output logic spi_clk_o ,
output logic spi_mosi ,
input logic spi_miso ,
output logic spi_ss
);
// ---------------
// 1. PLIC
// ---------------
logic [ariane_soc::NumSources-1:0] irq_sources;
// Unused interrupt sources
assign irq_sources[ariane_soc::NumSources-1:7] = '0;
REG_BUS #(
.ADDR_WIDTH ( 32 ),
.DATA_WIDTH ( 32 )
) reg_bus (clk_i);
logic plic_penable;
logic plic_pwrite;
logic [31:0] plic_paddr;
logic plic_psel;
logic [31:0] plic_pwdata;
logic [31:0] plic_prdata;
logic plic_pready;
logic plic_pslverr;
axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
.AXI4_RDATA_WIDTH ( AxiDataWidth ),
.AXI4_WDATA_WIDTH ( AxiDataWidth ),
.AXI4_ID_WIDTH ( AxiIdWidth ),
.AXI4_USER_WIDTH ( AxiUserWidth ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32_plic (
.ACLK ( clk_i ),
.ARESETn ( rst_ni ),
.test_en_i ( 1'b0 ),
.AWID_i ( plic.aw_id ),
.AWADDR_i ( plic.aw_addr ),
.AWLEN_i ( plic.aw_len ),
.AWSIZE_i ( plic.aw_size ),
.AWBURST_i ( plic.aw_burst ),
.AWLOCK_i ( plic.aw_lock ),
.AWCACHE_i ( plic.aw_cache ),
.AWPROT_i ( plic.aw_prot ),
.AWREGION_i( plic.aw_region ),
.AWUSER_i ( plic.aw_user ),
.AWQOS_i ( plic.aw_qos ),
.AWVALID_i ( plic.aw_valid ),
.AWREADY_o ( plic.aw_ready ),
.WDATA_i ( plic.w_data ),
.WSTRB_i ( plic.w_strb ),
.WLAST_i ( plic.w_last ),
.WUSER_i ( plic.w_user ),
.WVALID_i ( plic.w_valid ),
.WREADY_o ( plic.w_ready ),
.BID_o ( plic.b_id ),
.BRESP_o ( plic.b_resp ),
.BVALID_o ( plic.b_valid ),
.BUSER_o ( plic.b_user ),
.BREADY_i ( plic.b_ready ),
.ARID_i ( plic.ar_id ),
.ARADDR_i ( plic.ar_addr ),
.ARLEN_i ( plic.ar_len ),
.ARSIZE_i ( plic.ar_size ),
.ARBURST_i ( plic.ar_burst ),
.ARLOCK_i ( plic.ar_lock ),
.ARCACHE_i ( plic.ar_cache ),
.ARPROT_i ( plic.ar_prot ),
.ARREGION_i( plic.ar_region ),
.ARUSER_i ( plic.ar_user ),
.ARQOS_i ( plic.ar_qos ),
.ARVALID_i ( plic.ar_valid ),
.ARREADY_o ( plic.ar_ready ),
.RID_o ( plic.r_id ),
.RDATA_o ( plic.r_data ),
.RRESP_o ( plic.r_resp ),
.RLAST_o ( plic.r_last ),
.RUSER_o ( plic.r_user ),
.RVALID_o ( plic.r_valid ),
.RREADY_i ( plic.r_ready ),
.PENABLE ( plic_penable ),
.PWRITE ( plic_pwrite ),
.PADDR ( plic_paddr ),
.PSEL ( plic_psel ),
.PWDATA ( plic_pwdata ),
.PRDATA ( plic_prdata ),
.PREADY ( plic_pready ),
.PSLVERR ( plic_pslverr )
);
apb_to_reg i_apb_to_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.penable_i ( plic_penable ),
.pwrite_i ( plic_pwrite ),
.paddr_i ( plic_paddr ),
.psel_i ( plic_psel ),
.pwdata_i ( plic_pwdata ),
.prdata_o ( plic_prdata ),
.pready_o ( plic_pready ),
.pslverr_o ( plic_pslverr ),
.reg_o ( reg_bus )
);
// define reg type according to REG_BUS above
`REG_BUS_TYPEDEF_ALL(plic, logic[31:0], logic[31:0], logic[3:0])
plic_req_t plic_req;
plic_rsp_t plic_rsp;
// assign REG_BUS.out to (req_t, rsp_t) pair
`REG_BUS_ASSIGN_TO_REQ(plic_req, reg_bus)
`REG_BUS_ASSIGN_FROM_RSP(reg_bus, plic_rsp)
plic_top #(
.N_SOURCE ( ariane_soc::NumSources ),
.N_TARGET ( ariane_soc::NumTargets ),
.MAX_PRIO ( ariane_soc::MaxPriority ),
.reg_req_t ( plic_req_t ),
.reg_rsp_t ( plic_rsp_t )
) i_plic (
.clk_i,
.rst_ni,
.req_i ( plic_req ),
.resp_o ( plic_rsp ),
.le_i ( '0 ), // 0:level 1:edge
.irq_sources_i ( irq_sources ),
.eip_targets_o ( irq_o )
);
// ---------------
// 2. UART
// ---------------
logic uart_penable;
logic uart_pwrite;
logic [31:0] uart_paddr;
logic uart_psel;
logic [31:0] uart_pwdata;
logic [31:0] uart_prdata;
logic uart_pready;
logic uart_pslverr;
axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
.AXI4_RDATA_WIDTH ( AxiDataWidth ),
.AXI4_WDATA_WIDTH ( AxiDataWidth ),
.AXI4_ID_WIDTH ( AxiIdWidth ),
.AXI4_USER_WIDTH ( AxiUserWidth ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32_uart (
.ACLK ( clk_i ),
.ARESETn ( rst_ni ),
.test_en_i ( 1'b0 ),
.AWID_i ( uart.aw_id ),
.AWADDR_i ( uart.aw_addr ),
.AWLEN_i ( uart.aw_len ),
.AWSIZE_i ( uart.aw_size ),
.AWBURST_i ( uart.aw_burst ),
.AWLOCK_i ( uart.aw_lock ),
.AWCACHE_i ( uart.aw_cache ),
.AWPROT_i ( uart.aw_prot ),
.AWREGION_i( uart.aw_region ),
.AWUSER_i ( uart.aw_user ),
.AWQOS_i ( uart.aw_qos ),
.AWVALID_i ( uart.aw_valid ),
.AWREADY_o ( uart.aw_ready ),
.WDATA_i ( uart.w_data ),
.WSTRB_i ( uart.w_strb ),
.WLAST_i ( uart.w_last ),
.WUSER_i ( uart.w_user ),
.WVALID_i ( uart.w_valid ),
.WREADY_o ( uart.w_ready ),
.BID_o ( uart.b_id ),
.BRESP_o ( uart.b_resp ),
.BVALID_o ( uart.b_valid ),
.BUSER_o ( uart.b_user ),
.BREADY_i ( uart.b_ready ),
.ARID_i ( uart.ar_id ),
.ARADDR_i ( uart.ar_addr ),
.ARLEN_i ( uart.ar_len ),
.ARSIZE_i ( uart.ar_size ),
.ARBURST_i ( uart.ar_burst ),
.ARLOCK_i ( uart.ar_lock ),
.ARCACHE_i ( uart.ar_cache ),
.ARPROT_i ( uart.ar_prot ),
.ARREGION_i( uart.ar_region ),
.ARUSER_i ( uart.ar_user ),
.ARQOS_i ( uart.ar_qos ),
.ARVALID_i ( uart.ar_valid ),
.ARREADY_o ( uart.ar_ready ),
.RID_o ( uart.r_id ),
.RDATA_o ( uart.r_data ),
.RRESP_o ( uart.r_resp ),
.RLAST_o ( uart.r_last ),
.RUSER_o ( uart.r_user ),
.RVALID_o ( uart.r_valid ),
.RREADY_i ( uart.r_ready ),
.PENABLE ( uart_penable ),
.PWRITE ( uart_pwrite ),
.PADDR ( uart_paddr ),
.PSEL ( uart_psel ),
.PWDATA ( uart_pwdata ),
.PRDATA ( uart_prdata ),
.PREADY ( uart_pready ),
.PSLVERR ( uart_pslverr )
);
if (InclUART) begin : gen_uart
apb_uart i_apb_uart (
.CLK ( clk_i ),
.RSTN ( rst_ni ),
.PSEL ( uart_psel ),
.PENABLE ( uart_penable ),
.PWRITE ( uart_pwrite ),
.PADDR ( uart_paddr[4:2] ),
.PWDATA ( uart_pwdata ),
.PRDATA ( uart_prdata ),
.PREADY ( uart_pready ),
.PSLVERR ( uart_pslverr ),
.INT ( irq_sources[0] ),
.OUT1N ( ), // keep open
.OUT2N ( ), // keep open
.RTSN ( ), // no flow control
.DTRN ( ), // no flow control
.CTSN ( 1'b0 ),
.DSRN ( 1'b0 ),
.DCDN ( 1'b0 ),
.RIN ( 1'b0 ),
.SIN ( rx_i ),
.SOUT ( tx_o )
);
end else begin
assign irq_sources[0] = 1'b0;
/* pragma translate_off */
mock_uart i_mock_uart (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.penable_i ( uart_penable ),
.pwrite_i ( uart_pwrite ),
.paddr_i ( uart_paddr ),
.psel_i ( uart_psel ),
.pwdata_i ( uart_pwdata ),
.prdata_o ( uart_prdata ),
.pready_o ( uart_pready ),
.pslverr_o ( uart_pslverr )
);
/* pragma translate_on */
end
// ---------------
// 3. SPI
// ---------------
if (InclSPI) begin : gen_spi
logic [31:0] s_axi_spi_awaddr;
logic [7:0] s_axi_spi_awlen;
logic [2:0] s_axi_spi_awsize;
logic [1:0] s_axi_spi_awburst;
logic [0:0] s_axi_spi_awlock;
logic [3:0] s_axi_spi_awcache;
logic [2:0] s_axi_spi_awprot;
logic [3:0] s_axi_spi_awregion;
logic [3:0] s_axi_spi_awqos;
logic s_axi_spi_awvalid;
logic s_axi_spi_awready;
logic [31:0] s_axi_spi_wdata;
logic [3:0] s_axi_spi_wstrb;
logic s_axi_spi_wlast;
logic s_axi_spi_wvalid;
logic s_axi_spi_wready;
logic [1:0] s_axi_spi_bresp;
logic s_axi_spi_bvalid;
logic s_axi_spi_bready;
logic [31:0] s_axi_spi_araddr;
logic [7:0] s_axi_spi_arlen;
logic [2:0] s_axi_spi_arsize;
logic [1:0] s_axi_spi_arburst;
logic [0:0] s_axi_spi_arlock;
logic [3:0] s_axi_spi_arcache;
logic [2:0] s_axi_spi_arprot;
logic [3:0] s_axi_spi_arregion;
logic [3:0] s_axi_spi_arqos;
logic s_axi_spi_arvalid;
logic s_axi_spi_arready;
logic [31:0] s_axi_spi_rdata;
logic [1:0] s_axi_spi_rresp;
logic s_axi_spi_rlast;
logic s_axi_spi_rvalid;
logic s_axi_spi_rready;
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_spi (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( spi.aw_id ),
.s_axi_awaddr ( spi.aw_addr[31:0] ),
.s_axi_awlen ( spi.aw_len ),
.s_axi_awsize ( spi.aw_size ),
.s_axi_awburst ( spi.aw_burst ),
.s_axi_awlock ( spi.aw_lock ),
.s_axi_awcache ( spi.aw_cache ),
.s_axi_awprot ( spi.aw_prot ),
.s_axi_awregion ( spi.aw_region ),
.s_axi_awqos ( spi.aw_qos ),
.s_axi_awvalid ( spi.aw_valid ),
.s_axi_awready ( spi.aw_ready ),
.s_axi_wdata ( spi.w_data ),
.s_axi_wstrb ( spi.w_strb ),
.s_axi_wlast ( spi.w_last ),
.s_axi_wvalid ( spi.w_valid ),
.s_axi_wready ( spi.w_ready ),
.s_axi_bid ( spi.b_id ),
.s_axi_bresp ( spi.b_resp ),
.s_axi_bvalid ( spi.b_valid ),
.s_axi_bready ( spi.b_ready ),
.s_axi_arid ( spi.ar_id ),
.s_axi_araddr ( spi.ar_addr[31:0] ),
.s_axi_arlen ( spi.ar_len ),
.s_axi_arsize ( spi.ar_size ),
.s_axi_arburst ( spi.ar_burst ),
.s_axi_arlock ( spi.ar_lock ),
.s_axi_arcache ( spi.ar_cache ),
.s_axi_arprot ( spi.ar_prot ),
.s_axi_arregion ( spi.ar_region ),
.s_axi_arqos ( spi.ar_qos ),
.s_axi_arvalid ( spi.ar_valid ),
.s_axi_arready ( spi.ar_ready ),
.s_axi_rid ( spi.r_id ),
.s_axi_rdata ( spi.r_data ),
.s_axi_rresp ( spi.r_resp ),
.s_axi_rlast ( spi.r_last ),
.s_axi_rvalid ( spi.r_valid ),
.s_axi_rready ( spi.r_ready ),
.m_axi_awaddr ( s_axi_spi_awaddr ),
.m_axi_awlen ( s_axi_spi_awlen ),
.m_axi_awsize ( s_axi_spi_awsize ),
.m_axi_awburst ( s_axi_spi_awburst ),
.m_axi_awlock ( s_axi_spi_awlock ),
.m_axi_awcache ( s_axi_spi_awcache ),
.m_axi_awprot ( s_axi_spi_awprot ),
.m_axi_awregion ( s_axi_spi_awregion ),
.m_axi_awqos ( s_axi_spi_awqos ),
.m_axi_awvalid ( s_axi_spi_awvalid ),
.m_axi_awready ( s_axi_spi_awready ),
.m_axi_wdata ( s_axi_spi_wdata ),
.m_axi_wstrb ( s_axi_spi_wstrb ),
.m_axi_wlast ( s_axi_spi_wlast ),
.m_axi_wvalid ( s_axi_spi_wvalid ),
.m_axi_wready ( s_axi_spi_wready ),
.m_axi_bresp ( s_axi_spi_bresp ),
.m_axi_bvalid ( s_axi_spi_bvalid ),
.m_axi_bready ( s_axi_spi_bready ),
.m_axi_araddr ( s_axi_spi_araddr ),
.m_axi_arlen ( s_axi_spi_arlen ),
.m_axi_arsize ( s_axi_spi_arsize ),
.m_axi_arburst ( s_axi_spi_arburst ),
.m_axi_arlock ( s_axi_spi_arlock ),
.m_axi_arcache ( s_axi_spi_arcache ),
.m_axi_arprot ( s_axi_spi_arprot ),
.m_axi_arregion ( s_axi_spi_arregion ),
.m_axi_arqos ( s_axi_spi_arqos ),
.m_axi_arvalid ( s_axi_spi_arvalid ),
.m_axi_arready ( s_axi_spi_arready ),
.m_axi_rdata ( s_axi_spi_rdata ),
.m_axi_rresp ( s_axi_spi_rresp ),
.m_axi_rlast ( s_axi_spi_rlast ),
.m_axi_rvalid ( s_axi_spi_rvalid ),
.m_axi_rready ( s_axi_spi_rready )
);
xlnx_axi_quad_spi i_xlnx_axi_quad_spi (
.ext_spi_clk ( clk_i ),
.s_axi4_aclk ( clk_i ),
.s_axi4_aresetn ( rst_ni ),
.s_axi4_awaddr ( s_axi_spi_awaddr[23:0] ),
.s_axi4_awlen ( s_axi_spi_awlen ),
.s_axi4_awsize ( s_axi_spi_awsize ),
.s_axi4_awburst ( s_axi_spi_awburst ),
.s_axi4_awlock ( s_axi_spi_awlock ),
.s_axi4_awcache ( s_axi_spi_awcache ),
.s_axi4_awprot ( s_axi_spi_awprot ),
.s_axi4_awvalid ( s_axi_spi_awvalid ),
.s_axi4_awready ( s_axi_spi_awready ),
.s_axi4_wdata ( s_axi_spi_wdata ),
.s_axi4_wstrb ( s_axi_spi_wstrb ),
.s_axi4_wlast ( s_axi_spi_wlast ),
.s_axi4_wvalid ( s_axi_spi_wvalid ),
.s_axi4_wready ( s_axi_spi_wready ),
.s_axi4_bresp ( s_axi_spi_bresp ),
.s_axi4_bvalid ( s_axi_spi_bvalid ),
.s_axi4_bready ( s_axi_spi_bready ),
.s_axi4_araddr ( s_axi_spi_araddr[23:0] ),
.s_axi4_arlen ( s_axi_spi_arlen ),
.s_axi4_arsize ( s_axi_spi_arsize ),
.s_axi4_arburst ( s_axi_spi_arburst ),
.s_axi4_arlock ( s_axi_spi_arlock ),
.s_axi4_arcache ( s_axi_spi_arcache ),
.s_axi4_arprot ( s_axi_spi_arprot ),
.s_axi4_arvalid ( s_axi_spi_arvalid ),
.s_axi4_arready ( s_axi_spi_arready ),
.s_axi4_rdata ( s_axi_spi_rdata ),
.s_axi4_rresp ( s_axi_spi_rresp ),
.s_axi4_rlast ( s_axi_spi_rlast ),
.s_axi4_rvalid ( s_axi_spi_rvalid ),
.s_axi4_rready ( s_axi_spi_rready ),
.io0_i ( '0 ),
.io0_o ( spi_mosi ),
.io0_t ( '0 ),
.io1_i ( spi_miso ),
.io1_o ( ),
.io1_t ( '0 ),
.ss_i ( '0 ),
.ss_o ( spi_ss ),
.ss_t ( '0 ),
.sck_o ( spi_clk_o ),
.sck_i ( '0 ),
.sck_t ( ),
.ip2intc_irpt ( irq_sources[1] )
// .ip2intc_irpt ( irq_sources[1] )
);
// assign irq_sources [1] = 1'b0;
end else begin
assign spi_clk_o = 1'b0;
assign spi_mosi = 1'b0;
assign spi_ss = 1'b0;
assign irq_sources [1] = 1'b0;
assign spi.aw_ready = 1'b1;
assign spi.ar_ready = 1'b1;
assign spi.w_ready = 1'b1;
assign spi.b_valid = spi.aw_valid;
assign spi.b_id = spi.aw_id;
assign spi.b_resp = axi_pkg::RESP_SLVERR;
assign spi.b_user = '0;
assign spi.r_valid = spi.ar_valid;
assign spi.r_resp = axi_pkg::RESP_SLVERR;
assign spi.r_data = 'hdeadbeef;
assign spi.r_last = 1'b1;
end
// ---------------
// 4. Ethernet
// ---------------
if (0)
begin
end
else
begin
assign irq_sources [2] = 1'b0;
assign ethernet.aw_ready = 1'b1;
assign ethernet.ar_ready = 1'b1;
assign ethernet.w_ready = 1'b1;
assign ethernet.b_valid = ethernet.aw_valid;
assign ethernet.b_id = ethernet.aw_id;
assign ethernet.b_resp = axi_pkg::RESP_SLVERR;
assign ethernet.b_user = '0;
assign ethernet.r_valid = ethernet.ar_valid;
assign ethernet.r_resp = axi_pkg::RESP_SLVERR;
assign ethernet.r_data = 'hdeadbeef;
assign ethernet.r_last = 1'b1;
end
// ---------------
// 5. Timer
// ---------------
if (InclTimer) begin : gen_timer
logic timer_penable;
logic timer_pwrite;
logic [31:0] timer_paddr;
logic timer_psel;
logic [31:0] timer_pwdata;
logic [31:0] timer_prdata;
logic timer_pready;
logic timer_pslverr;
axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
.AXI4_RDATA_WIDTH ( AxiDataWidth ),
.AXI4_WDATA_WIDTH ( AxiDataWidth ),
.AXI4_ID_WIDTH ( AxiIdWidth ),
.AXI4_USER_WIDTH ( AxiUserWidth ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32_timer (
.ACLK ( clk_i ),
.ARESETn ( rst_ni ),
.test_en_i ( 1'b0 ),
.AWID_i ( timer.aw_id ),
.AWADDR_i ( timer.aw_addr ),
.AWLEN_i ( timer.aw_len ),
.AWSIZE_i ( timer.aw_size ),
.AWBURST_i ( timer.aw_burst ),
.AWLOCK_i ( timer.aw_lock ),
.AWCACHE_i ( timer.aw_cache ),
.AWPROT_i ( timer.aw_prot ),
.AWREGION_i( timer.aw_region ),
.AWUSER_i ( timer.aw_user ),
.AWQOS_i ( timer.aw_qos ),
.AWVALID_i ( timer.aw_valid ),
.AWREADY_o ( timer.aw_ready ),
.WDATA_i ( timer.w_data ),
.WSTRB_i ( timer.w_strb ),
.WLAST_i ( timer.w_last ),
.WUSER_i ( timer.w_user ),
.WVALID_i ( timer.w_valid ),
.WREADY_o ( timer.w_ready ),
.BID_o ( timer.b_id ),
.BRESP_o ( timer.b_resp ),
.BVALID_o ( timer.b_valid ),
.BUSER_o ( timer.b_user ),
.BREADY_i ( timer.b_ready ),
.ARID_i ( timer.ar_id ),
.ARADDR_i ( timer.ar_addr ),
.ARLEN_i ( timer.ar_len ),
.ARSIZE_i ( timer.ar_size ),
.ARBURST_i ( timer.ar_burst ),
.ARLOCK_i ( timer.ar_lock ),
.ARCACHE_i ( timer.ar_cache ),
.ARPROT_i ( timer.ar_prot ),
.ARREGION_i( timer.ar_region ),
.ARUSER_i ( timer.ar_user ),
.ARQOS_i ( timer.ar_qos ),
.ARVALID_i ( timer.ar_valid ),
.ARREADY_o ( timer.ar_ready ),
.RID_o ( timer.r_id ),
.RDATA_o ( timer.r_data ),
.RRESP_o ( timer.r_resp ),
.RLAST_o ( timer.r_last ),
.RUSER_o ( timer.r_user ),
.RVALID_o ( timer.r_valid ),
.RREADY_i ( timer.r_ready ),
.PENABLE ( timer_penable ),
.PWRITE ( timer_pwrite ),
.PADDR ( timer_paddr ),
.PSEL ( timer_psel ),
.PWDATA ( timer_pwdata ),
.PRDATA ( timer_prdata ),
.PREADY ( timer_pready ),
.PSLVERR ( timer_pslverr )
);
apb_timer #(
.APB_ADDR_WIDTH ( 32 ),
.TIMER_CNT ( 2 )
) i_timer (
.HCLK ( clk_i ),
.HRESETn ( rst_ni ),
.PSEL ( timer_psel ),
.PENABLE ( timer_penable ),
.PWRITE ( timer_pwrite ),
.PADDR ( timer_paddr ),
.PWDATA ( timer_pwdata ),
.PRDATA ( timer_prdata ),
.PREADY ( timer_pready ),
.PSLVERR ( timer_pslverr ),
.irq_o ( irq_sources[6:3] )
);
end
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Description: Contains SoC information as constants
package ariane_soc;
// M-Mode Hart, S-Mode Hart
localparam int unsigned NumTargets = 2;
// Uart, SPI, Ethernet, reserved
localparam int unsigned NumSources = 30;
localparam int unsigned MaxPriority = 7;
localparam NrSlaves = 3; // actually masters, but slaves on the crossbar
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam IdWidthSlave = IdWidth + $clog2(NrSlaves);
typedef enum int unsigned {
DRAM = 0,
eFPGA = 1,
AES = 2,
DMA = 3,
GPIO = 4,
Ethernet = 5,
SPI = 6,
Timer = 7,
UART = 8,
PLIC = 9,
CLINT = 10,
ROM = 11,
Debug = 12
} axi_slaves_t;
localparam NB_PERIPHERALS = Debug + 1;
localparam logic[63:0] DebugLength = 64'h1000;
localparam logic[63:0] ROMLength = 64'h10000;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h1000;
localparam logic[63:0] TimerLength = 64'h1000;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] GPIOLength = 64'h1000;
localparam logic[63:0] DMALength = 64'h10000;
localparam logic[63:0] AESLength = 64'h10000;
localparam logic[63:0] eFPGALength = 64'h10000;
localparam logic[63:0] DRAMLength = 64'h40000000; // 1GByte of DDR (split between two chips on Genesys2)
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
// Instantiate AXI protocol checkers
localparam bit GenProtocolChecker = 1'b0;
typedef enum logic [63:0] {
DebugBase = 64'h0000_0000,
ROMBase = 64'h0001_0000,
CLINTBase = 64'h0200_0000,
PLICBase = 64'h0C00_0000,
UARTBase = 64'h1000_0000,
TimerBase = 64'h1800_0000,
SPIBase = 64'h2000_0000,
EthernetBase = 64'h3000_0000,
GPIOBase = 64'h4000_0000,
DMABase = 64'h5000_0000,
AESBase = 64'h6000_0000,
eFPGABase = 64'h7000_0000,
DRAMBase = 64'h8000_0000
} soc_bus_start_t;
localparam NrRegion = 1;
localparam logic [NrRegion-1:0][NB_PERIPHERALS-1:0] ValidRule = {{NrRegion * NB_PERIPHERALS}{1'b1}};
localparam ariane_pkg::ariane_cfg_t ArianeSocCfg = '{
RASDepth: 2,
BTBEntries: 32,
BHTEntries: 128,
// idempotent region
NrNonIdempotentRules: 1,
NonIdempotentAddrBase: {64'b0},
NonIdempotentLength: {DRAMBase},
NrExecuteRegionRules: 3,
ExecuteRegionAddrBase: {DRAMBase, ROMBase, DebugBase},
ExecuteRegionLength: {DRAMLength, ROMLength, DebugLength},
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {DRAMBase},
CachedRegionLength: {DRAMLength},
// cache config
Axi64BitCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: DebugBase,
NrPMPEntries: 8
};
endpackage
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Description: Contains SoC information as constants
package ariane_soc;
// M-Mode Hart, S-Mode Hart
localparam int unsigned NumTargets = 2;
// Uart, SPI, Ethernet, reserved
localparam int unsigned NumSources = 30;
localparam int unsigned MaxPriority = 7;
localparam NrSlaves = 2; // actually masters, but slaves on the crossbar
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam IdWidthSlave = IdWidth + $clog2(NrSlaves);
typedef enum int unsigned {
DRAM = 0,
GPIO = 1,
Ethernet = 2,
SPI = 3,
Timer = 4,
UART = 5,
PLIC = 6,
CLINT = 7,
ROM = 8,
Debug = 9
} axi_slaves_t;
localparam NB_PERIPHERALS = Debug + 1;
localparam logic[63:0] DebugLength = 64'h1000;
localparam logic[63:0] ROMLength = 64'h10000;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h1000;
localparam logic[63:0] TimerLength = 64'h1000;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] GPIOLength = 64'h1000;
localparam logic[63:0] DRAMLength = 64'h40000000; // 1GByte of DDR (split between two chips on Genesys2)
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
// Instantiate AXI protocol checkers
localparam bit GenProtocolChecker = 1'b0;
typedef enum logic [63:0] {
DebugBase = 64'h0000_0000,
ROMBase = 64'h0001_0000,
CLINTBase = 64'h0200_0000,
PLICBase = 64'h0C00_0000,
UARTBase = 64'h1000_0000,
TimerBase = 64'h1800_0000,
SPIBase = 64'h2000_0000,
EthernetBase = 64'h3000_0000,
GPIOBase = 64'h4000_0000,
DRAMBase = 64'h8000_0000
} soc_bus_start_t;
localparam NrRegion = 1;
localparam logic [NrRegion-1:0][NB_PERIPHERALS-1:0] ValidRule = {{NrRegion * NB_PERIPHERALS}{1'b1}};
localparam ariane_pkg::ariane_cfg_t ArianeSocCfg = '{
RASDepth: 2,
BTBEntries: 32,
BHTEntries: 128,
// idempotent region
NrNonIdempotentRules: 1,
NonIdempotentAddrBase: {64'b0},
NonIdempotentLength: {DRAMBase},
NrExecuteRegionRules: 3,
ExecuteRegionAddrBase: {DRAMBase, ROMBase, DebugBase},
ExecuteRegionLength: {DRAMLength, ROMLength, DebugLength},
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {DRAMBase},
CachedRegionLength: {DRAMLength},
// cache config
Axi64BitCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: DebugBase,
NrPMPEntries: 8
};
endpackage
|
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
#include "Variane_testharness.h"
#include "verilator.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "Variane_testharness__Dpi.h"
#include <stdio.h>
#include <iostream>
#include <iomanip>
#include <string>
#include <getopt.h>
#include <chrono>
#include <ctime>
#include <signal.h>
#include <unistd.h>
#include <fesvr/dtm.h>
#include <fesvr/htif_hexwriter.h>
#include <fesvr/elfloader.h>
#include "remote_bitbang.h"
// This software is heavily based on Rocket Chip
// Checkout this awesome project:
// https://github.com/freechipsproject/rocket-chip/
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. You can also use a double, if you wish.
static vluint64_t main_time = 0;
static const char *verilog_plusargs[] = {"jtag_rbb_enable", "time_out", "debug_disable"};
#ifndef DROMAJO
extern dtm_t* dtm;
extern remote_bitbang_t * jtag;
void handle_sigterm(int sig) {
dtm->stop();
}
#endif
// Called by $time in Verilog converts to double, to match what SystemC does
double sc_time_stamp () {
return main_time;
}
static void usage(const char * program_name) {
printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n",
program_name);
fputs("\
Run a BINARY on the Ariane emulator.\n\
\n\
Mandatory arguments to long options are mandatory for short options too.\n\
\n\
EMULATOR OPTIONS\n\
-r, --rbb-port=PORT Use PORT for remote bit bang (with OpenOCD and GDB) \n\
If not specified, a random port will be chosen\n\
automatically.\n\
", stdout);
#if VM_TRACE == 0
fputs("\
\n\
EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n",
stdout);
#endif
fputs("\
-v, --vcd=FILE, Write vcd trace to FILE (or '-' for stdout)\n\
-p, Print performance statistic at end of test\n\
", stdout);
// fputs("\n" PLUSARG_USAGE_OPTIONS, stdout);
fputs("\n" HTIF_USAGE_OPTIONS, stdout);
printf("\n"
"EXAMPLES\n"
" - run a bare metal test:\n"
" %s $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n"
" - run a bare metal test showing cycle-by-cycle information:\n"
" %s spike-dasm < trace_core_00_0.dasm > trace.out\n"
#if VM_TRACE
" - run a bare metal test to generate a VCD waveform:\n"
" %s -v rv64ui-p-add.vcd $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n"
#endif
" - run an ELF (you wrote, called 'hello') using the proxy kernel:\n"
" %s pk hello\n",
program_name, program_name, program_name
#if VM_TRACE
, program_name
#endif
);
}
// In case we use the DTM we do not want to use the JTAG
// to preload the data but only use the DTM to host fesvr functionality.
class preload_aware_dtm_t : public dtm_t {
public:
preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {}
bool is_address_preloaded(addr_t taddr, size_t len) override { return true; }
// We do not want to reset the hart here as the reset function in `dtm_t` seems to disregard
// the privilege level and in general does not perform propper reset (despite the name).
// As all our binaries in preloading will always start at the base of DRAM this should not
// be such a big problem.
void reset() {}
};
int main(int argc, char **argv) {
std::clock_t c_start = std::clock();
auto t_start = std::chrono::high_resolution_clock::now();
bool verbose;
bool perf;
unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
uint64_t max_cycles = -1;
int ret = 0;
bool print_cycles = false;
// Port numbers are 16 bit unsigned integers.
uint16_t rbb_port = 0;
#if VM_TRACE
FILE * vcdfile = NULL;
uint64_t start = 0;
#endif
char ** htif_argv = NULL;
int verilog_plusargs_legal = 1;
while (1) {
static struct option long_options[] = {
{"cycle-count", no_argument, 0, 'c' },
{"help", no_argument, 0, 'h' },
{"max-cycles", required_argument, 0, 'm' },
{"seed", required_argument, 0, 's' },
{"rbb-port", required_argument, 0, 'r' },
{"verbose", no_argument, 0, 'V' },
#if VM_TRACE
{"vcd", required_argument, 0, 'v' },
{"dump-start", required_argument, 0, 'x' },
#endif
HTIF_LONG_OPTIONS
};
int option_index = 0;
#if VM_TRACE
int c = getopt_long(argc, argv, "-chpm:s:r:v:Vx:", long_options, &option_index);
#else
int c = getopt_long(argc, argv, "-chpm:s:r:V", long_options, &option_index);
#endif
if (c == -1) break;
retry:
switch (c) {
// Process long and short EMULATOR options
case '?': usage(argv[0]); return 1;
case 'c': print_cycles = true; break;
case 'h': usage(argv[0]); return 0;
case 'm': max_cycles = atoll(optarg); break;
case 's': random_seed = atoi(optarg); break;
case 'r': rbb_port = atoi(optarg); break;
case 'V': verbose = true; break;
case 'p': perf = true; break;
#ifdef DROMAJO
case 'D': break;
#endif
#if VM_TRACE
case 'v': {
vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w");
if (!vcdfile) {
std::cerr << "Unable to open " << optarg << " for VCD write\n";
return 1;
}
break;
}
case 'x': start = atoll(optarg); break;
#endif
// Process legacy '+' EMULATOR arguments by replacing them with
// their getopt equivalents
case 1: {
std::string arg = optarg;
if (arg.substr(0, 1) != "+") {
optind--;
goto done_processing;
}
if (arg == "+verbose")
c = 'V';
else if (arg.substr(0, 12) == "+max-cycles=") {
c = 'm';
optarg = optarg+12;
}
#ifdef DROMAJO
else if (arg.substr(0, 12) == "+checkpoint=") {
c = 'D';
optarg = optarg+12;
}
#endif
#if VM_TRACE
else if (arg.substr(0, 12) == "+dump-start=") {
c = 'x';
optarg = optarg+12;
}
#endif
else if (arg.substr(0, 12) == "+cycle-count")
c = 'c';
// If we don't find a legacy '+' EMULATOR argument, it still could be
// a VERILOG_PLUSARG and not an error.
else if (verilog_plusargs_legal) {
const char ** plusarg = &verilog_plusargs[0];
int legal_verilog_plusarg = 0;
while (*plusarg && (legal_verilog_plusarg == 0)){
if (arg.substr(1, strlen(*plusarg)) == *plusarg) {
legal_verilog_plusarg = 1;
}
plusarg ++;
}
if (!legal_verilog_plusarg) {
verilog_plusargs_legal = 0;
} else {
c = 'P';
}
goto retry;
}
// If we STILL don't find a legacy '+' argument, it still could be
// an HTIF (HOST) argument and not an error. If this is the case, then
// we're done processing EMULATOR and VERILOG arguments.
else {
static struct option htif_long_options [] = { HTIF_LONG_OPTIONS };
struct option * htif_option = &htif_long_options[0];
while (htif_option->name) {
if (arg.substr(1, strlen(htif_option->name)) == htif_option->name) {
optind--;
goto done_processing;
}
htif_option++;
}
std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \""
<< arg << "\"\n";
c = '?';
}
goto retry;
}
case 'P': break; // Nothing to do here, Verilog PlusArg
// Realize that we've hit HTIF (HOST) arguments or error out
default:
if (c >= HTIF_LONG_OPTIONS_OPTIND) {
optind--;
goto done_processing;
}
c = '?';
goto retry;
}
}
done_processing:
// allow proceeding without a binary if DROMAJO set,
// binary will be loaded through checkpoint
#ifndef DROMAJO
if (optind == argc) {
std::cerr << "No binary specified for emulator\n";
usage(argv[0]);
return 1;
}
#endif
int htif_argc = 1 + argc - optind;
htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
htif_argv[0] = argv[0];
for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++];
const char *vcd_file = NULL;
Verilated::commandArgs(argc, argv);
#ifndef DROMAJO
jtag = new remote_bitbang_t(rbb_port);
dtm = new preload_aware_dtm_t(htif_argc, htif_argv);
signal(SIGTERM, handle_sigterm);
#endif
std::unique_ptr<Variane_testharness> top(new Variane_testharness);
// Use an hitf hexwriter to read the binary data.
htif_hexwriter_t htif(0x0, 1, -1);
memif_t memif(&htif);
reg_t entry;
load_elf(htif_argv[1], &memif, &entry);
#if VM_TRACE
Verilated::traceEverOn(true); // Verilator must compute traced signals
std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC(vcdfd.get()));
if (vcdfile) {
top->trace(tfp.get(), 99); // Trace 99 levels of hierarchy
tfp->open("");
}
#endif
for (int i = 0; i < 10; i++) {
top->rst_ni = 0;
top->clk_i = 0;
top->rtc_i = 0;
top->eval();
#if VM_TRACE
tfp->dump(static_cast<vluint64_t>(main_time * 2));
#endif
top->clk_i = 1;
top->eval();
#if VM_TRACE
tfp->dump(static_cast<vluint64_t>(main_time * 2 + 1));
#endif
main_time++;
}
top->rst_ni = 1;
// Preload memory.
size_t mem_size = 0xFFFFFF;
memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_ram__DOT__Mem_DP);
#ifndef DROMAJO
while (!dtm->done() && !jtag->done()) {
#else
// the simulation gets killed by dromajo
while (true) {
#endif
top->clk_i = 0;
top->eval();
#if VM_TRACE
// dump = tfp && trace_count >= start;
// if (dump)
tfp->dump(static_cast<vluint64_t>(main_time * 2));
#endif
top->clk_i = 1;
top->eval();
#if VM_TRACE
// if (dump)
tfp->dump(static_cast<vluint64_t>(main_time * 2 + 1));
#endif
// toggle RTC
if (main_time % 2 == 0) {
top->rtc_i ^= 1;
}
main_time++;
}
#if VM_TRACE
if (tfp)
tfp->close();
if (vcdfile)
fclose(vcdfile);
#endif
#ifndef DROMAJO
if (dtm->exit_code()) {
fprintf(stderr, "%s *** FAILED *** (code = %d) after %ld cycles\n", htif_argv[1], dtm->exit_code(), main_time);
ret = dtm->exit_code();
} else if (jtag->exit_code()) {
fprintf(stderr, "%s *** FAILED *** (code = %d, seed %d) after %ld cycles\n", htif_argv[1], jtag->exit_code(), random_seed, main_time);
ret = jtag->exit_code();
} else {
fprintf(stderr, "%s completed after %ld cycles\n", htif_argv[1], main_time);
}
if (dtm) delete dtm;
if (jtag) delete jtag;
#endif
std::clock_t c_end = std::clock();
auto t_end = std::chrono::high_resolution_clock::now();
if (perf) {
std::cout << std::fixed << std::setprecision(2) << "CPU time used: "
<< 1000.0 * (c_end-c_start) / CLOCKS_PER_SEC << " ms\n"
<< "Wall clock time passed: "
<< std::chrono::duration<double, std::milli>(t_end-t_start).count()
<< " ms\n";
}
return ret;
}
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Date: 15/04/2017
// Description: Top level testbench module. Instantiates the top level DUT, configures
// the virtual interfaces and starts the test passed by +UVM_TEST+
import ariane_pkg::*;
import uvm_pkg::*;
`include "uvm_macros.svh"
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].gen_mem.i_ram.Mem_DP[(``P``)]
import "DPI-C" function read_elf(input string filename);
import "DPI-C" function byte get_section(output longint address, output longint len);
import "DPI-C" context function void read_section(input longint address, inout byte buffer[]);
module ariane_tb;
static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
localparam int unsigned CLOCK_PERIOD = 20ns;
// toggle with RTC period
localparam int unsigned RTC_CLOCK_PERIOD = 30.517us;
localparam NUM_WORDS = 2**25;
logic clk_i;
logic rst_ni;
logic rtc_i;
longint unsigned cycles;
longint unsigned max_cycles;
logic [31:0] exit_o;
string binary = "";
ariane_testharness #(
.NUM_WORDS ( NUM_WORDS ),
.InclSimDTM ( 1'b1 ),
.StallRandomOutput ( 1'b1 ),
.StallRandomInput ( 1'b1 )
) dut (
.clk_i,
.rst_ni,
.rtc_i,
.exit_o
);
`ifdef SPIKE_TANDEM
spike #(
.Size ( NUM_WORDS * 8 )
) i_spike (
.clk_i,
.rst_ni,
.clint_tick_i ( rtc_i ),
.commit_instr_i ( dut.i_ariane.commit_instr_id_commit ),
.commit_ack_i ( dut.i_ariane.commit_ack ),
.exception_i ( dut.i_ariane.ex_commit ),
.waddr_i ( dut.i_ariane.waddr_commit_id ),
.wdata_i ( dut.i_ariane.wdata_commit_id ),
.priv_lvl_i ( dut.i_ariane.priv_lvl )
);
initial begin
$display("Running binary in tandem mode");
end
`endif
// Clock process
initial begin
clk_i = 1'b0;
rst_ni = 1'b0;
repeat(8)
#(CLOCK_PERIOD/2) clk_i = ~clk_i;
rst_ni = 1'b1;
forever begin
#(CLOCK_PERIOD/2) clk_i = 1'b1;
#(CLOCK_PERIOD/2) clk_i = 1'b0;
//if (cycles > max_cycles)
// $fatal(1, "Simulation reached maximum cycle count of %d", max_cycles);
cycles++;
end
end
initial begin
forever begin
rtc_i = 1'b0;
#(RTC_CLOCK_PERIOD/2) rtc_i = 1'b1;
#(RTC_CLOCK_PERIOD/2) rtc_i = 1'b0;
end
end
initial begin
forever begin
wait (exit_o[0]);
if ((exit_o >> 1)) begin
`uvm_error( "Core Test", $sformatf("*** FAILED *** (tohost = %0d)", (exit_o >> 1)))
end else begin
`uvm_info( "Core Test", $sformatf("*** SUCCESS *** (tohost = %0d)", (exit_o >> 1)), UVM_LOW)
end
$finish();
end
end
// for faster simulation we can directly preload the ELF
// Note that we are loosing the capabilities to use risc-fesvr though
initial begin
automatic logic [7:0][7:0] mem_row;
longint address, len;
byte buffer[];
void'(uvcl.get_arg_value("+PRELOAD=", binary));
if (binary != "") begin
`uvm_info( "Core Test", $sformatf("Preloading ELF: %s", binary), UVM_LOW)
void'(read_elf(binary));
// wait with preloading, otherwise randomization will overwrite the existing value
wait(rst_ni);
// while there are more sections to process
while (get_section(address, len)) begin
automatic int num_words = (len+7)/8;
`uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len),
UVM_LOW)
buffer = new [num_words*8];
void'(read_section(address, buffer));
// preload memories
// 64-bit
for (int i = 0; i < num_words; i++) begin
mem_row = '0;
for (int j = 0; j < 8; j++) begin
mem_row[j] = buffer[i*8 + j];
end
`MAIN_MEM((address[28:0] >> 3) + i) = mem_row;
end
end
end
end
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Date: 19.03.2017
// Description: Test-harness for Ariane
// Instantiates an AXI-Bus and memories
`include "axi/assign.svh"
module ariane_testharness #(
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
`ifdef DROMAJO
parameter bit InclSimDTM = 1'b0,
`else
parameter bit InclSimDTM = 1'b1,
`endif
parameter int unsigned NUM_WORDS = 2**25, // memory size
parameter bit StallRandomOutput = 1'b0,
parameter bit StallRandomInput = 1'b0
) (
input logic clk_i,
input logic rtc_i,
input logic rst_ni,
output logic [31:0] exit_o
);
localparam [7:0] hart_id = '0;
// disable test-enable
logic test_en;
logic ndmreset;
logic ndmreset_n;
logic debug_req_core;
int jtag_enable;
logic init_done;
logic [31:0] jtag_exit, dmi_exit;
logic jtag_TCK;
logic jtag_TMS;
logic jtag_TDI;
logic jtag_TRSTn;
logic jtag_TDO_data;
logic jtag_TDO_driven;
logic debug_req_valid;
logic debug_req_ready;
logic debug_resp_valid;
logic debug_resp_ready;
logic jtag_req_valid;
logic [6:0] jtag_req_bits_addr;
logic [1:0] jtag_req_bits_op;
logic [31:0] jtag_req_bits_data;
logic jtag_resp_ready;
logic jtag_resp_valid;
logic dmi_req_valid;
logic dmi_resp_ready;
logic dmi_resp_valid;
dm::dmi_req_t jtag_dmi_req;
dm::dmi_req_t dmi_req;
dm::dmi_req_t debug_req;
dm::dmi_resp_t debug_resp;
assign test_en = 1'b0;
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidth ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) slave[ariane_soc::NrSlaves-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) master[ariane_soc::NB_PERIPHERALS-1:0]();
rstgen i_rstgen_main (
.clk_i ( clk_i ),
.rst_ni ( rst_ni & (~ndmreset) ),
.test_mode_i ( test_en ),
.rst_no ( ndmreset_n ),
.init_no ( ) // keep open
);
// ---------------
// Debug
// ---------------
assign init_done = rst_ni;
logic debug_enable;
initial begin
if (!$value$plusargs("jtag_rbb_enable=%b", jtag_enable)) jtag_enable = 'h0;
if ($test$plusargs("debug_disable")) debug_enable = 'h0; else debug_enable = 'h1;
if (riscv::XLEN != 32 & riscv::XLEN != 64) $error("XLEN different from 32 and 64");
end
// debug if MUX
assign debug_req_valid = (jtag_enable[0]) ? jtag_req_valid : dmi_req_valid;
assign debug_resp_ready = (jtag_enable[0]) ? jtag_resp_ready : dmi_resp_ready;
assign debug_req = (jtag_enable[0]) ? jtag_dmi_req : dmi_req;
assign exit_o = (jtag_enable[0]) ? jtag_exit : dmi_exit;
assign jtag_resp_valid = (jtag_enable[0]) ? debug_resp_valid : 1'b0;
assign dmi_resp_valid = (jtag_enable[0]) ? 1'b0 : debug_resp_valid;
// SiFive's SimJTAG Module
// Converts to DPI calls
SimJTAG i_SimJTAG (
.clock ( clk_i ),
.reset ( ~rst_ni ),
.enable ( jtag_enable[0] ),
.init_done ( init_done ),
.jtag_TCK ( jtag_TCK ),
.jtag_TMS ( jtag_TMS ),
.jtag_TDI ( jtag_TDI ),
.jtag_TRSTn ( jtag_TRSTn ),
.jtag_TDO_data ( jtag_TDO_data ),
.jtag_TDO_driven ( jtag_TDO_driven ),
.exit ( jtag_exit )
);
dmi_jtag i_dmi_jtag (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( test_en ),
.dmi_req_o ( jtag_dmi_req ),
.dmi_req_valid_o ( jtag_req_valid ),
.dmi_req_ready_i ( debug_req_ready ),
.dmi_resp_i ( debug_resp ),
.dmi_resp_ready_o ( jtag_resp_ready ),
.dmi_resp_valid_i ( jtag_resp_valid ),
.dmi_rst_no ( ), // not connected
.tck_i ( jtag_TCK ),
.tms_i ( jtag_TMS ),
.trst_ni ( jtag_TRSTn ),
.td_i ( jtag_TDI ),
.td_o ( jtag_TDO_data ),
.tdo_oe_o ( jtag_TDO_driven )
);
// SiFive's SimDTM Module
// Converts to DPI calls
logic [1:0] debug_req_bits_op;
assign dmi_req.op = dm::dtm_op_e'(debug_req_bits_op);
if (InclSimDTM) begin
SimDTM i_SimDTM (
.clk ( clk_i ),
.reset ( ~rst_ni ),
.debug_req_valid ( dmi_req_valid ),
.debug_req_ready ( debug_req_ready ),
.debug_req_bits_addr ( dmi_req.addr ),
.debug_req_bits_op ( debug_req_bits_op ),
.debug_req_bits_data ( dmi_req.data ),
.debug_resp_valid ( dmi_resp_valid ),
.debug_resp_ready ( dmi_resp_ready ),
.debug_resp_bits_resp ( debug_resp.resp ),
.debug_resp_bits_data ( debug_resp.data ),
.exit ( dmi_exit )
);
end else begin
assign dmi_req_valid = '0;
assign debug_req_bits_op = '0;
assign dmi_exit = 1'b0;
end
// this delay window allows the core to read and execute init code
// from the bootrom before the first debug request can interrupt
// core. this is needed in cases where an fsbl is involved that
// expects a0 and a1 to be initialized with the hart id and a
// pointer to the dev tree, respectively.
localparam int unsigned DmiDelCycles = 500;
logic debug_req_core_ungtd;
int dmi_del_cnt_d, dmi_del_cnt_q;
assign dmi_del_cnt_d = (dmi_del_cnt_q) ? dmi_del_cnt_q - 1 : 0;
assign debug_req_core = (dmi_del_cnt_q) ? 1'b0 :
(!debug_enable) ? 1'b0 : debug_req_core_ungtd;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_dmi_del_cnt
if(!rst_ni) begin
dmi_del_cnt_q <= DmiDelCycles;
end else begin
dmi_del_cnt_q <= dmi_del_cnt_d;
end
end
ariane_axi_soc::req_t dm_axi_m_req;
ariane_axi_soc::resp_t dm_axi_m_resp;
logic dm_slave_req;
logic dm_slave_we;
logic [64-1:0] dm_slave_addr;
logic [64/8-1:0] dm_slave_be;
logic [64-1:0] dm_slave_wdata;
logic [64-1:0] dm_slave_rdata;
logic dm_master_req;
logic [64-1:0] dm_master_add;
logic dm_master_we;
logic [64-1:0] dm_master_wdata;
logic [64/8-1:0] dm_master_be;
logic dm_master_gnt;
logic dm_master_r_valid;
logic [64-1:0] dm_master_r_rdata;
// debug module
dm_top #(
.NrHarts ( 1 ),
.BusWidth ( AXI_DATA_WIDTH ),
.SelectableHarts ( 1'b1 )
) i_dm_top (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
.debug_req_o ( debug_req_core_ungtd ),
.unavailable_i ( '0 ),
.hartinfo_i ( {ariane_pkg::DebugHartInfo} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),
.slave_be_i ( dm_slave_be ),
.slave_wdata_i ( dm_slave_wdata ),
.slave_rdata_o ( dm_slave_rdata ),
.master_req_o ( dm_master_req ),
.master_add_o ( dm_master_add ),
.master_we_o ( dm_master_we ),
.master_wdata_o ( dm_master_wdata ),
.master_be_o ( dm_master_be ),
.master_gnt_i ( dm_master_gnt ),
.master_r_valid_i ( dm_master_r_valid ),
.master_r_rdata_i ( dm_master_r_rdata ),
.dmi_rst_ni ( rst_ni ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
);
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_dm_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slave ( master[ariane_soc::Debug] ),
.req_o ( dm_slave_req ),
.we_o ( dm_slave_we ),
.addr_o ( dm_slave_addr ),
.be_o ( dm_slave_be ),
.data_o ( dm_slave_wdata ),
.data_i ( dm_slave_rdata )
);
`AXI_ASSIGN_FROM_REQ(slave[1], dm_axi_m_req)
`AXI_ASSIGN_TO_RESP(dm_axi_m_resp, slave[1])
axi_adapter #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidth )
) i_dm_axi_master (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( dm_master_req ),
.type_i ( ariane_axi::SINGLE_REQ ),
.gnt_o ( dm_master_gnt ),
.gnt_id_o ( ),
.addr_i ( dm_master_add ),
.we_i ( dm_master_we ),
.wdata_i ( dm_master_wdata ),
.be_i ( dm_master_be ),
.size_i ( 2'b11 ), // always do 64bit here and use byte enables to gate
.id_i ( '0 ),
.valid_o ( dm_master_r_valid ),
.rdata_o ( dm_master_r_rdata ),
.id_o ( ),
.critical_word_o ( ),
.critical_word_valid_o ( ),
.axi_req_o ( dm_axi_m_req ),
.axi_resp_i ( dm_axi_m_resp )
);
// ---------------
// ROM
// ---------------
logic rom_req;
logic [AXI_ADDRESS_WIDTH-1:0] rom_addr;
logic [AXI_DATA_WIDTH-1:0] rom_rdata;
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_axi2rom (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slave ( master[ariane_soc::ROM] ),
.req_o ( rom_req ),
.we_o ( ),
.addr_o ( rom_addr ),
.be_o ( ),
.data_o ( ),
.data_i ( rom_rdata )
);
`ifdef DROMAJO
dromajo_bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
`else
bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
`endif
// ------------------------------
// GPIO
// ------------------------------
// GPIO not implemented, adding an error slave here
ariane_axi_soc::req_slv_t gpio_req;
ariane_axi_soc::resp_slv_t gpio_resp;
`AXI_ASSIGN_TO_REQ(gpio_req, master[ariane_soc::GPIO])
`AXI_ASSIGN_FROM_RESP(master[ariane_soc::GPIO], gpio_resp)
axi_err_slv #(
.AxiIdWidth ( ariane_soc::IdWidthSlave ),
.req_t ( ariane_axi_soc::req_slv_t ),
.resp_t ( ariane_axi_soc::resp_slv_t )
) i_gpio_err_slv (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.test_i ( test_en ),
.slv_req_i ( gpio_req ),
.slv_resp_o ( gpio_resp )
);
// ------------------------------
// Memory + Exclusive Access
// ------------------------------
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) dram();
logic req;
logic we;
logic [AXI_ADDRESS_WIDTH-1:0] addr;
logic [AXI_DATA_WIDTH/8-1:0] be;
logic [AXI_DATA_WIDTH-1:0] wdata;
logic [AXI_DATA_WIDTH-1:0] rdata;
axi_riscv_atomics_wrap #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
) i_axi_riscv_atomics (
.clk_i,
.rst_ni ( ndmreset_n ),
.slv ( master[ariane_soc::DRAM] ),
.mst ( dram )
);
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) dram_delayed();
axi_delayer_intf #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.STALL_RANDOM_INPUT ( StallRandomInput ),
.STALL_RANDOM_OUTPUT ( StallRandomOutput ),
.FIXED_DELAY_INPUT ( 0 ),
.FIXED_DELAY_OUTPUT ( 0 )
) i_axi_delayer (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slv ( dram ),
.mst ( dram_delayed )
);
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slave ( dram_delayed ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),
.be_o ( be ),
.data_o ( wdata ),
.data_i ( rdata )
);
sram #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
`ifdef DROMAJO
.DROMAJO_RAM (1),
`endif
.NUM_WORDS ( NUM_WORDS )
) i_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req ),
.we_i ( we ),
.addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ),
.wdata_i ( wdata ),
.be_i ( be ),
.rdata_o ( rdata )
);
// ---------------
// AXI Xbar
// ---------------
axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS-1:0] addr_map;
assign addr_map = '{
'{ idx: ariane_soc::Debug, start_addr: ariane_soc::DebugBase, end_addr: ariane_soc::DebugBase + ariane_soc::DebugLength },
'{ idx: ariane_soc::ROM, start_addr: ariane_soc::ROMBase, end_addr: ariane_soc::ROMBase + ariane_soc::ROMLength },
'{ idx: ariane_soc::CLINT, start_addr: ariane_soc::CLINTBase, end_addr: ariane_soc::CLINTBase + ariane_soc::CLINTLength },
'{ idx: ariane_soc::PLIC, start_addr: ariane_soc::PLICBase, end_addr: ariane_soc::PLICBase + ariane_soc::PLICLength },
'{ idx: ariane_soc::UART, start_addr: ariane_soc::UARTBase, end_addr: ariane_soc::UARTBase + ariane_soc::UARTLength },
'{ idx: ariane_soc::Timer, start_addr: ariane_soc::TimerBase, end_addr: ariane_soc::TimerBase + ariane_soc::TimerLength },
'{ idx: ariane_soc::SPI, start_addr: ariane_soc::SPIBase, end_addr: ariane_soc::SPIBase + ariane_soc::SPILength },
'{ idx: ariane_soc::Ethernet, start_addr: ariane_soc::EthernetBase, end_addr: ariane_soc::EthernetBase + ariane_soc::EthernetLength },
'{ idx: ariane_soc::GPIO, start_addr: ariane_soc::GPIOBase, end_addr: ariane_soc::GPIOBase + ariane_soc::GPIOLength },
'{ idx: ariane_soc::DMA, start_addr: ariane_soc::DMABase, end_addr: ariane_soc::DMABase + ariane_soc::DMALength },
'{ idx: ariane_soc::AES, start_addr: ariane_soc::AESBase, end_addr: ariane_soc::AESBase + ariane_soc::AESLength },
'{ idx: ariane_soc::eFPGA, start_addr: ariane_soc::eFPGABase, end_addr: ariane_soc::eFPGABase + ariane_soc::eFPGALength },
'{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength }
};
localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
NoSlvPorts: ariane_soc::NrSlaves,
NoMstPorts: ariane_soc::NB_PERIPHERALS,
MaxMstTrans: 1, // Probably requires update
MaxSlvTrans: 1, // Probably requires update
FallThrough: 1'b0,
LatencyMode: axi_pkg::NO_LATENCY,
AxiIdWidthSlvPorts: ariane_soc::IdWidth,
AxiIdUsedSlvPorts: ariane_soc::IdWidth,
UniqueIds: 1'b0,
AxiAddrWidth: AXI_ADDRESS_WIDTH,
AxiDataWidth: AXI_DATA_WIDTH,
NoAddrRules: ariane_soc::NB_PERIPHERALS
};
axi_xbar_intf #(
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.Cfg ( AXI_XBAR_CFG ),
.rule_t ( axi_pkg::xbar_rule_64_t )
) i_axi_xbar (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.test_i ( test_en ),
.slv_ports ( slave ),
.mst_ports ( master ),
.addr_map_i ( addr_map ),
.en_default_mst_port_i ( '0 ),
.default_mst_port_i ( '0 )
);
//----------------
// AES : mash
//----------------
AXI_LITE #(
.AXI_ADDR_WIDTH (32),
.AXI_DATA_WIDTH (32)
) aes_lite();
axi_to_axi_lite_mod axi_to_axi_lite_aes (
.clk_i (clk_i),
.rst_ni (ndmreset_n),
.testmode_i (test_en),
.in (master[ariane_soc::AES]),
.out (aes_lite)
);
AES_PIPE_v1_0_S00_AXI aes (
.S_AXI_ACLK (clk_i ),
.S_AXI_ARESETN (ndmreset_n ),
.S_AXI_AWADDR (aes_lite.aw_addr ),
.S_AXI_AWPROT ( ),
.S_AXI_AWVALID (aes_lite.aw_valid ),
.S_AXI_AWREADY (aes_lite.aw_ready ),
.S_AXI_WDATA (aes_lite.w_data ),
.S_AXI_WSTRB (aes_lite.w_strb ),
.S_AXI_WVALID (aes_lite.w_valid ),
.S_AXI_WREADY (aes_lite.w_ready ),
.S_AXI_BRESP (aes_lite.b_resp ),
.S_AXI_BVALID (aes_lite.b_valid ),
.S_AXI_BREADY (aes_lite.b_ready ),
.S_AXI_ARADDR (aes_lite.ar_addr ),
.S_AXI_ARPROT ( ),
.S_AXI_ARVALID (aes_lite.ar_valid ),
.S_AXI_ARREADY (aes_lite.ar_ready ),
.S_AXI_RDATA (aes_lite.r_data ),
.S_AXI_RRESP (aes_lite.r_resp ),
.S_AXI_RVALID (aes_lite.r_valid ),
.S_AXI_RREADY (aes_lite.r_ready )
);
//----------------
// DMA : mash
//----------------
logic dma_penable;
logic dma_pwrite;
logic [31:0] dma_paddr;
logic dma_psel;
logic [31:0] dma_pwdata;
logic [31:0] dma_prdata;
logic dma_pready;
logic dma_pslverr;
axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI4_RDATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI4_WDATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI4_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI4_USER_WIDTH ( AXI_USER_WIDTH ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32_dma (
.ACLK ( clk_i ),
.ARESETn ( ndmreset_n ),
.test_en_i ( 1'b0 ),
.AWID_i ( master[ariane_soc::DMA].aw_id ),
.AWADDR_i ( master[ariane_soc::DMA].aw_addr ),
.AWLEN_i ( master[ariane_soc::DMA].aw_len ),
.AWSIZE_i ( master[ariane_soc::DMA].aw_size ),
.AWBURST_i ( master[ariane_soc::DMA].aw_burst ),
.AWLOCK_i ( master[ariane_soc::DMA].aw_lock ),
.AWCACHE_i ( master[ariane_soc::DMA].aw_cache ),
.AWPROT_i ( master[ariane_soc::DMA].aw_prot ),
.AWREGION_i( master[ariane_soc::DMA].aw_region ),
.AWUSER_i ( master[ariane_soc::DMA].aw_user ),
.AWQOS_i ( master[ariane_soc::DMA].aw_qos ),
.AWVALID_i ( master[ariane_soc::DMA].aw_valid ),
.AWREADY_o ( master[ariane_soc::DMA].aw_ready ),
.WDATA_i ( master[ariane_soc::DMA].w_data ),
.WSTRB_i ( master[ariane_soc::DMA].w_strb ),
.WLAST_i ( master[ariane_soc::DMA].w_last ),
.WUSER_i ( master[ariane_soc::DMA].w_user ),
.WVALID_i ( master[ariane_soc::DMA].w_valid ),
.WREADY_o ( master[ariane_soc::DMA].w_ready ),
.BID_o ( master[ariane_soc::DMA].b_id ),
.BRESP_o ( master[ariane_soc::DMA].b_resp ),
.BVALID_o ( master[ariane_soc::DMA].b_valid ),
.BUSER_o ( master[ariane_soc::DMA].b_user ),
.BREADY_i ( master[ariane_soc::DMA].b_ready ),
.ARID_i ( master[ariane_soc::DMA].ar_id ),
.ARADDR_i ( master[ariane_soc::DMA].ar_addr ),
.ARLEN_i ( master[ariane_soc::DMA].ar_len ),
.ARSIZE_i ( master[ariane_soc::DMA].ar_size ),
.ARBURST_i ( master[ariane_soc::DMA].ar_burst ),
.ARLOCK_i ( master[ariane_soc::DMA].ar_lock ),
.ARCACHE_i ( master[ariane_soc::DMA].ar_cache ),
.ARPROT_i ( master[ariane_soc::DMA].ar_prot ),
.ARREGION_i( master[ariane_soc::DMA].ar_region ),
.ARUSER_i ( master[ariane_soc::DMA].ar_user ),
.ARQOS_i ( master[ariane_soc::DMA].ar_qos ),
.ARVALID_i ( master[ariane_soc::DMA].ar_valid ),
.ARREADY_o ( master[ariane_soc::DMA].ar_ready ),
.RID_o ( master[ariane_soc::DMA].r_id ),
.RDATA_o ( master[ariane_soc::DMA].r_data ),
.RRESP_o ( master[ariane_soc::DMA].r_resp ),
.RLAST_o ( master[ariane_soc::DMA].r_last ),
.RUSER_o ( master[ariane_soc::DMA].r_user ),
.RVALID_o ( master[ariane_soc::DMA].r_valid ),
.RREADY_i ( master[ariane_soc::DMA].r_ready ),
.PENABLE ( dma_penable ),
.PWRITE ( dma_pwrite ),
.PADDR ( dma_paddr ),
.PSEL ( dma_psel ),
.PWDATA ( dma_pwdata ),
.PRDATA ( dma_prdata ),
.PREADY ( dma_pready ),
.PSLVERR ( dma_pslverr )
);
dma_axi64 dma (
.clk ( clk_i ),
.reset ( ~ndmreset_n ),
.scan_en ( 1'b0 ),
.idle ( ),
.INT ( ),
.periph_tx_req ( ),
.periph_tx_clr ( ),
.periph_rx_req ( ),
.periph_rx_clr ( ),
.pclken ( 1'b1 ),
.psel ( dma_psel ),
.penable ( ~dma_penable ),
.paddr ( dma_paddr ),
.pwrite ( dma_pwrite ),
.pwdata ( dma_pwdata ),
.prdata ( dma_prdata ),
.pslverr ( dma_pslverr ),
.pready ( dma_pready ),
.AWID0 ( slave[2].aw_id ),
.AWADDR0 ( slave[2].aw_addr ),
.AWLEN0 ( slave[2].aw_len ),
.AWSIZE0 ( slave[2].aw_size ),
.AWVALID0 ( slave[2].aw_valid ),
.AWREADY0 ( slave[2].aw_ready ),
.WID0 ( ),
.WDATA0 ( slave[2].w_data ),
.WSTRB0 ( slave[2].w_strb ),
.WLAST0 ( slave[2].w_last ),
.WVALID0 ( slave[2].w_valid ),
.WREADY0 ( slave[2].w_ready ),
.BID0 ( slave[2].b_id ),
.BRESP0 ( slave[2].b_resp ),
.BVALID0 ( slave[2].b_valid ),
.BREADY0 ( slave[2].b_ready ),
.ARID0 ( slave[2].ar_id ),
.ARADDR0 ( slave[2].ar_addr ),
.ARLEN0 ( slave[2].ar_len ),
.ARSIZE0 ( slave[2].ar_size ),
.ARVALID0 ( slave[2].ar_valid ),
.ARREADY0 ( slave[2].ar_ready ),
.RID0 ( slave[2].r_id ),
.RDATA0 ( slave[2].r_data ),
.RRESP0 ( slave[2].r_resp ),
.RLAST0 ( slave[2].r_last ),
.RVALID0 ( slave[2].r_valid ),
.RREADY0 ( slave[2].r_ready )
);
//----------------
// eFPGA : mash
//----------------
//wrapper_efpga efpga (
// .clk (clk_i)
//);
AXI_LITE #(
.AXI_ADDR_WIDTH (32),
.AXI_DATA_WIDTH (32)
) aes_lite_efpga();
axi_to_axi_lite_mod axi_to_axi_lite_efpga (
.clk_i (clk_i),
.rst_ni (ndmreset_n),
.testmode_i (test_en),
.in (master[ariane_soc::eFPGA]),
.out (aes_lite_efpga)
);
efpga_ip_v1_0_S00_AXI eFPGA (
.S_AXI_ACLK (clk_i ),
.S_AXI_ARESETN (ndmreset_n ),
.S_AXI_AWADDR (aes_lite_efpga.aw_addr ),
.S_AXI_AWPROT ( ),
.S_AXI_AWVALID (aes_lite_efpga.aw_valid ),
.S_AXI_AWREADY (aes_lite_efpga.aw_ready ),
.S_AXI_WDATA (aes_lite_efpga.w_data ),
.S_AXI_WSTRB (aes_lite_efpga.w_strb ),
.S_AXI_WVALID (aes_lite_efpga.w_valid ),
.S_AXI_WREADY (aes_lite_efpga.w_ready ),
.S_AXI_BRESP (aes_lite_efpga.b_resp ),
.S_AXI_BVALID (aes_lite_efpga.b_valid ),
.S_AXI_BREADY (aes_lite_efpga.b_ready ),
.S_AXI_ARADDR (aes_lite_efpga.ar_addr ),
.S_AXI_ARPROT ( ),
.S_AXI_ARVALID (aes_lite_efpga.ar_valid ),
.S_AXI_ARREADY (aes_lite_efpga.ar_ready ),
.S_AXI_RDATA (aes_lite_efpga.r_data ),
.S_AXI_RRESP (aes_lite_efpga.r_resp ),
.S_AXI_RVALID (aes_lite_efpga.r_valid ),
.S_AXI_RREADY (aes_lite_efpga.r_ready )
);
// ---------------
// CLINT
// ---------------
logic ipi;
logic timer_irq;
ariane_axi_soc::req_slv_t axi_clint_req;
ariane_axi_soc::resp_slv_t axi_clint_resp;
clint #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.NR_CORES ( 1 ),
.axi_req_t ( ariane_axi_soc::req_slv_t ),
.axi_resp_t ( ariane_axi_soc::resp_slv_t )
) i_clint (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.testmode_i ( test_en ),
.axi_req_i ( axi_clint_req ),
.axi_resp_o ( axi_clint_resp ),
.rtc_i ( rtc_i ),
.timer_irq_o ( timer_irq ),
.ipi_o ( ipi )
);
`AXI_ASSIGN_TO_REQ(axi_clint_req, master[ariane_soc::CLINT])
`AXI_ASSIGN_FROM_RESP(master[ariane_soc::CLINT], axi_clint_resp)
// ---------------
// Peripherals
// ---------------
logic tx, rx;
logic [1:0] irqs;
ariane_peripherals #(
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.AxiIdWidth ( ariane_soc::IdWidthSlave ),
`ifndef VERILATOR
// disable UART when using Spike, as we need to rely on the mockuart
`ifdef SPIKE_TANDEM
.InclUART ( 1'b0 ),
`else
.InclUART ( 1'b1 ),
`endif
`else
.InclUART ( 1'b0 ),
`endif
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
) i_ariane_peripherals (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.ethernet ( master[ariane_soc::Ethernet] ),
.timer ( master[ariane_soc::Timer] ),
.irq_o ( irqs ),
.rx_i ( rx ),
.tx_o ( tx ),
.eth_txck ( ),
.eth_rxck ( ),
.eth_rxctl ( ),
.eth_rxd ( ),
.eth_rst_n ( ),
.eth_tx_en ( ),
.eth_txd ( ),
.phy_mdio ( ),
.eth_mdc ( ),
.mdio ( ),
.mdc ( ),
.spi_clk_o ( ),
.spi_mosi ( ),
.spi_miso ( ),
.spi_ss ( )
);
uart_bus #(.BAUD_RATE(115200), .PARITY_EN(0)) i_uart_bus (.rx(tx), .tx(rx), .rx_en(1'b1));
// ---------------
// Core
// ---------------
ariane_axi_soc::req_t axi_ariane_req;
ariane_axi_soc::resp_t axi_ariane_resp;
ariane_rvfi_pkg::rvfi_port_t rvfi;
ariane #(
.ArianeCfg ( ariane_soc::ArianeSocCfg )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM
.hart_id_i ( {56'h0, hart_id} ),
.irq_i ( irqs ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
`ifdef RVFI_TRACE
.rvfi_o ( rvfi ),
`endif
// Disable Debug when simulating with Spike
`ifdef SPIKE_TANDEM
.debug_req_i ( 1'b0 ),
`else
.debug_req_i ( debug_req_core ),
`endif
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
);
`AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req)
`AXI_ASSIGN_TO_RESP(axi_ariane_resp, slave[0])
// -------------
// Simulation Helper Functions
// -------------
// check for response errors
always_ff @(posedge clk_i) begin : p_assert
if (axi_ariane_req.r_ready &&
axi_ariane_resp.r_valid &&
axi_ariane_resp.r.resp inside {axi_pkg::RESP_DECERR, axi_pkg::RESP_SLVERR}) begin
$warning("R Response Errored");
end
if (axi_ariane_req.b_ready &&
axi_ariane_resp.b_valid &&
axi_ariane_resp.b.resp inside {axi_pkg::RESP_DECERR, axi_pkg::RESP_SLVERR}) begin
$warning("B Response Errored");
end
end
rvfi_tracer #(
.HART_ID(hart_id),
.DEBUG_START(0),
.DEBUG_STOP(0)
) rvfi_tracer_i (
.clk_i(clk_i),
.rst_ni(rst_ni),
.rvfi_i(rvfi)
);
`ifdef AXI_SVA
// AXI 4 Assertion IP integration - You will need to get your own copy of this IP if you want
// to use it
Axi4PC #(
.DATA_WIDTH(ariane_axi_soc::DataWidth),
.WID_WIDTH(ariane_soc::IdWidthSlave),
.RID_WIDTH(ariane_soc::IdWidthSlave),
.AWUSER_WIDTH(ariane_axi_soc::UserWidth),
.WUSER_WIDTH(ariane_axi_soc::UserWidth),
.BUSER_WIDTH(ariane_axi_soc::UserWidth),
.ARUSER_WIDTH(ariane_axi_soc::UserWidth),
.RUSER_WIDTH(ariane_axi_soc::UserWidth),
.ADDR_WIDTH(ariane_axi_soc::AddrWidth)
) i_Axi4PC (
.ACLK(clk_i),
.ARESETn(ndmreset_n),
.AWID(dram.aw_id),
.AWADDR(dram.aw_addr),
.AWLEN(dram.aw_len),
.AWSIZE(dram.aw_size),
.AWBURST(dram.aw_burst),
.AWLOCK(dram.aw_lock),
.AWCACHE(dram.aw_cache),
.AWPROT(dram.aw_prot),
.AWQOS(dram.aw_qos),
.AWREGION(dram.aw_region),
.AWUSER(dram.aw_user),
.AWVALID(dram.aw_valid),
.AWREADY(dram.aw_ready),
.WLAST(dram.w_last),
.WDATA(dram.w_data),
.WSTRB(dram.w_strb),
.WUSER(dram.w_user),
.WVALID(dram.w_valid),
.WREADY(dram.w_ready),
.BID(dram.b_id),
.BRESP(dram.b_resp),
.BUSER(dram.b_user),
.BVALID(dram.b_valid),
.BREADY(dram.b_ready),
.ARID(dram.ar_id),
.ARADDR(dram.ar_addr),
.ARLEN(dram.ar_len),
.ARSIZE(dram.ar_size),
.ARBURST(dram.ar_burst),
.ARLOCK(dram.ar_lock),
.ARCACHE(dram.ar_cache),
.ARPROT(dram.ar_prot),
.ARQOS(dram.ar_qos),
.ARREGION(dram.ar_region),
.ARUSER(dram.ar_user),
.ARVALID(dram.ar_valid),
.ARREADY(dram.ar_ready),
.RID(dram.r_id),
.RLAST(dram.r_last),
.RDATA(dram.r_data),
.RRESP(dram.r_resp),
.RUSER(dram.r_user),
.RVALID(dram.r_valid),
.RREADY(dram.r_ready),
.CACTIVE('0),
.CSYSREQ('0),
.CSYSACK('0)
);
`endif
endmodule
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Date: 19.03.2017
// Description: Test-harness for Ariane
// Instantiates an AXI-Bus and memories
module ariane_testharness #(
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
`ifdef DROMAJO
parameter bit InclSimDTM = 1'b0,
`else
parameter bit InclSimDTM = 1'b1,
`endif
parameter int unsigned NUM_WORDS = 2**25, // memory size
parameter bit StallRandomOutput = 1'b0,
parameter bit StallRandomInput = 1'b0
) (
input logic clk_i,
input logic rtc_i,
input logic rst_ni,
output logic [31:0] exit_o
);
localparam [7:0] hart_id = '0;
// disable test-enable
logic test_en;
logic ndmreset;
logic ndmreset_n;
logic debug_req_core;
int jtag_enable;
logic init_done;
logic [31:0] jtag_exit, dmi_exit;
logic jtag_TCK;
logic jtag_TMS;
logic jtag_TDI;
logic jtag_TRSTn;
logic jtag_TDO_data;
logic jtag_TDO_driven;
logic debug_req_valid;
logic debug_req_ready;
logic debug_resp_valid;
logic debug_resp_ready;
logic jtag_req_valid;
logic [6:0] jtag_req_bits_addr;
logic [1:0] jtag_req_bits_op;
logic [31:0] jtag_req_bits_data;
logic jtag_resp_ready;
logic jtag_resp_valid;
logic dmi_req_valid;
logic dmi_resp_ready;
logic dmi_resp_valid;
dm::dmi_req_t jtag_dmi_req;
dm::dmi_req_t dmi_req;
dm::dmi_req_t debug_req;
dm::dmi_resp_t debug_resp;
assign test_en = 1'b0;
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidth ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) slave[ariane_soc::NrSlaves-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) master[ariane_soc::NB_PERIPHERALS-1:0]();
rstgen i_rstgen_main (
.clk_i ( clk_i ),
.rst_ni ( rst_ni & (~ndmreset) ),
.test_mode_i ( test_en ),
.rst_no ( ndmreset_n ),
.init_no ( ) // keep open
);
// ---------------
// Debug
// ---------------
assign init_done = rst_ni;
logic debug_enable;
initial begin
if (!$value$plusargs("jtag_rbb_enable=%b", jtag_enable)) jtag_enable = 'h0;
if ($test$plusargs("debug_disable")) debug_enable = 'h0; else debug_enable = 'h1;
if (riscv::XLEN != 32 & riscv::XLEN != 64) $error("XLEN different from 32 and 64");
end
// debug if MUX
assign debug_req_valid = (jtag_enable[0]) ? jtag_req_valid : dmi_req_valid;
assign debug_resp_ready = (jtag_enable[0]) ? jtag_resp_ready : dmi_resp_ready;
assign debug_req = (jtag_enable[0]) ? jtag_dmi_req : dmi_req;
assign exit_o = (jtag_enable[0]) ? jtag_exit : dmi_exit;
assign jtag_resp_valid = (jtag_enable[0]) ? debug_resp_valid : 1'b0;
assign dmi_resp_valid = (jtag_enable[0]) ? 1'b0 : debug_resp_valid;
// SiFive's SimJTAG Module
// Converts to DPI calls
SimJTAG i_SimJTAG (
.clock ( clk_i ),
.reset ( ~rst_ni ),
.enable ( jtag_enable[0] ),
.init_done ( init_done ),
.jtag_TCK ( jtag_TCK ),
.jtag_TMS ( jtag_TMS ),
.jtag_TDI ( jtag_TDI ),
.jtag_TRSTn ( jtag_TRSTn ),
.jtag_TDO_data ( jtag_TDO_data ),
.jtag_TDO_driven ( jtag_TDO_driven ),
.exit ( jtag_exit )
);
dmi_jtag i_dmi_jtag (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( test_en ),
.dmi_req_o ( jtag_dmi_req ),
.dmi_req_valid_o ( jtag_req_valid ),
.dmi_req_ready_i ( debug_req_ready ),
.dmi_resp_i ( debug_resp ),
.dmi_resp_ready_o ( jtag_resp_ready ),
.dmi_resp_valid_i ( jtag_resp_valid ),
.dmi_rst_no ( ), // not connected
.tck_i ( jtag_TCK ),
.tms_i ( jtag_TMS ),
.trst_ni ( jtag_TRSTn ),
.td_i ( jtag_TDI ),
.td_o ( jtag_TDO_data ),
.tdo_oe_o ( jtag_TDO_driven )
);
// SiFive's SimDTM Module
// Converts to DPI calls
logic [1:0] debug_req_bits_op;
assign dmi_req.op = dm::dtm_op_e'(debug_req_bits_op);
if (InclSimDTM) begin
SimDTM i_SimDTM (
.clk ( clk_i ),
.reset ( ~rst_ni ),
.debug_req_valid ( dmi_req_valid ),
.debug_req_ready ( debug_req_ready ),
.debug_req_bits_addr ( dmi_req.addr ),
.debug_req_bits_op ( debug_req_bits_op ),
.debug_req_bits_data ( dmi_req.data ),
.debug_resp_valid ( dmi_resp_valid ),
.debug_resp_ready ( dmi_resp_ready ),
.debug_resp_bits_resp ( debug_resp.resp ),
.debug_resp_bits_data ( debug_resp.data ),
.exit ( dmi_exit )
);
end else begin
assign dmi_req_valid = '0;
assign debug_req_bits_op = '0;
assign dmi_exit = 1'b0;
end
// this delay window allows the core to read and execute init code
// from the bootrom before the first debug request can interrupt
// core. this is needed in cases where an fsbl is involved that
// expects a0 and a1 to be initialized with the hart id and a
// pointer to the dev tree, respectively.
localparam int unsigned DmiDelCycles = 500;
logic debug_req_core_ungtd;
int dmi_del_cnt_d, dmi_del_cnt_q;
assign dmi_del_cnt_d = (dmi_del_cnt_q) ? dmi_del_cnt_q - 1 : 0;
assign debug_req_core = (dmi_del_cnt_q) ? 1'b0 :
(!debug_enable) ? 1'b0 : debug_req_core_ungtd;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_dmi_del_cnt
if(!rst_ni) begin
dmi_del_cnt_q <= DmiDelCycles;
end else begin
dmi_del_cnt_q <= dmi_del_cnt_d;
end
end
ariane_axi_soc::req_t dm_axi_m_req;
ariane_axi_soc::resp_t dm_axi_m_resp;
logic dm_slave_req;
logic dm_slave_we;
logic [64-1:0] dm_slave_addr;
logic [64/8-1:0] dm_slave_be;
logic [64-1:0] dm_slave_wdata;
logic [64-1:0] dm_slave_rdata;
logic dm_master_req;
logic [64-1:0] dm_master_add;
logic dm_master_we;
logic [64-1:0] dm_master_wdata;
logic [64/8-1:0] dm_master_be;
logic dm_master_gnt;
logic dm_master_r_valid;
logic [64-1:0] dm_master_r_rdata;
// debug module
dm_top #(
.NrHarts ( 1 ),
.BusWidth ( AXI_DATA_WIDTH ),
.SelectableHarts ( 1'b1 )
) i_dm_top (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
.debug_req_o ( debug_req_core_ungtd ),
.unavailable_i ( '0 ),
.hartinfo_i ( {ariane_pkg::DebugHartInfo} ),
.slave_req_i ( dm_slave_req ),
.slave_we_i ( dm_slave_we ),
.slave_addr_i ( dm_slave_addr ),
.slave_be_i ( dm_slave_be ),
.slave_wdata_i ( dm_slave_wdata ),
.slave_rdata_o ( dm_slave_rdata ),
.master_req_o ( dm_master_req ),
.master_add_o ( dm_master_add ),
.master_we_o ( dm_master_we ),
.master_wdata_o ( dm_master_wdata ),
.master_be_o ( dm_master_be ),
.master_gnt_i ( dm_master_gnt ),
.master_r_valid_i ( dm_master_r_valid ),
.master_r_rdata_i ( dm_master_r_rdata ),
.dmi_rst_ni ( rst_ni ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
);
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_dm_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slave ( master[ariane_soc::Debug] ),
.req_o ( dm_slave_req ),
.we_o ( dm_slave_we ),
.addr_o ( dm_slave_addr ),
.be_o ( dm_slave_be ),
.data_o ( dm_slave_wdata ),
.data_i ( dm_slave_rdata )
);
axi_master_connect i_dm_axi_master_connect (
.axi_req_i(dm_axi_m_req),
.axi_resp_o(dm_axi_m_resp),
.master(slave[1])
);
axi_adapter #(
.DATA_WIDTH ( AXI_DATA_WIDTH )
) i_dm_axi_master (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( dm_master_req ),
.type_i ( ariane_axi::SINGLE_REQ ),
.gnt_o ( dm_master_gnt ),
.gnt_id_o ( ),
.addr_i ( dm_master_add ),
.we_i ( dm_master_we ),
.wdata_i ( dm_master_wdata ),
.be_i ( dm_master_be ),
.size_i ( 2'b11 ), // always do 64bit here and use byte enables to gate
.id_i ( '0 ),
.valid_o ( dm_master_r_valid ),
.rdata_o ( dm_master_r_rdata ),
.id_o ( ),
.critical_word_o ( ),
.critical_word_valid_o ( ),
.axi_req_o ( dm_axi_m_req ),
.axi_resp_i ( dm_axi_m_resp )
);
// ---------------
// ROM
// ---------------
logic rom_req;
logic [AXI_ADDRESS_WIDTH-1:0] rom_addr;
logic [AXI_DATA_WIDTH-1:0] rom_rdata;
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_axi2rom (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slave ( master[ariane_soc::ROM] ),
.req_o ( rom_req ),
.we_o ( ),
.addr_o ( rom_addr ),
.be_o ( ),
.data_o ( ),
.data_i ( rom_rdata )
);
`ifdef DROMAJO
dromajo_bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
`else
bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
`endif
// ------------------------------
// Memory + Exclusive Access
// ------------------------------
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) dram();
logic req;
logic we;
logic [AXI_ADDRESS_WIDTH-1:0] addr;
logic [AXI_DATA_WIDTH/8-1:0] be;
logic [AXI_DATA_WIDTH-1:0] wdata;
logic [AXI_DATA_WIDTH-1:0] rdata;
axi_riscv_atomics_wrap #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
) i_axi_riscv_atomics (
.clk_i,
.rst_ni ( ndmreset_n ),
.slv ( master[ariane_soc::DRAM] ),
.mst ( dram )
);
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) dram_delayed();
ariane_axi_soc::aw_chan_slv_t aw_chan_i;
ariane_axi_soc::w_chan_t w_chan_i;
ariane_axi_soc::b_chan_slv_t b_chan_o;
ariane_axi_soc::ar_chan_slv_t ar_chan_i;
ariane_axi_soc::r_chan_slv_t r_chan_o;
ariane_axi_soc::aw_chan_slv_t aw_chan_o;
ariane_axi_soc::w_chan_t w_chan_o;
ariane_axi_soc::b_chan_slv_t b_chan_i;
ariane_axi_soc::ar_chan_slv_t ar_chan_o;
ariane_axi_soc::r_chan_slv_t r_chan_i;
axi_delayer #(
.aw_t ( ariane_axi_soc::aw_chan_slv_t ),
.w_t ( ariane_axi_soc::w_chan_t ),
.b_t ( ariane_axi_soc::b_chan_slv_t ),
.ar_t ( ariane_axi_soc::ar_chan_slv_t ),
.r_t ( ariane_axi_soc::r_chan_slv_t ),
.StallRandomOutput ( StallRandomOutput ),
.StallRandomInput ( StallRandomInput ),
.FixedDelayInput ( 0 ),
.FixedDelayOutput ( 0 )
) i_axi_delayer (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.aw_valid_i ( dram.aw_valid ),
.aw_chan_i ( aw_chan_i ),
.aw_ready_o ( dram.aw_ready ),
.w_valid_i ( dram.w_valid ),
.w_chan_i ( w_chan_i ),
.w_ready_o ( dram.w_ready ),
.b_valid_o ( dram.b_valid ),
.b_chan_o ( b_chan_o ),
.b_ready_i ( dram.b_ready ),
.ar_valid_i ( dram.ar_valid ),
.ar_chan_i ( ar_chan_i ),
.ar_ready_o ( dram.ar_ready ),
.r_valid_o ( dram.r_valid ),
.r_chan_o ( r_chan_o ),
.r_ready_i ( dram.r_ready ),
.aw_valid_o ( dram_delayed.aw_valid ),
.aw_chan_o ( aw_chan_o ),
.aw_ready_i ( dram_delayed.aw_ready ),
.w_valid_o ( dram_delayed.w_valid ),
.w_chan_o ( w_chan_o ),
.w_ready_i ( dram_delayed.w_ready ),
.b_valid_i ( dram_delayed.b_valid ),
.b_chan_i ( b_chan_i ),
.b_ready_o ( dram_delayed.b_ready ),
.ar_valid_o ( dram_delayed.ar_valid ),
.ar_chan_o ( ar_chan_o ),
.ar_ready_i ( dram_delayed.ar_ready ),
.r_valid_i ( dram_delayed.r_valid ),
.r_chan_i ( r_chan_i ),
.r_ready_o ( dram_delayed.r_ready )
);
assign aw_chan_i.atop = dram.aw_atop;
assign aw_chan_i.id = dram.aw_id;
assign aw_chan_i.addr = dram.aw_addr;
assign aw_chan_i.len = dram.aw_len;
assign aw_chan_i.size = dram.aw_size;
assign aw_chan_i.burst = dram.aw_burst;
assign aw_chan_i.lock = dram.aw_lock;
assign aw_chan_i.cache = dram.aw_cache;
assign aw_chan_i.prot = dram.aw_prot;
assign aw_chan_i.qos = dram.aw_qos;
assign aw_chan_i.region = dram.aw_region;
assign ar_chan_i.id = dram.ar_id;
assign ar_chan_i.addr = dram.ar_addr;
assign ar_chan_i.len = dram.ar_len;
assign ar_chan_i.size = dram.ar_size;
assign ar_chan_i.burst = dram.ar_burst;
assign ar_chan_i.lock = dram.ar_lock;
assign ar_chan_i.cache = dram.ar_cache;
assign ar_chan_i.prot = dram.ar_prot;
assign ar_chan_i.qos = dram.ar_qos;
assign ar_chan_i.region = dram.ar_region;
assign w_chan_i.data = dram.w_data;
assign w_chan_i.strb = dram.w_strb;
assign w_chan_i.last = dram.w_last;
assign dram.r_id = r_chan_o.id;
assign dram.r_data = r_chan_o.data;
assign dram.r_resp = r_chan_o.resp;
assign dram.r_last = r_chan_o.last;
assign dram.b_id = b_chan_o.id;
assign dram.b_resp = b_chan_o.resp;
assign dram_delayed.aw_id = aw_chan_o.id;
assign dram_delayed.aw_addr = aw_chan_o.addr;
assign dram_delayed.aw_len = aw_chan_o.len;
assign dram_delayed.aw_size = aw_chan_o.size;
assign dram_delayed.aw_burst = aw_chan_o.burst;
assign dram_delayed.aw_lock = aw_chan_o.lock;
assign dram_delayed.aw_cache = aw_chan_o.cache;
assign dram_delayed.aw_prot = aw_chan_o.prot;
assign dram_delayed.aw_qos = aw_chan_o.qos;
assign dram_delayed.aw_atop = aw_chan_o.atop;
assign dram_delayed.aw_region = aw_chan_o.region;
assign dram_delayed.aw_user = '0;
assign dram_delayed.ar_id = ar_chan_o.id;
assign dram_delayed.ar_addr = ar_chan_o.addr;
assign dram_delayed.ar_len = ar_chan_o.len;
assign dram_delayed.ar_size = ar_chan_o.size;
assign dram_delayed.ar_burst = ar_chan_o.burst;
assign dram_delayed.ar_lock = ar_chan_o.lock;
assign dram_delayed.ar_cache = ar_chan_o.cache;
assign dram_delayed.ar_prot = ar_chan_o.prot;
assign dram_delayed.ar_qos = ar_chan_o.qos;
assign dram_delayed.ar_region = ar_chan_o.region;
assign dram_delayed.ar_user = '0;
assign dram_delayed.w_data = w_chan_o.data;
assign dram_delayed.w_strb = w_chan_o.strb;
assign dram_delayed.w_last = w_chan_o.last;
assign dram_delayed.w_user = '0;
assign r_chan_i.id = dram_delayed.r_id;
assign r_chan_i.data = dram_delayed.r_data;
assign r_chan_i.resp = dram_delayed.r_resp;
assign r_chan_i.last = dram_delayed.r_last;
assign dram.r_user = '0;
assign b_chan_i.id = dram_delayed.b_id;
assign b_chan_i.resp = dram_delayed.b_resp;
assign dram.b_user = '0;
axi2mem #(
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) i_axi2mem (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.slave ( dram_delayed ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),
.be_o ( be ),
.data_o ( wdata ),
.data_i ( rdata )
);
sram #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
`ifdef DROMAJO
.DROMAJO_RAM (1),
`endif
.NUM_WORDS ( NUM_WORDS )
) i_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req ),
.we_i ( we ),
.addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ),
.wdata_i ( wdata ),
.be_i ( be ),
.rdata_o ( rdata )
);
// ---------------
// AXI Xbar
// ---------------
typedef logic [ariane_soc::NrRegion-1:0][ariane_soc::NB_PERIPHERALS-1:0][AXI_ADDRESS_WIDTH-1:0] addr_map_t;
axi_node_intf_wrap #(
.NB_SLAVE ( ariane_soc::NrSlaves ),
.NB_MASTER ( ariane_soc::NB_PERIPHERALS ),
.NB_REGION ( ariane_soc::NrRegion ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidth )
// .MASTER_SLICE_DEPTH ( 0 ),
// .SLAVE_SLICE_DEPTH ( 0 )
) i_axi_xbar (
.clk ( clk_i ),
.rst_n ( ndmreset_n ),
.test_en_i ( test_en ),
.slave ( slave ),
.master ( master ),
.start_addr_i ({
ariane_soc::DebugBase,
ariane_soc::ROMBase,
ariane_soc::CLINTBase,
ariane_soc::PLICBase,
ariane_soc::UARTBase,
ariane_soc::TimerBase,
ariane_soc::SPIBase,
ariane_soc::EthernetBase,
ariane_soc::GPIOBase,
ariane_soc::DMABase,
ariane_soc::AESBase,
ariane_soc::DRAMBase
}),
.end_addr_i ({
ariane_soc::DebugBase + ariane_soc::DebugLength - 1,
ariane_soc::ROMBase + ariane_soc::ROMLength - 1,
ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1,
ariane_soc::PLICBase + ariane_soc::PLICLength - 1,
ariane_soc::UARTBase + ariane_soc::UARTLength - 1,
ariane_soc::TimerBase + ariane_soc::TimerLength - 1,
ariane_soc::SPIBase + ariane_soc::SPILength - 1,
ariane_soc::EthernetBase + ariane_soc::EthernetLength -1,
ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1,
ariane_soc::DMABase + ariane_soc::DMALength - 1,
ariane_soc::AESBase + ariane_soc::AESLength - 1,
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
}),
.valid_rule_i (ariane_soc::ValidRule)
);
//----------------
// AES : mash
//----------------
AXI_LITE #(
.AXI_ADDR_WIDTH (32),
.AXI_DATA_WIDTH (32)
) aes_lite();
axi_to_axi_lite_mod axi_to_axi_lite_aes (
.clk_i (clk_i),
.rst_ni (ndmreset_n),
.testmode_i (test_en),
.in (master[ariane_soc::AES]),
.out (aes_lite)
);
AES_PIPE_v1_0_S00_AXI aes (
.S_AXI_ACLK (clk_i ),
.S_AXI_ARESETN (ndmreset_n ),
.S_AXI_AWADDR (aes_lite.aw_addr ),
.S_AXI_AWPROT ( ),
.S_AXI_AWVALID (aes_lite.aw_valid ),
.S_AXI_AWREADY (aes_lite.aw_ready ),
.S_AXI_WDATA (aes_lite.w_data ),
.S_AXI_WSTRB (aes_lite.w_strb ),
.S_AXI_WVALID (aes_lite.w_valid ),
.S_AXI_WREADY (aes_lite.w_ready ),
.S_AXI_BRESP (aes_lite.b_resp ),
.S_AXI_BVALID (aes_lite.b_valid ),
.S_AXI_BREADY (aes_lite.b_ready ),
.S_AXI_ARADDR (aes_lite.ar_addr ),
.S_AXI_ARPROT ( ),
.S_AXI_ARVALID (aes_lite.ar_valid ),
.S_AXI_ARREADY (aes_lite.ar_ready ),
.S_AXI_RDATA (aes_lite.r_data ),
.S_AXI_RRESP (aes_lite.r_resp ),
.S_AXI_RVALID (aes_lite.r_valid ),
.S_AXI_RREADY (aes_lite.r_ready )
);
//----------------
// DMA : mash
//----------------
logic dma_penable;
logic dma_pwrite;
logic [31:0] dma_paddr;
logic dma_psel;
logic [31:0] dma_pwdata;
logic [31:0] dma_prdata;
logic dma_pready;
logic dma_pslverr;
axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI4_RDATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI4_WDATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI4_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI4_USER_WIDTH ( AXI_USER_WIDTH ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32_dma (
.ACLK ( clk_i ),
.ARESETn ( ndmreset_n ),
.test_en_i ( 1'b0 ),
.AWID_i ( master[ariane_soc::DMA].aw_id ),
.AWADDR_i ( master[ariane_soc::DMA].aw_addr ),
.AWLEN_i ( master[ariane_soc::DMA].aw_len ),
.AWSIZE_i ( master[ariane_soc::DMA].aw_size ),
.AWBURST_i ( master[ariane_soc::DMA].aw_burst ),
.AWLOCK_i ( master[ariane_soc::DMA].aw_lock ),
.AWCACHE_i ( master[ariane_soc::DMA].aw_cache ),
.AWPROT_i ( master[ariane_soc::DMA].aw_prot ),
.AWREGION_i( master[ariane_soc::DMA].aw_region ),
.AWUSER_i ( master[ariane_soc::DMA].aw_user ),
.AWQOS_i ( master[ariane_soc::DMA].aw_qos ),
.AWVALID_i ( master[ariane_soc::DMA].aw_valid ),
.AWREADY_o ( master[ariane_soc::DMA].aw_ready ),
.WDATA_i ( master[ariane_soc::DMA].w_data ),
.WSTRB_i ( master[ariane_soc::DMA].w_strb ),
.WLAST_i ( master[ariane_soc::DMA].w_last ),
.WUSER_i ( master[ariane_soc::DMA].w_user ),
.WVALID_i ( master[ariane_soc::DMA].w_valid ),
.WREADY_o ( master[ariane_soc::DMA].w_ready ),
.BID_o ( master[ariane_soc::DMA].b_id ),
.BRESP_o ( master[ariane_soc::DMA].b_resp ),
.BVALID_o ( master[ariane_soc::DMA].b_valid ),
.BUSER_o ( master[ariane_soc::DMA].b_user ),
.BREADY_i ( master[ariane_soc::DMA].b_ready ),
.ARID_i ( master[ariane_soc::DMA].ar_id ),
.ARADDR_i ( master[ariane_soc::DMA].ar_addr ),
.ARLEN_i ( master[ariane_soc::DMA].ar_len ),
.ARSIZE_i ( master[ariane_soc::DMA].ar_size ),
.ARBURST_i ( master[ariane_soc::DMA].ar_burst ),
.ARLOCK_i ( master[ariane_soc::DMA].ar_lock ),
.ARCACHE_i ( master[ariane_soc::DMA].ar_cache ),
.ARPROT_i ( master[ariane_soc::DMA].ar_prot ),
.ARREGION_i( master[ariane_soc::DMA].ar_region ),
.ARUSER_i ( master[ariane_soc::DMA].ar_user ),
.ARQOS_i ( master[ariane_soc::DMA].ar_qos ),
.ARVALID_i ( master[ariane_soc::DMA].ar_valid ),
.ARREADY_o ( master[ariane_soc::DMA].ar_ready ),
.RID_o ( master[ariane_soc::DMA].r_id ),
.RDATA_o ( master[ariane_soc::DMA].r_data ),
.RRESP_o ( master[ariane_soc::DMA].r_resp ),
.RLAST_o ( master[ariane_soc::DMA].r_last ),
.RUSER_o ( master[ariane_soc::DMA].r_user ),
.RVALID_o ( master[ariane_soc::DMA].r_valid ),
.RREADY_i ( master[ariane_soc::DMA].r_ready ),
.PENABLE ( dma_penable ),
.PWRITE ( dma_pwrite ),
.PADDR ( dma_paddr ),
.PSEL ( dma_psel ),
.PWDATA ( dma_pwdata ),
.PRDATA ( dma_prdata ),
.PREADY ( dma_pready ),
.PSLVERR ( dma_pslverr )
);
dma_axi64 dma (
.clk ( clk_i ),
.reset ( ~ndmreset_n ),
.scan_en ( 1'b0 ),
.idle ( ),
.INT ( ),
.periph_tx_req ( ),
.periph_tx_clr ( ),
.periph_rx_req ( ),
.periph_rx_clr ( ),
.pclken ( 1'b1 ),
.psel ( dma_psel ),
.penable ( ~dma_penable ),
.paddr ( dma_paddr ),
.pwrite ( dma_pwrite ),
.pwdata ( dma_pwdata ),
.prdata ( dma_prdata ),
.pslverr ( dma_pslverr ),
.pready ( dma_pready ),
.AWID0 ( slave[2].aw_id ),
.AWADDR0 ( slave[2].aw_addr ),
.AWLEN0 ( slave[2].aw_len ),
.AWSIZE0 ( slave[2].aw_size ),
.AWVALID0 ( slave[2].aw_valid ),
.AWREADY0 ( slave[2].aw_ready ),
.WID0 ( ),
.WDATA0 ( slave[2].w_data ),
.WSTRB0 ( slave[2].w_strb ),
.WLAST0 ( slave[2].w_last ),
.WVALID0 ( slave[2].w_valid ),
.WREADY0 ( slave[2].w_ready ),
.BID0 ( slave[2].b_id ),
.BRESP0 ( slave[2].b_resp ),
.BVALID0 ( slave[2].b_valid ),
.BREADY0 ( slave[2].b_ready ),
.ARID0 ( slave[2].ar_id ),
.ARADDR0 ( slave[2].ar_addr ),
.ARLEN0 ( slave[2].ar_len ),
.ARSIZE0 ( slave[2].ar_size ),
.ARVALID0 ( slave[2].ar_valid ),
.ARREADY0 ( slave[2].ar_ready ),
.RID0 ( slave[2].r_id ),
.RDATA0 ( slave[2].r_data ),
.RRESP0 ( slave[2].r_resp ),
.RLAST0 ( slave[2].r_last ),
.RVALID0 ( slave[2].r_valid ),
.RREADY0 ( slave[2].r_ready )
);
//----------------
// eFPGA : mash
//----------------
wrapper_efpga efpga (
.clk (clk_i)
);
// ---------------
// CLINT
// ---------------
logic ipi;
logic timer_irq;
ariane_axi_soc::req_t axi_clint_req;
ariane_axi_soc::resp_t axi_clint_resp;
clint #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.NR_CORES ( 1 )
) i_clint (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.testmode_i ( test_en ),
.axi_req_i ( axi_clint_req ),
.axi_resp_o ( axi_clint_resp ),
.rtc_i ( rtc_i ),
.timer_irq_o ( timer_irq ),
.ipi_o ( ipi )
);
axi_slave_connect i_axi_slave_connect_clint (
.axi_req_o(axi_clint_req),
.axi_resp_i(axi_clint_resp),
.slave(master[ariane_soc::CLINT])
);
// ---------------
// Peripherals
// ---------------
logic tx, rx;
logic [1:0] irqs;
ariane_peripherals #(
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.AxiIdWidth ( ariane_soc::IdWidthSlave ),
`ifndef VERILATOR
// disable UART when using Spike, as we need to rely on the mockuart
`ifdef SPIKE_TANDEM
.InclUART ( 1'b0 ),
`else
.InclUART ( 1'b1 ),
`endif
`else
.InclUART ( 1'b0 ),
`endif
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
) i_ariane_peripherals (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.ethernet ( master[ariane_soc::Ethernet] ),
.timer ( master[ariane_soc::Timer] ),
.irq_o ( irqs ),
.rx_i ( rx ),
.tx_o ( tx ),
.eth_txck ( ),
.eth_rxck ( ),
.eth_rxctl ( ),
.eth_rxd ( ),
.eth_rst_n ( ),
.eth_tx_en ( ),
.eth_txd ( ),
.phy_mdio ( ),
.eth_mdc ( ),
.mdio ( ),
.mdc ( ),
.spi_clk_o ( ),
.spi_mosi ( ),
.spi_miso ( ),
.spi_ss ( )
);
uart_bus #(.BAUD_RATE(115200), .PARITY_EN(0)) i_uart_bus (.rx(tx), .tx(rx), .rx_en(1'b1));
// ---------------
// Core
// ---------------
ariane_axi_soc::req_t axi_ariane_req;
ariane_axi_soc::resp_t axi_ariane_resp;
ariane_rvfi_pkg::rvfi_port_t rvfi;
ariane #(
.ArianeCfg ( ariane_soc::ArianeSocCfg )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM
.hart_id_i ( {56'h0, hart_id} ),
.irq_i ( irqs ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
`ifdef RVFI_TRACE
.rvfi_o ( rvfi ),
`endif
// Disable Debug when simulating with Spike
`ifdef SPIKE_TANDEM
.debug_req_i ( 1'b0 ),
`else
.debug_req_i ( debug_req_core ),
`endif
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
);
axi_master_connect i_axi_master_connect_ariane (
.axi_req_i(axi_ariane_req),
.axi_resp_o(axi_ariane_resp),
.master(slave[0])
);
// -------------
// Simulation Helper Functions
// -------------
// check for response errors
always_ff @(posedge clk_i) begin : p_assert
if (axi_ariane_req.r_ready &&
axi_ariane_resp.r_valid &&
axi_ariane_resp.r.resp inside {axi_pkg::RESP_DECERR, axi_pkg::RESP_SLVERR}) begin
$warning("R Response Errored");
end
if (axi_ariane_req.b_ready &&
axi_ariane_resp.b_valid &&
axi_ariane_resp.b.resp inside {axi_pkg::RESP_DECERR, axi_pkg::RESP_SLVERR}) begin
$warning("B Response Errored");
end
end
rvfi_tracer #(
.HART_ID(hart_id),
.DEBUG_START(0),
.DEBUG_STOP(0)
) rvfi_tracer_i (
.clk_i(clk_i),
.rst_ni(rst_ni),
.rvfi_i(rvfi)
);
`ifdef AXI_SVA
// AXI 4 Assertion IP integration - You will need to get your own copy of this IP if you want
// to use it
Axi4PC #(
.DATA_WIDTH(ariane_axi_soc::DataWidth),
.WID_WIDTH(ariane_soc::IdWidthSlave),
.RID_WIDTH(ariane_soc::IdWidthSlave),
.AWUSER_WIDTH(ariane_axi_soc::UserWidth),
.WUSER_WIDTH(ariane_axi_soc::UserWidth),
.BUSER_WIDTH(ariane_axi_soc::UserWidth),
.ARUSER_WIDTH(ariane_axi_soc::UserWidth),
.RUSER_WIDTH(ariane_axi_soc::UserWidth),
.ADDR_WIDTH(ariane_axi_soc::AddrWidth)
) i_Axi4PC (
.ACLK(clk_i),
.ARESETn(ndmreset_n),
.AWID(dram.aw_id),
.AWADDR(dram.aw_addr),
.AWLEN(dram.aw_len),
.AWSIZE(dram.aw_size),
.AWBURST(dram.aw_burst),
.AWLOCK(dram.aw_lock),
.AWCACHE(dram.aw_cache),
.AWPROT(dram.aw_prot),
.AWQOS(dram.aw_qos),
.AWREGION(dram.aw_region),
.AWUSER(dram.aw_user),
.AWVALID(dram.aw_valid),
.AWREADY(dram.aw_ready),
.WLAST(dram.w_last),
.WDATA(dram.w_data),
.WSTRB(dram.w_strb),
.WUSER(dram.w_user),
.WVALID(dram.w_valid),
.WREADY(dram.w_ready),
.BID(dram.b_id),
.BRESP(dram.b_resp),
.BUSER(dram.b_user),
.BVALID(dram.b_valid),
.BREADY(dram.b_ready),
.ARID(dram.ar_id),
.ARADDR(dram.ar_addr),
.ARLEN(dram.ar_len),
.ARSIZE(dram.ar_size),
.ARBURST(dram.ar_burst),
.ARLOCK(dram.ar_lock),
.ARCACHE(dram.ar_cache),
.ARPROT(dram.ar_prot),
.ARQOS(dram.ar_qos),
.ARREGION(dram.ar_region),
.ARUSER(dram.ar_user),
.ARVALID(dram.ar_valid),
.ARREADY(dram.ar_ready),
.RID(dram.r_id),
.RLAST(dram.r_last),
.RDATA(dram.r_data),
.RRESP(dram.r_resp),
.RUSER(dram.r_user),
.RVALID(dram.r_valid),
.RREADY(dram.r_ready),
.CACTIVE('0),
.CSYSREQ('0),
.CSYSACK('0)
);
`endif
endmodule
|
// Copyright 2020 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
package rvfi_pkg;
localparam NRET = 1;
localparam ILEN = 32;
typedef struct packed {
logic [NRET-1:0] valid;
logic [NRET*63:0] order;
logic [NRET*ILEN-1:0] insn;
logic [NRET-1:0] trap;
logic [NRET-1:0] halt;
logic [NRET-1:0] intr;
logic [NRET*2-1:0] mode;
logic [NRET*2-1:0] ixl;
logic [NRET*5-1:0] rs1_addr;
logic [NRET*5-1:0] rs2_addr;
logic [NRET*riscv::XLEN-1:0] rs1_rdata;
logic [NRET*riscv::XLEN-1:0] rs2_rdata;
logic [NRET*5-1:0] rd_addr;
logic [NRET*riscv::XLEN-1:0] rd_wdata;
logic [NRET*riscv::XLEN-1:0] pc_rdata;
logic [NRET*riscv::XLEN-1:0] pc_wdata;
logic [NRET*riscv::XLEN-1:0] mem_addr;
logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask;
logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask;
logic [NRET*riscv::XLEN-1:0] mem_rdata;
logic [NRET*riscv::XLEN-1:0] mem_wdata;
} rvfi_instr_t;
endpackage
|
// Copyright 2020 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON (jean-roch.coulon@invia.fr)
module rvfi_tracer #(
parameter logic [7:0] HART_ID = '0,
parameter int unsigned DEBUG_START = 0,
parameter int unsigned NR_COMMIT_PORTS = 2,
parameter int unsigned DEBUG_STOP = 0
)(
input logic clk_i,
input logic rst_ni,
input rvfi_pkg::rvfi_instr_t[NR_COMMIT_PORTS-1:0] rvfi_i
);
int f;
int unsigned SIM_FINISH;
initial begin
f = $fopen($sformatf("trace_rvfi_hart_%h.dasm", HART_ID), "w");
if (!$value$plusargs("time_out=%d", SIM_FINISH)) SIM_FINISH = 2000000;
end
final $fclose(f);
logic [31:0] cycles;
// Generate the trace based on RVFI
logic [63:0] pc64;
always_ff @(posedge clk_i) begin
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
pc64 = {{riscv::XLEN-riscv::VLEN{rvfi_i[i].pc_rdata[riscv::VLEN-1]}}, rvfi_i[i].pc_rdata};
// print the instruction information if the instruction is valid or a trap is taken
if (rvfi_i[i].valid) begin
// Instruction information
$fwrite(f, "core 0: 0x%h (0x%h) DASM(%h)\n",
pc64, rvfi_i[i].insn, rvfi_i[i].insn);
// Destination register information
$fwrite(f, "%h 0x%h (0x%h)",
rvfi_i[i].mode, pc64, rvfi_i[i].insn);
// Decode instruction to know if destination register is FP register
if ( rvfi_i[i].insn[6:0] == 7'b1001111 ||
rvfi_i[i].insn[6:0] == 7'b1001011 ||
rvfi_i[i].insn[6:0] == 7'b1000111 ||
rvfi_i[i].insn[6:0] == 7'b1000011 ||
rvfi_i[i].insn[6:0] == 7'b0000111 ||
(rvfi_i[i].insn[6:0] == 7'b1010011 && rvfi_i[i].insn[31:26] != 6'b111000
&& rvfi_i[i].insn[31:26] != 6'b101000
&& rvfi_i[i].insn[31:26] != 6'b110000) )
$fwrite(f, " f%d 0x%h\n",
rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
else if (rvfi_i[i].rd_addr != 0) begin
$fwrite(f, " x%d 0x%h\n",
rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
end else $fwrite(f, "\n");
//if (rvfi_i[i].insn == 32'h00000073) begin
// $finish(1);
// $finish(1);
//end
end else if (rvfi_i[i].trap)
$fwrite(f, "exception : 0x%h\n", pc64);
end
if (cycles > SIM_FINISH) $finish(1);
end
always_ff @(posedge clk_i or negedge rst_ni)
if (~rst_ni)
cycles <= 0;
else
cycles <= cycles+1;
// Trace any custom signals
// Define signals to be traced by adding them into debug and name arrays
string name[0:10];
logic[63:0] debug[0:10], debug_previous[0:10];
always_ff @(posedge clk_i) begin
if (cycles > DEBUG_START && cycles < DEBUG_STOP)
for (int index = 0; index < 100; index++)
if (debug_previous[index] != debug[index])
$fwrite(f, "%d %s %x\n", cycles, name[index], debug[index]);
debug_previous <= debug;
end
endmodule // rvfi_tracer
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Author:
// Andreas Kurth <akurth@iis.ee.ethz.ch>
// Macros to assign AXI Interfaces and Structs
`ifndef AXI_ASSIGN_SVH_
`define AXI_ASSIGN_SVH_
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning one AXI4+ATOP interface to another, as if you would do `assign slv = mst;`
//
// The channel assignments `AXI_ASSIGN_XX(dst, src)` assign all payload and the valid signal of the
// `XX` channel from the `src` to the `dst` interface and they assign the ready signal from the
// `src` to the `dst` interface.
// The interface assignment `AXI_ASSIGN(dst, src)` assigns all channels including handshakes as if
// `src` was the master of `dst`.
//
// Usage Example:
// `AXI_ASSIGN(slv, mst)
// `AXI_ASSIGN_AW(dst, src)
// `AXI_ASSIGN_R(dst, src)
`define AXI_ASSIGN_AW(dst, src) \
assign dst.aw_id = src.aw_id; \
assign dst.aw_addr = src.aw_addr; \
assign dst.aw_len = src.aw_len; \
assign dst.aw_size = src.aw_size; \
assign dst.aw_burst = src.aw_burst; \
assign dst.aw_lock = src.aw_lock; \
assign dst.aw_cache = src.aw_cache; \
assign dst.aw_prot = src.aw_prot; \
assign dst.aw_qos = src.aw_qos; \
assign dst.aw_region = src.aw_region; \
assign dst.aw_atop = src.aw_atop; \
assign dst.aw_user = src.aw_user; \
assign dst.aw_valid = src.aw_valid; \
assign src.aw_ready = dst.aw_ready;
`define AXI_ASSIGN_W(dst, src) \
assign dst.w_data = src.w_data; \
assign dst.w_strb = src.w_strb; \
assign dst.w_last = src.w_last; \
assign dst.w_user = src.w_user; \
assign dst.w_valid = src.w_valid; \
assign src.w_ready = dst.w_ready;
`define AXI_ASSIGN_B(dst, src) \
assign dst.b_id = src.b_id; \
assign dst.b_resp = src.b_resp; \
assign dst.b_user = src.b_user; \
assign dst.b_valid = src.b_valid; \
assign src.b_ready = dst.b_ready;
`define AXI_ASSIGN_AR(dst, src) \
assign dst.ar_id = src.ar_id; \
assign dst.ar_addr = src.ar_addr; \
assign dst.ar_len = src.ar_len; \
assign dst.ar_size = src.ar_size; \
assign dst.ar_burst = src.ar_burst; \
assign dst.ar_lock = src.ar_lock; \
assign dst.ar_cache = src.ar_cache; \
assign dst.ar_prot = src.ar_prot; \
assign dst.ar_qos = src.ar_qos; \
assign dst.ar_region = src.ar_region; \
assign dst.ar_user = src.ar_user; \
assign dst.ar_valid = src.ar_valid; \
assign src.ar_ready = dst.ar_ready;
`define AXI_ASSIGN_R(dst, src) \
assign dst.r_id = src.r_id; \
assign dst.r_data = src.r_data; \
assign dst.r_resp = src.r_resp; \
assign dst.r_last = src.r_last; \
assign dst.r_user = src.r_user; \
assign dst.r_valid = src.r_valid; \
assign src.r_ready = dst.r_ready;
`define AXI_ASSIGN(slv, mst) \
`AXI_ASSIGN_AW(slv, mst) \
`AXI_ASSIGN_W(slv, mst) \
`AXI_ASSIGN_B(mst, slv) \
`AXI_ASSIGN_AR(slv, mst) \
`AXI_ASSIGN_R(mst, slv)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning a AXI4+ATOP interface to a monitor modport, as if you would do `assign mon = axi_if;`
//
// The channel assignment `AXI_ASSIGN_MONITOR(mon_dv, axi_if)` assigns all signals from `axi_if`
// to the `mon_dv` interface.
//
// Usage Example:
// `AXI_ASSIGN_MONITOR(mon_dv, axi_if)
`define AXI_ASSIGN_MONITOR(mon_dv, axi_if) \
assign mon_dv.aw_id = axi_if.aw_id; \
assign mon_dv.aw_addr = axi_if.aw_addr; \
assign mon_dv.aw_len = axi_if.aw_len; \
assign mon_dv.aw_size = axi_if.aw_size; \
assign mon_dv.aw_burst = axi_if.aw_burst; \
assign mon_dv.aw_lock = axi_if.aw_lock; \
assign mon_dv.aw_cache = axi_if.aw_cache; \
assign mon_dv.aw_prot = axi_if.aw_prot; \
assign mon_dv.aw_qos = axi_if.aw_qos; \
assign mon_dv.aw_region = axi_if.aw_region; \
assign mon_dv.aw_atop = axi_if.aw_atop; \
assign mon_dv.aw_user = axi_if.aw_user; \
assign mon_dv.aw_valid = axi_if.aw_valid; \
assign mon_dv.aw_ready = axi_if.aw_ready; \
assign mon_dv.w_data = axi_if.w_data; \
assign mon_dv.w_strb = axi_if.w_strb; \
assign mon_dv.w_last = axi_if.w_last; \
assign mon_dv.w_user = axi_if.w_user; \
assign mon_dv.w_valid = axi_if.w_valid; \
assign mon_dv.w_ready = axi_if.w_ready; \
assign mon_dv.b_id = axi_if.b_id; \
assign mon_dv.b_resp = axi_if.b_resp; \
assign mon_dv.b_user = axi_if.b_user; \
assign mon_dv.b_valid = axi_if.b_valid; \
assign mon_dv.b_ready = axi_if.b_ready; \
assign mon_dv.ar_id = axi_if.ar_id; \
assign mon_dv.ar_addr = axi_if.ar_addr; \
assign mon_dv.ar_len = axi_if.ar_len; \
assign mon_dv.ar_size = axi_if.ar_size; \
assign mon_dv.ar_burst = axi_if.ar_burst; \
assign mon_dv.ar_lock = axi_if.ar_lock; \
assign mon_dv.ar_cache = axi_if.ar_cache; \
assign mon_dv.ar_prot = axi_if.ar_prot; \
assign mon_dv.ar_qos = axi_if.ar_qos; \
assign mon_dv.ar_region = axi_if.ar_region; \
assign mon_dv.ar_user = axi_if.ar_user; \
assign mon_dv.ar_valid = axi_if.ar_valid; \
assign mon_dv.ar_ready = axi_if.ar_ready; \
assign mon_dv.r_id = axi_if.r_id; \
assign mon_dv.r_data = axi_if.r_data; \
assign mon_dv.r_resp = axi_if.r_resp; \
assign mon_dv.r_last = axi_if.r_last; \
assign mon_dv.r_user = axi_if.r_user; \
assign mon_dv.r_valid = axi_if.r_valid; \
assign mon_dv.r_ready = axi_if.r_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal implementation for assigning interfaces from structs, allows for standalone assignments
// (with `opt_as = assign`) and assignments inside processes (with `opt_as` void) with the same
// code.
`define AXI_FROM_AW(opt_as, axi_if, aw_struct) \
opt_as axi_if.aw_id = aw_struct.id; \
opt_as axi_if.aw_addr = aw_struct.addr; \
opt_as axi_if.aw_len = aw_struct.len; \
opt_as axi_if.aw_size = aw_struct.size; \
opt_as axi_if.aw_burst = aw_struct.burst; \
opt_as axi_if.aw_lock = aw_struct.lock; \
opt_as axi_if.aw_cache = aw_struct.cache; \
opt_as axi_if.aw_prot = aw_struct.prot; \
opt_as axi_if.aw_qos = aw_struct.qos; \
opt_as axi_if.aw_region = aw_struct.region; \
opt_as axi_if.aw_atop = aw_struct.atop; \
opt_as axi_if.aw_user = aw_struct.user;
`define AXI_FROM_W(opt_as, axi_if, w_struct) \
opt_as axi_if.w_data = w_struct.data; \
opt_as axi_if.w_strb = w_struct.strb; \
opt_as axi_if.w_last = w_struct.last; \
opt_as axi_if.w_user = w_struct.user;
`define AXI_FROM_B(opt_as, axi_if, b_struct) \
opt_as axi_if.b_id = b_struct.id; \
opt_as axi_if.b_resp = b_struct.resp; \
opt_as axi_if.b_user = b_struct.user;
`define AXI_FROM_AR(opt_as, axi_if, ar_struct) \
opt_as axi_if.ar_id = ar_struct.id; \
opt_as axi_if.ar_addr = ar_struct.addr; \
opt_as axi_if.ar_len = ar_struct.len; \
opt_as axi_if.ar_size = ar_struct.size; \
opt_as axi_if.ar_burst = ar_struct.burst; \
opt_as axi_if.ar_lock = ar_struct.lock; \
opt_as axi_if.ar_cache = ar_struct.cache; \
opt_as axi_if.ar_prot = ar_struct.prot; \
opt_as axi_if.ar_qos = ar_struct.qos; \
opt_as axi_if.ar_region = ar_struct.region; \
opt_as axi_if.ar_user = ar_struct.user;
`define AXI_FROM_R(opt_as, axi_if, r_struct) \
opt_as axi_if.r_id = r_struct.id; \
opt_as axi_if.r_data = r_struct.data; \
opt_as axi_if.r_resp = r_struct.resp; \
opt_as axi_if.r_last = r_struct.last; \
opt_as axi_if.r_user = r_struct.user;
`define AXI_FROM_REQ(opt_as, axi_if, req_struct) \
`AXI_FROM_AW(opt_as, axi_if, req_struct.aw) \
opt_as axi_if.aw_valid = req_struct.aw_valid; \
`AXI_FROM_W(opt_as, axi_if, req_struct.w) \
opt_as axi_if.w_valid = req_struct.w_valid; \
opt_as axi_if.b_ready = req_struct.b_ready; \
`AXI_FROM_AR(opt_as, axi_if, req_struct.ar) \
opt_as axi_if.ar_valid = req_struct.ar_valid; \
opt_as axi_if.r_ready = req_struct.r_ready;
`define AXI_FROM_RESP(opt_as, axi_if, resp_struct) \
opt_as axi_if.aw_ready = resp_struct.aw_ready; \
opt_as axi_if.ar_ready = resp_struct.ar_ready; \
opt_as axi_if.w_ready = resp_struct.w_ready; \
opt_as axi_if.b_valid = resp_struct.b_valid; \
`AXI_FROM_B(opt_as, axi_if, resp_struct.b) \
opt_as axi_if.r_valid = resp_struct.r_valid; \
`AXI_FROM_R(opt_as, axi_if, resp_struct.r)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting an interface from channel or request/response structs inside a process.
//
// The channel macros `AXI_SET_FROM_XX(axi_if, xx_struct)` set the payload signals of the `axi_if`
// interface from the signals in `xx_struct`. They do not set the handshake signals.
// The request macro `AXI_SET_FROM_REQ(axi_if, req_struct)` sets all request channels (AW, W, AR)
// and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the `axi_if`
// interface from the signals in `req_struct`.
// The response macro `AXI_SET_FROM_RESP(axi_if, resp_struct)` sets both response channels (B and R)
// and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the `axi_if`
// interface from the signals in `resp_struct`.
//
// Usage Example:
// always_comb begin
// `AXI_SET_FROM_REQ(my_if, my_req_struct)
// end
`define AXI_SET_FROM_AW(axi_if, aw_struct) `AXI_FROM_AW(, axi_if, aw_struct)
`define AXI_SET_FROM_W(axi_if, w_struct) `AXI_FROM_W(, axi_if, w_struct)
`define AXI_SET_FROM_B(axi_if, b_struct) `AXI_FROM_B(, axi_if, b_struct)
`define AXI_SET_FROM_AR(axi_if, ar_struct) `AXI_FROM_AR(, axi_if, ar_struct)
`define AXI_SET_FROM_R(axi_if, r_struct) `AXI_FROM_R(, axi_if, r_struct)
`define AXI_SET_FROM_REQ(axi_if, req_struct) `AXI_FROM_REQ(, axi_if, req_struct)
`define AXI_SET_FROM_RESP(axi_if, resp_struct) `AXI_FROM_RESP(, axi_if, resp_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning an interface from channel or request/response structs outside a process.
//
// The channel macros `AXI_ASSIGN_FROM_XX(axi_if, xx_struct)` assign the payload signals of the
// `axi_if` interface from the signals in `xx_struct`. They do not assign the handshake signals.
// The request macro `AXI_ASSIGN_FROM_REQ(axi_if, req_struct)` assigns all request channels (AW, W,
// AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the
// `axi_if` interface from the signals in `req_struct`.
// The response macro `AXI_ASSIGN_FROM_RESP(axi_if, resp_struct)` assigns both response channels (B
// and R) and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the
// `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// `AXI_ASSIGN_FROM_REQ(my_if, my_req_struct)
`define AXI_ASSIGN_FROM_AW(axi_if, aw_struct) `AXI_FROM_AW(assign, axi_if, aw_struct)
`define AXI_ASSIGN_FROM_W(axi_if, w_struct) `AXI_FROM_W(assign, axi_if, w_struct)
`define AXI_ASSIGN_FROM_B(axi_if, b_struct) `AXI_FROM_B(assign, axi_if, b_struct)
`define AXI_ASSIGN_FROM_AR(axi_if, ar_struct) `AXI_FROM_AR(assign, axi_if, ar_struct)
`define AXI_ASSIGN_FROM_R(axi_if, r_struct) `AXI_FROM_R(assign, axi_if, r_struct)
`define AXI_ASSIGN_FROM_REQ(axi_if, req_struct) `AXI_FROM_REQ(assign, axi_if, req_struct)
`define AXI_ASSIGN_FROM_RESP(axi_if, resp_struct) `AXI_FROM_RESP(assign, axi_if, resp_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal implementation for assigning to structs from interfaces, allows for standalone
// assignments (with `opt_as = assign`) and assignments inside processes (with `opt_as` void) with
// the same code.
`define AXI_TO_AW(opt_as, aw_struct, axi_if) \
opt_as aw_struct = '{ \
id: axi_if.aw_id, \
addr: axi_if.aw_addr, \
len: axi_if.aw_len, \
size: axi_if.aw_size, \
burst: axi_if.aw_burst, \
lock: axi_if.aw_lock, \
cache: axi_if.aw_cache, \
prot: axi_if.aw_prot, \
qos: axi_if.aw_qos, \
region: axi_if.aw_region, \
atop: axi_if.aw_atop, \
user: axi_if.aw_user \
};
`define AXI_TO_W(opt_as, w_struct, axi_if) \
opt_as w_struct = '{ \
data: axi_if.w_data, \
strb: axi_if.w_strb, \
last: axi_if.w_last, \
user: axi_if.w_user \
};
`define AXI_TO_B(opt_as, b_struct, axi_if) \
opt_as b_struct = '{ \
id: axi_if.b_id, \
resp: axi_if.b_resp, \
user: axi_if.b_user \
};
`define AXI_TO_AR(opt_as, ar_struct, axi_if) \
opt_as ar_struct = '{ \
id: axi_if.ar_id, \
addr: axi_if.ar_addr, \
len: axi_if.ar_len, \
size: axi_if.ar_size, \
burst: axi_if.ar_burst, \
lock: axi_if.ar_lock, \
cache: axi_if.ar_cache, \
prot: axi_if.ar_prot, \
qos: axi_if.ar_qos, \
region: axi_if.ar_region, \
user: axi_if.ar_user \
};
`define AXI_TO_R(opt_as, r_struct, axi_if) \
opt_as r_struct = '{ \
id: axi_if.r_id, \
data: axi_if.r_data, \
resp: axi_if.r_resp, \
last: axi_if.r_last, \
user: axi_if.r_user \
};
`define AXI_TO_REQ(opt_as, req_struct, axi_if) \
`AXI_TO_AW(opt_as, req_struct.aw, axi_if) \
opt_as req_struct.aw_valid = axi_if.aw_valid; \
`AXI_TO_W(opt_as, req_struct.w, axi_if) \
opt_as req_struct.w_valid = axi_if.w_valid; \
opt_as req_struct.b_ready = axi_if.b_ready; \
`AXI_TO_AR(opt_as, req_struct.ar, axi_if) \
opt_as req_struct.ar_valid = axi_if.ar_valid; \
opt_as req_struct.r_ready = axi_if.r_ready;
`define AXI_TO_RESP(opt_as, resp_struct, axi_if) \
opt_as resp_struct.aw_ready = axi_if.aw_ready; \
opt_as resp_struct.ar_ready = axi_if.ar_ready; \
opt_as resp_struct.w_ready = axi_if.w_ready; \
opt_as resp_struct.b_valid = axi_if.b_valid; \
`AXI_TO_B(opt_as, resp_struct.b, axi_if) \
opt_as resp_struct.r_valid = axi_if.r_valid; \
`AXI_TO_R(opt_as, resp_struct.r, axi_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting channel or request/response structs from an interface inside a process.
//
// The channel macros `AXI_SET_TO_XX(xx_struct, axi_if)` set the signals of `xx_struct` to the
// payload signals of that channel in the `axi_if` interface. They do not set the handshake
// signals.
// The request macro `AXI_SET_TO_REQ(axi_if, req_struct)` sets all signals of `req_struct` (i.e.,
// request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR valid and
// B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_SET_TO_RESP(axi_if, resp_struct)` sets all signals of `resp_struct`
// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// always_comb begin
// `AXI_SET_TO_REQ(my_req_struct, my_if)
// end
`define AXI_SET_TO_AW(aw_struct, axi_if) `AXI_TO_AW(, aw_struct, axi_if)
`define AXI_SET_TO_W(w_struct, axi_if) `AXI_TO_W(, w_struct, axi_if)
`define AXI_SET_TO_B(b_struct, axi_if) `AXI_TO_B(, b_struct, axi_if)
`define AXI_SET_TO_AR(ar_struct, axi_if) `AXI_TO_AR(, ar_struct, axi_if)
`define AXI_SET_TO_R(r_struct, axi_if) `AXI_TO_R(, r_struct, axi_if)
`define AXI_SET_TO_REQ(req_struct, axi_if) `AXI_TO_REQ(, req_struct, axi_if)
`define AXI_SET_TO_RESP(resp_struct, axi_if) `AXI_TO_RESP(, resp_struct, axi_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning channel or request/response structs from an interface outside a process.
//
// The channel macros `AXI_ASSIGN_TO_XX(xx_struct, axi_if)` assign the signals of `xx_struct` to the
// payload signals of that channel in the `axi_if` interface. They do not assign the handshake
// signals.
// The request macro `AXI_ASSIGN_TO_REQ(axi_if, req_struct)` assigns all signals of `req_struct`
// (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR
// valid and B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_ASSIGN_TO_RESP(axi_if, resp_struct)` assigns all signals of `resp_struct`
// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// `AXI_ASSIGN_TO_REQ(my_req_struct, my_if)
`define AXI_ASSIGN_TO_AW(aw_struct, axi_if) `AXI_TO_AW(assign, aw_struct, axi_if)
`define AXI_ASSIGN_TO_W(w_struct, axi_if) `AXI_TO_W(assign, w_struct, axi_if)
`define AXI_ASSIGN_TO_B(b_struct, axi_if) `AXI_TO_B(assign, b_struct, axi_if)
`define AXI_ASSIGN_TO_AR(ar_struct, axi_if) `AXI_TO_AR(assign, ar_struct, axi_if)
`define AXI_ASSIGN_TO_R(r_struct, axi_if) `AXI_TO_R(assign, r_struct, axi_if)
`define AXI_ASSIGN_TO_REQ(req_struct, axi_if) `AXI_TO_REQ(assign, req_struct, axi_if)
`define AXI_ASSIGN_TO_RESP(resp_struct, axi_if) `AXI_TO_RESP(assign, resp_struct, axi_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning one AXI-Lite interface to another, as if you would do `assign slv = mst;`
//
// The channel assignments `AXI_LITE_ASSIGN_XX(dst, src)` assign all payload and the valid signal of
// the `XX` channel from the `src` to the `dst` interface and they assign the ready signal from the
// `src` to the `dst` interface.
// The interface assignment `AXI_LITE_ASSIGN(dst, src)` assigns all channels including handshakes as
// if `src` was the master of `dst`.
//
// Usage Example:
// `AXI_LITE_ASSIGN(slv, mst)
// `AXI_LITE_ASSIGN_AW(dst, src)
// `AXI_LITE_ASSIGN_R(dst, src)
`define AXI_LITE_ASSIGN_AW(dst, src) \
assign dst.aw_addr = src.aw_addr; \
assign dst.aw_prot = src.aw_prot; \
assign dst.aw_valid = src.aw_valid; \
assign src.aw_ready = dst.aw_ready;
`define AXI_LITE_ASSIGN_W(dst, src) \
assign dst.w_data = src.w_data; \
assign dst.w_strb = src.w_strb; \
assign dst.w_valid = src.w_valid; \
assign src.w_ready = dst.w_ready;
`define AXI_LITE_ASSIGN_B(dst, src) \
assign dst.b_resp = src.b_resp; \
assign dst.b_valid = src.b_valid; \
assign src.b_ready = dst.b_ready;
`define AXI_LITE_ASSIGN_AR(dst, src) \
assign dst.ar_addr = src.ar_addr; \
assign dst.ar_prot = src.ar_prot; \
assign dst.ar_valid = src.ar_valid; \
assign src.ar_ready = dst.ar_ready;
`define AXI_LITE_ASSIGN_R(dst, src) \
assign dst.r_data = src.r_data; \
assign dst.r_resp = src.r_resp; \
assign dst.r_valid = src.r_valid; \
assign src.r_ready = dst.r_ready;
`define AXI_LITE_ASSIGN(slv, mst) \
`AXI_LITE_ASSIGN_AW(slv, mst) \
`AXI_LITE_ASSIGN_W(slv, mst) \
`AXI_LITE_ASSIGN_B(mst, slv) \
`AXI_LITE_ASSIGN_AR(slv, mst) \
`AXI_LITE_ASSIGN_R(mst, slv)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal implementation for assigning Lite interfaces from structs, allows for standalone
// assignments (with `opt_as = assign`) and assignments inside processes (with `opt_as` void) with
// the same code.
`define AXI_LITE_FROM_AW(opt_as, axi_lite_if, aw_lite_struct) \
opt_as axi_lite_if.aw_addr = aw_lite_struct.addr; \
opt_as axi_lite_if.aw_prot = aw_lite_struct.prot;
`define AXI_LITE_FROM_W(opt_as, axi_lite_if, w_lite_struct) \
opt_as axi_lite_if.w_data = w_lite_struct.data; \
opt_as axi_lite_if.w_strb = w_lite_struct.strb;
`define AXI_LITE_FROM_B(opt_as, axi_lite_if, b_lite_struct) \
opt_as axi_lite_if.b_resp = b_lite_struct.resp;
`define AXI_LITE_FROM_AR(opt_as, axi_lite_if, ar_lite_struct) \
opt_as axi_lite_if.ar_addr = ar_lite_struct.addr; \
opt_as axi_lite_if.ar_prot = ar_lite_struct.prot;
`define AXI_LITE_FROM_R(opt_as, axi_lite_if, r_lite_struct) \
opt_as axi_lite_if.r_data = r_lite_struct.data; \
opt_as axi_lite_if.r_resp = r_lite_struct.resp;
`define AXI_LITE_FROM_REQ(opt_as, axi_lite_if, req_lite_struct) \
`AXI_LITE_FROM_AW(opt_as, axi_lite_if, req_lite_struct.aw) \
opt_as axi_lite_if.aw_valid = req_lite_struct.aw_valid; \
`AXI_LITE_FROM_W(opt_as, axi_lite_if, req_lite_struct.w) \
opt_as axi_lite_if.w_valid = req_lite_struct.w_valid; \
opt_as axi_lite_if.b_ready = req_lite_struct.b_ready; \
`AXI_LITE_FROM_AR(opt_as, axi_lite_if, req_lite_struct.ar) \
opt_as axi_lite_if.ar_valid = req_lite_struct.ar_valid; \
opt_as axi_lite_if.r_ready = req_lite_struct.r_ready;
`define AXI_LITE_FROM_RESP(opt_as, axi_lite_if, resp_lite_struct) \
opt_as axi_lite_if.aw_ready = resp_lite_struct.aw_ready; \
opt_as axi_lite_if.ar_ready = resp_lite_struct.ar_ready; \
opt_as axi_lite_if.w_ready = resp_lite_struct.w_ready; \
opt_as axi_lite_if.b_valid = resp_lite_struct.b_valid; \
`AXI_LITE_FROM_B(opt_as, axi_lite_if, resp_lite_struct.b) \
opt_as axi_lite_if.r_valid = resp_lite_struct.r_valid; \
`AXI_LITE_FROM_R(opt_as, axi_lite_if, resp_lite_struct.r)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting a Lite interface from channel or request/response structs inside a process.
//
// The channel macros `AXI_LITE_SET_FROM_XX(axi_if, xx_struct)` set the payload signals of the
// `axi_if` interface from the signals in `xx_struct`. They do not set the handshake signals.
// The request macro `AXI_LITE_SET_FROM_REQ(axi_if, req_struct)` sets all request channels (AW, W,
// AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the
// `axi_if` interface from the signals in `req_struct`.
// The response macro `AXI_LITE_SET_FROM_RESP(axi_if, resp_struct)` sets both response channels (B
// and R) and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the
// `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_FROM_REQ(my_if, my_req_struct)
// end
`define AXI_LITE_SET_FROM_AW(axi_if, aw_struct) `AXI_LITE_FROM_AW(, axi_if, aw_struct)
`define AXI_LITE_SET_FROM_W(axi_if, w_struct) `AXI_LITE_FROM_W(, axi_if, w_struct)
`define AXI_LITE_SET_FROM_B(axi_if, b_struct) `AXI_LITE_FROM_B(, axi_if, b_struct)
`define AXI_LITE_SET_FROM_AR(axi_if, ar_struct) `AXI_LITE_FROM_AR(, axi_if, ar_struct)
`define AXI_LITE_SET_FROM_R(axi_if, r_struct) `AXI_LITE_FROM_R(, axi_if, r_struct)
`define AXI_LITE_SET_FROM_REQ(axi_if, req_struct) `AXI_LITE_FROM_REQ(, axi_if, req_struct)
`define AXI_LITE_SET_FROM_RESP(axi_if, resp_struct) `AXI_LITE_FROM_RESP(, axi_if, resp_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning a Lite interface from channel or request/response structs outside a process.
//
// The channel macros `AXI_LITE_ASSIGN_FROM_XX(axi_if, xx_struct)` assign the payload signals of the
// `axi_if` interface from the signals in `xx_struct`. They do not assign the handshake signals.
// The request macro `AXI_LITE_ASSIGN_FROM_REQ(axi_if, req_struct)` assigns all request channels
// (AW, W, AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the
// `axi_if` interface from the signals in `req_struct`.
// The response macro `AXI_LITE_ASSIGN_FROM_RESP(axi_if, resp_struct)` assigns both response
// channels (B and R) and the response-side handshake signals (B and R valid and AW, W, and AR
// ready) of the `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// `AXI_LITE_ASSIGN_FROM_REQ(my_if, my_req_struct)
`define AXI_LITE_ASSIGN_FROM_AW(axi_if, aw_struct) `AXI_LITE_FROM_AW(assign, axi_if, aw_struct)
`define AXI_LITE_ASSIGN_FROM_W(axi_if, w_struct) `AXI_LITE_FROM_W(assign, axi_if, w_struct)
`define AXI_LITE_ASSIGN_FROM_B(axi_if, b_struct) `AXI_LITE_FROM_B(assign, axi_if, b_struct)
`define AXI_LITE_ASSIGN_FROM_AR(axi_if, ar_struct) `AXI_LITE_FROM_AR(assign, axi_if, ar_struct)
`define AXI_LITE_ASSIGN_FROM_R(axi_if, r_struct) `AXI_LITE_FROM_R(assign, axi_if, r_struct)
`define AXI_LITE_ASSIGN_FROM_REQ(axi_if, req_struct) `AXI_LITE_FROM_REQ(assign, axi_if, req_struct)
`define AXI_LITE_ASSIGN_FROM_RESP(axi_if, resp_struct) `AXI_LITE_FROM_RESP(assign, axi_if, resp_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal implementation for assigning to Lite structs from interfaces, allows for standalone
// assignments (with `opt_as = assign`) and assignments inside processes (with `opt_as` void) with
// the same code.
`define AXI_LITE_TO_AW(opt_as, aw_lite_struct, axi_lite_if) \
opt_as aw_lite_struct = '{ \
addr: axi_lite_if.aw_addr, \
prot: axi_lite_if.aw_prot \
};
// prot not in interface!
`define AXI_LITE_TO_W(opt_as, w_lite_struct, axi_lite_if) \
opt_as w_lite_struct = '{ \
data: axi_lite_if.w_data, \
strb: axi_lite_if.w_strb \
};
`define AXI_LITE_TO_B(opt_as, b_lite_struct, axi_lite_if) \
opt_as b_lite_struct = '{ \
resp: axi_lite_if.b_resp \
};
`define AXI_LITE_TO_AR(opt_as, ar_lite_struct, axi_lite_if) \
opt_as ar_lite_struct = '{ \
addr: axi_lite_if.ar_addr, \
prot: axi_lite_if.ar_prot \
};
`define AXI_LITE_TO_R(opt_as, r_lite_struct, axi_lite_if) \
opt_as r_lite_struct = '{ \
data: axi_lite_if.r_data, \
resp: axi_lite_if.r_resp \
};
`define AXI_LITE_TO_REQ(opt_as, req_lite_struct, axi_lite_if) \
`AXI_LITE_TO_AW(opt_as, req_lite_struct.aw, axi_lite_if) \
opt_as req_lite_struct.aw_valid = axi_lite_if.aw_valid; \
`AXI_LITE_TO_W(opt_as, req_lite_struct.w, axi_lite_if) \
opt_as req_lite_struct.w_valid = axi_lite_if.w_valid; \
opt_as req_lite_struct.b_ready = axi_lite_if.b_ready; \
`AXI_LITE_TO_AR(opt_as, req_lite_struct.ar, axi_lite_if) \
opt_as req_lite_struct.ar_valid = axi_lite_if.ar_valid; \
opt_as req_lite_struct.r_ready = axi_lite_if.r_ready;
`define AXI_LITE_TO_RESP(opt_as, resp_lite_struct, axi_lite_if) \
opt_as resp_lite_struct.aw_ready = axi_lite_if.aw_ready; \
opt_as resp_lite_struct.ar_ready = axi_lite_if.ar_ready; \
opt_as resp_lite_struct.w_ready = axi_lite_if.w_ready; \
opt_as resp_lite_struct.b_valid = axi_lite_if.b_valid; \
`AXI_LITE_TO_B(opt_as, resp_lite_struct.b, axi_lite_if) \
opt_as resp_lite_struct.r_valid = axi_lite_if.r_valid; \
`AXI_LITE_TO_R(opt_as, resp_lite_struct.r, axi_lite_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting channel or request/response structs from an interface inside a process.
//
// The channel macros `AXI_LITE_SET_TO_XX(xx_struct, axi_if)` set the signals of `xx_struct` to the
// payload signals of that channel in the `axi_if` interface. They do not set the handshake
// signals.
// The request macro `AXI_LITE_SET_TO_REQ(axi_if, req_struct)` sets all signals of `req_struct`
// (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR
// valid and B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_LITE_SET_TO_RESP(axi_if, resp_struct)` sets all signals of `resp_struct`
// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_TO_REQ(my_req_struct, my_if)
// end
`define AXI_LITE_SET_TO_AW(aw_struct, axi_if) `AXI_LITE_TO_AW(, aw_struct, axi_if)
`define AXI_LITE_SET_TO_W(w_struct, axi_if) `AXI_LITE_TO_W(, w_struct, axi_if)
`define AXI_LITE_SET_TO_B(b_struct, axi_if) `AXI_LITE_TO_B(, b_struct, axi_if)
`define AXI_LITE_SET_TO_AR(ar_struct, axi_if) `AXI_LITE_TO_AR(, ar_struct, axi_if)
`define AXI_LITE_SET_TO_R(r_struct, axi_if) `AXI_LITE_TO_R(, r_struct, axi_if)
`define AXI_LITE_SET_TO_REQ(req_struct, axi_if) `AXI_LITE_TO_REQ(, req_struct, axi_if)
`define AXI_LITE_SET_TO_RESP(resp_struct, axi_if) `AXI_LITE_TO_RESP(, resp_struct, axi_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning channel or request/response structs from an interface outside a process.
//
// The channel macros `AXI_LITE_ASSIGN_TO_XX(xx_struct, axi_if)` assign the signals of `xx_struct`
// to the payload signals of that channel in the `axi_if` interface. They do not assign the
// handshake signals.
// The request macro `AXI_LITE_ASSIGN_TO_REQ(axi_if, req_struct)` assigns all signals of
// `req_struct` (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW,
// W, and AR valid and B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_LITE_ASSIGN_TO_RESP(axi_if, resp_struct)` assigns all signals of
// `resp_struct` (i.e., response channel (B and R) payload and response-side handshake signals (B
// and R valid and AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// `AXI_LITE_ASSIGN_TO_REQ(my_req_struct, my_if)
`define AXI_LITE_ASSIGN_TO_AW(aw_struct, axi_if) `AXI_LITE_TO_AW(assign, aw_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_W(w_struct, axi_if) `AXI_LITE_TO_W(assign, w_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_B(b_struct, axi_if) `AXI_LITE_TO_B(assign, b_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_AR(ar_struct, axi_if) `AXI_LITE_TO_AR(assign, ar_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_R(r_struct, axi_if) `AXI_LITE_TO_R(assign, r_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_REQ(req_struct, axi_if) `AXI_LITE_TO_REQ(assign, req_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_RESP(resp_struct, axi_if) `AXI_LITE_TO_RESP(assign, resp_struct, axi_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
`endif
|
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Date: 23.05.2017
// Description: Load Store Unit, handles address calculation and memory interface signals
module core_mem #(
parameter logic [63:0] DRAM_BASE = 64'h80000000
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// Data memory/cache
input logic [63:0] data_if_address_i,
input logic data_if_data_req_i,
input logic [7:0] data_if_data_be_i,
output logic data_if_data_rvalid_o,
output logic [63:0] data_if_data_rdata_o,
input logic [63:0] data_if_data_wdata_i,
input logic data_if_data_we_i
);
// we always grant the access
localparam ADDRESS_WIDTH = 24;
logic [63:0] fetch_data_ram, fetch_data_rom;
logic [63:0] data_address_q;
logic [63:0] data_ram, data_rom;
// look at the address of the previous cycle to determine what to return
assign data_if_data_rdata_o = (data_address_q >= DRAM_BASE) ? data_ram : data_rom;
dp_ram #(
.ADDR_WIDTH ( ADDRESS_WIDTH ),
.DATA_WIDTH ( 64 )
) ram_i (
.clk ( clk_i ),
.en_a_i ( 1'b0 ),
.addr_a_i ( ),
.wdata_a_i ( ), // not connected
.rdata_a_o ( ),
.we_a_i ( 1'b0 ), // r/o interface
.be_a_i ( ),
// data RAM
.en_b_i ( data_if_data_req_i ),
.addr_b_i ( data_if_address_i[ADDRESS_WIDTH-1+3:3] ),
.wdata_b_i ( data_if_data_wdata_i ),
.rdata_b_o ( data_ram ),
.we_b_i ( ((data_if_address_i >= DRAM_BASE) ? data_if_data_we_i : 1'b0) ),
.be_b_i ( data_if_data_be_i )
);
boot_rom data_boot_rom_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.address_i ( data_address_q ),
.data_o ( data_rom )
);
// Output the rvalid one cycle later, together with the rdata
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_
if (~rst_ni) begin
data_if_data_rvalid_o <= 1'b0;
data_address_q <= '0;
end else begin
data_if_data_rvalid_o <= data_if_data_req_i;
data_address_q <= data_if_address_i;
end
end
endmodule
|
// Copyright 2015-2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module dp_ram
#(
parameter int ADDR_WIDTH = 8,
parameter int DATA_WIDTH = 64
)(
// Clock and Reset
input logic clk,
input logic en_a_i,
input logic [ADDR_WIDTH-1:0] addr_a_i,
input logic [DATA_WIDTH-1:0] wdata_a_i,
output logic [DATA_WIDTH-1:0] rdata_a_o,
input logic we_a_i,
input logic [DATA_WIDTH/8-1:0] be_a_i,
input logic en_b_i,
input logic [ADDR_WIDTH-1:0] addr_b_i,
input logic [DATA_WIDTH-1:0] wdata_b_i,
output logic [DATA_WIDTH-1:0] rdata_b_o,
input logic we_b_i,
input logic [DATA_WIDTH/8-1:0] be_b_i
);
localparam words = 2**ADDR_WIDTH;
logic [DATA_WIDTH/8-1:0][7:0] mem [words-1:0];
always @(posedge clk) begin
if (en_a_i && we_a_i) begin
for (int i = 0; i < DATA_WIDTH/8; i++) begin
if (be_a_i[i])
mem[addr_a_i][i] <= wdata_a_i[i*8 +: 8];
end
end
rdata_a_o <= mem[addr_a_i];
if (en_b_i && we_b_i) begin
for (int i = 0; i < DATA_WIDTH/8; i++) begin
if (be_b_i[i])
mem[addr_b_i][i] <= wdata_b_i[i*8 +: 8];
end
end
rdata_b_o <= mem[addr_b_i];
end
endmodule
|
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